xref: /illumos-gate/usr/src/uts/common/sys/usb/hcd/ehci/ehcid.h (revision 6aef9e11)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
53b00f311Syq  * Common Development and Distribution License (the "License").
63b00f311Syq  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22dfbb3a42SRaymond Chen  * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
237c478bd9Sstevel@tonic-gate  */
247c478bd9Sstevel@tonic-gate 
257c478bd9Sstevel@tonic-gate #ifndef _SYS_USB_EHCID_H
267c478bd9Sstevel@tonic-gate #define	_SYS_USB_EHCID_H
277c478bd9Sstevel@tonic-gate 
287c478bd9Sstevel@tonic-gate 
297c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
307c478bd9Sstevel@tonic-gate extern "C" {
317c478bd9Sstevel@tonic-gate #endif
327c478bd9Sstevel@tonic-gate 
337c478bd9Sstevel@tonic-gate /*
347c478bd9Sstevel@tonic-gate  * Enchanced Host Controller Driver (EHCI)
357c478bd9Sstevel@tonic-gate  *
367c478bd9Sstevel@tonic-gate  * The EHCI driver is a software driver which interfaces to the Universal
377c478bd9Sstevel@tonic-gate  * Serial Bus layer (USBA) and the Host Controller (HC). The interface to
387c478bd9Sstevel@tonic-gate  * the Host Controller is defined by the EHCI Host Controller Interface.
397c478bd9Sstevel@tonic-gate  *
407c478bd9Sstevel@tonic-gate  * This header file describes the data structures and function prototypes
417c478bd9Sstevel@tonic-gate  * required for the EHCI Driver to maintain state of Host Controller (HC),
427c478bd9Sstevel@tonic-gate  * to perform different USB transfers and for the bandwidth allocations.
437c478bd9Sstevel@tonic-gate  */
447c478bd9Sstevel@tonic-gate 
457c478bd9Sstevel@tonic-gate #include <sys/usb/hcd/ehci/ehci.h>
467c478bd9Sstevel@tonic-gate #include <sys/usb/hcd/ehci/ehci_hub.h>
477c478bd9Sstevel@tonic-gate 
487c478bd9Sstevel@tonic-gate 
497c478bd9Sstevel@tonic-gate /*
507c478bd9Sstevel@tonic-gate  * EHCI Bandwidth Maintainence Structure.
517c478bd9Sstevel@tonic-gate  *
527c478bd9Sstevel@tonic-gate  * The ehci_bandwidth array keeps track of allocated bandwidth for ehci
537c478bd9Sstevel@tonic-gate  * host controller. There are 32 bandwidth lists corresponding to 32 ms
547c478bd9Sstevel@tonic-gate  * periodic frame lists.  Each bandwidth list inturn will contain eight
557c478bd9Sstevel@tonic-gate  * micro frame bandwidth lists.
567c478bd9Sstevel@tonic-gate  */
577c478bd9Sstevel@tonic-gate #define	EHCI_MAX_UFRAMES	8	/* Max uframes 125us per frame */
587c478bd9Sstevel@tonic-gate 
597c478bd9Sstevel@tonic-gate typedef struct ehci_frame_bandwidth {
607c478bd9Sstevel@tonic-gate 	uint_t			ehci_allocated_frame_bandwidth;
617c478bd9Sstevel@tonic-gate 	uint_t			ehci_micro_frame_bandwidth[EHCI_MAX_UFRAMES];
627c478bd9Sstevel@tonic-gate } ehci_frame_bandwidth_t;
637c478bd9Sstevel@tonic-gate 
647c478bd9Sstevel@tonic-gate 
657c478bd9Sstevel@tonic-gate /*
667c478bd9Sstevel@tonic-gate  * EHCI Host Controller state structure
677c478bd9Sstevel@tonic-gate  *
687c478bd9Sstevel@tonic-gate  * The Host Controller Driver (HCD) maintains the state of Host Controller
697c478bd9Sstevel@tonic-gate  * (HC). There is an ehci_state structure per instance	of the EHCI
707c478bd9Sstevel@tonic-gate  * host controller.
717c478bd9Sstevel@tonic-gate  */
727c478bd9Sstevel@tonic-gate typedef struct ehci_state {
737c478bd9Sstevel@tonic-gate 	dev_info_t		*ehci_dip;		/* Dip of HC */
747c478bd9Sstevel@tonic-gate 	uint_t			ehci_instance;
757c478bd9Sstevel@tonic-gate 	usba_hcdi_ops_t		*ehci_hcdi_ops;		/* HCDI structure */
767c478bd9Sstevel@tonic-gate 	uint_t			ehci_flags;		/* Used for cleanup */
777c478bd9Sstevel@tonic-gate 	uint16_t		ehci_vendor_id;		/* chip vendor */
787c478bd9Sstevel@tonic-gate 	uint16_t		ehci_device_id;		/* chip device */
797c478bd9Sstevel@tonic-gate 	uint8_t			ehci_rev_id;		/* chip revison */
807c478bd9Sstevel@tonic-gate 
817c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	ehci_caps_handle;	/* Caps Reg Handle */
827c478bd9Sstevel@tonic-gate 	ehci_caps_t		*ehci_capsp;		/* Capability Regs */
837c478bd9Sstevel@tonic-gate 	ehci_regs_t		*ehci_regsp;		/* Operational Regs */
847c478bd9Sstevel@tonic-gate 
857c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	ehci_config_handle;	/* Config space hndle */
867c478bd9Sstevel@tonic-gate 	uint_t			ehci_frame_interval;	/* Frme inter reg */
877c478bd9Sstevel@tonic-gate 	ddi_dma_attr_t		ehci_dma_attr;		/* DMA attributes */
887c478bd9Sstevel@tonic-gate 
897c478bd9Sstevel@tonic-gate 	ddi_intr_handle_t	*ehci_htable;		/* intr handle */
909c75c6bfSgovinda 	int			ehci_intr_type;		/* intr type used */
919c75c6bfSgovinda 	int			ehci_intr_cnt;		/* # of intrs inuse */
927c478bd9Sstevel@tonic-gate 	uint_t			ehci_intr_pri;		/* intr priority */
939c75c6bfSgovinda 	int			ehci_intr_cap;		/* intr capabilities */
949c75c6bfSgovinda 	boolean_t		ehci_msi_enabled;	/* default to true */
957c478bd9Sstevel@tonic-gate 	kmutex_t		ehci_int_mutex;		/* Global EHCI mutex */
967c478bd9Sstevel@tonic-gate 
977c478bd9Sstevel@tonic-gate 	/* Periodic Frame List area */
987c478bd9Sstevel@tonic-gate 	ehci_periodic_frame_list_t	*ehci_periodic_frame_list_tablep;
997c478bd9Sstevel@tonic-gate 				/* Virtual Periodic Frame List ptr */
1007c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t	ehci_pflt_cookie;	/* DMA cookie */
1017c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t	ehci_pflt_dma_handle;	/* DMA handle */
1027c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	ehci_pflt_mem_handle;	/* Memory handle */
1037c478bd9Sstevel@tonic-gate 
1047c478bd9Sstevel@tonic-gate 	/*
1057c478bd9Sstevel@tonic-gate 	 * There are two pools of memory. One pool contains the memory for
1067c478bd9Sstevel@tonic-gate 	 * the transfer descriptors and other pool contains the memory for
1077c478bd9Sstevel@tonic-gate 	 * the endpoint descriptors. The advantage of the pools is that it's
1087c478bd9Sstevel@tonic-gate 	 * easy to go back and forth between the iommu and the cpu addresses.
1097c478bd9Sstevel@tonic-gate 	 *
1107c478bd9Sstevel@tonic-gate 	 * The pools are protected by the ehci_int_mutex because the memory
1117c478bd9Sstevel@tonic-gate 	 * in the pools may be accessed by either the host controller or the
1127c478bd9Sstevel@tonic-gate 	 * host controller driver.
1137c478bd9Sstevel@tonic-gate 	 */
1147c478bd9Sstevel@tonic-gate 
1157c478bd9Sstevel@tonic-gate 	/* Endpoint descriptor pool */
1167c478bd9Sstevel@tonic-gate 	ehci_qh_t		*ehci_qh_pool_addr;	/* Start of the pool */
1177c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t	ehci_qh_pool_cookie;	/* DMA cookie */
1187c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t	ehci_qh_pool_dma_handle;	/* DMA handle */
1197c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	ehci_qh_pool_mem_handle;	/* Mem handle */
1207c478bd9Sstevel@tonic-gate 	uint_t			ehci_dma_addr_bind_flag;	/* DMA flag */
1217c478bd9Sstevel@tonic-gate 
1227c478bd9Sstevel@tonic-gate 	/* General transfer descriptor pool */
1237c478bd9Sstevel@tonic-gate 	ehci_qtd_t		*ehci_qtd_pool_addr;	/* Start of the pool */
1247c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t	ehci_qtd_pool_cookie;	/* DMA cookie */
1257c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t	ehci_qtd_pool_dma_handle;	/* DMA hndle */
1267c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	ehci_qtd_pool_mem_handle;	/* Mem hndle */
1277c478bd9Sstevel@tonic-gate 
1287c478bd9Sstevel@tonic-gate 	/* Isochronous transfer descriptor pool */
1297c478bd9Sstevel@tonic-gate 	ehci_itd_t		*ehci_itd_pool_addr;	/* Start of the pool */
1307c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t	ehci_itd_pool_cookie;	/* DMA cookie */
1317c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t	ehci_itd_pool_dma_handle;	/* DMA hndle */
1327c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	ehci_itd_pool_mem_handle;	/* Mem hndle */
1337c478bd9Sstevel@tonic-gate 
1347c478bd9Sstevel@tonic-gate 	/* Condition variable for advance on Asynchronous Schedule */
1357c478bd9Sstevel@tonic-gate 	kcondvar_t		ehci_async_schedule_advance_cv;
1367c478bd9Sstevel@tonic-gate 
1377c478bd9Sstevel@tonic-gate 	/* Head of Asynchronous Schedule List */
1387c478bd9Sstevel@tonic-gate 	ehci_qh_t		*ehci_head_of_async_sched_list;
1397c478bd9Sstevel@tonic-gate 
1407c478bd9Sstevel@tonic-gate 	/*
1417c478bd9Sstevel@tonic-gate 	 * List of QTD inserted either into Asynchronous or Periodic
1427c478bd9Sstevel@tonic-gate 	 * Schedule lists.
1437c478bd9Sstevel@tonic-gate 	 */
1447c478bd9Sstevel@tonic-gate 	ehci_qtd_t		*ehci_active_qtd_list;
1457c478bd9Sstevel@tonic-gate 	/*
1467c478bd9Sstevel@tonic-gate 	 * List of ITD active itd list.
1477c478bd9Sstevel@tonic-gate 	 */
1487c478bd9Sstevel@tonic-gate 	ehci_itd_t		*ehci_active_itd_list;
1497c478bd9Sstevel@tonic-gate 
1507c478bd9Sstevel@tonic-gate 	/*
1517c478bd9Sstevel@tonic-gate 	 * Bandwidth fields
1527c478bd9Sstevel@tonic-gate 	 *
1537c478bd9Sstevel@tonic-gate 	 * The ehci_bandwidth array keeps track of allocated bandwidth for
1547c478bd9Sstevel@tonic-gate 	 * ehci host controller. There are 32 bandwidth lists corresponding
1557c478bd9Sstevel@tonic-gate 	 * to 32 ms periodic frame lists. Each bandwidth list in turn will
1567c478bd9Sstevel@tonic-gate 	 * contain eight micro frame bandwidth lists.
1577c478bd9Sstevel@tonic-gate 	 *
1587c478bd9Sstevel@tonic-gate 	 * ehci_min_frame_bandwidth field indicates least allocated milli
1597c478bd9Sstevel@tonic-gate 	 * second bandwidth list.
1607c478bd9Sstevel@tonic-gate 	 */
1617c478bd9Sstevel@tonic-gate 	ehci_frame_bandwidth_t	ehci_frame_bandwidth[EHCI_NUM_INTR_QH_LISTS];
1627c478bd9Sstevel@tonic-gate 
1637c478bd9Sstevel@tonic-gate 	/* No. of open pipes, async qh, and periodic qh */
1647c478bd9Sstevel@tonic-gate 	uint_t			ehci_open_pipe_count;
1657c478bd9Sstevel@tonic-gate 	uint_t			ehci_open_async_count;
1667c478bd9Sstevel@tonic-gate 	uint_t			ehci_open_periodic_count;
1677c478bd9Sstevel@tonic-gate 
168dfbb3a42SRaymond Chen 	/* No. of async and periodic requests */
169dfbb3a42SRaymond Chen 	uint_t			ehci_async_req_count;
170dfbb3a42SRaymond Chen 	uint_t			ehci_periodic_req_count;
171dfbb3a42SRaymond Chen 
1727c478bd9Sstevel@tonic-gate 	/*
1737c478bd9Sstevel@tonic-gate 	 * Endpoint Reclamation List
1747c478bd9Sstevel@tonic-gate 	 *
1757c478bd9Sstevel@tonic-gate 	 * The interrupt list processing cannot be stopped when a periodic
1767c478bd9Sstevel@tonic-gate 	 * endpoint is removed from the list.  The endpoints are detached
1777c478bd9Sstevel@tonic-gate 	 * from the interrupt lattice tree and put on to the reclaimation
1787c478bd9Sstevel@tonic-gate 	 * list. On next SOF interrupt all those endpoints,  which are on
1797c478bd9Sstevel@tonic-gate 	 * the reclaimation list will be deallocated.
1807c478bd9Sstevel@tonic-gate 	 */
1817c478bd9Sstevel@tonic-gate 	ehci_qh_t		*ehci_reclaim_list;	/* Reclaimation list */
1827c478bd9Sstevel@tonic-gate 
1837c478bd9Sstevel@tonic-gate 	ehci_root_hub_t		ehci_root_hub;		/* Root hub info */
1847c478bd9Sstevel@tonic-gate 
1857c478bd9Sstevel@tonic-gate 	/* Frame number overflow information */
1867c478bd9Sstevel@tonic-gate 	usb_frame_number_t	ehci_fno;
1877c478bd9Sstevel@tonic-gate 
1887c478bd9Sstevel@tonic-gate 	/* For host controller error counter */
1897c478bd9Sstevel@tonic-gate 	uint_t			ehci_hc_error;
1907c478bd9Sstevel@tonic-gate 
1917c478bd9Sstevel@tonic-gate 	/*
1927c478bd9Sstevel@tonic-gate 	 * ehci_missed_intr_sts is used to save the normal mode interrupt
1937c478bd9Sstevel@tonic-gate 	 * status information  if an interrupt is pending for normal mode
1947c478bd9Sstevel@tonic-gate 	 * when polled code is entered.
1957c478bd9Sstevel@tonic-gate 	 */
1967c478bd9Sstevel@tonic-gate 	uint_t			ehci_missed_intr_sts;
1977c478bd9Sstevel@tonic-gate 
1987c478bd9Sstevel@tonic-gate 	/*
1997c478bd9Sstevel@tonic-gate 	 * Saved copy of the ehci registers of the normal mode & change
2007c478bd9Sstevel@tonic-gate 	 * required ehci registers values for the polled mode operation.
2017c478bd9Sstevel@tonic-gate 	 * Before returning from the polled mode to normal mode replace
2027c478bd9Sstevel@tonic-gate 	 * the required current registers with this saved ehci registers
2037c478bd9Sstevel@tonic-gate 	 * copy.
2047c478bd9Sstevel@tonic-gate 	 */
2057c478bd9Sstevel@tonic-gate 	ehci_regs_t	ehci_polled_save_regs;
2067c478bd9Sstevel@tonic-gate 
2077c478bd9Sstevel@tonic-gate 	/*
2087c478bd9Sstevel@tonic-gate 	 * Saved copy of the interrupt table used in normal ehci mode and
2097c478bd9Sstevel@tonic-gate 	 * replace this table by another interrupt table that used in the
2107c478bd9Sstevel@tonic-gate 	 * POLLED mode.
2117c478bd9Sstevel@tonic-gate 	 */
2127c478bd9Sstevel@tonic-gate 	ehci_qh_t *ehci_polled_frame_list_table[EHCI_NUM_PERIODIC_FRAME_LISTS];
2137c478bd9Sstevel@tonic-gate 
2147c478bd9Sstevel@tonic-gate 	/* ehci polled mode enter counter */
2157c478bd9Sstevel@tonic-gate 	uint_t			ehci_polled_enter_count;
2167c478bd9Sstevel@tonic-gate 
2177c478bd9Sstevel@tonic-gate 	/*
2187c478bd9Sstevel@tonic-gate 	 * counter for polled mode and used in suspend mode to see if
2197c478bd9Sstevel@tonic-gate 	 * there is a keyboard connected.
2207c478bd9Sstevel@tonic-gate 	 */
2217c478bd9Sstevel@tonic-gate 	uint_t			ehci_polled_kbd_count;
2227c478bd9Sstevel@tonic-gate 
2237c478bd9Sstevel@tonic-gate 	/* counter for polled read and use it to clean the interrupt status */
2247c478bd9Sstevel@tonic-gate 	uint_t			ehci_polled_read_count;
2257c478bd9Sstevel@tonic-gate 
2263b00f311Syq #if defined(__x86)
2273b00f311Syq 	/* counter for polled root hub status */
2283b00f311Syq 	uint_t			ehci_polled_root_hub_count;
2293b00f311Syq #endif	/* __x86 */
2303b00f311Syq 
2317c478bd9Sstevel@tonic-gate 	/* EHCI Host Controller Software State information */
2327c478bd9Sstevel@tonic-gate 	uint_t			ehci_hc_soft_state;
2337c478bd9Sstevel@tonic-gate 
2347c478bd9Sstevel@tonic-gate 	/* Log handle for debug, console, log messages */
2357c478bd9Sstevel@tonic-gate 	usb_log_handle_t	ehci_log_hdl;
2367c478bd9Sstevel@tonic-gate 
2377c478bd9Sstevel@tonic-gate 	/* Kstat structures */
2387c478bd9Sstevel@tonic-gate 	kstat_t			*ehci_intrs_stats;
2397c478bd9Sstevel@tonic-gate 	kstat_t			*ehci_total_stats;
2407c478bd9Sstevel@tonic-gate 	kstat_t			*ehci_count_stats[USB_N_COUNT_KSTATS];
2417c478bd9Sstevel@tonic-gate } ehci_state_t;
2427c478bd9Sstevel@tonic-gate 
2437c478bd9Sstevel@tonic-gate typedef struct ehci_intrs_stats {
2447c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_async_sched_status;
2457c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_periodic_sched_status;
2467c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_empty_async_schedule;
2477c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_host_ctrl_halted;
2487c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_async_advance_intr;
2497c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_host_system_error_intr;
2507c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_frm_list_rollover_intr;
2517c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_rh_port_change_intr;
2527c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_usb_error_intr;
2537c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_usb_intr;
2547c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_not_claimed;
2557c478bd9Sstevel@tonic-gate 	struct kstat_named	ehci_sts_total;
2567c478bd9Sstevel@tonic-gate } ehci_intrs_stats_t;
2577c478bd9Sstevel@tonic-gate 
2587c478bd9Sstevel@tonic-gate /*
2597c478bd9Sstevel@tonic-gate  * ehci kstat defines
2607c478bd9Sstevel@tonic-gate  */
2617c478bd9Sstevel@tonic-gate #define	EHCI_INTRS_STATS(ehci)	((ehci)->ehci_intrs_stats)
2627c478bd9Sstevel@tonic-gate #define	EHCI_INTRS_STATS_DATA(ehci)	\
2637c478bd9Sstevel@tonic-gate 	((ehci_intrs_stats_t *)EHCI_INTRS_STATS((ehci))->ks_data)
2647c478bd9Sstevel@tonic-gate 
2657c478bd9Sstevel@tonic-gate #define	EHCI_TOTAL_STATS(ehci)	((ehci)->ehci_total_stats)
2667c478bd9Sstevel@tonic-gate #define	EHCI_TOTAL_STATS_DATA(ehci)	(KSTAT_IO_PTR((ehci)->ehci_total_stats))
2677c478bd9Sstevel@tonic-gate #define	EHCI_CTRL_STATS(ehci)	\
2687c478bd9Sstevel@tonic-gate 	(KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_CONTROL]))
2697c478bd9Sstevel@tonic-gate #define	EHCI_BULK_STATS(ehci)	\
2707c478bd9Sstevel@tonic-gate 	(KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_BULK]))
2717c478bd9Sstevel@tonic-gate #define	EHCI_INTR_STATS(ehci)	\
2727c478bd9Sstevel@tonic-gate 	(KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_INTR]))
2737c478bd9Sstevel@tonic-gate #define	EHCI_ISOC_STATS(ehci)	\
2747c478bd9Sstevel@tonic-gate 	(KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_ISOCH]))
2757c478bd9Sstevel@tonic-gate 
2767c478bd9Sstevel@tonic-gate /* warlock directives, stable data */
2777c478bd9Sstevel@tonic-gate _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_state_t))
2787c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_intr_pri))
2797c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dip))
2807c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_regsp))
2817c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_instance))
2827c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_vendor_id))
2837c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_device_id))
2847c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_rev_id))
2857c478bd9Sstevel@tonic-gate 
2867c478bd9Sstevel@tonic-gate /* this may not be stable data in the future */
2877c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_addr))
2887c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_mem_handle))
2897c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_cookie))
2907c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_addr))
2917c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_mem_handle))
2927c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_cookie))
2937c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_addr))
2947c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_mem_handle))
2957c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_cookie))
2967c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dma_addr_bind_flag))
2977c478bd9Sstevel@tonic-gate _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_log_hdl))
2987c478bd9Sstevel@tonic-gate 
2997c478bd9Sstevel@tonic-gate _NOTE(LOCK_ORDER(ehci_state::ehci_int_mutex \
3007c478bd9Sstevel@tonic-gate 		usba_pipe_handle_data::p_mutex \
3017c478bd9Sstevel@tonic-gate 		usba_device::usb_mutex \
3027c478bd9Sstevel@tonic-gate 		usba_ph_impl::usba_ph_mutex))
3037c478bd9Sstevel@tonic-gate 
3047c478bd9Sstevel@tonic-gate /*
3057c478bd9Sstevel@tonic-gate  * Host Contoller Software States
3067c478bd9Sstevel@tonic-gate  *
3077c478bd9Sstevel@tonic-gate  * EHCI_CTLR_INIT_STATE:
3087c478bd9Sstevel@tonic-gate  *	The host controller soft state will be set to this during the
3097c478bd9Sstevel@tonic-gate  *	ehci_attach.
3107c478bd9Sstevel@tonic-gate  *
3117c478bd9Sstevel@tonic-gate  * EHCI_CTLR_SUSPEND_STATE:
3127c478bd9Sstevel@tonic-gate  *	The host controller soft state will be set to this during the
3137c478bd9Sstevel@tonic-gate  *	ehci_cpr_suspend.
3147c478bd9Sstevel@tonic-gate  *
3157c478bd9Sstevel@tonic-gate  * EHCI_CTLR_OPERATIONAL_STATE:
3167c478bd9Sstevel@tonic-gate  *	The host controller soft state will be set to this after moving
3177c478bd9Sstevel@tonic-gate  *	host controller to operational state and host controller start
3187c478bd9Sstevel@tonic-gate  *	generating SOF successfully.
3197c478bd9Sstevel@tonic-gate  *
3207c478bd9Sstevel@tonic-gate  * EHCI_CTLR_ERROR_STATE:
3217c478bd9Sstevel@tonic-gate  *	The host controller soft state will be set to this during the
3227c478bd9Sstevel@tonic-gate  *	no SOF or UE error conditions.
3237c478bd9Sstevel@tonic-gate  *
3247c478bd9Sstevel@tonic-gate  *	Under this state or condition, only pipe stop polling, pipe reset
3257c478bd9Sstevel@tonic-gate  *	and pipe close are allowed. But all other entry points like  pipe
3267c478bd9Sstevel@tonic-gate  *	open, get/set pipe policy, cotrol send/receive, bulk send/receive
3277c478bd9Sstevel@tonic-gate  *	isoch send/receive, start polling etc. will fail.
3287c478bd9Sstevel@tonic-gate  *
3297c478bd9Sstevel@tonic-gate  * State Diagram for the host controller software state
3307c478bd9Sstevel@tonic-gate  *
3317c478bd9Sstevel@tonic-gate  *
3327c478bd9Sstevel@tonic-gate  * ehci_attach->[INIT_STATE]
3337c478bd9Sstevel@tonic-gate  *	|
3347c478bd9Sstevel@tonic-gate  *	|	-------->----[ERROR_STATE]--<-----------<---
3357c478bd9Sstevel@tonic-gate  *	|      |      Failure (UE/no SOF condition)	    |
3367c478bd9Sstevel@tonic-gate  *	|      ^					    ^
3377c478bd9Sstevel@tonic-gate  *	V      |      Success				    |
3387c478bd9Sstevel@tonic-gate  * ehci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ehci_send/recv/polling
3397c478bd9Sstevel@tonic-gate  *	^					    |
3407c478bd9Sstevel@tonic-gate  *	|					    |
3417c478bd9Sstevel@tonic-gate  *	|					    V
3427c478bd9Sstevel@tonic-gate  *	-<-ehci_cpr_resume--[SUSPEND_STATE]-<-ehci_cpr_suspend
3437c478bd9Sstevel@tonic-gate  */
3447c478bd9Sstevel@tonic-gate #define	EHCI_CTLR_INIT_STATE		0	/* Initilization state */
3457c478bd9Sstevel@tonic-gate #define	EHCI_CTLR_SUSPEND_STATE		1	/* Suspend state */
3467c478bd9Sstevel@tonic-gate #define	EHCI_CTLR_OPERATIONAL_STATE	2	/* Operational state */
3477c478bd9Sstevel@tonic-gate #define	EHCI_CTLR_ERROR_STATE		3	/* Ue error or no sof state */
3487c478bd9Sstevel@tonic-gate 
3493b00f311Syq /*
3503b00f311Syq  * Flags for initializatoin of host controller
3513b00f311Syq  */
3523b00f311Syq #define	EHCI_NORMAL_INITIALIZATION	0	/* Normal initialization */
3533b00f311Syq #define	EHCI_REINITIALIZATION		1	/* Re-initialization */
3543b00f311Syq 
3557c478bd9Sstevel@tonic-gate /*
3567c478bd9Sstevel@tonic-gate  * Periodic and non-periodic macros
3577c478bd9Sstevel@tonic-gate  */
3587c478bd9Sstevel@tonic-gate #define	EHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
3597c478bd9Sstevel@tonic-gate 				USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\
3607c478bd9Sstevel@tonic-gate 				((endpoint->bmAttributes &\
3617c478bd9Sstevel@tonic-gate 				USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH))
3627c478bd9Sstevel@tonic-gate 
3637c478bd9Sstevel@tonic-gate #define	EHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
3647c478bd9Sstevel@tonic-gate 				USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\
3657c478bd9Sstevel@tonic-gate 				((endpoint->bmAttributes &\
3667c478bd9Sstevel@tonic-gate 				USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK))
3677c478bd9Sstevel@tonic-gate 
3687c478bd9Sstevel@tonic-gate #define	EHCI_ISOC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
3697c478bd9Sstevel@tonic-gate 				USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH))
3707c478bd9Sstevel@tonic-gate 
3717c478bd9Sstevel@tonic-gate #define	EHCI_INTR_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
3727c478bd9Sstevel@tonic-gate 				USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR))
3737c478bd9Sstevel@tonic-gate 
3747c478bd9Sstevel@tonic-gate 
3757c478bd9Sstevel@tonic-gate /*
3767c478bd9Sstevel@tonic-gate  * EHCI QH and QTD Pool sizes.
3777c478bd9Sstevel@tonic-gate  */
3787c478bd9Sstevel@tonic-gate #define	EHCI_QH_POOL_SIZE	100
3797c478bd9Sstevel@tonic-gate #define	EHCI_QTD_POOL_SIZE	200
3807c478bd9Sstevel@tonic-gate #define	EHCI_ITD_POOL_SIZE	200
3817c478bd9Sstevel@tonic-gate 
3827c478bd9Sstevel@tonic-gate /*
3837c478bd9Sstevel@tonic-gate  * ehci_dma_addr_bind_flag values
3847c478bd9Sstevel@tonic-gate  *
3857c478bd9Sstevel@tonic-gate  * This flag indicates if the various DMA addresses allocated by the EHCI
3867c478bd9Sstevel@tonic-gate  * have been bound to their respective handles. This is needed to recover
3877c478bd9Sstevel@tonic-gate  * without errors from ehci_cleanup when it calls ddi_dma_unbind_handle()
3887c478bd9Sstevel@tonic-gate  */
3897c478bd9Sstevel@tonic-gate #define	EHCI_QTD_POOL_BOUND	0x01	/* For QTD pools  */
3907c478bd9Sstevel@tonic-gate #define	EHCI_QH_POOL_BOUND	0x02	/* For QH pools  */
3917c478bd9Sstevel@tonic-gate #define	EHCI_PFLT_DMA_BOUND	0x04	/* For Periodic Frame List area */
3927c478bd9Sstevel@tonic-gate #define	EHCI_ITD_POOL_BOUND	0x08	/* For QTD pools  */
3937c478bd9Sstevel@tonic-gate 
3947c478bd9Sstevel@tonic-gate /*
3957c478bd9Sstevel@tonic-gate  * Maximum SOF wait count
3967c478bd9Sstevel@tonic-gate  */
3977c478bd9Sstevel@tonic-gate #define	MAX_SOF_WAIT_COUNT	2	/* Wait for maximum SOF frames */
3987c478bd9Sstevel@tonic-gate 
3997c478bd9Sstevel@tonic-gate /*
4007c478bd9Sstevel@tonic-gate  * One uFrame	125 micro seconds
4017c478bd9Sstevel@tonic-gate  * One Frame	1 milli second or 8 uFrames
4027c478bd9Sstevel@tonic-gate  */
4037c478bd9Sstevel@tonic-gate #define	EHCI_uFRAMES_PER_USB_FRAME		8
4047c478bd9Sstevel@tonic-gate #define	EHCI_uFRAMES_PER_USB_FRAME_SHIFT	3
4057c478bd9Sstevel@tonic-gate 
4067c478bd9Sstevel@tonic-gate 
4077c478bd9Sstevel@tonic-gate /*
4087c478bd9Sstevel@tonic-gate  * Pipe private structure
4097c478bd9Sstevel@tonic-gate  *
4107c478bd9Sstevel@tonic-gate  * There is an instance of this structure per pipe.  This structure holds
4117c478bd9Sstevel@tonic-gate  * HCD specific pipe information.  A pointer to this structure is kept in
4127c478bd9Sstevel@tonic-gate  * the USBA pipe handle (usba_pipe_handle_data_t).
4137c478bd9Sstevel@tonic-gate  */
4147c478bd9Sstevel@tonic-gate typedef struct ehci_pipe_private {
4157c478bd9Sstevel@tonic-gate 	usba_pipe_handle_data_t	*pp_pipe_handle;	/* Back ptr to handle */
4167c478bd9Sstevel@tonic-gate 	ehci_qh_t		*pp_qh;			/* Pipe's qh */
4177c478bd9Sstevel@tonic-gate 
4187c478bd9Sstevel@tonic-gate 	/* State of the pipe */
4197c478bd9Sstevel@tonic-gate 	uint_t			pp_state;		/* See below */
4207c478bd9Sstevel@tonic-gate 
4217c478bd9Sstevel@tonic-gate 	/* Local copy of the pipe policy */
4227c478bd9Sstevel@tonic-gate 	usb_pipe_policy_t	pp_policy;
4237c478bd9Sstevel@tonic-gate 
4247c478bd9Sstevel@tonic-gate 	/* For Periodic Pipes Only */
4257c478bd9Sstevel@tonic-gate 	uint_t			pp_pnode;		/* periodic node */
4267c478bd9Sstevel@tonic-gate 	uchar_t			pp_smask;		/* Start split mask */
4277c478bd9Sstevel@tonic-gate 	uchar_t			pp_cmask;		/* Comp split mask */
4287c478bd9Sstevel@tonic-gate 	uint_t			pp_cur_periodic_req_cnt; /* Curr req count */
4297c478bd9Sstevel@tonic-gate 	uint_t			pp_max_periodic_req_cnt; /* Max req count */
4307c478bd9Sstevel@tonic-gate 
4317c478bd9Sstevel@tonic-gate 	/* For Isochronous pipes only */
4327c478bd9Sstevel@tonic-gate 	usb_frame_number_t	pp_next_frame_number;	/* Next frame no */
4337c478bd9Sstevel@tonic-gate 
4347c478bd9Sstevel@tonic-gate 	/*
4357c478bd9Sstevel@tonic-gate 	 * Each pipe may have multiple transfer wrappers. Each transfer
4367c478bd9Sstevel@tonic-gate 	 * wrapper represents a USB transfer on the bus.  A transfer is
4377c478bd9Sstevel@tonic-gate 	 * made up of one or more transactions.
4387c478bd9Sstevel@tonic-gate 	 */
4397c478bd9Sstevel@tonic-gate 	struct ehci_trans_wrapper *pp_tw_head;	/* Head of the list */
4407c478bd9Sstevel@tonic-gate 	struct ehci_trans_wrapper *pp_tw_tail;	/* Tail of the list */
4417c478bd9Sstevel@tonic-gate 
4427c478bd9Sstevel@tonic-gate 	struct ehci_isoc_xwrapper *pp_itw_head;	/* Head of the list */
4437c478bd9Sstevel@tonic-gate 	struct ehci_isoc_xwrapper *pp_itw_tail;	/* Tail of the list */
4447c478bd9Sstevel@tonic-gate 
4457c478bd9Sstevel@tonic-gate 	/*
4467c478bd9Sstevel@tonic-gate 	 * Pipe's transfer timeout handling & this transfer timeout handling
4477c478bd9Sstevel@tonic-gate 	 * will be per pipe.
4487c478bd9Sstevel@tonic-gate 	 */
4497c478bd9Sstevel@tonic-gate 	struct ehci_trans_wrapper *pp_timeout_list;	/* Timeout list */
4507c478bd9Sstevel@tonic-gate 	timeout_id_t		pp_timer_id;		/* Timer id  */
4517c478bd9Sstevel@tonic-gate 
4527c478bd9Sstevel@tonic-gate 	/* Done td count */
4537c478bd9Sstevel@tonic-gate 	uint_t			pp_count_done_qtds;	/* Done td count */
4547c478bd9Sstevel@tonic-gate 
4557c478bd9Sstevel@tonic-gate 	/* Errors */
4567c478bd9Sstevel@tonic-gate 	usb_cr_t		pp_error;		/* Pipe error */
4577c478bd9Sstevel@tonic-gate 
4587c478bd9Sstevel@tonic-gate 	/* Condition variable for transfers completion event */
4597c478bd9Sstevel@tonic-gate 	kcondvar_t		pp_xfer_cmpl_cv;	/* Xfer completion */
4607c478bd9Sstevel@tonic-gate 
4617c478bd9Sstevel@tonic-gate 	/* Pipe flag */
4627c478bd9Sstevel@tonic-gate 	uint_t			pp_flag;		/* For polled mode */
4637c478bd9Sstevel@tonic-gate 
4647c478bd9Sstevel@tonic-gate 	/* Halting States */
4657c478bd9Sstevel@tonic-gate 	uint_t			pp_halt_state;		/* Is it halting */
4667c478bd9Sstevel@tonic-gate 
4677c478bd9Sstevel@tonic-gate 	/* Condition variable for halt completion event */
4687c478bd9Sstevel@tonic-gate 	kcondvar_t		pp_halt_cmpl_cv;	/* Xfer completion */
4697c478bd9Sstevel@tonic-gate 
4707c478bd9Sstevel@tonic-gate 	/*
4717c478bd9Sstevel@tonic-gate 	 * HCD gets Interrupt/Isochronous IN polling request only once and
4727c478bd9Sstevel@tonic-gate 	 * it has to insert next polling requests after completion of first
4737c478bd9Sstevel@tonic-gate 	 * request until either stop polling/pipe close is called. So  HCD
4747c478bd9Sstevel@tonic-gate 	 * has to take copy of the original Interrupt/Isochronous IN request.
4757c478bd9Sstevel@tonic-gate 	 */
4767c478bd9Sstevel@tonic-gate 	usb_opaque_t		pp_client_periodic_in_reqp;
4777c478bd9Sstevel@tonic-gate } ehci_pipe_private_t;
4787c478bd9Sstevel@tonic-gate 
4797c478bd9Sstevel@tonic-gate _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_pipe_private_t))
4807c478bd9Sstevel@tonic-gate 
4817c478bd9Sstevel@tonic-gate /*
4827c478bd9Sstevel@tonic-gate  * Pipe states
4837c478bd9Sstevel@tonic-gate  *
4847c478bd9Sstevel@tonic-gate  * ehci pipe states will be similar to usba. Refer usbai.h.
4857c478bd9Sstevel@tonic-gate  */
4867c478bd9Sstevel@tonic-gate #define	EHCI_PIPE_STATE_IDLE		1	/* Pipe is in ready state */
4877c478bd9Sstevel@tonic-gate #define	EHCI_PIPE_STATE_ACTIVE		2	/* Pipe is in busy state */
4887c478bd9Sstevel@tonic-gate #define	EHCI_PIPE_STATE_ERROR		3	/* Pipe is in error state */
4897c478bd9Sstevel@tonic-gate 
4907c478bd9Sstevel@tonic-gate /* Additional ehci pipe states for the ehci_pipe_cleanup */
4917c478bd9Sstevel@tonic-gate #define	EHCI_PIPE_STATE_CLOSE		4	/* Pipe close */
4927c478bd9Sstevel@tonic-gate #define	EHCI_PIPE_STATE_RESET		5	/* Pipe reset */
4937c478bd9Sstevel@tonic-gate #define	EHCI_PIPE_STATE_STOP_POLLING	6	/* Pipe stop polling */
4947c478bd9Sstevel@tonic-gate 
4957c478bd9Sstevel@tonic-gate /*
4967c478bd9Sstevel@tonic-gate  * Pipe flag
4977c478bd9Sstevel@tonic-gate  *
498*6aef9e11SToomas Soome  * Interrupt or polled mode.
4997c478bd9Sstevel@tonic-gate  */
500*6aef9e11SToomas Soome #define	EHCI_INTERRUPT_MODE_FLAG	0	/* Interrupt mode flag */
5017c478bd9Sstevel@tonic-gate #define	EHCI_POLLED_MODE_FLAG		1	/* Polled mode flag */
5027c478bd9Sstevel@tonic-gate 
5037c478bd9Sstevel@tonic-gate /* Pipe specific flags */
5047c478bd9Sstevel@tonic-gate #define	EHCI_ISOC_XFER_CONTINUE		1	/* For isoc transfers */
5057c478bd9Sstevel@tonic-gate 
5067c478bd9Sstevel@tonic-gate /*
5077c478bd9Sstevel@tonic-gate  * Halting States
5087c478bd9Sstevel@tonic-gate  *  prevent halting from interleaving.
5097c478bd9Sstevel@tonic-gate  */
5107c478bd9Sstevel@tonic-gate #define	EHCI_HALT_STATE_FREE		0	/* Pipe free to accept reqs */
5117c478bd9Sstevel@tonic-gate #define	EHCI_HALT_STATE_HALTING		1	/* Currently Halting */
5127c478bd9Sstevel@tonic-gate 
5137c478bd9Sstevel@tonic-gate /*
5147c478bd9Sstevel@tonic-gate  * Request values for Clear_TT_Buffer
5157c478bd9Sstevel@tonic-gate  */
5167c478bd9Sstevel@tonic-gate #define	EHCI_CLEAR_TT_BUFFER_REQTYPE	(USB_DEV_REQ_TYPE_CLASS | \
5177c478bd9Sstevel@tonic-gate 					USB_DEV_REQ_RCPT_OTHER)
5187c478bd9Sstevel@tonic-gate #define	EHCI_CLEAR_TT_BUFFER_BREQ	8
5197c478bd9Sstevel@tonic-gate 
5207c478bd9Sstevel@tonic-gate /*
5217c478bd9Sstevel@tonic-gate  * USB frame offset
5227c478bd9Sstevel@tonic-gate  *
5237c478bd9Sstevel@tonic-gate  * Add appropriate frame offset to the current usb frame number and use it
5247c478bd9Sstevel@tonic-gate  * as a starting frame number for a given usb isochronous request.
5257c478bd9Sstevel@tonic-gate  */
5267c478bd9Sstevel@tonic-gate #define	EHCI_FRAME_OFFSET		2	/* Frame offset */
5277c478bd9Sstevel@tonic-gate 
5287c478bd9Sstevel@tonic-gate /*
5297c478bd9Sstevel@tonic-gate  * Different interrupt polling intervals supported for high speed
5307c478bd9Sstevel@tonic-gate  * devices and its range must be from 1 to 16 units. This value is
5317c478bd9Sstevel@tonic-gate  * used as th exponent for a 2 ^ (bInterval - 1). Ex: a Binterval
5327c478bd9Sstevel@tonic-gate  * of 4 means a period of 8us (2 ^ (4-1)).
5337c478bd9Sstevel@tonic-gate  *
5347c478bd9Sstevel@tonic-gate  * The following values are defined after above convertion in terms
5357c478bd9Sstevel@tonic-gate  * 125us units.
5367c478bd9Sstevel@tonic-gate  */
5377c478bd9Sstevel@tonic-gate #define	EHCI_INTR_1US_POLL		1	/* 1us poll interval */
5387c478bd9Sstevel@tonic-gate #define	EHCI_INTR_2US_POLL		2	/* 2us poll interval */
5397c478bd9Sstevel@tonic-gate #define	EHCI_INTR_4US_POLL		4	/* 4us poll interval */
5407c478bd9Sstevel@tonic-gate #define	EHCI_INTR_XUS_POLL		8	/* 8us and above */
5417c478bd9Sstevel@tonic-gate 
5427c478bd9Sstevel@tonic-gate /*
5437c478bd9Sstevel@tonic-gate  * The following indecies are are used to calculate Start and complete
5447c478bd9Sstevel@tonic-gate  * masks as per the polling interval.
5457c478bd9Sstevel@tonic-gate  */
5467c478bd9Sstevel@tonic-gate #define	EHCI_1US_MASK_INDEX		14	/* 1us mask index */
5477c478bd9Sstevel@tonic-gate #define	EHCI_2US_MASK_INDEX		12	/* 2us mask index */
5487c478bd9Sstevel@tonic-gate #define	EHCI_4US_MASK_INDEX		8	/* 4us mask index */
5497c478bd9Sstevel@tonic-gate #define	EHCI_XUS_MASK_INDEX		0	/* 8us and above */
5507c478bd9Sstevel@tonic-gate 
5517c478bd9Sstevel@tonic-gate /*
5527c478bd9Sstevel@tonic-gate  * Different interrupt polling intervals supported for low/full/high
5537c478bd9Sstevel@tonic-gate  * speed devices. For high speed devices, the following values are
5547c478bd9Sstevel@tonic-gate  * applicable after convertion.
5557c478bd9Sstevel@tonic-gate  */
5567c478bd9Sstevel@tonic-gate #define	EHCI_INTR_1MS_POLL		1	/* 1ms poll interval */
5577c478bd9Sstevel@tonic-gate #define	EHCI_INTR_2MS_POLL		2	/* 2ms poll interval */
5587c478bd9Sstevel@tonic-gate #define	EHCI_INTR_4MS_POLL		4	/* 4ms poll interval */
5597c478bd9Sstevel@tonic-gate #define	EHCI_INTR_8MS_POLL		8	/* 8ms poll interval */
5607c478bd9Sstevel@tonic-gate #define	EHCI_INTR_16MS_POLL		16	/* 16ms poll interval */
5617c478bd9Sstevel@tonic-gate #define	EHCI_INTR_32MS_POLL		32	/* 32ms poll interval */
5627c478bd9Sstevel@tonic-gate 
5637c478bd9Sstevel@tonic-gate /*
5647c478bd9Sstevel@tonic-gate  * Number of interrupt transfer requests that should be maintained on
5657c478bd9Sstevel@tonic-gate  * the interrupt endpoint corresponding to different polling intervals
5667c478bd9Sstevel@tonic-gate  * supported.
5677c478bd9Sstevel@tonic-gate  */
5687c478bd9Sstevel@tonic-gate #define	EHCI_INTR_1MS_REQS		4	/* 1ms polling interval */
5697c478bd9Sstevel@tonic-gate #define	EHCI_INTR_2MS_REQS		2	/* 2ms polling interval */
5707c478bd9Sstevel@tonic-gate #define	EHCI_INTR_XMS_REQS		1	/* Between 4ms and 32ms */
5717c478bd9Sstevel@tonic-gate 
5727c478bd9Sstevel@tonic-gate /* Function prototype */
5737c478bd9Sstevel@tonic-gate typedef void (*ehci_handler_function_t)(
5747c478bd9Sstevel@tonic-gate 	ehci_state_t			*ehcip,
5757c478bd9Sstevel@tonic-gate 	ehci_pipe_private_t		*pp,
5767c478bd9Sstevel@tonic-gate 	struct ehci_trans_wrapper	*tw,
5777c478bd9Sstevel@tonic-gate 	ehci_qtd_t			*qtd,
5787c478bd9Sstevel@tonic-gate 	void				*ehci_handle_callback_value);
5797c478bd9Sstevel@tonic-gate 
5807c478bd9Sstevel@tonic-gate 
5817c478bd9Sstevel@tonic-gate /*
5827c478bd9Sstevel@tonic-gate  * Transfer wrapper
5837c478bd9Sstevel@tonic-gate  *
5847c478bd9Sstevel@tonic-gate  * The transfer wrapper represents a USB transfer on the bus and there
5857c478bd9Sstevel@tonic-gate  * is one instance per USB transfer.  A transfer is made up of one or
5863304303fSsl  * more transactions. EHCI uses one QTD for one transaction. So one
5873304303fSsl  * transfer wrapper may have one or more QTDs associated.
5883304303fSsl  *
5893304303fSsl  * The data to be transferred are contained in the TW buffer which is
5903304303fSsl  * virtually contiguous but physically discontiguous. When preparing
5913304303fSsl  * the QTDs for a USB transfer, the DMA cookies corresponding to the
5923304303fSsl  * TW buffer need to be walked through to retrieve the DMA addresses.
5937c478bd9Sstevel@tonic-gate  *
5947c478bd9Sstevel@tonic-gate  * Control and bulk pipes will have one transfer wrapper per transfer
5957c478bd9Sstevel@tonic-gate  * and where as Isochronous and Interrupt pipes will only have one
5967c478bd9Sstevel@tonic-gate  * transfer wrapper. The transfers wrapper are continually reused for
5977c478bd9Sstevel@tonic-gate  * the Interrupt and Isochronous pipes as those pipes are polled.
5987c478bd9Sstevel@tonic-gate  */
5997c478bd9Sstevel@tonic-gate typedef struct ehci_trans_wrapper {
6007c478bd9Sstevel@tonic-gate 	struct ehci_trans_wrapper	*tw_next;	/* Next wrapper */
6017c478bd9Sstevel@tonic-gate 	ehci_pipe_private_t		*tw_pipe_private; /* Back ptr */
6027c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t		tw_dmahandle;	/* DMA handle */
6037c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t		tw_accesshandle; /* Acc hndle */
6047c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t		tw_cookie;	/* DMA cookie */
6053304303fSsl 	uint_t				tw_ncookies;	/* DMA cookie count */
6063304303fSsl 	uint_t				tw_cookie_idx;	/* DMA cookie index */
6073304303fSsl 	size_t				tw_dma_offs;	/* DMA buffer offset */
6087c478bd9Sstevel@tonic-gate 	uint32_t			tw_id;		/* 32bit ID */
6097c478bd9Sstevel@tonic-gate 	size_t				tw_length;	/* Txfer length */
6107c478bd9Sstevel@tonic-gate 	char				*tw_buf;	/* Buffer for Xfer */
6117c478bd9Sstevel@tonic-gate 	usb_flags_t			tw_flags;	/* Flags */
6127c478bd9Sstevel@tonic-gate 	uint_t				tw_num_qtds;	/* Number of QTDs */
6137c478bd9Sstevel@tonic-gate 	ehci_qtd_t			*tw_qtd_head;	/* Head QTD */
6147c478bd9Sstevel@tonic-gate 	ehci_qtd_t			*tw_qtd_tail;	/* Tail QTD */
6157c478bd9Sstevel@tonic-gate 	uint_t				tw_direction;	/* Direction of QTD */
6167c478bd9Sstevel@tonic-gate 
6177c478bd9Sstevel@tonic-gate 	/* Current transfer request pointer */
6187c478bd9Sstevel@tonic-gate 	usb_opaque_t			tw_curr_xfer_reqp;
6197c478bd9Sstevel@tonic-gate 
6207c478bd9Sstevel@tonic-gate 	/* Transfer timeout information */
6217c478bd9Sstevel@tonic-gate 	int				tw_timeout;	/* Timeout value */
6227c478bd9Sstevel@tonic-gate 	struct ehci_trans_wrapper	*tw_timeout_next; /* Xfer Timeout Q */
6237c478bd9Sstevel@tonic-gate 
6247c478bd9Sstevel@tonic-gate 	/*
6257c478bd9Sstevel@tonic-gate 	 * This is the function to call when this td is done. This way
6267c478bd9Sstevel@tonic-gate 	 * we don't have to look in the td to figure out what kind it is.
6277c478bd9Sstevel@tonic-gate 	 */
6287c478bd9Sstevel@tonic-gate 	ehci_handler_function_t		tw_handle_qtd;
6297c478bd9Sstevel@tonic-gate 
6307c478bd9Sstevel@tonic-gate 	/*
6317c478bd9Sstevel@tonic-gate 	 * This is the callback value used when processing a done td.
6327c478bd9Sstevel@tonic-gate 	 */
6337c478bd9Sstevel@tonic-gate 	usb_opaque_t			tw_handle_callback_value;
6347c478bd9Sstevel@tonic-gate 
6357c478bd9Sstevel@tonic-gate 	/* We preallocate all the td's for each tw and place them here */
6367c478bd9Sstevel@tonic-gate 	ehci_qtd_t			*tw_qtd_free_list;
6377c478bd9Sstevel@tonic-gate 	ehci_qtd_t			*tw_alt_qtd;
6387c478bd9Sstevel@tonic-gate } ehci_trans_wrapper_t;
6397c478bd9Sstevel@tonic-gate 
6407c478bd9Sstevel@tonic-gate _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_trans_wrapper))
6417c478bd9Sstevel@tonic-gate 
6427c478bd9Sstevel@tonic-gate /*
6437c478bd9Sstevel@tonic-gate  * Isochronous Transfer Wrapper
6447c478bd9Sstevel@tonic-gate  *
6457c478bd9Sstevel@tonic-gate  * This transfer wrapper is built specifically for the LOW/FULL/HIGH speed
6467c478bd9Sstevel@tonic-gate  * isochronous transfers.  A transfer wrapper consists of one or more
6477c478bd9Sstevel@tonic-gate  * transactionsl, but there is one one instance per USB transfer request.
6487c478bd9Sstevel@tonic-gate  *
6497c478bd9Sstevel@tonic-gate  * The isochrnous transfer wrapper are continiously reused because these
6507c478bd9Sstevel@tonic-gate  * pipes are polled.
6517c478bd9Sstevel@tonic-gate  */
6527c478bd9Sstevel@tonic-gate typedef struct ehci_isoc_xwrapper {
6537c478bd9Sstevel@tonic-gate 	struct ehci_isoc_xwrapper	*itw_next;	/* Next wrapper in pp */
6547c478bd9Sstevel@tonic-gate 	ehci_pipe_private_t		*itw_pipe_private;
6557c478bd9Sstevel@tonic-gate 
6567c478bd9Sstevel@tonic-gate 	/* DMA and memory pointers */
6577c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t		itw_dmahandle;	/* DMA handle ETT */
6587c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t		itw_accesshandle; /* Acc hndle */
6597c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t		itw_cookie;	/* DMA cookie */
6607c478bd9Sstevel@tonic-gate 
6617c478bd9Sstevel@tonic-gate 	/* Transfer information */
6627c478bd9Sstevel@tonic-gate 	char				*itw_buf;	/* Buffer for Xfer */
6637c478bd9Sstevel@tonic-gate 	size_t				itw_length;	/* Txfer length */
6647c478bd9Sstevel@tonic-gate 	usb_flags_t			itw_flags;	/* Flags */
6657c478bd9Sstevel@tonic-gate 	usb_port_status_t		itw_port_status; /* Port Speed */
6667c478bd9Sstevel@tonic-gate 	uint_t				itw_direction;	/* Direction of ITD */
6677c478bd9Sstevel@tonic-gate 
6687c478bd9Sstevel@tonic-gate 	/* ITD information */
6697c478bd9Sstevel@tonic-gate 	uint_t				itw_num_itds;	/* Number of ITDs */
6707c478bd9Sstevel@tonic-gate 	ehci_itd_t			*itw_itd_head;	/* Head ITD */
6717c478bd9Sstevel@tonic-gate 	ehci_itd_t			*itw_itd_tail;	/* Tail ITD */
6727c478bd9Sstevel@tonic-gate 	usb_isoc_req_t			*itw_curr_xfer_reqp;
6737c478bd9Sstevel@tonic-gate 	usb_isoc_pkt_descr_t		*itw_curr_isoc_pktp;
6747c478bd9Sstevel@tonic-gate 
6757c478bd9Sstevel@tonic-gate 	/* We preallocate all the td's for each tw and place them here */
6767c478bd9Sstevel@tonic-gate 	ehci_itd_t			*itw_itd_free_list;
6777c478bd9Sstevel@tonic-gate 
6787c478bd9Sstevel@tonic-gate 	/* Device and hub information needed by every iTD */
6797c478bd9Sstevel@tonic-gate 	uint_t				itw_hub_addr;
6807c478bd9Sstevel@tonic-gate 	uint_t				itw_hub_port;
6817c478bd9Sstevel@tonic-gate 	uint_t				itw_endpoint_num;
6827c478bd9Sstevel@tonic-gate 	uint_t				itw_device_addr;
6837c478bd9Sstevel@tonic-gate 
6847c478bd9Sstevel@tonic-gate 	/*
6857c478bd9Sstevel@tonic-gate 	 * Callback handling function and arguement.  Called when an iTD is
6867c478bd9Sstevel@tonic-gate 	 * is done.
6877c478bd9Sstevel@tonic-gate 	 */
6887c478bd9Sstevel@tonic-gate 	usb_opaque_t			itw_handle_callback_value;
6897c478bd9Sstevel@tonic-gate 
6907c478bd9Sstevel@tonic-gate 	/* 32bit ID */
6917c478bd9Sstevel@tonic-gate 	uint32_t			itw_id;
6927c478bd9Sstevel@tonic-gate } ehci_isoc_xwrapper_t;
6937c478bd9Sstevel@tonic-gate 
6947c478bd9Sstevel@tonic-gate _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_isoc_xwrapper_t))
6957c478bd9Sstevel@tonic-gate 
6967c478bd9Sstevel@tonic-gate /*
6977c478bd9Sstevel@tonic-gate  * Time waits for the different EHCI specific operations.
6987c478bd9Sstevel@tonic-gate  * These timeout values are specified in terms of microseconds.
6997c478bd9Sstevel@tonic-gate  */
7007c478bd9Sstevel@tonic-gate #define	EHCI_RESET_TIMEWAIT	10000	/* HC reset waiting time */
7017c478bd9Sstevel@tonic-gate #define	EHCI_TIMEWAIT		10000	/* HC any other waiting time */
7027c478bd9Sstevel@tonic-gate #define	EHCI_SOF_TIMEWAIT	20000	/* SOF Wait time */
7037c478bd9Sstevel@tonic-gate #define	EHCI_TAKEOVER_DELAY	10000	/* HC take over waiting time */
7047c478bd9Sstevel@tonic-gate #define	EHCI_TAKEOVER_WAIT_COUNT	25	/* HC take over waiting count */
7057c478bd9Sstevel@tonic-gate 
7067c478bd9Sstevel@tonic-gate /* These timeout values are specified in seconds */
7077c478bd9Sstevel@tonic-gate #define	EHCI_DEFAULT_XFER_TIMEOUT	5 /* Default transfer timeout */
7087c478bd9Sstevel@tonic-gate #define	EHCI_XFER_CMPL_TIMEWAIT		3 /* Xfers completion timewait */
7097c478bd9Sstevel@tonic-gate 
7107c478bd9Sstevel@tonic-gate /* EHCI flags for general use */
7117c478bd9Sstevel@tonic-gate #define	EHCI_FLAGS_NOSLEEP	0x000	/* Don't wait for SOF */
7127c478bd9Sstevel@tonic-gate #define	EHCI_FLAGS_SLEEP	0x100	/* Wait for SOF */
7137c478bd9Sstevel@tonic-gate #define	EHCI_FLAGS_DMA_SYNC	0x200	/* Call ddi_dma_sync */
7147c478bd9Sstevel@tonic-gate 
7157c478bd9Sstevel@tonic-gate /*
7167c478bd9Sstevel@tonic-gate  * Maximum allowable data transfer  size per transaction as supported
7177c478bd9Sstevel@tonic-gate  * by EHCI is 20k. (See EHCI Host Controller Interface Spec Rev 0.96)
7187c478bd9Sstevel@tonic-gate  *
7197c478bd9Sstevel@tonic-gate  * Also within QTD, there will be five buffer pointers abd each buffer
7207c478bd9Sstevel@tonic-gate  * pointer can transfer upto 4k bytes of data.
7217c478bd9Sstevel@tonic-gate  */
7227c478bd9Sstevel@tonic-gate #define	EHCI_MAX_QTD_XFER_SIZE	0x5000	/* Maxmum data per transaction */
7237c478bd9Sstevel@tonic-gate #define	EHCI_MAX_QTD_BUF_SIZE	0x1000	/* Maxmum data per buffer */
7247c478bd9Sstevel@tonic-gate 
7257c478bd9Sstevel@tonic-gate /*
7267c478bd9Sstevel@tonic-gate  * The maximum allowable bulk data transfer size. It can be different
7277c478bd9Sstevel@tonic-gate  * from EHCI_MAX_QTD_XFER_SIZE and if it is more then ehci driver will
7287c478bd9Sstevel@tonic-gate  * take care of  breaking a bulk data request into  multiples of ehci
7297c478bd9Sstevel@tonic-gate  * EHCI_MAX_QTD_XFER_SIZE  until request is satisfied.	Currently this
7307c478bd9Sstevel@tonic-gate  * value is set to 640k bytes.
7317c478bd9Sstevel@tonic-gate  */
7327c478bd9Sstevel@tonic-gate #define	EHCI_MAX_BULK_XFER_SIZE	0xA0000	/* Maximum bulk transfer size */
7337c478bd9Sstevel@tonic-gate 
7347c478bd9Sstevel@tonic-gate /*
7357c478bd9Sstevel@tonic-gate  * Timeout flags
7367c478bd9Sstevel@tonic-gate  *
7377c478bd9Sstevel@tonic-gate  * These flags will be used to stop the timer before timeout handler
7387c478bd9Sstevel@tonic-gate  * gets executed.
7397c478bd9Sstevel@tonic-gate  */
7407c478bd9Sstevel@tonic-gate #define	EHCI_REMOVE_XFER_IFLAST	1	/* Stop the timer if it is last QTD */
7417c478bd9Sstevel@tonic-gate #define	EHCI_REMOVE_XFER_ALWAYS	2	/* Stop the timer without condition */
7427c478bd9Sstevel@tonic-gate 
7437c478bd9Sstevel@tonic-gate 
7447c478bd9Sstevel@tonic-gate /*
7457c478bd9Sstevel@tonic-gate  * High speed bandwidth allocation
7467c478bd9Sstevel@tonic-gate  *
7477c478bd9Sstevel@tonic-gate  * The following definitions are used during bandwidth calculations
7487c478bd9Sstevel@tonic-gate  * for a given high speed endpoint or high speed split transactions.
7497c478bd9Sstevel@tonic-gate  */
7507c478bd9Sstevel@tonic-gate #define	HS_BUS_BANDWIDTH	7500	/* Up to 7500 bytes per 125us */
7517c478bd9Sstevel@tonic-gate #define	HS_MAX_POLL_INTERVAL	16	/* Max high speed polling interval */
7527c478bd9Sstevel@tonic-gate #define	HS_MIN_POLL_INTERVAL	1	/* Min high speed polling interval */
7537c478bd9Sstevel@tonic-gate #define	HS_SOF			12	/* Length in bytes of High speed SOF */
7547c478bd9Sstevel@tonic-gate #define	HS_EOF			70	/* Length in bytes of High speed EOF */
7557c478bd9Sstevel@tonic-gate #define	TREE_HEIGHT		5	/* Log base 2 of 32 */
7567c478bd9Sstevel@tonic-gate 
7577c478bd9Sstevel@tonic-gate /*
7587c478bd9Sstevel@tonic-gate  * As per USB 2.0 specification section 5.5.4, 20% of bus time is reserved
7597c478bd9Sstevel@tonic-gate  * for the non-periodic high-speed transfers. Where as peridoic high-speed
7607c478bd9Sstevel@tonic-gate  * transfers will get 80% of the bus time. In one micro-frame or 125us, we
7617c478bd9Sstevel@tonic-gate  * can transfer 7500 bytes or 60,000 bits.
7627c478bd9Sstevel@tonic-gate  */
7637c478bd9Sstevel@tonic-gate #define	HS_NON_PERIODIC_BANDWIDTH	1500
7647c478bd9Sstevel@tonic-gate #define	HS_PERIODIC_BANDWIDTH		(HS_BUS_BANDWIDTH - HS_SOF - \
7657c478bd9Sstevel@tonic-gate 					HS_EOF - HS_NON_PERIODIC_BANDWIDTH)
7667c478bd9Sstevel@tonic-gate 
7677c478bd9Sstevel@tonic-gate /*
7687c478bd9Sstevel@tonic-gate  * High speed periodic frame bandwidth will be eight times the micro frame
7697c478bd9Sstevel@tonic-gate  * high speed periodic bandwidth.
7707c478bd9Sstevel@tonic-gate  */
7717c478bd9Sstevel@tonic-gate #define	HS_PERIODIC_FRAME_BANDWIDTH	HS_PERIODIC_BANDWIDTH * EHCI_MAX_UFRAMES
7727c478bd9Sstevel@tonic-gate 
7737c478bd9Sstevel@tonic-gate /*
7747c478bd9Sstevel@tonic-gate  * The following are the protocol overheads in terms of Bytes for the
7757c478bd9Sstevel@tonic-gate  * different transfer types.  All these protocol overhead  values are
7767c478bd9Sstevel@tonic-gate  * derived from the 5.11.3 section of USB 2.0 Specification.
7777c478bd9Sstevel@tonic-gate  */
7787c478bd9Sstevel@tonic-gate #define	HS_NON_ISOC_PROTO_OVERHEAD	55
7797c478bd9Sstevel@tonic-gate #define	HS_ISOC_PROTO_OVERHEAD		38
7807c478bd9Sstevel@tonic-gate 
7817c478bd9Sstevel@tonic-gate /*
7827c478bd9Sstevel@tonic-gate  * The following are THE protocol overheads in terms of Bytes for the
7837c478bd9Sstevel@tonic-gate  * start and complete split transactions tokens overheads.  All these
7847c478bd9Sstevel@tonic-gate  * protocol overhead values are derived from the 8.4.2.2 and 8.4.2.3
7857c478bd9Sstevel@tonic-gate  * of USB2.0 Specification.
7867c478bd9Sstevel@tonic-gate  */
7877c478bd9Sstevel@tonic-gate #define	START_SPLIT_OVERHEAD		04
7887c478bd9Sstevel@tonic-gate #define	COMPLETE_SPLIT_OVERHEAD		04
7897c478bd9Sstevel@tonic-gate 
7907c478bd9Sstevel@tonic-gate /*
7917c478bd9Sstevel@tonic-gate  * The Host Controller (HC) delays are the USB host controller specific
7927c478bd9Sstevel@tonic-gate  * delays. The value shown below is the host  controller delay for  the
7937c478bd9Sstevel@tonic-gate  * given EHCI host controller.
7947c478bd9Sstevel@tonic-gate  */
7957c478bd9Sstevel@tonic-gate #define	EHCI_HOST_CONTROLLER_DELAY	18
7967c478bd9Sstevel@tonic-gate 
7977c478bd9Sstevel@tonic-gate /*
7987c478bd9Sstevel@tonic-gate  * Low/Full speed bandwidth allocation
7997c478bd9Sstevel@tonic-gate  *
8007c478bd9Sstevel@tonic-gate  * The following definitions are used during bandwidth calculations for
8017c478bd9Sstevel@tonic-gate  * a given high speed hub or  a transaction translator	(TT) and  for a
8027c478bd9Sstevel@tonic-gate  * given low/full speed device connected to high speed hub or TT  using
8037c478bd9Sstevel@tonic-gate  * split transactions
8047c478bd9Sstevel@tonic-gate  */
8057c478bd9Sstevel@tonic-gate #define	FS_BUS_BANDWIDTH	1500	/* Up to 1500 bytes per 1ms */
8067c478bd9Sstevel@tonic-gate #define	FS_MAX_POLL_INTERVAL	255	/* Max full speed poll interval */
8077c478bd9Sstevel@tonic-gate #define	FS_MIN_POLL_INTERVAL	1	/* Min full speed polling interval */
8087c478bd9Sstevel@tonic-gate #define	FS_SOF			6	/* Length in bytes of Full speed SOF */
8097c478bd9Sstevel@tonic-gate #define	FS_EOF			4	/* Length in bytes of Full speed EOF */
8107c478bd9Sstevel@tonic-gate 
8117c478bd9Sstevel@tonic-gate /*
8127c478bd9Sstevel@tonic-gate  * Minimum polling interval for low speed endpoint
8137c478bd9Sstevel@tonic-gate  *
8147c478bd9Sstevel@tonic-gate  * According USB 2.0 Specification, a full-speed endpoint can specify
8157c478bd9Sstevel@tonic-gate  * a desired polling interval 1ms to 255ms and a low speed endpoints
8167c478bd9Sstevel@tonic-gate  * are limited to specifying only 10ms to 255ms. But some old keyboards
8177c478bd9Sstevel@tonic-gate  * and mice uses polling interval of 8ms. For compatibility purpose,
8187c478bd9Sstevel@tonic-gate  * we are using polling interval between 8ms and 255ms for low speed
8197c478bd9Sstevel@tonic-gate  * endpoints. The ehci driver will use 8ms polling interval if a low
8207c478bd9Sstevel@tonic-gate  * speed device reports a polling interval that is less than 8ms.
8217c478bd9Sstevel@tonic-gate  */
8227c478bd9Sstevel@tonic-gate #define	LS_MAX_POLL_INTERVAL	255	/* Max low speed poll interval */
8237c478bd9Sstevel@tonic-gate #define	LS_MIN_POLL_INTERVAL	8	/* Min low speed polling interval */
8247c478bd9Sstevel@tonic-gate 
8257c478bd9Sstevel@tonic-gate /*
8267c478bd9Sstevel@tonic-gate  * For non-periodic transfers, reserve atleast for one low-speed device
8277c478bd9Sstevel@tonic-gate  * transaction. According to USB Bandwidth Analysis white paper and also
8287c478bd9Sstevel@tonic-gate  * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed
8297c478bd9Sstevel@tonic-gate  * transaction takes 0x628h full speed bits (197 bytes), which comes to
8307c478bd9Sstevel@tonic-gate  * around 13% of USB frame time.
8317c478bd9Sstevel@tonic-gate  *
8327c478bd9Sstevel@tonic-gate  * The periodic transfers will	get around 87% of USB frame time.
8337c478bd9Sstevel@tonic-gate  */
8347c478bd9Sstevel@tonic-gate #define	FS_NON_PERIODIC_BANDWIDTH	197
8357c478bd9Sstevel@tonic-gate #define	FS_PERIODIC_BANDWIDTH		(FS_BUS_BANDWIDTH - FS_SOF - \
8367c478bd9Sstevel@tonic-gate 					FS_EOF - FS_NON_PERIODIC_BANDWIDTH)
8377c478bd9Sstevel@tonic-gate 
8387c478bd9Sstevel@tonic-gate /*
8397c478bd9Sstevel@tonic-gate  * The following are the protocol overheads in terms of Bytes for the
8407c478bd9Sstevel@tonic-gate  * different transfer types.  All these protocol overhead  values are
8417c478bd9Sstevel@tonic-gate  * derived from the 5.11.3 section of USB Specification	and  with the
8427c478bd9Sstevel@tonic-gate  * help of Bandwidth Analysis white paper which is posted on the  USB
8437c478bd9Sstevel@tonic-gate  * developer forum.
8447c478bd9Sstevel@tonic-gate  */
8457c478bd9Sstevel@tonic-gate #define	FS_NON_ISOC_PROTO_OVERHEAD	14
8467c478bd9Sstevel@tonic-gate #define	FS_ISOC_INPUT_PROTO_OVERHEAD	11
8477c478bd9Sstevel@tonic-gate #define	FS_ISOC_OUTPUT_PROTO_OVERHEAD	10
8487c478bd9Sstevel@tonic-gate #define	LOW_SPEED_PROTO_OVERHEAD	97
8497c478bd9Sstevel@tonic-gate #define	HUB_LOW_SPEED_PROTO_OVERHEAD	01
8507c478bd9Sstevel@tonic-gate 
8517c478bd9Sstevel@tonic-gate /* The maximum amount of isoch data that can be transferred in one uFrame */
8527c478bd9Sstevel@tonic-gate #define	MAX_UFRAME_SITD_XFER		188
8537c478bd9Sstevel@tonic-gate 
8547c478bd9Sstevel@tonic-gate /*
8557c478bd9Sstevel@tonic-gate  * The low speed clock below represents that to transmit one low-speed
8567c478bd9Sstevel@tonic-gate  * bit takes eight times more than one full speed bit time.
8577c478bd9Sstevel@tonic-gate  */
8587c478bd9Sstevel@tonic-gate #define	LOW_SPEED_CLOCK			8
8597c478bd9Sstevel@tonic-gate 
8607c478bd9Sstevel@tonic-gate /*
8617c478bd9Sstevel@tonic-gate  * The Transaction Translator (TT) delay is the additional time needed
8627c478bd9Sstevel@tonic-gate  * to execute low/full speed transaction from high speed split transaction
8637c478bd9Sstevel@tonic-gate  * for the low/full device connected to the high speed extrenal hub.
8647c478bd9Sstevel@tonic-gate  */
8657c478bd9Sstevel@tonic-gate #define	TT_DELAY			18
8667c478bd9Sstevel@tonic-gate 
8677c478bd9Sstevel@tonic-gate 
8687c478bd9Sstevel@tonic-gate /*
8697c478bd9Sstevel@tonic-gate  * Macros for setting/getting information
8707c478bd9Sstevel@tonic-gate  */
8717c478bd9Sstevel@tonic-gate #define	Get_QH(addr)		ddi_get32(ehcip->ehci_qh_pool_mem_handle, \
8727c478bd9Sstevel@tonic-gate 					(uint32_t *)&addr)
8737c478bd9Sstevel@tonic-gate 
8747c478bd9Sstevel@tonic-gate #define	Set_QH(addr, val)	ddi_put32(ehcip->ehci_qh_pool_mem_handle,  \
8757c478bd9Sstevel@tonic-gate 					((uint32_t *)&addr), \
8767c478bd9Sstevel@tonic-gate 					((int32_t)(val)))
8777c478bd9Sstevel@tonic-gate 
8787c478bd9Sstevel@tonic-gate #define	Get_QTD(addr)		ddi_get32(ehcip->ehci_qtd_pool_mem_handle, \
8797c478bd9Sstevel@tonic-gate 					(uint32_t *)&addr)
8807c478bd9Sstevel@tonic-gate 
8817c478bd9Sstevel@tonic-gate #define	Set_QTD(addr, val)	ddi_put32(ehcip->ehci_qtd_pool_mem_handle, \
8827c478bd9Sstevel@tonic-gate 					((uint32_t *)&addr), \
8837c478bd9Sstevel@tonic-gate 					((int32_t)(val)))
8847c478bd9Sstevel@tonic-gate 
8857c478bd9Sstevel@tonic-gate #define	Get_ITD(addr)		ddi_get32(ehcip->ehci_itd_pool_mem_handle, \
8867c478bd9Sstevel@tonic-gate 					(uint32_t *)&addr)
8877c478bd9Sstevel@tonic-gate 
8887c478bd9Sstevel@tonic-gate #define	Set_ITD(addr, val)	ddi_put32(ehcip->ehci_itd_pool_mem_handle, \
8897c478bd9Sstevel@tonic-gate 					((uint32_t *)&addr), \
8907c478bd9Sstevel@tonic-gate 					((int32_t)(val)))
8917c478bd9Sstevel@tonic-gate 
8927c478bd9Sstevel@tonic-gate #define	Get_ITD_BODY(ptr, addr)		ddi_get32( \
8937c478bd9Sstevel@tonic-gate 					    ehcip->ehci_itd_pool_mem_handle, \
8947c478bd9Sstevel@tonic-gate 					    (uint32_t *)&ptr->itd_body[addr])
8957c478bd9Sstevel@tonic-gate 
8967c478bd9Sstevel@tonic-gate #define	Set_ITD_BODY(ptr, addr, val)	ddi_put32( \
8977c478bd9Sstevel@tonic-gate 					    ehcip->ehci_itd_pool_mem_handle, \
8987c478bd9Sstevel@tonic-gate 					    ((uint32_t *)&ptr->itd_body[addr]),\
8997c478bd9Sstevel@tonic-gate 					    ((int32_t)(val)))
9007c478bd9Sstevel@tonic-gate 
901b3001defSlg #define	Get_ITD_INDEX(ptr, pos)		ddi_get32( \
902b3001defSlg 					    ehcip->ehci_itd_pool_mem_handle, \
903b3001defSlg 					    (uint32_t *)&ptr->itd_index[pos])
904b3001defSlg 
905b3001defSlg #define	Set_ITD_INDEX(ptr, pos, val)	ddi_put32( \
906b3001defSlg 					    ehcip->ehci_itd_pool_mem_handle, \
907b3001defSlg 					    ((uint32_t *)&ptr->itd_index[pos]),\
908b3001defSlg 					    ((uint32_t)(val)))
909b3001defSlg 
9107c478bd9Sstevel@tonic-gate #define	Get_ITD_FRAME(addr)		ddi_get64( \
9117c478bd9Sstevel@tonic-gate 					    ehcip->ehci_itd_pool_mem_handle, \
9127c478bd9Sstevel@tonic-gate 					    (uint64_t *)&addr)
9137c478bd9Sstevel@tonic-gate 
9147c478bd9Sstevel@tonic-gate #define	Set_ITD_FRAME(addr, val)	ddi_put64( \
9157c478bd9Sstevel@tonic-gate 					    ehcip->ehci_itd_pool_mem_handle, \
9167c478bd9Sstevel@tonic-gate 					    ((uint64_t *)&addr), \
9177c478bd9Sstevel@tonic-gate 					    (val))
9187c478bd9Sstevel@tonic-gate 
9197c478bd9Sstevel@tonic-gate #define	Get_PFLT(addr)		ddi_get32(ehcip->ehci_pflt_mem_handle, \
9207c478bd9Sstevel@tonic-gate 					(uint32_t *)&addr)
9217c478bd9Sstevel@tonic-gate 
9227c478bd9Sstevel@tonic-gate #define	Set_PFLT(addr, val)	ddi_put32(ehcip->ehci_pflt_mem_handle, \
9237c478bd9Sstevel@tonic-gate 					((uint32_t *)&addr), \
9247c478bd9Sstevel@tonic-gate 					((int32_t)(uintptr_t)(val)))
9257c478bd9Sstevel@tonic-gate 
9267c478bd9Sstevel@tonic-gate #define	Get_8Cap(addr)		ddi_get8(ehcip->ehci_caps_handle, \
9277c478bd9Sstevel@tonic-gate 					(uint8_t *)&ehcip->ehci_capsp->addr)
9287c478bd9Sstevel@tonic-gate 
9297c478bd9Sstevel@tonic-gate #define	Get_16Cap(addr)		ddi_get16(ehcip->ehci_caps_handle, \
9307c478bd9Sstevel@tonic-gate 					(uint16_t *)&ehcip->ehci_capsp->addr)
9317c478bd9Sstevel@tonic-gate 
9327c478bd9Sstevel@tonic-gate #define	Get_Cap(addr)		ddi_get32(ehcip->ehci_caps_handle, \
9337c478bd9Sstevel@tonic-gate 					(uint32_t *)&ehcip->ehci_capsp->addr)
9347c478bd9Sstevel@tonic-gate 
9357c478bd9Sstevel@tonic-gate #define	Get_OpReg(addr)		ddi_get32(ehcip->ehci_caps_handle, \
9367c478bd9Sstevel@tonic-gate 					(uint32_t *)&ehcip->ehci_regsp->addr)
9377c478bd9Sstevel@tonic-gate 
9387c478bd9Sstevel@tonic-gate #define	Set_OpReg(addr, val)	ddi_put32(ehcip->ehci_caps_handle, \
9397c478bd9Sstevel@tonic-gate 				((uint32_t *)&ehcip->ehci_regsp->addr), \
9407c478bd9Sstevel@tonic-gate 					((int32_t)(val)))
9417c478bd9Sstevel@tonic-gate 
942b3001defSlg #define	CalculateITDMultiField(pkgSize)		(1 + (((pkgSize)>>11) & 0x03))
943b3001defSlg 
944921cd50dSgk #define	EHCI_MAX_RETRY		10
945921cd50dSgk 
946921cd50dSgk #define	Set_OpRegRetry(addr, val, r) \
947921cd50dSgk 				while (Get_OpReg(addr) != val) { \
948921cd50dSgk 					if (r >= EHCI_MAX_RETRY) \
949921cd50dSgk 						break; \
950921cd50dSgk 					r++; \
951921cd50dSgk 					Set_OpReg(addr, val); \
952921cd50dSgk 				}
953921cd50dSgk 
9547c478bd9Sstevel@tonic-gate #define	Sync_QH_QTD_Pool(ehcip) (void) ddi_dma_sync( \
9557c478bd9Sstevel@tonic-gate 				ehcip->ehci_qh_pool_dma_handle, \
9567c478bd9Sstevel@tonic-gate 				0, EHCI_QH_POOL_SIZE * sizeof (ehci_qh_t), \
9577c478bd9Sstevel@tonic-gate 				DDI_DMA_SYNC_FORCPU); \
9587c478bd9Sstevel@tonic-gate 				(void) ddi_dma_sync( \
9597c478bd9Sstevel@tonic-gate 				ehcip->ehci_qtd_pool_dma_handle, \
9607c478bd9Sstevel@tonic-gate 				0, EHCI_QTD_POOL_SIZE * sizeof (ehci_qtd_t), \
9617c478bd9Sstevel@tonic-gate 				DDI_DMA_SYNC_FORCPU);
9627c478bd9Sstevel@tonic-gate 
9637c478bd9Sstevel@tonic-gate #define	Sync_ITD_Pool(ehcip) (void) ddi_dma_sync( \
9647c478bd9Sstevel@tonic-gate 				ehcip->ehci_itd_pool_dma_handle, \
9657c478bd9Sstevel@tonic-gate 				0, EHCI_ITD_POOL_SIZE * sizeof (ehci_itd_t), \
9667c478bd9Sstevel@tonic-gate 				DDI_DMA_SYNC_FORCPU);
9677c478bd9Sstevel@tonic-gate 
9687c478bd9Sstevel@tonic-gate #define	Sync_IO_Buffer(dma_handle, length) \
9697c478bd9Sstevel@tonic-gate 				(void) ddi_dma_sync(dma_handle, \
9707c478bd9Sstevel@tonic-gate 				0, length, DDI_DMA_SYNC_FORCPU);
9717c478bd9Sstevel@tonic-gate 
9727c478bd9Sstevel@tonic-gate #define	Sync_IO_Buffer_for_device(dma_handle, length) \
9737c478bd9Sstevel@tonic-gate 				(void) ddi_dma_sync(dma_handle, \
9747c478bd9Sstevel@tonic-gate 				0, length, DDI_DMA_SYNC_FORDEV);
9757c478bd9Sstevel@tonic-gate 
9767c478bd9Sstevel@tonic-gate /*
9777c478bd9Sstevel@tonic-gate  * Macros to speed handling of 32bit IDs
9787c478bd9Sstevel@tonic-gate  */
9797c478bd9Sstevel@tonic-gate #define	EHCI_GET_ID(x)		id32_alloc((void *)(x), KM_SLEEP)
9807c478bd9Sstevel@tonic-gate #define	EHCI_LOOKUP_ID(x)	id32_lookup((x))
9817c478bd9Sstevel@tonic-gate #define	EHCI_FREE_ID(x)		id32_free((x))
9827c478bd9Sstevel@tonic-gate 
9837c478bd9Sstevel@tonic-gate 
9847c478bd9Sstevel@tonic-gate /*
9857c478bd9Sstevel@tonic-gate  * Miscellaneous definitions.
9867c478bd9Sstevel@tonic-gate  */
9877c478bd9Sstevel@tonic-gate 
9887c478bd9Sstevel@tonic-gate /* Data toggle bits */
9897c478bd9Sstevel@tonic-gate #define	DATA0		0
9907c478bd9Sstevel@tonic-gate #define	DATA1		1
9917c478bd9Sstevel@tonic-gate 
9927c478bd9Sstevel@tonic-gate /* Halt bit actions */
9937c478bd9Sstevel@tonic-gate #define	CLEAR_HALT	0
9947c478bd9Sstevel@tonic-gate #define	SET_HALT	1
9957c478bd9Sstevel@tonic-gate 
9967c478bd9Sstevel@tonic-gate typedef uint_t		halt_bit_t;
9977c478bd9Sstevel@tonic-gate 
9987c478bd9Sstevel@tonic-gate /*
9997c478bd9Sstevel@tonic-gate  * Setup Packet
10007c478bd9Sstevel@tonic-gate  */
10017c478bd9Sstevel@tonic-gate typedef struct setup_pkt {
10027c478bd9Sstevel@tonic-gate 	uchar_t	bmRequestType;
10037c478bd9Sstevel@tonic-gate 	uchar_t	bRequest;
10047c478bd9Sstevel@tonic-gate 	ushort_t wValue;
10057c478bd9Sstevel@tonic-gate 	ushort_t wIndex;
10067c478bd9Sstevel@tonic-gate 	ushort_t wLength;
10077c478bd9Sstevel@tonic-gate }setup_pkt_t;
10087c478bd9Sstevel@tonic-gate 
10097c478bd9Sstevel@tonic-gate #define	SETUP_SIZE		8	/* Setup packet is always 8 bytes */
10107c478bd9Sstevel@tonic-gate 
10117c478bd9Sstevel@tonic-gate #define	REQUEST_TYPE_OFFSET	0
10127c478bd9Sstevel@tonic-gate #define	REQUEST_OFFSET		1
10137c478bd9Sstevel@tonic-gate #define	VALUE_OFFSET		2
10147c478bd9Sstevel@tonic-gate #define	INDEX_OFFSET		4
10157c478bd9Sstevel@tonic-gate #define	LENGTH_OFFSET		6
10167c478bd9Sstevel@tonic-gate 
10177c478bd9Sstevel@tonic-gate #define	TYPE_DEV_TO_HOST	0x80000000
10187c478bd9Sstevel@tonic-gate #define	DEVICE			0x00000001
10197c478bd9Sstevel@tonic-gate #define	CONFIGURATION		0x00000002
10207c478bd9Sstevel@tonic-gate 
10217c478bd9Sstevel@tonic-gate /*
10227c478bd9Sstevel@tonic-gate  * The following are used in attach to	 indicate
10237c478bd9Sstevel@tonic-gate  * what has been succesfully allocated, so detach
10247c478bd9Sstevel@tonic-gate  * can remove them.
10257c478bd9Sstevel@tonic-gate  */
10267c478bd9Sstevel@tonic-gate #define	EHCI_ATTACH		0x01	/* ehci driver initilization */
10277c478bd9Sstevel@tonic-gate #define	EHCI_ZALLOC		0x02	/* Memory for ehci state structure */
10287c478bd9Sstevel@tonic-gate #define	EHCI_INTR		0x04	/* Interrupt handler registered */
10297c478bd9Sstevel@tonic-gate #define	EHCI_USBAREG		0x08	/* USBA registered */
10307c478bd9Sstevel@tonic-gate #define	EHCI_RHREG		0x10	/* Root hub driver loaded */
10317c478bd9Sstevel@tonic-gate 
10327c478bd9Sstevel@tonic-gate /*
10337c478bd9Sstevel@tonic-gate  * This variable is used in the EHCI_FLAGS to tell the ISR to broadcase
10347c478bd9Sstevel@tonic-gate  * the ehci_async_schedule_advance_cv when an intr occurs.  It is used to
10357c478bd9Sstevel@tonic-gate  * make sure that EHCI is receiving interrupts.
10367c478bd9Sstevel@tonic-gate  */
10377c478bd9Sstevel@tonic-gate #define	EHCI_CV_INTR		0x20	/* Ask INTR to broadcast cv */
10387c478bd9Sstevel@tonic-gate 
10397c478bd9Sstevel@tonic-gate #define	EHCI_UNIT(dev)	(getminor((dev)) & ~HUBD_IS_ROOT_HUB)
10407c478bd9Sstevel@tonic-gate 
10417c478bd9Sstevel@tonic-gate /*
10427c478bd9Sstevel@tonic-gate  * Debug printing
10437c478bd9Sstevel@tonic-gate  * Masks
10447c478bd9Sstevel@tonic-gate  */
10457c478bd9Sstevel@tonic-gate #define	PRINT_MASK_ATTA		0x00000001	/* Attach time */
10467c478bd9Sstevel@tonic-gate #define	PRINT_MASK_LISTS	0x00000002	/* List management */
10477c478bd9Sstevel@tonic-gate #define	PRINT_MASK_ROOT_HUB	0x00000004	/* Root hub stuff */
10487c478bd9Sstevel@tonic-gate #define	PRINT_MASK_ALLOC	0x00000008	/* Alloc/dealloc descr */
10497c478bd9Sstevel@tonic-gate #define	PRINT_MASK_INTR		0x00000010	/* Interrupt handling */
10507c478bd9Sstevel@tonic-gate #define	PRINT_MASK_BW		0x00000020	/* Bandwidth */
10517c478bd9Sstevel@tonic-gate #define	PRINT_MASK_CBOPS	0x00000040	/* CB-OPS */
10527c478bd9Sstevel@tonic-gate #define	PRINT_MASK_HCDI		0x00000080	/* HCDI entry points */
10537c478bd9Sstevel@tonic-gate #define	PRINT_MASK_DUMPING	0x00000100	/* Dump ehci info */
10547c478bd9Sstevel@tonic-gate #define	PRINT_MASK_ALL		0xFFFFFFFF
10557c478bd9Sstevel@tonic-gate 
10563ceb94daSbc #define	PCI_VENDOR_NVIDIA	0x10de		/* PCI Vendor-id NVIDIA */
10573ceb94daSbc #define	PCI_DEVICE_NVIDIA_CK804	0x5b
10582259743eSbinzi cao - Sun Microsystems - Beijing China #define	PCI_DEVICE_NVIDIA_MCP04	0x3c
10597c478bd9Sstevel@tonic-gate /*
10607c478bd9Sstevel@tonic-gate  * workaround for ALI chips
10617c478bd9Sstevel@tonic-gate  */
10627c478bd9Sstevel@tonic-gate #define	PCI_VENDOR_ALI		0x10b9		/* PCI Vendor-id Acer */
1063677739beShx 
10644610e4a0Sfrits /*
10654610e4a0Sfrits  * NEC on COMBO and Uli M1575 can support PM
10664610e4a0Sfrits  */
10674610e4a0Sfrits #define	PCI_VENDOR_NEC_COMBO	0x1033
10684610e4a0Sfrits #define	PCI_DEVICE_NEC_COMBO	0xe0
10694610e4a0Sfrits #define	PCI_VENDOR_ULi_M1575	0x10b9
10704610e4a0Sfrits #define	PCI_DEVICE_ULi_M1575	0x5239
10714610e4a0Sfrits 
1072677739beShx /*
1073677739beShx  * VIA chips have some problems, the workaround can ensure those chips
1074677739beShx  * work reliably. Revisions >= 0x80 are part of a southbridge and appear
1075677739beShx  * to be reliable.
1076677739beShx  */
10777c478bd9Sstevel@tonic-gate #define	PCI_VENDOR_VIA		0x1106		/* PCI Vendor-id VIA */
1078677739beShx #define	PCI_VIA_REVISION_6212	0x80		/* VIA 6212 revision ID */
10797c478bd9Sstevel@tonic-gate 
10807c478bd9Sstevel@tonic-gate #define	EHCI_VIA_LOST_INTERRUPTS	0x01
10817c478bd9Sstevel@tonic-gate #define	EHCI_VIA_ASYNC_SCHEDULE		0x02
10827c478bd9Sstevel@tonic-gate #define	EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE	0x04
10837c478bd9Sstevel@tonic-gate 
10847c478bd9Sstevel@tonic-gate #define	EHCI_VIA_WORKAROUNDS \
10857c478bd9Sstevel@tonic-gate 	(EHCI_VIA_LOST_INTERRUPTS | \
10867c478bd9Sstevel@tonic-gate 	EHCI_VIA_ASYNC_SCHEDULE | \
10877c478bd9Sstevel@tonic-gate 	EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE)
10887c478bd9Sstevel@tonic-gate 
10897c478bd9Sstevel@tonic-gate #define	EHCI_VIA_MAX_BULK_XFER_SIZE 0x8000 /* Maximum bulk transfer size */
10907c478bd9Sstevel@tonic-gate 
10917c478bd9Sstevel@tonic-gate 
10927c478bd9Sstevel@tonic-gate /*
10937c478bd9Sstevel@tonic-gate  * EHCI HCDI entry points
10947c478bd9Sstevel@tonic-gate  *
10957c478bd9Sstevel@tonic-gate  * The Host Controller Driver Interfaces (HCDI) are the software interfaces
10967c478bd9Sstevel@tonic-gate  * between the Universal Serial Bus Driver (USBA) and the Host	Controller
10977c478bd9Sstevel@tonic-gate  * Driver (HCD). The HCDI interfaces or entry points are subject to change.
10987c478bd9Sstevel@tonic-gate  */
10997c478bd9Sstevel@tonic-gate int		ehci_hcdi_pipe_open(
11007c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11017c478bd9Sstevel@tonic-gate 				usb_flags_t		usb_flags);
11027c478bd9Sstevel@tonic-gate int		ehci_hcdi_pipe_close(
11037c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11047c478bd9Sstevel@tonic-gate 				usb_flags_t		usb_flags);
11057c478bd9Sstevel@tonic-gate int		ehci_hcdi_pipe_reset(
11067c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11077c478bd9Sstevel@tonic-gate 				usb_flags_t		usb_flags);
1108269552cdSguoqing zhu - Sun Microsystems - Beijing China void		ehci_hcdi_pipe_reset_data_toggle(
1109269552cdSguoqing zhu - Sun Microsystems - Beijing China 				usba_pipe_handle_data_t	*ph);
11107c478bd9Sstevel@tonic-gate int		ehci_hcdi_pipe_ctrl_xfer(
11117c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11127c478bd9Sstevel@tonic-gate 				usb_ctrl_req_t		*ctrl_reqp,
11137c478bd9Sstevel@tonic-gate 				usb_flags_t		usb_flags);
11147c478bd9Sstevel@tonic-gate int		ehci_hcdi_bulk_transfer_size(
11157c478bd9Sstevel@tonic-gate 				usba_device_t		*usba_device,
11167c478bd9Sstevel@tonic-gate 				size_t			*size);
11177c478bd9Sstevel@tonic-gate int		ehci_hcdi_pipe_bulk_xfer(
11187c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11197c478bd9Sstevel@tonic-gate 				usb_bulk_req_t		*bulk_reqp,
11207c478bd9Sstevel@tonic-gate 				usb_flags_t		usb_flags);
11217c478bd9Sstevel@tonic-gate int		ehci_hcdi_pipe_intr_xfer(
11227c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11237c478bd9Sstevel@tonic-gate 				usb_intr_req_t		*intr_req,
11247c478bd9Sstevel@tonic-gate 				usb_flags_t		usb_flags);
11257c478bd9Sstevel@tonic-gate int		ehci_hcdi_pipe_stop_intr_polling(
11267c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11277c478bd9Sstevel@tonic-gate 				usb_flags_t		usb_flags);
1128fffe0b30Sqz int		ehci_hcdi_get_current_frame_number(
1129fffe0b30Sqz 				usba_device_t		*usba_device,
1130fffe0b30Sqz 				usb_frame_number_t	*frame_number);
1131fffe0b30Sqz int		ehci_hcdi_get_max_isoc_pkts(
1132fffe0b30Sqz 				usba_device_t		*usba_device,
1133fffe0b30Sqz 				uint_t		*max_isoc_pkts_per_request);
11347c478bd9Sstevel@tonic-gate int		ehci_hcdi_pipe_isoc_xfer(
11357c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11367c478bd9Sstevel@tonic-gate 				usb_isoc_req_t		*isoc_reqp,
11377c478bd9Sstevel@tonic-gate 				usb_flags_t		usb_flags);
11387c478bd9Sstevel@tonic-gate int		ehci_hcdi_pipe_stop_isoc_polling(
11397c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11407c478bd9Sstevel@tonic-gate 				usb_flags_t		usb_flags);
11417c478bd9Sstevel@tonic-gate 
11427c478bd9Sstevel@tonic-gate /*
11437c478bd9Sstevel@tonic-gate  * EHCI Polled entry points function prototypes.
11447c478bd9Sstevel@tonic-gate  */
11457c478bd9Sstevel@tonic-gate int		ehci_hcdi_polled_input_init(
11467c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11477c478bd9Sstevel@tonic-gate 				uchar_t			**polled_buf,
11487c478bd9Sstevel@tonic-gate 				usb_console_info_impl_t	*info);
11497c478bd9Sstevel@tonic-gate int		ehci_hcdi_polled_input_enter(
11507c478bd9Sstevel@tonic-gate 				usb_console_info_impl_t	*info);
11517c478bd9Sstevel@tonic-gate int		ehci_hcdi_polled_read(
11527c478bd9Sstevel@tonic-gate 				usb_console_info_impl_t	*info,
11537c478bd9Sstevel@tonic-gate 				uint_t			*num_characters);
11547c478bd9Sstevel@tonic-gate int		ehci_hcdi_polled_input_exit(
11557c478bd9Sstevel@tonic-gate 				usb_console_info_impl_t	*info);
11567c478bd9Sstevel@tonic-gate int		ehci_hcdi_polled_input_fini(
11577c478bd9Sstevel@tonic-gate 				usb_console_info_impl_t	*info);
11589b58c2adSzhigang lu - Sun Microsystems - Beijing China int		ehci_hcdi_polled_output_init(
11599b58c2adSzhigang lu - Sun Microsystems - Beijing China 				usba_pipe_handle_data_t	*ph,
11609b58c2adSzhigang lu - Sun Microsystems - Beijing China 				usb_console_info_impl_t	*console_output_info);
11619b58c2adSzhigang lu - Sun Microsystems - Beijing China int		ehci_hcdi_polled_output_enter(
11629b58c2adSzhigang lu - Sun Microsystems - Beijing China 				usb_console_info_impl_t	*info);
11639b58c2adSzhigang lu - Sun Microsystems - Beijing China int		ehci_hcdi_polled_write(
11649b58c2adSzhigang lu - Sun Microsystems - Beijing China 				usb_console_info_impl_t *info,
11659b58c2adSzhigang lu - Sun Microsystems - Beijing China 				uchar_t *buf,
11669b58c2adSzhigang lu - Sun Microsystems - Beijing China 				uint_t num_characters,
11679b58c2adSzhigang lu - Sun Microsystems - Beijing China 				uint_t *num_characters_written);
11689b58c2adSzhigang lu - Sun Microsystems - Beijing China int		ehci_hcdi_polled_output_exit(
11699b58c2adSzhigang lu - Sun Microsystems - Beijing China 				usb_console_info_impl_t	*info);
11709b58c2adSzhigang lu - Sun Microsystems - Beijing China int		ehci_hcdi_polled_output_fini(
11719b58c2adSzhigang lu - Sun Microsystems - Beijing China 				usb_console_info_impl_t *info);
11727c478bd9Sstevel@tonic-gate /*
11737c478bd9Sstevel@tonic-gate  * EHCI Root Hub entry points function prototypes.
11747c478bd9Sstevel@tonic-gate  */
11757c478bd9Sstevel@tonic-gate int		ehci_init_root_hub(
11767c478bd9Sstevel@tonic-gate 				ehci_state_t		*ehcip);
11777c478bd9Sstevel@tonic-gate int		ehci_load_root_hub_driver(
11787c478bd9Sstevel@tonic-gate 				ehci_state_t		*ehcip);
11797c478bd9Sstevel@tonic-gate int		ehci_unload_root_hub_driver(
11807c478bd9Sstevel@tonic-gate 				ehci_state_t		*ehcip);
11817c478bd9Sstevel@tonic-gate int		ehci_handle_root_hub_pipe_open(
11827c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11837c478bd9Sstevel@tonic-gate 				usb_flags_t		flags);
11847c478bd9Sstevel@tonic-gate int		ehci_handle_root_hub_pipe_close(
11857c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph);
11867c478bd9Sstevel@tonic-gate int		ehci_handle_root_hub_pipe_reset(
11877c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11887c478bd9Sstevel@tonic-gate 				usb_flags_t		flags);
11897c478bd9Sstevel@tonic-gate int		ehci_handle_root_hub_request(
11907c478bd9Sstevel@tonic-gate 				ehci_state_t		*ehcip,
11917c478bd9Sstevel@tonic-gate 				usba_pipe_handle_data_t	*ph,
11927c478bd9Sstevel@tonic-gate 				usb_ctrl_req_t		*ctrl_reqp);
11937c478bd9Sstevel@tonic-gate int		ehci_handle_root_hub_pipe_start_intr_polling(
1194