17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 53304303fSsl * Common Development and Distribution License (the "License"). 63304303fSsl * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22d29f5a71Szhigang lu - Sun Microsystems - Beijing China * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_USB_EHCI_H 277c478bd9Sstevel@tonic-gate #define _SYS_USB_EHCI_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #ifdef __cplusplus 317c478bd9Sstevel@tonic-gate extern "C" { 327c478bd9Sstevel@tonic-gate #endif 337c478bd9Sstevel@tonic-gate 347c478bd9Sstevel@tonic-gate /* 357c478bd9Sstevel@tonic-gate * Enhanced Host Controller Driver (EHCI) 367c478bd9Sstevel@tonic-gate * 377c478bd9Sstevel@tonic-gate * The EHCI driver is a software driver which interfaces to the Universal 387c478bd9Sstevel@tonic-gate * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 397c478bd9Sstevel@tonic-gate * the Host Controller is defined by the EHCI Host Controller Interface. 407c478bd9Sstevel@tonic-gate * 417c478bd9Sstevel@tonic-gate * This header file describes the registers and data structures shared by 427c478bd9Sstevel@tonic-gate * the EHCI USB controller (HC) and the EHCI Driver. 437c478bd9Sstevel@tonic-gate */ 447c478bd9Sstevel@tonic-gate 457c478bd9Sstevel@tonic-gate #include <sys/types.h> 467c478bd9Sstevel@tonic-gate #include <sys/pci.h> 477c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 487c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 497c478bd9Sstevel@tonic-gate #include <sys/ndi_impldefs.h> 507c478bd9Sstevel@tonic-gate #include <sys/disp.h> 517c478bd9Sstevel@tonic-gate 527c478bd9Sstevel@tonic-gate #include <sys/usb/usba.h> 537c478bd9Sstevel@tonic-gate 547c478bd9Sstevel@tonic-gate #include <sys/usb/usba/hcdi.h> 557c478bd9Sstevel@tonic-gate 567c478bd9Sstevel@tonic-gate #include <sys/usb/hubd/hub.h> 577c478bd9Sstevel@tonic-gate #include <sys/usb/usba/hubdi.h> 587c478bd9Sstevel@tonic-gate #include <sys/usb/hubd/hubdvar.h> 597c478bd9Sstevel@tonic-gate 607c478bd9Sstevel@tonic-gate #include <sys/id32.h> 617c478bd9Sstevel@tonic-gate 627c478bd9Sstevel@tonic-gate #define EHCI_MAX_RH_PORTS 31 /* Maximum root hub ports */ 637c478bd9Sstevel@tonic-gate 647c478bd9Sstevel@tonic-gate 657c478bd9Sstevel@tonic-gate /* 667c478bd9Sstevel@tonic-gate * Each EHCI buffer can hold upto 4k bytes of data. Hence there is a 677c478bd9Sstevel@tonic-gate * restriction of 4k alignment while allocating a dma buffer. 687c478bd9Sstevel@tonic-gate */ 697c478bd9Sstevel@tonic-gate #define EHCI_4K_ALIGN 0x1000 707c478bd9Sstevel@tonic-gate 717c478bd9Sstevel@tonic-gate /* 727c478bd9Sstevel@tonic-gate * USB Host controller DMA scatter gather list defines for 737c478bd9Sstevel@tonic-gate * Sparc and non-sparc architectures. 747c478bd9Sstevel@tonic-gate */ 757c478bd9Sstevel@tonic-gate #if defined(__sparc) 767c478bd9Sstevel@tonic-gate #define EHCI_DMA_ATTR_MAX_XFER 0xffffffffull 777c478bd9Sstevel@tonic-gate #define EHCI_DMA_ATTR_COUNT_MAX 0xffffffffull 787c478bd9Sstevel@tonic-gate #define EHCI_DMA_ATTR_GRANULAR 512 797c478bd9Sstevel@tonic-gate #define EHCI_DMA_ATTR_ALIGNMENT EHCI_4K_ALIGN 807c478bd9Sstevel@tonic-gate #else 817c478bd9Sstevel@tonic-gate #define EHCI_DMA_ATTR_MAX_XFER 0x00ffffffull 827c478bd9Sstevel@tonic-gate #define EHCI_DMA_ATTR_COUNT_MAX 0x00ffffffull 837c478bd9Sstevel@tonic-gate #define EHCI_DMA_ATTR_GRANULAR 1 843304303fSsl #define EHCI_DMA_ATTR_ALIGNMENT EHCI_4K_ALIGN 857c478bd9Sstevel@tonic-gate #endif 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate /* Set the default data structure (QTD,QH,SITD,ITD) to a 32 byte alignment */ 887c478bd9Sstevel@tonic-gate #define EHCI_DMA_ATTR_TD_QH_ALIGNMENT 0x0020 897c478bd9Sstevel@tonic-gate #define EHCI_DMA_ATTR_PFL_ALIGNMENT EHCI_4K_ALIGN 907c478bd9Sstevel@tonic-gate 913304303fSsl /* TW scatter/gatter list defines */ 923304303fSsl #define EHCI_DMA_ATTR_TW_SGLLEN 0x7fffffff 933304303fSsl 947c478bd9Sstevel@tonic-gate /* 957c478bd9Sstevel@tonic-gate * EHCI Capability Registers 967c478bd9Sstevel@tonic-gate * 977c478bd9Sstevel@tonic-gate * The registers specify the limits, restrictions and capabilities of the 987c478bd9Sstevel@tonic-gate * specific EHCI Host Controller implementation. 997c478bd9Sstevel@tonic-gate */ 1007c478bd9Sstevel@tonic-gate typedef volatile struct ehci_caps { 1017c478bd9Sstevel@tonic-gate uint8_t ehci_caps_length; /* Capability register length */ 1027c478bd9Sstevel@tonic-gate uint8_t ehci_pad; /* Reserved */ 1037c478bd9Sstevel@tonic-gate uint16_t ehci_version; /* Interface version number */ 1047c478bd9Sstevel@tonic-gate uint32_t ehci_hcs_params; /* Structural paramters */ 1057c478bd9Sstevel@tonic-gate uint32_t ehci_hcc_params; /* Capability paramters */ 1067c478bd9Sstevel@tonic-gate uint8_t ehci_port_route[8]; /* Companion port route */ 1077c478bd9Sstevel@tonic-gate } ehci_caps_t; 1087c478bd9Sstevel@tonic-gate 1097c478bd9Sstevel@tonic-gate /* 1107c478bd9Sstevel@tonic-gate * EHCI revision 1117c478bd9Sstevel@tonic-gate * 1127c478bd9Sstevel@tonic-gate * EHCI driver supports EHCI host controllers compliant to 0.95 and higher 1137c478bd9Sstevel@tonic-gate * revisions of EHCI specifications. 1147c478bd9Sstevel@tonic-gate */ 1157c478bd9Sstevel@tonic-gate #define EHCI_REVISION_0_95 0x95 /* Revision 0.95 */ 1167c478bd9Sstevel@tonic-gate 1177c478bd9Sstevel@tonic-gate /* EHCI HCS Params Register Bits */ 1187c478bd9Sstevel@tonic-gate #define EHCI_HCS_PORT_INDICATOR 0x00010000 /* Port indicator control */ 1197c478bd9Sstevel@tonic-gate #define EHCI_HCS_NUM_COMP_CTRLS 0x0000F000 /* No of companion ctrls */ 1207c478bd9Sstevel@tonic-gate #define EHCI_HCS_NUM_COMP_CTRL_SHIFT 12 1217c478bd9Sstevel@tonic-gate #define EHCI_HCS_NUM_PORTS_CC 0x00000F00 /* Ports per classic ctrls */ 1227c478bd9Sstevel@tonic-gate #define EHCI_HCS_NUM_PORTS_CC_SHIFT 8 1237c478bd9Sstevel@tonic-gate #define EHCI_HCS_PORT_ROUTING_RULES 0x00000080 /* Port routing rules */ 1247c478bd9Sstevel@tonic-gate #define EHCI_HCS_PORT_POWER_CONTROL 0x00000010 /* Port power control */ 1257c478bd9Sstevel@tonic-gate #define EHCI_HCS_NUM_PORTS 0x0000000F /* No of root hub ports */ 1267c478bd9Sstevel@tonic-gate 1277c478bd9Sstevel@tonic-gate /* EHCI HCC Params Register Bits */ 1287c478bd9Sstevel@tonic-gate #define EHCI_HCC_EECP 0x0000FF00 /* Extended capbilities */ 1297c478bd9Sstevel@tonic-gate #define EHCI_HCC_EECP_SHIFT 8 1307c478bd9Sstevel@tonic-gate #define EHCI_HCC_EECP_MIN_OFFSET 0x00000040 /* Minimum valid offset */ 1317c478bd9Sstevel@tonic-gate #define EHCI_HCC_ISOCH_SCHED_THRESHOLD 0x000000F0 /* Isoch sched threshold */ 1327c478bd9Sstevel@tonic-gate #define EHCI_HCC_ASYNC_SCHED_PARK_CAP 0x00000004 /* Async schedule park cap */ 1337c478bd9Sstevel@tonic-gate #define EHCI_HCC_PROG_FRAME_LIST_FLAG 0x00000002 /* Prog frame list flag */ 1347c478bd9Sstevel@tonic-gate #define EHCI_HCC_64BIT_ADDR_CAP 0x00000001 /* 64bit addr capability */ 1357c478bd9Sstevel@tonic-gate 1367c478bd9Sstevel@tonic-gate /* EHCI Port Route Register Bits */ 1377c478bd9Sstevel@tonic-gate #define EHCI_PORT_ROUTE_EVEN 0x0F /* Classic even port route */ 1387c478bd9Sstevel@tonic-gate #define EHCI_PORT_ROUTE_ODD 0xF0 /* Classic odd port route */ 1397c478bd9Sstevel@tonic-gate #define EHCI_PORT_ROUTE_ODD_SHIFT 4 1407c478bd9Sstevel@tonic-gate 1417c478bd9Sstevel@tonic-gate 1427c478bd9Sstevel@tonic-gate /* 1437c478bd9Sstevel@tonic-gate * EHCI Operational Registers 1447c478bd9Sstevel@tonic-gate * 1457c478bd9Sstevel@tonic-gate * The EHCI Host Controller contains a set of on-chip operational registers 1467c478bd9Sstevel@tonic-gate * which are mapped into a non-cacheable portion of the system addressable 1477c478bd9Sstevel@tonic-gate * space. These registers are also used by the EHCI Host Controller Driver. 1487c478bd9Sstevel@tonic-gate * This structure must be aligned to 32 byte boundary. 1497c478bd9Sstevel@tonic-gate */ 1507c478bd9Sstevel@tonic-gate typedef volatile struct ehci_regs { 1517c478bd9Sstevel@tonic-gate /* Control and status registers */ 1527c478bd9Sstevel@tonic-gate uint32_t ehci_command; /* USB commands */ 1537c478bd9Sstevel@tonic-gate uint32_t ehci_status; /* USB status */ 1547c478bd9Sstevel@tonic-gate uint32_t ehci_interrupt; /* Interrupt enable */ 1557c478bd9Sstevel@tonic-gate uint32_t ehci_frame_index; /* Frame index */ 1567c478bd9Sstevel@tonic-gate 1577c478bd9Sstevel@tonic-gate /* Memory pointer registers */ 1587c478bd9Sstevel@tonic-gate uint32_t ehci_ctrl_segment; /* Control data segment */ 1597c478bd9Sstevel@tonic-gate uint32_t ehci_periodic_list_base; /* Period frm list base addr */ 1607c478bd9Sstevel@tonic-gate uint32_t ehci_async_list_addr; /* Async list base address */ 1617c478bd9Sstevel@tonic-gate uint32_t ehci_pad[9]; /* Head of the bulk list */ 1627c478bd9Sstevel@tonic-gate 1637c478bd9Sstevel@tonic-gate /* Root hub registers */ 1647c478bd9Sstevel@tonic-gate uint32_t ehci_config_flag; /* Config Flag */ 1657c478bd9Sstevel@tonic-gate uint32_t ehci_rh_port_status[EHCI_MAX_RH_PORTS]; 1667c478bd9Sstevel@tonic-gate /* Root hub port status and control information */ 1677c478bd9Sstevel@tonic-gate } ehci_regs_t; 1687c478bd9Sstevel@tonic-gate 1697c478bd9Sstevel@tonic-gate /* EHCI Command Register Bits */ 1707c478bd9Sstevel@tonic-gate #define EHCI_CMD_INTR_THRESHOLD 0x00FF0000 /* Intr threshold control */ 1717c478bd9Sstevel@tonic-gate #define EHCI_CMD_INTR_SHIFT 16 1727c478bd9Sstevel@tonic-gate #define EHCI_CMD_01_INTR 0x00010000 /* 01 micro-frame */ 1737c478bd9Sstevel@tonic-gate #define EHCI_CMD_02_INTR 0x00020000 /* 02 micro-frames */ 1747c478bd9Sstevel@tonic-gate #define EHCI_CMD_04_INTR 0x00040000 /* 04 micro-frames */ 1757c478bd9Sstevel@tonic-gate #define EHCI_CMD_08_INTR 0x00080000 /* 08 micro-frames */ 1767c478bd9Sstevel@tonic-gate #define EHCI_CMD_16_INTR 0x00100000 /* 16 micro-frames */ 1777c478bd9Sstevel@tonic-gate #define EHCI_CMD_32_INTR 0x00200000 /* 32 micro-frames */ 1787c478bd9Sstevel@tonic-gate #define EHCI_CMD_64_INTR 0x00400000 /* 64 micro-frames */ 1797c478bd9Sstevel@tonic-gate 1807c478bd9Sstevel@tonic-gate #define EHCI_CMD_ASYNC_PARK_ENABLE 0x00000800 /* Async sched park enable */ 1817c478bd9Sstevel@tonic-gate #define EHCI_CMD_ASYNC_PARK_COUNT 0x00000300 /* Async sched park count */ 1827c478bd9Sstevel@tonic-gate #define EHCI_CMD_ASYNC_PARK_COUNT_1 0x00000100 /* Async sched park cnt 1 */ 1837c478bd9Sstevel@tonic-gate #define EHCI_CMD_ASYNC_PARK_COUNT_2 0x00000200 /* Async sched park cnt 2 */ 1847c478bd9Sstevel@tonic-gate #define EHCI_CMD_ASYNC_PARK_COUNT_3 0x00000300 /* Async sched park cnt 3 */ 1857c478bd9Sstevel@tonic-gate #define EHCI_CMD_ASYNC_PARK_SHIFT 8 1867c478bd9Sstevel@tonic-gate #define EHCI_CMD_LIGHT_HC_RESET 0x00000080 /* Light host ctrl reset */ 1877c478bd9Sstevel@tonic-gate #define EHCI_CMD_INTR_ON_ASYNC_ADVANCE 0x00000040 /* Async advance doorbell */ 1887c478bd9Sstevel@tonic-gate #define EHCI_CMD_ASYNC_SCHED_ENABLE 0x00000020 /* Async schedule enable */ 1897c478bd9Sstevel@tonic-gate #define EHCI_CMD_PERIODIC_SCHED_ENABLE 0x00000010 /* Periodic sched enable */ 1907c478bd9Sstevel@tonic-gate #define EHCI_CMD_FRAME_LIST_SIZE 0x0000000C /* Frame list size */ 1917c478bd9Sstevel@tonic-gate #define EHCI_CMD_FRAME_LIST_SIZE_SHIFT 2 1927c478bd9Sstevel@tonic-gate #define EHCI_CMD_FRAME_1024_SIZE 0x00000000 /* 1024 frame list size */ 1937c478bd9Sstevel@tonic-gate #define EHCI_CMD_FRAME_512_SIZE 0x00000004 /* 512 frame list size */ 1947c478bd9Sstevel@tonic-gate #define EHCI_CMD_FRAME_256_SIZE 0X00000008 /* 256 frame list size */ 1957c478bd9Sstevel@tonic-gate #define EHCI_CMD_HOST_CTRL_RESET 0x00000002 /* Host controller reset */ 1967c478bd9Sstevel@tonic-gate #define EHCI_CMD_HOST_CTRL_RS 0x00000001 /* Host ctrl run or stop */ 1977c478bd9Sstevel@tonic-gate #define EHCI_CMD_HOST_CTRL_RUN 0x00000001 /* Host controller run */ 1987c478bd9Sstevel@tonic-gate #define EHCI_CMD_HOST_CTRL_STOP 0x00000000 /* Host controller stop */ 1997c478bd9Sstevel@tonic-gate 2007c478bd9Sstevel@tonic-gate /* EHCI Status Register Bits */ 2017c478bd9Sstevel@tonic-gate #define EHCI_STS_ASYNC_SCHED_STATUS 0x00008000 /* Async schedule status */ 2027c478bd9Sstevel@tonic-gate #define EHCI_STS_PERIODIC_SCHED_STATUS 0x00004000 /* Periodic sched status */ 2037c478bd9Sstevel@tonic-gate #define EHCI_STS_EMPTY_ASYNC_SCHEDULE 0x00002000 /* Empty async schedule */ 2047c478bd9Sstevel@tonic-gate #define EHCI_STS_HOST_CTRL_HALTED 0x00001000 /* Host controller Halted */ 2057c478bd9Sstevel@tonic-gate #define EHCI_STS_ASYNC_ADVANCE_INTR 0x00000020 /* Intr on async advance */ 2067c478bd9Sstevel@tonic-gate #define EHCI_STS_HOST_SYSTEM_ERROR_INTR 0x00000010 /* Host system error */ 2077c478bd9Sstevel@tonic-gate #define EHCI_STS_FRM_LIST_ROLLOVER_INTR 0x00000008 /* Frame list rollover */ 2087c478bd9Sstevel@tonic-gate #define EHCI_STS_RH_PORT_CHANGE_INTR 0x00000004 /* Port change detect */ 2097c478bd9Sstevel@tonic-gate #define EHCI_STS_USB_ERROR_INTR 0x00000002 /* USB error interrupt */ 2107c478bd9Sstevel@tonic-gate #define EHCI_STS_USB_INTR 0x00000001 /* USB interrupt */ 2117c478bd9Sstevel@tonic-gate 2127c478bd9Sstevel@tonic-gate /* EHCI Interrupt Register Bits */ 2137c478bd9Sstevel@tonic-gate #define EHCI_INTR_ASYNC_ADVANCE 0x00000020 /* Async advance interrupt */ 2147c478bd9Sstevel@tonic-gate #define EHCI_INTR_HOST_SYSTEM_ERROR 0x00000010 /* Host system error intr */ 2157c478bd9Sstevel@tonic-gate #define EHCI_INTR_FRAME_LIST_ROLLOVER 0x00000008 /* Framelist rollover intr */ 2167c478bd9Sstevel@tonic-gate #define EHCI_INTR_RH_PORT_CHANGE 0x00000004 /* Port change interrupt */ 2177c478bd9Sstevel@tonic-gate #define EHCI_INTR_USB_ERROR 0x00000002 /* USB error interrupt */ 2187c478bd9Sstevel@tonic-gate #define EHCI_INTR_USB 0x00000001 /* USB interrupt */ 2197c478bd9Sstevel@tonic-gate 2207c478bd9Sstevel@tonic-gate /* EHCI Frame Index Register Bits */ 2217c478bd9Sstevel@tonic-gate #define EHCI_FRAME_INDEX 0x00003FFF /* Frame index */ 2227c478bd9Sstevel@tonic-gate #define EHCI_FRAME_1024 0x00003FFF /* 1024 elements */ 2237c478bd9Sstevel@tonic-gate #define EHCI_FRAME_0512 0x00001FFF /* 512 elements */ 2247c478bd9Sstevel@tonic-gate #define EHCI_FRAME_0256 0x00000FFF /* 256 elements */ 2257c478bd9Sstevel@tonic-gate 2267c478bd9Sstevel@tonic-gate /* EHCI Control Data Structure Segment Register Bits */ 2277c478bd9Sstevel@tonic-gate /* Most significant 32 bits for all EHCI data structures in 64bit addressing */ 2287c478bd9Sstevel@tonic-gate #define EHCI_CTRLD_SEGMENT 0xFFFFFFFF /* Control data segment */ 2297c478bd9Sstevel@tonic-gate 2307c478bd9Sstevel@tonic-gate /* EHCI Periodic Frame List Base Address Register Bits */ 2317c478bd9Sstevel@tonic-gate #define EHCI_PERIODIC_LIST_BASE 0xFFFFF000 /* Periodic framelist addr */ 2327c478bd9Sstevel@tonic-gate #define EHCI_PERIODIC_LIST_BASE_SHIFT 12 2337c478bd9Sstevel@tonic-gate 2347c478bd9Sstevel@tonic-gate /* EHCI Asynchronous List Address Register Bits */ 2357c478bd9Sstevel@tonic-gate #define EHCI_ASYNC_LIST_ADDR 0xFFFFFFE0 /* Async list address */ 2367c478bd9Sstevel@tonic-gate #define EHCI_ASYNC_LIST_ADDR_SHIFT 5 2377c478bd9Sstevel@tonic-gate 2387c478bd9Sstevel@tonic-gate /* EHCI Config Flag Register Bits */ 2397c478bd9Sstevel@tonic-gate #define EHCI_CONFIG_FLAG 0x00000001 /* Route host controllers */ 2407c478bd9Sstevel@tonic-gate #define EHCI_CONFIG_FLAG_CLASSIC 0x00000000 /* Route to Classic ctrl */ 2417c478bd9Sstevel@tonic-gate #define EHCI_CONFIG_FLAG_EHCI 0x00000001 /* Route to EHCI ctrl */ 2427c478bd9Sstevel@tonic-gate 2437c478bd9Sstevel@tonic-gate /* EHCI Root Hub Port Status and Control Register Bits */ 2447c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_OVER_CURENT_ENABLE 0x00400000 /* Over current enable */ 2457c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_DISCONNECT_ENABLE 0x00200000 /* Disconnect enable */ 2467c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_CONNECT_ENABLE 0x00100000 /* Connect enable */ 2477c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_INDICATOR 0x0000C000 /* Port indicator control */ 2487c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_IND_SHIFT 14 2497c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_IND_OFF 0x00000000 /* Port indicators off */ 2507c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_IND_AMBER 0x00004000 /* Amber port indicator */ 2517c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_IND_GREEN 0x00008000 /* Green port indicator */ 2527c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_OWNER 0x00002000 /* Port ownership */ 2537c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_OWNER_CLASSIC 0x00002000 /* Classic port ownership */ 2547c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_OWNER_EHCI 0x00000000 /* EHCI port ownership */ 2557c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_POWER 0x00001000 /* Port power */ 2567c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_LINE_STATUS 0x00000C00 /* USB speed line status */ 2577c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_LOW_SPEED 0x00000400 /* Low speed */ 2587c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_RESET 0x00000100 /* Port reset */ 2597c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_SUSPEND 0x00000080 /* Port suspend */ 2607c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_RESUME 0x00000040 /* Port resume */ 2617c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_OVER_CURR_CHANGE 0x00000020 /* Over current change */ 2627c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_OVER_CURR_ACTIVE 0x00000010 /* Over current active */ 2637c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_ENABLE_CHANGE 0x00000008 /* Port enable change */ 2647c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_ENABLE 0x00000004 /* Port enable */ 2657c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_CONNECT_STS_CHANGE 0x00000002 /* Connect status change */ 2667c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_CONNECT_STATUS 0x00000001 /* Connect status */ 2677c478bd9Sstevel@tonic-gate 2687c478bd9Sstevel@tonic-gate /* Root hub port change bits mask */ 2697c478bd9Sstevel@tonic-gate #define EHCI_RH_PORT_CLEAR_MASK 0x0000002A /* Clear bits mask */ 2707c478bd9Sstevel@tonic-gate 2717c478bd9Sstevel@tonic-gate 2727c478bd9Sstevel@tonic-gate /* 2737c478bd9Sstevel@tonic-gate * EHCI Extended Capability Registers 2747c478bd9Sstevel@tonic-gate * 2757c478bd9Sstevel@tonic-gate * Currently this register only specifies BIOS handoff information. 2767c478bd9Sstevel@tonic-gate */ 2777c478bd9Sstevel@tonic-gate #define EHCI_EX_CAP_SPECIFICS 0xFFFF0000 2787c478bd9Sstevel@tonic-gate #define EHCI_EX_CAP_SPECIFICS_SHIFT 16 2797c478bd9Sstevel@tonic-gate #define EHCI_EX_CAP_NEXT_PTR 0x0000FF00 2807c478bd9Sstevel@tonic-gate #define EHCI_EX_CAP_NEXT_PTR_SHIFT 8 2817c478bd9Sstevel@tonic-gate #define EHCI_EX_CAP_ID 0x000000FF 2827c478bd9Sstevel@tonic-gate #define EHCI_EX_CAP_ID_SHIFT 0 283*9a48f6c4SRobert Mustacchi #define EHCI_EX_CAP_ID_RESERVED 0 2847c478bd9Sstevel@tonic-gate #define EHCI_EX_CAP_ID_BIOS_HANDOFF 1 2857c478bd9Sstevel@tonic-gate 2867c478bd9Sstevel@tonic-gate #define EHCI_LEGSUP_OS_OWNED_SEM 0x01000000 2877c478bd9Sstevel@tonic-gate #define EHCI_LEGSUP_BIOS_OWNED_SEM 0x00010000 2887c478bd9Sstevel@tonic-gate 2897c478bd9Sstevel@tonic-gate 2907c478bd9Sstevel@tonic-gate /* 2917c478bd9Sstevel@tonic-gate * Host Controller Periodic Frame List Area 2927c478bd9Sstevel@tonic-gate * 2937c478bd9Sstevel@tonic-gate * The Host Controller Periodic Frame List Area is a 4K structre of system 2947c478bd9Sstevel@tonic-gate * memory that is established by the Host Controller Driver (HCD) and this 2957c478bd9Sstevel@tonic-gate * structre is used for communication between HCD and HC. The HCD maintains 2967c478bd9Sstevel@tonic-gate * a pointer to this structure in the Host Controller (HC). This structure 2977c478bd9Sstevel@tonic-gate * must be aligned to a 4K boundary. There are 1024 periodic frame list 2987c478bd9Sstevel@tonic-gate * entries. 2997c478bd9Sstevel@tonic-gate */ 3007c478bd9Sstevel@tonic-gate 3017c478bd9Sstevel@tonic-gate #define EHCI_NUM_INTR_QH_LISTS 32 /* No of intr lists */ 3027c478bd9Sstevel@tonic-gate #define EHCI_NUM_STATIC_NODES 63 /* No of static QHs */ 3037c478bd9Sstevel@tonic-gate #define EHCI_NUM_PERIODIC_FRAME_LISTS 1024 /* No of entries */ 3047c478bd9Sstevel@tonic-gate 3057c478bd9Sstevel@tonic-gate typedef volatile struct ehci_periodic_frame_list { 3067c478bd9Sstevel@tonic-gate uint32_t ehci_periodic_frame_list_table[ 3077c478bd9Sstevel@tonic-gate EHCI_NUM_PERIODIC_FRAME_LISTS]; /* 1024 lists */ 3087c478bd9Sstevel@tonic-gate } ehci_periodic_frame_list_t; 3097c478bd9Sstevel@tonic-gate 3107c478bd9Sstevel@tonic-gate 3117c478bd9Sstevel@tonic-gate /* 3127c478bd9Sstevel@tonic-gate * Host Controller Queue Head 3137c478bd9Sstevel@tonic-gate * 3147c478bd9Sstevel@tonic-gate * An Queue Head (QH) is a memory structure that describes the information 3157c478bd9Sstevel@tonic-gate * necessary for the Host Controller to communicate with a device endpoint 3167c478bd9Sstevel@tonic-gate * except High Speed and Full Speed Isochronous's endpoints. An QH includes 3177c478bd9Sstevel@tonic-gate * a Queue Element Transfer Descriptor (QTD) pointer. This structure must 3187c478bd9Sstevel@tonic-gate * be aligned to a 32 byte boundary. 3197c478bd9Sstevel@tonic-gate */ 3207c478bd9Sstevel@tonic-gate typedef volatile struct ehci_qh { 3217c478bd9Sstevel@tonic-gate /* Endpoint capabilities or characteristics */ 3227c478bd9Sstevel@tonic-gate uint32_t qh_link_ptr; /* Next QH or ITD or SITD */ 3237c478bd9Sstevel@tonic-gate uint32_t qh_ctrl; /* Generic control information */ 3247c478bd9Sstevel@tonic-gate uint32_t qh_split_ctrl; /* Split transaction control info */ 3257c478bd9Sstevel@tonic-gate uint32_t qh_curr_qtd; /* Current QTD */ 3267c478bd9Sstevel@tonic-gate 3277c478bd9Sstevel@tonic-gate /* Tranfer overlay */ 3287c478bd9Sstevel@tonic-gate uint32_t qh_next_qtd; /* Next QTD */ 3297c478bd9Sstevel@tonic-gate uint32_t qh_alt_next_qtd; /* Next alternate QTD */ 3307c478bd9Sstevel@tonic-gate uint32_t qh_status; /* Status of current QTD */ 3317c478bd9Sstevel@tonic-gate uint32_t qh_buf[5]; /* Buffer pointers */ 3327c478bd9Sstevel@tonic-gate uint32_t qh_buf_high[5]; /* For 64 bit addressing */ 3337c478bd9Sstevel@tonic-gate 3347c478bd9Sstevel@tonic-gate /* HCD private fields */ 3357c478bd9Sstevel@tonic-gate uint32_t qh_dummy_qtd; /* Current dummy qtd */ 3367c478bd9Sstevel@tonic-gate uint32_t qh_prev; /* Prevous QH */ 3377c478bd9Sstevel@tonic-gate uint32_t qh_state; /* QH's state */ 3387c478bd9Sstevel@tonic-gate uint32_t qh_reclaim_next; /* Next QH on reclaim list */ 3397c478bd9Sstevel@tonic-gate uint32_t qh_reclaim_frame; /* Reclaim usb frame number */ 3407c478bd9Sstevel@tonic-gate uint8_t qh_pad[8]; /* Required padding */ 3417c478bd9Sstevel@tonic-gate } ehci_qh_t; 3427c478bd9Sstevel@tonic-gate 3437c478bd9Sstevel@tonic-gate /* 3447c478bd9Sstevel@tonic-gate * qh_link_ptr control bits. 3457c478bd9Sstevel@tonic-gate */ 3467c478bd9Sstevel@tonic-gate #define EHCI_QH_LINK_PTR 0xFFFFFFE0 /* QH link ptr mask */ 3477c478bd9Sstevel@tonic-gate #define EHCI_QH_LINK_REF 0x00000006 /* Ref to QH/ITD/SITD */ 3487c478bd9Sstevel@tonic-gate #define EHCI_QH_LINK_REF_ITD 0x00000000 /* Isoch QTD pointer */ 3497c478bd9Sstevel@tonic-gate #define EHCI_QH_LINK_REF_QH 0x00000002 /* QH pointer */ 3507c478bd9Sstevel@tonic-gate #define EHCI_QH_LINK_REF_SITD 0x00000004 /* SIQTD pointer */ 3517c478bd9Sstevel@tonic-gate #define EHCI_QH_LINK_REF_FSTN 0x00000006 /* FSTN pointer */ 3527c478bd9Sstevel@tonic-gate #define EHCI_QH_LINK_PTR_VALID 0x00000001 /* Link ptr validity */ 3537c478bd9Sstevel@tonic-gate 3547c478bd9Sstevel@tonic-gate /* 3557c478bd9Sstevel@tonic-gate * qh_ctrl control bits. 3567c478bd9Sstevel@tonic-gate */ 3577c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_NC_RL 0xF0000000 /* Nak count reload */ 3587c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_NC_RL_SHIFT 28 /* NC reload shift */ 3597c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_MAX_NC 0xF0000000 /* Max Nak counts */ 3607c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_CONTROL_ED_FLAG 0x08000000 /* Ctrl endpoint flag */ 3617c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_MAXPKTSZ 0x07FF0000 /* Max packet length */ 3627c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_MAXPKTSZ_SHIFT 16 /* Max packet shift */ 3637c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_RECLAIM_HEAD 0x00008000 /* Head reclaim list */ 3647c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_DATA_TOGGLE 0x00004000 /* Data toggle */ 3657c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_ED_SPEED 0x00003000 /* Endpoint speed */ 3667c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_ED_FULL_SPEED 0x00000000 /* FullSpeed endpoint */ 3677c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_ED_LOW_SPEED 0x00001000 /* LowSpeed endpoint */ 3687c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_ED_HIGH_SPEED 0x00002000 /* HighSpeed endpoint */ 3697c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_ED_SPEED_SHIFT 12 /* ED speed shift */ 3707c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_ED_NUMBER 0x00000F00 /* Endpoint number */ 3717c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_ED_NUMBER_SHIFT 8 /* ED number shift */ 3727c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_ED_INACTIVATE 0x00000080 /* Inctivate endpoint */ 3737c478bd9Sstevel@tonic-gate #define EHCI_QH_CTRL_DEVICE_ADDRESS 0x0000007F /* Device address */ 3747c478bd9Sstevel@tonic-gate 3757c478bd9Sstevel@tonic-gate /* 3767c478bd9Sstevel@tonic-gate * q_split_ctrl control bits. 3777c478bd9Sstevel@tonic-gate */ 3787c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_MULT 0xC0000000 /* HB multiplier */ 3797c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_MULT_SHIFT 30 /* HB mult Shift */ 3807c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_1_XACTS 0x40000000 /* 1 Xacts per uFrame */ 3817c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_2_XACTS 0x80000000 /* 2 Xacts per uFrame */ 3827c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_3_XACTS 0xC0000000 /* 3 Xacts per uFrame */ 3837c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_HUB_PORT 0x3F800000 /* HS hub port number */ 3847c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_HUB_PORT_SHIFT 23 /* HS hubport no shft */ 3857c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_HUB_ADDR 0x007F0000 /* HS hub address */ 3867c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_HUB_ADDR_SHIFT 16 /* HS hub addr mask */ 3877c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_COMP_MASK 0x0000FF00 /* Split comp mask */ 3887c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_COMP_SHIFT 8 /* Split comp shift */ 3897c478bd9Sstevel@tonic-gate #define EHCI_QH_SPLIT_CTRL_INTR_MASK 0x000000FF /* Intr schedule mask */ 3907c478bd9Sstevel@tonic-gate 3917c478bd9Sstevel@tonic-gate /* 3927c478bd9Sstevel@tonic-gate * qh_curr_qtd control bits. 3937c478bd9Sstevel@tonic-gate */ 3947c478bd9Sstevel@tonic-gate #define EHCI_QH_CURR_QTD_PTR 0xFFFFFFE0 /* Curr element QTD */ 3957c478bd9Sstevel@tonic-gate 3967c478bd9Sstevel@tonic-gate /* 3977c478bd9Sstevel@tonic-gate * qh_next_qtd control bits. 3987c478bd9Sstevel@tonic-gate */ 3997c478bd9Sstevel@tonic-gate #define EHCI_QH_NEXT_QTD_PTR 0xFFFFFFE0 /* Next QTD */ 4007c478bd9Sstevel@tonic-gate #define EHCI_QH_NEXT_QTD_PTR_VALID 0x00000001 /* Next QTD validity */ 4017c478bd9Sstevel@tonic-gate 4027c478bd9Sstevel@tonic-gate /* 4037c478bd9Sstevel@tonic-gate * qh_alt_next_qtd control bits. 4047c478bd9Sstevel@tonic-gate */ 4057c478bd9Sstevel@tonic-gate #define EHCI_QH_ALT_NEXT_QTD_PTR 0xFFFFFFE0 /* Alternate next QTD */ 4067c478bd9Sstevel@tonic-gate #define EHCI_QH_ALT_NEXT_QTD_PTR_VALID 0x00000001 /* Alt QTD validity */ 4077c478bd9Sstevel@tonic-gate #define EHCI_QH_ALT_NEXT_QTD_NAKCNT 0x0000001E /* NAK counter */ 4087c478bd9Sstevel@tonic-gate 4097c478bd9Sstevel@tonic-gate /* 4107c478bd9Sstevel@tonic-gate * qh_status control bits. 4117c478bd9Sstevel@tonic-gate */ 4127c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_DATA_TOGGLE 0x80000000 /* Data toggle */ 4137c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_BYTES_TO_XFER 0x7FFF0000 /* Bytes to transfer */ 4147c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_BYTES_TO_XFER_SHIFT 16 /* Bytes to xfer mask */ 4157c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_INTR_ON_COMPLETE 0x00008000 /* Intr on complete */ 4167c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_C_PAGE 0x00007000 /* C page */ 4177c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_ERROR_COUNTER 0x00000C00 /* Error counter */ 4187c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_ERROR_COUNT_MASK 0x00000C00 /* Error count mask */ 4197c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_PID_CODE 0x00000300 /* PID code */ 4207c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_XACT_STATUS 0x000000FF /* Xact Status */ 4217c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_HS_XACT_STATUS 0x000000F8 /* HS Xact status */ 4227c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_NON_HS_XACT_STATUS 0x000000FD /* Non HS Xact status */ 4237c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_NO_ERROR 0x00000000 /* No error */ 4247c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_ACTIVE 0x00000080 /* Active */ 4257c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_HALTED 0x00000040 /* Halted */ 4267c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_DATA_BUFFER_ERR 0x00000020 /* Data buffer error */ 4277c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_BABBLE_DETECTED 0x00000010 /* Babble detected */ 4287c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_XACT_ERROR 0x00000008 /* Transaction error */ 4297c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_MISSED_uFRAME 0x00000004 /* Missed micro frame */ 4307c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_SPLIT_XSTATE 0x00000002 /* Split xact state */ 4317c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_DO_START_SPLIT 0x00000000 /* Do start split */ 4327c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_DO_COMPLETE_SPLIT 0x00000002 /* Do complete split */ 4337c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_PING_STATE 0x00000001 /* Ping state */ 4347c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_DO_OUT 0x00000000 /* Do OUT */ 4357c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_DO_PING 0x00000001 /* Do PING */ 4367c478bd9Sstevel@tonic-gate #define EHCI_QH_STS_PRD_SPLIT_XACT_ERR 0x00000001 /* Periodic split err */ 4377c478bd9Sstevel@tonic-gate 4387c478bd9Sstevel@tonic-gate /* 4397c478bd9Sstevel@tonic-gate * qh_buf[X] control bits. 4407c478bd9Sstevel@tonic-gate */ 4417c478bd9Sstevel@tonic-gate #define EHCI_QH_BUF_PTR 0xFFFFF000 /* Buffer pointer */ 4427c478bd9Sstevel@tonic-gate #define EHCI_QH_BUF_CURR_OFFSET 0x00000FFF /* Current offset */ 4437c478bd9Sstevel@tonic-gate #define EHCI_QH_BUF_CPROG_MASK 0x000000FF /* Split progress */ 4447c478bd9Sstevel@tonic-gate #define EHCI_QH_BUF_SBYTES 0x00000FE0 /* Software S bytes */ 4457c478bd9Sstevel@tonic-gate #define EHCI_QH_BUF_FRAME_TAG 0x0000001F /* Split xct frametag */ 4467c478bd9Sstevel@tonic-gate 4477c478bd9Sstevel@tonic-gate /* 4487c478bd9Sstevel@tonic-gate * qh_buf_high[X] control bits. 4497c478bd9Sstevel@tonic-gate */ 4507c478bd9Sstevel@tonic-gate #define EHCI_QH_BUF_HIGH_PTR 0xFFFFFFFF /* For 64 addressing */ 4517c478bd9Sstevel@tonic-gate 4527c478bd9Sstevel@tonic-gate /* 4537c478bd9Sstevel@tonic-gate * qh_state 4547c478bd9Sstevel@tonic-gate * 4557c478bd9Sstevel@tonic-gate * QH States 4567c478bd9Sstevel@tonic-gate */ 4577c478bd9Sstevel@tonic-gate #define EHCI_QH_FREE 1 /* Free QH */ 4587c478bd9Sstevel@tonic-gate #define EHCI_QH_STATIC 2 /* Static QH */ 4597c478bd9Sstevel@tonic-gate #define EHCI_QH_ACTIVE 3 /* Active QH */ 4607c478bd9Sstevel@tonic-gate 4617c478bd9Sstevel@tonic-gate 4627c478bd9Sstevel@tonic-gate /* 4637c478bd9Sstevel@tonic-gate * Host Controller Queue Element Transfer Descriptor 4647c478bd9Sstevel@tonic-gate * 4657c478bd9Sstevel@tonic-gate * A Queue Element Transfer Descriptor (QTD) is a memory structure that 4667c478bd9Sstevel@tonic-gate * describes the information necessary for the Host Controller (HC) to 4677c478bd9Sstevel@tonic-gate * transfer a block of data to or from a device endpoint except High 4687c478bd9Sstevel@tonic-gate * Speed and Full Speed Isochronous's endpoints. These QTD's will be 4697c478bd9Sstevel@tonic-gate * attached to a Queue Head (QH). This structure must be aligned to a 4707c478bd9Sstevel@tonic-gate * 32 byte boundary. 4717c478bd9Sstevel@tonic-gate */ 4727c478bd9Sstevel@tonic-gate typedef volatile struct ehci_qtd { 4737c478bd9Sstevel@tonic-gate uint32_t qtd_next_qtd; /* Next QTD */ 4747c478bd9Sstevel@tonic-gate uint32_t qtd_alt_next_qtd; /* Next alternate QTD */ 4757c478bd9Sstevel@tonic-gate uint32_t qtd_ctrl; /* Control information */ 4767c478bd9Sstevel@tonic-gate uint32_t qtd_buf[5]; /* Buffer pointers */ 4777c478bd9Sstevel@tonic-gate uint32_t qtd_buf_high[5]; /* For 64 bit addressing */ 4787c478bd9Sstevel@tonic-gate 4797c478bd9Sstevel@tonic-gate /* HCD private fields */ 4807c478bd9Sstevel@tonic-gate uint32_t qtd_trans_wrapper; /* Transfer wrapper */ 4817c478bd9Sstevel@tonic-gate uint32_t qtd_tw_next_qtd; /* Next qtd on TW */ 4827c478bd9Sstevel@tonic-gate uint32_t qtd_active_qtd_next; /* Next QTD on active list */ 4837c478bd9Sstevel@tonic-gate uint32_t qtd_active_qtd_prev; /* Prev QTD on active list */ 4847c478bd9Sstevel@tonic-gate uint32_t qtd_state; /* QTD state */ 4857c478bd9Sstevel@tonic-gate uint32_t qtd_ctrl_phase; /* Control xfer phase info */ 4863304303fSsl uint32_t qtd_xfer_offs; /* Starting buffer offset */ 4877c478bd9Sstevel@tonic-gate uint32_t qtd_xfer_len; /* Transfer length */ 4887c478bd9Sstevel@tonic-gate uint8_t qtd_pad[12]; /* Required padding */ 4897c478bd9Sstevel@tonic-gate } ehci_qtd_t; 4907c478bd9Sstevel@tonic-gate 4917c478bd9Sstevel@tonic-gate /* 4927c478bd9Sstevel@tonic-gate * qtd_next_qtd control bits. 4937c478bd9Sstevel@tonic-gate */ 4947c478bd9Sstevel@tonic-gate #define EHCI_QTD_NEXT_QTD_PTR 0xFFFFFFE0 /* Next QTD pointer */ 4957c478bd9Sstevel@tonic-gate #define EHCI_QTD_NEXT_QTD_PTR_VALID 0x00000001 /* Next QTD validity */ 4967c478bd9Sstevel@tonic-gate 4977c478bd9Sstevel@tonic-gate /* 4987c478bd9Sstevel@tonic-gate * qtd_alt_next_qtd control bits. 4997c478bd9Sstevel@tonic-gate */ 5007c478bd9Sstevel@tonic-gate #define EHCI_QTD_ALT_NEXT_QTD_PTR 0xFFFFFFE0 /* Alt QTD pointer */ 5017c478bd9Sstevel@tonic-gate #define EHCI_QTD_ALT_NEXT_QTD_PTR_VALID 0x00000001 /* Alt QTD validity */ 5027c478bd9Sstevel@tonic-gate 5037c478bd9Sstevel@tonic-gate /* 5047c478bd9Sstevel@tonic-gate * qtd_ctrl control bits. 5057c478bd9Sstevel@tonic-gate */ 5067c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_DATA_TOGGLE 0x80000000 /* Data toggle */ 5077c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_DATA_TOGGLE_0 0x00000000 /* Data toggle 0 */ 5087c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_DATA_TOGGLE_1 0x80000000 /* Data toggle 1 */ 5097c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_BYTES_TO_XFER 0x7FFF0000 /* Bytes to xfer */ 5107c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_BYTES_TO_XFER_SHIFT 16 /* Bytes xfer mask */ 5117c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_INTR_ON_COMPLETE 0x00008000 /* Intr on complete */ 5127c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_C_PAGE 0x00007000 /* Current page */ 5137c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_MAX_ERR_COUNTS 0x00000C00 /* Max error counts */ 5147c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_PID_CODE 0x00000300 /* PID code */ 5157c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_OUT_PID 0x00000000 /* OUT token */ 5167c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_IN_PID 0x00000100 /* IN token */ 5177c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_SETUP_PID 0x00000200 /* SETUP token */ 5187c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_XACT_STATUS 0x000000FF /* Xact status */ 5197c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_HS_XACT_STATUS 0x000000F8 /* HS Xact status */ 5207c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_NON_HS_XACT_STATUS 0x000000FD /* Non HS Xact status */ 5217c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_NO_ERROR 0x00000000 /* No error */ 5227c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_ACTIVE_XACT 0x00000080 /* Active xact */ 5237c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_HALTED_XACT 0x00000040 /* Halted due to err */ 5247c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_DATA_BUFFER_ERROR 0x00000020 /* Data buffer error */ 5257c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_ERR_COUNT_MASK 0x00000C00 /* Error count */ 5267c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_BABBLE_DETECTED 0x00000010 /* Babble detected */ 5277c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_XACT_ERROR 0x00000008 /* Transaction error */ 5287c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_MISSED_uFRAME 0x00000004 /* Missed uFrame */ 5297c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_SPLIT_XACT_STATE 0x00000002 /* Split xact state */ 5307c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_DO_START_SPLIT 0x00000000 /* Do start split */ 5317c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_DO_COMPLETE_SPLIT 0x00000002 /* Do complete split */ 5327c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_PING_STATE 0x00000001 /* Ping state */ 5337c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_DO_OUT 0x00000000 /* Do OUT */ 5347c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_DO_PING 0x00000001 /* Do PING */ 5357c478bd9Sstevel@tonic-gate #define EHCI_QTD_CTRL_PRD_SPLIT_XACT_ERR 0x00000001 /* Periodic split err */ 5367c478bd9Sstevel@tonic-gate 5377c478bd9Sstevel@tonic-gate /* 5387c478bd9Sstevel@tonic-gate * qtd_buf[X] control bits. 5397c478bd9Sstevel@tonic-gate */ 5407c478bd9Sstevel@tonic-gate #define EHCI_QTD_BUF_PTR 0xFFFFF000 /* Buffer pointer */ 5417c478bd9Sstevel@tonic-gate #define EHCI_QTD_BUF_CURR_OFFSET 0x00000FFF /* Current offset */ 5427c478bd9Sstevel@tonic-gate 5437c478bd9Sstevel@tonic-gate /* 5447c478bd9Sstevel@tonic-gate * qtd_buf_high[X] control bits. 5457c478bd9Sstevel@tonic-gate */ 5467c478bd9Sstevel@tonic-gate #define EHCI_QTD_BUF_HIGH_PTR 0xFFFFFFFF /* 64 bit addressing */ 5477c478bd9Sstevel@tonic-gate 5487c478bd9Sstevel@tonic-gate /* 5497c478bd9Sstevel@tonic-gate * qtd_state 5507c478bd9Sstevel@tonic-gate * 5517c478bd9Sstevel@tonic-gate * QTD States 5527c478bd9Sstevel@tonic-gate */ 5537c478bd9Sstevel@tonic-gate #define EHCI_QTD_FREE 1 /* Free QTD */ 5547c478bd9Sstevel@tonic-gate #define EHCI_QTD_DUMMY 2 /* Dummy QTD */ 5557c478bd9Sstevel@tonic-gate #define EHCI_QTD_ACTIVE 3 /* Active QTD */ 5567c478bd9Sstevel@tonic-gate #define EHCI_QTD_RECLAIM 4 /* Reclaim QTD */ 5577c478bd9Sstevel@tonic-gate 5587c478bd9Sstevel@tonic-gate /* 5597c478bd9Sstevel@tonic-gate * qtd_ctrl_phase 5607c478bd9Sstevel@tonic-gate * 5617c478bd9Sstevel@tonic-gate * Control Transfer Phase information 5627c478bd9Sstevel@tonic-gate */ 5637c478bd9Sstevel@tonic-gate #define EHCI_CTRL_SETUP_PHASE 1 /* Setup phase */ 5647c478bd9Sstevel@tonic-gate #define EHCI_CTRL_DATA_PHASE 2 /* Data phase */ 5657c478bd9Sstevel@tonic-gate #define EHCI_CTRL_STATUS_PHASE 3 /* Status phase */ 5667c478bd9Sstevel@tonic-gate 5677c478bd9Sstevel@tonic-gate /* 5687c478bd9Sstevel@tonic-gate * Host Controller Split Isochronous Transfer Descripter 5697c478bd9Sstevel@tonic-gate * 5707c478bd9Sstevel@tonic-gate * iTD/siTD is a memory structure that describes the information necessary for 5717c478bd9Sstevel@tonic-gate * the Host Controller (HC) to transfer a block of data to or from a 5727c478bd9Sstevel@tonic-gate * 1.1 isochronous device end point. The iTD/siTD will be inserted between 5737c478bd9Sstevel@tonic-gate * the periodic frame list and the interrupt tree lattice. This structure 5747c478bd9Sstevel@tonic-gate * must be aligned to a 32 byte boundary. 5757c478bd9Sstevel@tonic-gate */ 5767c478bd9Sstevel@tonic-gate typedef volatile struct ehci_itd { 5777c478bd9Sstevel@tonic-gate uint32_t itd_link_ptr; /* Next TD */ 5787c478bd9Sstevel@tonic-gate uint32_t itd_body[15]; /* iTD and siTD body */ 579b3001defSlg uint32_t itd_body_high[7]; /* For 64 bit addressing */ 5807c478bd9Sstevel@tonic-gate 5817c478bd9Sstevel@tonic-gate /* Padding required */ 582b3001defSlg uint32_t itd_pad; 5837c478bd9Sstevel@tonic-gate 5847c478bd9Sstevel@tonic-gate /* HCD private fields */ 5857c478bd9Sstevel@tonic-gate uint32_t itd_trans_wrapper; /* Transfer wrapper */ 5867c478bd9Sstevel@tonic-gate uint32_t itd_itw_next_itd; /* Next iTD on TW */ 5877c478bd9Sstevel@tonic-gate uint32_t itd_next_active_itd; /* Next iTD in active list */ 5887c478bd9Sstevel@tonic-gate uint32_t itd_state; /* iTD state */ 589b3001defSlg uint32_t itd_index[8]; /* iTD index */ 5907c478bd9Sstevel@tonic-gate uint64_t itd_frame_number; /* Frame iTD exists */ 5917c478bd9Sstevel@tonic-gate uint64_t itd_reclaim_number; /* Frame iTD is reclaimed */ 5927c478bd9Sstevel@tonic-gate } ehci_itd_t; 5937c478bd9Sstevel@tonic-gate 5947c478bd9Sstevel@tonic-gate /* 5957c478bd9Sstevel@tonic-gate * Generic Link Ptr Bits 5967c478bd9Sstevel@tonic-gate * EHCI_TD_LINK_PTR : Points to the next data object to be processed 5977c478bd9Sstevel@tonic-gate * EHCI_TD_LINK_PTR_TYPE : Type of reference this descriptor is 5987c478bd9Sstevel@tonic-gate * EHCI_TD_LINK_PTR_VALID : Is this link pointer valid 5997c478bd9Sstevel@tonic-gate */ 6007c478bd9Sstevel@tonic-gate #define EHCI_ITD_LINK_PTR 0xFFFFFFE0 /* TD link ptr mask */ 6017c478bd9Sstevel@tonic-gate #define EHCI_ITD_LINK_REF 0x00000006 /* Ref to TD/ITD/SITD */ 6027c478bd9Sstevel@tonic-gate #define EHCI_ITD_LINK_REF_ITD 0x00000000 /* ITD pointer */ 6037c478bd9Sstevel@tonic-gate #define EHCI_ITD_LINK_REF_QH 0x00000002 /* QH pointer */ 6047c478bd9Sstevel@tonic-gate #define EHCI_ITD_LINK_REF_SITD 0x00000004 /* SITD pointer */ 6057c478bd9Sstevel@tonic-gate #define EHCI_ITD_LINK_REF_FSTN 0x00000006 /* FSTN pointer */ 6067c478bd9Sstevel@tonic-gate #define EHCI_ITD_LINK_PTR_INVALID 0x00000001 /* Link ptr validity */ 6077c478bd9Sstevel@tonic-gate 608b3001defSlg #define EHCI_ITD_CTRL_LIST_SIZE 8 609b3001defSlg #define EHCI_ITD_BUFFER_LIST_SIZE 7 6107c478bd9Sstevel@tonic-gate #define EHCI_ITD_CTRL0 0 /* Status and Ctrl List */ 6117c478bd9Sstevel@tonic-gate #define EHCI_ITD_CTRL1 1 6127c478bd9Sstevel@tonic-gate #define EHCI_ITD_CTRL2 2 6137c478bd9Sstevel@tonic-gate #define EHCI_ITD_CTRL3 3 6147c478bd9Sstevel@tonic-gate #define EHCI_ITD_CTRL4 4 6157c478bd9Sstevel@tonic-gate #define EHCI_ITD_CTRL5 5 6167c478bd9Sstevel@tonic-gate #define EHCI_ITD_CTRL6 6 6177c478bd9Sstevel@tonic-gate #define EHCI_ITD_CTRL7 7 6187c478bd9Sstevel@tonic-gate #define EHCI_ITD_BUFFER0 8 /* Buffer Page Ptr List */ 6197c478bd9Sstevel@tonic-gate #define EHCI_ITD_BUFFER1 9 6207c478bd9Sstevel@tonic-gate #define EHCI_ITD_BUFFER2 10 6217c478bd9Sstevel@tonic-gate #define EHCI_ITD_BUFFER3 11 6227c478bd9Sstevel@tonic-gate #define EHCI_ITD_BUFFER4 12 6237c478bd9Sstevel@tonic-gate #define EHCI_ITD_BUFFER5 13 6247c478bd9Sstevel@tonic-gate #define EHCI_ITD_BUFFER6 14 6257c478bd9Sstevel@tonic-gate 626b3001defSlg /* 627b3001defSlg * iTD Transaction Status and Control bits 628b3001defSlg */ 629b3001defSlg #define EHCI_ITD_XFER_STATUS_MASK 0xF0000000 630b3001defSlg #define EHCI_ITD_XFER_STATUS_SHIFT 28 631b3001defSlg #define EHCI_ITD_XFER_ACTIVE 0x80000000 632b3001defSlg #define EHCI_ITD_XFER_DATA_BUFFER_ERR 0x40000000 633b3001defSlg #define EHCI_ITD_XFER_BABBLE 0x20000000 634b3001defSlg #define EHCI_ITD_XFER_ERROR 0x10000000 635b3001defSlg #define EHCI_ITD_XFER_LENGTH 0x0FFF0000 636b3001defSlg #define EHCI_ITD_XFER_IOC 0x00008000 637b3001defSlg #define EHCI_ITD_XFER_IOC_ON 0x00008000 638b3001defSlg #define EHCI_ITD_XFER_IOC_OFF 0x00000000 639b3001defSlg #define EHCI_ITD_XFER_PAGE_SELECT 0x00007000 640b3001defSlg #define EHCI_ITD_XFER_OFFSET 0x00000FFF 641b3001defSlg 642b3001defSlg /* 643b3001defSlg * iTD Buffer Page Pointer bits 644b3001defSlg */ 645b3001defSlg #define EHCI_ITD_CTRL_BUFFER_MASK 0xFFFFF000 646b3001defSlg #define EHCI_ITD_CTRL_ENDPT_MASK 0x00000F00 647b3001defSlg #define EHCI_ITD_CTRL_DEVICE_MASK 0x0000007F 648b3001defSlg #define EHCI_ITD_CTRL_DIR 0x00000800 649b3001defSlg #define EHCI_ITD_CTRL_DIR_IN 0x00000800 650b3001defSlg #define EHCI_ITD_CTRL_DIR_OUT 0x00000000 651b3001defSlg #define EHCI_ITD_CTRL_MAX_PACKET_MASK 0x000007FF 652b3001defSlg #define EHCI_ITD_CTRL_MULTI_MASK 0x00000003 653b3001defSlg #define EHCI_ITD_CTRL_ONE_XACT 0x00000001 654b3001defSlg #define EHCI_ITD_CTRL_TWO_XACT 0x00000002 655b3001defSlg #define EHCI_ITD_CTRL_THREE_XACT 0x00000003 656b3001defSlg 657b3001defSlg /* Unused iTD index */ 658b3001defSlg #define EHCI_ITD_UNUSED_INDEX 0xFFFFFFFF 659b3001defSlg 6607c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL 0 6617c478bd9Sstevel@tonic-gate #define EHCI_SITD_UFRAME_SCHED 1 6627c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_STATE 2 6637c478bd9Sstevel@tonic-gate #define EHCI_SITD_BUFFER0 3 6647c478bd9Sstevel@tonic-gate #define EHCI_SITD_BUFFER1 4 6657c478bd9Sstevel@tonic-gate #define EHCI_SITD_PREV_SITD 5 6667c478bd9Sstevel@tonic-gate 6677c478bd9Sstevel@tonic-gate /* 6687c478bd9Sstevel@tonic-gate * sitd_ctrl bits 6697c478bd9Sstevel@tonic-gate * EHCI_SITD_CTRL_DIR : Direction of transaction 6707c478bd9Sstevel@tonic-gate * EHCI_SITD_CTRL_PORT_MASK : Port # of recipient transaction translator(TT) 6717c478bd9Sstevel@tonic-gate * EHCI_SITD_CTRL_HUB_MASK : Device address of the TT's hub 6727c478bd9Sstevel@tonic-gate * EHCI_SITD_CTRL_END_PT_MASK : Endpoint # on device serving as data source/sink 6737c478bd9Sstevel@tonic-gate * EHCI_SITD_CTRL_DEVICE_MASK : Address of device serving as data source/sink 6747c478bd9Sstevel@tonic-gate */ 6757c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_DIR 0x80000000 6767c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_DIR_IN 0x80000000 6777c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_DIR_OUT 0x00000000 6787c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_PORT_MASK 0x7F000000 6797c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_PORT_SHIFT 24 6807c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_HUB_MASK 0x007F0000 6817c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_HUB_SHIFT 16 6827c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_END_PT_MASK 0x00000F00 6837c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_END_PT_SHIFT 8 6847c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_DEVICE_MASK 0x0000007F 6857c478bd9Sstevel@tonic-gate #define EHCI_SITD_CTRL_DEVICE_SHIFT 0 6867c478bd9Sstevel@tonic-gate 6877c478bd9Sstevel@tonic-gate /* 6887c478bd9Sstevel@tonic-gate * sitd_uframe_sched bits 6897c478bd9Sstevel@tonic-gate * EHCI_SITD_UFRAME_CMASK_MASK : Determines which uFrame the HC executes CSplit 6907c478bd9Sstevel@tonic-gate * EHCI_SITD_UFRAME_SMASK_MASK : Determines which uFrame the HC executes SSplit 6917c478bd9Sstevel@tonic-gate */ 6927c478bd9Sstevel@tonic-gate #define EHCI_SITD_UFRAME_CMASK_MASK 0x0000FF00 6937c478bd9Sstevel@tonic-gate #define EHCI_SITD_UFRAME_CMASK_SHIFT 8 6947c478bd9Sstevel@tonic-gate #define EHCI_SITD_UFRAME_SMASK_MASK 0x000000FF 6957c478bd9Sstevel@tonic-gate #define EHCI_SITD_UFRAME_SMASK_SHIFT 0 6967c478bd9Sstevel@tonic-gate 6977c478bd9Sstevel@tonic-gate /* 6987c478bd9Sstevel@tonic-gate * sitd_xfer_state bits 6997c478bd9Sstevel@tonic-gate * EHCI_SITD_XFER_IOC_MASK : Interrupt when transaction is complete. 7007c478bd9Sstevel@tonic-gate * EHCI_SITD_XFER_PAGE_MASK : Which data page pointer should be concatenated 7017c478bd9Sstevel@tonic-gate * with the CurrentOffset to construct a data 7027c478bd9Sstevel@tonic-gate * buffer pointer 7037c478bd9Sstevel@tonic-gate * EHCI_SITD_XFER_TOTAL_MASK : Total number of bytes expected in xfer(1023 Max). 7047c478bd9Sstevel@tonic-gate * EHCI_SITD_XFER_CPROG_MASK : HC tracks which CSplit has been executed. 7057c478bd9Sstevel@tonic-gate * EHCI_SITD_XFER_STATUS_MASK : Status of xfer 7067c478bd9Sstevel@tonic-gate */ 7077c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_IOC_MASK 0x80000000 7087c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_IOC_ON 0x80000000 7097c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_IOC_OFF 0x00000000 7107c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_PAGE_MASK 0x40000000 7117c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_PAGE_0 0x00000000 7127c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_PAGE_1 0x40000000 7137c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_TOTAL_MASK 0x03FF0000 7147c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_TOTAL_SHIFT 16 7157c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_CPROG_MASK 0x0000FF00 7167c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_CPROG_SHIFT 8 7177c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_STATUS_MASK 0x000000FF 7187c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_STATUS_SHIFT 0 7197c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_ACTIVE 0x80 7207c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_ERROR 0x40 7217c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_DATA_BUFFER_ERR 0x20 7227c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_BABBLE 0x10 7237c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_XACT_ERROR 0x08 7247c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_MISSED_UFRAME 0x04 7257c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_SPLIT_XACT_STATE 0x02 7267c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_SSPLIT_STATE 0x00 7277c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_CSPLIT_STATE 0x02 7287c478bd9Sstevel@tonic-gate 7297c478bd9Sstevel@tonic-gate /* 7307c478bd9Sstevel@tonic-gate * sitd_xfer_buffer0/1 7317c478bd9Sstevel@tonic-gate * EHCI_SITD_XFER_BUFFER_MASK : Buffer Pointer List 7327c478bd9Sstevel@tonic-gate * EHCI_SITD_XFER_OFFSET_MASK : Current byte offset 7337c478bd9Sstevel@tonic-gate * EHCI_SITD_XFER_TP_MASK : Transaction position 7347c478bd9Sstevel@tonic-gate * EHCI_SITD_XFER_TCOUNT_MASK : Transaction count 7357c478bd9Sstevel@tonic-gate */ 7367c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_BUFFER_MASK 0xFFFFF000 7377c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_BUFFER_SHIFT 12 7387c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_OFFSET_MASK 0x00000FFF 7397c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_OFFSET_SHIFT 0 7407c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_TP_MASK 0x00000018 7417c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_TP_ALL 0x0 7427c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_TP_BEGIN 0x1 7437c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_TP_MID 0x2 7447c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_TP_END 0x3 7457c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_TCOUNT_MASK 0x00000007 7467c478bd9Sstevel@tonic-gate #define EHCI_SITD_XFER_TCOUNT_SHIFT 0 7477c478bd9Sstevel@tonic-gate 7487c478bd9Sstevel@tonic-gate /* 7497c478bd9Sstevel@tonic-gate * qtd_state 7507c478bd9Sstevel@tonic-gate * 7517c478bd9Sstevel@tonic-gate * ITD States 7527c478bd9Sstevel@tonic-gate */ 7537c478bd9Sstevel@tonic-gate #define EHCI_ITD_FREE 1 /* Free ITD */ 7547c478bd9Sstevel@tonic-gate #define EHCI_ITD_DUMMY 2 /* Dummy ITD */ 7557c478bd9Sstevel@tonic-gate #define EHCI_ITD_ACTIVE 3 /* Active ITD */ 7567c478bd9Sstevel@tonic-gate #define EHCI_ITD_RECLAIM 4 /* Reclaim ITD */ 7577c478bd9Sstevel@tonic-gate 7587c478bd9Sstevel@tonic-gate #ifdef __cplusplus 7597c478bd9Sstevel@tonic-gate } 7607c478bd9Sstevel@tonic-gate #endif 7617c478bd9Sstevel@tonic-gate 7627c478bd9Sstevel@tonic-gate #endif /* _SYS_USB_EHCI_H */ 763