1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _PMCS_DEF_H 26 #define _PMCS_DEF_H 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 typedef enum { 32 NOTHING, /* nothing connected here */ 33 SATA, /* SATA connection */ 34 SAS, /* direct or indirect SAS connection */ 35 EXPANDER, /* connection to an expander */ 36 NEW /* Brand new device (pending state) */ 37 } pmcs_dtype_t; 38 39 /* 40 * This structure defines a PHY device that represents what we 41 * are connected to. 42 * 43 * The eight real physical PHYs that are in the PMC8X6G are represented 44 * as an array of eight of these structures which define what these 45 * real PHYs are connected to. 46 * 47 * Depending upon what is actually connected to each PHY, the 48 * type set will define what we're connected to. If it is 49 * a direct SATA connection, the phy will describe a SATA endpoint 50 * If it is a direct SAS connection, it will describe a SAS 51 * endpoint. 52 * 53 * If it is an EXPANDER, this will describe the edge of an expander. 54 * As we perform discovery on what is in an EXPANDER we define an 55 * additional list of phys that represent what the Expander is connected to. 56 */ 57 #define PMCS_HW_MIN_LINK_RATE SAS_LINK_RATE_1_5GBIT 58 #define PMCS_HW_MAX_LINK_RATE SAS_LINK_RATE_6GBIT 59 60 #define PMCS_INVALID_DEVICE_ID 0xffffffff 61 #define PMCS_PHY_INVALID_PORT_ID 0xf 62 63 #define PMCS_PM_MAX_NAMELEN 16 64 #define PMCS_MAX_REENUMERATE 2 /* Maximum re-enumeration attempts */ 65 66 /* 67 * Number of usecs to wait after last noted activate/deactivate callback 68 * before possibly restarting discovery 69 */ 70 #define PMCS_REDISCOVERY_DELAY (5 * MICROSEC) 71 72 struct pmcs_phy { 73 pmcs_phy_t *sibling; /* sibling phy */ 74 pmcs_phy_t *parent; /* parent phy */ 75 pmcs_phy_t *children; /* head of list of children */ 76 pmcs_phy_t *dead_next; /* dead PHY list link */ 77 list_node_t list_node; /* list element */ 78 uint32_t device_id; /* PMC8X6G device handle */ 79 uint32_t 80 ncphy : 8, /* # of contained phys for expander */ 81 hw_event_ack : 24; /* XXX: first level phy event acked */ 82 uint8_t phynum; /* phy number on parent expander */ 83 uint8_t width; /* how many phys wide */ 84 uint8_t ds_recovery_retries; /* # error retry attempts */ 85 uint8_t ds_prev_good_recoveries; /* # successful recoveries */ 86 clock_t prev_recovery; /* previous successful recovery */ 87 clock_t last_good_recovery; /* oldest successful recovery */ 88 /* within PMCS_MAX_DS_RECOVERY_TIME time frame */ 89 pmcs_dtype_t dtype; /* current dtype of the phy */ 90 pmcs_dtype_t pend_dtype; /* new dtype (pending change) */ 91 uint32_t 92 level : 8, /* level in expander tree */ 93 tolerates_sas2 : 1, /* tolerates SAS2 SMP */ 94 spinup_hold : 1, /* spinup hold needs releasing */ 95 atdt : 3, /* attached device type */ 96 portid : 4, /* PMC8X6G port context */ 97 link_rate : 4, /* current supported speeds */ 98 valid_device_id : 1, /* device id is valid */ 99 abort_sent : 1, /* we've sent an abort */ 100 abort_pending : 1, /* we have an abort pending */ 101 need_rl_ext : 1, /* need SATA RL_EXT recocvery */ 102 subsidiary : 1, /* this is part of a wide phy */ 103 configured : 1, /* is configured */ 104 dead : 1, /* dead */ 105 changed : 1, /* this phy is changing */ 106 reenumerate : 1, /* attempt re-enumeration */ 107 deregister_wait : 1; /* phy waiting to get deregistered */ 108 clock_t config_stop; /* When config attempts will stop */ 109 hrtime_t abort_all_start; 110 kcondvar_t abort_all_cv; /* Wait for ABORT_ALL completion */ 111 kmutex_t phy_lock; 112 volatile uint32_t ref_count; /* Targets & work on this PHY */ 113 uint32_t enum_attempts; /* # of enumeration attempts */ 114 uint8_t sas_address[8]; /* SAS address for this PHY */ 115 struct { 116 uint32_t 117 prog_min_rate :4, 118 hw_min_rate :4, 119 prog_max_rate :4, 120 hw_max_rate :4, 121 reserved :16; 122 } state; 123 char path[32]; /* path name for this phy */ 124 pmcs_hw_t *pwp; /* back ptr to hba struct */ 125 pmcs_iport_t *iport; /* back ptr to the iport handle */ 126 pmcs_iport_t *last_iport; /* last iport this PHY was on */ 127 pmcs_xscsi_t *target; /* back ptr to current target */ 128 kstat_t *phy_stats; /* kstats for this phy */ 129 /* 130 * Attached port phy mask and target port phymask. With 16 bytes 131 * we can represent a phymask for anything with up to 64 ports 132 */ 133 uint64_t att_port_pm; /* att port pm for this PHY */ 134 uint64_t att_port_pm_tmp; /* Temp area for wide-ports */ 135 char att_port_pm_str[PMCS_PM_MAX_NAMELEN + 1]; 136 uint64_t tgt_port_pm; /* tgt port pm for this PHY */ 137 uint64_t tgt_port_pm_tmp; /* Temp area for wide-ports */ 138 char tgt_port_pm_str[PMCS_PM_MAX_NAMELEN + 1]; 139 smp_routing_attr_t routing_attr; /* Routing attr. from discover resp. */ 140 smp_routing_attr_t routing_method; /* Actual routing method used. */ 141 smp_report_general_resp_t rg_resp; /* Response to REPORT_GENERAL */ 142 smp_discover_resp_t disc_resp; /* Response to DISCOVER */ 143 }; 144 145 /* maximum number of ds recovery retries (ds_recovery_retries) */ 146 #define PMCS_MAX_DS_RECOVERY_RETRIES 10 147 148 /* max time allowed for successful recovery */ 149 #define PMCS_MAX_DS_RECOVERY_TIME (60 * 1000000) /* 60 seconds */ 150 151 /* ds recovery on same same phy is not allowed within this interval */ 152 #define PMCS_DS_RECOVERY_INTERVAL (1000000) /* 1 second */ 153 154 155 /* 156 * Inbound and Outbound Queue Related Definitions. 157 * 158 * The PMC8X6G has a programmable number of inbound and outbound circular 159 * queues for use in message passing between the host and the PMC8X6G 160 * (up to 64 queues for the Rev C Chip). This driver does not use all 161 * possible queues. 162 * 163 * Each Queue is given 4K of consistent memory and we set a 64 byte size for 164 * the queue entry size (this gives us 256 queue entries per queue). 165 * 166 * This allocation then continues up a further PMCS_SCRATCH_SIZE bytes 167 * that the driver uses as a temporary scratch area for things like 168 * SMP discovery. 169 * 170 * This control area looks like this: 171 * 172 * Offset What 173 * ------------------------------------------------ 174 * 0 IQ 0 Consumer Index 175 * 4 IQ 1 Consumer Index 176 * 8..255 ... 177 * 252..255 IQ 63 Consumer Index 178 * 256 OQ 0 Producer Index 179 * 260 OQ 1 Producer Index 180 * 264..259 .... 181 * 508..511 OQ 63 Producer Index 182 * 512..512+PMCS_SCRATCH_SIZE-1 Scratch area. 183 */ 184 #define IQCI_BASE_OFFSET 0 185 #define IQ_OFFSET(qnum) (IQCI_BASE_OFFSET + (qnum << 2)) 186 #define OQPI_BASE_OFFSET 256 187 #define OQ_OFFSET(qnum) (OQPI_BASE_OFFSET + (qnum << 2)) 188 189 /* 190 * Work related structures. Each one of these structures is paired 191 * with *any* command that is fed to the PMC8X6G via one of the 192 * Inbound Queues. The work structure has a tag to compare with 193 * the message that comes back out of an Outbound Queue. The 194 * work structure also points to the phy which this command is 195 * tied to. It also has a pointer a callback function (if defined). 196 * See that TAG Architecture below for the various kinds of 197 * dispositions of a work structure. 198 */ 199 200 /* 201 * Work Structure States 202 * 203 * NIL -> READY 204 * READY -> NIL 205 * READY -> ONCHIP 206 * ONCHIP -> INTR 207 * INTR -> READY 208 * INTR -> NIL 209 * INTR -> ABORTED 210 * INTR -> TIMED_OUT 211 * ABORTED -> NIL 212 * TIMED_OUT -> NIL 213 */ 214 typedef enum { 215 PMCS_WORK_STATE_NIL = 0, 216 PMCS_WORK_STATE_READY, 217 PMCS_WORK_STATE_ONCHIP, 218 PMCS_WORK_STATE_INTR, 219 PMCS_WORK_STATE_IOCOMPQ, 220 PMCS_WORK_STATE_ABORTED, 221 PMCS_WORK_STATE_TIMED_OUT 222 } pmcs_work_state_t; 223 224 struct pmcwork { 225 STAILQ_ENTRY(pmcwork) next; 226 kmutex_t lock; 227 kcondvar_t sleep_cv; 228 void *ptr; /* linkage or callback function */ 229 void *arg; /* command specific data */ 230 pmcs_phy_t *phy; /* phy who owns this command */ 231 pmcs_xscsi_t *xp; /* Back pointer to xscsi struct */ 232 volatile uint32_t htag; /* tag for this structure */ 233 uint32_t abt_htag; /* Tag of command to be aborted */ 234 uint32_t 235 timer : 27, 236 onwire : 1, 237 dead : 1, 238 state : 3; 239 hrtime_t start; /* timestamp start */ 240 uint32_t ssp_event; /* ssp event */ 241 pmcs_dtype_t dtype; /* stash, incase phy gets cleared */ 242 243 void *last_ptr; 244 void *last_arg; 245 pmcs_phy_t *last_phy; 246 pmcs_xscsi_t *last_xp; 247 uint32_t last_htag; 248 pmcs_work_state_t last_state; 249 hrtime_t finish; 250 }; 251 252 #define PMCS_REC_EVENT 0xffffffff /* event recovery */ 253 254 /* 255 * This structure defines a PMC-Sierra defined firmware header. 256 */ 257 #pragma pack(4) 258 typedef struct { 259 char vendor_id[8]; 260 uint8_t product_id; 261 uint8_t hwrev; 262 uint8_t destination_partition; 263 uint8_t reserved0; 264 uint8_t fwrev[4]; 265 uint32_t firmware_length; 266 uint32_t crc; 267 uint32_t start_address; 268 uint8_t data[]; 269 } pmcs_fw_hdr_t; 270 #pragma pack() 271 272 /* 273 * Offlevel work as a bit pattern. 274 */ 275 #define PMCS_WORK_DISCOVER 0 276 #define PMCS_WORK_ABORT_HANDLE 3 277 #define PMCS_WORK_SPINUP_RELEASE 4 278 #define PMCS_WORK_SAS_HW_ACK 5 279 #define PMCS_WORK_SATA_RUN 6 280 #define PMCS_WORK_RUN_QUEUES 7 281 #define PMCS_WORK_ADD_DMA_CHUNKS 8 282 #define PMCS_WORK_DS_ERR_RECOVERY 9 283 #define PMCS_WORK_SSP_EVT_RECOVERY 10 284 #define PMCS_WORK_DEREGISTER_DEV 11 285 #define PMCS_WORK_DUMP_REGS 12 286 287 /* 288 * The actual values as they appear in work_flags 289 */ 290 #define PMCS_WORK_FLAG_DISCOVER (1 << 0) 291 #define PMCS_WORK_FLAG_ABORT_HANDLE (1 << 3) 292 #define PMCS_WORK_FLAG_SPINUP_RELEASE (1 << 4) 293 #define PMCS_WORK_FLAG_SAS_HW_ACK (1 << 5) 294 #define PMCS_WORK_FLAG_SATA_RUN (1 << 6) 295 #define PMCS_WORK_FLAG_RUN_QUEUES (1 << 7) 296 #define PMCS_WORK_FLAG_ADD_DMA_CHUNKS (1 << 8) 297 #define PMCS_WORK_FLAG_DS_ERR_RECOVERY (1 << 9) 298 #define PMCS_WORK_FLAG_SSP_EVT_RECOVERY (1 << 10) 299 #define PMCS_WORK_FLAG_DEREGISTER_DEV (1 << 11) 300 #define PMCS_WORK_FLAG_DUMP_REGS (1 << 12) 301 302 /* 303 * This structure is used by this function to test MPI (and interrupts) 304 * after MPI has been started to make sure it's working reliably. 305 */ 306 typedef struct { 307 uint32_t signature; 308 uint32_t count; 309 uint32_t *ptr; 310 } echo_test_t; 311 #define ECHO_SIGNATURE 0xbebebeef 312 313 /* 314 * Tag Architecture. The PMC has 32 bit tags for MPI messages. 315 * We use this tag this way. 316 * 317 * bits what 318 * ------------------------ 319 * 31 done bit 320 * 30..28 tag type 321 * 27..12 rolling serial number 322 * 11..0 index into work area to get pmcwork structure 323 * 324 * A tag type of NONE means that nobody is waiting on any results, 325 * so the interrupt code frees the work structure that has this 326 * tag. 327 * 328 * A tag type of CBACK means that the the interrupt handler 329 * takes the tag 'arg' in the work structure to be a callback 330 * function pointer (see pmcs_cb_t). The callee is responsible 331 * for freeing the work structure that has this tag. 332 * 333 * A tag type of WAIT means that the issuer of the work needs 334 * be woken up from interrupt level when the command completes 335 * (or times out). If work structure tag 'arg' is non-null, 336 * up to 2*PMCS_QENTRY_SIZE bits of data from the Outbound Queue 337 * entry may be copied to the area pointed to by 'arg'. This 338 * allows issuers to get directly at the results of the command 339 * they issed. The synchronization point for the issuer and the 340 * interrupt code for command done notification is the setting 341 * of the 'DONE' bit in the tag as stored in the work structure. 342 */ 343 #define PMCS_TAG_TYPE_FREE 0 344 #define PMCS_TAG_TYPE_NONE 1 345 #define PMCS_TAG_TYPE_CBACK 2 346 #define PMCS_TAG_TYPE_WAIT 3 347 #define PMCS_TAG_TYPE_SHIFT 28 348 #define PMCS_TAG_SERNO_SHIFT 12 349 #define PMCS_TAG_INDEX_SHIFT 0 350 #define PMCS_TAG_TYPE_MASK 0x70000000 351 #define PMCS_TAG_DONE 0x80000000 352 #define PMCS_TAG_SERNO_MASK 0x0ffff000 353 #define PMCS_TAG_INDEX_MASK 0x00000fff 354 #define PMCS_TAG_TYPE(x) \ 355 (((x) & PMCS_TAG_TYPE_MASK) >> PMCS_TAG_TYPE_SHIFT) 356 #define PMCS_TAG_SERNO(x) \ 357 (((x) & PMCS_TAG_SERNO_MASK) >> PMCS_TAG_SERNO_SHIFT) 358 #define PMCS_TAG_INDEX(x) \ 359 (((x) & PMCS_TAG_INDEX_MASK) >> PMCS_TAG_INDEX_SHIFT) 360 #define PMCS_TAG_FREE 0 361 #define PMCS_COMMAND_DONE(x) \ 362 (((x)->htag == PMCS_TAG_FREE) || (((x)->htag & PMCS_TAG_DONE) != 0)) 363 #define PMCS_COMMAND_ACTIVE(x) \ 364 ((x)->htag != PMCS_TAG_FREE && (x)->state == PMCS_WORK_STATE_ONCHIP) 365 366 /* 367 * Miscellaneous Definitions 368 */ 369 #define CLEAN_MESSAGE(m, x) { \ 370 int _j = x; \ 371 while (_j < PMCS_MSG_SIZE) { \ 372 m[_j++] = 0; \ 373 } \ 374 } 375 376 #define COPY_MESSAGE(t, f, a) { \ 377 int _j; \ 378 for (_j = 0; _j < a; _j++) { \ 379 t[_j] = f[_j]; \ 380 } \ 381 while (_j < PMCS_MSG_SIZE) { \ 382 t[_j++] = 0; \ 383 } \ 384 } 385 386 #define PMCS_PHY_ADDRESSABLE(pp) \ 387 ((pp)->level == 0 && (pp)->dtype == SATA && \ 388 ((pp)->sas_address[0] >> 4) != 5) 389 390 #define RESTART_DISCOVERY(pwp) \ 391 ASSERT(!mutex_owned(&pwp->config_lock)); \ 392 mutex_enter(&pwp->config_lock); \ 393 pwp->config_changed = B_TRUE; \ 394 mutex_exit(&pwp->config_lock); \ 395 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 396 397 #define RESTART_DISCOVERY_LOCKED(pwp) \ 398 ASSERT(mutex_owned(&pwp->config_lock)); \ 399 pwp->config_changed = B_TRUE; \ 400 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 401 402 #define PHY_CHANGED(pwp, p) \ 403 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, p, NULL, "%s changed in " \ 404 "%s line %d", p->path, __func__, __LINE__); \ 405 p->changed = 1; \ 406 p->enum_attempts = 0 407 408 #define PHY_CHANGED_AT_LOCATION(pwp, p, func, line) \ 409 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, p, NULL, "%s changed in " \ 410 "%s line %d", p->path, func, line); \ 411 p->changed = 1; \ 412 p->enum_attempts = 0 413 414 #define PHY_TYPE(pptr) \ 415 (((pptr)->dtype == NOTHING)? "NOTHING" : \ 416 (((pptr)->dtype == SATA)? "SATA" : \ 417 (((pptr)->dtype == SAS)? "SAS" : "EXPANDER"))) 418 419 #define IS_ROOT_PHY(pptr) (pptr->parent == NULL) 420 421 #define PMCS_HIPRI(pwp, oq, c) \ 422 (pwp->hipri_queue & (1 << PMCS_IQ_OTHER)) ? \ 423 (PMCS_IOMB_HIPRI | PMCS_IOMB_IN_SAS(oq, c)) : \ 424 (PMCS_IOMB_IN_SAS(oq, c)) 425 426 #define SCHEDULE_WORK(hwp, wrk) \ 427 (void) atomic_set_long_excl(&hwp->work_flags, wrk) 428 429 /* 430 * Check to see if the requested work bit is set. Either way, the bit will 431 * be cleared upon return. 432 */ 433 #define WORK_SCHEDULED(hwp, wrk) \ 434 (atomic_clear_long_excl(&hwp->work_flags, wrk) == 0) 435 436 /* 437 * Check to see if the requested work bit is set. The value will not be 438 * changed in this case. The atomic_xx_nv operations can be quite expensive 439 * so this should not be used in non-DEBUG code. 440 */ 441 #define WORK_IS_SCHEDULED(hwp, wrk) \ 442 ((atomic_and_ulong_nv(&hwp->work_flags, (ulong_t)-1) & (1 << wrk)) != 0) 443 444 #define WAIT_FOR(p, t, r) \ 445 r = 0; \ 446 while (!PMCS_COMMAND_DONE(p)) { \ 447 clock_t tmp = cv_timedwait(&p->sleep_cv, \ 448 &p->lock, ddi_get_lbolt() + \ 449 drv_usectohz(t * 1000)); \ 450 if (!PMCS_COMMAND_DONE(p) && tmp < 0) { \ 451 r = 1; \ 452 break; \ 453 } \ 454 } 455 456 /* 457 * Signal the next I/O completion thread to start running. 458 */ 459 460 #define PMCS_CQ_RUN_LOCKED(hwp) \ 461 if (!STAILQ_EMPTY(&hwp->cq) || hwp->iocomp_cb_head) { \ 462 pmcs_cq_thr_info_t *cqti; \ 463 cqti = &hwp->cq_info.cq_thr_info \ 464 [hwp->cq_info.cq_next_disp_thr]; \ 465 hwp->cq_info.cq_next_disp_thr++; \ 466 if (hwp->cq_info.cq_next_disp_thr == \ 467 hwp->cq_info.cq_threads) { \ 468 hwp->cq_info.cq_next_disp_thr = 0; \ 469 } \ 470 mutex_enter(&cqti->cq_thr_lock); \ 471 cv_signal(&cqti->cq_cv); \ 472 mutex_exit(&cqti->cq_thr_lock); \ 473 } \ 474 475 #define PMCS_CQ_RUN(hwp) \ 476 mutex_enter(&hwp->cq_lock); \ 477 PMCS_CQ_RUN_LOCKED(hwp); \ 478 mutex_exit(&hwp->cq_lock); 479 480 481 /* 482 * Watchdog/SCSA timer definitions 483 */ 484 /* usecs to SCSA watchdog ticks */ 485 #define US2WT(x) (x)/10 486 487 /* 488 * More misc 489 */ 490 #define BYTE0(x) (((x) >> 0) & 0xff) 491 #define BYTE1(x) (((x) >> 8) & 0xff) 492 #define BYTE2(x) (((x) >> 16) & 0xff) 493 #define BYTE3(x) (((x) >> 24) & 0xff) 494 #define BYTE4(x) (((x) >> 32) & 0xff) 495 #define BYTE5(x) (((x) >> 40) & 0xff) 496 #define BYTE6(x) (((x) >> 48) & 0xff) 497 #define BYTE7(x) (((x) >> 56) & 0xff) 498 #define WORD0(x) (((x) >> 0) & 0xffff) 499 #define WORD1(x) (((x) >> 16) & 0xffff) 500 #define WORD2(x) (((x) >> 32) & 0xffff) 501 #define WORD3(x) (((x) >> 48) & 0xffff) 502 #define DWORD0(x) ((uint32_t)(x)) 503 #define DWORD1(x) ((uint32_t)(((uint64_t)x) >> 32)) 504 505 #define SAS_ADDR_FMT "0x%02x%02x%02x%02x%02x%02x%02x%02x" 506 #define SAS_ADDR_PRT(x) x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7] 507 508 #define PMCS_VALID_LINK_RATE(r) \ 509 ((r == SAS_LINK_RATE_1_5GBIT) || (r == SAS_LINK_RATE_3GBIT) || \ 510 (r == SAS_LINK_RATE_6GBIT)) 511 512 /* 513 * This is here to avoid inclusion of <sys/ctype.h> which is not lint clean. 514 */ 515 #define HEXDIGIT(x) (((x) >= '0' && (x) <= '9') || \ 516 ((x) >= 'a' && (x) <= 'f') || ((x) >= 'A' && (x) <= 'F')) 517 518 519 typedef void (*pmcs_cb_t) (pmcs_hw_t *, pmcwork_t *, uint32_t *); 520 521 /* 522 * Defines and structure used for tracing/logging information 523 */ 524 525 #define PMCS_TBUF_ELEM_SIZE 120 526 527 #ifdef DEBUG 528 #define PMCS_TBUF_NUM_ELEMS_DEF 100000 529 #else 530 #define PMCS_TBUF_NUM_ELEMS_DEF 15000 531 #endif 532 533 #define PMCS_TBUF_UA_MAX_SIZE 32 534 typedef struct { 535 /* Target-specific data */ 536 uint16_t target_num; 537 char target_ua[PMCS_TBUF_UA_MAX_SIZE]; 538 /* PHY-specific data */ 539 uint8_t phy_sas_address[8]; 540 char phy_path[32]; 541 pmcs_dtype_t phy_dtype; 542 /* Log data */ 543 timespec_t timestamp; 544 char buf[PMCS_TBUF_ELEM_SIZE]; 545 } pmcs_tbuf_t; 546 547 /* 548 * Firmware event log header format 549 */ 550 551 typedef struct pmcs_fw_event_hdr_s { 552 uint32_t fw_el_signature; 553 uint32_t fw_el_entry_start_offset; 554 uint32_t fw_el_rsvd1; 555 uint32_t fw_el_buf_size; 556 uint32_t fw_el_rsvd2; 557 uint32_t fw_el_oldest_idx; 558 uint32_t fw_el_latest_idx; 559 uint32_t fw_el_entry_size; 560 } pmcs_fw_event_hdr_t; 561 562 #ifdef __cplusplus 563 } 564 #endif 565 #endif /* _PMCS_DEF_H */ 566