1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _PMCS_DEF_H 26 #define _PMCS_DEF_H 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 typedef enum { 32 NOTHING, /* nothing connected here */ 33 SATA, /* SATA connection */ 34 SAS, /* direct or indirect SAS connection */ 35 EXPANDER, /* connection to an expander */ 36 NEW /* Brand new device (pending state) */ 37 } pmcs_dtype_t; 38 39 /* 40 * This structure defines a PHY device that represents what we 41 * are connected to. 42 * 43 * The eight real physical PHYs that are in the PMC8X6G are represented 44 * as an array of eight of these structures which define what these 45 * real PHYs are connected to. 46 * 47 * Depending upon what is actually connected to each PHY, the 48 * type set will define what we're connected to. If it is 49 * a direct SATA connection, the phy will describe a SATA endpoint 50 * If it is a direct SAS connection, it will describe a SAS 51 * endpoint. 52 * 53 * If it is an EXPANDER, this will describe the edge of an expander. 54 * As we perform discovery on what is in an EXPANDER we define an 55 * additional list of phys that represent what the Expander is connected to. 56 */ 57 #define PMCS_HW_MIN_LINK_RATE SAS_LINK_RATE_1_5GBIT 58 #define PMCS_HW_MAX_LINK_RATE SAS_LINK_RATE_6GBIT 59 60 #define PMCS_INVALID_DEVICE_ID 0xffffffff 61 62 #define PMCS_PM_MAX_NAMELEN 16 63 64 struct pmcs_phy { 65 pmcs_phy_t *sibling; /* sibling phy */ 66 pmcs_phy_t *parent; /* parent phy */ 67 pmcs_phy_t *children; /* head of list of children */ 68 pmcs_phy_t *dead_next; /* dead PHY list link */ 69 list_node_t list_node; /* list element */ 70 uint32_t device_id; /* PMC8X6G device handle */ 71 uint32_t 72 ncphy : 8, /* # of contained phys for expander */ 73 hw_event_ack : 24; /* XXX: first level phy event acked */ 74 uint8_t phynum; /* phy number on parent expander */ 75 uint8_t width; /* how many phys wide */ 76 uint8_t ds_recovery_retries; /* # error retry attempts */ 77 uint8_t ds_prev_good_recoveries; /* # successful recoveries */ 78 clock_t prev_recovery; /* previous successful recovery */ 79 clock_t last_good_recovery; /* oldest successful recovery */ 80 /* within PMCS_MAX_DS_RECOVERY_TIME time frame */ 81 pmcs_dtype_t dtype; /* current dtype of the phy */ 82 pmcs_dtype_t pend_dtype; /* new dtype (pending change) */ 83 uint32_t 84 level : 8, /* level in expander tree */ 85 tolerates_sas2 : 1, /* tolerates SAS2 SMP */ 86 spinup_hold : 1, /* spinup hold needs releasing */ 87 atdt : 3, /* attached device type */ 88 portid : 4, /* PMC8X6G port context */ 89 link_rate : 4, /* current supported speeds */ 90 valid_device_id : 1, /* device id is valid */ 91 abort_sent : 1, /* we've sent an abort */ 92 abort_pending : 1, /* we have an abort pending */ 93 need_rl_ext : 1, /* need SATA RL_EXT recocvery */ 94 subsidiary : 1, /* this is part of a wide phy */ 95 configured : 1, /* is configured */ 96 dead : 1, /* dead */ 97 changed : 1; /* this phy is changing */ 98 clock_t config_stop; /* When config attempts will stop */ 99 hrtime_t abort_all_start; 100 kcondvar_t abort_all_cv; /* Wait for ABORT_ALL completion */ 101 kmutex_t phy_lock; 102 volatile uint32_t ref_count; /* Targets & work on this PHY */ 103 uint8_t sas_address[8]; /* SAS address for this PHY */ 104 struct { 105 uint32_t 106 prog_min_rate :4, 107 hw_min_rate :4, 108 prog_max_rate :4, 109 hw_max_rate :4, 110 reserved :16; 111 } state; 112 char path[32]; /* path name for this phy */ 113 pmcs_hw_t *pwp; /* back ptr to hba struct */ 114 pmcs_iport_t *iport; /* back ptr to the iport handle */ 115 pmcs_xscsi_t *target; /* back ptr to current target */ 116 kstat_t *phy_stats; /* kstats for this phy */ 117 /* 118 * Attached port phy mask and target port phymask. With 16 bytes 119 * we can represent a phymask for anything with up to 64 ports 120 */ 121 uint64_t att_port_pm; /* att port pm for this PHY */ 122 uint64_t att_port_pm_tmp; /* Temp area for wide-ports */ 123 char att_port_pm_str[PMCS_PM_MAX_NAMELEN + 1]; 124 uint64_t tgt_port_pm; /* tgt port pm for this PHY */ 125 uint64_t tgt_port_pm_tmp; /* Temp area for wide-ports */ 126 char tgt_port_pm_str[PMCS_PM_MAX_NAMELEN + 1]; 127 }; 128 129 /* maximum number of ds recovery retries (ds_recovery_retries) */ 130 #define PMCS_MAX_DS_RECOVERY_RETRIES 4 131 132 /* max time allowed for successful recovery */ 133 #define PMCS_MAX_DS_RECOVERY_TIME (60 * 1000000) /* 60 seconds */ 134 135 /* ds recovery on same same phy is not allowed within this interval */ 136 #define PMCS_DS_RECOVERY_INTERVAL (1000000) /* 1 second */ 137 138 139 /* 140 * Inbound and Outbound Queue Related Definitions. 141 * 142 * The PMC8X6G has a programmable number of inbound and outbound circular 143 * queues for use in message passing between the host and the PMC8X6G 144 * (up to 64 queues for the Rev C Chip). This driver does not use all 145 * possible queues. 146 * 147 * Each Queue is given 4K of consistent memory and we set a 64 byte size for 148 * the queue entry size (this gives us 256 queue entries per queue). 149 * 150 * This allocation then continues up a further PMCS_SCRATCH_SIZE bytes 151 * that the driver uses as a temporary scratch area for things like 152 * SMP discovery. 153 * 154 * This control area looks like this: 155 * 156 * Offset What 157 * ------------------------------------------------ 158 * 0 IQ 0 Consumer Index 159 * 4 IQ 1 Consumer Index 160 * 8..255 ... 161 * 252..255 IQ 63 Consumer Index 162 * 256 OQ 0 Producer Index 163 * 260 OQ 1 Producer Index 164 * 264..259 .... 165 * 508..511 OQ 63 Producer Index 166 * 512..512+PMCS_SCRATCH_SIZE-1 Scratch area. 167 */ 168 #define IQCI_BASE_OFFSET 0 169 #define IQ_OFFSET(qnum) (IQCI_BASE_OFFSET + (qnum << 2)) 170 #define OQPI_BASE_OFFSET 256 171 #define OQ_OFFSET(qnum) (OQPI_BASE_OFFSET + (qnum << 2)) 172 173 /* 174 * Work related structures. Each one of these structures is paired 175 * with *any* command that is fed to the PMC8X6G via one of the 176 * Inbound Queues. The work structure has a tag to compare with 177 * the message that comes back out of an Outbound Queue. The 178 * work structure also points to the phy which this command is 179 * tied to. It also has a pointer a callback function (if defined). 180 * See that TAG Architecture below for the various kinds of 181 * dispositions of a work structure. 182 */ 183 184 /* 185 * Work Structure States 186 * 187 * NIL -> READY 188 * READY -> NIL 189 * READY -> ONCHIP 190 * ONCHIP -> INTR 191 * INTR -> READY 192 * INTR -> NIL 193 * INTR -> ABORTED 194 * INTR -> TIMED_OUT 195 * ABORTED -> NIL 196 * TIMED_OUT -> NIL 197 */ 198 typedef enum { 199 PMCS_WORK_STATE_NIL = 0, 200 PMCS_WORK_STATE_READY, 201 PMCS_WORK_STATE_ONCHIP, 202 PMCS_WORK_STATE_INTR, 203 PMCS_WORK_STATE_IOCOMPQ, 204 PMCS_WORK_STATE_ABORTED, 205 PMCS_WORK_STATE_TIMED_OUT 206 } pmcs_work_state_t; 207 208 struct pmcwork { 209 STAILQ_ENTRY(pmcwork) next; 210 kmutex_t lock; 211 kcondvar_t sleep_cv; 212 void *ptr; /* linkage or callback function */ 213 void *arg; /* command specific data */ 214 pmcs_phy_t *phy; /* phy who owns this command */ 215 pmcs_xscsi_t *xp; /* Back pointer to xscsi struct */ 216 volatile uint32_t htag; /* tag for this structure */ 217 uint32_t abt_htag; /* Tag of command to be aborted */ 218 uint32_t 219 timer : 27, 220 onwire : 1, 221 dead : 1, 222 state : 3; 223 hrtime_t start; /* timestamp start */ 224 uint32_t ssp_event; /* ssp event */ 225 pmcs_dtype_t dtype; /* stash, incase phy gets cleared */ 226 227 void *last_ptr; 228 void *last_arg; 229 pmcs_phy_t *last_phy; 230 pmcs_xscsi_t *last_xp; 231 uint32_t last_htag; 232 pmcs_work_state_t last_state; 233 hrtime_t finish; 234 }; 235 236 #define PMCS_REC_EVENT 0xffffffff /* event recovery */ 237 238 /* 239 * This structure defines a PMC-Sierra defined firmware header. 240 */ 241 #pragma pack(4) 242 typedef struct { 243 char vendor_id[8]; 244 uint8_t product_id; 245 uint8_t hwrev; 246 uint8_t destination_partition; 247 uint8_t reserved0; 248 uint8_t fwrev[4]; 249 uint32_t firmware_length; 250 uint32_t crc; 251 uint32_t start_address; 252 uint8_t data[]; 253 } pmcs_fw_hdr_t; 254 #pragma pack() 255 256 /* 257 * Offlevel work as a bit pattern. 258 */ 259 #define PMCS_WORK_DISCOVER 0 260 #define PMCS_WORK_ABORT_HANDLE 3 261 #define PMCS_WORK_SPINUP_RELEASE 4 262 #define PMCS_WORK_SAS_HW_ACK 5 263 #define PMCS_WORK_SATA_RUN 6 264 #define PMCS_WORK_RUN_QUEUES 7 265 #define PMCS_WORK_ADD_DMA_CHUNKS 8 266 #define PMCS_WORK_DS_ERR_RECOVERY 9 267 #define PMCS_WORK_SSP_EVT_RECOVERY 10 268 269 /* 270 * The actual values as they appear in work_flags 271 */ 272 #define PMCS_WORK_FLAG_DISCOVER (1 << 0) 273 #define PMCS_WORK_FLAG_ABORT_HANDLE (1 << 3) 274 #define PMCS_WORK_FLAG_SPINUP_RELEASE (1 << 4) 275 #define PMCS_WORK_FLAG_SAS_HW_ACK (1 << 5) 276 #define PMCS_WORK_FLAG_SATA_RUN (1 << 6) 277 #define PMCS_WORK_FLAG_RUN_QUEUES (1 << 7) 278 #define PMCS_WORK_FLAG_ADD_DMA_CHUNKS (1 << 8) 279 #define PMCS_WORK_FLAG_DS_ERR_RECOVERY (1 << 9) 280 #define PMCS_WORK_FLAG_SSP_EVT_RECOVERY (1 << 10) 281 282 /* 283 * This structure is used by this function to test MPI (and interrupts) 284 * after MPI has been started to make sure it's working reliably. 285 */ 286 typedef struct { 287 uint32_t signature; 288 uint32_t count; 289 uint32_t *ptr; 290 } echo_test_t; 291 #define ECHO_SIGNATURE 0xbebebeef 292 293 /* 294 * Tag Architecture. The PMC has 32 bit tags for MPI messages. 295 * We use this tag this way. 296 * 297 * bits what 298 * ------------------------ 299 * 31 done bit 300 * 30..28 tag type 301 * 27..12 rolling serial number 302 * 11..0 index into work area to get pmcwork structure 303 * 304 * A tag type of NONE means that nobody is waiting on any results, 305 * so the interrupt code frees the work structure that has this 306 * tag. 307 * 308 * A tag type of CBACK means that the the interrupt handler 309 * takes the tag 'arg' in the work structure to be a callback 310 * function pointer (see pmcs_cb_t). The callee is responsible 311 * for freeing the work structure that has this tag. 312 * 313 * A tag type of WAIT means that the issuer of the work needs 314 * be woken up from interrupt level when the command completes 315 * (or times out). If work structure tag 'arg' is non-null, 316 * up to 2*PMCS_QENTRY_SIZE bits of data from the Outbound Queue 317 * entry may be copied to the area pointed to by 'arg'. This 318 * allows issuers to get directly at the results of the command 319 * they issed. The synchronization point for the issuer and the 320 * interrupt code for command done notification is the setting 321 * of the 'DONE' bit in the tag as stored in the work structure. 322 */ 323 #define PMCS_TAG_TYPE_FREE 0 324 #define PMCS_TAG_TYPE_NONE 1 325 #define PMCS_TAG_TYPE_CBACK 2 326 #define PMCS_TAG_TYPE_WAIT 3 327 #define PMCS_TAG_TYPE_SHIFT 28 328 #define PMCS_TAG_SERNO_SHIFT 12 329 #define PMCS_TAG_INDEX_SHIFT 0 330 #define PMCS_TAG_TYPE_MASK 0x70000000 331 #define PMCS_TAG_DONE 0x80000000 332 #define PMCS_TAG_SERNO_MASK 0x0ffff000 333 #define PMCS_TAG_INDEX_MASK 0x00000fff 334 #define PMCS_TAG_TYPE(x) \ 335 (((x) & PMCS_TAG_TYPE_MASK) >> PMCS_TAG_TYPE_SHIFT) 336 #define PMCS_TAG_SERNO(x) \ 337 (((x) & PMCS_TAG_SERNO_MASK) >> PMCS_TAG_SERNO_SHIFT) 338 #define PMCS_TAG_INDEX(x) \ 339 (((x) & PMCS_TAG_INDEX_MASK) >> PMCS_TAG_INDEX_SHIFT) 340 #define PMCS_TAG_FREE 0 341 #define PMCS_COMMAND_DONE(x) \ 342 (((x)->htag == PMCS_TAG_FREE) || (((x)->htag & PMCS_TAG_DONE) != 0)) 343 #define PMCS_COMMAND_ACTIVE(x) \ 344 ((x)->htag != PMCS_TAG_FREE && (x)->state == PMCS_WORK_STATE_ONCHIP) 345 346 /* 347 * Miscellaneous Definitions 348 */ 349 #define CLEAN_MESSAGE(m, x) { \ 350 int _j = x; \ 351 while (_j < PMCS_MSG_SIZE) { \ 352 m[_j++] = 0; \ 353 } \ 354 } 355 356 #define COPY_MESSAGE(t, f, a) { \ 357 int _j; \ 358 for (_j = 0; _j < a; _j++) { \ 359 t[_j] = f[_j]; \ 360 } \ 361 while (_j < PMCS_MSG_SIZE) { \ 362 t[_j++] = 0; \ 363 } \ 364 } 365 366 #define PMCS_PHY_ADDRESSABLE(pp) \ 367 ((pp)->level == 0 && (pp)->dtype == SATA && \ 368 ((pp)->sas_address[0] >> 4) != 5) 369 370 #define RESTART_DISCOVERY(pwp) \ 371 ASSERT(!mutex_owned(&pwp->config_lock)); \ 372 mutex_enter(&pwp->config_lock); \ 373 pwp->config_changed = B_TRUE; \ 374 mutex_exit(&pwp->config_lock); \ 375 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 376 377 #define RESTART_DISCOVERY_LOCKED(pwp) \ 378 ASSERT(mutex_owned(&pwp->config_lock)); \ 379 pwp->config_changed = B_TRUE; \ 380 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 381 382 #define PHY_CHANGED(pwp, p) \ 383 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, p, NULL, "%s changed in " \ 384 "%s line %d", p->path, __func__, __LINE__); \ 385 p->changed = 1 386 387 #define PHY_CHANGED_AT_LOCATION(pwp, p, func, line) \ 388 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, p, NULL, "%s changed in " \ 389 "%s line %d", p->path, func, line); \ 390 p->changed = 1 391 392 #define PHY_TYPE(pptr) \ 393 (((pptr)->dtype == NOTHING)? "NOTHING" : \ 394 (((pptr)->dtype == SATA)? "SATA" : \ 395 (((pptr)->dtype == SAS)? "SAS" : "EXPANDER"))) 396 397 #define IS_ROOT_PHY(pptr) (pptr->parent == NULL) 398 399 #define PMCS_HIPRI(pwp, oq, c) \ 400 (pwp->hipri_queue & (1 << PMCS_IQ_OTHER)) ? \ 401 (PMCS_IOMB_HIPRI | PMCS_IOMB_IN_SAS(oq, c)) : \ 402 (PMCS_IOMB_IN_SAS(oq, c)) 403 404 #define SCHEDULE_WORK(hwp, wrk) \ 405 (void) atomic_set_long_excl(&hwp->work_flags, wrk) 406 407 /* 408 * Check to see if the requested work bit is set. Either way, the bit will 409 * be cleared upon return. 410 */ 411 #define WORK_SCHEDULED(hwp, wrk) \ 412 (atomic_clear_long_excl(&hwp->work_flags, wrk) == 0) 413 414 /* 415 * Check to see if the requested work bit is set. The value will not be 416 * changed in this case. The atomic_xx_nv operations can be quite expensive 417 * so this should not be used in non-DEBUG code. 418 */ 419 #define WORK_IS_SCHEDULED(hwp, wrk) \ 420 ((atomic_and_ulong_nv(&hwp->work_flags, (ulong_t)-1) & (1 << wrk)) != 0) 421 422 #define WAIT_FOR(p, t, r) \ 423 r = 0; \ 424 while (!PMCS_COMMAND_DONE(p)) { \ 425 clock_t tmp = cv_timedwait(&p->sleep_cv, \ 426 &p->lock, ddi_get_lbolt() + \ 427 drv_usectohz(t * 1000)); \ 428 if (!PMCS_COMMAND_DONE(p) && tmp < 0) { \ 429 r = 1; \ 430 break; \ 431 } \ 432 } 433 434 /* 435 * Signal the next I/O completion thread to start running. 436 */ 437 438 #define PMCS_CQ_RUN_LOCKED(hwp) \ 439 if (!STAILQ_EMPTY(&hwp->cq) || hwp->iocomp_cb_head) { \ 440 pmcs_cq_thr_info_t *cqti; \ 441 cqti = &hwp->cq_info.cq_thr_info \ 442 [hwp->cq_info.cq_next_disp_thr]; \ 443 hwp->cq_info.cq_next_disp_thr++; \ 444 if (hwp->cq_info.cq_next_disp_thr == \ 445 hwp->cq_info.cq_threads) { \ 446 hwp->cq_info.cq_next_disp_thr = 0; \ 447 } \ 448 mutex_enter(&cqti->cq_thr_lock); \ 449 cv_signal(&cqti->cq_cv); \ 450 mutex_exit(&cqti->cq_thr_lock); \ 451 } \ 452 453 #define PMCS_CQ_RUN(hwp) \ 454 mutex_enter(&hwp->cq_lock); \ 455 PMCS_CQ_RUN_LOCKED(hwp); \ 456 mutex_exit(&hwp->cq_lock); 457 458 459 /* 460 * Watchdog/SCSA timer definitions 461 */ 462 /* usecs to SCSA watchdog ticks */ 463 #define US2WT(x) (x)/10 464 465 /* 466 * More misc 467 */ 468 #define BYTE0(x) (((x) >> 0) & 0xff) 469 #define BYTE1(x) (((x) >> 8) & 0xff) 470 #define BYTE2(x) (((x) >> 16) & 0xff) 471 #define BYTE3(x) (((x) >> 24) & 0xff) 472 #define BYTE4(x) (((x) >> 32) & 0xff) 473 #define BYTE5(x) (((x) >> 40) & 0xff) 474 #define BYTE6(x) (((x) >> 48) & 0xff) 475 #define BYTE7(x) (((x) >> 56) & 0xff) 476 #define WORD0(x) (((x) >> 0) & 0xffff) 477 #define WORD1(x) (((x) >> 16) & 0xffff) 478 #define WORD2(x) (((x) >> 32) & 0xffff) 479 #define WORD3(x) (((x) >> 48) & 0xffff) 480 #define DWORD0(x) ((uint32_t)(x)) 481 #define DWORD1(x) ((uint32_t)(((uint64_t)x) >> 32)) 482 483 #define SAS_ADDR_FMT "0x%02x%02x%02x%02x%02x%02x%02x%02x" 484 #define SAS_ADDR_PRT(x) x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7] 485 486 #define PMCS_VALID_LINK_RATE(r) \ 487 ((r == SAS_LINK_RATE_1_5GBIT) || (r == SAS_LINK_RATE_3GBIT) || \ 488 (r == SAS_LINK_RATE_6GBIT)) 489 490 /* 491 * This is here to avoid inclusion of <sys/ctype.h> which is not lint clean. 492 */ 493 #define HEXDIGIT(x) (((x) >= '0' && (x) <= '9') || \ 494 ((x) >= 'a' && (x) <= 'f') || ((x) >= 'A' && (x) <= 'F')) 495 496 497 typedef void (*pmcs_cb_t) (pmcs_hw_t *, pmcwork_t *, uint32_t *); 498 499 /* 500 * Defines and structure used for tracing/logging information 501 */ 502 503 #define PMCS_TBUF_ELEM_SIZE 120 504 505 #ifdef DEBUG 506 #define PMCS_TBUF_NUM_ELEMS_DEF 100000 507 #else 508 #define PMCS_TBUF_NUM_ELEMS_DEF 15000 509 #endif 510 511 #define PMCS_TBUF_UA_MAX_SIZE 32 512 typedef struct { 513 /* Target-specific data */ 514 uint16_t target_num; 515 char target_ua[PMCS_TBUF_UA_MAX_SIZE]; 516 /* PHY-specific data */ 517 uint8_t phy_sas_address[8]; 518 char phy_path[32]; 519 pmcs_dtype_t phy_dtype; 520 /* Log data */ 521 timespec_t timestamp; 522 char buf[PMCS_TBUF_ELEM_SIZE]; 523 } pmcs_tbuf_t; 524 525 /* 526 * Firmware event log header format 527 */ 528 529 typedef struct pmcs_fw_event_hdr_s { 530 uint32_t fw_el_signature; 531 uint32_t fw_el_entry_start_offset; 532 uint32_t fw_el_rsvd1; 533 uint32_t fw_el_buf_size; 534 uint32_t fw_el_rsvd2; 535 uint32_t fw_el_oldest_idx; 536 uint32_t fw_el_latest_idx; 537 uint32_t fw_el_entry_size; 538 } pmcs_fw_event_hdr_t; 539 540 #ifdef __cplusplus 541 } 542 #endif 543 #endif /* _PMCS_DEF_H */ 544