1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 #ifndef _PMCS_DEF_H 25 #define _PMCS_DEF_H 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 typedef enum { 31 NOTHING, /* nothing connected here */ 32 SATA, /* SATA connection */ 33 SAS, /* direct or indirect SAS connection */ 34 EXPANDER, /* connection to an expander */ 35 NEW /* Brand new device (pending state) */ 36 } pmcs_dtype_t; 37 38 /* 39 * This structure defines a PHY device that represents what we 40 * are connected to. 41 * 42 * The eight real physical PHYs that are in the PMC8X6G are represented 43 * as an array of eight of these structures which define what these 44 * real PHYs are connected to. 45 * 46 * Depending upon what is actually connected to each PHY, the 47 * type set will define what we're connected to. If it is 48 * a direct SATA connection, the phy will describe a SATA endpoint 49 * If it is a direct SAS connection, it will describe a SAS 50 * endpoint. 51 * 52 * If it is an EXPANDER, this will describe the edge of an expander. 53 * As we perform discovery on what is in an EXPANDER we define an 54 * additional list of phys that represent what the Expander is connected to. 55 */ 56 #define PMCS_HW_MIN_LINK_RATE SAS_LINK_RATE_1_5GBIT 57 #define PMCS_HW_MAX_LINK_RATE SAS_LINK_RATE_6GBIT 58 59 #define PMCS_INVALID_DEVICE_ID 0xffffffff 60 #define PMCS_PHY_INVALID_PORT_ID 0xf 61 62 #define PMCS_PM_MAX_NAMELEN 16 63 #define PMCS_MAX_REENUMERATE 2 /* Maximum re-enumeration attempts */ 64 65 /* 66 * Number of usecs to wait after last noted activate/deactivate callback 67 * before possibly restarting discovery 68 */ 69 #define PMCS_REDISCOVERY_DELAY (5 * MICROSEC) 70 71 struct pmcs_phy { 72 pmcs_phy_t *sibling; /* sibling phy */ 73 pmcs_phy_t *parent; /* parent phy */ 74 pmcs_phy_t *children; /* head of list of children */ 75 pmcs_phy_t *dead_next; /* dead PHY list link */ 76 list_node_t list_node; /* list element */ 77 uint32_t device_id; /* PMC8X6G device handle */ 78 uint32_t 79 ncphy : 8, /* # of contained phys for expander */ 80 hw_event_ack : 24; /* XXX: first level phy event acked */ 81 uint8_t phynum; /* phy number on parent expander */ 82 uint8_t width; /* how many phys wide */ 83 uint8_t ds_recovery_retries; /* # error retry attempts */ 84 uint8_t ds_prev_good_recoveries; /* # successful recoveries */ 85 clock_t prev_recovery; /* previous successful recovery */ 86 clock_t last_good_recovery; /* oldest successful recovery */ 87 /* within PMCS_MAX_DS_RECOVERY_TIME time frame */ 88 pmcs_dtype_t dtype; /* current dtype of the phy */ 89 pmcs_dtype_t pend_dtype; /* new dtype (pending change) */ 90 uint32_t 91 level : 8, /* level in expander tree */ 92 tolerates_sas2 : 1, /* tolerates SAS2 SMP */ 93 spinup_hold : 1, /* spinup hold needs releasing */ 94 atdt : 3, /* attached device type */ 95 portid : 4, /* PMC8X6G port context */ 96 link_rate : 4, /* current supported speeds */ 97 valid_device_id : 1, /* device id is valid */ 98 abort_sent : 1, /* we've sent an abort */ 99 abort_pending : 1, /* we have an abort pending */ 100 need_rl_ext : 1, /* need SATA RL_EXT recocvery */ 101 subsidiary : 1, /* this is part of a wide phy */ 102 configured : 1, /* is configured */ 103 dead : 1, /* dead */ 104 changed : 1, /* this phy is changing */ 105 reenumerate : 1, /* attempt re-enumeration */ 106 deregister_wait : 1; /* phy waiting to get deregistered */ 107 clock_t config_stop; /* When config attempts will stop */ 108 hrtime_t abort_all_start; 109 kcondvar_t abort_all_cv; /* Wait for ABORT_ALL completion */ 110 kmutex_t phy_lock; 111 volatile uint32_t ref_count; /* Targets & work on this PHY */ 112 uint32_t enum_attempts; /* # of enumeration attempts */ 113 uint8_t sas_address[8]; /* SAS address for this PHY */ 114 struct { 115 uint32_t 116 prog_min_rate :4, 117 hw_min_rate :4, 118 prog_max_rate :4, 119 hw_max_rate :4, 120 reserved :16; 121 } state; 122 char path[32]; /* path name for this phy */ 123 pmcs_hw_t *pwp; /* back ptr to hba struct */ 124 pmcs_iport_t *iport; /* back ptr to the iport handle */ 125 pmcs_iport_t *last_iport; /* last iport this PHY was on */ 126 pmcs_xscsi_t *target; /* back ptr to current target */ 127 kstat_t *phy_stats; /* kstats for this phy */ 128 /* 129 * Attached port phy mask and target port phymask. With 16 bytes 130 * we can represent a phymask for anything with up to 64 ports 131 */ 132 uint64_t att_port_pm; /* att port pm for this PHY */ 133 uint64_t att_port_pm_tmp; /* Temp area for wide-ports */ 134 char att_port_pm_str[PMCS_PM_MAX_NAMELEN + 1]; 135 uint64_t tgt_port_pm; /* tgt port pm for this PHY */ 136 uint64_t tgt_port_pm_tmp; /* Temp area for wide-ports */ 137 char tgt_port_pm_str[PMCS_PM_MAX_NAMELEN + 1]; 138 smp_routing_attr_t routing_attr; /* Routing attr. from discover resp. */ 139 smp_routing_attr_t routing_method; /* Actual routing method used. */ 140 smp_report_general_resp_t rg_resp; /* Response to REPORT_GENERAL */ 141 smp_discover_resp_t disc_resp; /* Response to DISCOVER */ 142 }; 143 144 /* maximum number of ds recovery retries (ds_recovery_retries) */ 145 #define PMCS_MAX_DS_RECOVERY_RETRIES 10 146 147 /* max time allowed for successful recovery */ 148 #define PMCS_MAX_DS_RECOVERY_TIME (60 * 1000000) /* 60 seconds */ 149 150 /* ds recovery on same same phy is not allowed within this interval */ 151 #define PMCS_DS_RECOVERY_INTERVAL (1000000) /* 1 second */ 152 153 154 /* 155 * Inbound and Outbound Queue Related Definitions. 156 * 157 * The PMC8X6G has a programmable number of inbound and outbound circular 158 * queues for use in message passing between the host and the PMC8X6G 159 * (up to 64 queues for the Rev C Chip). This driver does not use all 160 * possible queues. 161 * 162 * Each Queue is given 4K of consistent memory and we set a 64 byte size for 163 * the queue entry size (this gives us 256 queue entries per queue). 164 * 165 * This allocation then continues up a further PMCS_SCRATCH_SIZE bytes 166 * that the driver uses as a temporary scratch area for things like 167 * SMP discovery. 168 * 169 * This control area looks like this: 170 * 171 * Offset What 172 * ------------------------------------------------ 173 * 0 IQ 0 Consumer Index 174 * 4 IQ 1 Consumer Index 175 * 8..255 ... 176 * 252..255 IQ 63 Consumer Index 177 * 256 OQ 0 Producer Index 178 * 260 OQ 1 Producer Index 179 * 264..259 .... 180 * 508..511 OQ 63 Producer Index 181 * 512..512+PMCS_SCRATCH_SIZE-1 Scratch area. 182 */ 183 #define IQCI_BASE_OFFSET 0 184 #define IQ_OFFSET(qnum) (IQCI_BASE_OFFSET + (qnum << 2)) 185 #define OQPI_BASE_OFFSET 256 186 #define OQ_OFFSET(qnum) (OQPI_BASE_OFFSET + (qnum << 2)) 187 188 /* 189 * Work related structures. Each one of these structures is paired 190 * with *any* command that is fed to the PMC8X6G via one of the 191 * Inbound Queues. The work structure has a tag to compare with 192 * the message that comes back out of an Outbound Queue. The 193 * work structure also points to the phy which this command is 194 * tied to. It also has a pointer a callback function (if defined). 195 * See that TAG Architecture below for the various kinds of 196 * dispositions of a work structure. 197 */ 198 199 /* 200 * Work Structure States 201 * 202 * NIL -> READY 203 * READY -> NIL 204 * READY -> ONCHIP 205 * ONCHIP -> INTR 206 * INTR -> READY 207 * INTR -> NIL 208 * INTR -> ABORTED 209 * INTR -> TIMED_OUT 210 * ABORTED -> NIL 211 * TIMED_OUT -> NIL 212 */ 213 typedef enum { 214 PMCS_WORK_STATE_NIL = 0, 215 PMCS_WORK_STATE_READY, 216 PMCS_WORK_STATE_ONCHIP, 217 PMCS_WORK_STATE_INTR, 218 PMCS_WORK_STATE_IOCOMPQ, 219 PMCS_WORK_STATE_ABORTED, 220 PMCS_WORK_STATE_TIMED_OUT 221 } pmcs_work_state_t; 222 223 struct pmcwork { 224 STAILQ_ENTRY(pmcwork) next; 225 kmutex_t lock; 226 kcondvar_t sleep_cv; 227 void *ptr; /* linkage or callback function */ 228 void *arg; /* command specific data */ 229 pmcs_phy_t *phy; /* phy who owns this command */ 230 pmcs_xscsi_t *xp; /* Back pointer to xscsi struct */ 231 volatile uint32_t htag; /* tag for this structure */ 232 uint32_t abt_htag; /* Tag of command to be aborted */ 233 uint32_t 234 timer : 27, 235 onwire : 1, 236 dead : 1, 237 state : 3; 238 hrtime_t start; /* timestamp start */ 239 uint32_t ssp_event; /* ssp event */ 240 pmcs_dtype_t dtype; /* stash, incase phy gets cleared */ 241 242 void *last_ptr; 243 void *last_arg; 244 pmcs_phy_t *last_phy; 245 pmcs_xscsi_t *last_xp; 246 uint32_t last_htag; 247 pmcs_work_state_t last_state; 248 hrtime_t finish; 249 }; 250 251 #define PMCS_REC_EVENT 0xffffffff /* event recovery */ 252 253 /* 254 * This structure defines a PMC-Sierra defined firmware header. 255 */ 256 #pragma pack(4) 257 typedef struct { 258 char vendor_id[8]; 259 uint8_t product_id; 260 uint8_t hwrev; 261 uint8_t destination_partition; 262 uint8_t reserved0; 263 uint8_t fwrev[4]; 264 uint32_t firmware_length; 265 uint32_t crc; 266 uint32_t start_address; 267 uint8_t data[]; 268 } pmcs_fw_hdr_t; 269 #pragma pack() 270 271 /* 272 * Offlevel work as a bit pattern. 273 */ 274 #define PMCS_WORK_DISCOVER 0 275 #define PMCS_WORK_ABORT_HANDLE 3 276 #define PMCS_WORK_SPINUP_RELEASE 4 277 #define PMCS_WORK_SAS_HW_ACK 5 278 #define PMCS_WORK_SATA_RUN 6 279 #define PMCS_WORK_RUN_QUEUES 7 280 #define PMCS_WORK_ADD_DMA_CHUNKS 8 281 #define PMCS_WORK_DS_ERR_RECOVERY 9 282 #define PMCS_WORK_SSP_EVT_RECOVERY 10 283 #define PMCS_WORK_DEREGISTER_DEV 11 284 #define PMCS_WORK_DUMP_REGS 12 285 286 /* 287 * The actual values as they appear in work_flags 288 */ 289 #define PMCS_WORK_FLAG_DISCOVER (1 << 0) 290 #define PMCS_WORK_FLAG_ABORT_HANDLE (1 << 3) 291 #define PMCS_WORK_FLAG_SPINUP_RELEASE (1 << 4) 292 #define PMCS_WORK_FLAG_SAS_HW_ACK (1 << 5) 293 #define PMCS_WORK_FLAG_SATA_RUN (1 << 6) 294 #define PMCS_WORK_FLAG_RUN_QUEUES (1 << 7) 295 #define PMCS_WORK_FLAG_ADD_DMA_CHUNKS (1 << 8) 296 #define PMCS_WORK_FLAG_DS_ERR_RECOVERY (1 << 9) 297 #define PMCS_WORK_FLAG_SSP_EVT_RECOVERY (1 << 10) 298 #define PMCS_WORK_FLAG_DEREGISTER_DEV (1 << 11) 299 #define PMCS_WORK_FLAG_DUMP_REGS (1 << 12) 300 301 /* 302 * This structure is used by this function to test MPI (and interrupts) 303 * after MPI has been started to make sure it's working reliably. 304 */ 305 typedef struct { 306 uint32_t signature; 307 uint32_t count; 308 uint32_t *ptr; 309 } echo_test_t; 310 #define ECHO_SIGNATURE 0xbebebeef 311 312 /* 313 * Tag Architecture. The PMC has 32 bit tags for MPI messages. 314 * We use this tag this way. 315 * 316 * bits what 317 * ------------------------ 318 * 31 done bit 319 * 30..28 tag type 320 * 27..12 rolling serial number 321 * 11..0 index into work area to get pmcwork structure 322 * 323 * A tag type of NONE means that nobody is waiting on any results, 324 * so the interrupt code frees the work structure that has this 325 * tag. 326 * 327 * A tag type of CBACK means that the the interrupt handler 328 * takes the tag 'arg' in the work structure to be a callback 329 * function pointer (see pmcs_cb_t). The callee is responsible 330 * for freeing the work structure that has this tag. 331 * 332 * A tag type of WAIT means that the issuer of the work needs 333 * be woken up from interrupt level when the command completes 334 * (or times out). If work structure tag 'arg' is non-null, 335 * up to 2*PMCS_QENTRY_SIZE bits of data from the Outbound Queue 336 * entry may be copied to the area pointed to by 'arg'. This 337 * allows issuers to get directly at the results of the command 338 * they issed. The synchronization point for the issuer and the 339 * interrupt code for command done notification is the setting 340 * of the 'DONE' bit in the tag as stored in the work structure. 341 */ 342 #define PMCS_TAG_TYPE_FREE 0 343 #define PMCS_TAG_TYPE_NONE 1 344 #define PMCS_TAG_TYPE_CBACK 2 345 #define PMCS_TAG_TYPE_WAIT 3 346 #define PMCS_TAG_TYPE_SHIFT 28 347 #define PMCS_TAG_SERNO_SHIFT 12 348 #define PMCS_TAG_INDEX_SHIFT 0 349 #define PMCS_TAG_TYPE_MASK 0x70000000 350 #define PMCS_TAG_DONE 0x80000000 351 #define PMCS_TAG_SERNO_MASK 0x0ffff000 352 #define PMCS_TAG_INDEX_MASK 0x00000fff 353 #define PMCS_TAG_TYPE(x) \ 354 (((x) & PMCS_TAG_TYPE_MASK) >> PMCS_TAG_TYPE_SHIFT) 355 #define PMCS_TAG_SERNO(x) \ 356 (((x) & PMCS_TAG_SERNO_MASK) >> PMCS_TAG_SERNO_SHIFT) 357 #define PMCS_TAG_INDEX(x) \ 358 (((x) & PMCS_TAG_INDEX_MASK) >> PMCS_TAG_INDEX_SHIFT) 359 #define PMCS_TAG_FREE 0 360 #define PMCS_COMMAND_DONE(x) \ 361 (((x)->htag == PMCS_TAG_FREE) || (((x)->htag & PMCS_TAG_DONE) != 0)) 362 #define PMCS_COMMAND_ACTIVE(x) \ 363 ((x)->htag != PMCS_TAG_FREE && (x)->state == PMCS_WORK_STATE_ONCHIP) 364 365 /* 366 * Miscellaneous Definitions 367 */ 368 #define CLEAN_MESSAGE(m, x) { \ 369 int _j = x; \ 370 while (_j < PMCS_MSG_SIZE) { \ 371 m[_j++] = 0; \ 372 } \ 373 } 374 375 #define COPY_MESSAGE(t, f, a) { \ 376 int _j; \ 377 for (_j = 0; _j < a; _j++) { \ 378 t[_j] = f[_j]; \ 379 } \ 380 while (_j < PMCS_MSG_SIZE) { \ 381 t[_j++] = 0; \ 382 } \ 383 } 384 385 #define PMCS_PHY_ADDRESSABLE(pp) \ 386 ((pp)->level == 0 && (pp)->dtype == SATA && \ 387 ((pp)->sas_address[0] >> 4) != 5) 388 389 #define RESTART_DISCOVERY(pwp) \ 390 ASSERT(!mutex_owned(&pwp->config_lock)); \ 391 mutex_enter(&pwp->config_lock); \ 392 pwp->config_changed = B_TRUE; \ 393 mutex_exit(&pwp->config_lock); \ 394 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 395 396 #define RESTART_DISCOVERY_LOCKED(pwp) \ 397 ASSERT(mutex_owned(&pwp->config_lock)); \ 398 pwp->config_changed = B_TRUE; \ 399 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 400 401 #define PHY_CHANGED(pwp, p) \ 402 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, p, NULL, "%s changed in " \ 403 "%s line %d", p->path, __func__, __LINE__); \ 404 p->changed = 1; \ 405 p->enum_attempts = 0 406 407 #define PHY_CHANGED_AT_LOCATION(pwp, p, func, line) \ 408 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, p, NULL, "%s changed in " \ 409 "%s line %d", p->path, func, line); \ 410 p->changed = 1; \ 411 p->enum_attempts = 0 412 413 #define PHY_TYPE(pptr) \ 414 (((pptr)->dtype == NOTHING)? "NOTHING" : \ 415 (((pptr)->dtype == SATA)? "SATA" : \ 416 (((pptr)->dtype == SAS)? "SAS" : "EXPANDER"))) 417 418 #define IS_ROOT_PHY(pptr) (pptr->parent == NULL) 419 420 #define PMCS_HIPRI(pwp, oq, c) \ 421 (pwp->hipri_queue & (1 << PMCS_IQ_OTHER)) ? \ 422 (PMCS_IOMB_HIPRI | PMCS_IOMB_IN_SAS(oq, c)) : \ 423 (PMCS_IOMB_IN_SAS(oq, c)) 424 425 #define SCHEDULE_WORK(hwp, wrk) \ 426 (void) atomic_set_long_excl(&hwp->work_flags, wrk) 427 428 /* 429 * Check to see if the requested work bit is set. Either way, the bit will 430 * be cleared upon return. 431 */ 432 #define WORK_SCHEDULED(hwp, wrk) \ 433 (atomic_clear_long_excl(&hwp->work_flags, wrk) == 0) 434 435 /* 436 * Check to see if the requested work bit is set. The value will not be 437 * changed in this case. The atomic_xx_nv operations can be quite expensive 438 * so this should not be used in non-DEBUG code. 439 */ 440 #define WORK_IS_SCHEDULED(hwp, wrk) \ 441 ((atomic_and_ulong_nv(&hwp->work_flags, (ulong_t)-1) & (1 << wrk)) != 0) 442 443 #define WAIT_FOR(p, t, r) \ 444 clock_t _lb = ddi_get_lbolt(); \ 445 r = 0; \ 446 while (!PMCS_COMMAND_DONE(p)) { \ 447 clock_t _ret = cv_timedwait(&p->sleep_cv, \ 448 &p->lock, _lb + drv_usectohz(t * 1000)); \ 449 if (!PMCS_COMMAND_DONE(p) && _ret < 0) { \ 450 r = 1; \ 451 break; \ 452 } \ 453 } 454 455 /* 456 * Signal the next I/O completion thread to start running. 457 */ 458 459 #define PMCS_CQ_RUN_LOCKED(hwp) \ 460 if (!STAILQ_EMPTY(&hwp->cq) || hwp->iocomp_cb_head) { \ 461 pmcs_cq_thr_info_t *cqti; \ 462 cqti = &hwp->cq_info.cq_thr_info \ 463 [hwp->cq_info.cq_next_disp_thr]; \ 464 hwp->cq_info.cq_next_disp_thr++; \ 465 if (hwp->cq_info.cq_next_disp_thr == \ 466 hwp->cq_info.cq_threads) { \ 467 hwp->cq_info.cq_next_disp_thr = 0; \ 468 } \ 469 mutex_enter(&cqti->cq_thr_lock); \ 470 cv_signal(&cqti->cq_cv); \ 471 mutex_exit(&cqti->cq_thr_lock); \ 472 } \ 473 474 #define PMCS_CQ_RUN(hwp) \ 475 mutex_enter(&hwp->cq_lock); \ 476 PMCS_CQ_RUN_LOCKED(hwp); \ 477 mutex_exit(&hwp->cq_lock); 478 479 480 /* 481 * Watchdog/SCSA timer definitions 482 */ 483 /* usecs to SCSA watchdog ticks */ 484 #define US2WT(x) (x)/10 485 486 /* 487 * More misc 488 */ 489 #define BYTE0(x) (((x) >> 0) & 0xff) 490 #define BYTE1(x) (((x) >> 8) & 0xff) 491 #define BYTE2(x) (((x) >> 16) & 0xff) 492 #define BYTE3(x) (((x) >> 24) & 0xff) 493 #define BYTE4(x) (((x) >> 32) & 0xff) 494 #define BYTE5(x) (((x) >> 40) & 0xff) 495 #define BYTE6(x) (((x) >> 48) & 0xff) 496 #define BYTE7(x) (((x) >> 56) & 0xff) 497 #define WORD0(x) (((x) >> 0) & 0xffff) 498 #define WORD1(x) (((x) >> 16) & 0xffff) 499 #define WORD2(x) (((x) >> 32) & 0xffff) 500 #define WORD3(x) (((x) >> 48) & 0xffff) 501 #define DWORD0(x) ((uint32_t)(x)) 502 #define DWORD1(x) ((uint32_t)(((uint64_t)x) >> 32)) 503 504 #define SAS_ADDR_FMT "0x%02x%02x%02x%02x%02x%02x%02x%02x" 505 #define SAS_ADDR_PRT(x) x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7] 506 507 #define PMCS_VALID_LINK_RATE(r) \ 508 ((r == SAS_LINK_RATE_1_5GBIT) || (r == SAS_LINK_RATE_3GBIT) || \ 509 (r == SAS_LINK_RATE_6GBIT)) 510 511 /* 512 * This is here to avoid inclusion of <sys/ctype.h> which is not lint clean. 513 */ 514 #define HEXDIGIT(x) (((x) >= '0' && (x) <= '9') || \ 515 ((x) >= 'a' && (x) <= 'f') || ((x) >= 'A' && (x) <= 'F')) 516 517 #define NSECS_PER_SEC 1000000000UL 518 519 520 typedef void (*pmcs_cb_t) (pmcs_hw_t *, pmcwork_t *, uint32_t *); 521 522 /* 523 * Defines and structure used for tracing/logging information 524 */ 525 526 #define PMCS_TBUF_ELEM_SIZE 120 527 #define PMCS_TBUF_NUM_ELEMS_DEF 100000 528 529 #define PMCS_TBUF_UA_MAX_SIZE 32 530 typedef struct { 531 /* Target-specific data */ 532 uint16_t target_num; 533 char target_ua[PMCS_TBUF_UA_MAX_SIZE]; 534 /* PHY-specific data */ 535 uint8_t phy_sas_address[8]; 536 char phy_path[32]; 537 pmcs_dtype_t phy_dtype; 538 /* Log data */ 539 timespec_t timestamp; 540 uint64_t fw_timestamp; 541 char buf[PMCS_TBUF_ELEM_SIZE]; 542 } pmcs_tbuf_t; 543 544 /* 545 * Firmware event log header format 546 */ 547 typedef struct pmcs_fw_event_hdr_s { 548 uint32_t fw_el_signature; 549 uint32_t fw_el_entry_start_offset; 550 uint32_t fw_el_rsvd1; 551 uint32_t fw_el_buf_size; 552 uint32_t fw_el_rsvd2; 553 uint32_t fw_el_oldest_idx; 554 uint32_t fw_el_latest_idx; 555 uint32_t fw_el_entry_size; 556 } pmcs_fw_event_hdr_t; 557 558 /* 559 * Firmware event log entry format 560 */ 561 typedef struct pmcs_fw_event_entry_s { 562 uint32_t num_words : 3, 563 reserved : 25, 564 severity: 4; 565 uint32_t ts_upper; 566 uint32_t ts_lower; 567 uint32_t seq_num; 568 uint32_t logw0; 569 uint32_t logw1; 570 uint32_t logw2; 571 uint32_t logw3; 572 } pmcs_fw_event_entry_t; 573 574 #define PMCS_FWLOG_TIMER_DIV 8 /* fw timer has 8ns granularity */ 575 #define PMCS_FWLOG_AAP1_SIG 0x1234AAAA 576 #define PMCS_FWLOG_IOP_SIG 0x5678CCCC 577 578 /* 579 * Receptacle information 580 */ 581 #define PMCS_NUM_RECEPTACLES 2 582 583 #define PMCS_RECEPT_LABEL_0 "SAS0" 584 #define PMCS_RECEPT_LABEL_1 "SAS1" 585 586 #define PMCS_RECEPT_PM_0 "f0" 587 #define PMCS_RECEPT_PM_1 "f" 588 589 #ifdef __cplusplus 590 } 591 #endif 592 #endif /* _PMCS_DEF_H */ 593