1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * This file is the principle header file for the PMCS driver 27 */ 28 #ifndef _PMCS_H 29 #define _PMCS_H 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 #include <sys/cpuvar.h> 36 #include <sys/ddi.h> 37 #include <sys/sunddi.h> 38 #include <sys/modctl.h> 39 #include <sys/pci.h> 40 #include <sys/pcie.h> 41 #include <sys/isa_defs.h> 42 #include <sys/sunmdi.h> 43 #include <sys/mdi_impldefs.h> 44 #include <sys/scsi/scsi.h> 45 #include <sys/scsi/impl/scsi_reset_notify.h> 46 #include <sys/scsi/impl/scsi_sas.h> 47 #include <sys/scsi/impl/smp_transport.h> 48 #include <sys/scsi/generic/sas.h> 49 #include <sys/scsi/generic/smp_frames.h> 50 #include <sys/atomic.h> 51 #include <sys/byteorder.h> 52 #include <sys/bitmap.h> 53 #include <sys/queue.h> 54 #include <sys/sdt.h> 55 #include <sys/ddifm.h> 56 #include <sys/fm/protocol.h> 57 #include <sys/fm/util.h> 58 #include <sys/fm/io/ddi.h> 59 #include <sys/scsi/impl/spc3_types.h> 60 61 typedef struct pmcs_hw pmcs_hw_t; 62 typedef struct pmcs_iport pmcs_iport_t; 63 typedef struct pmcs_phy pmcs_phy_t; 64 typedef struct lsas_cmd lsas_cmd_t; 65 typedef struct lsas_result lsas_result_t; 66 typedef struct lsata_cmd lsata_cmd_t; 67 typedef struct lsata_result lsata_result_t; 68 typedef struct pmcwork pmcwork_t; 69 typedef struct pmcs_cmd pmcs_cmd_t; 70 typedef struct pmcs_xscsi pmcs_xscsi_t; 71 typedef struct pmcs_lun pmcs_lun_t; 72 typedef struct pmcs_chunk pmcs_chunk_t; 73 74 #include <sys/scsi/adapters/pmcs/pmcs_param.h> 75 #include <sys/scsi/adapters/pmcs/pmcs_reg.h> 76 #include <sys/scsi/adapters/pmcs/pmcs_mpi.h> 77 #include <sys/scsi/adapters/pmcs/pmcs_iomb.h> 78 #include <sys/scsi/adapters/pmcs/pmcs_sgl.h> 79 80 #include <sys/scsi/adapters/pmcs/ata.h> 81 #include <sys/scsi/adapters/pmcs/pmcs_def.h> 82 #include <sys/scsi/adapters/pmcs/pmcs_proto.h> 83 #include <sys/scsi/adapters/pmcs/pmcs_scsa.h> 84 #include <sys/scsi/adapters/pmcs/pmcs_smhba.h> 85 86 #define PMCS_MAX_UA_SIZE 32 87 88 struct pmcs_xscsi { 89 uint32_t 90 ca : 1, /* SATA specific */ 91 ncq : 1, /* SATA specific */ 92 pio : 1, /* SATA specific */ 93 special_needed : 1, /* SATA specific */ 94 special_running : 1, /* SATA specific */ 95 reset_success : 1, /* last reset ok */ 96 reset_wait : 1, /* wait for reset */ 97 resetting : 1, /* now resetting */ 98 recover_wait : 1, /* wait for recovery */ 99 recovering : 1, /* now recovering */ 100 event_recovery : 1, /* event recovery */ 101 draining : 1, 102 new : 1, 103 assigned : 1, 104 dev_gone : 1, 105 phy_addressable : 1, /* Direct attach SATA */ 106 dev_state : 4; 107 uint16_t maxdepth; 108 uint16_t qdepth; 109 uint16_t actv_cnt; 110 uint16_t target_num; 111 /* statlock protects both target stats and the special queue (sq) */ 112 kmutex_t statlock; 113 int32_t ref_count; 114 dev_info_t *dip; /* Solaris device dip */ 115 pmcs_phy_t *phy; 116 STAILQ_HEAD(wqh, pmcs_cmd) wq; 117 pmcs_cmd_t *wq_recovery_tail; /* See below */ 118 kmutex_t wqlock; 119 STAILQ_HEAD(aqh, pmcs_cmd) aq; 120 kmutex_t aqlock; 121 STAILQ_HEAD(sqh, pmcs_cmd) sq; /* SATA specific */ 122 uint32_t tagmap; /* SATA specific */ 123 pmcs_hw_t *pwp; 124 ddi_soft_state_bystr *lun_sstate; 125 uint64_t capacity; /* SATA specific */ 126 char unit_address[PMCS_MAX_UA_SIZE]; 127 kcondvar_t reset_cv; 128 kcondvar_t abort_cv; 129 char *ua; 130 pmcs_dtype_t dtype; 131 }; 132 133 /* 134 * wq_recovery_tail in the pmcs_xscsi structure is a pointer to a command in 135 * the wait queue (wq). That pointer is the last command in the wait queue 136 * that needs to be reissued after device state recovery is complete. Commands 137 * that need to be retried are reinserted into the wq after wq_recovery_tail 138 * to maintain the order in which the commands were originally submitted. 139 */ 140 141 #define PMCS_INVALID_TARGET_NUM (uint16_t)-1 142 143 #define PMCS_TGT_WAIT_QUEUE 0x01 144 #define PMCS_TGT_ACTIVE_QUEUE 0x02 145 #define PMCS_TGT_SPECIAL_QUEUE 0x04 146 #define PMCS_TGT_ALL_QUEUES 0xff 147 148 /* 149 * LUN representation. Just a LUN (number) and pointer to the target 150 * structure (pmcs_xscsi). 151 */ 152 153 struct pmcs_lun { 154 pmcs_xscsi_t *target; 155 uint64_t lun_num; /* lun64 */ 156 scsi_lun_t scsi_lun; /* Wire format */ 157 char unit_address[PMCS_MAX_UA_SIZE]; 158 }; 159 160 /* 161 * Interrupt coalescing values 162 */ 163 #define PMCS_MAX_IO_COMPS_PER_INTR 12 164 #define PMCS_MAX_IO_COMPS_HIWAT_SHIFT 6 165 #define PMCS_MAX_IO_COMPS_LOWAT_SHIFT 10 166 #define PMCS_QUANTUM_TIME_USECS (1000000 / 10) /* 1/10th sec. */ 167 #define PMCS_MAX_COAL_TIMER 0x200 /* Don't set > than this */ 168 #define PMCS_MAX_CQ_THREADS 4 169 #define PMCS_COAL_TIMER_GRAN 2 /* Go up/down by 2 usecs */ 170 #define PMCS_INTR_THRESHOLD(x) ((x) * 6 / 10) 171 172 /* 173 * This structure is used to maintain state with regard to I/O interrupt 174 * coalescing. 175 */ 176 177 typedef struct pmcs_io_intr_coal_s { 178 hrtime_t nsecs_between_intrs; 179 hrtime_t last_io_comp; 180 clock_t quantum; 181 uint32_t num_io_completions; 182 uint32_t num_intrs; 183 uint32_t max_io_completions; 184 uint32_t intr_latency; 185 uint32_t intr_threshold; 186 uint16_t intr_coal_timer; 187 boolean_t timer_on; 188 boolean_t stop_thread; 189 boolean_t int_cleared; 190 } pmcs_io_intr_coal_t; 191 192 typedef struct pmcs_cq_thr_info_s { 193 kthread_t *cq_thread; 194 kmutex_t cq_thr_lock; 195 kcondvar_t cq_cv; 196 pmcs_hw_t *cq_pwp; 197 } pmcs_cq_thr_info_t; 198 199 typedef struct pmcs_cq_info_s { 200 uint32_t cq_threads; 201 uint32_t cq_next_disp_thr; 202 boolean_t cq_stop; 203 pmcs_cq_thr_info_t *cq_thr_info; 204 } pmcs_cq_info_t; 205 206 typedef struct pmcs_iocomp_cb_s { 207 pmcwork_t *pwrk; 208 char iomb[PMCS_QENTRY_SIZE << 1]; 209 struct pmcs_iocomp_cb_s *next; 210 } pmcs_iocomp_cb_t; 211 212 typedef struct pmcs_iqp_trace_s { 213 char *head; 214 char *curpos; 215 uint32_t size_left; 216 } pmcs_iqp_trace_t; 217 218 /* 219 * Used by string-based softstate as hint to possible size. 220 */ 221 222 #define PMCS_TGT_SSTATE_SZ 64 223 #define PMCS_LUN_SSTATE_SZ 4 224 225 /* 226 * HBA iport node softstate 227 */ 228 #define PMCS_IPORT_INVALID_PORT_ID 0xffff 229 230 struct pmcs_iport { 231 kmutex_t lock; /* iport lock */ 232 list_node_t list_node; /* list node for pwp->iports list_t */ 233 kmutex_t refcnt_lock; /* refcnt lock */ 234 kcondvar_t refcnt_cv; /* refcnt cv */ 235 int refcnt; /* refcnt for this iport */ 236 dev_info_t *dip; /* iport dip */ 237 pmcs_hw_t *pwp; /* back pointer to HBA state */ 238 pmcs_phy_t *pptr; /* pointer to this port's primary phy */ 239 enum { /* unit address state in the phymap */ 240 UA_INACTIVE, 241 UA_PEND_ACTIVATE, 242 UA_ACTIVE, 243 UA_PEND_DEACTIVATE 244 } ua_state; 245 char *ua; /* unit address (phy mask) */ 246 int portid; /* portid */ 247 int report_skip; /* skip or report during discovery */ 248 list_t phys; /* list of phys on this port */ 249 int nphy; /* number of phys in this port */ 250 scsi_hba_tgtmap_t *iss_tgtmap; /* tgtmap */ 251 ddi_soft_state_bystr *tgt_sstate; /* tgt softstate */ 252 }; 253 254 struct pmcs_chunk { 255 pmcs_chunk_t *next; 256 ddi_acc_handle_t acc_handle; 257 ddi_dma_handle_t dma_handle; 258 uint8_t *addrp; 259 uint64_t dma_addr; 260 }; 261 262 /* 263 * HBA node (i.e. non-iport) softstate 264 */ 265 struct pmcs_hw { 266 /* 267 * Identity 268 */ 269 dev_info_t *dip; 270 271 /* 272 * 16 possible initiator PHY WWNs 273 */ 274 uint64_t sas_wwns[PMCS_MAX_PORTS]; 275 276 /* 277 * Card State 278 */ 279 enum pwpstate { 280 STATE_NIL, 281 STATE_PROBING, 282 STATE_RUNNING, 283 STATE_UNPROBING, 284 STATE_DEAD 285 } state; 286 287 uint32_t 288 fw_disable_update : 1, 289 fw_force_update : 1, 290 blocked : 1, 291 stuck : 1, 292 locks_initted : 1, 293 mpi_table_setup : 1, 294 hba_attached : 1, 295 iports_attached : 1, 296 suspended : 1, 297 separate_ports : 1, 298 fwlog : 4, 299 phymode : 3, 300 physpeed : 3, 301 resource_limited : 1, 302 configuring : 1, 303 ds_err_recovering : 1; 304 305 /* 306 * This HBA instance's iportmap and list of iport states. 307 * Note: iports_lock protects iports, iports_attached, and 308 * num_iports on the HBA softstate. 309 */ 310 krwlock_t iports_lock; 311 scsi_hba_iportmap_t *hss_iportmap; 312 list_t iports; 313 int num_iports; 314 315 sas_phymap_t *hss_phymap; 316 int phymap_active; 317 318 /* 319 * Locks 320 */ 321 kmutex_t lock; 322 kmutex_t dma_lock; 323 kmutex_t axil_lock; 324 kcondvar_t drain_cv; 325 326 /* 327 * FMA Capabilities 328 */ 329 int fm_capabilities; 330 331 /* 332 * Register Access Handles 333 */ 334 ddi_device_acc_attr_t dev_acc_attr; 335 ddi_device_acc_attr_t reg_acc_attr; 336 ddi_acc_handle_t pci_acc_handle; 337 ddi_acc_handle_t msg_acc_handle; 338 ddi_acc_handle_t top_acc_handle; 339 ddi_acc_handle_t mpi_acc_handle; 340 ddi_acc_handle_t gsm_acc_handle; 341 ddi_acc_handle_t iqp_acchdls[PMCS_MAX_IQ]; 342 ddi_acc_handle_t oqp_acchdls[PMCS_MAX_IQ]; 343 ddi_acc_handle_t cip_acchdls; 344 ddi_acc_handle_t fwlog_acchdl; 345 ddi_acc_handle_t regdump_acchdl; 346 347 /* 348 * DMA Handles 349 */ 350 ddi_dma_attr_t iqp_dma_attr; 351 ddi_dma_attr_t oqp_dma_attr; 352 ddi_dma_attr_t cip_dma_attr; 353 ddi_dma_attr_t fwlog_dma_attr; 354 ddi_dma_attr_t regdump_dma_attr; 355 ddi_dma_handle_t iqp_handles[PMCS_MAX_IQ]; 356 ddi_dma_handle_t oqp_handles[PMCS_MAX_OQ]; 357 ddi_dma_handle_t cip_handles; 358 ddi_dma_handle_t fwlog_hndl; 359 ddi_dma_handle_t regdump_hndl; 360 361 /* 362 * Register Pointers 363 */ 364 uint32_t *msg_regs; /* message unit registers */ 365 uint32_t *top_regs; /* top unit registers */ 366 uint32_t *mpi_regs; /* message passing unit registers */ 367 uint32_t *gsm_regs; /* GSM registers */ 368 369 /* 370 * Message Passing and other offsets. 371 * 372 * mpi_offset is the offset within the fourth register set (mpi_regs) 373 * that contains the base of the MPI structures. Since this is actually 374 * set by the card firmware, it can change from startup to startup. 375 * 376 * The other offsets (gst, iqc, oqc) are for similar tables in 377 * MPI space, typically only accessed during setup. 378 */ 379 uint32_t mpi_offset; 380 uint32_t mpi_gst_offset; 381 uint32_t mpi_iqc_offset; 382 uint32_t mpi_oqc_offset; 383 384 /* 385 * Inbound and outbound queue depth 386 */ 387 uint32_t ioq_depth; 388 389 /* 390 * Kernel addresses and offsets for Inbound Queue Producer Indices 391 * 392 * See comments in pmcs_iomb.h about Inbound Queues. Since it 393 * is relatively expensive to go across the PCIe bus to read or 394 * write inside the card, we maintain shadow copies in kernel 395 * memory and update the card as needed. 396 */ 397 uint32_t shadow_iqpi[PMCS_MAX_IQ]; 398 uint32_t iqpi_offset[PMCS_MAX_IQ]; 399 uint32_t *iqp[PMCS_MAX_IQ]; 400 kmutex_t iqp_lock[PMCS_NIQ]; 401 402 pmcs_iqp_trace_t *iqpt; 403 404 /* 405 * Kernel addresses and offsets for Outbound Queue Consumer Indices 406 */ 407 uint32_t *oqp[PMCS_MAX_OQ]; 408 uint32_t oqci_offset[PMCS_MAX_OQ]; 409 410 /* 411 * Driver's copy of the outbound queue indices 412 */ 413 414 uint32_t oqci[PMCS_NOQ]; 415 uint32_t oqpi[PMCS_NOQ]; 416 417 /* 418 * DMA addresses for both Inbound and Outbound queues. 419 */ 420 uint64_t oqaddr[PMCS_MAX_OQ]; 421 uint64_t iqaddr[PMCS_MAX_IQ]; 422 423 /* 424 * Producer/Queue Host Memory Pointers and scratch areas, 425 * as well as DMA scatter/gather chunk areas. 426 * 427 * See discussion in pmcs_def.h about how this is laid out. 428 */ 429 uint8_t *cip; 430 uint64_t ciaddr; 431 432 /* 433 * Scratch area pointer and DMA addrress for SATA and SMP operations. 434 */ 435 void *scratch; 436 uint64_t scratch_dma; 437 volatile uint8_t scratch_locked; /* Scratch area ownership */ 438 439 /* 440 * Firmware log pointer 441 */ 442 uint32_t *fwlogp; 443 uint64_t fwaddr; 444 445 /* 446 * Internal register dump region and flash chunk DMA info 447 */ 448 449 caddr_t regdumpp; 450 uint32_t *flash_chunkp; 451 uint64_t flash_chunk_addr; 452 453 /* 454 * Card information, some determined during MPI setup 455 */ 456 uint32_t fw; /* firmware version */ 457 uint8_t max_iq; /* maximum inbound queues this card */ 458 uint8_t max_oq; /* "" outbound "" */ 459 uint8_t nphy; /* number of phys this card */ 460 uint8_t chiprev; /* chip revision */ 461 uint16_t max_cmd; /* max number of commands supported */ 462 uint16_t max_dev; /* max number of devices supported */ 463 uint16_t last_wq_dev; /* last dev whose wq was serviced */ 464 465 466 /* 467 * Interrupt Setup stuff. 468 * 469 * int_type defines the kind of interrupt we're using with this card. 470 * oqvec defines the relationship between an Outbound Queue Number and 471 * a MSI-X vector. 472 */ 473 enum { 474 PMCS_INT_NONE, 475 PMCS_INT_TIMER, 476 PMCS_INT_MSI, 477 PMCS_INT_MSIX, 478 PMCS_INT_FIXED 479 } int_type; 480 uint8_t oqvec[PMCS_NOQ]; 481 482 /* 483 * Interrupt handle table and size 484 */ 485 ddi_intr_handle_t *ih_table; 486 size_t ih_table_size; 487 488 timeout_id_t wdhandle; 489 uint32_t intr_mask; 490 int intr_cnt; 491 int intr_cap; 492 uint32_t odb_auto_clear; 493 494 /* 495 * DMA S/G chunk list 496 */ 497 int nchunks; 498 pmcs_chunk_t *dma_chunklist; 499 500 /* 501 * Front of the DMA S/G chunk freelist 502 */ 503 pmcs_dmachunk_t *dma_freelist; 504 505 /* 506 * PHY and Discovery Related Stuff 507 * 508 * The PMC chip can have up to 16 local phys. We build a level-first 509 * traversal tree of phys starting with the physical phys on the 510 * chip itself (i.e., treating the chip as if it were an expander). 511 * 512 * Our discovery process goes through a level and discovers what 513 * each entity is (and it's phy number within that expander's 514 * address space). It then configures each non-empty item (SAS, 515 * SATA/STP, EXPANDER). For expanders, it then performs 516 * discover on that expander itself via REPORT GENERAL and 517 * DISCOVERY SMP commands, attaching the discovered entities 518 * to the next level. Then we step down a level and continue 519 * (and so on). 520 * 521 * The PMC chip maintains an I_T_NEXUS notion based upon our 522 * registering each new device found (getting back a device handle). 523 * 524 * Like with the number of physical PHYS being a maximum of 16, 525 * there are a maximum number of PORTS also being 16. Some 526 * events apply to PORTS entirely, so we track PORTS as well. 527 */ 528 pmcs_phy_t *root_phys; /* HBA PHYs (level 0) */ 529 pmcs_phy_t *ports[PMCS_MAX_PORTS]; 530 kmutex_t dead_phylist_lock; /* Protects dead_phys */ 531 pmcs_phy_t *dead_phys; /* PHYs waiting to be freed */ 532 533 kmem_cache_t *phy_cache; 534 535 /* 536 * Discovery-related items. 537 * config_lock: Protects config_changed and should never be held 538 * outside of getting or setting the value of config_changed. 539 * config_changed: Boolean indicating whether discovery needs to 540 * be restarted. 541 * configuring: 1 = discovery is running, 0 = discovery not running. 542 * NOTE: configuring is now in the bitfield above. 543 */ 544 kmutex_t config_lock; 545 volatile boolean_t config_changed; 546 547 /* 548 * Work Related Stuff 549 * 550 * Each command given to the PMC chip has an associated work structure. 551 * See the discussion in pmcs_def.h about work structures. 552 */ 553 pmcwork_t *work; /* pool of work structures */ 554 STAILQ_HEAD(wfh, pmcwork) wf; /* current freelist */ 555 STAILQ_HEAD(pfh, pmcwork) pf; /* current pending freelist */ 556 uint16_t wserno; /* rolling serial number */ 557 kmutex_t wfree_lock; /* freelist/actvlist/wserno lock */ 558 kmutex_t pfree_lock; /* freelist/actvlist/wserno lock */ 559 560 /* 561 * Solaris/SCSA items. 562 */ 563 scsi_hba_tran_t *tran; 564 smp_hba_tran_t *smp_tran; 565 struct scsi_reset_notify_entry *reset_notify_listf; 566 567 /* 568 * Thread Level stuff. 569 * 570 * A number of tasks are done off worker thread taskq. 571 */ 572 ddi_taskq_t *tq; /* For the worker thread */ 573 volatile ulong_t work_flags; 574 575 /* 576 * Solaris target representation. 577 * targets = array of pointers to xscsi structures 578 * allocated by ssoftstate. 579 */ 580 pmcs_xscsi_t **targets; 581 582 STAILQ_HEAD(dqh, pmcs_cmd) dq; /* dead commands */ 583 STAILQ_HEAD(cqh, pmcs_cmd) cq; /* completed commands */ 584 kmutex_t cq_lock; 585 kmem_cache_t *iocomp_cb_cache; 586 pmcs_iocomp_cb_t *iocomp_cb_head; 587 pmcs_iocomp_cb_t *iocomp_cb_tail; 588 589 uint16_t debug_mask; 590 uint16_t phyid_block_mask; 591 uint16_t phys_started; 592 uint32_t hipri_queue; 593 uint32_t mpibar; 594 uint32_t intr_pri; 595 596 pmcs_io_intr_coal_t io_intr_coal; 597 pmcs_cq_info_t cq_info; 598 kmutex_t ict_lock; 599 kcondvar_t ict_cv; 600 kthread_t *ict_thread; 601 602 #ifdef DEBUG 603 kmutex_t dbglock; 604 uint32_t ltags[256]; 605 uint32_t ftags[256]; 606 hrtime_t ltime[256]; 607 hrtime_t ftime[256]; 608 uint16_t ftag_lines[256]; 609 uint8_t lti; /* last tag index */ 610 uint8_t fti; /* first tag index */ 611 #endif 612 }; 613 614 extern void *pmcs_softc_state; 615 extern void *pmcs_iport_softstate; 616 617 /* 618 * Some miscellaneous, oft used strings 619 */ 620 extern const char pmcs_nowrk[]; 621 extern const char pmcs_nomsg[]; 622 extern const char pmcs_timeo[]; 623 624 #ifdef __cplusplus 625 } 626 #endif 627 #endif /* _PMCS_H */ 628