14c06356dh/*
24c06356dh * CDDL HEADER START
34c06356dh *
44c06356dh * The contents of this file are subject to the terms of the
54c06356dh * Common Development and Distribution License (the "License").
64c06356dh * You may not use this file except in compliance with the License.
74c06356dh *
84c06356dh * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
94c06356dh * or http://www.opensolaris.org/os/licensing.
104c06356dh * See the License for the specific language governing permissions
114c06356dh * and limitations under the License.
124c06356dh *
134c06356dh * When distributing Covered Code, include this CDDL HEADER in each
144c06356dh * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
154c06356dh * If applicable, add the following below this CDDL HEADER, with the
164c06356dh * fields enclosed by brackets "[]" replaced with your own identifying
174c06356dh * information: Portions Copyright [yyyy] [name of copyright owner]
184c06356dh *
194c06356dh * CDDL HEADER END
20658280bDavid Hollister */
21658280bDavid Hollister/*
22658280bDavid Hollister * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
234c06356dh */
244c06356dh/*
254c06356dh * This file is the principle header file for the PMCS driver
264c06356dh */
274c06356dh#ifndef _PMCS_H
284c06356dh#define	_PMCS_H
294c06356dh#ifdef	__cplusplus
304c06356dhextern "C" {
314c06356dh#endif
324c06356dh
334c06356dh
344c06356dh#include <sys/cpuvar.h>
354c06356dh#include <sys/ddi.h>
364c06356dh#include <sys/sunddi.h>
374c06356dh#include <sys/modctl.h>
384c06356dh#include <sys/pci.h>
394c06356dh#include <sys/pcie.h>
409719310David Hollister#include <sys/file.h>
414c06356dh#include <sys/isa_defs.h>
424c06356dh#include <sys/sunmdi.h>
434c06356dh#include <sys/mdi_impldefs.h>
444c06356dh#include <sys/scsi/scsi.h>
454c06356dh#include <sys/scsi/impl/scsi_reset_notify.h>
4696c4a17Chris Horne#include <sys/scsi/impl/scsi_sas.h>
4796c4a17Chris Horne#include <sys/scsi/impl/smp_transport.h>
484c06356dh#include <sys/scsi/generic/sas.h>
4996c4a17Chris Horne#include <sys/scsi/generic/smp_frames.h>
504c06356dh#include <sys/atomic.h>
514c06356dh#include <sys/byteorder.h>
524b45646David Hollister#include <sys/sysmacros.h>
534c06356dh#include <sys/bitmap.h>
544c06356dh#include <sys/queue.h>
554c06356dh#include <sys/sdt.h>
564c06356dh#include <sys/ddifm.h>
574c06356dh#include <sys/fm/protocol.h>
584c06356dh#include <sys/fm/util.h>
594c06356dh#include <sys/fm/io/ddi.h>
604c06356dh#include <sys/scsi/impl/spc3_types.h>
614c06356dh
624c06356dhtypedef struct pmcs_hw pmcs_hw_t;
634c06356dhtypedef struct pmcs_iport pmcs_iport_t;
644c06356dhtypedef struct pmcs_phy pmcs_phy_t;
654c06356dhtypedef struct lsas_cmd lsas_cmd_t;
664c06356dhtypedef struct lsas_result lsas_result_t;
674c06356dhtypedef struct lsata_cmd lsata_cmd_t;
684c06356dhtypedef struct lsata_result lsata_result_t;
694c06356dhtypedef struct pmcwork pmcwork_t;
704c06356dhtypedef struct pmcs_cmd pmcs_cmd_t;
714c06356dhtypedef	struct pmcs_xscsi pmcs_xscsi_t;
724c06356dhtypedef	struct pmcs_lun pmcs_lun_t;
734c06356dhtypedef struct pmcs_chunk pmcs_chunk_t;
744c06356dh
754c06356dh#include <sys/scsi/adapters/pmcs/pmcs_param.h>
764c06356dh#include <sys/scsi/adapters/pmcs/pmcs_reg.h>
774c06356dh#include <sys/scsi/adapters/pmcs/pmcs_mpi.h>
784c06356dh#include <sys/scsi/adapters/pmcs/pmcs_iomb.h>
794c06356dh#include <sys/scsi/adapters/pmcs/pmcs_sgl.h>
804c06356dh
814c06356dh#include <sys/scsi/adapters/pmcs/ata.h>
824c06356dh#include <sys/scsi/adapters/pmcs/pmcs_def.h>
834c06356dh#include <sys/scsi/adapters/pmcs/pmcs_proto.h>
844c06356dh#include <sys/scsi/adapters/pmcs/pmcs_scsa.h>
854c06356dh#include <sys/scsi/adapters/pmcs/pmcs_smhba.h>
864c06356dh
874c06356dh#define	PMCS_MAX_UA_SIZE	32
884c06356dh
894c06356dhstruct pmcs_xscsi {
904c06356dh	uint32_t
914c06356dh		ca		:	1,		/* SATA specific */
924c06356dh		ncq		:	1,		/* SATA specific */
934c06356dh		pio		:	1,		/* SATA specific */
944c06356dh		special_needed	:	1,		/* SATA specific */
954c06356dh		special_running	:	1,		/* SATA specific */
964c06356dh		reset_success	:	1,		/* last reset ok */
974c06356dh		reset_wait	:	1,		/* wait for reset */
984c06356dh		resetting	:	1,		/* now resetting */
994c06356dh		recover_wait	:	1,		/* wait for recovery */
1004c06356dh		recovering	:	1,		/* now recovering */
1014c06356dh		event_recovery	:	1,		/* event recovery */
1024c06356dh		draining	:	1,
1034c06356dh		new		:	1,
1044c06356dh		assigned	:	1,
1054c06356dh		dev_gone	:	1,
1064c06356dh		phy_addressable	:	1,		/* Direct attach SATA */
1074c06356dh		dev_state	:	4;
1084c06356dh	uint16_t			maxdepth;
1094c06356dh	uint16_t			qdepth;
110601c90fSrikanth, Ramana	uint16_t			actv_cnt;	/* Pkts ON CHIP */
111601c90fSrikanth, Ramana	uint16_t			actv_pkts;	/* Pkts in driver */
1124c06356dh	uint16_t			target_num;
1134c06356dh	/* statlock protects both target stats and the special queue (sq) */
1144c06356dh	kmutex_t			statlock;
1154c06356dh	int32_t				ref_count;
1164c06356dh	dev_info_t 			*dip;	/* Solaris device dip */
1174c06356dh	pmcs_phy_t			*phy;
1184c06356dh	STAILQ_HEAD(wqh, pmcs_cmd)	wq;
1194c06356dh	pmcs_cmd_t			*wq_recovery_tail;	/* See below */
1204c06356dh	kmutex_t			wqlock;
1214c06356dh	STAILQ_HEAD(aqh, pmcs_cmd)	aq;
1224c06356dh	kmutex_t			aqlock;
1234c06356dh	STAILQ_HEAD(sqh, pmcs_cmd)	sq;		/* SATA specific */
1244c06356dh	uint32_t			tagmap;		/* SATA specific */
1254c06356dh	pmcs_hw_t			*pwp;
1264c06356dh	ddi_soft_state_bystr		*lun_sstate;
1274c06356dh	uint64_t			capacity;	/* SATA specific */
1284c06356dh	char				unit_address[PMCS_MAX_UA_SIZE];
1294c06356dh	kcondvar_t			reset_cv;
1304c06356dh	kcondvar_t			abort_cv;
1314c06356dh	char				*ua;
1324c06356dh	pmcs_dtype_t			dtype;
13373a3eccDavid Hollister	list_t				lun_list;	/* list of LUNs */
134499cfd1David Hollister	struct smp_device		*smpd;		/* Ptr to smp_device */
1354c06356dh};
1364c06356dh
1374c06356dh/*
1384c06356dh * wq_recovery_tail in the pmcs_xscsi structure is a pointer to a command in
1394c06356dh * the wait queue (wq).  That pointer is the last command in the wait queue
1404c06356dh * that needs to be reissued after device state recovery is complete.  Commands
1414c06356dh * that need to be retried are reinserted into the wq after wq_recovery_tail
1424c06356dh * to maintain the order in which the commands were originally submitted.
1434c06356dh */
1444c06356dh
1454c06356dh#define	PMCS_INVALID_TARGET_NUM		(uint16_t)-1
1464c06356dh
1474c06356dh#define	PMCS_TGT_WAIT_QUEUE		0x01
1484c06356dh#define	PMCS_TGT_ACTIVE_QUEUE		0x02
1494c06356dh#define	PMCS_TGT_SPECIAL_QUEUE		0x04
1504c06356dh#define	PMCS_TGT_ALL_QUEUES		0xff
1514c06356dh
1524c06356dh/*
1534c06356dh * LUN representation.  Just a LUN (number) and pointer to the target
1544c06356dh * structure (pmcs_xscsi).
1554c06356dh */
1564c06356dh
1574c06356dhstruct pmcs_lun {
15873a3eccDavid Hollister	list_node_t		lun_list_next;
15973a3eccDavid Hollister	pmcs_xscsi_t		*target;
16073a3eccDavid Hollister	struct scsi_device	*sd;
16173a3eccDavid Hollister	uint64_t		lun_num;	/* lun64 */
16273a3eccDavid Hollister	scsi_lun_t		scsi_lun;	/* Wire format */
16373a3eccDavid Hollister	char			unit_address[PMCS_MAX_UA_SIZE];
1644c06356dh};
1654c06356dh
1664c06356dh/*
1674c06356dh * Interrupt coalescing values
1684c06356dh */
1694c06356dh#define	PMCS_MAX_IO_COMPS_PER_INTR	12
1704c06356dh#define	PMCS_MAX_IO_COMPS_HIWAT_SHIFT	6
1714c06356dh#define	PMCS_MAX_IO_COMPS_LOWAT_SHIFT	10
1724c06356dh#define	PMCS_QUANTUM_TIME_USECS		(1000000 / 10)	/* 1/10th sec. */
1734c06356dh#define	PMCS_MAX_COAL_TIMER		0x200	/* Don't set > than this */
1744c06356dh#define	PMCS_MAX_CQ_THREADS		4
1754c06356dh#define	PMCS_COAL_TIMER_GRAN		2	/* Go up/down by 2 usecs */
1764c06356dh#define	PMCS_INTR_THRESHOLD(x)		((x) * 6 / 10)
1774c06356dh
1784c06356dh/*
1794c06356dh * This structure is used to maintain state with regard to I/O interrupt
1804c06356dh * coalescing.
1814c06356dh */
1824c06356dh
1834c06356dhtypedef struct pmcs_io_intr_coal_s {
1844c06356dh	hrtime_t	nsecs_between_intrs;
1854c06356dh	hrtime_t	last_io_comp;
1864c06356dh	clock_t		quantum;
1874c06356dh	uint32_t	num_io_completions;
1884c06356dh	uint32_t	num_intrs;
1894c06356dh	uint32_t	max_io_completions;
1904c06356dh	uint32_t	intr_latency;
1914c06356dh	uint32_t	intr_threshold;
1924c06356dh	uint16_t	intr_coal_timer;
1934c06356dh	boolean_t	timer_on;
1944c06356dh	boolean_t	stop_thread;
1954c06356dh	boolean_t	int_cleared;
1964c06356dh} pmcs_io_intr_coal_t;
1974c06356dh
1984c06356dhtypedef struct pmcs_cq_thr_info_s {
1994c06356dh	kthread_t	*cq_thread;
2004c06356dh	kmutex_t	cq_thr_lock;
2014c06356dh	kcondvar_t	cq_cv;
2024c06356dh	pmcs_hw_t	*cq_pwp;
2034c06356dh} pmcs_cq_thr_info_t;
2044c06356dh
2054c06356dhtypedef struct pmcs_cq_info_s {
2064c06356dh	uint32_t		cq_threads;
2074c06356dh	uint32_t		cq_next_disp_thr;
2084c06356dh	boolean_t		cq_stop;
2094c06356dh	pmcs_cq_thr_info_t	*cq_thr_info;
2104c06356dh} pmcs_cq_info_t;
2114c06356dh
2124c06356dhtypedef struct pmcs_iocomp_cb_s {
2134c06356dh	pmcwork_t		*pwrk;
2144c06356dh	char			iomb[PMCS_QENTRY_SIZE << 1];
2154c06356dh	struct pmcs_iocomp_cb_s	*next;
2164c06356dh} pmcs_iocomp_cb_t;
2174c06356dh
2184c06356dhtypedef struct pmcs_iqp_trace_s {
2194c06356dh	char		*head;
2204c06356dh	char		*curpos;
2214c06356dh	uint32_t	size_left;
2224c06356dh} pmcs_iqp_trace_t;
2234c06356dh
2244c06356dh/*
2254c06356dh * Used by string-based softstate as hint to possible size.
2264c06356dh */
2274c06356dh
2284c06356dh#define	PMCS_TGT_SSTATE_SZ		64
2294c06356dh#define	PMCS_LUN_SSTATE_SZ		4
2304c06356dh
2314c06356dh/*
2324c06356dh * HBA iport node softstate
2334c06356dh */
234601c90fSrikanth, Ramana#define	PMCS_IPORT_INVALID_PORT_ID	0xf
2354c06356dh
2364c06356dhstruct pmcs_iport {
2374c06356dh	kmutex_t	lock;		/* iport lock */
2384c06356dh	list_node_t	list_node;	/* list node for pwp->iports list_t */
2394c06356dh	kmutex_t	refcnt_lock;	/* refcnt lock */
2404c06356dh	kcondvar_t	refcnt_cv;	/* refcnt cv */
2414c06356dh	int		refcnt;		/* refcnt for this iport */
2424c06356dh	dev_info_t	*dip;		/* iport dip */
2434c06356dh	pmcs_hw_t	*pwp;		/* back pointer to HBA state */
2444c06356dh	pmcs_phy_t	*pptr;		/* pointer to this port's primary phy */
2454c06356dh	enum {				/* unit address state in the phymap */
2464c06356dh		UA_INACTIVE,
2474c06356dh		UA_PEND_ACTIVATE,
2484c06356dh		UA_ACTIVE,
2494c06356dh		UA_PEND_DEACTIVATE
2504c06356dh	} ua_state;
2514c06356dh	char		*ua;		/* unit address (phy mask) */
2524c06356dh	int		portid;		/* portid */
2534c06356dh	int		report_skip;	/* skip or report during discovery */
2544c06356dh	list_t		phys;		/* list of phys on this port */
2554c06356dh	int		nphy;		/* number of phys in this port */
2564c06356dh	scsi_hba_tgtmap_t	*iss_tgtmap;	/* tgtmap */
2574c06356dh	ddi_soft_state_bystr	*tgt_sstate;	/* tgt softstate */
2586745c55Jesse Butler	/* SMP serialization */
2596745c55Jesse Butler	kmutex_t	smp_lock;
2606745c55Jesse Butler	kcondvar_t	smp_cv;
2616745c55Jesse Butler	boolean_t	smp_active;
2626745c55Jesse Butler	kthread_t	*smp_active_thread;
2634c06356dh};
2644c06356dh
2654c06356dhstruct pmcs_chunk {
2664c06356dh	pmcs_chunk_t		*next;
2674c06356dh	ddi_acc_handle_t	acc_handle;
2684c06356dh	ddi_dma_handle_t	dma_handle;
2694c06356dh	uint8_t			*addrp;
2704c06356dh	uint64_t		dma_addr;
2714c06356dh};
2724c06356dh
2734c06356dh/*
2744c06356dh * HBA node (i.e. non-iport) softstate
2754c06356dh */
2764c06356dhstruct pmcs_hw {
2774c06356dh	/*
2784c06356dh	 * Identity
2794c06356dh	 */
2804c06356dh	dev_info_t	*dip;
2814c06356dh
2824c06356dh	/*
2834c06356dh	 * 16 possible initiator PHY WWNs
2844c06356dh	 */
2854c06356dh	uint64_t	sas_wwns[PMCS_MAX_PORTS];
2864c06356dh
2874c06356dh	/*
2884c06356dh	 * Card State
2894c06356dh	 */
2904c06356dh	enum pwpstate {
2914c06356dh		STATE_NIL,
2924c06356dh		STATE_PROBING,
2934c06356dh		STATE_RUNNING,
2944c06356dh		STATE_UNPROBING,
2955c45adfJesse Butler		STATE_IN_RESET,
2964c06356dh		STATE_DEAD
2974c06356dh	} state;
2984c06356dh
2995c45adfJesse Butler	/*
3005c45adfJesse Butler	 * Last reason for a soft reset
3015c45adfJesse Butler	 */
3025c45adfJesse Butler	enum pwp_last_reset_reason {
3035c45adfJesse Butler		PMCS_LAST_RST_UNINIT,
3045c45adfJesse Butler		PMCS_LAST_RST_ATTACH,
3055c45adfJesse Butler		PMCS_LAST_RST_FW_UPGRADE,
3065c45adfJesse Butler		PMCS_LAST_RST_FATAL_ERROR,
3075c45adfJesse Butler		PMCS_LAST_RST_STALL,
3085c45adfJesse Butler		PMCS_LAST_RST_QUIESCE,
3095c45adfJesse Butler		PMCS_LAST_RST_DETACH
3105c45adfJesse Butler	} last_reset_reason;
3115c45adfJesse Butler
3124c06356dh	uint32_t
3134c06356dh		fw_disable_update	: 1,
3144c06356dh		fw_force_update		: 1,
3154c06356dh		blocked			: 1,
3164c06356dh		stuck			: 1,
3174c06356dh		locks_initted		: 1,
3184c06356dh		mpi_table_setup		: 1,
3194c06356dh		hba_attached		: 1,
3204c06356dh		iports_attached		: 1,
3214c06356dh		suspended		: 1,
3224c06356dh		separate_ports		: 1,
3234c06356dh		fwlog			: 4,
3244c06356dh		phymode			: 3,
3254c06356dh		physpeed		: 3,
3264c06356dh		resource_limited	: 1,
3274c06356dh		configuring		: 1,
3285c45adfJesse Butler		ds_err_recovering	: 1,
3299719310David Hollister		quiesced		: 1,
3302ac4abeDavid Hollister		fwlog_file		: 1,
3312ac4abeDavid Hollister		fw_active_img		: 1;	/* 1='A', 0='B' */
3324c06356dh
3334c06356dh	/*
3344c06356dh	 * This HBA instance's iportmap and list of iport states.
3354c06356dh	 * Note: iports_lock protects iports, iports_attached, and
3364c06356dh	 * num_iports on the HBA softstate.
3374c06356dh	 */
3384c06356dh	krwlock_t		iports_lock;
3394c06356dh	scsi_hba_iportmap_t	*hss_iportmap;
3404c06356dh	list_t			iports;
3414c06356dh	int			num_iports;
3424c06356dh
3434c06356dh	sas_phymap_t		*hss_phymap;
3444c06356dh	int			phymap_active;
3454c06356dh
3464c06356dh	/*
3474c06356dh	 * Locks
3484c06356dh	 */
3494c06356dh	kmutex_t	lock;
3504c06356dh	kmutex_t	dma_lock;
3514c06356dh	kmutex_t	axil_lock;
3524c06356dh	kcondvar_t	drain_cv;
3534c06356dh
3544c06356dh	/*
3554c06356dh	 * FMA Capabilities
3564c06356dh	 */
3574c06356dh	int		fm_capabilities;
3584c06356dh
3594c06356dh	/*
3604c06356dh	 * Register Access Handles
3614c06356dh	 */
3624c06356dh	ddi_device_acc_attr_t 	dev_acc_attr;
3634c06356dh	ddi_device_acc_attr_t	reg_acc_attr;
3644c06356dh	ddi_acc_handle_t 	pci_acc_handle;
3654c06356dh	ddi_acc_handle_t 	msg_acc_handle;
3664c06356dh	ddi_acc_handle_t 	top_acc_handle;
3674c06356dh	ddi_acc_handle_t	mpi_acc_handle;
3684c06356dh	ddi_acc_handle_t	gsm_acc_handle;
3694c06356dh	ddi_acc_handle_t	iqp_acchdls[PMCS_MAX_IQ];
3704c06356dh	ddi_acc_handle_t	oqp_acchdls[PMCS_MAX_IQ];
3714c06356dh	ddi_acc_handle_t	cip_acchdls;
3724c06356dh	ddi_acc_handle_t	fwlog_acchdl;
3734c06356dh	ddi_acc_handle_t	regdump_acchdl;
3744c06356dh
3754c06356dh	/*
3764c06356dh	 * DMA Handles
3774c06356dh	 */
3784c06356dh	ddi_dma_attr_t		iqp_dma_attr;
3794c06356dh	ddi_dma_attr_t		oqp_dma_attr;
3804c06356dh	ddi_dma_attr_t		cip_dma_attr;
3814c06356dh	ddi_dma_attr_t		fwlog_dma_attr;
3824c06356dh	ddi_dma_attr_t		regdump_dma_attr;
3834c06356dh	ddi_dma_handle_t 	iqp_handles[PMCS_MAX_IQ];
3844c06356dh	ddi_dma_handle_t 	oqp_handles[PMCS_MAX_OQ];
3854c06356dh	ddi_dma_handle_t	cip_handles;
3864c06356dh	ddi_dma_handle_t	fwlog_hndl;
3874c06356dh	ddi_dma_handle_t	regdump_hndl;
3884c06356dh
3894c06356dh	/*
3904c06356dh	 * Register Pointers
3914c06356dh	 */
3924c06356dh	uint32_t	*msg_regs;	/* message unit registers */
3934c06356dh	uint32_t	*top_regs;	/* top unit registers */
3944c06356dh	uint32_t	*mpi_regs;	/* message passing unit registers */
3954c06356dh	uint32_t	*gsm_regs;	/* GSM registers */
3964c06356dh
3974c06356dh	/*
3984c06356dh	 * Message Passing and other offsets.
3994c06356dh	 *
4004c06356dh	 * mpi_offset is the offset within the fourth register set (mpi_regs)
4014c06356dh	 * that contains the base of the MPI structures. Since this is actually
4024c06356dh	 * set by the card firmware, it can change from startup to startup.
4034c06356dh	 *
4044c06356dh	 * The other offsets (gst, iqc, oqc) are for similar tables in
4054c06356dh	 * MPI space, typically only accessed during setup.
4064c06356dh	 */
4074c06356dh	uint32_t	mpi_offset;
4084c06356dh	uint32_t	mpi_gst_offset;
4094c06356dh	uint32_t	mpi_iqc_offset;
4104c06356dh	uint32_t	mpi_oqc_offset;
4114c06356dh
4124c06356dh	/*
4134c06356dh	 * Inbound and outbound queue depth
4144c06356dh	 */
4154c06356dh	uint32_t	ioq_depth;
4164c06356dh
4174c06356dh	/*
4184c06356dh	 * Kernel addresses and offsets for Inbound Queue Producer Indices
4194c06356dh	 *
4204c06356dh	 * See comments in pmcs_iomb.h about Inbound Queues. Since it
4214c06356dh	 * is relatively expensive to go across the PCIe bus to read or
4224c06356dh	 * write inside the card, we maintain shadow copies in kernel
4234c06356dh	 * memory and update the card as needed.
4244c06356dh	 */
4254c06356dh	uint32_t	shadow_iqpi[PMCS_MAX_IQ];
4264c06356dh	uint32_t	iqpi_offset[PMCS_MAX_IQ];
427d78a6b7Jesse Butler	uint32_t	last_iqci[PMCS_MAX_IQ];
428d78a6b7Jesse Butler	uint32_t	last_htag[PMCS_MAX_IQ];
4294c06356dh	uint32_t	*iqp[PMCS_MAX_IQ];
4304c06356dh	kmutex_t	iqp_lock[PMCS_NIQ];
4314c06356dh
4324c06356dh	pmcs_iqp_trace_t	*iqpt;
4334c06356dh
4344c06356dh	/*
4354c06356dh	 * Kernel addresses and offsets for Outbound Queue Consumer Indices
4364c06356dh	 */
4374c06356dh	uint32_t	*oqp[PMCS_MAX_OQ];
4384c06356dh	uint32_t	oqci_offset[PMCS_MAX_OQ];
4394c06356dh
4404c06356dh	/*
4414c06356dh	 * Driver's copy of the outbound queue indices
4424c06356dh	 */
4434c06356dh
4444c06356dh	uint32_t	oqci[PMCS_NOQ];
4454c06356dh	uint32_t	oqpi[PMCS_NOQ];
4464c06356dh
4474c06356dh	/*
4484c06356dh	 * DMA addresses for both Inbound and Outbound queues.
4494c06356dh	 */
4504c06356dh	uint64_t	oqaddr[PMCS_MAX_OQ];
4514c06356dh	uint64_t	iqaddr[PMCS_MAX_IQ];
4524c06356dh
4534c06356dh	/*
4544c06356dh	 * Producer/Queue Host Memory Pointers and scratch areas,
4554c06356dh	 * as well as DMA scatter/gather chunk areas.
4564c06356dh	 *
4574c06356dh	 * See discussion in pmcs_def.h about how this is laid out.
4584c06356dh	 */
4594c06356dh	uint8_t		*cip;
4604c06356dh	uint64_t	ciaddr;
4614c06356dh
4624c06356dh	/*
4634c06356dh	 * Scratch area pointer and DMA addrress for SATA and SMP operations.
4644c06356dh	 */
4654c06356dh	void			*scratch;
4664c06356dh	uint64_t		scratch_dma;
4674c06356dh	volatile uint8_t	scratch_locked;	/* Scratch area ownership */
4684c06356dh
4694c06356dh	/*
4709719310David Hollister	 * Firmware info
4719719310David Hollister	 *
4729719310David Hollister	 * fwlogp: Pointer to block of memory mapped for the event logs
4739719310David Hollister	 * fwlogp_aap1: Pointer to the beginning of the AAP1 event log
4749719310David Hollister	 * fwlogp_iop: Pointer to the beginning of the IOP event log
4759719310David Hollister	 * fwaddr: The physical address of fwlogp
4769719310David Hollister	 *
4779719310David Hollister	 * fwlogfile_aap1/iop: Path to the saved AAP1/IOP event logs
4789719310David Hollister	 * fwlog_max_entries_aap1/iop: Max # of entries in each log
4799719310David Hollister	 * fwlog_oldest_idx_aap1/iop: Index of oldest entry in each log
4809719310David Hollister	 * fwlog_latest_idx_aap1/iop: Index of newest entry in each log
4819719310David Hollister	 * fwlog_threshold_aap1/iop: % full at which we save the event log
4829719310David Hollister	 * fwlog_findex_aap1/iop: Suffix to each event log's next filename
4839719310David Hollister	 *
4849719310David Hollister	 * Firmware event logs are written out to the filenames specified in
4859719310David Hollister	 * fwlogp_aap1/iop when the number of entries in the in-memory copy
4869719310David Hollister	 * reaches or exceeds the threshold value.  The filenames are suffixed
4879719310David Hollister	 * with .X where X is an integer ranging from 0 to 4.  This allows us
4889719310David Hollister	 * to save up to 5MB of event log data for each log.
4894c06356dh	 */
4904c06356dh	uint32_t	*fwlogp;
4919719310David Hollister	pmcs_fw_event_hdr_t *fwlogp_aap1;
4929719310David Hollister	pmcs_fw_event_hdr_t *fwlogp_iop;
4934c06356dh	uint64_t	fwaddr;
4949719310David Hollister	char		fwlogfile_aap1[MAXPATHLEN + 1];
4959719310David Hollister	uint32_t	fwlog_max_entries_aap1;
4969719310David Hollister	uint32_t	fwlog_oldest_idx_aap1;
4979719310David Hollister	uint32_t	fwlog_latest_idx_aap1;
4989719310David Hollister	uint32_t	fwlog_threshold_aap1;
4999719310David Hollister	uint32_t	fwlog_findex_aap1;
5009719310David Hollister	char		fwlogfile_iop[MAXPATHLEN + 1];
5019719310David Hollister	uint32_t	fwlog_max_entries_iop;
5029719310David Hollister	uint32_t	fwlog_oldest_idx_iop;
5039719310David Hollister	uint32_t	fwlog_latest_idx_iop;
5049719310David Hollister	uint32_t	fwlog_threshold_iop;
5059719310David Hollister	uint32_t	fwlog_findex_iop;
5064c06356dh
5074c06356dh	/*
5084c06356dh	 * Internal register dump region and flash chunk DMA info
5094c06356dh	 */
5104c06356dh
5114c06356dh	caddr_t		regdumpp;
5124c06356dh	uint32_t	*flash_chunkp;
5134c06356dh	uint64_t	flash_chunk_addr;
5144c06356dh
5154c06356dh	/*
5165c45adfJesse Butler	 * Copies of the last read MSGU and IOP heartbeats.
5175c45adfJesse Butler	 */
5185c45adfJesse Butler	uint32_t	last_msgu_tick;
5195c45adfJesse Butler	uint32_t	last_iop_tick;
5205c45adfJesse Butler
5215c45adfJesse Butler	/*
5224c06356dh	 * Card information, some determined during MPI setup
5234c06356dh	 */
5244c06356dh	uint32_t	fw;		/* firmware version */
5252ac4abeDavid Hollister	uint32_t	ila_ver;	/* ILA version */
5264c06356dh	uint8_t		max_iq;		/* maximum inbound queues this card */
5274c06356dh	uint8_t 	max_oq;		/* "" outbound "" */
5284c06356dh	uint8_t		nphy;		/* number of phys this card */
5294c06356dh	uint8_t		chiprev;	/* chip revision */
5304c06356dh	uint16_t	max_cmd;	/* max number of commands supported */
5314c06356dh	uint16_t	max_dev;	/* max number of devices supported */
5324c06356dh	uint16_t	last_wq_dev;	/* last dev whose wq was serviced */
5334c06356dh
5345c45adfJesse Butler	/*
5355c45adfJesse Butler	 * Counter for the number of times watchdog fires.  We can use this
5365c45adfJesse Butler	 * to throttle events which fire off of the watchdog, such as the
5375c45adfJesse Butler	 * forward progress detection routine.
5385c45adfJesse Butler	 */
5395c45adfJesse Butler	uint8_t		watchdog_count;
5404c06356dh
5414c06356dh	/*
5424c06356dh	 * Interrupt Setup stuff.
5434c06356dh	 *
5444c06356dh	 * int_type defines the kind of interrupt we're using with this card.
5454c06356dh	 * oqvec defines the relationship between an Outbound Queue Number and
5464c06356dh	 * a MSI-X vector.
5474c06356dh	 */
5484c06356dh	enum {
5494c06356dh		PMCS_INT_NONE,
5504c06356dh		PMCS_INT_TIMER,
5514c06356dh		PMCS_INT_MSI,
5524c06356dh		PMCS_INT_MSIX,
5534c06356dh		PMCS_INT_FIXED
5544c06356dh	} int_type;
5554c06356dh	uint8_t			oqvec[PMCS_NOQ];
5564c06356dh
5574c06356dh	/*
5584c06356dh	 * Interrupt handle table and size
5594c06356dh	 */
5604c06356dh	ddi_intr_handle_t	*ih_table;
5614c06356dh	size_t			ih_table_size;
5624c06356dh
5634c06356dh	timeout_id_t		wdhandle;
5644c06356dh	uint32_t		intr_mask;
5654c06356dh	int			intr_cnt;
5664c06356dh	int			intr_cap;
5674c06356dh	uint32_t		odb_auto_clear;
5684c06356dh
5694c06356dh	/*
5704c06356dh	 * DMA S/G chunk list
5714c06356dh	 */
5724c06356dh	int		nchunks;
5734c06356dh	pmcs_chunk_t	*dma_chunklist;
5744c06356dh
5754c06356dh	/*
5764c06356dh	 * Front of the DMA S/G chunk freelist
5774c06356dh	 */
5784c06356dh	pmcs_dmachunk_t	*dma_freelist;
5794c06356dh
5804c06356dh	/*
5814c06356dh	 * PHY and Discovery Related Stuff
5824c06356dh	 *
5834c06356dh	 * The PMC chip can have up to 16 local phys. We build a level-first
5844c06356dh	 * traversal tree of phys starting with the physical phys on the
5854c06356dh	 * chip itself (i.e., treating the chip as if it were an expander).
5864c06356dh	 *
5874c06356dh	 * Our discovery process goes through a level and discovers what
5884c06356dh	 * each entity is (and it's phy number within that expander's
5894c06356dh	 * address space). It then configures each non-empty item (SAS,
5904c06356dh	 * SATA/STP, EXPANDER). For expanders, it then performs
5914c06356dh	 * discover on that expander itself via REPORT GENERAL and
5924c06356dh	 * DISCOVERY SMP commands, attaching the discovered entities
5934c06356dh	 * to the next level. Then we step down a level and continue
5944c06356dh	 * (and so on).
5954c06356dh	 *
5964c06356dh	 * The PMC chip maintains an I_T_NEXUS notion based upon our
5974c06356dh	 * registering each new device found (getting back a device handle).
5984c06356dh	 *
5994c06356dh	 * Like with the number of physical PHYS being a maximum of 16,
6004c06356dh	 * there are a maximum number of PORTS also being 16. Some
6014c06356dh	 * events apply to PORTS entirely, so we track PORTS as well.
6024c06356dh	 */
6034c06356dh	pmcs_phy_t		*root_phys;	/* HBA PHYs (level 0) */
6044c06356dh	pmcs_phy_t		*ports[PMCS_MAX_PORTS];
6054c06356dh	kmutex_t		dead_phylist_lock;	/* Protects dead_phys */
6064c06356dh	pmcs_phy_t		*dead_phys;	/* PHYs waiting to be freed */
6074c06356dh
6084c06356dh	kmem_cache_t		*phy_cache;
6094c06356dh
6104c06356dh	/*
6114c06356dh	 * Discovery-related items.
6124c06356dh	 * config_lock: Protects config_changed and should never be held
61332b54dbJesse Butler	 * outside of getting or setting the value of config_changed or
61432b54dbJesse Butler	 * configuring.
6154c06356dh	 * config_changed: Boolean indicating whether discovery needs to
6164c06356dh	 * be restarted.
6174c06356dh	 * configuring: 1 = discovery is running, 0 = discovery not running.
6184c06356dh	 * NOTE: configuring is now in the bitfield above.
6199aed162David Hollister	 * config_restart_time is set by the tgtmap_[de]activate callbacks each
6209aed162David Hollister	 * time we decide we want SCSA to retry enumeration on some device.
6219aed162David Hollister	 * The watchdog timer will not fire discovery unless it has reached
6229aed162David Hollister	 * config_restart_time and config_restart is TRUE.  This ensures that
6239aed162David Hollister	 * we don't ask SCSA to retry enumerating devices while it is still
6249aed162David Hollister	 * running.
62532b54dbJesse Butler	 * config_cv can be used by any thread waiting on the configuring
62632b54dbJesse Butler	 * bit to clear.
6274c06356dh	 */
6284c06356dh	kmutex_t		config_lock;
6294c06356dh	volatile boolean_t	config_changed;
6309aed162David Hollister	boolean_t		config_restart;
6319aed162David Hollister	clock_t			config_restart_time;
63232b54dbJesse Butler	kcondvar_t		config_cv;
6334c06356dh
6344c06356dh	/*
6354c06356dh	 * Work Related Stuff
6364c06356dh	 *
6374c06356dh	 * Each command given to the PMC chip has an associated work structure.
6384c06356dh	 * See the discussion in pmcs_def.h about work structures.
6394c06356dh	 */
6404c06356dh	pmcwork_t	*work;		/* pool of work structures */
6414c06356dh	STAILQ_HEAD(wfh, pmcwork) wf;	/* current freelist */
6424c06356dh	STAILQ_HEAD(pfh, pmcwork) pf;	/* current pending freelist */
6434c06356dh	uint16_t	wserno;		/* rolling serial number */
6444c06356dh	kmutex_t	wfree_lock;	/* freelist/actvlist/wserno lock */
6454c06356dh	kmutex_t	pfree_lock;	/* freelist/actvlist/wserno lock */
6464c06356dh
6474c06356dh	/*
6484c06356dh	 * Solaris/SCSA items.
6494c06356dh	 */
6504c06356dh	scsi_hba_tran_t		*tran;
65196c4a17Chris Horne	smp_hba_tran_t		*smp_tran;
6524c06356dh	struct scsi_reset_notify_entry	*reset_notify_listf;
6534c06356dh
6544c06356dh	/*
6554c06356dh	 * Thread Level stuff.
6564c06356dh	 *
6574c06356dh	 * A number of tasks are done off worker thread taskq.
6584c06356dh	 */
6594c06356dh	ddi_taskq_t 		*tq;		/* For the worker thread */
6604c06356dh	volatile ulong_t	work_flags;
6614c06356dh
6624c06356dh	/*
6634c06356dh	 * Solaris target representation.
6644c06356dh	 * targets = array of pointers to xscsi structures
6654c06356dh	 * allocated by ssoftstate.
6664c06356dh	 */
6674c06356dh	pmcs_xscsi_t			**targets;
6684c06356dh
6694c06356dh	STAILQ_HEAD(dqh, pmcs_cmd)	dq;	/* dead commands */
6704c06356dh	STAILQ_HEAD(cqh, pmcs_cmd)	cq;	/* completed commands */
6714c06356dh	kmutex_t			cq_lock;
6724c06356dh	kmem_cache_t			*iocomp_cb_cache;
6734c06356dh	pmcs_iocomp_cb_t		*iocomp_cb_head;
6744c06356dh	pmcs_iocomp_cb_t		*iocomp_cb_tail;
6754c06356dh
6764c06356dh	uint16_t			debug_mask;
6774c06356dh	uint16_t			phyid_block_mask;
6784c06356dh	uint16_t			phys_started;
679658280bDavid Hollister	uint16_t			open_retry_interval;
6804c06356dh	uint32_t			hipri_queue;
6814c06356dh	uint32_t			mpibar;
6824c06356dh	uint32_t			intr_pri;
6834c06356dh
6844c06356dh	pmcs_io_intr_coal_t		io_intr_coal;
6854c06356dh	pmcs_cq_info_t			cq_info;
6864c06356dh	kmutex_t			ict_lock;
6874c06356dh	kcondvar_t			ict_cv;
6884c06356dh	kthread_t			*ict_thread;
6894c06356dh
690658280bDavid Hollister	/*
691658280bDavid Hollister	 * Receptacle information - FMA
692658280bDavid Hollister	 */
693658280bDavid Hollister	char				*recept_labels[PMCS_NUM_RECEPTACLES];
6941f81b46David Hollister	char				*recept_pm[PMCS_NUM_RECEPTACLES];
6951f81b46David Hollister
6961f81b46David Hollister	/*
6971f81b46David Hollister	 * fw_timestamp: Firmware timestamp taken after PHYs are started
6981f81b46David Hollister	 * sys_timestamp: System timestamp taken at roughly the same time
6991f81b46David Hollister	 * hrtimestamp is the hrtime at roughly the same time
7001f81b46David Hollister	 * All of these are protected by the global pmcs_trace_lock.
7011f81b46David Hollister	 */
7021f81b46David Hollister	uint64_t	fw_timestamp;
7031f81b46David Hollister	timespec_t	sys_timestamp;
7041f81b46David Hollister	hrtime_t	hrtimestamp;
705658280bDavid Hollister
7064c06356dh#ifdef	DEBUG
7074c06356dh	kmutex_t	dbglock;
7084c06356dh	uint32_t	ltags[256];
7094c06356dh	uint32_t	ftags[256];
7104c06356dh	hrtime_t	ltime[256];
7114c06356dh	hrtime_t	ftime[256];
7124c06356dh	uint16_t	ftag_lines[256];
7134c06356dh	uint8_t		lti;			/* last tag index */
7144c06356dh	uint8_t		fti;			/* first tag index */
7154c06356dh#endif
7164c06356dh};
7174c06356dh
7184c06356dhextern void 		*pmcs_softc_state;
7194c06356dhextern void 		*pmcs_iport_softstate;
7204c06356dh
7214c06356dh/*
7224c06356dh * Some miscellaneous, oft used strings
7234c06356dh */
7244c06356dhextern const char pmcs_nowrk[];
7254c06356dhextern const char pmcs_nomsg[];
7264c06356dhextern const char pmcs_timeo[];
7274c06356dh
72888e8a7fDavid Hollister/*
72988e8a7fDavid Hollister * Other externs
73088e8a7fDavid Hollister */
73188e8a7fDavid Hollisterextern int modrootloaded;
73288e8a7fDavid Hollister
7334c06356dh#ifdef	__cplusplus
7344c06356dh}
7354c06356dh#endif
7364c06356dh#endif	/* _PMCS_H */
737