1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2015 Nexenta Systems, Inc. All rights reserved. 25 * Copyright 2019 Joyent, Inc. 26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved. 27 */ 28 29 /* 30 * Copyright (c) 2000 to 2010, LSI Corporation. 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms of all code within 34 * this file that is exclusively owned by LSI, with or without 35 * modification, is permitted provided that, in addition to the CDDL 1.0 36 * License requirements, the following conditions are met: 37 * 38 * Neither the name of the author nor the names of its contributors may be 39 * used to endorse or promote products derived from this software without 40 * specific prior written permission. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 45 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 46 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 48 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 49 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 50 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 52 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 53 * DAMAGE. 54 */ 55 56 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 57 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 58 59 #include <sys/byteorder.h> 60 #include <sys/queue.h> 61 #include <sys/isa_defs.h> 62 #include <sys/sunmdi.h> 63 #include <sys/mdi_impldefs.h> 64 #include <sys/ddi_ufm.h> 65 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h> 66 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 67 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 68 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 69 70 #ifdef __cplusplus 71 extern "C" { 72 #endif 73 74 /* 75 * Compile options 76 */ 77 #ifdef DEBUG 78 #define MPTSAS_DEBUG /* turn on debugging code */ 79 #endif /* DEBUG */ 80 81 #define MPTSAS_INITIAL_SOFT_SPACE 4 82 83 /* 84 * Note below macro definition and data type definition 85 * are used for phy mask handling, it should be changed 86 * simultaneously. 87 */ 88 #define MPTSAS_MAX_PHYS 24 89 typedef uint32_t mptsas_phymask_t; 90 91 #define MPTSAS_INVALID_DEVHDL 0xffff 92 #define MPTSAS_SATA_GUID "sata-guid" 93 94 /* 95 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP 96 * targets. There's no need to go overboard here, as the ordinary paths for 97 * I/O do not normally require hashed target lookups. These should be good 98 * enough and then some for any fabric within the hardware's capabilities. 99 */ 100 #define MPTSAS_SMP_BUCKET_COUNT 23 101 #define MPTSAS_TARGET_BUCKET_COUNT 97 102 #define MPTSAS_TMP_TARGET_BUCKET_COUNT 13 103 104 /* 105 * MPT HW defines 106 */ 107 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 108 #define MPTSAS_MAX_DISKS_IN_VOL 10 109 #define MPTSAS_MAX_HOTSPARES 2 110 #define MPTSAS_MAX_RAIDVOLS 2 111 #define MPTSAS_MAX_RAIDCONFIGS 5 112 113 /* 114 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 115 * plus two means the prefix 'w' and end of the string '\0'. 116 */ 117 #define MPTSAS_WWN_STRLEN (16 + 2) 118 #define MPTSAS_MAX_GUID_LEN 64 119 120 /* 121 * DMA routine flags 122 */ 123 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 124 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 125 #define MPTSAS_DMA_HANDLE_BOUND 0x8 126 127 /* 128 * If the HBA supports DMA or bus-mastering, you may have your own 129 * scatter-gather list for physically non-contiguous memory in one 130 * I/O operation; if so, there's probably a size for that list. 131 * It must be placed in the ddi_dma_lim_t structure, so that the system 132 * DMA-support routines can use it to break up the I/O request, so we 133 * define it here. 134 */ 135 #if defined(__sparc) 136 #define MPTSAS_MAX_DMA_SEGS 1 137 #define MPTSAS_MAX_CMD_SEGS 1 138 #else 139 #define MPTSAS_MAX_DMA_SEGS 256 140 #define MPTSAS_MAX_CMD_SEGS 257 141 #endif 142 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 143 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 144 145 #define MPTSAS_SGE_SIZE(mpt) \ 146 ((mpt)->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \ 147 sizeof (MPI2_SGE_SIMPLE64)) 148 149 /* 150 * Calculating how many 64-bit DMA simple elements can be stored in the first 151 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 152 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 153 * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words 154 * (16 bytes). 155 */ 156 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 157 ((mpt->m_req_frame_size - \ 158 sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \ 159 MPTSAS_SGE_SIZE(mpt)) 160 161 /* 162 * Scatter-gather list structure defined by HBA hardware 163 */ 164 typedef struct NcrTableIndirect { /* Table Indirect entries */ 165 uint32_t count; /* 24 bit count */ 166 union { 167 uint32_t address32; /* 32 bit address */ 168 struct { 169 uint32_t Low; 170 uint32_t High; 171 } address64; /* 64 bit address */ 172 } addr; 173 } mptti_t; 174 175 /* 176 * preferred pkt_private length in 64-bit quantities 177 */ 178 #ifdef _LP64 179 #define PKT_PRIV_SIZE 2 180 #define PKT_PRIV_LEN 16 /* in bytes */ 181 #else /* _ILP32 */ 182 #define PKT_PRIV_SIZE 1 183 #define PKT_PRIV_LEN 8 /* in bytes */ 184 #endif 185 186 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 187 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 188 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 189 190 /* 191 * get offset of item in structure 192 */ 193 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 194 195 /* 196 * WWID provided by LSI firmware is generated by firmware but the WWID is not 197 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 198 * address. According LSI's confirmation, the top nibble of RAID WWID is 199 * meanless, so the consensus between Solaris and OBP is to replace top nibble 200 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 201 * format unit address. 202 */ 203 #define MPTSAS_RAID_WWID(wwid) \ 204 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 205 206 typedef struct mptsas_target_addr { 207 uint64_t mta_wwn; 208 mptsas_phymask_t mta_phymask; 209 } mptsas_target_addr_t; 210 211 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd); 212 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t; 213 214 typedef struct mptsas_target { 215 mptsas_target_addr_t m_addr; 216 refhash_link_t m_link; 217 uint8_t m_dr_flag; 218 uint16_t m_devhdl; 219 uint32_t m_deviceinfo; 220 uint8_t m_phynum; 221 uint32_t m_dups; 222 mptsas_active_cmdq_t m_active_cmdq; 223 int32_t m_t_throttle; 224 int32_t m_t_ncmds; 225 int32_t m_reset_delay; 226 int32_t m_t_nwait; 227 228 uint16_t m_qfull_retry_interval; 229 uint8_t m_qfull_retries; 230 uint16_t m_io_flags; 231 uint16_t m_enclosure; 232 uint16_t m_slot_num; 233 uint32_t m_tgt_unconfigured; 234 } mptsas_target_t; 235 236 /* 237 * If you change this structure, be sure that mptsas_smp_target_copy() 238 * does the right thing. 239 */ 240 typedef struct mptsas_smp { 241 mptsas_target_addr_t m_addr; 242 refhash_link_t m_link; 243 uint16_t m_devhdl; 244 uint32_t m_deviceinfo; 245 uint16_t m_pdevhdl; 246 uint32_t m_pdevinfo; 247 } mptsas_smp_t; 248 249 /* 250 * This represents a single enclosure. Targets point to an enclosure through 251 * their m_enclosure member. 252 */ 253 typedef struct mptsas_enclosure { 254 list_node_t me_link; 255 uint16_t me_enchdl; 256 uint16_t me_flags; 257 uint16_t me_nslots; 258 uint16_t me_fslot; 259 uint8_t *me_slotleds; 260 } mptsas_enclosure_t; 261 262 typedef struct mptsas_cache_frames { 263 ddi_dma_handle_t m_dma_hdl; 264 ddi_acc_handle_t m_acc_hdl; 265 caddr_t m_frames_addr; 266 uint64_t m_phys_addr; 267 } mptsas_cache_frames_t; 268 269 typedef struct mptsas_cmd { 270 uint_t cmd_flags; /* flags from scsi_init_pkt */ 271 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 272 ddi_dma_cookie_t cmd_cookie; 273 uint_t cmd_cookiec; 274 uint_t cmd_winindex; 275 uint_t cmd_nwin; 276 uint_t cmd_cur_cookie; 277 off_t cmd_dma_offset; 278 size_t cmd_dma_len; 279 uint32_t cmd_totaldmacount; 280 caddr_t cmd_arq_buf; 281 282 int cmd_pkt_flags; 283 284 /* pending expiration time for command in active slot */ 285 hrtime_t cmd_active_expiration; 286 TAILQ_ENTRY(mptsas_cmd) cmd_active_link; 287 288 struct scsi_pkt *cmd_pkt; 289 struct scsi_arq_status cmd_scb; 290 uchar_t cmd_cdblen; /* length of cdb */ 291 uchar_t cmd_rqslen; /* len of requested rqsense */ 292 uchar_t cmd_privlen; 293 uint16_t cmd_extrqslen; /* len of extended rqsense */ 294 uint16_t cmd_extrqschunks; /* len in map chunks */ 295 uint16_t cmd_extrqsidx; /* Index into map */ 296 uint_t cmd_scblen; 297 uint32_t cmd_dmacount; 298 uint64_t cmd_dma_addr; 299 uchar_t cmd_age; 300 ushort_t cmd_qfull_retries; 301 uchar_t cmd_queued; /* true if queued */ 302 struct mptsas_cmd *cmd_linkp; 303 mptti_t *cmd_sg; /* Scatter/Gather structure */ 304 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 305 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 306 uint32_t cmd_slot; 307 uint32_t ioc_cmd_slot; 308 309 mptsas_cache_frames_t *cmd_extra_frames; 310 311 uint32_t cmd_rfm; 312 mptsas_target_t *cmd_tgt_addr; 313 } mptsas_cmd_t; 314 315 /* 316 * These are the defined cmd_flags for this structure. 317 */ 318 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 319 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 320 #define CFLAG_FINISHED 0x000004 /* command completed */ 321 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 322 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 323 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 324 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 325 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 326 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 327 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 328 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 329 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 330 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 331 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 332 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 333 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 334 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 335 #define CFLAG_FREE 0x010000 /* packet is on free list */ 336 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 337 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 338 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 339 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 340 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 341 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 342 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 343 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 344 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 345 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 346 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 347 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 348 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 349 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 350 351 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 352 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 353 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 354 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 355 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 356 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 357 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 358 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 359 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 360 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 361 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 362 363 #define MPTSAS_HASH_ARRAY_SIZE 16 364 /* 365 * hash table definition 366 */ 367 368 #define MPTSAS_HASH_FIRST 0xffff 369 #define MPTSAS_HASH_NEXT 0x0000 370 371 typedef struct mptsas_dma_alloc_state 372 { 373 ddi_dma_handle_t handle; 374 caddr_t memp; 375 size_t size; 376 ddi_acc_handle_t accessp; 377 ddi_dma_cookie_t cookie; 378 } mptsas_dma_alloc_state_t; 379 380 /* 381 * passthrough request structure 382 */ 383 typedef struct mptsas_pt_request { 384 uint8_t *request; 385 uint32_t request_size; 386 uint32_t data_size; 387 uint32_t dataout_size; 388 uint32_t direction; 389 uint8_t simple; 390 uint16_t sgl_offset; 391 ddi_dma_cookie_t data_cookie; 392 ddi_dma_cookie_t dataout_cookie; 393 } mptsas_pt_request_t; 394 395 /* 396 * config page request structure 397 */ 398 typedef struct mptsas_config_request { 399 uint32_t page_address; 400 uint8_t action; 401 uint8_t page_type; 402 uint8_t page_number; 403 uint8_t page_length; 404 uint8_t page_version; 405 uint8_t ext_page_type; 406 uint16_t ext_page_length; 407 } mptsas_config_request_t; 408 409 typedef struct mptsas_fw_diagnostic_buffer { 410 mptsas_dma_alloc_state_t buffer_data; 411 uint8_t extended_type; 412 uint8_t buffer_type; 413 uint8_t force_release; 414 uint32_t product_specific[23]; 415 uint8_t immediate; 416 uint8_t enabled; 417 uint8_t valid_data; 418 uint8_t owned_by_firmware; 419 uint32_t unique_id; 420 } mptsas_fw_diagnostic_buffer_t; 421 422 /* 423 * FW diag request structure 424 */ 425 typedef struct mptsas_diag_request { 426 mptsas_fw_diagnostic_buffer_t *pBuffer; 427 uint8_t function; 428 } mptsas_diag_request_t; 429 430 typedef struct mptsas_hash_node { 431 void *data; 432 struct mptsas_hash_node *next; 433 } mptsas_hash_node_t; 434 435 typedef struct mptsas_hash_table { 436 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 437 /* 438 * last position in traverse 439 */ 440 struct mptsas_hash_node *cur; 441 uint16_t line; 442 443 } mptsas_hash_table_t; 444 445 /* 446 * RAID volume information 447 */ 448 typedef struct mptsas_raidvol { 449 ushort_t m_israid; 450 uint16_t m_raidhandle; 451 uint64_t m_raidwwid; 452 uint8_t m_state; 453 uint32_t m_statusflags; 454 uint32_t m_settings; 455 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 456 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 457 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 458 uint64_t m_raidsize; 459 int m_raidlevel; 460 int m_ndisks; 461 mptsas_target_t *m_raidtgt; 462 } mptsas_raidvol_t; 463 464 /* 465 * RAID configurations 466 */ 467 typedef struct mptsas_raidconfig { 468 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 469 uint16_t m_physdisk_devhdl[ 470 MPTSAS_MAX_DISKS_IN_CONFIG]; 471 uint8_t m_native; 472 } m_raidconfig_t; 473 474 /* 475 * Track outstanding commands. The index into the m_slot array is the SMID 476 * (system message ID) of the outstanding command. SMID 0 is reserved by the 477 * software/firmware protocol and is never used for any command we generate; 478 * as such, the assertion m_slot[0] == NULL is universally true. The last 479 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for 480 * task management commands. No normal SCSI or ATA command will ever occupy 481 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any 482 * time that a consistent view of the target array is obtainable. 483 * 484 * As such, m_n_normal is the maximum number of slots available to ordinary 485 * commands, and the relationship: 486 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2 487 * always holds after initialisation. 488 */ 489 typedef struct mptsas_slots { 490 size_t m_size; /* size of struct, bytes */ 491 uint_t m_n_normal; /* see above */ 492 uint_t m_rotor; /* next slot idx to consider */ 493 mptsas_cmd_t *m_slot[1]; 494 } mptsas_slots_t; 495 496 /* 497 * Structure to hold command and packets for event ack 498 * and task management commands. 499 */ 500 typedef struct m_event_struct { 501 struct mptsas_cmd m_event_cmd; 502 struct m_event_struct *m_event_linkp; 503 /* 504 * event member record the failure event and eventcntx 505 * event member would be used in send ack pending process 506 */ 507 uint32_t m_event; 508 uint32_t m_eventcntx; 509 uint_t in_use; 510 struct scsi_pkt m_event_pkt; /* must be last */ 511 /* ... scsi_pkt_size() */ 512 } m_event_struct_t; 513 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 514 sizeof (struct scsi_pkt) + scsi_pkt_size()) 515 516 #define MAX_IOC_COMMANDS 8 517 518 /* 519 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 520 * A new event ack command requests mptsas_cmd and scsi_pkt structures 521 * from this pool, and returns it back when done. 522 */ 523 524 typedef struct m_replyh_arg { 525 void *mpt; 526 uint32_t rfm; 527 } m_replyh_arg_t; 528 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 529 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 530 531 /* 532 * Flags for DR handler topology change 533 */ 534 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 535 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 536 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 537 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 538 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 539 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 540 541 typedef struct mptsas_topo_change_list { 542 void *mpt; 543 uint_t event; 544 union { 545 uint8_t physport; 546 mptsas_phymask_t phymask; 547 } un; 548 uint16_t devhdl; 549 void *object; 550 uint8_t flags; 551 struct mptsas_topo_change_list *next; 552 } mptsas_topo_change_list_t; 553 554 555 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 556 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 557 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 558 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 559 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 560 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 561 562 /* 563 * Status types when calling mptsas_get_target_device_info 564 */ 565 #define DEV_INFO_SUCCESS 0x0 566 #define DEV_INFO_FAIL_PAGE0 0x1 567 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 568 #define DEV_INFO_PHYS_DISK 0x3 569 #define DEV_INFO_FAIL_ALLOC 0x4 570 #define DEV_INFO_FAIL_GUID 0x5 571 572 /* 573 * mpt hotplug event defines 574 */ 575 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 576 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 577 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 578 579 /* 580 * SMP target hotplug events 581 */ 582 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 583 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 584 #define MPTSAS_DR_EVENT_MASK 0x3F 585 586 /* 587 * mpt hotplug status definition for m_dr_flag 588 */ 589 590 /* 591 * MPTSAS_DR_INACTIVE 592 * 593 * The target is in a normal operating state. 594 * No dynamic reconfiguration operation is in progress. 595 */ 596 #define MPTSAS_DR_INACTIVE 0x0 597 /* 598 * MPTSAS_DR_INTRANSITION 599 * 600 * The target is in a transition mode since 601 * hotplug event happens and offline procedure has not 602 * been finished 603 */ 604 #define MPTSAS_DR_INTRANSITION 0x1 605 606 typedef struct mptsas_tgt_private { 607 int t_lun; 608 struct mptsas_target *t_private; 609 } mptsas_tgt_private_t; 610 611 /* 612 * The following defines are used in mptsas_set_init_mode to track the current 613 * state as we progress through reprogramming the HBA from target mode into 614 * initiator mode. 615 */ 616 617 #define IOUC_READ_PAGE0 0x00000100 618 #define IOUC_READ_PAGE1 0x00000200 619 #define IOUC_WRITE_PAGE1 0x00000400 620 #define IOUC_DONE 0x00000800 621 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 622 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 623 624 /* 625 * Last allocated slot is used for TM requests. Since only m_max_requests 626 * frames are allocated, the last SMID will be m_max_requests - 1. 627 */ 628 #define MPTSAS_SLOTS_SIZE(mpt) \ 629 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 630 mpt->m_max_requests)) 631 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 632 633 /* 634 * Macro for phy_flags 635 */ 636 637 typedef struct smhba_info { 638 kmutex_t phy_mutex; 639 uint8_t phy_id; 640 uint64_t sas_addr; 641 char path[8]; 642 uint16_t owner_devhdl; 643 uint16_t attached_devhdl; 644 uint8_t attached_phy_identify; 645 uint32_t attached_phy_info; 646 uint8_t programmed_link_rate; 647 uint8_t hw_link_rate; 648 uint8_t change_count; 649 uint32_t phy_info; 650 uint8_t negotiated_link_rate; 651 uint8_t port_num; 652 kstat_t *phy_stats; 653 uint32_t invalid_dword_count; 654 uint32_t running_disparity_error_count; 655 uint32_t loss_of_dword_sync_count; 656 uint32_t phy_reset_problem_count; 657 void *mpt; 658 } smhba_info_t; 659 660 typedef struct mptsas_phy_info { 661 uint8_t port_num; 662 uint8_t port_flags; 663 uint16_t ctrl_devhdl; 664 uint32_t phy_device_type; 665 uint16_t attached_devhdl; 666 mptsas_phymask_t phy_mask; 667 smhba_info_t smhba_info; 668 } mptsas_phy_info_t; 669 670 671 typedef struct mptsas_doneq_thread_arg { 672 void *mpt; 673 uint64_t t; 674 } mptsas_doneq_thread_arg_t; 675 676 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 677 typedef struct mptsas_doneq_thread_list { 678 mptsas_cmd_t *doneq; 679 mptsas_cmd_t **donetail; 680 kthread_t *threadp; 681 kcondvar_t cv; 682 ushort_t reserv1; 683 uint32_t reserv2; 684 kmutex_t mutex; 685 uint32_t flag; 686 uint32_t len; 687 mptsas_doneq_thread_arg_t arg; 688 } mptsas_doneq_thread_list_t; 689 690 typedef struct mptsas { 691 int m_instance; 692 693 struct mptsas *m_next; 694 695 scsi_hba_tran_t *m_tran; 696 smp_hba_tran_t *m_smptran; 697 kmutex_t m_mutex; 698 kmutex_t m_passthru_mutex; 699 kcondvar_t m_cv; 700 kcondvar_t m_passthru_cv; 701 kcondvar_t m_fw_cv; 702 kcondvar_t m_config_cv; 703 kcondvar_t m_fw_diag_cv; 704 dev_info_t *m_dip; 705 706 /* 707 * soft state flags 708 */ 709 uint_t m_softstate; 710 711 refhash_t *m_targets; 712 refhash_t *m_smp_targets; 713 list_t m_enclosures; 714 refhash_t *m_tmp_targets; 715 716 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 717 uint8_t m_num_raid_configs; 718 719 struct mptsas_slots *m_active; /* outstanding cmds */ 720 721 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 722 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 723 724 kmutex_t m_tx_waitq_mutex; 725 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */ 726 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */ 727 int m_tx_draining; /* TX queue draining flag */ 728 729 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 730 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 731 732 /* 733 * variables for helper threads (fan-out interrupts) 734 */ 735 mptsas_doneq_thread_list_t *m_doneq_thread_id; 736 uint32_t m_doneq_thread_n; 737 uint32_t m_doneq_thread_threshold; 738 uint32_t m_doneq_length_threshold; 739 uint32_t m_doneq_len; 740 kcondvar_t m_doneq_thread_cv; 741 kmutex_t m_doneq_mutex; 742 743 int m_ncmds; /* number of outstanding commands */ 744 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 745 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 746 747 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 748 749 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 750 751 ushort_t m_devid; /* device id of chip. */ 752 uchar_t m_revid; /* revision of chip. */ 753 uint16_t m_svid; /* subsystem Vendor ID of chip */ 754 uint16_t m_ssid; /* subsystem Device ID of chip */ 755 756 uchar_t m_sync_offset; /* default offset for this chip. */ 757 758 timeout_id_t m_quiesce_timeid; 759 760 ddi_dma_handle_t m_dma_req_frame_hdl; 761 ddi_acc_handle_t m_acc_req_frame_hdl; 762 ddi_dma_handle_t m_dma_req_sense_hdl; 763 ddi_acc_handle_t m_acc_req_sense_hdl; 764 ddi_dma_handle_t m_dma_reply_frame_hdl; 765 ddi_acc_handle_t m_acc_reply_frame_hdl; 766 ddi_dma_handle_t m_dma_free_queue_hdl; 767 ddi_acc_handle_t m_acc_free_queue_hdl; 768 ddi_dma_handle_t m_dma_post_queue_hdl; 769 ddi_acc_handle_t m_acc_post_queue_hdl; 770 771 /* 772 * list of reset notification requests 773 */ 774 struct scsi_reset_notify_entry *m_reset_notify_listf; 775 776 /* 777 * qfull handling 778 */ 779 timeout_id_t m_restart_cmd_timeid; 780 781 /* 782 * scsi reset delay per bus 783 */ 784 uint_t m_scsi_reset_delay; 785 786 int m_pm_idle_delay; 787 788 uchar_t m_polled_intr; /* intr was polled. */ 789 uchar_t m_suspended; /* true if driver is suspended */ 790 791 struct kmem_cache *m_kmem_cache; 792 struct kmem_cache *m_cache_frames; 793 794 /* 795 * hba options. 796 */ 797 uint_t m_options; 798 799 int m_in_callback; 800 801 int m_power_level; /* current power level */ 802 803 int m_busy; /* power management busy state */ 804 805 off_t m_pmcsr_offset; /* PMCSR offset */ 806 807 ddi_acc_handle_t m_config_handle; 808 809 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 810 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 811 ddi_device_acc_attr_t m_dev_acc_attr; 812 ddi_device_acc_attr_t m_reg_acc_attr; 813 814 /* 815 * request/reply variables 816 */ 817 caddr_t m_req_frame; 818 uint64_t m_req_frame_dma_addr; 819 caddr_t m_req_sense; 820 caddr_t m_extreq_sense; 821 uint_t m_extreq_sense_refcount; 822 kcondvar_t m_extreq_sense_refcount_cv; 823 uint64_t m_req_sense_dma_addr; 824 caddr_t m_reply_frame; 825 uint64_t m_reply_frame_dma_addr; 826 caddr_t m_free_queue; 827 uint64_t m_free_queue_dma_addr; 828 caddr_t m_post_queue; 829 uint64_t m_post_queue_dma_addr; 830 struct map *m_erqsense_map; 831 832 m_replyh_arg_t *m_replyh_args; 833 834 uint16_t m_max_requests; 835 uint16_t m_req_frame_size; 836 uint16_t m_req_sense_size; 837 838 /* 839 * Max frames per request reprted in IOC Facts 840 */ 841 uint8_t m_max_chain_depth; 842 /* 843 * Max frames per request which is used in reality. It's adjusted 844 * according DMA SG length attribute, and shall not exceed the 845 * m_max_chain_depth. 846 */ 847 uint8_t m_max_request_frames; 848 849 uint16_t m_free_queue_depth; 850 uint16_t m_post_queue_depth; 851 uint16_t m_max_replies; 852 uint32_t m_free_index; 853 uint32_t m_post_index; 854 uint8_t m_reply_frame_size; 855 uint32_t m_ioc_capabilities; 856 857 /* 858 * indicates if the firmware was upload by the driver 859 * at boot time 860 */ 861 ushort_t m_fwupload; 862 863 uint16_t m_productid; 864 865 /* 866 * per instance data structures for dma memory resources for 867 * MPI handshake protocol. only one handshake cmd can run at a time. 868 */ 869 ddi_dma_handle_t m_hshk_dma_hdl; 870 ddi_acc_handle_t m_hshk_acc_hdl; 871 caddr_t m_hshk_memp; 872 size_t m_hshk_dma_size; 873 874 /* Firmware version on the card at boot time */ 875 uint32_t m_fwversion; 876 877 /* MSI specific fields */ 878 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 879 int m_intr_type; /* What type of interrupt */ 880 int m_intr_cnt; /* # of intrs count returned */ 881 size_t m_intr_size; /* Size of intr array */ 882 uint_t m_intr_pri; /* Interrupt priority */ 883 int m_intr_cap; /* Interrupt capabilities */ 884 ddi_taskq_t *m_event_taskq; 885 886 /* SAS specific information */ 887 888 union { 889 uint64_t m_base_wwid; /* Base WWID */ 890 struct { 891 #ifdef _BIG_ENDIAN 892 uint32_t m_base_wwid_hi; 893 uint32_t m_base_wwid_lo; 894 #else 895 uint32_t m_base_wwid_lo; 896 uint32_t m_base_wwid_hi; 897 #endif 898 } sasaddr; 899 } un; 900 901 uint8_t m_num_phys; /* # of PHYs */ 902 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 903 uint8_t m_port_chng; /* initiator port changes */ 904 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */ 905 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */ 906 907 /* FMA Capabilities */ 908 int m_fm_capabilities; 909 ddi_taskq_t *m_dr_taskq; 910 int m_mpxio_enable; 911 uint8_t m_done_traverse_dev; 912 uint8_t m_done_traverse_smp; 913 uint8_t m_done_traverse_enc; 914 int m_diag_action_in_progress; 915 uint16_t m_dev_handle; 916 uint16_t m_smp_devhdl; 917 918 /* DDI UFM Handle */ 919 ddi_ufm_handle_t *m_ufmh; 920 921 /* 922 * Event recording 923 */ 924 uint8_t m_event_index; 925 uint32_t m_event_number; 926 uint32_t m_event_mask[4]; 927 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 928 929 /* 930 * FW diag Buffer List 931 */ 932 mptsas_fw_diagnostic_buffer_t 933 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 934 935 /* GEN3 support */ 936 uint8_t m_MPI25; 937 938 /* 939 * Event Replay flag (MUR support) 940 */ 941 uint8_t m_event_replay; 942 943 /* 944 * IR Capable flag 945 */ 946 uint8_t m_ir_capable; 947 948 /* 949 * Is HBA processing a diag reset? 950 */ 951 uint8_t m_in_reset; 952 953 /* 954 * per instance cmd data structures for task management cmds 955 */ 956 m_event_struct_t m_event_task_mgmt; /* must be last */ 957 /* ... scsi_pkt_size */ 958 } mptsas_t; 959 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 960 sizeof (struct scsi_pkt) + scsi_pkt_size()) 961 /* 962 * Only one of below two conditions is satisfied, we 963 * think the target is associated to the iport and 964 * allow call into mptsas_probe_lun(). 965 * 1. physicalsport == physport 966 * 2. (phymask & (1 << physport)) == 0 967 * The condition #2 is because LSI uses lowest PHY 968 * number as the value of physical port when auto port 969 * configuration. 970 */ 971 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 972 ((physicalport == physport) || (dynamicport && (phymask & \ 973 (1 << physport)))) 974 975 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 976 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 977 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 978 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 979 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 980 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 981 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 982 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 983 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 984 985 /* 986 * These should eventually migrate into the mpt header files 987 * that may become the /kernel/misc/mpt module... 988 */ 989 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 990 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 991 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 992 mptsas_put_msg_Function(hdl, mp, Function); \ 993 mptsas_put_msg_Lun(hdl, mp, Lun) 994 995 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 996 ddi_put16(hdl, &(mp)->DevHandle, (val)) 997 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 998 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 999 #define mptsas_put_msg_Function(hdl, mp, val) \ 1000 ddi_put8(hdl, &(mp)->Function, (val)) 1001 #define mptsas_put_msg_Lun(hdl, mp, val) \ 1002 ddi_put8(hdl, &(mp)->LUN[1], (val)) 1003 1004 #define mptsas_get_msg_Function(hdl, mp) \ 1005 ddi_get8(hdl, &(mp)->Function) 1006 1007 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 1008 ddi_get8(hdl, &(mp)->MsgFlags) 1009 1010 #define MPTSAS_ENABLE_DRWE(hdl) \ 1011 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1012 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 1013 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1014 MPI2_WRSEQ_1ST_KEY_VALUE); \ 1015 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1016 MPI2_WRSEQ_2ND_KEY_VALUE); \ 1017 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1018 MPI2_WRSEQ_3RD_KEY_VALUE); \ 1019 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1020 MPI2_WRSEQ_4TH_KEY_VALUE); \ 1021 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1022 MPI2_WRSEQ_5TH_KEY_VALUE); \ 1023 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1024 MPI2_WRSEQ_6TH_KEY_VALUE); 1025 1026 /* 1027 * m_options flags 1028 */ 1029 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 1030 1031 /* 1032 * m_softstate flags 1033 */ 1034 #define MPTSAS_SS_DRAINING 0x02 1035 #define MPTSAS_SS_QUIESCED 0x04 1036 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 1037 #define MPTSAS_DID_MSG_UNIT_RESET 0x10 1038 1039 /* 1040 * regspec defines. 1041 */ 1042 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 1043 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 1044 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 1045 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 1046 1047 /* 1048 * Handy constants 1049 */ 1050 #define FALSE 0 1051 #define TRUE 1 1052 #define UNDEFINED -1 1053 #define FAILED -2 1054 1055 /* 1056 * power management. 1057 */ 1058 #define MPTSAS_POWER_ON(mpt) { \ 1059 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1060 PCI_PMCSR_D0); \ 1061 delay(drv_usectohz(10000)); \ 1062 (void) pci_restore_config_regs(mpt->m_dip); \ 1063 mptsas_setup_cmd_reg(mpt); \ 1064 } 1065 1066 #define MPTSAS_POWER_OFF(mpt) { \ 1067 (void) pci_save_config_regs(mpt->m_dip); \ 1068 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1069 PCI_PMCSR_D3HOT); \ 1070 mpt->m_power_level = PM_LEVEL_D3; \ 1071 } 1072 1073 /* 1074 * inq_dtype: 1075 * Bits 5 through 7 are the Peripheral Device Qualifier 1076 * 001b: device not connected to the LUN 1077 * Bits 0 through 4 are the Peripheral Device Type 1078 * 1fh: Unknown or no device type 1079 * 1080 * Although the inquiry may return success, the following value 1081 * means no valid LUN connected. 1082 */ 1083 #define MPTSAS_VALID_LUN(sd_inq) \ 1084 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 1085 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 1086 1087 /* 1088 * Default is to have 10 retries on receiving QFULL status and 1089 * each retry to be after 100 ms. 1090 */ 1091 #define QFULL_RETRIES 10 1092 #define QFULL_RETRY_INTERVAL 100 1093 1094 /* 1095 * Handy macros 1096 */ 1097 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1098 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1099 1100 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1101 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1102 1103 /* 1104 * poll time for mptsas_pollret() and mptsas_wait_intr() 1105 */ 1106 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1107 1108 /* 1109 * default time for mptsas_do_passthru 1110 */ 1111 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1112 1113 /* 1114 * macro to return the effective address of a given per-target field 1115 */ 1116 #define EFF_ADDR(start, offset) ((start) + (offset)) 1117 1118 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1119 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1120 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1121 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1122 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1123 1124 1125 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1126 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1127 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1128 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1129 1130 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1131 1132 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1133 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1134 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1135 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1136 1137 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \ 1138 &(mpt)->m_reg->HostInterruptStatus)) 1139 1140 #define MPTSAS_SET_SIGP(P) \ 1141 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1142 1143 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1144 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1145 1146 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \ 1147 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1148 1149 1150 #define MPTSAS_START_CMD(mpt, req_desc) \ 1151 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow, \ 1152 req_desc & 0xffffffffu); \ 1153 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh, \ 1154 (req_desc >> 32) & 0xffffffffu); 1155 1156 #define INTPENDING(mpt) \ 1157 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1158 1159 /* 1160 * Mask all interrupts to disable 1161 */ 1162 #define MPTSAS_DISABLE_INTR(mpt) \ 1163 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1164 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1165 1166 /* 1167 * Mask Doorbell and Reset interrupts to enable reply desc int. 1168 */ 1169 #define MPTSAS_ENABLE_INTR(mpt) \ 1170 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1171 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1172 1173 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1174 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1175 1176 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1177 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1178 1179 #define ClrSetBits32(hdl, reg, clr, set) \ 1180 ddi_put32(hdl, (reg), \ 1181 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set))) 1182 1183 #define ClrSetBits(reg, clr, set) \ 1184 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1185 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1186 1187 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1188 if ((cmdp = mpt->m_waitq) != NULL) { \ 1189 /* If the queue is now empty fix the tail pointer */ \ 1190 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1191 mpt->m_waitqtail = &mpt->m_waitq; \ 1192 cmdp->cmd_linkp = NULL; \ 1193 cmdp->cmd_queued = FALSE; \ 1194 } 1195 1196 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1197 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1198 /* If the queue is now empty fix the tail pointer */ \ 1199 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1200 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1201 cmdp->cmd_linkp = NULL; \ 1202 cmdp->cmd_queued = FALSE; \ 1203 } 1204 1205 /* 1206 * defaults for the global properties 1207 */ 1208 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1209 #define DEFAULT_TAG_AGE_LIMIT 2 1210 #define DEFAULT_WD_TICK 1 1211 1212 /* 1213 * invalid hostid. 1214 */ 1215 #define MPTSAS_INVALID_HOSTID -1 1216 1217 /* 1218 * Get/Set hostid from SCSI port configuration page 1219 */ 1220 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1221 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1222 1223 /* 1224 * Config space. 1225 */ 1226 #define MPTSAS_LATENCY_TIMER 0x40 1227 1228 /* 1229 * Offset to firmware version 1230 */ 1231 #define MPTSAS_FW_VERSION_OFFSET 9 1232 1233 /* 1234 * Offset and masks to get at the ProductId field 1235 */ 1236 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1237 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1238 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1239 1240 /* 1241 * Subsystem ID for HBAs. 1242 */ 1243 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1244 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1245 1246 /* 1247 * reset delay tick 1248 */ 1249 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1250 1251 /* 1252 * Ioc reset return values 1253 */ 1254 #define MPTSAS_RESET_FAIL -1 1255 #define MPTSAS_NO_RESET 0 1256 #define MPTSAS_SUCCESS_HARDRESET 1 1257 #define MPTSAS_SUCCESS_MUR 2 1258 1259 /* 1260 * throttle support. 1261 */ 1262 #define MAX_THROTTLE 32 1263 #define HOLD_THROTTLE 0 1264 #define DRAIN_THROTTLE -1 1265 #define QFULL_THROTTLE -2 1266 1267 /* 1268 * Passthrough/config request flags 1269 */ 1270 #define MPTSAS_DATA_ALLOCATED 0x0001 1271 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1272 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1273 #define MPTSAS_ADDRESS_REPLY 0x0008 1274 #define MPTSAS_CMD_TIMEOUT 0x0010 1275 1276 /* 1277 * response code tlr flag 1278 */ 1279 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1280 1281 /* 1282 * System Events 1283 */ 1284 #ifndef DDI_VENDOR_LSI 1285 #define DDI_VENDOR_LSI "LSI" 1286 #endif /* DDI_VENDOR_LSI */ 1287 1288 /* 1289 * Shared functions 1290 */ 1291 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1292 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1293 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1294 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1295 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1296 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1297 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1298 uint8_t type, int mode); 1299 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1300 uint8_t type, int mode); 1301 int mptsas_download_firmware(); 1302 int mptsas_can_download_firmware(); 1303 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1304 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1305 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1306 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1307 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1308 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1309 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1310 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 1311 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 1312 uint32_t alloc_size, ddi_dma_cookie_t *cookiep); 1313 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *); 1314 1315 /* 1316 * impl functions 1317 */ 1318 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1319 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1320 int mptsas_ioc_reset(mptsas_t *mpt, int); 1321 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1322 ddi_acc_handle_t accessp); 1323 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1324 ddi_acc_handle_t accessp); 1325 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1326 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1327 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1328 uint64_t SGEaddress); 1329 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1330 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1331 uint8_t pageversion, uint16_t extpagelength, 1332 uint32_t SGEflagslength, uint64_t SGEaddress); 1333 1334 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1335 struct scsi_pkt **pkt); 1336 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1337 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1338 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1339 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1340 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1341 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1342 1343 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1344 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1345 int mode); 1346 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1347 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1348 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1349 int mptsas_restart_ioc(mptsas_t *mpt); 1350 void mptsas_update_driver_data(struct mptsas *mpt); 1351 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1352 1353 /* 1354 * init functions 1355 */ 1356 int mptsas_ioc_get_facts(mptsas_t *mpt); 1357 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1358 int mptsas_ioc_enable_port(mptsas_t *mpt); 1359 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1360 int mptsas_ioc_init(mptsas_t *mpt); 1361 1362 /* 1363 * configuration pages operation 1364 */ 1365 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1366 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1367 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle, 1368 uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags); 1369 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1370 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1371 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1372 mptsas_smp_t *info); 1373 int mptsas_set_ioc_params(mptsas_t *mpt); 1374 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1375 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1376 uint64_t *sas_wwn, uint8_t *portwidth); 1377 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1378 int mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address, 1379 smhba_info_t *info); 1380 int mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address, 1381 smhba_info_t *info); 1382 int mptsas_get_manufacture_page0(mptsas_t *mpt); 1383 int mptsas_get_enclosure_page0(mptsas_t *mpt, uint32_t page_address, 1384 mptsas_enclosure_t *mpe); 1385 void mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip); 1386 void mptsas_destroy_phy_stats(mptsas_t *mpt); 1387 int mptsas_smhba_phy_init(mptsas_t *mpt); 1388 /* 1389 * RAID functions 1390 */ 1391 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1392 int mptsas_get_raid_info(mptsas_t *mpt); 1393 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1394 uint8_t physdisknum); 1395 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1396 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1397 1398 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1399 /* 1400 * debugging. 1401 * MPTSAS_DBGLOG_LINECNT must be a power of 2. 1402 */ 1403 #define MPTSAS_DBGLOG_LINECNT 128 1404 #define MPTSAS_DBGLOG_LINELEN 256 1405 #define MPTSAS_DBGLOG_BUFSIZE (MPTSAS_DBGLOG_LINECNT * MPTSAS_DBGLOG_LINELEN) 1406 1407 #if defined(MPTSAS_DEBUG) 1408 1409 extern uint32_t mptsas_debugprt_flags; 1410 extern uint32_t mptsas_debuglog_flags; 1411 1412 void mptsas_printf(char *fmt, ...); 1413 void mptsas_debug_log(char *fmt, ...); 1414 1415 #define MPTSAS_DBGPR(m, args) \ 1416 if (mptsas_debugprt_flags & (m)) \ 1417 mptsas_printf args; \ 1418 if (mptsas_debuglog_flags & (m)) \ 1419 mptsas_debug_log args 1420 #else /* ! defined(MPTSAS_DEBUG) */ 1421 #define MPTSAS_DBGPR(m, args) 1422 #endif /* defined(MPTSAS_DEBUG) */ 1423 1424 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1425 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1426 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1427 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1428 1429 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1430 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1431 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1432 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1433 1434 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1435 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1436 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1437 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1438 1439 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1440 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1441 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */ 1442 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */ 1443 1444 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) /* SAS Broadcasts */ 1445 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1446 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1447 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1448 1449 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1450 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1451 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1452 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1453 1454 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1455 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1456 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1457 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) /* passthrough */ 1458 1459 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1460 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1461 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1462 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1463 1464 /* 1465 * auto request sense 1466 */ 1467 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1468 (pkt)->pkt_flags = (flag), \ 1469 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1470 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1471 (pkt)->pkt_address.a_lun 1472 1473 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1474 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1475 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1476 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1477 1478 1479 #ifdef __cplusplus 1480 } 1481 #endif 1482 1483 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1484