1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2017, Joyent, Inc. 24 */ 25 26 /* 27 * Copyright 2019, Joyent, Inc. 28 */ 29 30 #ifndef _SYS_PCIE_IMPL_H 31 #define _SYS_PCIE_IMPL_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #include <sys/pcie.h> 38 #include <sys/pciev.h> 39 40 #define PCI_GET_BDF(dip) \ 41 PCIE_DIP2BUS(dip)->bus_bdf 42 #define PCI_GET_SEC_BUS(dip) \ 43 PCIE_DIP2BUS(dip)->bus_bdg_secbus 44 #define PCI_GET_PCIE2PCI_SECBUS(dip) \ 45 PCIE_DIP2BUS(dip)->bus_pcie2pci_secbus 46 47 #define DEVI_PORT_TYPE_PCI \ 48 ((PCI_CLASS_BRIDGE << 16) | (PCI_BRIDGE_PCI << 8) | \ 49 PCI_BRIDGE_PCI_IF_PCI2PCI) 50 51 #define PCIE_DIP2BUS(dip) \ 52 (ndi_port_type(dip, B_TRUE, DEVI_PORT_TYPE_PCI) ? \ 53 PCIE_DIP2UPBUS(dip) : \ 54 ndi_port_type(dip, B_FALSE, DEVI_PORT_TYPE_PCI) ? \ 55 PCIE_DIP2DOWNBUS(dip) : NULL) 56 57 #define PCIE_DIP2UPBUS(dip) \ 58 ((pcie_bus_t *)ndi_get_bus_private(dip, B_TRUE)) 59 #define PCIE_DIP2DOWNBUS(dip) \ 60 ((pcie_bus_t *)ndi_get_bus_private(dip, B_FALSE)) 61 #define PCIE_DIP2PFD(dip) (PCIE_DIP2BUS(dip))->bus_pfd 62 #define PCIE_PFD2BUS(pfd_p) pfd_p->pe_bus_p 63 #define PCIE_PFD2DIP(pfd_p) PCIE_PFD2BUS(pfd_p)->bus_dip 64 #define PCIE_BUS2DIP(bus_p) bus_p->bus_dip 65 #define PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p)) 66 #define PCIE_BUS2DOM(bus_p) bus_p->bus_dom 67 #define PCIE_DIP2DOM(dip) PCIE_BUS2DOM(PCIE_DIP2BUS(dip)) 68 69 /* 70 * These macros depend on initialization of type related data in bus_p. 71 */ 72 #define PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off) 73 #define PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off) 74 #define PCIE_IS_PCI(bus_p) (!PCIE_IS_PCIE(bus_p)) 75 #define PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off) 76 /* IS_ROOT = is RC or RP */ 77 #define PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p)) 78 79 #define PCIE_IS_HOTPLUG_CAPABLE(dip) \ 80 (PCIE_DIP2BUS(dip)->bus_hp_sup_modes) 81 82 #define PCIE_IS_HOTPLUG_ENABLED(dip) \ 83 ((PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_PCI_HP_MODE) || \ 84 (PCIE_DIP2BUS(dip)->bus_hp_curr_mode == PCIE_NATIVE_HP_MODE)) 85 86 /* 87 * This is a pseudo pcie "device type", but it's needed to explain describe 88 * nodes such as PX and NPE, which aren't really PCI devices but do control or 89 * interaction with PCI error handling. 90 */ 91 #define PCIE_IS_RC(bus_p) \ 92 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO) 93 #define PCIE_IS_RP(bus_p) \ 94 ((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) && \ 95 PCIE_IS_PCIE(bus_p)) 96 #define PCIE_IS_SWU(bus_p) \ 97 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_UP) 98 #define PCIE_IS_SWD(bus_p) \ 99 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) 100 #define PCIE_IS_SW(bus_p) \ 101 (PCIE_IS_SWU(bus_p) || PCIE_IS_SWD(bus_p)) 102 #define PCIE_IS_BDG(bus_p) (bus_p->bus_hdr_type == PCI_HEADER_ONE) 103 #define PCIE_IS_PCI_BDG(bus_p) (PCIE_IS_PCI(bus_p) && PCIE_IS_BDG(bus_p)) 104 #define PCIE_IS_PCIE_BDG(bus_p) \ 105 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) 106 #define PCIE_IS_PCI2PCIE(bus_p) \ 107 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE) 108 #define PCIE_IS_PCIE_SEC(bus_p) \ 109 (PCIE_IS_PCIE(bus_p) && PCIE_IS_BDG(bus_p) && !PCIE_IS_PCIE_BDG(bus_p)) 110 #define PCIX_ECC_VERSION_CHECK(bus_p) \ 111 ((bus_p->bus_ecc_ver == PCI_PCIX_VER_1) || \ 112 (bus_p->bus_ecc_ver == PCI_PCIX_VER_2)) 113 114 #define PCIE_VENID(bus_p) (bus_p->bus_dev_ven_id & 0xffff) 115 #define PCIE_DEVID(bus_p) ((bus_p->bus_dev_ven_id >> 16) & 0xffff) 116 117 /* PCIE Cap/AER shortcuts */ 118 #define PCIE_GET(sz, bus_p, off) \ 119 pci_config_get ## sz(bus_p->bus_cfg_hdl, off) 120 #define PCIE_PUT(sz, bus_p, off, val) \ 121 pci_config_put ## sz(bus_p->bus_cfg_hdl, off, val) 122 #define PCIE_CAP_GET(sz, bus_p, off) \ 123 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcie_off, off) 124 #define PCIE_CAP_PUT(sz, bus_p, off, val) \ 125 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcie_off, off, \ 126 val) 127 #define PCIE_AER_GET(sz, bus_p, off) \ 128 PCI_XCAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_aer_off, off) 129 #define PCIE_AER_PUT(sz, bus_p, off, val) \ 130 PCI_XCAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_aer_off, off, \ 131 val) 132 #define PCIX_CAP_GET(sz, bus_p, off) \ 133 PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcix_off, off) 134 #define PCIX_CAP_PUT(sz, bus_p, off, val) \ 135 PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, 0, bus_p->bus_pcix_off, off, \ 136 val) 137 138 /* Translate PF error return values to DDI_FM values */ 139 #define PF_ERR2DDIFM_ERR(sts) \ 140 (sts & PF_ERR_FATAL_FLAGS ? DDI_FM_FATAL : \ 141 (sts == PF_ERR_NO_ERROR ? DDI_FM_OK : DDI_FM_NONFATAL)) 142 143 /* 144 * The following flag is used for Broadcom 5714/5715 bridge prefetch issue. 145 * This flag will be used both by px and pcieb nexus drivers. 146 */ 147 #define PX_DMAI_FLAGS_MAP_BUFZONE 0x40000 148 149 /* 150 * PCI(e/-X) structures used to to gather and report errors detected by 151 * PCI(e/-X) compliant devices. These registers only contain "dynamic" data. 152 * Static data such as Capability Offsets and Version #s is saved in the parent 153 * private data. 154 */ 155 #define PCI_ERR_REG(pfd_p) pfd_p->pe_pci_regs 156 #define PCI_BDG_ERR_REG(pfd_p) PCI_ERR_REG(pfd_p)->pci_bdg_regs 157 #define PCIX_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcix_regs 158 #define PCIX_ECC_REG(pfd_p) PCIX_ERR_REG(pfd_p)->pcix_ecc_regs 159 #define PCIX_BDG_ERR_REG(pfd_p) pfd_p->pe_pcix_bdg_regs 160 #define PCIX_BDG_ECC_REG(pfd_p, n) PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_ecc_regs[n] 161 #define PCIE_ERR_REG(pfd_p) pfd_p->pe_ext.pe_pcie_regs 162 #define PCIE_RP_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_rp_regs 163 #define PCIE_ROOT_FAULT(pfd_p) pfd_p->pe_root_fault 164 #define PCIE_ROOT_EH_SRC(pfd_p) pfd_p->pe_root_eh_src 165 #define PCIE_ADV_REG(pfd_p) PCIE_ERR_REG(pfd_p)->pcie_adv_regs 166 #define PCIE_ADV_HDR(pfd_p, n) PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[n] 167 #define PCIE_ADV_BDG_REG(pfd_p) \ 168 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_bdg_regs 169 #define PCIE_ADV_BDG_HDR(pfd_p, n) PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[n] 170 #define PCIE_ADV_RP_REG(pfd_p) \ 171 PCIE_ADV_REG(pfd_p)->pcie_ext.pcie_adv_rp_regs 172 #define PFD_AFFECTED_DEV(pfd_p) pfd_p->pe_affected_dev 173 #define PFD_SET_AFFECTED_FLAG(pfd_p, aff_flag) \ 174 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = aff_flag 175 #define PFD_SET_AFFECTED_BDF(pfd_p, bdf) \ 176 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = bdf 177 178 #define PFD_IS_ROOT(pfd_p) PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p)) 179 #define PFD_IS_RC(pfd_p) PCIE_IS_RC(PCIE_PFD2BUS(pfd_p)) 180 #define PFD_IS_RP(pfd_p) PCIE_IS_RP(PCIE_PFD2BUS(pfd_p)) 181 182 /* bus_hp_mode field */ 183 typedef enum { 184 PCIE_NONE_HP_MODE = 0x0, 185 PCIE_ACPI_HP_MODE = 0x1, 186 PCIE_PCI_HP_MODE = 0x2, 187 PCIE_NATIVE_HP_MODE = 0x4 188 } pcie_hp_mode_t; 189 190 typedef struct pf_pci_bdg_err_regs { 191 uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 192 uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 193 } pf_pci_bdg_err_regs_t; 194 195 typedef struct pf_pci_err_regs { 196 uint16_t pci_err_status; /* pci status register */ 197 uint16_t pci_cfg_comm; /* pci command register */ 198 pf_pci_bdg_err_regs_t *pci_bdg_regs; 199 } pf_pci_err_regs_t; 200 201 typedef struct pf_pcix_ecc_regs { 202 uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */ 203 uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */ 204 uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */ 205 uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */ 206 } pf_pcix_ecc_regs_t; 207 208 typedef struct pf_pcix_err_regs { 209 uint16_t pcix_command; /* pcix command register */ 210 uint32_t pcix_status; /* pcix status register */ 211 pf_pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */ 212 } pf_pcix_err_regs_t; 213 214 typedef struct pf_pcix_bdg_err_regs { 215 uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 216 uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 217 pf_pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */ 218 } pf_pcix_bdg_err_regs_t; 219 220 typedef struct pf_pcie_adv_bdg_err_regs { 221 uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */ 222 uint32_t pcie_sue_status; /* pcie bridge secondary ue status */ 223 uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */ 224 uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */ 225 uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */ 226 uint32_t pcie_sue_tgt_trans; /* Fault trans type from SAER Logs */ 227 uint64_t pcie_sue_tgt_addr; /* Fault addr from SAER Logs */ 228 pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */ 229 } pf_pcie_adv_bdg_err_regs_t; 230 231 typedef struct pf_pcie_adv_rp_err_regs { 232 uint32_t pcie_rp_err_status; /* pcie root complex error status reg */ 233 uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */ 234 uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */ 235 uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */ 236 } pf_pcie_adv_rp_err_regs_t; 237 238 typedef struct pf_pcie_adv_err_regs { 239 uint32_t pcie_adv_ctl; /* pcie advanced control reg */ 240 uint32_t pcie_ue_status; /* pcie ue error status reg */ 241 uint32_t pcie_ue_mask; /* pcie ue error mask reg */ 242 uint32_t pcie_ue_sev; /* pcie ue error severity reg */ 243 uint32_t pcie_ue_hdr[4]; /* pcie ue header log */ 244 uint32_t pcie_ce_status; /* pcie ce error status reg */ 245 uint32_t pcie_ce_mask; /* pcie ce error mask reg */ 246 union { 247 pf_pcie_adv_bdg_err_regs_t *pcie_adv_bdg_regs; /* bdg regs */ 248 pf_pcie_adv_rp_err_regs_t *pcie_adv_rp_regs; /* rp regs */ 249 } pcie_ext; 250 uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */ 251 uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */ 252 pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from AER Logs */ 253 } pf_pcie_adv_err_regs_t; 254 255 typedef struct pf_pcie_rp_err_regs { 256 uint32_t pcie_rp_status; /* root complex status register */ 257 uint16_t pcie_rp_ctl; /* root complex control register */ 258 } pf_pcie_rp_err_regs_t; 259 260 typedef struct pf_pcie_err_regs { 261 uint16_t pcie_err_status; /* pcie device status register */ 262 uint16_t pcie_err_ctl; /* pcie error control register */ 263 uint32_t pcie_dev_cap; /* pcie device capabilities register */ 264 pf_pcie_rp_err_regs_t *pcie_rp_regs; /* pcie root complex regs */ 265 pf_pcie_adv_err_regs_t *pcie_adv_regs; /* pcie aer regs */ 266 } pf_pcie_err_regs_t; 267 268 typedef enum { 269 PF_INTR_TYPE_NONE = 0, 270 PF_INTR_TYPE_FABRIC = 1, /* Fabric Message */ 271 PF_INTR_TYPE_DATA, /* Data Access Failure, failed loads */ 272 PF_INTR_TYPE_AER, /* Root Port AER MSI */ 273 PF_INTR_TYPE_INTERNAL /* Chip specific internal errors */ 274 } pf_intr_type_t; 275 276 typedef struct pf_root_eh_src { 277 pf_intr_type_t intr_type; 278 void *intr_data; /* Interrupt Data */ 279 } pf_root_eh_src_t; 280 281 typedef struct pf_root_fault { 282 pcie_req_id_t scan_bdf; /* BDF from error logs */ 283 uint64_t scan_addr; /* Addr from error logs */ 284 boolean_t full_scan; /* Option to do a full scan */ 285 } pf_root_fault_t; 286 287 typedef struct pf_data pf_data_t; 288 289 typedef enum pcie_link_width { 290 PCIE_LINK_WIDTH_UNKNOWN, 291 PCIE_LINK_WIDTH_X1, 292 PCIE_LINK_WIDTH_X2, 293 PCIE_LINK_WIDTH_X4, 294 PCIE_LINK_WIDTH_X8, 295 PCIE_LINK_WIDTH_X12, 296 PCIE_LINK_WIDTH_X16, 297 PCIE_LINK_WIDTH_X32 298 } pcie_link_width_t; 299 300 /* 301 * Note, this member should always be treated as a bit field, as a device may 302 * support multiple speeds. 303 */ 304 typedef enum pcie_link_speed { 305 PCIE_LINK_SPEED_UNKNOWN = 0x00, 306 PCIE_LINK_SPEED_2_5 = 0x01, 307 PCIE_LINK_SPEED_5 = 0x02, 308 PCIE_LINK_SPEED_8 = 0x04 309 } pcie_link_speed_t; 310 311 /* 312 * For hot plugged device, these data are init'ed during during probe 313 * For non-hotplugged device, these data are init'ed in pci_autoconfig (on x86), 314 * or in px_attach()(on sparc). 315 * 316 * For root complex the fields are initialized in pcie_rc_init_bus(); 317 * for others part of the fields are initialized in pcie_init_bus(), 318 * and part of fields initialized in pcie_post_init_bus(). See comments 319 * on top of respective functions for details. 320 */ 321 typedef struct pcie_bus { 322 /* Needed for PCI/PCIe fabric error handling */ 323 dev_info_t *bus_dip; 324 dev_info_t *bus_rp_dip; 325 ddi_acc_handle_t bus_cfg_hdl; /* error handling acc hdle */ 326 uint_t bus_fm_flags; 327 uint_t bus_soft_state; 328 329 /* Static PCI/PCIe information */ 330 pcie_req_id_t bus_bdf; 331 pcie_req_id_t bus_rp_bdf; /* BDF of device's Root Port */ 332 uint32_t bus_dev_ven_id; /* device/vendor ID */ 333 uint8_t bus_rev_id; /* revision ID */ 334 uint8_t bus_hdr_type; /* pci header type, see pci.h */ 335 uint16_t bus_dev_type; /* PCI-E dev type, see pcie.h */ 336 uint8_t bus_bdg_secbus; /* Bridge secondary bus num */ 337 uint16_t bus_pcie_off; /* PCIe Capability Offset */ 338 uint16_t bus_aer_off; /* PCIe Advanced Error Offset */ 339 uint16_t bus_pcix_off; /* PCIx Capability Offset */ 340 uint16_t bus_pci_hp_off; /* PCI HP (SHPC) Cap Offset */ 341 uint16_t bus_ecc_ver; /* PCIX ecc version */ 342 pci_bus_range_t bus_bus_range; /* pci bus-range property */ 343 ppb_ranges_t *bus_addr_ranges; /* pci range property */ 344 int bus_addr_entries; /* number of range prop */ 345 pci_regspec_t *bus_assigned_addr; /* "assigned-address" prop */ 346 int bus_assigned_entries; /* number of prop entries */ 347 348 /* Cache of last fault data */ 349 pf_data_t *bus_pfd; 350 pcie_domain_t *bus_dom; 351 352 int bus_mps; /* Maximum Payload Size */ 353 354 void *bus_plat_private; /* Platform specific */ 355 /* Hotplug specific fields */ 356 pcie_hp_mode_t bus_hp_sup_modes; /* HP modes supported */ 357 pcie_hp_mode_t bus_hp_curr_mode; /* HP mode used */ 358 void *bus_hp_ctrl; /* HP bus ctrl data */ 359 int bus_ari; /* ARI device */ 360 361 uint64_t bus_cfgacc_base; /* config space base address */ 362 363 /* workaround for PCI/PCI-X devs behind PCIe2PCI Bridge */ 364 pcie_req_id_t bus_pcie2pci_secbus; 365 366 /* 367 * Link speed specific fields. 368 */ 369 pcie_link_width_t bus_max_width; 370 pcie_link_width_t bus_cur_width; 371 pcie_link_speed_t bus_sup_speed; 372 pcie_link_speed_t bus_max_speed; 373 pcie_link_speed_t bus_cur_speed; 374 } pcie_bus_t; 375 376 /* 377 * Data structure to log what devices are affected in relationship to the 378 * severity after all the errors bits have been analyzed. 379 */ 380 #define PF_AFFECTED_ROOT (1 << 0) /* RP/RC is affected */ 381 #define PF_AFFECTED_SELF (1 << 1) /* Reporting Device is affected */ 382 #define PF_AFFECTED_PARENT (1 << 2) /* Parent device is affected */ 383 #define PF_AFFECTED_CHILDREN (1 << 3) /* All children below are affected */ 384 #define PF_AFFECTED_BDF (1 << 4) /* See affected_bdf */ 385 #define PF_AFFECTED_AER (1 << 5) /* See AER Registers */ 386 #define PF_AFFECTED_SAER (1 << 6) /* See SAER Registers */ 387 #define PF_AFFECTED_ADDR (1 << 7) /* Device targeted by addr */ 388 389 #define PF_MAX_AFFECTED_FLAG PF_AFFECTED_ADDR 390 391 typedef struct pf_affected_dev { 392 uint16_t pe_affected_flags; 393 pcie_req_id_t pe_affected_bdf; 394 } pf_affected_dev_t; 395 396 struct pf_data { 397 boolean_t pe_lock; 398 boolean_t pe_valid; 399 uint32_t pe_severity_flags; /* Severity of error */ 400 uint32_t pe_orig_severity_flags; /* Original severity */ 401 pf_affected_dev_t *pe_affected_dev; 402 pcie_bus_t *pe_bus_p; 403 pf_root_fault_t *pe_root_fault; /* Only valid for RC and RP */ 404 pf_root_eh_src_t *pe_root_eh_src; /* Only valid for RC and RP */ 405 pf_pci_err_regs_t *pe_pci_regs; /* PCI error reg */ 406 union { 407 pf_pcix_err_regs_t *pe_pcix_regs; /* PCI-X error reg */ 408 pf_pcie_err_regs_t *pe_pcie_regs; /* PCIe error reg */ 409 } pe_ext; 410 pf_pcix_bdg_err_regs_t *pe_pcix_bdg_regs; /* PCI-X bridge regs */ 411 pf_data_t *pe_prev; /* Next error in queue */ 412 pf_data_t *pe_next; /* Next error in queue */ 413 boolean_t pe_rber_fatal; 414 }; 415 416 /* Information used while handling errors in the fabric. */ 417 typedef struct pf_impl { 418 ddi_fm_error_t *pf_derr; 419 pf_root_fault_t *pf_fault; /* captured fault bdf/addr to scan */ 420 pf_data_t *pf_dq_head_p; /* ptr to fault data queue */ 421 pf_data_t *pf_dq_tail_p; /* ptr pt last fault data q */ 422 uint32_t pf_total; /* total non RC pf_datas */ 423 } pf_impl_t; 424 425 /* bus_fm_flags field */ 426 #define PF_FM_READY (1 << 0) /* bus_fm_lock initialized */ 427 #define PF_FM_IS_NH (1 << 1) /* known as non-hardened */ 428 429 /* 430 * PCIe fabric handle lookup address flags. Used to define what type of 431 * transaction the address is for. These same value are defined again in 432 * fabric-xlate FM module. Do not modify these variables, without modifying 433 * those. 434 */ 435 #define PF_ADDR_DMA (1 << 0) 436 #define PF_ADDR_PIO (1 << 1) 437 #define PF_ADDR_CFG (1 << 2) 438 439 /* PCIe fabric error scanning status flags */ 440 #define PF_SCAN_SUCCESS (1 << 0) 441 #define PF_SCAN_CB_FAILURE (1 << 1) /* hardened device callback failure */ 442 #define PF_SCAN_NO_ERR_IN_CHILD (1 << 2) /* no errors in bridge sec stat reg */ 443 #define PF_SCAN_IN_DQ (1 << 3) /* already present in the faultq */ 444 #define PF_SCAN_DEADLOCK (1 << 4) /* deadlock detected */ 445 #define PF_SCAN_BAD_RESPONSE (1 << 5) /* Incorrect device response */ 446 447 /* PCIe fabric error handling severity return flags */ 448 #define PF_ERR_NO_ERROR (1 << 0) /* No error seen */ 449 #define PF_ERR_CE (1 << 1) /* Correctable Error */ 450 #define PF_ERR_NO_PANIC (1 << 2) /* Error should not panic sys */ 451 #define PF_ERR_MATCHED_DEVICE (1 << 3) /* Error Handled By Device */ 452 #define PF_ERR_MATCHED_RC (1 << 4) /* Error Handled By RC */ 453 #define PF_ERR_MATCHED_PARENT (1 << 5) /* Error Handled By Parent */ 454 #define PF_ERR_PANIC (1 << 6) /* Error should panic system */ 455 #define PF_ERR_PANIC_DEADLOCK (1 << 7) /* deadlock detected */ 456 #define PF_ERR_BAD_RESPONSE (1 << 8) /* Device bad/no response */ 457 #define PF_ERR_MATCH_DOM (1 << 9) /* Error Handled By IO domain */ 458 459 #define PF_ERR_FATAL_FLAGS (PF_ERR_PANIC | PF_ERR_PANIC_DEADLOCK) 460 461 #define PF_HDL_FOUND 1 462 #define PF_HDL_NOTFOUND 2 463 464 /* 465 * PCIe Capability Device Type Pseudo Definitions. 466 * 467 * PCI_PSEUDO is used on real PCI devices. The Legacy PCI definition in the 468 * PCIe spec really refers to PCIe devices that *require* IO Space access. IO 469 * Space access is usually frowned upon now in PCIe, but there for legacy 470 * purposes. 471 */ 472 #define PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO 0x100 473 #define PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO 0x101 474 475 #define PCIE_INVALID_BDF 0xFFFF 476 #define PCIE_CHECK_VALID_BDF(x) (x != PCIE_INVALID_BDF) 477 478 typedef struct { 479 dev_info_t *dip; 480 int highest_common_mps; 481 } pcie_max_supported_t; 482 483 /* 484 * Default interrupt priority for all PCI and PCIe nexus drivers including 485 * hotplug interrupts. 486 */ 487 #define PCIE_INTR_PRI (LOCK_LEVEL - 1) 488 489 /* 490 * XXX - PCIE_IS_PCIE check is required in order not to invoke these macros 491 * for non-standard PCI or PCI Express Hotplug Controllers. 492 */ 493 #define PCIE_ENABLE_ERRORS(dip) \ 494 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 495 pcie_enable_errors(dip); \ 496 (void) pcie_enable_ce(dip); \ 497 } 498 499 #define PCIE_DISABLE_ERRORS(dip) \ 500 if (PCIE_IS_PCIE(PCIE_DIP2BUS(dip))) { \ 501 pcie_disable_errors(dip); \ 502 } 503 504 /* 505 * pcie_init_buspcie_fini_bus specific flags 506 */ 507 #define PCIE_BUS_INITIAL 0x0001 508 #define PCIE_BUS_FINAL 0x0002 509 #define PCIE_BUS_ALL (PCIE_BUS_INITIAL | PCIE_BUS_FINAL) 510 511 #ifdef DEBUG 512 #define PCIE_DBG pcie_dbg 513 /* Common Debugging shortcuts */ 514 #define PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \ 515 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 516 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 517 PCIE_GET(sz, bus_p, off)) 518 #define PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \ 519 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 520 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 521 PCIE_CAP_GET(sz, bus_p, off)) 522 #define PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \ 523 PCIE_DBG("%s:%d:(0x%x) %s(0x%x) 0x%x -> 0x%x\n", ddi_node_name(dip), \ 524 ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \ 525 PCIE_AER_GET(sz, bus_p, off)) 526 527 #else /* DEBUG */ 528 529 #define PCIE_DBG_CFG(...) (void)(0) 530 #define PCIE_DBG(...) (void)(0) 531 #define PCIE_ARI_DBG(...) (void)(0) 532 #define PCIE_DBG_CAP(...) (void)(0) 533 #define PCIE_DBG_AER(...) (void)(0) 534 535 #endif /* DEBUG */ 536 537 /* PCIe Friendly Functions */ 538 extern int pcie_init(dev_info_t *dip, caddr_t arg); 539 extern int pcie_uninit(dev_info_t *dip); 540 extern int pcie_hpintr_enable(dev_info_t *dip); 541 extern int pcie_hpintr_disable(dev_info_t *dip); 542 extern int pcie_intr(dev_info_t *dip); 543 extern int pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp, 544 cred_t *credp); 545 extern int pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp, 546 cred_t *credp); 547 extern int pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg, 548 int mode, cred_t *credp, int *rvalp); 549 extern int pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 550 int flags, char *name, caddr_t valuep, int *lengthp); 551 552 extern void pcie_init_root_port_mps(dev_info_t *dip); 553 extern int pcie_initchild(dev_info_t *dip); 554 extern void pcie_uninitchild(dev_info_t *dip); 555 extern int pcie_init_cfghdl(dev_info_t *dip); 556 extern void pcie_fini_cfghdl(dev_info_t *dip); 557 extern void pcie_clear_errors(dev_info_t *dip); 558 extern int pcie_postattach_child(dev_info_t *dip); 559 extern void pcie_enable_errors(dev_info_t *dip); 560 extern void pcie_disable_errors(dev_info_t *dip); 561 extern int pcie_enable_ce(dev_info_t *dip); 562 extern boolean_t pcie_bridge_is_link_disabled(dev_info_t *); 563 extern boolean_t pcie_is_pci_device(dev_info_t *dip); 564 565 extern pcie_bus_t *pcie_init_bus(dev_info_t *dip, pcie_req_id_t bdf, 566 uint8_t flags); 567 extern void pcie_fini_bus(dev_info_t *dip, uint8_t flags); 568 extern void pcie_fab_init_bus(dev_info_t *dip, uint8_t flags); 569 extern void pcie_fab_fini_bus(dev_info_t *dip, uint8_t flags); 570 extern void pcie_rc_init_bus(dev_info_t *dip); 571 extern void pcie_rc_fini_bus(dev_info_t *dip); 572 extern void pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd); 573 extern void pcie_rc_fini_pfd(pf_data_t *pfd); 574 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip); 575 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf); 576 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 577 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip); 578 extern int pcie_dev(dev_info_t *dip); 579 extern void pcie_get_fabric_mps(dev_info_t *rc_dip, dev_info_t *dip, 580 int *max_supported); 581 extern int pcie_root_port(dev_info_t *dip); 582 extern int pcie_initchild_mps(dev_info_t *dip); 583 extern void pcie_set_rber_fatal(dev_info_t *dip, boolean_t val); 584 extern boolean_t pcie_get_rber_fatal(dev_info_t *dip); 585 586 extern uint32_t pcie_get_aer_uce_mask(); 587 extern uint32_t pcie_get_aer_ce_mask(); 588 extern uint32_t pcie_get_aer_suce_mask(); 589 extern uint32_t pcie_get_serr_mask(); 590 extern void pcie_set_aer_uce_mask(uint32_t mask); 591 extern void pcie_set_aer_ce_mask(uint32_t mask); 592 extern void pcie_set_aer_suce_mask(uint32_t mask); 593 extern void pcie_set_serr_mask(uint32_t mask); 594 extern void pcie_init_plat(dev_info_t *dip); 595 extern void pcie_fini_plat(dev_info_t *dip); 596 extern int pcie_read_only_probe(dev_info_t *, char *, dev_info_t **); 597 extern dev_info_t *pcie_func_to_dip(dev_info_t *dip, pcie_req_id_t function); 598 extern int pcie_ari_disable(dev_info_t *dip); 599 extern int pcie_ari_enable(dev_info_t *dip); 600 601 #define PCIE_ARI_FORW_NOT_SUPPORTED 0 602 #define PCIE_ARI_FORW_SUPPORTED 1 603 604 extern int pcie_ari_supported(dev_info_t *dip); 605 606 #define PCIE_ARI_FORW_DISABLED 0 607 #define PCIE_ARI_FORW_ENABLED 1 608 609 extern int pcie_ari_is_enabled(dev_info_t *dip); 610 611 #define PCIE_NOT_ARI_DEVICE 0 612 #define PCIE_ARI_DEVICE 1 613 614 extern int pcie_ari_device(dev_info_t *dip); 615 extern int pcie_ari_get_next_function(dev_info_t *dip, int *func); 616 617 /* PCIe error handling functions */ 618 extern void pf_eh_enter(pcie_bus_t *bus_p); 619 extern void pf_eh_exit(pcie_bus_t *bus_p); 620 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr, 621 pf_data_t *root_pfd_p); 622 extern void pf_init(dev_info_t *, ddi_iblock_cookie_t, ddi_attach_cmd_t); 623 extern void pf_fini(dev_info_t *, ddi_detach_cmd_t); 624 extern int pf_hdl_lookup(dev_info_t *, uint64_t, uint32_t, uint64_t, 625 pcie_req_id_t); 626 extern int pf_tlp_decode(pcie_bus_t *, pf_pcie_adv_err_regs_t *); 627 extern void pcie_force_fullscan(); 628 629 #ifdef DEBUG 630 extern uint_t pcie_debug_flags; 631 extern void pcie_dbg(char *fmt, ...); 632 #endif /* DEBUG */ 633 634 /* PCIe IOV functions */ 635 extern dev_info_t *pcie_find_dip_by_bdf(dev_info_t *rootp, pcie_req_id_t bdf); 636 637 extern boolean_t pf_in_bus_range(pcie_bus_t *, pcie_req_id_t); 638 extern boolean_t pf_in_assigned_addr(pcie_bus_t *, uint64_t); 639 extern int pf_pci_decode(pf_data_t *, uint16_t *); 640 extern pcie_bus_t *pf_find_busp_by_bdf(pf_impl_t *, pcie_req_id_t); 641 extern pcie_bus_t *pf_find_busp_by_addr(pf_impl_t *, uint64_t); 642 extern pcie_bus_t *pf_find_busp_by_aer(pf_impl_t *, pf_data_t *); 643 extern pcie_bus_t *pf_find_busp_by_saer(pf_impl_t *, pf_data_t *); 644 645 extern int pciev_eh(pf_data_t *, pf_impl_t *); 646 extern pcie_bus_t *pciev_get_affected_dev(pf_impl_t *, pf_data_t *, 647 uint16_t, uint16_t); 648 extern void pciev_eh_exit(pf_data_t *, uint_t); 649 extern boolean_t pcie_in_domain(pcie_bus_t *, uint_t); 650 651 #define PCIE_ZALLOC(data) kmem_zalloc(sizeof (data), KM_SLEEP) 652 653 654 #ifdef __cplusplus 655 } 656 #endif 657 658 #endif /* _SYS_PCIE_IMPL_H */ 659