xref: /illumos-gate/usr/src/uts/common/sys/pci_impl.h (revision b5cf5bc277244cdacc06d213322ec98e76ef8d89)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  * Copyright 2018 Joyent, Inc.
25  */
26 
27 #ifndef _SYS_PCI_IMPL_H
28 #define	_SYS_PCI_IMPL_H
29 
30 #include <sys/dditypes.h>
31 #include <sys/memlist.h>
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 #if defined(__i386) || defined(__amd64)
38 
39 /*
40  * There are two ways to access the PCI configuration space on X86
41  *	Access method 2 is the older method
42  *	Access method 1 is the newer method and is preferred because
43  *	  of the problems in trying to lock the configuration space
44  *	  for MP machines using method 2.  See PCI Local BUS Specification
45  *	  Revision 2.0 section 3.6.4.1 for more details.
46  *
47  * In addition, on IBM Sandalfoot and a few related machines there's
48  * still another mechanism.  See PReP 1.1 section 6.1.7.
49  */
50 
51 #define	PCI_MECHANISM_UNKNOWN		-1
52 #define	PCI_MECHANISM_NONE		0
53 #if defined(__i386) || defined(__amd64)
54 #define	PCI_MECHANISM_1			1
55 #define	PCI_MECHANISM_2			2
56 #else
57 #error "Unknown processor type"
58 #endif
59 
60 
61 #ifndef FALSE
62 #define	FALSE   0
63 #endif
64 
65 #ifndef TRUE
66 #define	TRUE    1
67 #endif
68 
69 #define	PCI_FUNC_MASK			0x07
70 
71 /* these macros apply to Configuration Mechanism #1 */
72 #define	PCI_CONFADD		0xcf8
73 #define	PCI_PMC			0xcfb
74 #define	PCI_CONFDATA		0xcfc
75 #define	PCI_CONE		0x80000000
76 #define	PCI_CADDR1(bus, device, function, reg) \
77 		(PCI_CONE | (((bus) & 0xff) << 16) | (((device & 0x1f)) << 11) \
78 			    | (((function) & 0x7) << 8) | ((reg) & 0xfc))
79 
80 /* these macros apply to Configuration Mechanism #2 */
81 #define	PCI_CSE_PORT		0xcf8
82 #define	PCI_FORW_PORT		0xcfa
83 #define	PCI_CADDR2(device, indx) \
84 		(0xc000 | (((device) & 0xf) <<  8) | (indx))
85 
86 typedef struct	pci_acc_cfblk {
87 	uchar_t	c_busnum;		/* bus number */
88 	uchar_t c_devnum;		/* device number */
89 	uchar_t c_funcnum;		/* function number */
90 	uchar_t c_fill;			/* reserve field */
91 } pci_acc_cfblk_t;
92 
93 struct pci_bus_resource {
94 	struct memlist *io_avail;	/* available free io res */
95 	struct memlist *io_used;	/* used io res */
96 	struct memlist *mem_avail;	/* available free mem res */
97 	struct memlist *mem_used;	/* used mem res */
98 	struct memlist *pmem_avail; /* available free prefetchable mem res */
99 	struct memlist *pmem_used; /* used prefetchable mem res */
100 	struct memlist *bus_avail;	/* available free bus res */
101 			/* bus_space_used not needed; can read from regs */
102 	dev_info_t *dip;	/* devinfo node */
103 	void *privdata;		/* private data for configuration */
104 	uchar_t par_bus;	/* parent bus number */
105 	uchar_t sub_bus;	/* highest bus number beyond this bridge */
106 	uchar_t root_addr;	/* legacy peer bus address assignment */
107 	uchar_t num_cbb;	/* # of CardBus Bridges on the bus */
108 	boolean_t io_reprogram;	/* need io reprog on this bus */
109 	boolean_t mem_reprogram;	/* need mem reprog on this bus */
110 	boolean_t subtractive;	/* subtractive PPB */
111 	uint64_t mem_size;	/* existing children required MEM space size */
112 	uint_t io_size;		/* existing children required I/O space size */
113 };
114 
115 extern struct pci_bus_resource *pci_bus_res;
116 
117 /*
118  * For now, x86-only to avoid conflicts with <sys/memlist_impl.h>
119  */
120 #define	memlist_find		memlist_find_pci
121 #define	memlist_insert		memlist_insert_pci
122 
123 extern struct memlist *memlist_alloc(void);
124 extern void memlist_free(struct memlist *);
125 extern void memlist_free_all(struct memlist **);
126 extern void memlist_insert(struct memlist **, uint64_t, uint64_t);
127 extern int memlist_remove(struct memlist **, uint64_t, uint64_t);
128 extern uint64_t memlist_find(struct memlist **, uint64_t, int);
129 extern uint64_t memlist_find_with_startaddr(struct memlist **, uint64_t,
130     uint64_t, int);
131 extern void memlist_dump(struct memlist *);
132 extern void memlist_subsume(struct memlist **, struct memlist **);
133 extern void memlist_merge(struct memlist **, struct memlist **);
134 extern struct memlist *memlist_dup(struct memlist *);
135 extern int memlist_count(struct memlist *);
136 
137 #endif /* __i386 || __amd64 */
138 
139 /* Definitions for minor numbers */
140 #define	PCI_MINOR_NUM(x, y)		(((uint_t)(x) << 8) | ((y) & 0xFF))
141 #define	PCI_MINOR_NUM_TO_PCI_DEVNUM(x)	((x) & 0xFF)
142 #define	PCI_MINOR_NUM_TO_INSTANCE(x)	((x) >> 8)
143 #define	PCI_DEVCTL_MINOR		0xFF
144 
145 /*
146  * Minor numbers for dedicated pcitool nodes.
147  * Note that FF and FE minor numbers are used for other minor nodes.
148  */
149 #define	PCI_TOOL_REG_MINOR_NUM		0xFD
150 #define	PCI_TOOL_INTR_MINOR_NUM		0xFC
151 
152 /* pci devctl soft state flag */
153 #define	PCI_SOFT_STATE_CLOSED		0x0
154 #define	PCI_SOFT_STATE_OPEN		0x1
155 #define	PCI_SOFT_STATE_OPEN_EXCL	0x2
156 
157 /*
158  * PCI capability related definitions.
159  */
160 
161 /*
162  * Minimum number of dwords to be saved.
163  */
164 #define	PCI_MSI_MIN_WORDS	3
165 #define	PCI_PCIX_MIN_WORDS	2
166 #define	PCI_PCIE_MIN_WORDS	5
167 
168 /*
169  * Total number of dwords to be saved.
170  */
171 #define	PCI_PMCAP_NDWORDS	2
172 #define	PCI_AGP_NDWORDS		3
173 #define	PCI_SLOTID_NDWORDS	1
174 #define	PCI_MSIX_NDWORDS	3
175 #define	PCI_CAP_SZUNKNOWN	0
176 
177 #define	PCI_HTCAP_SLPRI_NDWORDS		7
178 #define	PCI_HTCAP_HOSTSEC_NDWORDS	6
179 #define	PCI_HTCAP_INTCONF_NDWORDS	2
180 #define	PCI_HTCAP_REVID_NDWORDS		1
181 #define	PCI_HTCAP_UNITID_CLUMP_NDWORDS	3
182 #define	PCI_HTCAP_ECFG_NDWORDS		3
183 #define	PCI_HTCAP_ADDRMAP_NDWORDS	PCI_CAP_SZUNKNOWN	/* variable */
184 #define	PCI_HTCAP_MSIMAP_NDWORDS	3
185 #define	PCI_HTCAP_DIRROUTE_NDWORDS	3
186 #define	PCI_HTCAP_VCSET_NDWORDS		3
187 #define	PCI_HTCAP_RETRYMODE_NDWORDS	3
188 #define	PCI_HTCAP_GEN3_NDWORDS		10
189 #define	PCI_HTCAP_FUNCEXT_NDWORDS	PCI_CAP_SZUNKNOWN	/* variable */
190 #define	PCI_HTCAP_PM_NDWORDS		2
191 
192 
193 #define	CAP_ID(confhdl, cap_ptr, xspace)		\
194 	((xspace) ? 0 : pci_config_get8((confhdl), (cap_ptr) + PCI_CAP_ID))
195 
196 #define	NEXT_CAP(confhdl, cap_ptr, xspace)	\
197 	((xspace) ? 0 :				\
198 	pci_config_get8((confhdl), (cap_ptr) + PCI_CAP_NEXT_PTR))
199 
200 extern int pci_resource_setup(dev_info_t *);
201 extern void pci_resource_destroy(dev_info_t *);
202 
203 #ifdef __cplusplus
204 }
205 #endif
206 
207 #endif /* _SYS_PCI_IMPL_H */
208