xref: /illumos-gate/usr/src/uts/common/sys/pci.h (revision 269473047d747f7815af570197e4ef7322d3632c)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
500d0963fSdilpreet  * Common Development and Distribution License (the "License").
600d0963fSdilpreet  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22fb66942fSCasper H.S. Dik  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
237c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate 
267c478bd9Sstevel@tonic-gate #ifndef	_SYS_PCI_H
277c478bd9Sstevel@tonic-gate #define	_SYS_PCI_H
287c478bd9Sstevel@tonic-gate 
297c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
307c478bd9Sstevel@tonic-gate extern "C" {
317c478bd9Sstevel@tonic-gate #endif
327c478bd9Sstevel@tonic-gate 
337c478bd9Sstevel@tonic-gate /*
347c478bd9Sstevel@tonic-gate  * PCI Configuration Header offsets
357c478bd9Sstevel@tonic-gate  */
367c478bd9Sstevel@tonic-gate #define	PCI_CONF_VENID		0x0	/* vendor id, 2 bytes */
377c478bd9Sstevel@tonic-gate #define	PCI_CONF_DEVID		0x2	/* device id, 2 bytes */
387c478bd9Sstevel@tonic-gate #define	PCI_CONF_COMM		0x4	/* command register, 2 bytes */
397c478bd9Sstevel@tonic-gate #define	PCI_CONF_STAT		0x6	/* status register, 2 bytes */
407c478bd9Sstevel@tonic-gate #define	PCI_CONF_REVID		0x8	/* revision id, 1 byte */
417c478bd9Sstevel@tonic-gate #define	PCI_CONF_PROGCLASS	0x9	/* programming class code, 1 byte */
427c478bd9Sstevel@tonic-gate #define	PCI_CONF_SUBCLASS	0xA	/* sub-class code, 1 byte */
437c478bd9Sstevel@tonic-gate #define	PCI_CONF_BASCLASS	0xB	/* basic class code, 1 byte */
447c478bd9Sstevel@tonic-gate #define	PCI_CONF_CACHE_LINESZ	0xC	/* cache line size, 1 byte */
457c478bd9Sstevel@tonic-gate #define	PCI_CONF_LATENCY_TIMER	0xD	/* latency timer, 1 byte */
467c478bd9Sstevel@tonic-gate #define	PCI_CONF_HEADER		0xE	/* header type, 1 byte */
477c478bd9Sstevel@tonic-gate #define	PCI_CONF_BIST		0xF	/* builtin self test, 1 byte */
487c478bd9Sstevel@tonic-gate 
497c478bd9Sstevel@tonic-gate /*
507c478bd9Sstevel@tonic-gate  * Header type 0 offsets
517c478bd9Sstevel@tonic-gate  */
527c478bd9Sstevel@tonic-gate #define	PCI_CONF_BASE0		0x10	/* base register 0, 4 bytes */
537c478bd9Sstevel@tonic-gate #define	PCI_CONF_BASE1		0x14	/* base register 1, 4 bytes */
547c478bd9Sstevel@tonic-gate #define	PCI_CONF_BASE2		0x18	/* base register 2, 4 bytes */
557c478bd9Sstevel@tonic-gate #define	PCI_CONF_BASE3		0x1c	/* base register 3, 4 bytes */
567c478bd9Sstevel@tonic-gate #define	PCI_CONF_BASE4		0x20	/* base register 4, 4 bytes */
577c478bd9Sstevel@tonic-gate #define	PCI_CONF_BASE5		0x24	/* base register 5, 4 bytes */
587c478bd9Sstevel@tonic-gate #define	PCI_CONF_CIS		0x28	/* Cardbus CIS Pointer */
597c478bd9Sstevel@tonic-gate #define	PCI_CONF_SUBVENID	0x2c	/* Subsystem Vendor ID */
607c478bd9Sstevel@tonic-gate #define	PCI_CONF_SUBSYSID	0x2e	/* Subsystem ID */
617c478bd9Sstevel@tonic-gate #define	PCI_CONF_ROM		0x30	/* ROM base register, 4 bytes */
627c478bd9Sstevel@tonic-gate #define	PCI_CONF_CAP_PTR	0x34	/* capabilities pointer, 1 byte */
637c478bd9Sstevel@tonic-gate #define	PCI_CONF_ILINE		0x3c	/* interrupt line, 1 byte */
647c478bd9Sstevel@tonic-gate #define	PCI_CONF_IPIN		0x3d	/* interrupt pin, 1 byte */
657c478bd9Sstevel@tonic-gate #define	PCI_CONF_MIN_G		0x3e	/* minimum grant, 1 byte */
667c478bd9Sstevel@tonic-gate #define	PCI_CONF_MAX_L		0x3f	/* maximum grant, 1 byte */
677c478bd9Sstevel@tonic-gate 
687c478bd9Sstevel@tonic-gate /*
697c478bd9Sstevel@tonic-gate  * PCI to PCI bridge configuration space header format
707c478bd9Sstevel@tonic-gate  */
717c478bd9Sstevel@tonic-gate #define	PCI_BCNF_PRIBUS		0x18	/* primary bus number */
727c478bd9Sstevel@tonic-gate #define	PCI_BCNF_SECBUS		0x19	/* secondary bus number */
737c478bd9Sstevel@tonic-gate #define	PCI_BCNF_SUBBUS		0x1a	/* subordinate bus number */
747c478bd9Sstevel@tonic-gate #define	PCI_BCNF_LATENCY_TIMER	0x1b
757c478bd9Sstevel@tonic-gate #define	PCI_BCNF_IO_BASE_LOW	0x1c
767c478bd9Sstevel@tonic-gate #define	PCI_BCNF_IO_LIMIT_LOW	0x1d
777c478bd9Sstevel@tonic-gate #define	PCI_BCNF_SEC_STATUS	0x1e
787c478bd9Sstevel@tonic-gate #define	PCI_BCNF_MEM_BASE	0x20
797c478bd9Sstevel@tonic-gate #define	PCI_BCNF_MEM_LIMIT	0x22
807c478bd9Sstevel@tonic-gate #define	PCI_BCNF_PF_BASE_LOW	0x24
817c478bd9Sstevel@tonic-gate #define	PCI_BCNF_PF_LIMIT_LOW	0x26
827c478bd9Sstevel@tonic-gate #define	PCI_BCNF_PF_BASE_HIGH	0x28
837c478bd9Sstevel@tonic-gate #define	PCI_BCNF_PF_LIMIT_HIGH	0x2c
847c478bd9Sstevel@tonic-gate #define	PCI_BCNF_IO_BASE_HI	0x30
857c478bd9Sstevel@tonic-gate #define	PCI_BCNF_IO_LIMIT_HI	0x32
867c478bd9Sstevel@tonic-gate #define	PCI_BCNF_CAP_PTR	0x34
877c478bd9Sstevel@tonic-gate #define	PCI_BCNF_ROM		0x38
887c478bd9Sstevel@tonic-gate #define	PCI_BCNF_ILINE		0x3c
897c478bd9Sstevel@tonic-gate #define	PCI_BCNF_IPIN		0x3d
907c478bd9Sstevel@tonic-gate #define	PCI_BCNF_BCNTRL		0x3e
917c478bd9Sstevel@tonic-gate 
927c478bd9Sstevel@tonic-gate #define	PCI_BCNF_BASE_NUM	0x2
937c478bd9Sstevel@tonic-gate 
947c478bd9Sstevel@tonic-gate /*
957c478bd9Sstevel@tonic-gate  * PCI to PCI bridge control register (0x3e) format
967c478bd9Sstevel@tonic-gate  */
977c478bd9Sstevel@tonic-gate #define	PCI_BCNF_BCNTRL_PARITY_ENABLE	0x1
987c478bd9Sstevel@tonic-gate #define	PCI_BCNF_BCNTRL_SERR_ENABLE	0x2
99eae2e508Skrishnae #define	PCI_BCNF_BCNTRL_ISA_ENABLE	0x4
1004e93fb0fSrugrat #define	PCI_BCNF_BCNTRL_VGA_ENABLE	0x8
1017c478bd9Sstevel@tonic-gate #define	PCI_BCNF_BCNTRL_MAST_AB_MODE	0x20
1027c478bd9Sstevel@tonic-gate #define	PCI_BCNF_BCNTRL_DTO_STAT	0x400
1037c478bd9Sstevel@tonic-gate 
104a9fb0ae8Srw #define	PCI_BCNF_BCNTRL_RESET		0x0040
105a9fb0ae8Srw #define	PCI_BCNF_BCNTRL_B2B_ENAB	0x0080
106a9fb0ae8Srw 
1077c478bd9Sstevel@tonic-gate #define	PCI_BCNF_IO_MASK	0xf0
1087c478bd9Sstevel@tonic-gate #define	PCI_BCNF_MEM_MASK	0xfff0
1097c478bd9Sstevel@tonic-gate 
1107c478bd9Sstevel@tonic-gate /*
1117c478bd9Sstevel@tonic-gate  * Header type 2 (Cardbus) offsets
1127c478bd9Sstevel@tonic-gate  */
1137c478bd9Sstevel@tonic-gate #define	PCI_CBUS_SOCK_REG	0x10	/* Cardbus socket regs, 4 bytes */
114fb66942fSCasper H.S. Dik #define	PCI_CBUS_CAP_PTR	0x14	/* Capability ptr, 1 byte */
115fb66942fSCasper H.S. Dik #define	PCI_CBUS_RESERVED1	0x15	/* Reserved, 1 byte */
1167c478bd9Sstevel@tonic-gate #define	PCI_CBUS_SEC_STATUS	0x16	/* Secondary status, 2 bytes */
1177c478bd9Sstevel@tonic-gate #define	PCI_CBUS_PCI_BUS_NO	0x18	/* PCI bus number, 1 byte */
1187c478bd9Sstevel@tonic-gate #define	PCI_CBUS_CBUS_NO	0x19	/* Cardbus bus number, 1 byte */
1197c478bd9Sstevel@tonic-gate #define	PCI_CBUS_SUB_BUS_NO	0x1a	/* Subordinate bus number, 1 byte */
1207c478bd9Sstevel@tonic-gate #define	PCI_CBUS_LATENCY_TIMER	0x1b	/* Cardbus latency timer, 1 byte */
1217c478bd9Sstevel@tonic-gate #define	PCI_CBUS_MEM_BASE0	0x1c	/* Memory base reg 0, 4 bytes */
1227c478bd9Sstevel@tonic-gate #define	PCI_CBUS_MEM_LIMIT0	0x20	/* Memory limit reg 0, 4 bytes */
1237c478bd9Sstevel@tonic-gate #define	PCI_CBUS_MEM_BASE1	0x24	/* Memory base reg 1, 4 bytes */
1247c478bd9Sstevel@tonic-gate #define	PCI_CBUS_MEM_LIMIT1	0x28	/* Memory limit reg 1, 4 bytes */
1257c478bd9Sstevel@tonic-gate #define	PCI_CBUS_IO_BASE0	0x2c	/* IO base reg 0, 4 bytes */
1267c478bd9Sstevel@tonic-gate #define	PCI_CBUS_IO_LIMIT0	0x30	/* IO limit reg 0, 4 bytes */
1277c478bd9Sstevel@tonic-gate #define	PCI_CBUS_IO_BASE1	0x34	/* IO base reg 1, 4 bytes */
1287c478bd9Sstevel@tonic-gate #define	PCI_CBUS_IO_LIMIT1	0x38	/* IO limit reg 1, 4 bytes */
1297c478bd9Sstevel@tonic-gate #define	PCI_CBUS_ILINE		0x3c	/* interrupt line, 1 byte */
1307c478bd9Sstevel@tonic-gate #define	PCI_CBUS_IPIN		0x3d	/* interrupt pin, 1 byte */
1317c478bd9Sstevel@tonic-gate #define	PCI_CBUS_BRIDGE_CTRL	0x3e	/* Bridge control, 2 bytes */
1327c478bd9Sstevel@tonic-gate #define	PCI_CBUS_SUBVENID	0x40	/* Subsystem Vendor ID, 2 bytes */
1337c478bd9Sstevel@tonic-gate #define	PCI_CBUS_SUBSYSID	0x42	/* Subsystem ID, 2 bytes */
1347c478bd9Sstevel@tonic-gate #define	PCI_CBUS_LEG_MODE_ADDR	0x44	/* PCCard 16bit IF legacy mode addr */
1357c478bd9Sstevel@tonic-gate 
1367c478bd9Sstevel@tonic-gate #define	PCI_CBUS_BASE_NUM	0x1	/* number of base registers */
1377c478bd9Sstevel@tonic-gate 
1387c478bd9Sstevel@tonic-gate /*
1397c478bd9Sstevel@tonic-gate  * PCI command register bits
1407c478bd9Sstevel@tonic-gate  */
1417c478bd9Sstevel@tonic-gate #define	PCI_COMM_IO		0x1	/* I/O access enable */
1427c478bd9Sstevel@tonic-gate #define	PCI_COMM_MAE		0x2	/* memory access enable */
1437c478bd9Sstevel@tonic-gate #define	PCI_COMM_ME		0x4	/* master enable */
1447c478bd9Sstevel@tonic-gate #define	PCI_COMM_SPEC_CYC	0x8
1457c478bd9Sstevel@tonic-gate #define	PCI_COMM_MEMWR_INVAL	0x10
1467c478bd9Sstevel@tonic-gate #define	PCI_COMM_PALETTE_SNOOP	0x20
1477c478bd9Sstevel@tonic-gate #define	PCI_COMM_PARITY_DETECT	0x40
1487c478bd9Sstevel@tonic-gate #define	PCI_COMM_WAIT_CYC_ENAB	0x80
1497c478bd9Sstevel@tonic-gate #define	PCI_COMM_SERR_ENABLE	0x100
1507c478bd9Sstevel@tonic-gate #define	PCI_COMM_BACK2BACK_ENAB	0x200
1517c478bd9Sstevel@tonic-gate #define	PCI_COMM_INTX_DISABLE	0x400	/* INTx emulation disable */
1527c478bd9Sstevel@tonic-gate 
1537c478bd9Sstevel@tonic-gate /*
1547c478bd9Sstevel@tonic-gate  * PCI Interrupt pin value
1557c478bd9Sstevel@tonic-gate  */
1567c478bd9Sstevel@tonic-gate #define	PCI_INTA	1
1577c478bd9Sstevel@tonic-gate #define	PCI_INTB	2
1587c478bd9Sstevel@tonic-gate #define	PCI_INTC	3
1597c478bd9Sstevel@tonic-gate #define	PCI_INTD	4
1607c478bd9Sstevel@tonic-gate 
1617c478bd9Sstevel@tonic-gate /*
1627c478bd9Sstevel@tonic-gate  * PCI status register bits
1637c478bd9Sstevel@tonic-gate  */
1647c478bd9Sstevel@tonic-gate #define	PCI_STAT_INTR		0x8	/* Interrupt state */
1657c478bd9Sstevel@tonic-gate #define	PCI_STAT_CAP		0x10	/* Implements Capabilities */
1667c478bd9Sstevel@tonic-gate #define	PCI_STAT_66MHZ		0x20	/* 66 MHz capable */
1677c478bd9Sstevel@tonic-gate #define	PCI_STAT_UDF		0x40	/* UDF supported */
1687c478bd9Sstevel@tonic-gate #define	PCI_STAT_FBBC		0x80	/* Fast Back-to-Back Capable */
1697c478bd9Sstevel@tonic-gate #define	PCI_STAT_S_PERROR	0x100	/* Data Parity Reported */
1707c478bd9Sstevel@tonic-gate #define	PCI_STAT_DEVSELT	0x600	/* Device select timing */
1717c478bd9Sstevel@tonic-gate #define	PCI_STAT_S_TARG_AB	0x800	/* Signaled Target Abort */
1727c478bd9Sstevel@tonic-gate #define	PCI_STAT_R_TARG_AB	0x1000	/* Received Target Abort */
1737c478bd9Sstevel@tonic-gate #define	PCI_STAT_R_MAST_AB	0x2000	/* Received Master Abort */
1747c478bd9Sstevel@tonic-gate #define	PCI_STAT_S_SYSERR	0x4000	/* Signaled System Error */
1757c478bd9Sstevel@tonic-gate #define	PCI_STAT_PERROR		0x8000	/* Detected Parity Error */
1767c478bd9Sstevel@tonic-gate 
1777c478bd9Sstevel@tonic-gate /*
1787c478bd9Sstevel@tonic-gate  * DEVSEL timing values
1797c478bd9Sstevel@tonic-gate  */
1807c478bd9Sstevel@tonic-gate #define	PCI_STAT_DEVSELT_FAST	0x0000
1817c478bd9Sstevel@tonic-gate #define	PCI_STAT_DEVSELT_MEDIUM	0x0200
1827c478bd9Sstevel@tonic-gate #define	PCI_STAT_DEVSELT_SLOW	0x0400
1837c478bd9Sstevel@tonic-gate 
1847c478bd9Sstevel@tonic-gate /*
1857c478bd9Sstevel@tonic-gate  * BIST values
1867c478bd9Sstevel@tonic-gate  */
1877c478bd9Sstevel@tonic-gate #define	PCI_BIST_SUPPORTED	0x80
1887c478bd9Sstevel@tonic-gate #define	PCI_BIST_GO		0x40
1897c478bd9Sstevel@tonic-gate #define	PCI_BIST_RESULT_M	0x0f
1907c478bd9Sstevel@tonic-gate #define	PCI_BIST_RESULT_OK	0x00
1917c478bd9Sstevel@tonic-gate 
1927c478bd9Sstevel@tonic-gate /*
1937c478bd9Sstevel@tonic-gate  * PCI class codes
1947c478bd9Sstevel@tonic-gate  */
1957c478bd9Sstevel@tonic-gate #define	PCI_CLASS_NONE		0x0	/* class code for pre-2.0 devices */
1967c478bd9Sstevel@tonic-gate #define	PCI_CLASS_MASS		0x1	/* Mass storage Controller class */
1977c478bd9Sstevel@tonic-gate #define	PCI_CLASS_NET		0x2	/* Network Controller class */
1987c478bd9Sstevel@tonic-gate #define	PCI_CLASS_DISPLAY	0x3	/* Display Controller class */
1997c478bd9Sstevel@tonic-gate #define	PCI_CLASS_MM		0x4	/* Multimedia Controller class */
2007c478bd9Sstevel@tonic-gate #define	PCI_CLASS_MEM		0x5	/* Memory Controller class */
2017c478bd9Sstevel@tonic-gate #define	PCI_CLASS_BRIDGE	0x6	/* Bridge Controller class */
2027c478bd9Sstevel@tonic-gate #define	PCI_CLASS_COMM		0x7	/* Communications Controller class */
2037c478bd9Sstevel@tonic-gate #define	PCI_CLASS_PERIPH	0x8	/* Peripheral Controller class */
2047c478bd9Sstevel@tonic-gate #define	PCI_CLASS_INPUT		0x9	/* Input Device class */
2057c478bd9Sstevel@tonic-gate #define	PCI_CLASS_DOCK		0xa	/* Docking Station class */
2067c478bd9Sstevel@tonic-gate #define	PCI_CLASS_PROCESSOR	0xb	/* Processor class */
2077c478bd9Sstevel@tonic-gate #define	PCI_CLASS_SERIALBUS	0xc	/* Serial Bus class */
2087c478bd9Sstevel@tonic-gate #define	PCI_CLASS_WIRELESS	0xd	/* Wireless Controller class */
2097c478bd9Sstevel@tonic-gate #define	PCI_CLASS_INTIO		0xe	/* Intelligent IO Controller class */
2107c478bd9Sstevel@tonic-gate #define	PCI_CLASS_SATELLITE	0xf	/* Satellite Communication class */
2117c478bd9Sstevel@tonic-gate #define	PCI_CLASS_CRYPT		0x10	/* Encrytion/Decryption class */
2127c478bd9Sstevel@tonic-gate #define	PCI_CLASS_SIGNAL	0x11	/* Signal Processing class */
2137c478bd9Sstevel@tonic-gate 
2147c478bd9Sstevel@tonic-gate /*
2157c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x0 (no new devices should use this code).
2167c478bd9Sstevel@tonic-gate  */
2177c478bd9Sstevel@tonic-gate #define	PCI_NONE_NOTVGA		0x0	/* All devices except VGA compatible */
2187c478bd9Sstevel@tonic-gate #define	PCI_NONE_VGA		0x1	/* VGA compatible */
2197c478bd9Sstevel@tonic-gate 
2207c478bd9Sstevel@tonic-gate /*
2217c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x1 (mass storage controllers)
2227c478bd9Sstevel@tonic-gate  */
2237c478bd9Sstevel@tonic-gate #define	PCI_MASS_SCSI		0x0	/* SCSI bus Controller */
2247c478bd9Sstevel@tonic-gate #define	PCI_MASS_IDE		0x1	/* IDE Controller */
225337fc9e2Sanish #define	PCI_MASS_FD		0x2	/* Floppy disk Controller */
2267c478bd9Sstevel@tonic-gate #define	PCI_MASS_IPI		0x3	/* IPI bus Controller */
2277c478bd9Sstevel@tonic-gate #define	PCI_MASS_RAID		0x4	/* RAID Controller */
2287c478bd9Sstevel@tonic-gate #define	PCI_MASS_ATA		0x5	/* ATA Controller */
2297c478bd9Sstevel@tonic-gate #define	PCI_MASS_SATA		0x6	/* Serial ATA */
230337fc9e2Sanish #define	PCI_MASS_SAS		0x7	/* Serial Attached SCSI (SAS) Cntrlr */
2317c478bd9Sstevel@tonic-gate #define	PCI_MASS_OTHER		0x80	/* Other Mass Storage Controller */
2327c478bd9Sstevel@tonic-gate 
2337c478bd9Sstevel@tonic-gate /*
2347c478bd9Sstevel@tonic-gate  * programming interface for IDE (subclass 1)
2357c478bd9Sstevel@tonic-gate  */
2367c478bd9Sstevel@tonic-gate #define	PCI_IDE_IF_NATIVE_PRI	0x1	/* primary channel is native */
2377c478bd9Sstevel@tonic-gate #define	PCI_IDE_IF_PROG_PRI	0x2	/* primary can operate in either mode */
2387c478bd9Sstevel@tonic-gate #define	PCI_IDE_IF_NATIVE_SEC	0x4	/* secondary channel is native */
2397c478bd9Sstevel@tonic-gate #define	PCI_IDE_IF_PROG_SEC	0x8	/* sec. can operate in either mode */
2407c478bd9Sstevel@tonic-gate #define	PCI_IDE_IF_MASK		0xf	/* programming interface mask */
2417c478bd9Sstevel@tonic-gate 
2427c478bd9Sstevel@tonic-gate 
2437c478bd9Sstevel@tonic-gate /*
2447c478bd9Sstevel@tonic-gate  * programming interface for ATA (subclass 5)
2457c478bd9Sstevel@tonic-gate  */
2467c478bd9Sstevel@tonic-gate #define	PCI_ATA_IF_SINGLE_DMA	0x20	/* ATA controller with single DMA */
2477c478bd9Sstevel@tonic-gate #define	PCI_ATA_IF_CHAINED_DMA	0x30	/* ATA controller with chained DMA */
2487c478bd9Sstevel@tonic-gate 
249337fc9e2Sanish /*
250337fc9e2Sanish  * programming interface for ATA (subclass 6) for SATA
251337fc9e2Sanish  */
252337fc9e2Sanish #define	PCI_SATA_VS_INTERFACE	0x0	/* SATA Ctlr Vendor Specific Intfc */
253337fc9e2Sanish #define	PCI_SATA_AHCI_INTERFACE	0x1	/* SATA Ctlr AHCI 1.0 Interface */
254337fc9e2Sanish #define	PCI_SATA_SSB_INTERFACE	0x2	/* Serial Storage Bus Interface */
255337fc9e2Sanish 
256337fc9e2Sanish /*
257337fc9e2Sanish  * programming interface for ATA (subclass 7) for SAS
258337fc9e2Sanish  */
259337fc9e2Sanish #define	PCI_SAS_CONTROLLER	0x0	/* SAS Controller */
260337fc9e2Sanish #define	PCI_SAS_BUS_INTERFACE	0x1	/* Serial Storage Bus Interface */
261337fc9e2Sanish 
2627c478bd9Sstevel@tonic-gate /*
2637c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x2 (Network controllers)
2647c478bd9Sstevel@tonic-gate  */
2657c478bd9Sstevel@tonic-gate #define	PCI_NET_ENET		0x0	/* Ethernet Controller */
2667c478bd9Sstevel@tonic-gate #define	PCI_NET_TOKEN		0x1	/* Token Ring Controller */
2677c478bd9Sstevel@tonic-gate #define	PCI_NET_FDDI		0x2	/* FDDI Controller */
2687c478bd9Sstevel@tonic-gate #define	PCI_NET_ATM		0x3	/* ATM Controller */
2697c478bd9Sstevel@tonic-gate #define	PCI_NET_ISDN		0x4	/* ISDN Controller */
2707c478bd9Sstevel@tonic-gate #define	PCI_NET_WFIP		0x5	/* WorldFip Controller */
2717c478bd9Sstevel@tonic-gate #define	PCI_NET_PICMG		0x6	/* PICMG 2.14 Multi Computing */
2727c478bd9Sstevel@tonic-gate #define	PCI_NET_OTHER		0x80	/* Other Network Controller */
2737c478bd9Sstevel@tonic-gate 
2747c478bd9Sstevel@tonic-gate /*
2757c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 03 (display controllers)
2767c478bd9Sstevel@tonic-gate  */
2777c478bd9Sstevel@tonic-gate #define	PCI_DISPLAY_VGA		0x0	/* VGA device */
2787c478bd9Sstevel@tonic-gate #define	PCI_DISPLAY_XGA		0x1	/* XGA device */
2797c478bd9Sstevel@tonic-gate #define	PCI_DISPLAY_3D		0x2	/* 3D controller */
2807c478bd9Sstevel@tonic-gate #define	PCI_DISPLAY_OTHER	0x80	/* Other Display Device */
2817c478bd9Sstevel@tonic-gate 
2827c478bd9Sstevel@tonic-gate /*
2837c478bd9Sstevel@tonic-gate  * programming interface for display for display class (subclass 0) VGA ctrlrs
2847c478bd9Sstevel@tonic-gate  */
2857c478bd9Sstevel@tonic-gate #define	PCI_DISPLAY_IF_VGA	0x0	/* VGA compatible */
2867c478bd9Sstevel@tonic-gate #define	PCI_DISPLAY_IF_8514	0x1	/* 8514 compatible */
2877c478bd9Sstevel@tonic-gate 
2887c478bd9Sstevel@tonic-gate /*
2897c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x4 (multi-media devices)
2907c478bd9Sstevel@tonic-gate  */
2917c478bd9Sstevel@tonic-gate #define	PCI_MM_VIDEO		0x0	/* Video device */
2927c478bd9Sstevel@tonic-gate #define	PCI_MM_AUDIO		0x1	/* Audio device */
2937c478bd9Sstevel@tonic-gate #define	PCI_MM_TELEPHONY	0x2	/* Computer Telephony device */
294337fc9e2Sanish #define	PCI_MM_MIXED_MODE	0x3	/* Mixed Mode device */
2957c478bd9Sstevel@tonic-gate #define	PCI_MM_OTHER		0x80	/* Other Multimedia Device */
2967c478bd9Sstevel@tonic-gate 
2977c478bd9Sstevel@tonic-gate /*
2987c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x5 (memory controllers)
2997c478bd9Sstevel@tonic-gate  */
3007c478bd9Sstevel@tonic-gate #define	PCI_MEM_RAM		0x0	/* RAM device */
3017c478bd9Sstevel@tonic-gate #define	PCI_MEM_FLASH		0x1	/* FLASH device */
3027c478bd9Sstevel@tonic-gate #define	PCI_MEM_OTHER		0x80	/* Other Memory Controller */
3037c478bd9Sstevel@tonic-gate 
3047c478bd9Sstevel@tonic-gate /*
3057c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x6 (Bridge devices)
3067c478bd9Sstevel@tonic-gate  */
3077c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_HOST		0x0	/* Host/PCI Bridge */
3087c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_ISA		0x1	/* PCI/ISA Bridge */
3097c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_EISA		0x2	/* PCI/EISA Bridge */
3107c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_MC		0x3	/* PCI/MC Bridge */
3117c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_PCI		0x4	/* PCI/PCI Bridge */
3127c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_PCMCIA	0x5	/* PCI/PCMCIA Bridge */
3137c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_NUBUS	0x6	/* PCI/NUBUS Bridge */
3147c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_CARDBUS	0x7	/* PCI/CARDBUS Bridge */
3157c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_RACE		0x8	/* RACE-way Bridge */
3167c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_STPCI	0x9	/* Semi-transparent PCI/PCI Bridge */
3177c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_IB		0xA	/* InfiniBand/PCI host Bridge */
318337fc9e2Sanish #define	PCI_BRIDGE_AS		0xB	/* AS/PCI host Bridge */
3197c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_OTHER	0x80	/* PCI/Other Bridge Device */
3207c478bd9Sstevel@tonic-gate 
3217c478bd9Sstevel@tonic-gate /*
3227c478bd9Sstevel@tonic-gate  * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
3237c478bd9Sstevel@tonic-gate  */
3247c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_PCI_IF_PCI2PCI	0x0	/* PCI-PCI bridge */
3257c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_PCI_IF_SUBDECODE	0x1	/* Subtractive Decode */
3267c478bd9Sstevel@tonic-gate 						/* PCI/PCI bridge */
3277c478bd9Sstevel@tonic-gate 
3287c478bd9Sstevel@tonic-gate /*
3297c478bd9Sstevel@tonic-gate  * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge
3307c478bd9Sstevel@tonic-gate  */
3317c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_RACE_IF_TRANSPARENT	0x0	/* Transport mode */
3327c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_RACE_IF_ENDPOINT	0x1	/* Endpoint mode */
3337c478bd9Sstevel@tonic-gate 
3347c478bd9Sstevel@tonic-gate /*
3357c478bd9Sstevel@tonic-gate  * programming interface for Bridges class 0x6 (subclass 09)
3367c478bd9Sstevel@tonic-gate  * Semi-transparent PCI-to-PCI bridge
3377c478bd9Sstevel@tonic-gate  */
3387c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_STPCI_IF_PRIMARY	0x40	/* primary PCI side bus */
3397c478bd9Sstevel@tonic-gate 						/* facing system processor */
3407c478bd9Sstevel@tonic-gate #define	PCI_BRIDGE_STPCI_IF_SECONDARY	0x80	/* secondary PCI side bus */
3417c478bd9Sstevel@tonic-gate 						/* facing system processor */
3427c478bd9Sstevel@tonic-gate 
343337fc9e2Sanish /*
344337fc9e2Sanish  * programming interface for Bridges class 0x6 (subclass 0B) AS bridge
345337fc9e2Sanish  */
346337fc9e2Sanish #define	PCI_BRIDGE_AS_CUSTOM_INTFC	0x0	/* Custom interface */
347337fc9e2Sanish #define	PCI_BRIDGE_AS_PORTAL_INTFC	0x1	/* ASI-SIG Portal Interface */
348337fc9e2Sanish 
3497c478bd9Sstevel@tonic-gate /*
3507c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x7 (communication devices)
3517c478bd9Sstevel@tonic-gate  */
3527c478bd9Sstevel@tonic-gate #define	PCI_COMM_GENERIC_XT	0x0	/* XT Compatible Serial Controller */
3537c478bd9Sstevel@tonic-gate #define	PCI_COMM_PARALLEL	0x1	/* Parallel Port Controller */
3547c478bd9Sstevel@tonic-gate #define	PCI_COMM_MSC		0x2	/* Multiport Serial Controller */
3557c478bd9Sstevel@tonic-gate #define	PCI_COMM_MODEM		0x3	/* Modem Controller */
3567c478bd9Sstevel@tonic-gate #define	PCI_COMM_GPIB		0x4	/* GPIB Controller */
3577c478bd9Sstevel@tonic-gate #define	PCI_COMM_SMARTCARD	0x5	/* Smart Card Controller */
3587c478bd9Sstevel@tonic-gate #define	PCI_COMM_OTHER		0x80	/* Other Communications Controller */
3597c478bd9Sstevel@tonic-gate 
3607c478bd9Sstevel@tonic-gate /*
3617c478bd9Sstevel@tonic-gate  * Programming interfaces for class 0x7 / subclass 0x0 (Serial)
3627c478bd9Sstevel@tonic-gate  */
3637c478bd9Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_GENERIC	0x0	/* Generic XT-compat serial */
3647c478bd9Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16450	0x1	/* 16450-compat serial ctrlr */
3657c478bd9Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16550	0x2	/* 16550-compat serial ctrlr */
3667c478bd9Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16650	0x3	/* 16650-compat serial ctrlr */
3677c478bd9Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16750	0x4	/* 16750-compat serial ctrlr */
3687c478bd9Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16850	0x5	/* 16850-compat serial ctrlr */
3697c478bd9Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16950	0x6	/* 16950-compat serial ctrlr */
3707c478bd9Sstevel@tonic-gate 
3717c478bd9Sstevel@tonic-gate /*
3727c478bd9Sstevel@tonic-gate  * Programming interfaces for class 0x7 / subclass 0x1 (Parallel)
3737c478bd9Sstevel@tonic-gate  */
3747c478bd9Sstevel@tonic-gate #define	PCI_COMM_PARALLEL_IF_GENERIC	0x0	/* Generic Parallel port */
3757c478bd9Sstevel@tonic-gate #define	PCI_COMM_PARALLEL_IF_BIDIRECT	0x1	/* Bi-directional Parallel */
3767c478bd9Sstevel@tonic-gate #define	PCI_COMM_PARALLEL_IF_ECP	0x2	/* ECP 1.X Parallel port */
3777c478bd9Sstevel@tonic-gate #define	PCI_COMM_PARALLEL_IF_1284	0x3	/* IEEE 1284 Parallel port */
3787c478bd9Sstevel@tonic-gate #define	PCI_COMM_PARALLEL_IF_1284_TARG	0xFE	/* IEEE 1284 target device */
3797c478bd9Sstevel@tonic-gate 
3807c478bd9Sstevel@tonic-gate /*
3817c478bd9Sstevel@tonic-gate  * Programming interfaces for class 0x7 / subclass 0x3 (Modem)
3827c478bd9Sstevel@tonic-gate  */
3837c478bd9Sstevel@tonic-gate #define	PCI_COMM_MODEM_IF_GENERIC	0x0	/* Generic Modem */
3847c478bd9Sstevel@tonic-gate #define	PCI_COMM_MODEM_IF_HAYES_16450	0x1	/* Hayes 16450-compat Modem */
3857c478bd9Sstevel@tonic-gate #define	PCI_COMM_MODEM_IF_HAYES_16550	0x2	/* Hayes 16550-compat Modem */
3867c478bd9Sstevel@tonic-gate #define	PCI_COMM_MODEM_IF_HAYES_16650	0x3	/* Hayes 16650-compat Modem */
3877c478bd9Sstevel@tonic-gate #define	PCI_COMM_MODEM_IF_HAYES_16750	0x4	/* Hayes 16750-compat Modem */
3887c478bd9Sstevel@tonic-gate 
3897c478bd9Sstevel@tonic-gate /*
3907c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x8
3917c478bd9Sstevel@tonic-gate  */
3927c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_PIC		0x0	/* Generic PIC */
3937c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_DMA		0x1	/* Generic DMA Controller */
3947c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_TIMER	0x2	/* Generic System Timer Controller */
3957c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_RTC		0x3	/* Generic RTC Controller */
396337fc9e2Sanish #define	PCI_PERIPH_HPC		0x4	/* Generic PCI Hot-Plug Controller */
397337fc9e2Sanish #define	PCI_PERIPH_SD_HC	0x5	/* SD Host Controller */
398337fc9e2Sanish #define	PCI_PERIPH_IOMMU	0x6	/* IOMMU */
3997c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_OTHER	0x80	/* Other System Peripheral */
4007c478bd9Sstevel@tonic-gate 
4017c478bd9Sstevel@tonic-gate /*
4027c478bd9Sstevel@tonic-gate  * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller)
4037c478bd9Sstevel@tonic-gate  */
4047c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_PIC_IF_GENERIC	0x0	/* Generic 8259 APIC */
4057c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_PIC_IF_ISA		0x1	/* ISA PIC */
4067c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_PIC_IF_EISA		0x2	/* EISA PIC */
4077c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_PIC_IF_IO_APIC	0x10	/* I/O APIC interrupt ctrlr */
4087c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_PIC_IF_IOX_APIC	0x20	/* I/O(x) APIC intr ctrlr */
4097c478bd9Sstevel@tonic-gate 
4107c478bd9Sstevel@tonic-gate /*
4117c478bd9Sstevel@tonic-gate  * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller)
4127c478bd9Sstevel@tonic-gate  */
4137c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_DMA_IF_GENERIC	0x0	/* Generic 8237 DMA ctrlr */
4147c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_DMA_IF_ISA		0x1	/* ISA DMA ctrlr */
4157c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_DMA_IF_EISA		0x2	/* EISA DMA ctrlr */
4167c478bd9Sstevel@tonic-gate 
4177c478bd9Sstevel@tonic-gate /*
4187c478bd9Sstevel@tonic-gate  * Programming interfaces for class 0x8 / subclass 0x2 (timer)
4197c478bd9Sstevel@tonic-gate  */
4207c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_TIMER_IF_GENERIC	0x0	/* Generic 8254 system timer */
4217c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_TIMER_IF_ISA		0x1	/* ISA system timers */
4227c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_TIMER_IF_EISA	0x2	/* EISA system timers (two) */
423337fc9e2Sanish #define	PCI_PERIPH_TIMER_IF_HPET	0x3	/* High Perf Event timer */
4247c478bd9Sstevel@tonic-gate 
4257c478bd9Sstevel@tonic-gate /*
4267c478bd9Sstevel@tonic-gate  * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock)
4277c478bd9Sstevel@tonic-gate  */
4287c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_RTC_IF_GENERIC	0x0	/* Generic RTC controller */
4297c478bd9Sstevel@tonic-gate #define	PCI_PERIPH_RTC_IF_ISA		0x1	/* ISA RTC controller */
4307c478bd9Sstevel@tonic-gate 
4317c478bd9Sstevel@tonic-gate /*
4327c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x9
4337c478bd9Sstevel@tonic-gate  */
4347c478bd9Sstevel@tonic-gate #define	PCI_INPUT_KEYBOARD	0x0	/* Keyboard Controller */
4357c478bd9Sstevel@tonic-gate #define	PCI_INPUT_DIGITIZ	0x1	/* Digitizer (Pen) */
4367c478bd9Sstevel@tonic-gate #define	PCI_INPUT_MOUSE		0x2	/* Mouse Controller */
4377c478bd9Sstevel@tonic-gate #define	PCI_INPUT_SCANNER	0x3	/* Scanner Controller */
4387c478bd9Sstevel@tonic-gate #define	PCI_INPUT_GAMEPORT	0x4	/* Gameport Controller */
4397c478bd9Sstevel@tonic-gate #define	PCI_INPUT_OTHER		0x80	/* Other Input Controller */
4407c478bd9Sstevel@tonic-gate 
4417c478bd9Sstevel@tonic-gate /*
4427c478bd9Sstevel@tonic-gate  * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller)
4437c478bd9Sstevel@tonic-gate  */
4447c478bd9Sstevel@tonic-gate #define	PCI_INPUT_GAMEPORT_IF_GENERIC	0x00	/* Generic controller */
4457c478bd9Sstevel@tonic-gate #define	PCI_INPUT_GAMEPORT_IF_LEGACY	0x10	/* Legacy controller */
4467c478bd9Sstevel@tonic-gate 
4477c478bd9Sstevel@tonic-gate /*
448337fc9e2Sanish  * PCI Sub-class codes - base class 0xA
4497c478bd9Sstevel@tonic-gate  */
4507c478bd9Sstevel@tonic-gate #define	PCI_DOCK_GENERIC	0x00	/* Generic Docking Station */
4517c478bd9Sstevel@tonic-gate #define	PCI_DOCK_OTHER		0x80	/* Other Type of Docking Station */
4527c478bd9Sstevel@tonic-gate 
4537c478bd9Sstevel@tonic-gate /*
454337fc9e2Sanish  * PCI Sub-class codes - base class 0xB
4557c478bd9Sstevel@tonic-gate  */
4567c478bd9Sstevel@tonic-gate #define	PCI_PROCESSOR_386	0x0	/* 386 */
4577c478bd9Sstevel@tonic-gate #define	PCI_PROCESSOR_486	0x1	/* 486 */
4587c478bd9Sstevel@tonic-gate #define	PCI_PROCESSOR_PENT	0x2	/* Pentium */
4597c478bd9Sstevel@tonic-gate #define	PCI_PROCESSOR_ALPHA	0x10	/* Alpha */
4607c478bd9Sstevel@tonic-gate #define	PCI_PROCESSOR_POWERPC	0x20	/* PowerPC */
4617c478bd9Sstevel@tonic-gate #define	PCI_PROCESSOR_MIPS	0x30	/* MIPS */
4627c478bd9Sstevel@tonic-gate #define	PCI_PROCESSOR_COPROC	0x40	/* Co-processor */
463337fc9e2Sanish #define	PCI_PROCESSOR_OTHER	0x80	/* Other processors */
4647c478bd9Sstevel@tonic-gate 
4657c478bd9Sstevel@tonic-gate /*
466337fc9e2Sanish  * PCI Sub-class codes - base class 0xC (Serial Controllers)
4677c478bd9Sstevel@tonic-gate  */
4687c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_FIRE		0x0	/* FireWire (IEEE 1394) */
4697c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_ACCESS	0x1	/* ACCESS.bus */
4707c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_SSA		0x2	/* SSA */
4717c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_USB		0x3	/* Universal Serial Bus */
4727c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_FIBRE	0x4	/* Fibre Channel */
4737c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_SMBUS	0x5	/* System Management Bus */
4747c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_IB		0x6	/* InfiniBand */
4757c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_IPMI		0x7	/* IPMI */
4767c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_SERCOS	0x8	/* SERCOS Interface Std (IEC 61491) */
4777c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_CANBUS	0x9	/* CANbus */
478337fc9e2Sanish #define	PCI_SERIAL_OTHER	0x80	/* Other Serial Bus Controllers */
479337fc9e2Sanish 
480337fc9e2Sanish /*
481337fc9e2Sanish  * Programming interfaces for class 0xC / subclass 0x0 (Firewire)
482337fc9e2Sanish  */
483337fc9e2Sanish #define	PCI_SERIAL_FIRE_WIRE  		0x00	/* IEEE 1394 (Firewire) */
484337fc9e2Sanish #define	PCI_SERIAL_FIRE_1394_HCI 	0x10	/* 1394 OpenHCI Host Cntrlr */
4857c478bd9Sstevel@tonic-gate 
4867c478bd9Sstevel@tonic-gate /*
4877c478bd9Sstevel@tonic-gate  * Programming interfaces for class 0xC / subclass 0x3 (USB controller)
4887c478bd9Sstevel@tonic-gate  */
4897c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_USB_IF_UHCI 		0x00	/* UHCI Compliant */
4907c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_USB_IF_OHCI 		0x10	/* OHCI Compliant */
4917c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_USB_IF_EHCI 		0x20	/* EHCI Compliant */
4927c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_USB_IF_GENERIC 	0x80	/* no specific HCD */
4937c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_USB_IF_DEVICE 	0xFE	/* not a HCD */
4947c478bd9Sstevel@tonic-gate 
4957c478bd9Sstevel@tonic-gate /*
4967c478bd9Sstevel@tonic-gate  * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller)
4977c478bd9Sstevel@tonic-gate  */
4987c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_IPMI_IF_SMIC 	0x0	/* SMIC Interface */
4997c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_IPMI_IF_KBD 		0x1	/* Keyboard Ctrl Style Intfc */
5007c478bd9Sstevel@tonic-gate #define	PCI_SERIAL_IPMI_IF_BTI		0x2	/* Block Transfer Interface */
5017c478bd9Sstevel@tonic-gate 
5027c478bd9Sstevel@tonic-gate /*
503337fc9e2Sanish  * PCI Sub-class codes - base class 0xD (Wireless controllers)
5047c478bd9Sstevel@tonic-gate  */
5057c478bd9Sstevel@tonic-gate #define	PCI_WIRELESS_IRDA		0x0	/* iRDA Compatible Controller */
5067c478bd9Sstevel@tonic-gate #define	PCI_WIRELESS_IR			0x1	/* Consumer IR Controller */
5077c478bd9Sstevel@tonic-gate #define	PCI_WIRELESS_RF			0x10	/* RF Controller */
5087c478bd9Sstevel@tonic-gate #define	PCI_WIRELESS_BLUETOOTH		0x11	/* Bluetooth Controller */
5097c478bd9Sstevel@tonic-gate #define	PCI_WIRELESS_BROADBAND		0x12	/* Broadband Controller */
5107c478bd9Sstevel@tonic-gate #define	PCI_WIRELESS_80211A		0x20	/* Ethernet 802.11a 5 GHz */
5117c478bd9Sstevel@tonic-gate #define	PCI_WIRELESS_80211B		0x21	/* Ethernet 802.11b 2.4 GHz */
5127c478bd9Sstevel@tonic-gate #define	PCI_WIRELESS_OTHER		0x80	/* Other Wireless Controllers */
5137c478bd9Sstevel@tonic-gate 
5147c478bd9Sstevel@tonic-gate /*
515337fc9e2Sanish  * Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller)
516337fc9e2Sanish  */
517337fc9e2Sanish #define	PCI_WIRELESS_IR_CONSUMER 	0x00	/* Consumer IR Controller */
518337fc9e2Sanish #define	PCI_WIRELESS_IR_UWB_RC 		0x10	/* UWB Radio Controller */
519337fc9e2Sanish 
520337fc9e2Sanish /*
521337fc9e2Sanish  * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
5227c478bd9Sstevel@tonic-gate  */
523337fc9e2Sanish #define	PCI_INTIO_MSG_FIFO		0x0	/* Message FIFO at off 40h */
5247c478bd9Sstevel@tonic-gate #define	PCI_INTIO_I20			0x1	/* I20 Arch Spec 1.0 */
5257c478bd9Sstevel@tonic-gate 
5267c478bd9Sstevel@tonic-gate /*
527337fc9e2Sanish  * PCI Sub-class codes - base class 0xF (Satellite Communication controllers)
5287c478bd9Sstevel@tonic-gate  */
5297c478bd9Sstevel@tonic-gate #define	PCI_SATELLITE_COMM_TV		0x01	/* TV */
5307c478bd9Sstevel@tonic-gate #define	PCI_SATELLITE_COMM_AUDIO	0x02	/* Audio */
5317c478bd9Sstevel@tonic-gate #define	PCI_SATELLITE_COMM_VOICE	0x03	/* Voice */
5327c478bd9Sstevel@tonic-gate #define	PCI_SATELLITE_COMM_DATA		0x04	/* DATA */
533337fc9e2Sanish #define	PCI_SATELLITE_COMM_OTHER	0x80	/* Other Satelite Comm Cntrlr */
5347c478bd9Sstevel@tonic-gate 
5357c478bd9Sstevel@tonic-gate /*
5367c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
5377c478bd9Sstevel@tonic-gate  */
5387c478bd9Sstevel@tonic-gate #define	PCI_CRYPT_NETWORK		0x00	/* Network and Computing */
5397c478bd9Sstevel@tonic-gate #define	PCI_CRYPT_ENTERTAINMENT		0x10	/* Entertainment en/decrypt */
5407c478bd9Sstevel@tonic-gate #define	PCI_CRYPT_OTHER			0x80	/* Other en/decryption ctrlrs */
5417c478bd9Sstevel@tonic-gate 
5427c478bd9Sstevel@tonic-gate /*
5437c478bd9Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
5447c478bd9Sstevel@tonic-gate  */
5457c478bd9Sstevel@tonic-gate #define	PCI_SIGNAL_DPIO			0x00	/* DPIO modules */
5467c478bd9Sstevel@tonic-gate #define	PCI_SIGNAL_PERF_COUNTERS	0x01	/* Performance counters */
5477c478bd9Sstevel@tonic-gate #define	PCI_SIGNAL_COMM_SYNC		0x10	/* Comm. synchronization plus */
5487c478bd9Sstevel@tonic-gate 						/* time and freq test ctrlr */
5497c478bd9Sstevel@tonic-gate #define	PCI_SIGNAL_MANAGEMENT		0x20	/* Management card */
5507c478bd9Sstevel@tonic-gate #define	PCI_SIGNAL_OTHER		0x80	/* DSP/DAP controller */
5517c478bd9Sstevel@tonic-gate 
5527c478bd9Sstevel@tonic-gate /* PCI header decode */
5537c478bd9Sstevel@tonic-gate #define	PCI_HEADER_MULTI	0x80	/* multi-function device */
5547c478bd9Sstevel@tonic-gate #define	PCI_HEADER_ZERO		0x00	/* type zero PCI header */
5557c478bd9Sstevel@tonic-gate #define	PCI_HEADER_ONE		0x01	/* type one PCI header */
5567c478bd9Sstevel@tonic-gate #define	PCI_HEADER_TWO		0x02	/* type two PCI header */
5577c478bd9Sstevel@tonic-gate #define	PCI_HEADER_PPB		PCI_HEADER_ONE  /* type one PCI to PCI Bridge */
5587c478bd9Sstevel@tonic-gate #define	PCI_HEADER_CARDBUS	PCI_HEADER_TWO	/* type one PCI header */
5597c478bd9Sstevel@tonic-gate 
5607c478bd9Sstevel@tonic-gate #define	PCI_HEADER_TYPE_M	0x7f  /* type mask for header */
5617c478bd9Sstevel@tonic-gate 
5627c478bd9Sstevel@tonic-gate /*
5637c478bd9Sstevel@tonic-gate  * Base register bit definitions.
5647c478bd9Sstevel@tonic-gate  */
5657c478bd9Sstevel@tonic-gate #define	PCI_BASE_SPACE_M    0x1  /* memory space indicator */
5667c478bd9Sstevel@tonic-gate #define	PCI_BASE_SPACE_IO   0x1   /* IO space */
5677c478bd9Sstevel@tonic-gate #define	PCI_BASE_SPACE_MEM  0x0   /* memory space */
5687c478bd9Sstevel@tonic-gate 
5697c478bd9Sstevel@tonic-gate #define	PCI_BASE_TYPE_MEM   0x0   /* 32-bit memory address */
5707c478bd9Sstevel@tonic-gate #define	PCI_BASE_TYPE_LOW   0x2   /* less than 1Mb address */
5717c478bd9Sstevel@tonic-gate #define	PCI_BASE_TYPE_ALL   0x4   /* 64-bit memory address */
5727c478bd9Sstevel@tonic-gate #define	PCI_BASE_TYPE_RES   0x6   /* reserved */
5737c478bd9Sstevel@tonic-gate 
5747c478bd9Sstevel@tonic-gate #define	PCI_BASE_TYPE_M		0x00000006  /* type indicator mask */
5757c478bd9Sstevel@tonic-gate #define	PCI_BASE_PREF_M		0x00000008  /* prefetch mask */
5767c478bd9Sstevel@tonic-gate #define	PCI_BASE_M_ADDR_M	0xfffffff0  /* memory address mask */
5777c478bd9Sstevel@tonic-gate #define	PCI_BASE_IO_ADDR_M	0xfffffffe  /* I/O address mask */
5787c478bd9Sstevel@tonic-gate 
5797c478bd9Sstevel@tonic-gate #define	PCI_BASE_ROM_ADDR_M	0xfffff800  /* ROM address mask */
5807c478bd9Sstevel@tonic-gate #define	PCI_BASE_ROM_ENABLE	0x00000001  /* ROM decoder enable */
5817c478bd9Sstevel@tonic-gate 
5827c478bd9Sstevel@tonic-gate /*
5837c478bd9Sstevel@tonic-gate  * Capabilities linked list entry offsets
5847c478bd9Sstevel@tonic-gate  */
5857c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID		0x0	/* capability identifier, 1 byte */
5867c478bd9Sstevel@tonic-gate #define	PCI_CAP_NEXT_PTR	0x1	/* next entry pointer, 1 byte */
58770025d76Sjohnny #define	PCI_CAP_ID_REGS_OFF	0x2	/* cap id register offset */
5887c478bd9Sstevel@tonic-gate #define	PCI_CAP_MAX_PTR		0x30	/* maximum number of cap pointers */
5897c478bd9Sstevel@tonic-gate #define	PCI_CAP_PTR_OFF		0x40	/* minimum cap pointer offset */
5907c478bd9Sstevel@tonic-gate #define	PCI_CAP_PTR_MASK	0xFC	/* mask for capability pointer */
5917c478bd9Sstevel@tonic-gate 
5927c478bd9Sstevel@tonic-gate /*
5937c478bd9Sstevel@tonic-gate  * Capability identifier values
5947c478bd9Sstevel@tonic-gate  */
5957c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_PM		0x1	/* power management entry */
5967c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_AGP		0x2	/* AGP supported */
5977c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_VPD		0x3	/* VPD supported */
5987c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_SLOT_ID	0x4	/* Slot Identification supported */
5997c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_MSI		0x5	/* MSI supported */
6007c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_cPCI_HS	0x6	/* CompactPCI Host Swap supported */
6017c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_PCIX		0x7	/* PCI-X supported */
6027c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_HT		0x8	/* HyperTransport supported */
6037c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_VS		0x9	/* Vendor Specific */
6047c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_DEBUG_PORT	0xA	/* Debug Port supported */
6057c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_cPCI_CRC	0xB	/* CompactPCI central resource ctrl */
606*26947304SEvan Yan #define	PCI_CAP_ID_PCI_HOTPLUG	0xC	/* PCI Hot Plug (SHPC) supported */
607337fc9e2Sanish #define	PCI_CAP_ID_P2P_SUBSYS	0xD	/* PCI bridge Sub-system ID */
6087c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_AGP_8X	0xE	/* AGP 8X supported */
6097c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_SECURE_DEV	0xF	/* Secure Device supported */
6107c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_PCI_E	0x10	/* PCI Express supported */
6117c478bd9Sstevel@tonic-gate #define	PCI_CAP_ID_MSI_X	0x11	/* MSI-X supported */
612337fc9e2Sanish #define	PCI_CAP_ID_SATA		0x12	/* SATA Data/Index Config supported */
613337fc9e2Sanish #define	PCI_CAP_ID_FLR		0x13	/* Function Level Reset supported */
6147c478bd9Sstevel@tonic-gate 
6157c478bd9Sstevel@tonic-gate /*
6167c478bd9Sstevel@tonic-gate  * Capability next entry pointer values
6177c478bd9Sstevel@tonic-gate  */
6187c478bd9Sstevel@tonic-gate #define	PCI_CAP_NEXT_PTR_NULL	0x0	/* no more entries in the list */
6197c478bd9Sstevel@tonic-gate 
6207c478bd9Sstevel@tonic-gate /*
6217c478bd9Sstevel@tonic-gate  * PCI power management (PM) capability entry offsets
6227c478bd9Sstevel@tonic-gate  */
6237c478bd9Sstevel@tonic-gate #define	PCI_PMCAP		0x2	/* PM capabilities, 2 bytes */
6247c478bd9Sstevel@tonic-gate #define	PCI_PMCSR		0x4	/* PM control/status reg, 2 bytes */
6257c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_BSE		0x6	/* PCI-PCI bridge extensions, 1 byte */
6267c478bd9Sstevel@tonic-gate #define	PCI_PMDATA		0x7	/* PM data, 1 byte */
6277c478bd9Sstevel@tonic-gate 
6287c478bd9Sstevel@tonic-gate /*
6297c478bd9Sstevel@tonic-gate  * PM capabilities values - 2 bytes
6307c478bd9Sstevel@tonic-gate  */
6317c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_VER_1_0	0x1	/* PCI PM spec 1.0 */
6327c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_VER_1_1	0x2	/* PCI PM spec 1.1 */
6337c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_VER_MASK	0x7	/* version mask */
6347c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_PME_CLOCK	0x8	/* needs PCI clock for PME */
6357c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_DSI		0x20	/* needs device specific init */
6367c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_SELF	0x0	/* 0 aux current - self powered */
6377c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_55mA	0x40	/* 55 mA aux current */
6387c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_100mA	0x80	/* 100 mA aux current */
6397c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_160mA	0xc0	/* 160 mA aux current */
6407c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_220mA	0x100	/* 220 mA aux current */
6417c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_270mA	0x140	/* 270 mA aux current */
6427c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_320mA	0x180	/* 320 mA aux current */
6437c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_375mA	0x1c0	/* 375 mA aux current */
6447c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_MASK	0x1c0	/* 3.3Vaux aux current needs */
6457c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_D1		0x200	/* D1 state supported */
6467c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_D2		0x400	/* D2 state supported */
6477c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_D0_PME	0x800	/* PME from D0 */
6487c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_D1_PME	0x1000	/* PME from D1 */
6497c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_D2_PME	0x2000	/* PME from D2 */
6507c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_D3HOT_PME	0x4000	/* PME from D3hot */
6517c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_D3COLD_PME	0x8000	/* PME from D3cold */
6527c478bd9Sstevel@tonic-gate #define	PCI_PMCAP_PME_MASK	0xf800	/* PME support mask */
6537c478bd9Sstevel@tonic-gate 
6547c478bd9Sstevel@tonic-gate /*
6557c478bd9Sstevel@tonic-gate  * PM control/status values - 2 bytes
6567c478bd9Sstevel@tonic-gate  */
6577c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_D0			0x0	/* power state D0 */
6587c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_D1			0x1	/* power state D1 */
6597c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_D2			0x2	/* power state D2 */
6607c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_D3HOT			0x3	/* power state D3hot */
6617c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_STATE_MASK		0x3	/* power state mask */
6627c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_PME_EN		0x100	/* enable PME assertion */
6637c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D0_PWR_C		0x0	/* D0 power consumed */
6647c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D1_PWR_C		0x200	/* D1 power consumed */
6657c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D2_PWR_C		0x400	/* D2 power consumed */
6667c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D3_PWR_C		0x600	/* D3 power consumed */
6677c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D0_PWR_D		0x800	/* D0 power dissipated */
6687c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D1_PWR_D		0xa00	/* D1 power dissipated */
6697c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D2_PWR_D		0xc00	/* D2 power dissipated */
6707c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D3_PWR_D		0xe00	/* D3 power dissipated */
6717c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_COM_C		0x1000	/* common power consumption */
6727c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_MASK		0x1e00	/* data select mask */
6737c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSCL_UNKNOWN		0x0	/* data scale unknown */
6747c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSCL_1_BY_10		0x2000	/* data scale 0.1x */
6757c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSCL_1_BY_100		0x4000	/* data scale 0.01x */
6767c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSCL_1_BY_1000	0x6000	/* data scale 0.001x */
6777c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_DSCL_MASK		0x6000	/* data scale mask */
6787c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_PME_STAT		0x8000	/* PME status */
6797c478bd9Sstevel@tonic-gate 
6807c478bd9Sstevel@tonic-gate /*
6817c478bd9Sstevel@tonic-gate  * PM PMCSR PCI to PCI bridge support extension values - 1 byte
6827c478bd9Sstevel@tonic-gate  */
6837c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_BSE_B2_B3	0x40	/* bridge D3hot -> secondary B2 */
6847c478bd9Sstevel@tonic-gate #define	PCI_PMCSR_BSE_BPCC_EN	0x80	/* bus power/clock control enabled */
6857c478bd9Sstevel@tonic-gate 
6867c478bd9Sstevel@tonic-gate /*
6877c478bd9Sstevel@tonic-gate  * PCI-X capability related definitions
6887c478bd9Sstevel@tonic-gate  */
6897c478bd9Sstevel@tonic-gate #define	PCI_PCIX_COMMAND	0x2	/* Command register offset */
69000d0963fSdilpreet #define	PCI_PCIX_STATUS		0x4	/* Status register offset */
69100d0963fSdilpreet #define	PCI_PCIX_ECC_STATUS	0x8	/* ECC Status register offset */
69200d0963fSdilpreet #define	PCI_PCIX_ECC_FST_AD	0xC	/* ECC First address register offset */
69300d0963fSdilpreet #define	PCI_PCIX_ECC_SEC_AD	0x10	/* ECC Second address register offset */
69400d0963fSdilpreet #define	PCI_PCIX_ECC_ATTR	0x14	/* ECC Attribute register offset */
6957c478bd9Sstevel@tonic-gate 
69600d0963fSdilpreet /*
69700d0963fSdilpreet  * PCI-X bridge capability related definitions
69800d0963fSdilpreet  */
699bf8fc234Set #define	PCI_PCIX_SEC_STATUS		0x2	/* Secondary Status offset */
700bf8fc234Set #define	PCI_PCIX_SEC_STATUS_SCD		0x4	/* Split Completion Discarded */
701bf8fc234Set #define	PCI_PCIX_SEC_STATUS_USC		0x8	/* Unexpected Split Complete */
702bf8fc234Set #define	PCI_PCIX_SEC_STATUS_SCO		0x10	/* Split Completion Overrun */
703bf8fc234Set #define	PCI_PCIX_SEC_STATUS_SRD		0x20	/* Split Completion Delayed */
704bf8fc234Set #define	PCI_PCIX_SEC_STATUS_ERR_MASK	0x3C
705bf8fc234Set 
706bf8fc234Set #define	PCI_PCIX_BDG_STATUS		0x4	/* Bridge Status offset */
707bf8fc234Set #define	PCI_PCIX_BDG_STATUS_USC		0x80000
708bf8fc234Set #define	PCI_PCIX_BDG_STATUS_SCO		0x100000
709bf8fc234Set #define	PCI_PCIX_BDG_STATUS_SRD		0x200000
710bf8fc234Set #define	PCI_PCIX_BDG_STATUS_ERR_MASK	0x380000
711bf8fc234Set 
71200d0963fSdilpreet #define	PCI_PCIX_UP_SPL_CTL	0x8	/* Upstream split ctrl reg offset */
71300d0963fSdilpreet #define	PCI_PCIX_DOWN_SPL_CTL	0xC	/* Downstream split ctrl reg offset */
71400d0963fSdilpreet #define	PCI_PCIX_BDG_ECC_STATUS	0x10	/* ECC Status register offset */
71500d0963fSdilpreet #define	PCI_PCIX_BDG_ECC_FST_AD	0x14	/* ECC First address register offset */
71600d0963fSdilpreet #define	PCI_PCIX_BDG_ECC_SEC_AD	0x18	/* ECC Second address register offset */
71700d0963fSdilpreet #define	PCI_PCIX_BDG_ECC_ATTR	0x1C	/* ECC Attribute register offset */
71800d0963fSdilpreet 
71900d0963fSdilpreet /*
72000d0963fSdilpreet  * PCIX capabilities values
72100d0963fSdilpreet  */
7227c478bd9Sstevel@tonic-gate #define	PCI_PCIX_VER_MASK	0x3000	/* Bits 12 and 13 */
7237c478bd9Sstevel@tonic-gate #define	PCI_PCIX_VER_0		0x0000	/* PCIX cap list item version 0 */
7247c478bd9Sstevel@tonic-gate #define	PCI_PCIX_VER_1		0x1000	/* PCIX cap list item version 1 */
7257c478bd9Sstevel@tonic-gate #define	PCI_PCIX_VER_2		0x2000	/* PCIX cap list item version 2 */
7267c478bd9Sstevel@tonic-gate 
72700d0963fSdilpreet #define	PCI_PCIX_SPL_DSCD	0x40000 /* Split Completion Discarded */
72800d0963fSdilpreet #define	PCI_PCIX_UNEX_SPL	0x80000	/* Unexpected Split Completion */
72900d0963fSdilpreet #define	PCI_PCIX_RX_SPL_MSG	0x20000000 /* Recieved Spl Comp Error Message */
73000d0963fSdilpreet 
73100d0963fSdilpreet #define	PCI_PCIX_ECC_SEL	0x1	/* Secondary ECC register select */
73200d0963fSdilpreet #define	PCI_PCIX_ECC_EP		0x2	/* Error Present on other side */
73300d0963fSdilpreet #define	PCI_PCIX_ECC_S_CE	0x4	/* Addl Correctable ECC Error */
73400d0963fSdilpreet #define	PCI_PCIX_ECC_S_UE	0x8	/* Addl Uncorrectable ECC Error */
73500d0963fSdilpreet #define	PCI_PCIX_ECC_PHASE	0x70	/* ECC Error Phase */
73600d0963fSdilpreet #define	PCI_PCIX_ECC_CORR	0x80	/* ECC Error Corrected */
73700d0963fSdilpreet #define	PCI_PCIX_ECC_SYN	0xff00	/* ECC Error Syndrome */
73800d0963fSdilpreet #define	PCI_PCIX_ECC_FST_CMD	0xf0000	 /* ECC Error First Command */
73900d0963fSdilpreet #define	PCI_PCIX_ECC_SEC_CMD	0xf00000 /* ECC Error Second Command */
74000d0963fSdilpreet #define	PCI_PCIX_ECC_UP_ATTR	0xf000000 /* ECC Error Upper Attributes */
74100d0963fSdilpreet 
74200d0963fSdilpreet /*
74300d0963fSdilpreet  * PCIX ECC Phase Values
74400d0963fSdilpreet  */
74500d0963fSdilpreet #define	PCI_PCIX_ECC_PHASE_NOERR	0x0
74600d0963fSdilpreet #define	PCI_PCIX_ECC_PHASE_FADDR	0x1
74700d0963fSdilpreet #define	PCI_PCIX_ECC_PHASE_SADDR	0x2
74800d0963fSdilpreet #define	PCI_PCIX_ECC_PHASE_ATTR		0x3
74900d0963fSdilpreet #define	PCI_PCIX_ECC_PHASE_DATA32	0x4
75000d0963fSdilpreet #define	PCI_PCIX_ECC_PHASE_DATA64	0x5
75100d0963fSdilpreet 
75200d0963fSdilpreet /*
75300d0963fSdilpreet  * PCI-X Command Encoding
75400d0963fSdilpreet  */
75500d0963fSdilpreet #define	PCI_PCIX_CMD_INTR		0x0
75600d0963fSdilpreet #define	PCI_PCIX_CMD_SPEC		0x1
75700d0963fSdilpreet #define	PCI_PCIX_CMD_IORD		0x2
75800d0963fSdilpreet #define	PCI_PCIX_CMD_IOWR		0x3
75900d0963fSdilpreet #define	PCI_PCIX_CMD_DEVID		0x5
76000d0963fSdilpreet #define	PCI_PCIX_CMD_MEMRD_DW		0x6
76100d0963fSdilpreet #define	PCI_PCIX_CMD_MEMWR		0x7
76200d0963fSdilpreet #define	PCI_PCIX_CMD_MEMRD_BL		0x8
76300d0963fSdilpreet #define	PCI_PCIX_CMD_MEMWR_BL		0x9
76400d0963fSdilpreet #define	PCI_PCIX_CMD_CFRD		0xA
76500d0963fSdilpreet #define	PCI_PCIX_CMD_CFWR		0xB
76600d0963fSdilpreet #define	PCI_PCIX_CMD_SPL		0xC
76700d0963fSdilpreet #define	PCI_PCIX_CMD_DADR		0xD
76800d0963fSdilpreet #define	PCI_PCIX_CMD_MEMRDBL		0xE
76900d0963fSdilpreet #define	PCI_PCIX_CMD_MEMWRBL		0xF
77000d0963fSdilpreet 
77100d0963fSdilpreet #if defined(_BIT_FIELDS_LTOH)
77200d0963fSdilpreet typedef struct pcix_attr {
77300d0963fSdilpreet 	uint32_t	lbc	:8,
77400d0963fSdilpreet 			rid	:16,
77500d0963fSdilpreet 			tag	:5,
77600d0963fSdilpreet 			ro	:1,
77700d0963fSdilpreet 			ns	:1,
77800d0963fSdilpreet 			r	:1;
77900d0963fSdilpreet } pcix_attr_t;
78000d0963fSdilpreet #elif defined(_BIT_FIELDS_HTOL)
78100d0963fSdilpreet typedef struct pcix_attr {
78200d0963fSdilpreet 	uint32_t	r	:1,
78300d0963fSdilpreet 			ns	:1,
78400d0963fSdilpreet 			ro	:1,
78500d0963fSdilpreet 			tag	:5,
78600d0963fSdilpreet 			rid	:16,
78700d0963fSdilpreet 			lbc	:8;
78800d0963fSdilpreet } pcix_attr_t;
78900d0963fSdilpreet #else
79000d0963fSdilpreet #error "bit field not defined"
79100d0963fSdilpreet #endif
79200d0963fSdilpreet 
79300d0963fSdilpreet #define	PCI_PCIX_BSS_SPL_DSCD	0x4	/* Secondary split comp discarded */
79400d0963fSdilpreet #define	PCI_PCIX_BSS_UNEX_SPL	0x8	/* Secondary unexpected split comp */
79500d0963fSdilpreet #define	PCI_PCIX_BSS_SPL_OR	0x10	/* Secondary split comp overrun */
79600d0963fSdilpreet #define	PCI_PCIX_BSS_SPL_DLY	0x20	/* Secondary split comp delayed */
79700d0963fSdilpreet 
798*26947304SEvan Yan /*
799*26947304SEvan Yan  * PCI Hotplug capability entry offsets
800*26947304SEvan Yan  *
801*26947304SEvan Yan  * SHPC based PCI hotplug controller registers accessed via the DWORD
802*26947304SEvan Yan  * select and DATA registers in PCI configuration space relative to the
803*26947304SEvan Yan  * PCI HP capibility pointer.
804*26947304SEvan Yan  */
805*26947304SEvan Yan #define	PCI_HP_DWORD_SELECT_OFF		0x2
806*26947304SEvan Yan #define	PCI_HP_DWORD_DATA_OFF		0x4
807*26947304SEvan Yan 
808*26947304SEvan Yan #define	PCI_HP_BASE_OFFSET_REG		0x00
809*26947304SEvan Yan #define	PCI_HP_SLOTS_AVAIL_I_REG	0x01
810*26947304SEvan Yan #define	PCI_HP_SLOTS_AVAIL_II_REG	0x02
811*26947304SEvan Yan #define	PCI_HP_SLOT_CONFIGURATION_REG	0x03
812*26947304SEvan Yan #define	PCI_HP_PROF_IF_SBCR_REG		0x04
813*26947304SEvan Yan #define	PCI_HP_COMMAND_STATUS_REG	0x05
814*26947304SEvan Yan #define	PCI_HP_IRQ_LOCATOR_REG		0x06
815*26947304SEvan Yan #define	PCI_HP_SERR_LOCATOR_REG		0x07
816*26947304SEvan Yan #define	PCI_HP_CTRL_SERR_INT_REG	0x08
817*26947304SEvan Yan #define	PCI_HP_LOGICAL_SLOT_REGS	0x09
818*26947304SEvan Yan #define	PCI_HP_VENDOR_SPECIFIC		0x28
819*26947304SEvan Yan 
820*26947304SEvan Yan /* Definitions used with the PCI_HP_SLOTS_AVAIL_I_REG register */
821*26947304SEvan Yan #define	PCI_HP_AVAIL_33MHZ_CONV_SPEED_SHIFT	0
822*26947304SEvan Yan #define	PCI_HP_AVAIL_66MHZ_PCIX_SPEED_SHIFT	8
823*26947304SEvan Yan #define	PCI_HP_AVAIL_100MHZ_PCIX_SPEED_SHIFT	16
824*26947304SEvan Yan #define	PCI_HP_AVAIL_133MHZ_PCIX_SPEED_SHIFT	24
825*26947304SEvan Yan #define	PCI_HP_AVAIL_SPEED_MASK			0x1F
826*26947304SEvan Yan 
827*26947304SEvan Yan /* Definitions used with the PCI_HP_SLOTS_AVAIL_II_REG register */
828*26947304SEvan Yan #define	PCI_HP_AVAIL_66MHZ_CONV_SPEED_SHIFT	0
829*26947304SEvan Yan 
830*26947304SEvan Yan /* Register bits used with the PCI_HP_PROF_IF_SBCR_REG register */
831*26947304SEvan Yan #define	PCI_HP_SBCR_33MHZ_CONV_SPEED		0x0
832*26947304SEvan Yan #define	PCI_HP_SBCR_66MHZ_CONV_SPEED		0x1
833*26947304SEvan Yan #define	PCI_HP_SBCR_66MHZ_PCIX_SPEED		0x2
834*26947304SEvan Yan #define	PCI_HP_SBCR_100MHZ_PCIX_SPEED		0x3
835*26947304SEvan Yan #define	PCI_HP_SBCR_133MHZ_PCIX_SPEED		0x4
836*26947304SEvan Yan #define	PCI_HP_SBCR_SPEED_MASK			0x7
837*26947304SEvan Yan 
838*26947304SEvan Yan /* Register bits used with the PCI_HP_COMMAND_STATUS_REG register */
839*26947304SEvan Yan #define	PCI_HP_COMM_STS_ERR_INVALID_SPEED	0x80000
840*26947304SEvan Yan #define	PCI_HP_COMM_STS_ERR_INVALID_COMMAND	0x40000
841*26947304SEvan Yan #define	PCI_HP_COMM_STS_ERR_MRL_OPEN		0x20000
842*26947304SEvan Yan #define	PCI_HP_COMM_STS_ERR_MASK		0xe0000
843*26947304SEvan Yan #define	PCI_HP_COMM_STS_CTRL_BUSY		0x10000
844*26947304SEvan Yan #define	PCI_HP_COMM_STS_SET_SPEED		0x40
845*26947304SEvan Yan 
846*26947304SEvan Yan /* Register bits used with the PCI_HP_CTRL_SERR_INT_REG register */
847*26947304SEvan Yan #define	PCI_HP_SERR_INT_GLOBAL_IRQ_MASK		0x1
848*26947304SEvan Yan #define	PCI_HP_SERR_INT_GLOBAL_SERR_MASK	0x2
849*26947304SEvan Yan #define	PCI_HP_SERR_INT_CMD_COMPLETE_MASK	0x4
850*26947304SEvan Yan #define	PCI_HP_SERR_INT_ARBITER_SERR_MASK	0x8
851*26947304SEvan Yan #define	PCI_HP_SERR_INT_CMD_COMPLETE_IRQ	0x10000
852*26947304SEvan Yan #define	PCI_HP_SERR_INT_ARBITER_IRQ		0x20000
853*26947304SEvan Yan #define	PCI_HP_SERR_INT_MASK_ALL		0xf
854*26947304SEvan Yan 
855*26947304SEvan Yan /* Register bits used with the PCI_HP_LOGICAL_SLOT_REGS register */
856*26947304SEvan Yan #define	PCI_HP_SLOT_POWER_ONLY			0x1
857*26947304SEvan Yan #define	PCI_HP_SLOT_ENABLED			0x2
858*26947304SEvan Yan #define	PCI_HP_SLOT_DISABLED			0x3
859*26947304SEvan Yan #define	PCI_HP_SLOT_STATE_MASK			0x3
860*26947304SEvan Yan #define	PCI_HP_SLOT_MRL_STATE_MASK		0x100
861*26947304SEvan Yan #define	PCI_HP_SLOT_66MHZ_CONV_CAPABLE		0x200
862*26947304SEvan Yan #define	PCI_HP_SLOT_CARD_EMPTY_MASK		0xc00
863*26947304SEvan Yan #define	PCI_HP_SLOT_66MHZ_PCIX_CAPABLE		0x1000
864*26947304SEvan Yan #define	PCI_HP_SLOT_100MHZ_PCIX_CAPABLE		0x2000
865*26947304SEvan Yan #define	PCI_HP_SLOT_133MHZ_PCIX_CAPABLE		0x3000
866*26947304SEvan Yan #define	PCI_HP_SLOT_PCIX_CAPABLE_MASK		0x3000
867*26947304SEvan Yan #define	PCI_HP_SLOT_PCIX_CAPABLE_SHIFT		12
868*26947304SEvan Yan #define	PCI_HP_SLOT_PRESENCE_DETECTED		0x10000
869*26947304SEvan Yan #define	PCI_HP_SLOT_ISO_PWR_DETECTED		0x20000
870*26947304SEvan Yan #define	PCI_HP_SLOT_ATTN_DETECTED		0x40000
871*26947304SEvan Yan #define	PCI_HP_SLOT_MRL_DETECTED		0x80000
872*26947304SEvan Yan #define	PCI_HP_SLOT_POWER_DETECTED		0x100000
873*26947304SEvan Yan #define	PCI_HP_SLOT_PRESENCE_MASK		0x1000000
874*26947304SEvan Yan #define	PCI_HP_SLOT_ISO_PWR_MASK		0x2000000
875*26947304SEvan Yan #define	PCI_HP_SLOT_ATTN_MASK			0x4000000
876*26947304SEvan Yan #define	PCI_HP_SLOT_MRL_MASK			0x8000000
877*26947304SEvan Yan #define	PCI_HP_SLOT_POWER_MASK			0x10000000
878*26947304SEvan Yan #define	PCI_HP_SLOT_MRL_SERR_MASK		0x20000000
879*26947304SEvan Yan #define	PCI_HP_SLOT_POWER_SERR_MASK		0x40000000
880*26947304SEvan Yan #define	PCI_HP_SLOT_MASK_ALL			0x5f000000
881*26947304SEvan Yan 
882*26947304SEvan Yan /* Register bits used with the PCI_HP_IRQ_LOCATOR_REG register */
883*26947304SEvan Yan #define	PCI_HP_IRQ_CMD_COMPLETE			0x1
884*26947304SEvan Yan #define	PCI_HP_IRQ_SLOT_N_PENDING		0x2
885*26947304SEvan Yan 
886*26947304SEvan Yan /* Register bits used with the PCI_HP_SERR_LOCATOR_REG register */
887*26947304SEvan Yan #define	PCI_HP_IRQ_SERR_ARBITER_PENDING		0x1
888*26947304SEvan Yan #define	PCI_HP_IRQ_SERR_SLOT_N_PENDING		0x2
889*26947304SEvan Yan 
890*26947304SEvan Yan /* Register bits used with the PCI_HP_SLOT_CONFIGURATION_REG register */
891*26947304SEvan Yan #define	PCI_HP_SLOT_CONFIG_MRL_SENSOR		0x40000000
892*26947304SEvan Yan #define	PCI_HP_SLOT_CONFIG_ATTN_BUTTON		0x80000000
893*26947304SEvan Yan #define	PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_SHIFT	16
894*26947304SEvan Yan #define	PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_MASK	0x3FF
895*26947304SEvan Yan 
8967c478bd9Sstevel@tonic-gate /*
8977c478bd9Sstevel@tonic-gate  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
8987c478bd9Sstevel@tonic-gate  */
8997c478bd9Sstevel@tonic-gate #define	PCI_MSI_CTRL		0x02	/* MSI control register, 2 bytes */
9007c478bd9Sstevel@tonic-gate #define	PCI_MSI_ADDR_OFFSET	0x04	/* MSI 32-bit msg address, 4 bytes */
9017c478bd9Sstevel@tonic-gate #define	PCI_MSI_32BIT_DATA	0x08	/* MSI 32-bit msg data, 2 bytes */
9027c478bd9Sstevel@tonic-gate #define	PCI_MSI_32BIT_MASK	0x0C	/* MSI 32-bit mask bits, 4 bytes */
9037c478bd9Sstevel@tonic-gate #define	PCI_MSI_32BIT_PENDING	0x10	/* MSI 32-bit pending bits, 4 bytes */
9047c478bd9Sstevel@tonic-gate 
9057c478bd9Sstevel@tonic-gate /*
9067c478bd9Sstevel@tonic-gate  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
9077c478bd9Sstevel@tonic-gate  */
9087c478bd9Sstevel@tonic-gate #define	PCI_MSI_64BIT_DATA	0x0C	/* MSI 64-bit msg data, 2 bytes */
9097c478bd9Sstevel@tonic-gate #define	PCI_MSI_64BIT_MASKBITS	0x10	/* MSI 64-bit mask bits, 4 bytes */
9107c478bd9Sstevel@tonic-gate #define	PCI_MSI_64BIT_PENDING	0x14	/* MSI 64-bit pending bits, 4 bytes */
9117c478bd9Sstevel@tonic-gate 
9127c478bd9Sstevel@tonic-gate /*
9137c478bd9Sstevel@tonic-gate  * PCI Message Signalled Interrupts (MSI) capability masks and shifts
9147c478bd9Sstevel@tonic-gate  */
9157c478bd9Sstevel@tonic-gate #define	PCI_MSI_ENABLE_BIT	0x0001	/* MSI enable mask in MSI ctrl reg */
9167c478bd9Sstevel@tonic-gate #define	PCI_MSI_MMC_MASK	0x000E	/* MMC mask in MSI ctrl reg */
9177c478bd9Sstevel@tonic-gate #define	PCI_MSI_MMC_SHIFT	0x1	/* Shift for MMC bits */
9187c478bd9Sstevel@tonic-gate #define	PCI_MSI_MME_MASK	0x0070	/* MME mask in MSI ctrl reg */
9197c478bd9Sstevel@tonic-gate #define	PCI_MSI_MME_SHIFT	0x4	/* Shift for MME bits */
9207c478bd9Sstevel@tonic-gate #define	PCI_MSI_64BIT_MASK	0x0080	/* 64bit support mask in MSI ctrl reg */
9217c478bd9Sstevel@tonic-gate #define	PCI_MSI_PVM_MASK	0x0100	/* PVM support mask in MSI ctrl reg */
9227c478bd9Sstevel@tonic-gate 
9237c478bd9Sstevel@tonic-gate /*
9247c478bd9Sstevel@tonic-gate  * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
9257c478bd9Sstevel@tonic-gate  */
9267c478bd9Sstevel@tonic-gate #define	PCI_MSIX_CTRL		0x02	/* MSI-X control register, 2 bytes */
9277c478bd9Sstevel@tonic-gate #define	PCI_MSIX_TBL_OFFSET	0x04	/* MSI-X table offset, 4 bytes */
9289c75c6bfSgovinda #define	PCI_MSIX_TBL_BIR_MASK	0x0007	/* MSI-X table BIR mask */
9299c75c6bfSgovinda #define	PCI_MSIX_PBA_OFFSET	0x08	/* MSI-X pending bit array, 4 bytes */
9309c75c6bfSgovinda #define	PCI_MSIX_PBA_BIR_MASK	0x0007	/* MSI-X PBA BIR mask */
9317c478bd9Sstevel@tonic-gate 
9327c478bd9Sstevel@tonic-gate #define	PCI_MSIX_TBL_SIZE_MASK	0x07FF	/* table size mask in MSI-X ctrl reg */
9337c478bd9Sstevel@tonic-gate #define	PCI_MSIX_FUNCTION_MASK	0x4000	/* function mask in MSI-X ctrl reg */
9347c478bd9Sstevel@tonic-gate #define	PCI_MSIX_ENABLE_BIT	0x8000	/* MSI-X enable mask in MSI-X ctl reg */
9357c478bd9Sstevel@tonic-gate 
9367c478bd9Sstevel@tonic-gate #define	PCI_MSIX_LOWER_ADDR_OFFSET	0	/* MSI-X lower addr offset */
9377c478bd9Sstevel@tonic-gate #define	PCI_MSIX_UPPER_ADDR_OFFSET	4	/* MSI-X upper addr offset */
9387c478bd9Sstevel@tonic-gate #define	PCI_MSIX_DATA_OFFSET		8	/* MSI-X data offset */
9397c478bd9Sstevel@tonic-gate #define	PCI_MSIX_VECTOR_CTRL_OFFSET	12	/* MSI-X vector ctrl offset */
9407c478bd9Sstevel@tonic-gate #define	PCI_MSIX_VECTOR_SIZE		16	/* MSI-X size of each vector */
9417c478bd9Sstevel@tonic-gate 
9427c478bd9Sstevel@tonic-gate /*
9437c478bd9Sstevel@tonic-gate  * PCI Message Signalled Interrupts: other interesting constants
9447c478bd9Sstevel@tonic-gate  */
9457c478bd9Sstevel@tonic-gate #define	PCI_MSI_MAX_INTRS	32	/* maximum MSI interrupts supported */
9467c478bd9Sstevel@tonic-gate #define	PCI_MSIX_MAX_INTRS	2048	/* maximum MSI-X interrupts supported */
9477c478bd9Sstevel@tonic-gate 
94870025d76Sjohnny /*
94970025d76Sjohnny  * PCI Slot Id Capabilities, 2 bytes
95070025d76Sjohnny  */
95170025d76Sjohnny /* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */
95270025d76Sjohnny #define	PCI_CAPSLOT_ESR_NSLOTS_MASK	0x1F	/* Number of slots mask */
95370025d76Sjohnny #define	PCI_CAPSLOT_ESR_FIC		0x20	/* First In Chassis bit */
95470025d76Sjohnny #define	PCI_CAPSLOT_ESR_FIC_MASK	0x01	/* First In Chassis mask */
95570025d76Sjohnny #define	PCI_CAPSLOT_ESR_FIC_SHIFT	5	/* First In Chassis shift */
95670025d76Sjohnny #define	PCI_CAPSLOT_FIC(esr_reg)	((esr_reg) & PCI_CAPSLOT_ESR_FIC)
95770025d76Sjohnny #define	PCI_CAPSLOT_NSLOTS(esr_reg)	((esr_reg) & \
95870025d76Sjohnny 						PCI_CAPSLOT_ESR_NSLOTS_MASK)
95970025d76Sjohnny 
960cb7ea99dSJimmy Vetayases /*
961cb7ea99dSJimmy Vetayases  * HyperTransport Capabilities; each HT cap uses the same PCI cap id of
962cb7ea99dSJimmy Vetayases  * PCI_CAP_ID_HT.  The header's upper 16-bits (command reg) contains an HT
963cb7ea99dSJimmy Vetayases  * cap type reg at bits [15:11].  For Slave/Pri Interface and Host/Sec
964cb7ea99dSJimmy Vetayases  * Interface types, only bits [15:13] are used.
965cb7ea99dSJimmy Vetayases  */
966cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_TYPE_MASK		0xF800
967cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_TYPE_SLHOST_MASK	0xE000	/* SLPRI and HOSTSEC types */
968cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_TYPE_SHIFT		11
969cb7ea99dSJimmy Vetayases 
970cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_SLPRI_ID		0x00
971cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_HOSTSEC_ID		0x04
972cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_SWITCH_ID		0x08
973cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_INTCONF_ID		0x10
974cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_REVID_ID		0x11
975cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_UNITID_CLUMP_ID	0x12
976cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_ECFG_ID		0x13
977cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_ADDRMAP_ID		0x14
978cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_MSIMAP_ID		0x15
979cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_DIRROUTE_ID		0x16
980cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_VCSET_ID		0x17
981cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_RETRYMODE_ID		0x18
982cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_X86ENC_ID		0x19
983cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_GEN3_ID		0x1A
984cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_FUNCEXT_ID		0x1B
985cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_PM_ID			0x1C
986cb7ea99dSJimmy Vetayases 
987cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_SLPRI_TYPE		/* 0x0000 */	\
988cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_SLPRI_ID	<< PCI_HTCAP_TYPE_SHIFT)
989cb7ea99dSJimmy Vetayases 
990cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_HOSTSEC_TYPE		/* 0x2000 */	\
991cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_HOSTSEC_ID	<< PCI_HTCAP_TYPE_SHIFT)
992cb7ea99dSJimmy Vetayases 
993cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_SWITCH_TYPE		/* 0x4000 */	\
994cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_SWITCH_ID	<< PCI_HTCAP_TYPE_SHIFT)
995cb7ea99dSJimmy Vetayases 
996cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_INTCONF_TYPE		/* 0x8000 */	\
997cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_INTCONF_ID	<< PCI_HTCAP_TYPE_SHIFT)
998cb7ea99dSJimmy Vetayases 
999cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_REVID_TYPE		/* 0x8800 */	\
1000cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_REVID_ID	<< PCI_HTCAP_TYPE_SHIFT)
1001cb7ea99dSJimmy Vetayases 
1002cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_UNITID_CLUMP_TYPE	/* 0x9000 */	\
1003cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_UNITID_CLUMP_ID	<< PCI_HTCAP_TYPE_SHIFT)
1004cb7ea99dSJimmy Vetayases 
1005cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_ECFG_TYPE		/* 0x9800 */	\
1006cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_ECFG_ID	<< PCI_HTCAP_TYPE_SHIFT)
1007cb7ea99dSJimmy Vetayases 
1008cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_ADDRMAP_TYPE		/* 0xA000 */	\
1009cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_ADDRMAP_ID	<< PCI_HTCAP_TYPE_SHIFT)
1010cb7ea99dSJimmy Vetayases 
1011cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_MSIMAP_TYPE		/* 0xA800 */	\
1012cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_MSIMAP_ID	<< PCI_HTCAP_TYPE_SHIFT)
1013cb7ea99dSJimmy Vetayases 
1014cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_DIRROUTE_TYPE		/* 0xB000 */	\
1015cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_DIRROUTE_ID	<< PCI_HTCAP_TYPE_SHIFT)
1016cb7ea99dSJimmy Vetayases 
1017cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_VCSET_TYPE		/* 0xB800 */	\
1018cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_VCSET_ID	<< PCI_HTCAP_TYPE_SHIFT)
1019cb7ea99dSJimmy Vetayases 
1020cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_RETRYMODE_TYPE	/* 0xC000 */	\
1021cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_RETRYMODE_ID	<< PCI_HTCAP_TYPE_SHIFT)
1022cb7ea99dSJimmy Vetayases 
1023cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_X86ENC_TYPE		/* 0xC800 */	\
1024cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_X86ENC_ID	<< PCI_HTCAP_TYPE_SHIFT)
1025cb7ea99dSJimmy Vetayases 
1026cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_GEN3_TYPE		/* 0xD000 */	\
1027cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_GEN3_ID	<< PCI_HTCAP_TYPE_SHIFT)
1028cb7ea99dSJimmy Vetayases 
1029cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_FUNCEXT_TYPE		/* 0xD800 */	\
1030cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_FUNCEXT_ID	<< PCI_HTCAP_TYPE_SHIFT)
1031cb7ea99dSJimmy Vetayases 
1032cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_PM_TYPE		/* 0xE000 */	\
1033cb7ea99dSJimmy Vetayases 	(PCI_HTCAP_PM_ID	<< PCI_HTCAP_TYPE_SHIFT)
1034cb7ea99dSJimmy Vetayases 
1035cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_MSIMAP_ENABLE			0x0001
1036cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_MSIMAP_ENABLE_MASK		0x0001
1037cb7ea99dSJimmy Vetayases 
1038cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_ADDRMAP_MAPTYPE_MASK		0x600
1039cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_ADDRMAP_MAPTYPE_SHIFT		9
1040cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_ADDRMAP_NUMMAP_MASK		0xF
1041cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_ADDRMAP_40BIT_ID		0x0
1042cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_ADDRMAP_64BIT_ID		0x1
1043cb7ea99dSJimmy Vetayases 
1044cb7ea99dSJimmy Vetayases #define	PCI_HTCAP_FUNCEXT_LEN_MASK		0xFF
1045cb7ea99dSJimmy Vetayases 
1046cb7ea99dSJimmy Vetayases 
10477c478bd9Sstevel@tonic-gate /*
10487c478bd9Sstevel@tonic-gate  * other interesting PCI constants
10497c478bd9Sstevel@tonic-gate  */
10507c478bd9Sstevel@tonic-gate #define	PCI_BASE_NUM	6	/* num of base regs in configuration header */
10517c478bd9Sstevel@tonic-gate #define	PCI_BAR_SZ_32	4	/* size of 32 bit base addr reg in bytes */
10527c478bd9Sstevel@tonic-gate #define	PCI_BAR_SZ_64	8	/* size of 64 bit base addr reg in bytes */
10537c478bd9Sstevel@tonic-gate #define	PCI_BASE_SIZE	4	/* size of base reg in bytes */
10547c478bd9Sstevel@tonic-gate #define	PCI_CONF_HDR_SIZE	256	/* configuration header size */
105570025d76Sjohnny #define	PCI_MAX_BUS_NUM		256		/* Maximum PCI buses allowed */
105669889278Sanish #define	PCI_MAX_DEVICES		32		/* Max PCI devices allowed */
105769889278Sanish #define	PCI_MAX_FUNCTIONS	8		/* Max PCI functions allowed */
105869889278Sanish #define	PCI_MAX_CHILDREN	PCI_MAX_DEVICES * PCI_MAX_FUNCTIONS
10597c478bd9Sstevel@tonic-gate #define	PCI_CLK_33MHZ	(33 * 1000 * 1000)	/* 33MHz clock speed */
10607c478bd9Sstevel@tonic-gate #define	PCI_CLK_66MHZ	(66 * 1000 * 1000)	/* 66MHz clock speed */
10617c478bd9Sstevel@tonic-gate #define	PCI_CLK_133MHZ	(133 * 1000 * 1000)	/* 133MHz clock speed */
10627c478bd9Sstevel@tonic-gate 
106300d0963fSdilpreet /*
106400d0963fSdilpreet  * pci bus range definition
106500d0963fSdilpreet  */
106600d0963fSdilpreet typedef struct pci_bus_range {
106700d0963fSdilpreet 	uint32_t lo;
106800d0963fSdilpreet 	uint32_t hi;
106900d0963fSdilpreet } pci_bus_range_t;
107000d0963fSdilpreet 
107100d0963fSdilpreet /*
107200d0963fSdilpreet  * The following typedef is used to represent an entry in the "ranges"
107300d0963fSdilpreet  * property of a pci hostbridge device node.
107400d0963fSdilpreet  */
107500d0963fSdilpreet typedef struct pci_ranges {
107600d0963fSdilpreet 	uint32_t child_high;
107700d0963fSdilpreet 	uint32_t child_mid;
107800d0963fSdilpreet 	uint32_t child_low;
107900d0963fSdilpreet 	uint32_t parent_high;
108000d0963fSdilpreet 	uint32_t parent_low;
108100d0963fSdilpreet 	uint32_t size_high;
108200d0963fSdilpreet 	uint32_t size_low;
108300d0963fSdilpreet } pci_ranges_t;
108400d0963fSdilpreet 
108500d0963fSdilpreet /*
108600d0963fSdilpreet  * The following typedef is used to represent an entry in the "ranges"
108700d0963fSdilpreet  * property of a pci-pci bridge device node.
108800d0963fSdilpreet  */
108900d0963fSdilpreet typedef struct {
109000d0963fSdilpreet 	uint32_t child_high;
109100d0963fSdilpreet 	uint32_t child_mid;
109200d0963fSdilpreet 	uint32_t child_low;
109300d0963fSdilpreet 	uint32_t parent_high;
109400d0963fSdilpreet 	uint32_t parent_mid;
109500d0963fSdilpreet 	uint32_t parent_low;
109600d0963fSdilpreet 	uint32_t size_high;
109700d0963fSdilpreet 	uint32_t size_low;
109800d0963fSdilpreet } ppb_ranges_t;
109900d0963fSdilpreet 
11007c478bd9Sstevel@tonic-gate /*
11017c478bd9Sstevel@tonic-gate  * This structure represents one entry of the 1275 "reg" property and
11027c478bd9Sstevel@tonic-gate  * "assigned-addresses" property for a PCI node.  For the "reg" property, it
11037c478bd9Sstevel@tonic-gate  * may be one of an arbitrary length array for devices with multiple address
11047c478bd9Sstevel@tonic-gate  * windows.  For the "assigned-addresses" property, it denotes an assigned
11057c478bd9Sstevel@tonic-gate  * physical address on the PCI bus.  It may be one entry of the six entries
11067c478bd9Sstevel@tonic-gate  * for devices with multiple base registers.
11077c478bd9Sstevel@tonic-gate  *
11087c478bd9Sstevel@tonic-gate  * The physical address format is:
11097c478bd9Sstevel@tonic-gate  *
11107c478bd9Sstevel@tonic-gate  *             Bit#:  33222222 22221111 11111100 00000000
11117c478bd9Sstevel@tonic-gate  *                    10987654 32109876 54321098 76543210
11127c478bd9Sstevel@tonic-gate  *
11133e98767bSMax zhen  * pci_phys_hi cell:  npt000ss bbbbbbbb dddddfff rrrrrrrr
11147c478bd9Sstevel@tonic-gate  * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
11157c478bd9Sstevel@tonic-gate  * pci_phys_low cell: llllllll llllllll llllllll llllllll
11167c478bd9Sstevel@tonic-gate  *
11177c478bd9Sstevel@tonic-gate  * n          is 0 if the address is relocatable, 1 otherwise
11187c478bd9Sstevel@tonic-gate  * p          is 1 if the addressable region is "prefetchable", 0 otherwise
11193e98767bSMax zhen  * t          is 1 if the address is aliased (for non-relocatable I/O), below
11203e98767bSMax zhen  *	      1MB (for mem), or below 64 KB (for relocatable I/O).
11213e98767bSMax zhen  * ss         is the type code, denoting which address space
11227c478bd9Sstevel@tonic-gate  * bbbbbbbb   is the 8-bit bus number
11237c478bd9Sstevel@tonic-gate  * ddddd      is the 5-bit device number
11247c478bd9Sstevel@tonic-gate  * fff        is the 3-bit function number
11257c478bd9Sstevel@tonic-gate  * rrrrrrrr   is the 8-bit register number
11263e98767bSMax zhen  *	      should be zero for non-relocatable, when ss is 01, or 10
11277c478bd9Sstevel@tonic-gate  * hh...hhh   is the 32-bit unsigned number
11287c478bd9Sstevel@tonic-gate  * ll...lll   is the 32-bit unsigned number
11297c478bd9Sstevel@tonic-gate  *
11307c478bd9Sstevel@tonic-gate  * The physical size format is:
11317c478bd9Sstevel@tonic-gate  *
11327c478bd9Sstevel@tonic-gate  * pci_size_hi cell:  hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
11337c478bd9Sstevel@tonic-gate  * pci_size_low cell: llllllll llllllll llllllll llllllll
11347c478bd9Sstevel@tonic-gate  *
11357c478bd9Sstevel@tonic-gate  * hh...hhh   is the 32-bit unsigned number
11367c478bd9Sstevel@tonic-gate  * ll...lll   is the 32-bit unsigned number
11377c478bd9Sstevel@tonic-gate  */
11387c478bd9Sstevel@tonic-gate struct pci_phys_spec {
11397c478bd9Sstevel@tonic-gate 	uint_t pci_phys_hi;		/* child's address, hi word */
11407c478bd9Sstevel@tonic-gate 	uint_t pci_phys_mid;		/* child's address, middle word */
11417c478bd9Sstevel@tonic-gate 	uint_t pci_phys_low;		/* child's address, low word */
11427c478bd9Sstevel@tonic-gate 	uint_t pci_size_hi;		/* high word of size field */
11437c478bd9Sstevel@tonic-gate 	uint_t pci_size_low;		/* low word of size field */
11447c478bd9Sstevel@tonic-gate };
11457c478bd9Sstevel@tonic-gate 
11467c478bd9Sstevel@tonic-gate typedef struct pci_phys_spec pci_regspec_t;
11477c478bd9Sstevel@tonic-gate 
11487c478bd9Sstevel@tonic-gate /*
11497c478bd9Sstevel@tonic-gate  * PCI masks for pci_phy_hi of PCI 1275 address cell.
11507c478bd9Sstevel@tonic-gate  */
11517c478bd9Sstevel@tonic-gate #define	PCI_REG_REG_M		0xff		/* register mask */
11527c478bd9Sstevel@tonic-gate #define	PCI_REG_FUNC_M		0x700		/* function mask */
11537c478bd9Sstevel@tonic-gate #define	PCI_REG_DEV_M		0xf800		/* device mask */
11547c478bd9Sstevel@tonic-gate #define	PCI_REG_BUS_M		0xff0000	/* bus number mask */
11557c478bd9Sstevel@tonic-gate #define	PCI_REG_ADDR_M		0x3000000	/* address space mask */
11567c478bd9Sstevel@tonic-gate #define	PCI_REG_ALIAS_M		0x20000000	/* aliased bit mask */
11577c478bd9Sstevel@tonic-gate #define	PCI_REG_PF_M		0x40000000	/* prefetch bit mask */
11587c478bd9Sstevel@tonic-gate #define	PCI_REG_REL_M		0x80000000	/* relocation bit mask */
11597c478bd9Sstevel@tonic-gate #define	PCI_REG_BDFR_M		0xffffff	/* bus, dev, func, reg mask */
116034d3f749Saa #define	PCI_REG_EXTREG_M	0xF0000000	/* extended config bits mask */
11617c478bd9Sstevel@tonic-gate 
11627c478bd9Sstevel@tonic-gate #define	PCI_REG_FUNC_SHIFT	8		/* Offset of function bits */
11637c478bd9Sstevel@tonic-gate #define	PCI_REG_DEV_SHIFT	11		/* Offset of device bits */
11647c478bd9Sstevel@tonic-gate #define	PCI_REG_BUS_SHIFT	16		/* Offset of bus bits */
11657c478bd9Sstevel@tonic-gate #define	PCI_REG_ADDR_SHIFT	24		/* Offset of address bits */
116634d3f749Saa #define	PCI_REG_EXTREG_SHIFT	28		/* Offset of ext. config bits */
11677c478bd9Sstevel@tonic-gate 
11687c478bd9Sstevel@tonic-gate #define	PCI_REG_REG_G(x)	((x) & PCI_REG_REG_M)
11697c478bd9Sstevel@tonic-gate #define	PCI_REG_FUNC_G(x)	(((x) & PCI_REG_FUNC_M) >> PCI_REG_FUNC_SHIFT)
11707c478bd9Sstevel@tonic-gate #define	PCI_REG_DEV_G(x)	(((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT)
11717c478bd9Sstevel@tonic-gate #define	PCI_REG_BUS_G(x)	(((x) & PCI_REG_BUS_M) >> PCI_REG_BUS_SHIFT)
11727c478bd9Sstevel@tonic-gate #define	PCI_REG_ADDR_G(x)	(((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT)
11737c478bd9Sstevel@tonic-gate #define	PCI_REG_BDFR_G(x)	((x) & PCI_REG_BDFR_M)
11747c478bd9Sstevel@tonic-gate 
11757c478bd9Sstevel@tonic-gate /*
11767c478bd9Sstevel@tonic-gate  * PCI bit encodings of pci_phys_hi of PCI 1275 address cell.
11777c478bd9Sstevel@tonic-gate  */
11787c478bd9Sstevel@tonic-gate #define	PCI_ADDR_MASK		PCI_REG_ADDR_M
11797c478bd9Sstevel@tonic-gate #define	PCI_ADDR_CONFIG		0x00000000	/* configuration address */
11807c478bd9Sstevel@tonic-gate #define	PCI_ADDR_IO		0x01000000	/* I/O address */
11817c478bd9Sstevel@tonic-gate #define	PCI_ADDR_MEM32		0x02000000	/* 32-bit memory address */
11827c478bd9Sstevel@tonic-gate #define	PCI_ADDR_MEM64		0x03000000	/* 64-bit memory address */
11837c478bd9Sstevel@tonic-gate #define	PCI_ALIAS_B		PCI_REG_ALIAS_M	/* aliased bit */
11847c478bd9Sstevel@tonic-gate #define	PCI_PREFETCH_B		PCI_REG_PF_M	/* prefetch bit */
11857c478bd9Sstevel@tonic-gate #define	PCI_RELOCAT_B		PCI_REG_REL_M	/* non-relocatable bit */
11867c478bd9Sstevel@tonic-gate #define	PCI_CONF_ADDR_MASK	0x00ffffff	/* mask for config address */
11877c478bd9Sstevel@tonic-gate 
11887c478bd9Sstevel@tonic-gate #define	PCI_HARDDEC_8514 2	/* number of reg entries for 8514 hard-decode */
11897c478bd9Sstevel@tonic-gate #define	PCI_HARDDEC_VGA	3	/* number of reg entries for VGA hard-decode */
11907c478bd9Sstevel@tonic-gate #define	PCI_HARDDEC_IDE	4	/* number of reg entries for IDE hard-decode */
11917c478bd9Sstevel@tonic-gate #define	PCI_HARDDEC_IDE_PRI 2	/* number of reg entries for IDE primary */
11927c478bd9Sstevel@tonic-gate #define	PCI_HARDDEC_IDE_SEC 2	/* number of reg entries for IDE secondary */
11937c478bd9Sstevel@tonic-gate 
11947c478bd9Sstevel@tonic-gate /*
11957c478bd9Sstevel@tonic-gate  * PCI Expansion ROM Header Format
11967c478bd9Sstevel@tonic-gate  */
11977c478bd9Sstevel@tonic-gate #define	PCI_ROM_SIGNATURE		0x0	/* ROM Signature 0xaa55 */
11987c478bd9Sstevel@tonic-gate #define	PCI_ROM_ARCH_UNIQUE_START	0x2	/* Start of processor unique */
11997c478bd9Sstevel@tonic-gate #define	PCI_ROM_PCI_DATA_STRUCT_PTR	0x18	/* Ptr to PCI Data Structure */
12007c478bd9Sstevel@tonic-gate 
12017c478bd9Sstevel@tonic-gate /*
12027c478bd9Sstevel@tonic-gate  * PCI Data Structure
12037c478bd9Sstevel@tonic-gate  *
12047c478bd9Sstevel@tonic-gate  * The PCI Data Structure is located within the first 64KB
12057c478bd9Sstevel@tonic-gate  * of the ROM image and must be DWORD aligned.
12067c478bd9Sstevel@tonic-gate  */
12077c478bd9Sstevel@tonic-gate #define	PCI_PDS_SIGNATURE	0x0	/* Signature, the string 'PCIR' */
12087c478bd9Sstevel@tonic-gate #define	PCI_PDS_VENDOR_ID	0x4	/* Vendor Identification */
12097c478bd9Sstevel@tonic-gate #define	PCI_PDS_DEVICE_ID	0x6	/* Device Identification */
12107c478bd9Sstevel@tonic-gate #define	PCI_PDS_VPD_PTR		0x8	/* Pointer to Vital Product Data */
12117c478bd9Sstevel@tonic-gate #define	PCI_PDS_PDS_LENGTH	0xa	/* PCI Data Structure Length */
12127c478bd9Sstevel@tonic-gate #define	PCI_PDS_PDS_REVISION	0xc	/* PCI Data Structure Revision */
12137c478bd9Sstevel@tonic-gate #define	PCI_PDS_CLASS_CODE	0xd	/* Class Code */
12147c478bd9Sstevel@tonic-gate #define	PCI_PDS_IMAGE_LENGTH	0x10	/* Image Length in 512 byte units */
12157c478bd9Sstevel@tonic-gate #define	PCI_PDS_CODE_REVISON	0x12	/* Revision Level of Code/Data */
12167c478bd9Sstevel@tonic-gate #define	PCI_PDS_CODE_TYPE	0x14	/* Code Type */
12177c478bd9Sstevel@tonic-gate #define	PCI_PDS_INDICATOR	0x15	/* Indicates if image is last in ROM */
12187c478bd9Sstevel@tonic-gate 
12197c478bd9Sstevel@tonic-gate #define	PCI_PDS_CODE_TYPE_PCAT		0x0	/* Intel x86/PC-AT Type */
12207c478bd9Sstevel@tonic-gate #define	PCI_PDS_CODE_TYPE_OPEN_FW	0x1	/* Open Firmware */
12217c478bd9Sstevel@tonic-gate 
12227c9e29aaSgovinda /*
12237c9e29aaSgovinda  * we recognize the non transparent bridge child nodes with the
12247c9e29aaSgovinda  * following property. This is specific to an implementation only.
12257c9e29aaSgovinda  * This property is specific to AP nodes only.
12267c9e29aaSgovinda  */
12277c9e29aaSgovinda #define	PCI_DEV_CONF_MAP_PROP	"pci-parent-indirect"
12287c9e29aaSgovinda 
12297c9e29aaSgovinda /*
12307c9e29aaSgovinda  * If a bridge device provides its own config space access services,
12317c9e29aaSgovinda  * and supports a hotplug/hotswap bus below at any level, then
12327c9e29aaSgovinda  * the following property must be defined for the node either by
12337c9e29aaSgovinda  * the driver or the OBP.
12347c9e29aaSgovinda  */
12357c9e29aaSgovinda #define	PCI_BUS_CONF_MAP_PROP	"pci-conf-indirect"
12367c9e29aaSgovinda 
12377c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
12387c478bd9Sstevel@tonic-gate }
12397c478bd9Sstevel@tonic-gate #endif
12407c478bd9Sstevel@tonic-gate 
12417c478bd9Sstevel@tonic-gate #endif	/* _SYS_PCI_H */
1242