17c478bdstevel@tonic-gate/*
27c478bdstevel@tonic-gate * CDDL HEADER START
37c478bdstevel@tonic-gate *
47c478bdstevel@tonic-gate * The contents of this file are subject to the terms of the
500d0963dilpreet * Common Development and Distribution License (the "License").
600d0963dilpreet * You may not use this file except in compliance with the License.
77c478bdstevel@tonic-gate *
87c478bdstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bdstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bdstevel@tonic-gate * See the License for the specific language governing permissions
117c478bdstevel@tonic-gate * and limitations under the License.
127c478bdstevel@tonic-gate *
137c478bdstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bdstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bdstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bdstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bdstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bdstevel@tonic-gate *
197c478bdstevel@tonic-gate * CDDL HEADER END
207c478bdstevel@tonic-gate */
217c478bdstevel@tonic-gate/*
22fb66942Casper H.S. Dik * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
237c478bdstevel@tonic-gate * Use is subject to license terms.
2433756aeRobert Mustacchi * Copyright 2019, Joyent, Inc.
257c478bdstevel@tonic-gate */
267c478bdstevel@tonic-gate
277c478bdstevel@tonic-gate#ifndef	_SYS_PCI_H
287c478bdstevel@tonic-gate#define	_SYS_PCI_H
297c478bdstevel@tonic-gate
307c478bdstevel@tonic-gate#ifdef	__cplusplus
317c478bdstevel@tonic-gateextern "C" {
327c478bdstevel@tonic-gate#endif
337c478bdstevel@tonic-gate
347c478bdstevel@tonic-gate/*
357c478bdstevel@tonic-gate * PCI Configuration Header offsets
367c478bdstevel@tonic-gate */
377c478bdstevel@tonic-gate#define	PCI_CONF_VENID		0x0	/* vendor id, 2 bytes */
387c478bdstevel@tonic-gate#define	PCI_CONF_DEVID		0x2	/* device id, 2 bytes */
397c478bdstevel@tonic-gate#define	PCI_CONF_COMM		0x4	/* command register, 2 bytes */
407c478bdstevel@tonic-gate#define	PCI_CONF_STAT		0x6	/* status register, 2 bytes */
417c478bdstevel@tonic-gate#define	PCI_CONF_REVID		0x8	/* revision id, 1 byte */
427c478bdstevel@tonic-gate#define	PCI_CONF_PROGCLASS	0x9	/* programming class code, 1 byte */
437c478bdstevel@tonic-gate#define	PCI_CONF_SUBCLASS	0xA	/* sub-class code, 1 byte */
447c478bdstevel@tonic-gate#define	PCI_CONF_BASCLASS	0xB	/* basic class code, 1 byte */
457c478bdstevel@tonic-gate#define	PCI_CONF_CACHE_LINESZ	0xC	/* cache line size, 1 byte */
467c478bdstevel@tonic-gate#define	PCI_CONF_LATENCY_TIMER	0xD	/* latency timer, 1 byte */
477c478bdstevel@tonic-gate#define	PCI_CONF_HEADER		0xE	/* header type, 1 byte */
487c478bdstevel@tonic-gate#define	PCI_CONF_BIST		0xF	/* builtin self test, 1 byte */
497c478bdstevel@tonic-gate
507c478bdstevel@tonic-gate/*
517c478bdstevel@tonic-gate * Header type 0 offsets
527c478bdstevel@tonic-gate */
537c478bdstevel@tonic-gate#define	PCI_CONF_BASE0		0x10	/* base register 0, 4 bytes */
547c478bdstevel@tonic-gate#define	PCI_CONF_BASE1		0x14	/* base register 1, 4 bytes */
557c478bdstevel@tonic-gate#define	PCI_CONF_BASE2		0x18	/* base register 2, 4 bytes */
567c478bdstevel@tonic-gate#define	PCI_CONF_BASE3		0x1c	/* base register 3, 4 bytes */
577c478bdstevel@tonic-gate#define	PCI_CONF_BASE4		0x20	/* base register 4, 4 bytes */
587c478bdstevel@tonic-gate#define	PCI_CONF_BASE5		0x24	/* base register 5, 4 bytes */
597c478bdstevel@tonic-gate#define	PCI_CONF_CIS		0x28	/* Cardbus CIS Pointer */
607c478bdstevel@tonic-gate#define	PCI_CONF_SUBVENID	0x2c	/* Subsystem Vendor ID */
617c478bdstevel@tonic-gate#define	PCI_CONF_SUBSYSID	0x2e	/* Subsystem ID */
627c478bdstevel@tonic-gate#define	PCI_CONF_ROM		0x30	/* ROM base register, 4 bytes */
637c478bdstevel@tonic-gate#define	PCI_CONF_CAP_PTR	0x34	/* capabilities pointer, 1 byte */
647c478bdstevel@tonic-gate#define	PCI_CONF_ILINE		0x3c	/* interrupt line, 1 byte */
657c478bdstevel@tonic-gate#define	PCI_CONF_IPIN		0x3d	/* interrupt pin, 1 byte */
667c478bdstevel@tonic-gate#define	PCI_CONF_MIN_G		0x3e	/* minimum grant, 1 byte */
677c478bdstevel@tonic-gate#define	PCI_CONF_MAX_L		0x3f	/* maximum grant, 1 byte */
687c478bdstevel@tonic-gate
697c478bdstevel@tonic-gate/*
707c478bdstevel@tonic-gate * PCI to PCI bridge configuration space header format
717c478bdstevel@tonic-gate */
727c478bdstevel@tonic-gate#define	PCI_BCNF_PRIBUS		0x18	/* primary bus number */
737c478bdstevel@tonic-gate#define	PCI_BCNF_SECBUS		0x19	/* secondary bus number */
747c478bdstevel@tonic-gate#define	PCI_BCNF_SUBBUS		0x1a	/* subordinate bus number */
757c478bdstevel@tonic-gate#define	PCI_BCNF_LATENCY_TIMER	0x1b
767c478bdstevel@tonic-gate#define	PCI_BCNF_IO_BASE_LOW	0x1c
777c478bdstevel@tonic-gate#define	PCI_BCNF_IO_LIMIT_LOW	0x1d
787c478bdstevel@tonic-gate#define	PCI_BCNF_SEC_STATUS	0x1e
797c478bdstevel@tonic-gate#define	PCI_BCNF_MEM_BASE	0x20
807c478bdstevel@tonic-gate#define	PCI_BCNF_MEM_LIMIT	0x22
817c478bdstevel@tonic-gate#define	PCI_BCNF_PF_BASE_LOW	0x24
827c478bdstevel@tonic-gate#define	PCI_BCNF_PF_LIMIT_LOW	0x26
837c478bdstevel@tonic-gate#define	PCI_BCNF_PF_BASE_HIGH	0x28
847c478bdstevel@tonic-gate#define	PCI_BCNF_PF_LIMIT_HIGH	0x2c
857c478bdstevel@tonic-gate#define	PCI_BCNF_IO_BASE_HI	0x30
867c478bdstevel@tonic-gate#define	PCI_BCNF_IO_LIMIT_HI	0x32
877c478bdstevel@tonic-gate#define	PCI_BCNF_CAP_PTR	0x34
887c478bdstevel@tonic-gate#define	PCI_BCNF_ROM		0x38
897c478bdstevel@tonic-gate#define	PCI_BCNF_ILINE		0x3c
907c478bdstevel@tonic-gate#define	PCI_BCNF_IPIN		0x3d
917c478bdstevel@tonic-gate#define	PCI_BCNF_BCNTRL		0x3e
927c478bdstevel@tonic-gate
937c478bdstevel@tonic-gate#define	PCI_BCNF_BASE_NUM	0x2
947c478bdstevel@tonic-gate
957c478bdstevel@tonic-gate/*
967c478bdstevel@tonic-gate * PCI to PCI bridge control register (0x3e) format
977c478bdstevel@tonic-gate */
987c478bdstevel@tonic-gate#define	PCI_BCNF_BCNTRL_PARITY_ENABLE	0x1
997c478bdstevel@tonic-gate#define	PCI_BCNF_BCNTRL_SERR_ENABLE	0x2
100eae2e50krishnae#define	PCI_BCNF_BCNTRL_ISA_ENABLE	0x4
1014e93fb0rugrat#define	PCI_BCNF_BCNTRL_VGA_ENABLE	0x8
1027c478bdstevel@tonic-gate#define	PCI_BCNF_BCNTRL_MAST_AB_MODE	0x20
1037c478bdstevel@tonic-gate#define	PCI_BCNF_BCNTRL_DTO_STAT	0x400
1047c478bdstevel@tonic-gate
105a9fb0aerw#define	PCI_BCNF_BCNTRL_RESET		0x0040
106a9fb0aerw#define	PCI_BCNF_BCNTRL_B2B_ENAB	0x0080
107a9fb0aerw
1087c478bdstevel@tonic-gate#define	PCI_BCNF_IO_MASK	0xf0
1091f0c5e6Robert Mustacchi#define	PCI_BCNF_IO_SHIFT	8
1107c478bdstevel@tonic-gate#define	PCI_BCNF_MEM_MASK	0xfff0
1111f0c5e6Robert Mustacchi#define	PCI_BCNF_MEM_SHIFT	16
1121f0c5e6Robert Mustacchi#define	PCI_BCNF_ADDR_MASK	0x000f
1131f0c5e6Robert Mustacchi
1141f0c5e6Robert Mustacchi#define	PCI_BCNF_IO_32BIT	0x01
1151f0c5e6Robert Mustacchi#define	PCI_BCNF_PF_MEM_64BIT	0x01
1167c478bdstevel@tonic-gate
1177c478bdstevel@tonic-gate/*
1187c478bdstevel@tonic-gate * Header type 2 (Cardbus) offsets
1197c478bdstevel@tonic-gate */
1207c478bdstevel@tonic-gate#define	PCI_CBUS_SOCK_REG	0x10	/* Cardbus socket regs, 4 bytes */
121fb66942Casper H.S. Dik#define	PCI_CBUS_CAP_PTR	0x14	/* Capability ptr, 1 byte */
122fb66942Casper H.S. Dik#define	PCI_CBUS_RESERVED1	0x15	/* Reserved, 1 byte */
1237c478bdstevel@tonic-gate#define	PCI_CBUS_SEC_STATUS	0x16	/* Secondary status, 2 bytes */
1247c478bdstevel@tonic-gate#define	PCI_CBUS_PCI_BUS_NO	0x18	/* PCI bus number, 1 byte */
1257c478bdstevel@tonic-gate#define	PCI_CBUS_CBUS_NO	0x19	/* Cardbus bus number, 1 byte */
1267c478bdstevel@tonic-gate#define	PCI_CBUS_SUB_BUS_NO	0x1a	/* Subordinate bus number, 1 byte */
1277c478bdstevel@tonic-gate#define	PCI_CBUS_LATENCY_TIMER	0x1b	/* Cardbus latency timer, 1 byte */
1287c478bdstevel@tonic-gate#define	PCI_CBUS_MEM_BASE0	0x1c	/* Memory base reg 0, 4 bytes */
1297c478bdstevel@tonic-gate#define	PCI_CBUS_MEM_LIMIT0	0x20	/* Memory limit reg 0, 4 bytes */
1307c478bdstevel@tonic-gate#define	PCI_CBUS_MEM_BASE1	0x24	/* Memory base reg 1, 4 bytes */
1317c478bdstevel@tonic-gate#define	PCI_CBUS_MEM_LIMIT1	0x28	/* Memory limit reg 1, 4 bytes */
1327c478bdstevel@tonic-gate#define	PCI_CBUS_IO_BASE0	0x2c	/* IO base reg 0, 4 bytes */
1337c478bdstevel@tonic-gate#define	PCI_CBUS_IO_LIMIT0	0x30	/* IO limit reg 0, 4 bytes */
1347c478bdstevel@tonic-gate#define	PCI_CBUS_IO_BASE1	0x34	/* IO base reg 1, 4 bytes */
1357c478bdstevel@tonic-gate#define	PCI_CBUS_IO_LIMIT1	0x38	/* IO limit reg 1, 4 bytes */
1367c478bdstevel@tonic-gate#define	PCI_CBUS_ILINE		0x3c	/* interrupt line, 1 byte */
1377c478bdstevel@tonic-gate#define	PCI_CBUS_IPIN		0x3d	/* interrupt pin, 1 byte */
1387c478bdstevel@tonic-gate#define	PCI_CBUS_BRIDGE_CTRL	0x3e	/* Bridge control, 2 bytes */
1397c478bdstevel@tonic-gate#define	PCI_CBUS_SUBVENID	0x40	/* Subsystem Vendor ID, 2 bytes */
1407c478bdstevel@tonic-gate#define	PCI_CBUS_SUBSYSID	0x42	/* Subsystem ID, 2 bytes */
1417c478bdstevel@tonic-gate#define	PCI_CBUS_LEG_MODE_ADDR	0x44	/* PCCard 16bit IF legacy mode addr */
1427c478bdstevel@tonic-gate
1437c478bdstevel@tonic-gate#define	PCI_CBUS_BASE_NUM	0x1	/* number of base registers */
1447c478bdstevel@tonic-gate
1457c478bdstevel@tonic-gate/*
1467c478bdstevel@tonic-gate * PCI command register bits
1477c478bdstevel@tonic-gate */
1487c478bdstevel@tonic-gate#define	PCI_COMM_IO		0x1	/* I/O access enable */
1497c478bdstevel@tonic-gate#define	PCI_COMM_MAE		0x2	/* memory access enable */
1507c478bdstevel@tonic-gate#define	PCI_COMM_ME		0x4	/* master enable */
1517c478bdstevel@tonic-gate#define	PCI_COMM_SPEC_CYC	0x8
1527c478bdstevel@tonic-gate#define	PCI_COMM_MEMWR_INVAL	0x10
1537c478bdstevel@tonic-gate#define	PCI_COMM_PALETTE_SNOOP	0x20
1547c478bdstevel@tonic-gate#define	PCI_COMM_PARITY_DETECT	0x40
1557c478bdstevel@tonic-gate#define	PCI_COMM_WAIT_CYC_ENAB	0x80
1567c478bdstevel@tonic-gate#define	PCI_COMM_SERR_ENABLE	0x100
1577c478bdstevel@tonic-gate#define	PCI_COMM_BACK2BACK_ENAB	0x200
1587c478bdstevel@tonic-gate#define	PCI_COMM_INTX_DISABLE	0x400	/* INTx emulation disable */
1597c478bdstevel@tonic-gate
1607c478bdstevel@tonic-gate/*
1617c478bdstevel@tonic-gate * PCI Interrupt pin value
1627c478bdstevel@tonic-gate */
1637c478bdstevel@tonic-gate#define	PCI_INTA	1
1647c478bdstevel@tonic-gate#define	PCI_INTB	2
1657c478bdstevel@tonic-gate#define	PCI_INTC	3
1667c478bdstevel@tonic-gate#define	PCI_INTD	4
1677c478bdstevel@tonic-gate
1687c478bdstevel@tonic-gate/*
1697c478bdstevel@tonic-gate * PCI status register bits
1707c478bdstevel@tonic-gate */
17133756aeRobert Mustacchi#define	PCI_STAT_READY		0x1	/* Immediate Readiness */
1727c478bdstevel@tonic-gate#define	PCI_STAT_INTR		0x8	/* Interrupt state */
1737c478bdstevel@tonic-gate#define	PCI_STAT_CAP		0x10	/* Implements Capabilities */
1747c478bdstevel@tonic-gate#define	PCI_STAT_66MHZ		0x20	/* 66 MHz capable */
1757c478bdstevel@tonic-gate#define	PCI_STAT_UDF		0x40	/* UDF supported */
1767c478bdstevel@tonic-gate#define	PCI_STAT_FBBC		0x80	/* Fast Back-to-Back Capable */
1777c478bdstevel@tonic-gate#define	PCI_STAT_S_PERROR	0x100	/* Data Parity Reported */
1787c478bdstevel@tonic-gate#define	PCI_STAT_DEVSELT	0x600	/* Device select timing */
1797c478bdstevel@tonic-gate#define	PCI_STAT_S_TARG_AB	0x800	/* Signaled Target Abort */
1807c478bdstevel@tonic-gate#define	PCI_STAT_R_TARG_AB	0x1000	/* Received Target Abort */
1817c478bdstevel@tonic-gate#define	PCI_STAT_R_MAST_AB	0x2000	/* Received Master Abort */
1827c478bdstevel@tonic-gate#define	PCI_STAT_S_SYSERR	0x4000	/* Signaled System Error */
1837c478bdstevel@tonic-gate#define	PCI_STAT_PERROR		0x8000	/* Detected Parity Error */
1847c478bdstevel@tonic-gate
1857c478bdstevel@tonic-gate/*
1867c478bdstevel@tonic-gate * DEVSEL timing values
1877c478bdstevel@tonic-gate */
1887c478bdstevel@tonic-gate#define	PCI_STAT_DEVSELT_FAST	0x0000
1897c478bdstevel@tonic-gate#define	PCI_STAT_DEVSELT_MEDIUM	0x0200
1907c478bdstevel@tonic-gate#define	PCI_STAT_DEVSELT_SLOW	0x0400
1917c478bdstevel@tonic-gate
1927c478bdstevel@tonic-gate/*
1937c478bdstevel@tonic-gate * BIST values
1947c478bdstevel@tonic-gate */
1957c478bdstevel@tonic-gate#define	PCI_BIST_SUPPORTED	0x80
1967c478bdstevel@tonic-gate#define	PCI_BIST_GO		0x40
1977c478bdstevel@tonic-gate#define	PCI_BIST_RESULT_M	0x0f
1987c478bdstevel@tonic-gate#define	PCI_BIST_RESULT_OK	0x00
1997c478bdstevel@tonic-gate
2007c478bdstevel@tonic-gate/*
2017c478bdstevel@tonic-gate * PCI class codes
2027c478bdstevel@tonic-gate */
2037c478bdstevel@tonic-gate#define	PCI_CLASS_NONE		0x0	/* class code for pre-2.0 devices */
2047c478bdstevel@tonic-gate#define	PCI_CLASS_MASS		0x1	/* Mass storage Controller class */
2057c478bdstevel@tonic-gate#define	PCI_CLASS_NET		0x2	/* Network Controller class */
2067c478bdstevel@tonic-gate#define	PCI_CLASS_DISPLAY	0x3	/* Display Controller class */
2077c478bdstevel@tonic-gate#define	PCI_CLASS_MM		0x4	/* Multimedia Controller class */
2087c478bdstevel@tonic-gate#define	PCI_CLASS_MEM		0x5	/* Memory Controller class */
2097c478bdstevel@tonic-gate#define	PCI_CLASS_BRIDGE	0x6	/* Bridge Controller class */
2107c478bdstevel@tonic-gate#define	PCI_CLASS_COMM		0x7	/* Communications Controller class */
2117c478bdstevel@tonic-gate#define	PCI_CLASS_PERIPH	0x8	/* Peripheral Controller class */
2127c478bdstevel@tonic-gate#define	PCI_CLASS_INPUT		0x9	/* Input Device class */
2137c478bdstevel@tonic-gate#define	PCI_CLASS_DOCK		0xa	/* Docking Station class */
2147c478bdstevel@tonic-gate#define	PCI_CLASS_PROCESSOR	0xb	/* Processor class */
2157c478bdstevel@tonic-gate#define	PCI_CLASS_SERIALBUS	0xc	/* Serial Bus class */
2167c478bdstevel@tonic-gate#define	PCI_CLASS_WIRELESS	0xd	/* Wireless Controller class */
2177c478bdstevel@tonic-gate#define	PCI_CLASS_INTIO		0xe	/* Intelligent IO Controller class */
2187c478bdstevel@tonic-gate#define	PCI_CLASS_SATELLITE	0xf	/* Satellite Communication class */
2197c478bdstevel@tonic-gate#define	PCI_CLASS_CRYPT		0x10	/* Encrytion/Decryption class */
2207c478bdstevel@tonic-gate#define	PCI_CLASS_SIGNAL	0x11	/* Signal Processing class */
2217c478bdstevel@tonic-gate
2227c478bdstevel@tonic-gate/*
2237c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x0 (no new devices should use this code).
2247c478bdstevel@tonic-gate */
2257c478bdstevel@tonic-gate#define	PCI_NONE_NOTVGA		0x0	/* All devices except VGA compatible */
2267c478bdstevel@tonic-gate#define	PCI_NONE_VGA		0x1	/* VGA compatible */
2277c478bdstevel@tonic-gate
2287c478bdstevel@tonic-gate/*
2297c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x1 (mass storage controllers)
2307c478bdstevel@tonic-gate */
2317c478bdstevel@tonic-gate#define	PCI_MASS_SCSI		0x0	/* SCSI bus Controller */
2327c478bdstevel@tonic-gate#define	PCI_MASS_IDE		0x1	/* IDE Controller */
233337fc9eanish#define	PCI_MASS_FD		0x2	/* Floppy disk Controller */
2347c478bdstevel@tonic-gate#define	PCI_MASS_IPI		0x3	/* IPI bus Controller */
2357c478bdstevel@tonic-gate#define	PCI_MASS_RAID		0x4	/* RAID Controller */
2367c478bdstevel@tonic-gate#define	PCI_MASS_ATA		0x5	/* ATA Controller */
2377c478bdstevel@tonic-gate#define	PCI_MASS_SATA		0x6	/* Serial ATA */
238337fc9eanish#define	PCI_MASS_SAS		0x7	/* Serial Attached SCSI (SAS) Cntrlr */
239b1b1835Toomas Soome#define	PCI_MASS_NVME		0x8	/* Non-Volatile memory controller */
2407c478bdstevel@tonic-gate#define	PCI_MASS_OTHER		0x80	/* Other Mass Storage Controller */
2417c478bdstevel@tonic-gate
2427c478bdstevel@tonic-gate/*
2437c478bdstevel@tonic-gate * programming interface for IDE (subclass 1)
2447c478bdstevel@tonic-gate */
2457c478bdstevel@tonic-gate#define	PCI_IDE_IF_NATIVE_PRI	0x1	/* primary channel is native */
2467c478bdstevel@tonic-gate#define	PCI_IDE_IF_PROG_PRI	0x2	/* primary can operate in either mode */
2477c478bdstevel@tonic-gate#define	PCI_IDE_IF_NATIVE_SEC	0x4	/* secondary channel is native */
2487c478bdstevel@tonic-gate#define	PCI_IDE_IF_PROG_SEC	0x8	/* sec. can operate in either mode */
2497c478bdstevel@tonic-gate#define	PCI_IDE_IF_MASK		0xf	/* programming interface mask */
2507c478bdstevel@tonic-gate
2517c478bdstevel@tonic-gate
2527c478bdstevel@tonic-gate/*
2537c478bdstevel@tonic-gate * programming interface for ATA (subclass 5)
2547c478bdstevel@tonic-gate */
2557c478bdstevel@tonic-gate#define	PCI_ATA_IF_SINGLE_DMA	0x20	/* ATA controller with single DMA */
2567c478bdstevel@tonic-gate#define	PCI_ATA_IF_CHAINED_DMA	0x30	/* ATA controller with chained DMA */
2577c478bdstevel@tonic-gate
2587c478bdstevel@tonic-gate/*
259337fc9eanish * programming interface for ATA (subclass 6) for SATA
260337fc9eanish */
261337fc9eanish#define	PCI_SATA_VS_INTERFACE	0x0	/* SATA Ctlr Vendor Specific Intfc */
262337fc9eanish#define	PCI_SATA_AHCI_INTERFACE	0x1	/* SATA Ctlr AHCI 1.0 Interface */
263337fc9eanish#define	PCI_SATA_SSB_INTERFACE	0x2	/* Serial Storage Bus Interface */
264337fc9eanish
265337fc9eanish/*
266337fc9eanish * programming interface for ATA (subclass 7) for SAS
267337fc9eanish */
268337fc9eanish#define	PCI_SAS_CONTROLLER	0x0	/* SAS Controller */
269337fc9eanish#define	PCI_SAS_BUS_INTERFACE	0x1	/* Serial Storage Bus Interface */
270337fc9eanish
271337fc9eanish/*
2727c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x2 (Network controllers)
2737c478bdstevel@tonic-gate */
2747c478bdstevel@tonic-gate#define	PCI_NET_ENET		0x0	/* Ethernet Controller */
2757c478bdstevel@tonic-gate#define	PCI_NET_TOKEN		0x1	/* Token Ring Controller */
2767c478bdstevel@tonic-gate#define	PCI_NET_FDDI		0x2	/* FDDI Controller */
2777c478bdstevel@tonic-gate#define	PCI_NET_ATM		0x3	/* ATM Controller */
2787c478bdstevel@tonic-gate#define	PCI_NET_ISDN		0x4	/* ISDN Controller */
2797c478bdstevel@tonic-gate#define	PCI_NET_WFIP		0x5	/* WorldFip Controller */
2807c478bdstevel@tonic-gate#define	PCI_NET_PICMG		0x6	/* PICMG 2.14 Multi Computing */
2817c478bdstevel@tonic-gate#define	PCI_NET_OTHER		0x80	/* Other Network Controller */
2827c478bdstevel@tonic-gate
2837c478bdstevel@tonic-gate/*
2847c478bdstevel@tonic-gate * PCI Sub-class codes - base class 03 (display controllers)
2857c478bdstevel@tonic-gate */
2867c478bdstevel@tonic-gate#define	PCI_DISPLAY_VGA		0x0	/* VGA device */
2877c478bdstevel@tonic-gate#define	PCI_DISPLAY_XGA		0x1	/* XGA device */
2887c478bdstevel@tonic-gate#define	PCI_DISPLAY_3D		0x2	/* 3D controller */
2897c478bdstevel@tonic-gate#define	PCI_DISPLAY_OTHER	0x80	/* Other Display Device */
2907c478bdstevel@tonic-gate
2917c478bdstevel@tonic-gate/*
2927c478bdstevel@tonic-gate * programming interface for display for display class (subclass 0) VGA ctrlrs
2937c478bdstevel@tonic-gate */
2947c478bdstevel@tonic-gate#define	PCI_DISPLAY_IF_VGA	0x0	/* VGA compatible */
2957c478bdstevel@tonic-gate#define	PCI_DISPLAY_IF_8514	0x1	/* 8514 compatible */
2967c478bdstevel@tonic-gate
2977c478bdstevel@tonic-gate/*
2987c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x4 (multi-media devices)
2997c478bdstevel@tonic-gate */
3007c478bdstevel@tonic-gate#define	PCI_MM_VIDEO		0x0	/* Video device */
3017c478bdstevel@tonic-gate#define	PCI_MM_AUDIO		0x1	/* Audio device */
3027c478bdstevel@tonic-gate#define	PCI_MM_TELEPHONY	0x2	/* Computer Telephony device */
303337fc9eanish#define	PCI_MM_MIXED_MODE	0x3	/* Mixed Mode device */
3047c478bdstevel@tonic-gate#define	PCI_MM_OTHER		0x80	/* Other Multimedia Device */
3057c478bdstevel@tonic-gate
3067c478bdstevel@tonic-gate/*
3077c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x5 (memory controllers)
3087c478bdstevel@tonic-gate */
3097c478bdstevel@tonic-gate#define	PCI_MEM_RAM		0x0	/* RAM device */
3107c478bdstevel@tonic-gate#define	PCI_MEM_FLASH		0x1	/* FLASH device */
3117c478bdstevel@tonic-gate#define	PCI_MEM_OTHER		0x80	/* Other Memory Controller */
3127c478bdstevel@tonic-gate
3137c478bdstevel@tonic-gate/*
3147c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x6 (Bridge devices)
3157c478bdstevel@tonic-gate */
3167c478bdstevel@tonic-gate#define	PCI_BRIDGE_HOST		0x0	/* Host/PCI Bridge */
3177c478bdstevel@tonic-gate#define	PCI_BRIDGE_ISA		0x1	/* PCI/ISA Bridge */
3187c478bdstevel@tonic-gate#define	PCI_BRIDGE_EISA		0x2	/* PCI/EISA Bridge */
3197c478bdstevel@tonic-gate#define	PCI_BRIDGE_MC		0x3	/* PCI/MC Bridge */
3207c478bdstevel@tonic-gate#define	PCI_BRIDGE_PCI		0x4	/* PCI/PCI Bridge */
3217c478bdstevel@tonic-gate#define	PCI_BRIDGE_PCMCIA	0x5	/* PCI/PCMCIA Bridge */
3227c478bdstevel@tonic-gate#define	PCI_BRIDGE_NUBUS	0x6	/* PCI/NUBUS Bridge */
3237c478bdstevel@tonic-gate#define	PCI_BRIDGE_CARDBUS	0x7	/* PCI/CARDBUS Bridge */
3247c478bdstevel@tonic-gate#define	PCI_BRIDGE_RACE		0x8	/* RACE-way Bridge */
3257c478bdstevel@tonic-gate#define	PCI_BRIDGE_STPCI	0x9	/* Semi-transparent PCI/PCI Bridge */
3267c478bdstevel@tonic-gate#define	PCI_BRIDGE_IB		0xA	/* InfiniBand/PCI host Bridge */
327337fc9eanish#define	PCI_BRIDGE_AS		0xB	/* AS/PCI host Bridge */
3287c478bdstevel@tonic-gate#define	PCI_BRIDGE_OTHER	0x80	/* PCI/Other Bridge Device */
3297c478bdstevel@tonic-gate
3307c478bdstevel@tonic-gate/*
3317c478bdstevel@tonic-gate * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
3327c478bdstevel@tonic-gate */
3337c478bdstevel@tonic-gate#define	PCI_BRIDGE_PCI_IF_PCI2PCI	0x0	/* PCI-PCI bridge */
3347c478bdstevel@tonic-gate#define	PCI_BRIDGE_PCI_IF_SUBDECODE	0x1	/* Subtractive Decode */
3357c478bdstevel@tonic-gate						/* PCI/PCI bridge */
3367c478bdstevel@tonic-gate
3377c478bdstevel@tonic-gate/*
3387c478bdstevel@tonic-gate * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge
3397c478bdstevel@tonic-gate */
3407c478bdstevel@tonic-gate#define	PCI_BRIDGE_RACE_IF_TRANSPARENT	0x0	/* Transport mode */
3417c478bdstevel@tonic-gate#define	PCI_BRIDGE_RACE_IF_ENDPOINT	0x1	/* Endpoint mode */
3427c478bdstevel@tonic-gate
3437c478bdstevel@tonic-gate/*
3447c478bdstevel@tonic-gate * programming interface for Bridges class 0x6 (subclass 09)
3457c478bdstevel@tonic-gate * Semi-transparent PCI-to-PCI bridge
3467c478bdstevel@tonic-gate */
3477c478bdstevel@tonic-gate#define	PCI_BRIDGE_STPCI_IF_PRIMARY	0x40	/* primary PCI side bus */
3487c478bdstevel@tonic-gate						/* facing system processor */
3497c478bdstevel@tonic-gate#define	PCI_BRIDGE_STPCI_IF_SECONDARY	0x80	/* secondary PCI side bus */
3507c478bdstevel@tonic-gate						/* facing system processor */
3517c478bdstevel@tonic-gate
3527c478bdstevel@tonic-gate/*
353337fc9eanish * programming interface for Bridges class 0x6 (subclass 0B) AS bridge
354337fc9eanish */
355337fc9eanish#define	PCI_BRIDGE_AS_CUSTOM_INTFC	0x0	/* Custom interface */
356337fc9eanish#define	PCI_BRIDGE_AS_PORTAL_INTFC	0x1	/* ASI-SIG Portal Interface */
357337fc9eanish
358337fc9eanish/*
3597c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x7 (communication devices)
3607c478bdstevel@tonic-gate */
3617c478bdstevel@tonic-gate#define	PCI_COMM_GENERIC_XT	0x0	/* XT Compatible Serial Controller */
3627c478bdstevel@tonic-gate#define	PCI_COMM_PARALLEL	0x1	/* Parallel Port Controller */
3637c478bdstevel@tonic-gate#define	PCI_COMM_MSC		0x2	/* Multiport Serial Controller */
3647c478bdstevel@tonic-gate#define	PCI_COMM_MODEM		0x3	/* Modem Controller */
3657c478bdstevel@tonic-gate#define	PCI_COMM_GPIB		0x4	/* GPIB Controller */
3667c478bdstevel@tonic-gate#define	PCI_COMM_SMARTCARD	0x5	/* Smart Card Controller */
3677c478bdstevel@tonic-gate#define	PCI_COMM_OTHER		0x80	/* Other Communications Controller */
3687c478bdstevel@tonic-gate
3697c478bdstevel@tonic-gate/*
3707c478bdstevel@tonic-gate * Programming interfaces for class 0x7 / subclass 0x0 (Serial)
3717c478bdstevel@tonic-gate */
3727c478bdstevel@tonic-gate#define	PCI_COMM_SERIAL_IF_GENERIC	0x0	/* Generic XT-compat serial */
3737c478bdstevel@tonic-gate#define	PCI_COMM_SERIAL_IF_16450	0x1	/* 16450-compat serial ctrlr */
3747c478bdstevel@tonic-gate#define	PCI_COMM_SERIAL_IF_16550	0x2	/* 16550-compat serial ctrlr */
3757c478bdstevel@tonic-gate#define	PCI_COMM_SERIAL_IF_16650	0x3	/* 16650-compat serial ctrlr */
3767c478bdstevel@tonic-gate#define	PCI_COMM_SERIAL_IF_16750	0x4	/* 16750-compat serial ctrlr */
3777c478bdstevel@tonic-gate#define	PCI_COMM_SERIAL_IF_16850	0x5	/* 16850-compat serial ctrlr */
3787c478bdstevel@tonic-gate#define	PCI_COMM_SERIAL_IF_16950	0x6	/* 16950-compat serial ctrlr */
3797c478bdstevel@tonic-gate
3807c478bdstevel@tonic-gate/*
3817c478bdstevel@tonic-gate * Programming interfaces for class 0x7 / subclass 0x1 (Parallel)
3827c478bdstevel@tonic-gate */
3837c478bdstevel@tonic-gate#define	PCI_COMM_PARALLEL_IF_GENERIC	0x0	/* Generic Parallel port */
3847c478bdstevel@tonic-gate#define	PCI_COMM_PARALLEL_IF_BIDIRECT	0x1	/* Bi-directional Parallel */
3857c478bdstevel@tonic-gate#define	PCI_COMM_PARALLEL_IF_ECP	0x2	/* ECP 1.X Parallel port */
3867c478bdstevel@tonic-gate#define	PCI_COMM_PARALLEL_IF_1284	0x3	/* IEEE 1284 Parallel port */
3877c478bdstevel@tonic-gate#define	PCI_COMM_PARALLEL_IF_1284_TARG	0xFE	/* IEEE 1284 target device */
3887c478bdstevel@tonic-gate
3897c478bdstevel@tonic-gate/*
3907c478bdstevel@tonic-gate * Programming interfaces for class 0x7 / subclass 0x3 (Modem)
3917c478bdstevel@tonic-gate */
3927c478bdstevel@tonic-gate#define	PCI_COMM_MODEM_IF_GENERIC	0x0	/* Generic Modem */
3937c478bdstevel@tonic-gate#define	PCI_COMM_MODEM_IF_HAYES_16450	0x1	/* Hayes 16450-compat Modem */
3947c478bdstevel@tonic-gate#define	PCI_COMM_MODEM_IF_HAYES_16550	0x2	/* Hayes 16550-compat Modem */
3957c478bdstevel@tonic-gate#define	PCI_COMM_MODEM_IF_HAYES_16650	0x3	/* Hayes 16650-compat Modem */
3967c478bdstevel@tonic-gate#define	PCI_COMM_MODEM_IF_HAYES_16750	0x4	/* Hayes 16750-compat Modem */
3977c478bdstevel@tonic-gate
3987c478bdstevel@tonic-gate/*
3997c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x8
4007c478bdstevel@tonic-gate */
4017c478bdstevel@tonic-gate#define	PCI_PERIPH_PIC		0x0	/* Generic PIC */
4027c478bdstevel@tonic-gate#define	PCI_PERIPH_DMA		0x1	/* Generic DMA Controller */
4037c478bdstevel@tonic-gate#define	PCI_PERIPH_TIMER	0x2	/* Generic System Timer Controller */
4047c478bdstevel@tonic-gate#define	PCI_PERIPH_RTC		0x3	/* Generic RTC Controller */
405337fc9eanish#define	PCI_PERIPH_HPC		0x4	/* Generic PCI Hot-Plug Controller */
406337fc9eanish#define	PCI_PERIPH_SD_HC	0x5	/* SD Host Controller */
407337fc9eanish#define	PCI_PERIPH_IOMMU	0x6	/* IOMMU */
4087c478bdstevel@tonic-gate#define	PCI_PERIPH_OTHER	0x80	/* Other System Peripheral */
4097c478bdstevel@tonic-gate
4107c478bdstevel@tonic-gate/*
4117c478bdstevel@tonic-gate * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller)
4127c478bdstevel@tonic-gate */
4137c478bdstevel@tonic-gate#define	PCI_PERIPH_PIC_IF_GENERIC	0x0	/* Generic 8259 APIC */
4147c478bdstevel@tonic-gate#define	PCI_PERIPH_PIC_IF_ISA		0x1	/* ISA PIC */
4157c478bdstevel@tonic-gate#define	PCI_PERIPH_PIC_IF_EISA		0x2	/* EISA PIC */
4167c478bdstevel@tonic-gate#define	PCI_PERIPH_PIC_IF_IO_APIC	0x10	/* I/O APIC interrupt ctrlr */
4177c478bdstevel@tonic-gate#define	PCI_PERIPH_PIC_IF_IOX_APIC	0x20	/* I/O(x) APIC intr ctrlr */
4187c478bdstevel@tonic-gate
4197c478bdstevel@tonic-gate/*
4207c478bdstevel@tonic-gate * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller)
4217c478bdstevel@tonic-gate */
4227c478bdstevel@tonic-gate#define	PCI_PERIPH_DMA_IF_GENERIC	0x0	/* Generic 8237 DMA ctrlr */
4237c478bdstevel@tonic-gate#define	PCI_PERIPH_DMA_IF_ISA		0x1	/* ISA DMA ctrlr */
4247c478bdstevel@tonic-gate#define	PCI_PERIPH_DMA_IF_EISA		0x2	/* EISA DMA ctrlr */
4257c478bdstevel@tonic-gate
4267c478bdstevel@tonic-gate/*
4277c478bdstevel@tonic-gate * Programming interfaces for class 0x8 / subclass 0x2 (timer)
4287c478bdstevel@tonic-gate */
4297c478bdstevel@tonic-gate#define	PCI_PERIPH_TIMER_IF_GENERIC	0x0	/* Generic 8254 system timer */
4307c478bdstevel@tonic-gate#define	PCI_PERIPH_TIMER_IF_ISA		0x1	/* ISA system timers */
4317c478bdstevel@tonic-gate#define	PCI_PERIPH_TIMER_IF_EISA	0x2	/* EISA system timers (two) */
432337fc9eanish#define	PCI_PERIPH_TIMER_IF_HPET	0x3	/* High Perf Event timer */
4337c478bdstevel@tonic-gate
4347c478bdstevel@tonic-gate/*
4357c478bdstevel@tonic-gate * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock)
4367c478bdstevel@tonic-gate */
4377c478bdstevel@tonic-gate#define	PCI_PERIPH_RTC_IF_GENERIC	0x0	/* Generic RTC controller */
4387c478bdstevel@tonic-gate#define	PCI_PERIPH_RTC_IF_ISA		0x1	/* ISA RTC controller */
4397c478bdstevel@tonic-gate
4407c478bdstevel@tonic-gate/*
4417c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x9
4427c478bdstevel@tonic-gate */
4437c478bdstevel@tonic-gate#define	PCI_INPUT_KEYBOARD	0x0	/* Keyboard Controller */
4447c478bdstevel@tonic-gate#define	PCI_INPUT_DIGITIZ	0x1	/* Digitizer (Pen) */
4457c478bdstevel@tonic-gate#define	PCI_INPUT_MOUSE		0x2	/* Mouse Controller */
4467c478bdstevel@tonic-gate#define	PCI_INPUT_SCANNER	0x3	/* Scanner Controller */
4477c478bdstevel@tonic-gate#define	PCI_INPUT_GAMEPORT	0x4	/* Gameport Controller */
4487c478bdstevel@tonic-gate#define	PCI_INPUT_OTHER		0x80	/* Other Input Controller */
4497c478bdstevel@tonic-gate
4507c478bdstevel@tonic-gate/*
4517c478bdstevel@tonic-gate * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller)
4527c478bdstevel@tonic-gate */
4537c478bdstevel@tonic-gate#define	PCI_INPUT_GAMEPORT_IF_GENERIC	0x00	/* Generic controller */
4547c478bdstevel@tonic-gate#define	PCI_INPUT_GAMEPORT_IF_LEGACY	0x10	/* Legacy controller */
4557c478bdstevel@tonic-gate
4567c478bdstevel@tonic-gate/*
457337fc9eanish * PCI Sub-class codes - base class 0xA
4587c478bdstevel@tonic-gate */
4597c478bdstevel@tonic-gate#define	PCI_DOCK_GENERIC	0x00	/* Generic Docking Station */
4607c478bdstevel@tonic-gate#define	PCI_DOCK_OTHER		0x80	/* Other Type of Docking Station */
4617c478bdstevel@tonic-gate
4627c478bdstevel@tonic-gate/*
463337fc9eanish * PCI Sub-class codes - base class 0xB
4647c478bdstevel@tonic-gate */
4657c478bdstevel@tonic-gate#define	PCI_PROCESSOR_386	0x0	/* 386 */
4667c478bdstevel@tonic-gate#define	PCI_PROCESSOR_486	0x1	/* 486 */
4677c478bdstevel@tonic-gate#define	PCI_PROCESSOR_PENT	0x2	/* Pentium */
4687c478bdstevel@tonic-gate#define	PCI_PROCESSOR_ALPHA	0x10	/* Alpha */
4697c478bdstevel@tonic-gate#define	PCI_PROCESSOR_POWERPC	0x20	/* PowerPC */
4707c478bdstevel@tonic-gate#define	PCI_PROCESSOR_MIPS	0x30	/* MIPS */
4717c478bdstevel@tonic-gate#define	PCI_PROCESSOR_COPROC	0x40	/* Co-processor */
472337fc9eanish#define	PCI_PROCESSOR_OTHER	0x80	/* Other processors */
4737c478bdstevel@tonic-gate
4747c478bdstevel@tonic-gate/*
475337fc9eanish * PCI Sub-class codes - base class 0xC (Serial Controllers)
4767c478bdstevel@tonic-gate */
4777c478bdstevel@tonic-gate#define	PCI_SERIAL_FIRE		0x0	/* FireWire (IEEE 1394) */
4787c478bdstevel@tonic-gate#define	PCI_SERIAL_ACCESS	0x1	/* ACCESS.bus */
4797c478bdstevel@tonic-gate#define	PCI_SERIAL_SSA		0x2	/* SSA */
4807c478bdstevel@tonic-gate#define	PCI_SERIAL_USB		0x3	/* Universal Serial Bus */
4817c478bdstevel@tonic-gate#define	PCI_SERIAL_FIBRE	0x4	/* Fibre Channel */
4827c478bdstevel@tonic-gate#define	PCI_SERIAL_SMBUS	0x5	/* System Management Bus */
4837c478bdstevel@tonic-gate#define	PCI_SERIAL_IB		0x6	/* InfiniBand */
4847c478bdstevel@tonic-gate#define	PCI_SERIAL_IPMI		0x7	/* IPMI */
4857c478bdstevel@tonic-gate#define	PCI_SERIAL_SERCOS	0x8	/* SERCOS Interface Std (IEC 61491) */
4867c478bdstevel@tonic-gate#define	PCI_SERIAL_CANBUS	0x9	/* CANbus */
487337fc9eanish#define	PCI_SERIAL_OTHER	0x80	/* Other Serial Bus Controllers */
488337fc9eanish
489337fc9eanish/*
490337fc9eanish * Programming interfaces for class 0xC / subclass 0x0 (Firewire)
491337fc9eanish */
49258b4950Hans Rosenfeld#define	PCI_SERIAL_FIRE_WIRE		0x00	/* IEEE 1394 (Firewire) */
49358b4950Hans Rosenfeld#define	PCI_SERIAL_FIRE_1394_HCI	0x10	/* 1394 OpenHCI Host Cntrlr */
4947c478bdstevel@tonic-gate
4957c478bdstevel@tonic-gate/*
4967c478bdstevel@tonic-gate * Programming interfaces for class 0xC / subclass 0x3 (USB controller)
4977c478bdstevel@tonic-gate */
49858b4950Hans Rosenfeld#define	PCI_SERIAL_USB_IF_UHCI		0x00	/* UHCI Compliant */
49958b4950Hans Rosenfeld#define	PCI_SERIAL_USB_IF_OHCI		0x10	/* OHCI Compliant */
50058b4950Hans Rosenfeld#define	PCI_SERIAL_USB_IF_EHCI		0x20	/* EHCI Compliant */
50158b4950Hans Rosenfeld#define	PCI_SERIAL_USB_IF_GENERIC	0x80	/* no specific HCD */
50258b4950Hans Rosenfeld#define	PCI_SERIAL_USB_IF_DEVICE	0xFE	/* not a HCD */
5037c478bdstevel@tonic-gate
5047c478bdstevel@tonic-gate/*
5057c478bdstevel@tonic-gate * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller)
5067c478bdstevel@tonic-gate */
50758b4950Hans Rosenfeld#define	PCI_SERIAL_IPMI_IF_SMIC		0x0	/* SMIC Interface */
50858b4950Hans Rosenfeld#define	PCI_SERIAL_IPMI_IF_KBD		0x1	/* Keyboard Ctrl Style Intfc */
5097c478bdstevel@tonic-gate#define	PCI_SERIAL_IPMI_IF_BTI		0x2	/* Block Transfer Interface */
5107c478bdstevel@tonic-gate
5117c478bdstevel@tonic-gate/*
512337fc9eanish * PCI Sub-class codes - base class 0xD (Wireless controllers)
5137c478bdstevel@tonic-gate */
5147c478bdstevel@tonic-gate#define	PCI_WIRELESS_IRDA		0x0	/* iRDA Compatible Controller */
5157c478bdstevel@tonic-gate#define	PCI_WIRELESS_IR			0x1	/* Consumer IR Controller */
5167c478bdstevel@tonic-gate#define	PCI_WIRELESS_RF			0x10	/* RF Controller */
5177c478bdstevel@tonic-gate#define	PCI_WIRELESS_BLUETOOTH		0x11	/* Bluetooth Controller */
5187c478bdstevel@tonic-gate#define	PCI_WIRELESS_BROADBAND		0x12	/* Broadband Controller */
5197c478bdstevel@tonic-gate#define	PCI_WIRELESS_80211A		0x20	/* Ethernet 802.11a 5 GHz */
5207c478bdstevel@tonic-gate#define	PCI_WIRELESS_80211B		0x21	/* Ethernet 802.11b 2.4 GHz */
5217c478bdstevel@tonic-gate#define	PCI_WIRELESS_OTHER		0x80	/* Other Wireless Controllers */
5227c478bdstevel@tonic-gate
5237c478bdstevel@tonic-gate/*
524337fc9eanish * Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller)
525337fc9eanish */
52658b4950Hans Rosenfeld#define	PCI_WIRELESS_IR_CONSUMER	0x00	/* Consumer IR Controller */
52758b4950Hans Rosenfeld#define	PCI_WIRELESS_IR_UWB_RC		0x10	/* UWB Radio Controller */
528337fc9eanish
529337fc9eanish/*
530337fc9eanish * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
5317c478bdstevel@tonic-gate */
532337fc9eanish#define	PCI_INTIO_MSG_FIFO		0x0	/* Message FIFO at off 40h */
5337c478bdstevel@tonic-gate#define	PCI_INTIO_I20			0x1	/* I20 Arch Spec 1.0 */
5347c478bdstevel@tonic-gate
5357c478bdstevel@tonic-gate/*
536337fc9eanish * PCI Sub-class codes - base class 0xF (Satellite Communication controllers)
5377c478bdstevel@tonic-gate */
5387c478bdstevel@tonic-gate#define	PCI_SATELLITE_COMM_TV		0x01	/* TV */
5397c478bdstevel@tonic-gate#define	PCI_SATELLITE_COMM_AUDIO	0x02	/* Audio */
5407c478bdstevel@tonic-gate#define	PCI_SATELLITE_COMM_VOICE	0x03	/* Voice */
5417c478bdstevel@tonic-gate#define	PCI_SATELLITE_COMM_DATA		0x04	/* DATA */
542337fc9eanish#define	PCI_SATELLITE_COMM_OTHER	0x80	/* Other Satelite Comm Cntrlr */
5437c478bdstevel@tonic-gate
5447c478bdstevel@tonic-gate/*
5457c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
5467c478bdstevel@tonic-gate */
5477c478bdstevel@tonic-gate#define	PCI_CRYPT_NETWORK		0x00	/* Network and Computing */
5487c478bdstevel@tonic-gate#define	PCI_CRYPT_ENTERTAINMENT		0x10	/* Entertainment en/decrypt */
5497c478bdstevel@tonic-gate#define	PCI_CRYPT_OTHER			0x80	/* Other en/decryption ctrlrs */
5507c478bdstevel@tonic-gate
5517c478bdstevel@tonic-gate/*
5527c478bdstevel@tonic-gate * PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
5537c478bdstevel@tonic-gate */
5547c478bdstevel@tonic-gate#define	PCI_SIGNAL_DPIO			0x00	/* DPIO modules */
5557c478bdstevel@tonic-gate#define	PCI_SIGNAL_PERF_COUNTERS	0x01	/* Performance counters */
5567c478bdstevel@tonic-gate#define	PCI_SIGNAL_COMM_SYNC		0x10	/* Comm. synchronization plus */
5577c478bdstevel@tonic-gate						/* time and freq test ctrlr */
5587c478bdstevel@tonic-gate#define	PCI_SIGNAL_MANAGEMENT		0x20	/* Management card */
5597c478bdstevel@tonic-gate#define	PCI_SIGNAL_OTHER		0x80	/* DSP/DAP controller */
5607c478bdstevel@tonic-gate
5617c478bdstevel@tonic-gate/* PCI header decode */
5627c478bdstevel@tonic-gate#define	PCI_HEADER_MULTI	0x80	/* multi-function device */
5637c478bdstevel@tonic-gate#define	PCI_HEADER_ZERO		0x00	/* type zero PCI header */
5647c478bdstevel@tonic-gate#define	PCI_HEADER_ONE		0x01	/* type one PCI header */
5657c478bdstevel@tonic-gate#define	PCI_HEADER_TWO		0x02	/* type two PCI header */
5667c478bdstevel@tonic-gate#define	PCI_HEADER_PPB		PCI_HEADER_ONE  /* type one PCI to PCI Bridge */
5677c478bdstevel@tonic-gate#define	PCI_HEADER_CARDBUS	PCI_HEADER_TWO	/* type one PCI header */
5687c478bdstevel@tonic-gate
5697c478bdstevel@tonic-gate#define	PCI_HEADER_TYPE_M	0x7f  /* type mask for header */
5707c478bdstevel@tonic-gate
5717c478bdstevel@tonic-gate/*
5727c478bdstevel@tonic-gate * Base register bit definitions.
5737c478bdstevel@tonic-gate */
5747c478bdstevel@tonic-gate#define	PCI_BASE_SPACE_M    0x1  /* memory space indicator */
5757c478bdstevel@tonic-gate#define	PCI_BASE_SPACE_IO   0x1   /* IO space */
5767c478bdstevel@tonic-gate#define	PCI_BASE_SPACE_MEM  0x0   /* memory space */
5777c478bdstevel@tonic-gate
5787c478bdstevel@tonic-gate#define	PCI_BASE_TYPE_MEM   0x0   /* 32-bit memory address */
5797c478bdstevel@tonic-gate#define	PCI_BASE_TYPE_LOW   0x2   /* less than 1Mb address */
5807c478bdstevel@tonic-gate#define	PCI_BASE_TYPE_ALL   0x4   /* 64-bit memory address */
5817c478bdstevel@tonic-gate#define	PCI_BASE_TYPE_RES   0x6   /* reserved */
5827c478bdstevel@tonic-gate
5837c478bdstevel@tonic-gate#define	PCI_BASE_TYPE_M		0x00000006  /* type indicator mask */
5847c478bdstevel@tonic-gate#define	PCI_BASE_PREF_M		0x00000008  /* prefetch mask */
5857c478bdstevel@tonic-gate#define	PCI_BASE_M_ADDR_M	0xfffffff0  /* memory address mask */
586b5cf5bcHans Rosenfeld#define	PCI_BASE_M_ADDR64_M	0xfffffffffffffff0ULL /* 64bit mem addr mask */
5877c478bdstevel@tonic-gate#define	PCI_BASE_IO_ADDR_M	0xfffffffe  /* I/O address mask */
5887c478bdstevel@tonic-gate
5897c478bdstevel@tonic-gate#define	PCI_BASE_ROM_ADDR_M	0xfffff800  /* ROM address mask */
5907c478bdstevel@tonic-gate#define	PCI_BASE_ROM_ENABLE	0x00000001  /* ROM decoder enable */
5917c478bdstevel@tonic-gate
5927c478bdstevel@tonic-gate/*
5937c478bdstevel@tonic-gate * Capabilities linked list entry offsets
5947c478bdstevel@tonic-gate */
5957c478bdstevel@tonic-gate#define	PCI_CAP_ID		0x0	/* capability identifier, 1 byte */
5967c478bdstevel@tonic-gate#define	PCI_CAP_NEXT_PTR	0x1	/* next entry pointer, 1 byte */
59770025d7johnny#define	PCI_CAP_ID_REGS_OFF	0x2	/* cap id register offset */
5987c478bdstevel@tonic-gate#define	PCI_CAP_MAX_PTR		0x30	/* maximum number of cap pointers */
5997c478bdstevel@tonic-gate#define	PCI_CAP_PTR_OFF		0x40	/* minimum cap pointer offset */
6007c478bdstevel@tonic-gate#define	PCI_CAP_PTR_MASK	0xFC	/* mask for capability pointer */
6017c478bdstevel@tonic-gate
6027c478bdstevel@tonic-gate/*
6037c478bdstevel@tonic-gate * Capability identifier values
6047c478bdstevel@tonic-gate */
6057c478bdstevel@tonic-gate#define	PCI_CAP_ID_PM		0x1	/* power management entry */
6067c478bdstevel@tonic-gate#define	PCI_CAP_ID_AGP		0x2	/* AGP supported */
6077c478bdstevel@tonic-gate#define	PCI_CAP_ID_VPD		0x3	/* VPD supported */
6087c478bdstevel@tonic-gate#define	PCI_CAP_ID_SLOT_ID	0x4	/* Slot Identification supported */
6097c478bdstevel@tonic-gate#define	PCI_CAP_ID_MSI		0x5	/* MSI supported */
6107c478bdstevel@tonic-gate#define	PCI_CAP_ID_cPCI_HS	0x6	/* CompactPCI Host Swap supported */
6117c478bdstevel@tonic-gate#define	PCI_CAP_ID_PCIX		0x7	/* PCI-X supported */
6127c478bdstevel@tonic-gate#define	PCI_CAP_ID_HT		0x8	/* HyperTransport supported */
6137c478bdstevel@tonic-gate#define	PCI_CAP_ID_VS		0x9	/* Vendor Specific */
6147c478bdstevel@tonic-gate#define	PCI_CAP_ID_DEBUG_PORT	0xA	/* Debug Port supported */
6157c478bdstevel@tonic-gate#define	PCI_CAP_ID_cPCI_CRC	0xB	/* CompactPCI central resource ctrl */
6162694730Evan Yan#define	PCI_CAP_ID_PCI_HOTPLUG	0xC	/* PCI Hot Plug (SHPC) supported */
617337fc9eanish#define	PCI_CAP_ID_P2P_SUBSYS	0xD	/* PCI bridge Sub-system ID */
6187c478bdstevel@tonic-gate#define	PCI_CAP_ID_AGP_8X	0xE	/* AGP 8X supported */
6197c478bdstevel@tonic-gate#define	PCI_CAP_ID_SECURE_DEV	0xF	/* Secure Device supported */
6207c478bdstevel@tonic-gate#define	PCI_CAP_ID_PCI_E	0x10	/* PCI Express supported */
6217c478bdstevel@tonic-gate#define	PCI_CAP_ID_MSI_X	0x11	/* MSI-X supported */
622337fc9eanish#define	PCI_CAP_ID_SATA		0x12	/* SATA Data/Index Config supported */
623337fc9eanish#define	PCI_CAP_ID_FLR		0x13	/* Function Level Reset supported */
6247c478bdstevel@tonic-gate
6257c478bdstevel@tonic-gate/*
6267c478bdstevel@tonic-gate * Capability next entry pointer values
6277c478bdstevel@tonic-gate */
6287c478bdstevel@tonic-gate#define	PCI_CAP_NEXT_PTR_NULL	0x0	/* no more entries in the list */
6297c478bdstevel@tonic-gate
6307c478bdstevel@tonic-gate/*
6317c478bdstevel@tonic-gate * PCI power management (PM) capability entry offsets
6327c478bdstevel@tonic-gate */
6337c478bdstevel@tonic-gate#define	PCI_PMCAP		0x2	/* PM capabilities, 2 bytes */
6347c478bdstevel@tonic-gate#define	PCI_PMCSR		0x4	/* PM control/status reg, 2 bytes */
6357c478bdstevel@tonic-gate#define	PCI_PMCSR_BSE		0x6	/* PCI-PCI bridge extensions, 1 byte */
6367c478bdstevel@tonic-gate#define	PCI_PMDATA		0x7	/* PM data, 1 byte */
6377c478bdstevel@tonic-gate
6387c478bdstevel@tonic-gate/*
6397c478bdstevel@tonic-gate * PM capabilities values - 2 bytes
6407c478bdstevel@tonic-gate */
6417c478bdstevel@tonic-gate#define	PCI_PMCAP_VER_1_0	0x1	/* PCI PM spec 1.0 */
6427c478bdstevel@tonic-gate#define	PCI_PMCAP_VER_1_1	0x2	/* PCI PM spec 1.1 */
6437c478bdstevel@tonic-gate#define	PCI_PMCAP_VER_MASK	0x7	/* version mask */
6447c478bdstevel@tonic-gate#define	PCI_PMCAP_PME_CLOCK	0x8	/* needs PCI clock for PME */
6457c478bdstevel@tonic-gate#define	PCI_PMCAP_DSI		0x20	/* needs device specific init */
6467c478bdstevel@tonic-gate#define	PCI_PMCAP_AUX_CUR_SELF	0x0	/* 0 aux current - self powered */
6477c478bdstevel@tonic-gate#define	PCI_PMCAP_AUX_CUR_55mA	0x40	/* 55 mA aux current */
6487c478bdstevel@tonic-gate#define	PCI_PMCAP_AUX_CUR_100mA	0x80	/* 100 mA aux current */
6497c478bdstevel@tonic-gate#define	PCI_PMCAP_AUX_CUR_160mA	0xc0	/* 160 mA aux current */
6507c478bdstevel@tonic-gate#define	PCI_PMCAP_AUX_CUR_220mA	0x100	/* 220 mA aux current */
6517c478bdstevel@tonic-gate#define	PCI_PMCAP_AUX_CUR_270mA	0x140	/* 270 mA aux current */
6527c478bdstevel@tonic-gate#define	PCI_PMCAP_AUX_CUR_320mA	0x180	/* 320 mA aux current */
6537c478bdstevel@tonic-gate#define	PCI_PMCAP_AUX_CUR_375mA	0x1c0	/* 375 mA aux current */
6547c478bdstevel@tonic-gate#define	PCI_PMCAP_AUX_CUR_MASK	0x1c0	/* 3.3Vaux aux current needs */
6557c478bdstevel@tonic-gate#define	PCI_PMCAP_D1		0x200	/* D1 state supported */
6567c478bdstevel@tonic-gate#define	PCI_PMCAP_D2		0x400	/* D2 state supported */
6577c478bdstevel@tonic-gate#define	PCI_PMCAP_D0_PME	0x800	/* PME from D0 */
6587c478bdstevel@tonic-gate#define	PCI_PMCAP_D1_PME	0x1000	/* PME from D1 */
6597c478bdstevel@tonic-gate#define	PCI_PMCAP_D2_PME	0x2000	/* PME from D2 */
6607c478bdstevel@tonic-gate#define	PCI_PMCAP_D3HOT_PME	0x4000	/* PME from D3hot */
6617c478bdstevel@tonic-gate#define	PCI_PMCAP_D3COLD_PME	0x8000	/* PME from D3cold */
6627c478bdstevel@tonic-gate#define	PCI_PMCAP_PME_MASK	0xf800	/* PME support mask */
6637c478bdstevel@tonic-gate
6647c478bdstevel@tonic-gate/*
6657c478bdstevel@tonic-gate * PM control/status values - 2 bytes
6667c478bdstevel@tonic-gate */
6677c478bdstevel@tonic-gate#define	PCI_PMCSR_D0			0x0	/* power state D0 */
6687c478bdstevel@tonic-gate#define	PCI_PMCSR_D1			0x1	/* power state D1 */
6697c478bdstevel@tonic-gate#define	PCI_PMCSR_D2			0x2	/* power state D2 */
6707c478bdstevel@tonic-gate#define	PCI_PMCSR_D3HOT			0x3	/* power state D3hot */
6717c478bdstevel@tonic-gate#define	PCI_PMCSR_STATE_MASK		0x3	/* power state mask */
6727c478bdstevel@tonic-gate#define	PCI_PMCSR_PME_EN		0x100	/* enable PME assertion */
6737c478bdstevel@tonic-gate#define	PCI_PMCSR_DSEL_D0_PWR_C		0x0	/* D0 power consumed */
6747c478bdstevel@tonic-gate#define	PCI_PMCSR_DSEL_D1_PWR_C		0x200	/* D1 power consumed */
6757c478bdstevel@tonic-gate#define	PCI_PMCSR_DSEL_D2_PWR_C		0x400	/* D2 power consumed */
6767c478bdstevel@tonic-gate#define	PCI_PMCSR_DSEL_D3_PWR_C		0x600	/* D3 power consumed */
6777c478bdstevel@tonic-gate#define	PCI_PMCSR_DSEL_D0_PWR_D		0x800	/* D0 power dissipated */
6787c478bdstevel@tonic-gate#define	PCI_PMCSR_DSEL_D1_PWR_D		0xa00	/* D1 power dissipated */
6797c478bdstevel@tonic-gate#define	PCI_PMCSR_DSEL_D2_PWR_D		0xc00	/* D2 power dissipated */
6807c478bdstevel@tonic-gate#define	PCI_PMCSR_DSEL_D3_PWR_D		0xe00	/* D3 power dissipated */
6817c478bdstevel@tonic-gate#define	PCI_PMCSR_DSEL_COM_C		0x1000	/* common power consumption */
6827c478bdstevel@tonic-gate#define	PCI_PMCSR_DSEL_MASK		0x1e00	/* data select mask */
6837c478bdstevel@tonic-gate#define	PCI_PMCSR_DSCL_UNKNOWN		0x0	/* data scale unknown */
6847c478bdstevel@tonic-gate#define	PCI_PMCSR_DSCL_1_BY_10		0x2000	/* data scale 0.1x */
6857c478bdstevel@tonic-gate#define	PCI_PMCSR_DSCL_1_BY_100		0x4000	/* data scale 0.01x */
6867c478bdstevel@tonic-gate#define	PCI_PMCSR_DSCL_1_BY_1000	0x6000	/* data scale 0.001x */
6877c478bdstevel@tonic-gate#define	PCI_PMCSR_DSCL_MASK		0x6000	/* data scale mask */
6887c478bdstevel@tonic-gate#define	PCI_PMCSR_PME_STAT		0x8000	/* PME status */
6897c478bdstevel@tonic-gate
6907c478bdstevel@tonic-gate/*
6917c478bdstevel@tonic-gate * PM PMCSR PCI to PCI bridge support extension values - 1 byte
6927c478bdstevel@tonic-gate */
6937c478bdstevel@tonic-gate#define	PCI_PMCSR_BSE_B2_B3	0x40	/* bridge D3hot -> secondary B2 */
6947c478bdstevel@tonic-gate#define	PCI_PMCSR_BSE_BPCC_EN	0x80	/* bus power/clock control enabled */
6957c478bdstevel@tonic-gate
6967c478bdstevel@tonic-gate/*
6977c478bdstevel@tonic-gate * PCI-X capability related definitions
6987c478bdstevel@tonic-gate */
6997c478bdstevel@tonic-gate#define	PCI_PCIX_COMMAND	0x2	/* Command register offset */
70000d0963dilpreet#define	PCI_PCIX_STATUS		0x4	/* Status register offset */
70100d0963dilpreet#define	PCI_PCIX_ECC_STATUS	0x8	/* ECC Status register offset */
70200d0963dilpreet#define	PCI_PCIX_ECC_FST_AD	0xC	/* ECC First address register offset */
70300d0963dilpreet#define	PCI_PCIX_ECC_SEC_AD	0x10	/* ECC Second address register offset */
70400d0963dilpreet#define	PCI_PCIX_ECC_ATTR	0x14	/* ECC Attribute register offset */
7057c478bdstevel@tonic-gate
70600d0963dilpreet/*
70700d0963dilpreet * PCI-X bridge capability related definitions
70800d0963dilpreet */
709bf8fc23et#define	PCI_PCIX_SEC_STATUS		0x2	/* Secondary Status offset */
710bf8fc23et#define	PCI_PCIX_SEC_STATUS_SCD		0x4	/* Split Completion Discarded */
711bf8fc23et#define	PCI_PCIX_SEC_STATUS_USC		0x8	/* Unexpected Split Complete */
712bf8fc23et#define	PCI_PCIX_SEC_STATUS_SCO		0x10	/* Split Completion Overrun */
713bf8fc23et#define	PCI_PCIX_SEC_STATUS_SRD		0x20	/* Split Completion Delayed */
714bf8fc23et#define	PCI_PCIX_SEC_STATUS_ERR_MASK	0x3C
715bf8fc23et
716bf8fc23et#define	PCI_PCIX_BDG_STATUS		0x4	/* Bridge Status offset */
717bf8fc23et#define	PCI_PCIX_BDG_STATUS_USC		0x80000
718bf8fc23et#define	PCI_PCIX_BDG_STATUS_SCO		0x100000
719bf8fc23et#define	PCI_PCIX_BDG_STATUS_SRD		0x200000
720bf8fc23et#define	PCI_PCIX_BDG_STATUS_ERR_MASK	0x380000
721bf8fc23et
72200d0963dilpreet#define	PCI_PCIX_UP_SPL_CTL	0x8	/* Upstream split ctrl reg offset */
72300d0963dilpreet#define	PCI_PCIX_DOWN_SPL_CTL	0xC	/* Downstream split ctrl reg offset */
72400d0963dilpreet#define	PCI_PCIX_BDG_ECC_STATUS	0x10	/* ECC Status register offset */
72500d0963dilpreet#define	PCI_PCIX_BDG_ECC_FST_AD	0x14	/* ECC First address register offset */
72600d0963dilpreet#define	PCI_PCIX_BDG_ECC_SEC_AD	0x18	/* ECC Second address register offset */
72700d0963dilpreet#define	PCI_PCIX_BDG_ECC_ATTR	0x1C	/* ECC Attribute register offset */
72800d0963dilpreet
72900d0963dilpreet/*
73000d0963dilpreet * PCIX capabilities values
73100d0963dilpreet */
7327c478bdstevel@tonic-gate#define	PCI_PCIX_VER_MASK	0x3000	/* Bits 12 and 13 */
7337c478bdstevel@tonic-gate#define	PCI_PCIX_VER_0		0x0000	/* PCIX cap list item version 0 */
7347c478bdstevel@tonic-gate#define	PCI_PCIX_VER_1		0x1000	/* PCIX cap list item version 1 */
7357c478bdstevel@tonic-gate#define	PCI_PCIX_VER_2		0x2000	/* PCIX cap list item version 2 */
7367c478bdstevel@tonic-gate
73700d0963dilpreet#define	PCI_PCIX_SPL_DSCD	0x40000 /* Split Completion Discarded */
73800d0963dilpreet#define	PCI_PCIX_UNEX_SPL	0x80000	/* Unexpected Split Completion */
73900d0963dilpreet#define	PCI_PCIX_RX_SPL_MSG	0x20000000 /* Recieved Spl Comp Error Message */
74000d0963dilpreet
74100d0963dilpreet#define	PCI_PCIX_ECC_SEL	0x1	/* Secondary ECC register select */
74200d0963dilpreet#define	PCI_PCIX_ECC_EP		0x2	/* Error Present on other side */
74300d0963dilpreet#define	PCI_PCIX_ECC_S_CE	0x4	/* Addl Correctable ECC Error */
74400d0963dilpreet#define	PCI_PCIX_ECC_S_UE	0x8	/* Addl Uncorrectable ECC Error */
74500d0963dilpreet#define	PCI_PCIX_ECC_PHASE	0x70	/* ECC Error Phase */
74600d0963dilpreet#define	PCI_PCIX_ECC_CORR	0x80	/* ECC Error Corrected */
74700d0963dilpreet#define	PCI_PCIX_ECC_SYN	0xff00	/* ECC Error Syndrome */
74800d0963dilpreet#define	PCI_PCIX_ECC_FST_CMD	0xf0000	 /* ECC Error First Command */
74900d0963dilpreet#define	PCI_PCIX_ECC_SEC_CMD	0xf00000 /* ECC Error Second Command */
75000d0963dilpreet#define	PCI_PCIX_ECC_UP_ATTR	0xf000000 /* ECC Error Upper Attributes */
75100d0963dilpreet
75200d0963dilpreet/*
75300d0963dilpreet * PCIX ECC Phase Values
75400d0963dilpreet */
75500d0963dilpreet#define	PCI_PCIX_ECC_PHASE_NOERR	0x0
75600d0963dilpreet#define	PCI_PCIX_ECC_PHASE_FADDR	0x1
75700d0963dilpreet#define	PCI_PCIX_ECC_PHASE_SADDR	0x2
75800d0963dilpreet#define	PCI_PCIX_ECC_PHASE_ATTR		0x3
75900d0963dilpreet#define	PCI_PCIX_ECC_PHASE_DATA32	0x4
76000d0963dilpreet#define	PCI_PCIX_ECC_PHASE_DATA64	0x5
76100d0963dilpreet
76200d0963dilpreet/*
76300d0963dilpreet * PCI-X Command Encoding
76400d0963dilpreet */
76500d0963dilpreet#define	PCI_PCIX_CMD_INTR		0x0
76600d0963dilpreet#define	PCI_PCIX_CMD_SPEC		0x1
76700d0963dilpreet#define	PCI_PCIX_CMD_IORD		0x2
76800d0963dilpreet#define	PCI_PCIX_CMD_IOWR		0x3
76900d0963dilpreet#define	PCI_PCIX_CMD_DEVID		0x5
77000d0963dilpreet#define	PCI_PCIX_CMD_MEMRD_DW		0x6
77100d0963dilpreet#define	PCI_PCIX_CMD_MEMWR		0x7
77200d0963dilpreet#define	PCI_PCIX_CMD_MEMRD_BL		0x8
77300d0963dilpreet#define	PCI_PCIX_CMD_MEMWR_BL		0x9
77400d0963dilpreet#define	PCI_PCIX_CMD_CFRD		0xA
77500d0963dilpreet#define	PCI_PCIX_CMD_CFWR		0xB
77600d0963dilpreet#define	PCI_PCIX_CMD_SPL		0xC
77700d0963dilpreet#define	PCI_PCIX_CMD_DADR		0xD
77800d0963dilpreet#define	PCI_PCIX_CMD_MEMRDBL		0xE
77900d0963dilpreet#define	PCI_PCIX_CMD_MEMWRBL		0xF
78000d0963dilpreet
78100d0963dilpreet#if defined(_BIT_FIELDS_LTOH)
78200d0963dilpreettypedef struct pcix_attr {
78300d0963dilpreet	uint32_t	lbc	:8,
78400d0963dilpreet			rid	:16,
78500d0963dilpreet			tag	:5,
78600d0963dilpreet			ro	:1,
78700d0963dilpreet			ns	:1,
78800d0963dilpreet			r	:1;
78900d0963dilpreet} pcix_attr_t;
79000d0963dilpreet#elif defined(_BIT_FIELDS_HTOL)
79100d0963dilpreettypedef struct pcix_attr {
79200d0963dilpreet	uint32_t	r	:1,
79300d0963dilpreet			ns	:1,
79400d0963dilpreet			ro	:1,
79500d0963dilpreet			tag	:5,
79600d0963dilpreet			rid	:16,
79700d0963dilpreet			lbc	:8;
79800d0963dilpreet} pcix_attr_t;
79900d0963dilpreet#else
80000d0963dilpreet#error "bit field not defined"
80100d0963dilpreet#endif
80200d0963dilpreet
80300d0963dilpreet#define	PCI_PCIX_BSS_SPL_DSCD	0x4	/* Secondary split comp discarded */
80400d0963dilpreet#define	PCI_PCIX_BSS_UNEX_SPL	0x8	/* Secondary unexpected split comp */
80500d0963dilpreet#define	PCI_PCIX_BSS_SPL_OR	0x10	/* Secondary split comp overrun */
80600d0963dilpreet#define	PCI_PCIX_BSS_SPL_DLY	0x20	/* Secondary split comp delayed */
80700d0963dilpreet
8087c478bdstevel@tonic-gate/*
8092694730Evan Yan * PCI Hotplug capability entry offsets
8102694730Evan Yan *
8112694730Evan Yan * SHPC based PCI hotplug controller registers accessed via the DWORD
8122694730Evan Yan * select and DATA registers in PCI configuration space relative to the
8132694730Evan Yan * PCI HP capibility pointer.
8142694730Evan Yan */
8152694730Evan Yan#define	PCI_HP_DWORD_SELECT_OFF		0x2
8162694730Evan Yan#define	PCI_HP_DWORD_DATA_OFF		0x4
8172694730Evan Yan
8182694730Evan Yan#define	PCI_HP_BASE_OFFSET_REG		0x00
8192694730Evan Yan#define	PCI_HP_SLOTS_AVAIL_I_REG	0x01
8202694730Evan Yan#define	PCI_HP_SLOTS_AVAIL_II_REG	0x02
8212694730Evan Yan#define	PCI_HP_SLOT_CONFIGURATION_REG	0x03
8222694730Evan Yan#define	PCI_HP_PROF_IF_SBCR_REG		0x04
8232694730Evan Yan#define	PCI_HP_COMMAND_STATUS_REG	0x05
8242694730Evan Yan#define	PCI_HP_IRQ_LOCATOR_REG		0x06
8252694730Evan Yan#define	PCI_HP_SERR_LOCATOR_REG		0x07
8262694730Evan Yan#define	PCI_HP_CTRL_SERR_INT_REG	0x08
8272694730Evan Yan#define	PCI_HP_LOGICAL_SLOT_REGS	0x09
8282694730Evan Yan#define	PCI_HP_VENDOR_SPECIFIC		0x28
8292694730Evan Yan
8302694730Evan Yan/* Definitions used with the PCI_HP_SLOTS_AVAIL_I_REG register */
8312694730Evan Yan#define	PCI_HP_AVAIL_33MHZ_CONV_SPEED_SHIFT	0
8322694730Evan Yan#define	PCI_HP_AVAIL_66MHZ_PCIX_SPEED_SHIFT	8
8332694730Evan Yan#define	PCI_HP_AVAIL_100MHZ_PCIX_SPEED_SHIFT	16
8342694730Evan Yan#define	PCI_HP_AVAIL_133MHZ_PCIX_SPEED_SHIFT	24
8352694730Evan Yan#define	PCI_HP_AVAIL_SPEED_MASK			0x1F
8362694730Evan Yan
8372694730Evan Yan/* Definitions used with the PCI_HP_SLOTS_AVAIL_II_REG register */
8382694730Evan Yan#define	PCI_HP_AVAIL_66MHZ_CONV_SPEED_SHIFT	0
8392694730Evan Yan
8402694730Evan Yan/* Register bits used with the PCI_HP_PROF_IF_SBCR_REG register */
8412694730Evan Yan#define	PCI_HP_SBCR_33MHZ_CONV_SPEED		0x0
8422694730Evan Yan#define	PCI_HP_SBCR_66MHZ_CONV_SPEED		0x1
8432694730Evan Yan#define	PCI_HP_SBCR_66MHZ_PCIX_SPEED		0x2
8442694730Evan Yan#define	PCI_HP_SBCR_100MHZ_PCIX_SPEED		0x3
8452694730Evan Yan#define	PCI_HP_SBCR_133MHZ_PCIX_SPEED		0x4
8462694730Evan Yan#define	PCI_HP_SBCR_SPEED_MASK			0x7
8472694730Evan Yan
8482694730Evan Yan/* Register bits used with the PCI_HP_COMMAND_STATUS_REG register */
8492694730Evan Yan#define	PCI_HP_COMM_STS_ERR_INVALID_SPEED	0x80000
8502694730Evan Yan#define	PCI_HP_COMM_STS_ERR_INVALID_COMMAND	0x40000
8512694730Evan Yan#define	PCI_HP_COMM_STS_ERR_MRL_OPEN		0x20000
8522694730Evan Yan#define	PCI_HP_COMM_STS_ERR_MASK		0xe0000
8532694730Evan Yan#define	PCI_HP_COMM_STS_CTRL_BUSY		0x10000
8542694730Evan Yan#define	PCI_HP_COMM_STS_SET_SPEED		0x40
8552694730Evan Yan
8562694730Evan Yan/* Register bits used with the PCI_HP_CTRL_SERR_INT_REG register */
8572694730Evan Yan#define	PCI_HP_SERR_INT_GLOBAL_IRQ_MASK		0x1
8582694730Evan Yan#define	PCI_HP_SERR_INT_GLOBAL_SERR_MASK	0x2
8592694730Evan Yan#define	PCI_HP_SERR_INT_CMD_COMPLETE_MASK	0x4
8602694730Evan Yan#define	PCI_HP_SERR_INT_ARBITER_SERR_MASK	0x8
8612694730Evan Yan#define	PCI_HP_SERR_INT_CMD_COMPLETE_IRQ	0x10000
8622694730Evan Yan#define	PCI_HP_SERR_INT_ARBITER_IRQ		0x20000
8632694730Evan Yan#define	PCI_HP_SERR_INT_MASK_ALL		0xf
8642694730Evan Yan
8652694730Evan Yan/* Register bits used with the PCI_HP_LOGICAL_SLOT_REGS register */
8662694730Evan Yan#define	PCI_HP_SLOT_POWER_ONLY			0x1
8672694730Evan Yan#define	PCI_HP_SLOT_ENABLED			0x2
8682694730Evan Yan#define	PCI_HP_SLOT_DISABLED			0x3
8692694730Evan Yan#define	PCI_HP_SLOT_STATE_MASK			0x3
8702694730Evan Yan#define	PCI_HP_SLOT_MRL_STATE_MASK		0x100
8712694730Evan Yan#define	PCI_HP_SLOT_66MHZ_CONV_CAPABLE		0x200
8722694730Evan Yan#define	PCI_HP_SLOT_CARD_EMPTY_MASK		0xc00
8732694730Evan Yan#define	PCI_HP_SLOT_66MHZ_PCIX_CAPABLE		0x1000
8742694730Evan Yan#define	PCI_HP_SLOT_100MHZ_PCIX_CAPABLE		0x2000
8752694730Evan Yan#define	PCI_HP_SLOT_133MHZ_PCIX_CAPABLE		0x3000
8762694730Evan Yan#define	PCI_HP_SLOT_PCIX_CAPABLE_MASK		0x3000
8772694730Evan Yan#define	PCI_HP_SLOT_PCIX_CAPABLE_SHIFT		12
8782694730Evan Yan#define	PCI_HP_SLOT_PRESENCE_DETECTED		0x10000
8792694730Evan Yan#define	PCI_HP_SLOT_ISO_PWR_DETECTED		0x20000
8802694730Evan Yan#define	PCI_HP_SLOT_ATTN_DETECTED		0x40000
8812694730Evan Yan#define	PCI_HP_SLOT_MRL_DETECTED		0x80000
8822694730Evan Yan#define	PCI_HP_SLOT_POWER_DETECTED		0x100000
8832694730Evan Yan#define	PCI_HP_SLOT_PRESENCE_MASK		0x1000000
8842694730Evan Yan#define	PCI_HP_SLOT_ISO_PWR_MASK		0x2000000
8852694730Evan Yan#define	PCI_HP_SLOT_ATTN_MASK			0x4000000
8862694730Evan Yan#define	PCI_HP_SLOT_MRL_MASK			0x8000000
8872694730Evan Yan#define	PCI_HP_SLOT_POWER_MASK			0x10000000
8882694730Evan Yan#define	PCI_HP_SLOT_MRL_SERR_MASK		0x20000000
8892694730Evan Yan#define	PCI_HP_SLOT_POWER_SERR_MASK		0x40000000
8902694730Evan Yan#define	PCI_HP_SLOT_MASK_ALL			0x5f000000
8912694730Evan Yan
8922694730Evan Yan/* Register bits used with the PCI_HP_IRQ_LOCATOR_REG register */
8932694730Evan Yan#define	PCI_HP_IRQ_CMD_COMPLETE			0x1
8942694730Evan Yan#define	PCI_HP_IRQ_SLOT_N_PENDING		0x2
8952694730Evan Yan
8962694730Evan Yan/* Register bits used with the PCI_HP_SERR_LOCATOR_REG register */
8972694730Evan Yan#define	PCI_HP_IRQ_SERR_ARBITER_PENDING		0x1
8982694730Evan Yan#define	PCI_HP_IRQ_SERR_SLOT_N_PENDING		0x2
8992694730Evan Yan
9002694730Evan Yan/* Register bits used with the PCI_HP_SLOT_CONFIGURATION_REG register */
9012694730Evan Yan#define	PCI_HP_SLOT_CONFIG_MRL_SENSOR		0x40000000
9022694730Evan Yan#define	PCI_HP_SLOT_CONFIG_ATTN_BUTTON		0x80000000
9032694730Evan Yan#define	PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_SHIFT	16
9042694730Evan Yan#define	PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_MASK	0x3FF
9052694730Evan Yan
9062694730Evan Yan/*
9077c478bdstevel@tonic-gate * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
9087c478bdstevel@tonic-gate */
9097c478bdstevel@tonic-gate#define	PCI_MSI_CTRL		0x02	/* MSI control register, 2 bytes */
9107c478bdstevel@tonic-gate#define	PCI_MSI_ADDR_OFFSET	0x04	/* MSI 32-bit msg address, 4 bytes */
9117c478bdstevel@tonic-gate#define	PCI_MSI_32BIT_DATA	0x08	/* MSI 32-bit msg data, 2 bytes */
9127c478bdstevel@tonic-gate#define	PCI_MSI_32BIT_MASK	0x0C	/* MSI 32-bit mask bits, 4 bytes */
9137c478bdstevel@tonic-gate#define	PCI_MSI_32BIT_PENDING	0x10	/* MSI 32-bit pending bits, 4 bytes */
9147c478bdstevel@tonic-gate
9157c478bdstevel@tonic-gate/*
9167c478bdstevel@tonic-gate * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
9177c478bdstevel@tonic-gate */
9187c478bdstevel@tonic-gate#define	PCI_MSI_64BIT_DATA	0x0C	/* MSI 64-bit msg data, 2 bytes */
9197c478bdstevel@tonic-gate#define	PCI_MSI_64BIT_MASKBITS	0x10	/* MSI 64-bit mask bits, 4 bytes */
9207c478bdstevel@tonic-gate#define	PCI_MSI_64BIT_PENDING	0x14	/* MSI 64-bit pending bits, 4 bytes */
9217c478bdstevel@tonic-gate
9227c478bdstevel@tonic-gate/*
9237c478bdstevel@tonic-gate * PCI Message Signalled Interrupts (MSI) capability masks and shifts
9247c478bdstevel@tonic-gate */
9257c478bdstevel@tonic-gate#define	PCI_MSI_ENABLE_BIT	0x0001	/* MSI enable mask in MSI ctrl reg */
9267c478bdstevel@tonic-gate#define	PCI_MSI_MMC_MASK	0x000E	/* MMC mask in MSI ctrl reg */
9277c478bdstevel@tonic-gate#define	PCI_MSI_MMC_SHIFT	0x1	/* Shift for MMC bits */
9287c478bdstevel@tonic-gate#define	PCI_MSI_MME_MASK	0x0070	/* MME mask in MSI ctrl reg */
9297c478bdstevel@tonic-gate#define	PCI_MSI_MME_SHIFT	0x4	/* Shift for MME bits */
9307c478bdstevel@tonic-gate#define	PCI_MSI_64BIT_MASK	0x0080	/* 64bit support mask in MSI ctrl reg */
9317c478bdstevel@tonic-gate#define	PCI_MSI_PVM_MASK	0x0100	/* PVM support mask in MSI ctrl reg */
93233756aeRobert Mustacchi#define	PCI_MSI_EMD_MASK	0x0200	/* EMD Capable Mask */
93333756aeRobert Mustacchi#define	PCI_MSI_EMD_ENABLE	0x0400	/* EMD Enable bit */
9347c478bdstevel@tonic-gate
9357c478bdstevel@tonic-gate/*
9367c478bdstevel@tonic-gate * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
9377c478bdstevel@tonic-gate */
9387c478bdstevel@tonic-gate#define	PCI_MSIX_CTRL		0x02	/* MSI-X control register, 2 bytes */
9397c478bdstevel@tonic-gate#define	PCI_MSIX_TBL_OFFSET	0x04	/* MSI-X table offset, 4 bytes */
9409c75c6bgovinda#define	PCI_MSIX_TBL_BIR_MASK	0x0007	/* MSI-X table BIR mask */
941