14496171girish/*
24496171girish * CDDL HEADER START
34496171girish *
44496171girish * The contents of this file are subject to the terms of the
54496171girish * Common Development and Distribution License (the "License").
64496171girish * You may not use this file except in compliance with the License.
74496171girish *
84496171girish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
94496171girish * or http://www.opensolaris.org/os/licensing.
104496171girish * See the License for the specific language governing permissions
114496171girish * and limitations under the License.
124496171girish *
134496171girish * When distributing Covered Code, include this CDDL HEADER in each
144496171girish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
154496171girish * If applicable, add the following below this CDDL HEADER, with the
164496171girish * fields enclosed by brackets "[]" replaced with your own identifying
174496171girish * information: Portions Copyright [yyyy] [name of copyright owner]
184496171girish *
194496171girish * CDDL HEADER END
204496171girish */
214496171girish/*
224496171girish * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
234496171girish * Use is subject to license terms.
244496171girish */
254496171girish
264496171girish#ifndef	_SYS_NXGE_NXGE_ZCP_HW_H
274496171girish#define	_SYS_NXGE_NXGE_ZCP_HW_H
284496171girish
294496171girish#pragma ident	"%Z%%M%	%I%	%E% SMI"
304496171girish
314496171girish#ifdef	__cplusplus
324496171girishextern "C" {
334496171girish#endif
344496171girish
354496171girish#include <nxge_defs.h>
364496171girish
374496171girish/*
384496171girish * Neptune Zerocopy Hardware definitions
394496171girish * Updated to reflect PRM-0.8.
404496171girish */
414496171girish
424496171girish#define	ZCP_CONFIG_REG		(FZC_ZCP + 0x00000)
434496171girish#define	ZCP_INT_STAT_REG	(FZC_ZCP + 0x00008)
444496171girish#define	ZCP_INT_STAT_TEST_REG	(FZC_ZCP + 0x00108)
454496171girish#define	ZCP_INT_MASK_REG	(FZC_ZCP + 0x00010)
464496171girish
474496171girish#define	ZCP_BAM4_RE_CTL_REG 	(FZC_ZCP + 0x00018)
484496171girish#define	ZCP_BAM8_RE_CTL_REG 	(FZC_ZCP + 0x00020)
494496171girish#define	ZCP_BAM16_RE_CTL_REG 	(FZC_ZCP + 0x00028)
504496171girish#define	ZCP_BAM32_RE_CTL_REG 	(FZC_ZCP + 0x00030)
514496171girish
524496171girish#define	ZCP_DST4_RE_CTL_REG 	(FZC_ZCP + 0x00038)
534496171girish#define	ZCP_DST8_RE_CTL_REG 	(FZC_ZCP + 0x00040)
544496171girish#define	ZCP_DST16_RE_CTL_REG 	(FZC_ZCP + 0x00048)
554496171girish#define	ZCP_DST32_RE_CTL_REG 	(FZC_ZCP + 0x00050)
564496171girish
574496171girish#define	ZCP_RAM_DATA_REG	(FZC_ZCP + 0x00058)
584496171girish#define	ZCP_RAM_DATA0_REG	(FZC_ZCP + 0x00058)
594496171girish#define	ZCP_RAM_DATA1_REG	(FZC_ZCP + 0x00060)
604496171girish#define	ZCP_RAM_DATA2_REG	(FZC_ZCP + 0x00068)
614496171girish#define	ZCP_RAM_DATA3_REG	(FZC_ZCP + 0x00070)
624496171girish#define	ZCP_RAM_DATA4_REG	(FZC_ZCP + 0x00078)
634496171girish#define	ZCP_RAM_BE_REG		(FZC_ZCP + 0x00080)
644496171girish#define	ZCP_RAM_ACC_REG		(FZC_ZCP + 0x00088)
654496171girish
664496171girish#define	ZCP_TRAINING_VECTOR_REG	(FZC_ZCP + 0x000C0)
674496171girish#define	ZCP_STATE_MACHINE_REG	(FZC_ZCP + 0x000C8)
684496171girish#define	ZCP_CHK_BIT_DATA_REG	(FZC_ZCP + 0x00090)
694496171girish#define	ZCP_RESET_CFIFO_REG	(FZC_ZCP + 0x00098)
704496171girish#define	ZCP_RESET_CFIFO_MASK	0x0F
714496171girish
724496171girish#define	ZCP_CFIFIO_RESET_WAIT		10
734496171girish#define	ZCP_P0_P1_CFIFO_DEPTH		2048
744496171girish#define	ZCP_P2_P3_CFIFO_DEPTH		1024
754496171girish#define	ZCP_NIU_CFIFO_DEPTH		1024
764496171girish
774496171girishtypedef union _zcp_reset_cfifo {
784496171girish	uint64_t value;
794496171girish	struct {
804496171girish#if defined(_BIG_ENDIAN)
814496171girish		uint32_t hdw;
824496171girish#endif
834496171girish		struct {
844496171girish#if defined(_BIT_FIELDS_HTOL)
854496171girish			uint32_t rsrvd:28;
864496171girish			uint32_t reset_cfifo3:1;
874496171girish			uint32_t reset_cfifo2:1;
884496171girish			uint32_t reset_cfifo1:1;
894496171girish			uint32_t reset_cfifo0:1;
904496171girish#elif defined(_BIT_FIELDS_LTOH)
914496171girish			uint32_t reset_cfifo0:1;
924496171girish			uint32_t reset_cfifo1:1;
934496171girish			uint32_t reset_cfifo2:1;
944496171girish			uint32_t reset_cfifo3:1;
954496171girish			uint32_t rsrvd:28;
964496171girish#endif
974496171girish		} ldw;
984496171girish#if !defined(_BIG_ENDIAN)
994496171girish		uint32_t hdw;
1004496171girish#endif
1014496171girish	} bits;
1024496171girish} zcp_reset_cfifo_t, *p_zcp_reset_cfifo_t;
1034496171girish
1044496171girish#define	ZCP_CFIFO_ECC_PORT0_REG	(FZC_ZCP + 0x000A0)
1054496171girish#define	ZCP_CFIFO_ECC_PORT1_REG	(FZC_ZCP + 0x000A8)
1064496171girish#define	ZCP_CFIFO_ECC_PORT2_REG	(FZC_ZCP + 0x000B0)
1074496171girish#define	ZCP_CFIFO_ECC_PORT3_REG	(FZC_ZCP + 0x000B8)
1084496171girish
1094496171girish/* NOTE: Same as RX_LOG_PAGE_HDL */
1104496171girish#define	ZCP_PAGE_HDL_REG	(FZC_DMC + 0x20038)
1114496171girish
1124496171girish/* Data Structures */
1134496171girish
1144496171girishtypedef union zcp_config_reg_u {
1154496171girish	uint64_t value;
1164496171girish	struct {
1174496171girish#if defined(_BIG_ENDIAN)
1184496171girish		uint32_t hdw;
1194496171girish#endif
1204496171girish		struct {
1214496171girish#if defined(_BIT_FIELDS_HTOL)
1224496171girish			uint32_t rsvd:7;
1234496171girish			uint32_t mode_32_bit:1;
1244496171girish			uint32_t debug_sel:8;
1254496171girish			uint32_t rdma_th:11;
1264496171girish			uint32_t ecc_chk_dis:1;
1274496171girish			uint32_t par_chk_dis:1;
1284496171girish			uint32_t dis_buf_rn:1;
1294496171girish			uint32_t dis_buf_rq_if:1;
1304496171girish			uint32_t zc_enable:1;
1314496171girish#elif defined(_BIT_FIELDS_LTOH)
1324496171girish			uint32_t zc_enable:1;
1334496171girish			uint32_t dis_buf_rq_if:1;
1344496171girish			uint32_t dis_buf_rn:1;
1354496171girish			uint32_t par_chk_dis:1;
1364496171girish			uint32_t ecc_chk_dis:1;
1374496171girish			uint32_t rdma_th:11;
1384496171girish			uint32_t debug_sel:8;
1394496171girish			uint32_t mode_32_bit:1;
1404496171girish			uint32_t rsvd:7;
1414496171girish#endif
1424496171girish		} ldw;
1434496171girish#if !defined(_BIG_ENDIAN)
1444496171girish		uint32_t hdw;
1454496171girish#endif
1464496171girish	} bits;
1474496171girish} zcp_config_reg_t, *zcp_config_reg_pt;
1484496171girish
1494496171girish#define	ZCP_DEBUG_SEL_BITS	0xFF
1504496171girish#define	ZCP_DEBUG_SEL_SHIFT	16
1514496171girish#define	ZCP_DEBUG_SEL_MASK	(ZCP_DEBUG_SEL_BITS << ZCP_DEBUG_SEL_SHIFT)
1524496171girish#define	RDMA_TH_BITS		0x7FF
1534496171girish#define	RDMA_TH_SHIFT		5
1544496171girish#define	RDMA_TH_MASK		(RDMA_TH_BITS << RDMA_TH_SHIFT)
1554496171girish#define	ECC_CHK_DIS		(1 << 4)
1564496171girish#define	PAR_CHK_DIS		(1 << 3)
1574496171girish#define	DIS_BUFF_RN		(1 << 2)
1584496171girish#define	DIS_BUFF_RQ_IF		(1 << 1)
1594496171girish#define	ZC_ENABLE		(1 << 0)
1604496171girish
1614496171girishtypedef union zcp_int_stat_reg_u {
1624496171girish	uint64_t value;
1634496171girish	struct {
1644496171girish#if defined(_BIG_ENDIAN)
1654496171girish		uint32_t hdw;
1664496171girish#endif
1674496171girish		struct {
1684496171girish#if defined(_BIT_FIELDS_HTOL)
1694496171girish			uint32_t rsvd:16;
1704496171girish			uint32_t rrfifo_urun:1;
1714496171girish			uint32_t rrfifo_orun:1;
1724496171girish			uint32_t rsvd1:1;
1734496171girish			uint32_t rspfifo_uc_err:1;
1744496171girish			uint32_t buf_overflow:1;
1754496171girish			uint32_t stat_tbl_perr:1;
1764496171girish			uint32_t dyn_tbl_perr:1;
1774496171girish			uint32_t buf_tbl_perr:1;
1784496171girish			uint32_t tt_tbl_perr:1;
1794496171girish			uint32_t rsp_tt_index_err:1;
1804496171girish			uint32_t slv_tt_index_err:1;
1814496171girish			uint32_t zcp_tt_index_err:1;
1824496171girish			uint32_t cfifo_ecc3:1;
1834496171girish			uint32_t cfifo_ecc2:1;
1844496171girish			uint32_t cfifo_ecc1:1;
1854496171girish			uint32_t cfifo_ecc0:1;
1864496171girish#elif defined(_BIT_FIELDS_LTOH)
1874496171girish			uint32_t cfifo_ecc0:1;
1884496171girish			uint32_t cfifo_ecc1:1;
1894496171girish			uint32_t cfifo_ecc2:1;
1904496171girish			uint32_t cfifo_ecc3:1;
1914496171girish			uint32_t zcp_tt_index_err:1;
1924496171girish			uint32_t slv_tt_index_err:1;
1934496171girish			uint32_t rsp_tt_index_err:1;
1944496171girish			uint32_t tt_tbl_perr:1;
1954496171girish			uint32_t buf_tbl_perr:1;
1964496171girish			uint32_t dyn_tbl_perr:1;
1974496171girish			uint32_t stat_tbl_perr:1;
1984496171girish			uint32_t buf_overflow:1;
1994496171girish			uint32_t rspfifo_uc_err:1;
2004496171girish			uint32_t rsvd1:1;
2014496171girish			uint32_t rrfifo_orun:1;
2024496171girish			uint32_t rrfifo_urun:1;
2034496171girish			uint32_t rsvd:16;
2044496171girish#endif
2054496171girish		} ldw;
2064496171girish#if !defined(_BIG_ENDIAN)
2074496171girish		uint32_t hdw;
2084496171girish#endif
2094496171girish	} bits;
2104496171girish} zcp_int_stat_reg_t, *zcp_int_stat_reg_pt, zcp_int_mask_reg_t,
2114496171girish	*zcp_int_mask_reg_pt;
2124496171girish
2134496171girish#define	RRFIFO_UNDERRUN		(1 << 15)
2144496171girish#define	RRFIFO_OVERRUN		(1 << 14)
2154496171girish#define	RSPFIFO_UNCORR_ERR	(1 << 12)
2164496171girish#define	BUFFER_OVERFLOW		(1 << 11)
2174496171girish#define	STAT_TBL_PERR		(1 << 10)
2184496171girish#define	BUF_DYN_TBL_PERR	(1 << 9)
2194496171girish#define	BUF_TBL_PERR		(1 << 8)
2204496171girish#define	TT_PROGRAM_ERR		(1 << 7)
2214496171girish#define	RSP_TT_INDEX_ERR	(1 << 6)
2224496171girish#define	SLV_TT_INDEX_ERR	(1 << 5)
2234496171girish#define	ZCP_TT_INDEX_ERR	(1 << 4)
2244496171girish#define	CFIFO_ECC3		(1 << 3)
2254496171girish#define	CFIFO_ECC0		(1 << 0)
2264496171girish#define	CFIFO_ECC2		(1 << 2)
2274496171girish#define	CFIFO_ECC1		(1 << 1)
2284496171girish
2294496171girishtypedef union zcp_bam_region_reg_u {
2304496171girish	uint64_t value;
2314496171girish	struct {
2324496171girish#if defined(_BIG_ENDIAN)
2334496171girish		uint32_t hdw;
2344496171girish#endif
2354496171girish		struct {
2364496171girish#if defined(_BIT_FIELDS_HTOL)
2374496171girish			uint32_t loj:1;
2384496171girish			uint32_t range_chk_en:1;
2394496171girish			uint32_t last_zcfid:10;
2404496171girish			uint32_t first_zcfid:10;
2414496171girish			uint32_t offset:10;
2424496171girish#elif defined(_BIT_FIELDS_LTOH)
2434496171girish			uint32_t offset:10;
2444496171girish			uint32_t first_zcfid:10;
2454496171girish			uint32_t last_zcfid:10;
2464496171girish			uint32_t range_chk_en:1;
2474496171girish			uint32_t loj:1;
2484496171girish#endif
2494496171girish		} ldw;
2504496171girish#if !defined(_BIG_ENDIAN)
2514496171girish		uint32_t hdw;
2524496171girish#endif
2534496171girish	} bits;
2544496171girish} zcp_bam_region_reg_t, *zcp_bam_region_reg_pt;
2554496171girish
2564496171girishtypedef union zcp_dst_region_reg_u {
2574496171girish	uint64_t value;
2584496171girish	struct {
2594496171girish#if defined(_BIG_ENDIAN)
2604496171girish		uint32_t hdw;
2614496171girish#endif
2624496171girish		struct {
2634496171girish#if defined(_BIT_FIELDS_HTOL)
2644496171girish			uint32_t rsvd:22;
2654496171girish			uint32_t ds_offset:10;
2664496171girish#elif defined(_BIT_FIELDS_LTOH)
2674496171girish			uint32_t rsvd:22;
2684496171girish			uint32_t ds_offset:10;
2694496171girish#endif
2704496171girish		} ldw;
2714496171girish#if !defined(_BIG_ENDIAN)
2724496171girish		uint32_t hdw;
2734496171girish#endif
2744496171girish	} bits;
2754496171girish} zcp_dst_region_reg_t, *zcp_dst_region_reg_pt;
2764496171girish
2774496171girishtypedef	enum tbuf_size_e {
2784496171girish	TBUF_4K		= 0,
2794496171girish	TBUF_8K,
2804496171girish	TBUF_16K,
2814496171girish	TBUF_32K,
2824496171girish	TBUF_64K,
2834496171girish	TBUF_128K,
2844496171girish	TBUF_256K,
2854496171girish	TBUF_512K,
2864496171girish	TBUF_1M,
2874496171girish	TBUF_2M,
2884496171girish	TBUF_4M,
2894496171girish	TBUF_8M
2904496171girish} tbuf_size_t;
2914496171girish
2924496171girishtypedef	enum tbuf_num_e {
2934496171girish	TBUF_NUM_4	= 0,
2944496171girish	TBUF_NUM_8,
2954496171girish	TBUF_NUM_16,
2964496171girish	TBUF_NUM_32
2974496171girish} tbuf_num_t;
2984496171girish
2994496171girishtypedef	enum tmode_e {
3004496171girish	TMODE_BASIC		= 0,
3014496171girish	TMODE_AUTO_UNMAP	= 1,
3024496171girish	TMODE_AUTO_ADV		= 3
3034496171girish} tmode_t;
3044496171girish
3054496171girishtypedef	struct tte_sflow_attr_s {
3064496171girish	union {
3074496171girish		uint64_t value;
3084496171girish		struct {
3094496171girish#if defined(_BIG_ENDIAN)
3104496171girish			uint32_t hdw;
3114496171girish#endif
3124496171girish			struct {
3134496171girish#if defined(_BIT_FIELDS_HTOL)
3144496171girish				uint32_t ulp_end:18;
3154496171girish				uint32_t num_buf:2;
3164496171girish				uint32_t buf_size:4;
3174496171girish				uint32_t rdc_tbl_offset:8;
3184496171girish#elif defined(_BIT_FIELDS_LTOH)
3194496171girish				uint32_t rdc_tbl_offset:8;
3204496171girish				uint32_t buf_size:4;
3214496171girish				uint32_t num_buf:2;
3224496171girish				uint32_t ulp_end:18;
3234496171girish#endif
3244496171girish			} ldw;
3254496171girish#if !defined(_BIG_ENDIAN)
3264496171girish			uint32_t hdw;
3274496171girish#endif
3284496171girish		} bits;
3294496171girish	} qw0;
3304496171girish
3314496171girish	union {
3324496171girish		uint64_t value;
3334496171girish		struct {
3344496171girish#if defined(_BIG_ENDIAN)
3354496171girish			uint32_t hdw;
3364496171girish#endif
3374496171girish			struct {
3384496171girish#if defined(_BIT_FIELDS_HTOL)
3394496171girish				uint32_t ring_base:12;
3404496171girish				uint32_t skip:1;
3414496171girish				uint32_t rsvd:1;
3424496171girish				uint32_t tmode:2;
3434496171girish				uint32_t unmap_all_en:1;
3444496171girish				uint32_t ulp_end_en:1;
3454496171girish				uint32_t ulp_end:14;
3464496171girish#elif defined(_BIT_FIELDS_LTOH)
3474496171girish				uint32_t ulp_end:14;
3484496171girish				uint32_t ulp_end_en:1;
3494496171girish				uint32_t unmap_all_en:1;
3504496171girish				uint32_t tmode:2;
3514496171girish				uint32_t rsvd:1;
3524496171girish				uint32_t skip:1;
3534496171girish				uint32_t ring_base:12;
3544496171girish#endif
3554496171girish			} ldw;
3564496171girish#if !defined(_BIG_ENDIAN)
3574496171girish		uint32_t hdw;
3584496171girish#endif
3594496171girish		} bits;
3604496171girish	} qw1;
3614496171girish
3624496171girish	union {
3634496171girish		uint64_t value;
3644496171girish		struct {
3654496171girish#if defined(_BIG_ENDIAN)
3664496171girish			uint32_t hdw;
3674496171girish#endif
3684496171girish			struct {
3694496171girish#if defined(_BIT_FIELDS_HTOL)
3704496171girish				uint32_t busy:1;
3714496171girish				uint32_t ring_size:4;
3724496171girish				uint32_t ring_base:27;
3734496171girish#elif defined(_BIT_FIELDS_LTOH)
3744496171girish				uint32_t ring_base:27;
3754496171girish				uint32_t ring_size:4;
3764496171girish				uint32_t busy:1;
3774496171girish#endif
3784496171girish			} ldw;
3794496171girish#if !defined(_BIG_ENDIAN)
3804496171girish			uint32_t hdw;
3814496171girish#endif
3824496171girish		} bits;
3834496171girish	} qw2;
3844496171girish
3854496171girish	union {
3864496171girish		uint64_t value;
3874496171girish		struct {
3884496171girish#if defined(_BIG_ENDIAN)
3894496171girish			uint32_t hdw;
3904496171girish#endif
3914496171girish			struct {
3924496171girish#if defined(_BIT_FIELDS_HTOL)
3934496171girish				uint32_t rsvd:16;
3944496171girish				uint32_t toq:16;
3954496171girish#elif defined(_BIT_FIELDS_LTOH)
3964496171girish				uint32_t toq:16;
3974496171girish				uint32_t rsvd:16;
3984496171girish#endif
3994496171girish			} ldw;
4004496171girish#if !defined(_BIG_ENDIAN)
4014496171girish			uint32_t hdw;
4024496171girish#endif
4034496171girish		} bits;
4044496171girish	} qw3;
4054496171girish
4064496171girish	union {
4074496171girish		uint64_t value;
4084496171girish		struct {
4094496171girish#if defined(_BIG_ENDIAN)
4104496171girish			uint32_t hdw;
4114496171girish#endif
4124496171girish			struct {
4134496171girish#if defined(_BIT_FIELDS_HTOL)
4144496171girish				uint32_t rsvd:28;
4154496171girish				uint32_t dat4:4;
4164496171girish#elif defined(_BIT_FIELDS_LTOH)
4174496171girish				uint32_t dat4:4;
4184496171girish				uint32_t rsvd:28;
4194496171girish#endif
4204496171girish			} ldw;
4214496171girish#if !defined(_BIG_ENDIAN)
4224496171girish			uint32_t hdw;
4234496171girish#endif
4244496171girish		} bits;
4254496171girish	} qw4;
4264496171girish
4274496171girish} tte_sflow_attr_t, *tte_sflow_attr_pt;
4284496171girish
4294496171girish#define	TTE_RDC_TBL_SFLOW_BITS_EN	0x0001
4304496171girish#define	TTE_BUF_SIZE_BITS_EN		0x0002
4314496171girish#define	TTE_NUM_BUF_BITS_EN		0x0002
4324496171girish#define	TTE_ULP_END_BITS_EN		0x003E
4334496171girish#define	TTE_ULP_END_EN_BITS_EN		0x0020
4344496171girish#define	TTE_UNMAP_ALL_BITS_EN		0x0020
4354496171girish#define	TTE_TMODE_BITS_EN		0x0040
4364496171girish#define	TTE_SKIP_BITS_EN		0x0040
4374496171girish#define	TTE_RING_BASE_ADDR_BITS_EN	0x0FC0
4384496171girish#define	TTE_RING_SIZE_BITS_EN		0x0800
4394496171girish#define	TTE_BUSY_BITS_EN		0x0800
4404496171girish#define	TTE_TOQ_BITS_EN			0x3000
4414496171girish
4424496171girish#define	TTE_MAPPED_IN_BITS_EN		0x0000F
4434496171girish#define	TTE_ANCHOR_SEQ_BITS_EN		0x000F0
4444496171girish#define	TTE_ANCHOR_OFFSET_BITS_EN	0x00700
4454496171girish#define	TTE_ANCHOR_BUFFER_BITS_EN	0x00800
4464496171girish#define	TTE_ANCHOR_BUF_FLAG_BITS_EN	0x00800
4474496171girish#define	TTE_UNMAP_ON_LEFT_BITS_EN	0x00800
4484496171girish#define	TTE_ULP_END_REACHED_BITS_EN	0x00800
4494496171girish#define	TTE_ERR_STAT_BITS_EN		0x01000
4504496171girish#define	TTE_WR_PTR_BITS_EN		0x01000
4514496171girish#define	TTE_HOQ_BITS_EN			0x0E000
4524496171girish#define	TTE_PREFETCH_ON_BITS_EN		0x08000
4534496171girish
4544496171girishtypedef	enum tring_size_e {
4554496171girish	TRING_SIZE_8		= 0,
4564496171girish	TRING_SIZE_16,
4574496171girish	TRING_SIZE_32,
4584496171girish	TRING_SIZE_64,
4594496171girish	TRING_SIZE_128,
4604496171girish	TRING_SIZE_256,
4614496171girish	TRING_SIZE_512,
4624496171girish	TRING_SIZE_1K,
4634496171girish	TRING_SIZE_2K,
4644496171girish	TRING_SIZE_4K,
4654496171girish	TRING_SIZE_8K,
4664496171girish	TRING_SIZE_16K,
4674496171girish	TRING_SIZE_32K
4684496171girish} tring_size_t;
4694496171girish
4704496171girishtypedef struct tte_dflow_attr_s {
4714496171girish	union {
4724496171girish		uint64_t value;
4734496171girish		struct {
4744496171girish#if defined(_BIG_ENDIAN)
4754496171girish			uint32_t hdw;
4764496171girish#endif
4774496171girish			struct {
4784496171girish#if defined(_BIT_FIELDS_HTOL)
4794496171girish				uint32_t mapped_in;
4804496171girish#elif defined(_BIT_FIELDS_LTOH)
4814496171girish				uint32_t mapped_in;
4824496171girish#endif
4834496171girish			} ldw;
4844496171girish#if !defined(_BIG_ENDIAN)
4854496171girish			uint32_t hdw;
4864496171girish#endif
4874496171girish		} bits;
4884496171girish	} qw0;
4894496171girish
4904496171girish	union {
4914496171girish		uint64_t value;
4924496171girish		struct {
4934496171girish#if defined(_BIG_ENDIAN)
4944496171girish			uint32_t hdw;
4954496171girish#endif
4964496171girish			struct {
4974496171girish#if defined(_BIT_FIELDS_HTOL)
4984496171girish				uint32_t anchor_seq;
4994496171girish#elif defined(_BIT_FIELDS_LTOH)
5004496171girish				uint32_t anchor_seq;
5014496171girish#endif
5024496171girish			} ldw;
5034496171girish#if !defined(_BIG_ENDIAN)
5044496171girish			uint32_t hdw;
5054496171girish#endif
5064496171girish		} bits;
5074496171girish	} qw1;
5084496171girish
5094496171girish	union {
5104496171girish		uint64_t value;
5114496171girish		struct {
5124496171girish#if defined(_BIG_ENDIAN)
5134496171girish			uint32_t hdw;
5144496171girish#endif
5154496171girish			struct {
5164496171girish#if defined(_BIT_FIELDS_HTOL)
5174496171girish				uint32_t ulp_end_reached;
5184496171girish				uint32_t unmap_on_left;
5194496171girish				uint32_t anchor_buf_flag;
5204496171girish				uint32_t anchor_buf:5;
5214496171girish				uint32_t anchor_offset:24;
5224496171girish#elif defined(_BIT_FIELDS_LTOH)
5234496171girish				uint32_t anchor_offset:24;
5244496171girish				uint32_t anchor_buf:5;
5254496171girish				uint32_t anchor_buf_flag;
5264496171girish				uint32_t unmap_on_left;
5274496171girish				uint32_t ulp_end_reached;
5284496171girish#endif
5294496171girish			} ldw;
5304496171girish#if !defined(_BIG_ENDIAN)
5314496171girish		uint32_t hdw;
5324496171girish#endif
5334496171girish		} bits;
5344496171girish	} qw2;
5354496171girish
5364496171girish	union {
5374496171girish		uint64_t value;
5384496171girish		struct {
5394496171girish#if defined(_BIG_ENDIAN)
5404496171girish			uint32_t hdw;
5414496171girish#endif
5424496171girish			struct {
5434496171girish#if defined(_BIT_FIELDS_HTOL)
5444496171girish				uint32_t rsvd1:1;
5454496171girish				uint32_t prefetch_on:1;
5464496171girish				uint32_t hoq:16;
5474496171girish				uint32_t rsvd:6;
5484496171girish				uint32_t wr_ptr:6;
5494496171girish				uint32_t err_stat:2;
5504496171girish#elif defined(_BIT_FIELDS_LTOH)
5514496171girish				uint32_t err_stat:2;
5524496171girish				uint32_t wr_ptr:6;
5534496171girish				uint32_t rsvd:6;
5544496171girish				uint32_t hoq:16;
5554496171girish				uint32_t prefetch_on:1;
5564496171girish				uint32_t rsvd1:1;
5574496171girish#endif
5584496171girish			} ldw;
5594496171girish#if !defined(_BIG_ENDIAN)
5604496171girish			uint32_t hdw;
5614496171girish#endif
5624496171girish		} bits;
5634496171girish	} qw3;
5644496171girish
5654496171girish	union {
5664496171girish		uint64_t value;
5674496171girish		struct {
5684496171girish#if defined(_BIG_ENDIAN)
5694496171girish			uint32_t hdw;
5704496171girish#endif
5714496171girish			struct {
5724496171girish#if defined(_BIT_FIELDS_HTOL)
5734496171girish				uint32_t rsvd:28;
5744496171girish				uint32_t dat4:4;
5754496171girish#elif defined(_BIT_FIELDS_LTOH)
5764496171girish				uint32_t dat4:4;
5774496171girish				uint32_t rsvd:28;
5784496171girish#endif
5794496171girish			} ldw;
5804496171girish#if !defined(_BIG_ENDIAN)
5814496171girish			uint32_t hdw;
5824496171girish#endif
5834496171girish		} bits;
5844496171girish	} qw4;
5854496171girish
5864496171girish} tte_dflow_attr_t, *tte_dflow_attr_pt;
5874496171girish
5884496171girish#define	MAX_BAM_BANKS	8
5894496171girish
5904496171girishtypedef	struct zcp_ram_unit_s {
5914496171girish	uint32_t	w0;
5924496171girish	uint32_t	w1;
5934496171girish	uint32_t	w2;
5944496171girish	uint32_t	w3;
5954496171girish	uint32_t	w4;
5964496171girish} zcp_ram_unit_t;
5974496171girish
5984496171girishtypedef	enum dmaw_type_e {
5994496171girish	DMAW_NO_CROSS_BUF	= 0,
6004496171girish	DMAW_IP_CROSS_BUF_2,
6014496171girish	DMAW_IP_CROSS_BUF_3,
6024496171girish	DMAW_IP_CROSS_BUF_4
6034496171girish} dmaw_type_t;
6044496171girish
6054496171girishtypedef union zcp_ram_data_u {
6064496171girish	tte_sflow_attr_t sentry;
6074496171girish	tte_dflow_attr_t dentry;
6084496171girish} zcp_ram_data_t, *zcp_ram_data_pt;
6094496171girish
6104496171girishtypedef union zcp_ram_access_u {
6114496171girish	uint64_t value;
6124496171girish	struct {
6134496171girish#if defined(_BIG_ENDIAN)
6144496171girish		uint32_t hdw;
6154496171girish#endif
6164496171girish		struct {
6174496171girish#if defined(_BIT_FIELDS_HTOL)
6184496171girish			uint32_t busy:1;
6194496171girish			uint32_t rdwr:1;
6204496171girish			uint32_t rsvd:1;
6214496171girish			uint32_t zcfid:12;
6224496171girish			uint32_t ram_sel:5;
6234496171girish			uint32_t cfifo:12;
6244496171girish#elif defined(_BIT_FIELDS_LTOH)
6254496171girish			uint32_t cfifo:12;
6264496171girish			uint32_t ram_sel:5;
6274496171girish			uint32_t zcfid:12;
6284496171girish			uint32_t rsvd:1;
6294496171girish			uint32_t rdwr:1;
6304496171girish			uint32_t busy:1;
6314496171girish#endif
6324496171girish		} ldw;
6334496171girish#if !defined(_BIG_ENDIAN)
6344496171girish		uint32_t hdw;
6354496171girish#endif
6364496171girish	} bits;
6374496171girish} zcp_ram_access_t, *zcp_ram_access_pt;
6384496171girish
6394496171girish#define	ZCP_RAM_WR		0
6404496171girish#define	ZCP_RAM_RD		1
6414496171girish#define	ZCP_RAM_SEL_BAM0	0
6424496171girish#define	ZCP_RAM_SEL_BAM1	0x1
6434496171girish#define	ZCP_RAM_SEL_BAM2	0x2
6444496171girish#define	ZCP_RAM_SEL_BAM3	0x3
6454496171girish#define	ZCP_RAM_SEL_BAM4	0x4
6464496171girish#define	ZCP_RAM_SEL_BAM5	0x5
6474496171girish#define	ZCP_RAM_SEL_BAM6	0x6
6484496171girish#define	ZCP_RAM_SEL_BAM7	0x7
6494496171girish#define	ZCP_RAM_SEL_TT_STATIC	0x8
6504496171girish#define	ZCP_RAM_SEL_TT_DYNAMIC	0x9
6514496171girish#define	ZCP_RAM_SEL_CFIFO0	0x10
6524496171girish#define	ZCP_RAM_SEL_CFIFO1	0x11
6534496171girish#define	ZCP_RAM_SEL_CFIFO2	0x12
6544496171girish#define	ZCP_RAM_SEL_CFIFO3	0x13
6554496171girish
6564496171girishtypedef union zcp_ram_benable_u {
6574496171girish	uint64_t value;
6584496171girish	struct {
6594496171girish#if defined(_BIG_ENDIAN)
6604496171girish		uint32_t hdw;
6614496171girish#endif
6624496171girish		struct {
6634496171girish#if defined(_BIT_FIELDS_HTOL)
6644496171girish			uint32_t rsvd:15;
6654496171girish			uint32_t be:17;
6664496171girish#elif defined(_BIT_FIELDS_LTOH)
6674496171girish			uint32_t be:17;
6684496171girish			uint32_t rsvd:15;
6694496171girish#endif
6704496171girish		} ldw;
6714496171girish#if !defined(_BIG_ENDIAN)
6724496171girish		uint32_t hdw;
6734496171girish#endif
6744496171girish	} bits;
6754496171girish} zcp_ram_benable_t, *zcp_ram_benable_pt;
6764496171girish
6774496171girishtypedef union zcp_training_vector_u {
6784496171girish	uint64_t value;
6794496171girish	struct {
6804496171girish#if defined(_BIG_ENDIAN)
6814496171girish		uint32_t hdw;
6824496171girish#endif
6834496171girish		struct {
6844496171girish#if defined(_BIT_FIELDS_HTOL)
6854496171girish			uint32_t train_vec;
6864496171girish#elif defined(_BIT_FIELDS_LTOH)
6874496171girish			uint32_t train_vec;
6884496171girish#endif
6894496171girish		} ldw;
6904496171girish#if !defined(_BIG_ENDIAN)
6914496171girish		uint32_t hdw;
6924496171girish#endif
6934496171girish	} bits;
6944496171girish} zcp_training_vector_t, *zcp_training_vector_pt;
6954496171girish
6964496171girishtypedef union zcp_state_machine_u {
6974496171girish	uint64_t value;
6984496171girish	struct {
6994496171girish#if defined(_BIG_ENDIAN)
7004496171girish		uint32_t hdw;
7014496171girish#endif
7024496171girish		struct {
7034496171girish#if defined(_BIT_FIELDS_HTOL)
7044496171girish			uint32_t state;
7054496171girish#elif defined(_BIT_FIELDS_LTOH)
7064496171girish			uint32_t state;
7074496171girish#endif
7084496171girish		} ldw;
7094496171girish#if !defined(_BIG_ENDIAN)
7104496171girish		uint32_t hdw;
7114496171girish#endif
7124496171girish	} bits;
7134496171girish} zcp_state_machine_t, *zcp_state_machine_pt;
7144496171girish
7154496171girishtypedef	struct zcp_hdr_s {
7164496171girish	uint16_t	zflowid;
7174496171girish	uint16_t	tcp_hdr_len;
7184496171girish	uint16_t	tcp_payld_len;
7194496171girish	uint16_t	head_of_que;
7204496171girish	uint32_t	first_b_offset;
7214496171girish	boolean_t	reach_buf_end;
7224496171girish	dmaw_type_t	dmaw_type;
7234496171girish	uint8_t		win_buf_offset;
7244496171girish} zcp_hdr_t;
7254496171girish
7264496171girishtypedef	union _zcp_ecc_ctrl {
7274496171girish	uint64_t value;
7284496171girish
7294496171girish	struct {
7304496171girish#if defined(_BIG_ENDIAN)
7314496171girish		uint32_t	w1;
7324496171girish#endif
7334496171girish		struct {
7344496171girish#if defined(_BIT_FIELDS_HTOL)
7354496171girish		uint32_t dis_dbl	: 1;
7364496171girish		uint32_t res3		: 13;
7374496171girish		uint32_t cor_dbl	: 1;
7384496171girish		uint32_t cor_sng	: 1;
7394496171girish		uint32_t res2		: 5;
7404496171girish		uint32_t cor_all	: 1;
7414496171girish		uint32_t res1		: 7;
7424496171girish		uint32_t cor_lst	: 1;
7434496171girish		uint32_t cor_snd	: 1;
7444496171girish		uint32_t cor_fst	: 1;
7454496171girish#elif defined(_BIT_FIELDS_LTOH)
7464496171girish		uint32_t cor_fst	: 1;
7474496171girish		uint32_t cor_snd	: 1;
7484496171girish		uint32_t cor_lst	: 1;
7494496171girish		uint32_t res1		: 7;
7504496171girish		uint32_t cor_all	: 1;
7514496171girish		uint32_t res2		: 5;
7524496171girish		uint32_t cor_sng	: 1;
7534496171girish		uint32_t cor_dbl	: 1;
7544496171girish		uint32_t res3		: 13;
7554496171girish		uint32_t dis_dbl	: 1;
7564496171girish#else
7574496171girish#error	one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
7584496171girish#endif
7594496171girish	} w0;
7604496171girish
7614496171girish#if !defined(_BIG_ENDIAN)
7624496171girish		uint32_t	w1;
7634496171girish#endif
7644496171girish	} bits;
7654496171girish} zcp_ecc_ctrl_t;
7664496171girish
7674496171girish#ifdef	__cplusplus
7684496171girish}
7694496171girish#endif
7704496171girish
7714496171girish#endif	/* _SYS_NXGE_NXGE_ZCP_HW_H */
772