1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#ifndef	_SYS_NXGE_NXGE_SR_HW_H
27#define	_SYS_NXGE_NXGE_SR_HW_H
28
29#pragma ident	"%Z%%M%	%I%	%E% SMI"
30
31#ifdef	__cplusplus
32extern "C" {
33#endif
34
35#define	ESR_NEPTUNE_DEV_ADDR	0x1E
36#define	ESR_NEPTUNE_BASE	0
37#define	ESR_PORT_ADDR_BASE	0
38#define	PCISR_DEV_ADDR		0x1E
39#define	PCISR_BASE		0
40#define	PCISR_PORT_ADDR_BASE	2
41
42#define	PB	0
43
44#define	SR_RX_TX_COMMON_CONTROL	PB + 0x000
45#define	SR_RX_TX_RESET_CONTROL	PB + 0x004
46#define	SR_RX_POWER_CONTROL	PB + 0x008
47#define	SR_TX_POWER_CONTROL	PB + 0x00C
48#define	SR_MISC_POWER_CONTROL	PB + 0x010
49#define	SR_RX_TX_CONTROL_A	PB + 0x100
50#define	SR_RX_TX_TUNING_A	PB + 0x104
51#define	SR_RX_SYNCCHAR_A	PB + 0x108
52#define	SR_RX_TX_TEST_A		PB + 0x10C
53#define	SR_GLUE_CONTROL0_A	PB + 0x110
54#define	SR_GLUE_CONTROL1_A	PB + 0x114
55#define	SR_RX_TX_CONTROL_B	PB + 0x120
56#define	SR_RX_TX_TUNING_B	PB + 0x124
57#define	SR_RX_SYNCCHAR_B	PB + 0x128
58#define	SR_RX_TX_TEST_B		PB + 0x12C
59#define	SR_GLUE_CONTROL0_B	PB + 0x130
60#define	SR_GLUE_CONTROL1_B	PB + 0x134
61#define	SR_RX_TX_CONTROL_C	PB + 0x140
62#define	SR_RX_TX_TUNING_C	PB + 0x144
63#define	SR_RX_SYNCCHAR_C	PB + 0x148
64#define	SR_RX_TX_TEST_C		PB + 0x14C
65#define	SR_GLUE_CONTROL0_C	PB + 0x150
66#define	SR_GLUE_CONTROL1_C	PB + 0x154
67#define	SR_RX_TX_CONTROL_D	PB + 0x160
68#define	SR_RX_TX_TUNING_D	PB + 0x164
69#define	SR_RX_SYNCCHAR_D	PB + 0x168
70#define	SR_RX_TX_TEST_D		PB + 0x16C
71#define	SR_GLUE_CONTROL0_D	PB + 0x170
72#define	SR_GLUE_CONTROL1_D	PB + 0x174
73#define	SR_RX_TX_TUNING_1_A	PB + 0x184
74#define	SR_RX_TX_TUNING_1_B	PB + 0x1A4
75#define	SR_RX_TX_TUNING_1_C	PB + 0x1C4
76#define	SR_RX_TX_TUNING_1_D	PB + 0x1E4
77#define	SR_RX_TX_TUNING_2_A	PB + 0x204
78#define	SR_RX_TX_TUNING_2_B	PB + 0x224
79#define	SR_RX_TX_TUNING_2_C	PB + 0x244
80#define	SR_RX_TX_TUNING_2_D	PB + 0x264
81#define	SR_RX_TX_TUNING_3_A	PB + 0x284
82#define	SR_RX_TX_TUNING_3_B	PB + 0x2A4
83#define	SR_RX_TX_TUNING_3_C	PB + 0x2C4
84#define	SR_RX_TX_TUNING_3_D	PB + 0x2E4
85
86/*
87 * Shift right by 1 because the PRM requires that all the serdes register
88 * address be divided by 2
89 */
90#define	ESR_NEP_RX_TX_COMMON_CONTROL_L_ADDR()	(ESR_NEPTUNE_BASE +\
91						(SR_RX_TX_COMMON_CONTROL >> 1))
92#define	ESR_NEP_RX_TX_COMMON_CONTROL_H_ADDR()	(ESR_NEPTUNE_BASE +\
93						(SR_RX_TX_COMMON_CONTROL >> 1)\
94						+ 1)
95#define	ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR()	(ESR_NEPTUNE_BASE +\
96						(SR_RX_TX_RESET_CONTROL >> 1))
97#define	ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR()	(ESR_NEPTUNE_BASE +\
98						(SR_RX_TX_RESET_CONTROL >> 1)\
99						+ 1)
100#define	ESR_NEP_RX_POWER_CONTROL_L_ADDR()	(ESR_NEPTUNE_BASE +\
101						(SR_RX_POWER_CONTROL >> 1))
102#define	ESR_NEP_RX_POWER_CONTROL_H_ADDR()	(ESR_NEPTUNE_BASE +\
103						(SR_RX_POWER_CONTROL >> 1) + 1)
104#define	ESR_NEP_TX_POWER_CONTROL_L_ADDR()	(ESR_NEPTUNE_BASE +\
105						(SR_TX_POWER_CONTROL >> 1))
106#define	ESR_NEP_TX_POWER_CONTROL_H_ADDR()	(ESR_NEPTUNE_BASE +\
107						(SR_TX_POWER_CONTROL >> 1) + 1)
108#define	ESR_NEP_MISC_POWER_CONTROL_L_ADDR()	(ESR_NEPTUNE_BASE +\
109						(SR_MISC_POWER_CONTROL >> 1))
110#define	ESR_NEP_MISC_POWER_CONTROL_H_ADDR()	(ESR_NEPTUNE_BASE +\
111						(SR_MISC_POWER_CONTROL >> 1)\
112						+ 1)
113#define	ESR_NEP_RX_TX_CONTROL_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
114						SR_RX_TX_CONTROL_A +\
115						(chan * 0x20)) >> 1)
116#define	ESR_NEP_RX_TX_CONTROL_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
117						SR_RX_TX_CONTROL_A +\
118						(chan * 0x20)) >> 1) + 1
119#define	ESR_NEP_RX_TX_TUNING_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
120						SR_RX_TX_TUNING_A +\
121						(chan * 0x20)) >> 1)
122#define	ESR_NEP_RX_TX_TUNING_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
123						SR_RX_TX_TUNING_A +\
124						(chan * 0x20)) >> 1) + 1
125#define	ESR_NEP_RX_TX_SYNCCHAR_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
126						SR_RX_SYNCCHAR_A +\
127						(chan * 0x20)) >> 1)
128#define	ESR_NEP_RX_TX_SYNCCHAR_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
129						SR_RX_SYNCCHAR_A +\
130						(chan * 0x20)) >> 1) + 1
131#define	ESR_NEP_RX_TX_TEST_L_ADDR(chan)		((ESR_NEPTUNE_BASE +\
132						SR_RX_TX_TEST_A +\
133						(chan * 0x20)) >> 1)
134#define	ESR_NEP_RX_TX_TEST_H_ADDR(chan)		((ESR_NEPTUNE_BASE +\
135						SR_RX_TX_TEST_A +\
136						(chan * 0x20)) >> 1) + 1
137#define	ESR_NEP_GLUE_CONTROL0_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
138						SR_GLUE_CONTROL0_A +\
139						(chan * 0x20)) >> 1)
140#define	ESR_NEP_GLUE_CONTROL0_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
141						SR_GLUE_CONTROL0_A +\
142						(chan * 0x20)) >> 1) + 1
143#define	ESR_NEP_GLUE_CONTROL1_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
144						SR_GLUE_CONTROL1_A +\
145						(chan * 0x20)) >> 1)
146#define	ESR_NEP_GLUE_CONTROL1_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
147						SR_GLUE_CONTROL1_A +\
148						(chan * 0x20)) >> 1) + 1
149#define	ESR_NEP_RX_TX_TUNING_1_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
150						SR_RX_TX_TUNING_1_A +\
151						(chan * 0x20)) >> 1)
152#define	ESR_NEP_RX_TX_TUNING_1_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
153						SR_RX_TX_TUNING_1_A +\
154						(chan * 0x20)) >> 1) + 1
155#define	ESR_NEP_RX_TX_TUNING_2_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
156						SR_RX_TX_TUNING_2_A +\
157						(chan * 0x20)) >> 1)
158#define	ESR_NEP_RX_TX_TUNING_2_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
159						SR_RX_TX_TUNING_2_A +\
160						(chan * 0x20)) >> 1) + 1
161#define	ESR_NEP_RX_TX_TUNING_3_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
162						SR_RX_TX_TUNING_3_A +\
163						(chan * 0x20)) >> 1)
164#define	ESR_NEP_RX_TX_TUNING_3_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
165						SR_RX_TX_TUNING_3_A +\
166						(chan * 0x20)) >> 1) + 1
167
168typedef	union _sr_rx_tx_common_ctrl_l {
169	uint16_t value;
170	struct {
171#if defined(_BIT_FIELDS_HTOL)
172		uint16_t res3		: 3;
173		uint16_t refclkr_freq	: 5;
174		uint16_t res4		: 8;
175#elif defined(_BIT_FIELDS_LTOH)
176		uint16_t res4		: 8;
177		uint16_t refclkr_freq	: 5;
178		uint16_t res3		: 3;
179#else
180#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
181#endif
182	} bits;
183} sr_rx_tx_common_ctrl_l;
184
185typedef	union _sr_rx_tx_common_ctrl_h {
186	uint16_t value;
187	struct {
188#if defined(_BIT_FIELDS_HTOL)
189		uint16_t res1		: 5;
190		uint16_t tdmaster	: 3;
191		uint16_t tp		: 2;
192		uint16_t tz		: 2;
193		uint16_t res2		: 2;
194		uint16_t revlbrefsel	: 2;
195#elif defined(_BIT_FIELDS_LTOH)
196		uint16_t revlbrefsel	: 2;
197		uint16_t res2		: 2;
198		uint16_t tz		: 2;
199		uint16_t tp		: 2;
200		uint16_t tdmaster	: 3;
201		uint16_t res1		: 5;
202#else
203#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
204#endif
205	} bits;
206} sr_rx_tx_common_ctrl_h;
207
208
209/* RX TX Common Control Register field values */
210
211#define	TDMASTER_LANE_A		0
212#define	TDMASTER_LANE_B		1
213#define	TDMASTER_LANE_C		2
214#define	TDMASTER_LANE_D		3
215
216#define	REVLBREFSEL_GBT_RBC_A_O		0
217#define	REVLBREFSEL_GBT_RBC_B_O		1
218#define	REVLBREFSEL_GBT_RBC_C_O		2
219#define	REVLBREFSEL_GBT_RBC_D_O		3
220
221#define	REFCLKR_FREQ_SIM		0
222#define	REFCLKR_FREQ_53_125		0x1
223#define	REFCLKR_FREQ_62_5		0x3
224#define	REFCLKR_FREQ_70_83		0x4
225#define	REFCLKR_FREQ_75			0x5
226#define	REFCLKR_FREQ_78_125		0x6
227#define	REFCLKR_FREQ_79_6875		0x7
228#define	REFCLKR_FREQ_83_33		0x8
229#define	REFCLKR_FREQ_85			0x9
230#define	REFCLKR_FREQ_100		0xA
231#define	REFCLKR_FREQ_104_17		0xB
232#define	REFCLKR_FREQ_106_25		0xC
233#define	REFCLKR_FREQ_120		0xF
234#define	REFCLKR_FREQ_125		0x10
235#define	REFCLKR_FREQ_127_5		0x11
236#define	REFCLKR_FREQ_141_67		0x13
237#define	REFCLKR_FREQ_150		0x15
238#define	REFCLKR_FREQ_156_25		0x16
239#define	REFCLKR_FREQ_159_375		0x17
240#define	REFCLKR_FREQ_170		0x19
241#define	REFCLKR_FREQ_212_5		0x1E
242
243typedef	union _sr_rx_tx_reset_ctrl_l {
244	uint16_t value;
245	struct {
246#if defined(_BIT_FIELDS_HTOL)
247		uint16_t rxreset_0a	: 1;
248		uint16_t rxreset_0b	: 1;
249		uint16_t rxreset_0c	: 1;
250		uint16_t rxreset_0d	: 1;
251		uint16_t rxreset_1a	: 1;
252		uint16_t rxreset_1b	: 1;
253		uint16_t rxreset_1c	: 1;
254		uint16_t rxreset_1d	: 1;
255		uint16_t rxreset_2a	: 1;
256		uint16_t rxreset_2b	: 1;
257		uint16_t rxreset_2c	: 1;
258		uint16_t rxreset_2d	: 1;
259		uint16_t rxreset_3a	: 1;
260		uint16_t rxreset_3b	: 1;
261		uint16_t rxreset_3c	: 1;
262		uint16_t rxreset_3d	: 1;
263#elif defined(_BIT_FIELDS_LTOH)
264		uint16_t rxreset_3d	: 1;
265		uint16_t rxreset_3c	: 1;
266		uint16_t rxreset_3b	: 1;
267		uint16_t rxreset_3a	: 1;
268		uint16_t rxreset_2d	: 1;
269		uint16_t rxreset_2c	: 1;
270		uint16_t rxreset_2b	: 1;
271		uint16_t rxreset_2a	: 1;
272		uint16_t rxreset_1d	: 1;
273		uint16_t rxreset_1c	: 1;
274		uint16_t rxreset_1b	: 1;
275		uint16_t rxreset_1a	: 1;
276		uint16_t rxreset_0d	: 1;
277		uint16_t rxreset_0c	: 1;
278		uint16_t rxreset_0b	: 1;
279		uint16_t rxreset_0a	: 1;
280#else
281#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
282#endif
283	} bits;
284} sr_rx_tx_reset_ctrl_l;
285
286
287typedef	union _sr_rx_tx_reset_ctrl_h {
288	uint16_t value;
289	struct {
290#if defined(_BIT_FIELDS_HTOL)
291		uint16_t txreset_0a	: 1;
292		uint16_t txreset_0b	: 1;
293		uint16_t txreset_0c	: 1;
294		uint16_t txreset_0d	: 1;
295		uint16_t txreset_1a	: 1;
296		uint16_t txreset_1b	: 1;
297		uint16_t txreset_1c	: 1;
298		uint16_t txreset_1d	: 1;
299		uint16_t txreset_2a	: 1;
300		uint16_t txreset_2b	: 1;
301		uint16_t txreset_2c	: 1;
302		uint16_t txreset_2d	: 1;
303		uint16_t txreset_3a	: 1;
304		uint16_t txreset_3b	: 1;
305		uint16_t txreset_3c	: 1;
306		uint16_t txreset_3d	: 1;
307#elif defined(_BIT_FIELDS_LTOH)
308		uint16_t txreset_3d	: 1;
309		uint16_t txreset_3c	: 1;
310		uint16_t txreset_3b	: 1;
311		uint16_t txreset_3a	: 1;
312		uint16_t txreset_2d	: 1;
313		uint16_t txreset_2c	: 1;
314		uint16_t txreset_2b	: 1;
315		uint16_t txreset_2a	: 1;
316		uint16_t txreset_1d	: 1;
317		uint16_t txreset_1c	: 1;
318		uint16_t txreset_1b	: 1;
319		uint16_t txreset_1a	: 1;
320		uint16_t txreset_0d	: 1;
321		uint16_t txreset_0c	: 1;
322		uint16_t txreset_0b	: 1;
323		uint16_t txreset_0a	: 1;
324#else
325#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
326#endif
327	} bits;
328} sr_rx_tx_reset_ctrl_h;
329
330typedef	union _sr_rx_power_ctrl_l {
331	uint16_t value;
332	struct {
333#if defined(_BIT_FIELDS_HTOL)
334		uint16_t pdrxlos_0a	: 1;
335		uint16_t pdrxlos_0b	: 1;
336		uint16_t pdrxlos_0c	: 1;
337		uint16_t pdrxlos_0d	: 1;
338		uint16_t pdrxlos_1a	: 1;
339		uint16_t pdrxlos_1b	: 1;
340		uint16_t pdrxlos_1c	: 1;
341		uint16_t pdrxlos_1d	: 1;
342		uint16_t pdrxlos_2a	: 1;
343		uint16_t pdrxlos_2b	: 1;
344		uint16_t pdrxlos_2c	: 1;
345		uint16_t pdrxlos_2d	: 1;
346		uint16_t pdrxlos_3a	: 1;
347		uint16_t pdrxlos_3b	: 1;
348		uint16_t pdrxlos_3c	: 1;
349		uint16_t pdrxlos_3d	: 1;
350#elif defined(_BIT_FIELDS_LTOH)
351		uint16_t pdrxlos_3d	: 1;
352		uint16_t pdrxlos_3c	: 1;
353		uint16_t pdrxlos_3b	: 1;
354		uint16_t pdrxlos_3a	: 1;
355		uint16_t pdrxlos_2d	: 1;
356		uint16_t pdrxlos_2c	: 1;
357		uint16_t pdrxlos_2b	: 1;
358		uint16_t pdrxlos_2a	: 1;
359		uint16_t pdrxlos_1d	: 1;
360		uint16_t pdrxlos_1c	: 1;
361		uint16_t pdrxlos_1b	: 1;
362		uint16_t pdrxlos_1a	: 1;
363		uint16_t pdrxlos_0d	: 1;
364		uint16_t pdrxlos_0c	: 1;
365		uint16_t pdrxlos_0b	: 1;
366		uint16_t pdrxlos_0a	: 1;
367#else
368#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
369#endif
370	} bits;
371} sr_rx_power_ctrl_l_t;
372
373
374typedef	union _sr_rx_power_ctrl_h {
375	uint16_t value;
376	struct {
377#if defined(_BIT_FIELDS_HTOL)
378		uint16_t pdownr_0a	: 1;
379		uint16_t pdownr_0b	: 1;
380		uint16_t pdownr_0c	: 1;
381		uint16_t pdownr_0d	: 1;
382		uint16_t pdownr_1a	: 1;
383		uint16_t pdownr_1b	: 1;
384		uint16_t pdownr_1c	: 1;
385		uint16_t pdownr_1d	: 1;
386		uint16_t pdownr_2a	: 1;
387		uint16_t pdownr_2b	: 1;
388		uint16_t pdownr_2c	: 1;
389		uint16_t pdownr_2d	: 1;
390		uint16_t pdownr_3a	: 1;
391		uint16_t pdownr_3b	: 1;
392		uint16_t pdownr_3c	: 1;
393		uint16_t pdownr_3d	: 1;
394#elif defined(_BIT_FIELDS_LTOH)
395		uint16_t pdownr_3d	: 1;
396		uint16_t pdownr_3c	: 1;
397		uint16_t pdownr_3b	: 1;
398		uint16_t pdownr_3a	: 1;
399		uint16_t pdownr_2d	: 1;
400		uint16_t pdownr_2c	: 1;
401		uint16_t pdownr_2b	: 1;
402		uint16_t pdownr_2a	: 1;
403		uint16_t pdownr_1d	: 1;
404		uint16_t pdownr_1c	: 1;
405		uint16_t pdownr_1b	: 1;
406		uint16_t pdownr_1a	: 1;
407		uint16_t pdownr_0d	: 1;
408		uint16_t pdownr_0c	: 1;
409		uint16_t pdownr_0b	: 1;
410		uint16_t pdownr_0a	: 1;
411#else
412#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
413#endif
414	} bits;
415} sr_rx_power_ctrl_h_t;
416
417typedef	union _sr_tx_power_ctrl_l {
418	uint16_t value;
419	struct {
420#if defined(_BIT_FIELDS_HTOL)
421		uint16_t res1		: 8;
422		uint16_t pdownppll0	: 1;
423		uint16_t pdownppll1	: 1;
424		uint16_t pdownppll2	: 1;
425		uint16_t pdownppll3	: 1;
426		uint16_t res2		: 4;
427#elif defined(_BIT_FIELDS_LTOH)
428		uint16_t res2		: 4;
429		uint16_t pdownppll3	: 1;
430		uint16_t pdownppll2	: 1;
431		uint16_t pdownppll1	: 1;
432		uint16_t pdownppll0	: 1;
433		uint16_t res1		: 8;
434#else
435#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
436#endif
437	} bits;
438} sr_tx_power_ctrl_l_t;
439
440typedef	union _sr_tx_power_ctrl_h {
441	uint16_t value;
442	struct {
443#if defined(_BIT_FIELDS_HTOL)
444		uint16_t pdownt_0a	: 1;
445		uint16_t pdownt_0b	: 1;
446		uint16_t pdownt_0c	: 1;
447		uint16_t pdownt_0d	: 1;
448		uint16_t pdownt_1a	: 1;
449		uint16_t pdownt_1b	: 1;
450		uint16_t pdownt_1c	: 1;
451		uint16_t pdownt_1d	: 1;
452		uint16_t pdownt_2a	: 1;
453		uint16_t pdownt_2b	: 1;
454		uint16_t pdownt_2c	: 1;
455		uint16_t pdownt_2d	: 1;
456		uint16_t pdownt_3a	: 1;
457		uint16_t pdownt_3b	: 1;
458		uint16_t pdownt_3c	: 1;
459		uint16_t pdownt_3d	: 1;
460#elif defined(_BIT_FIELDS_LTOH)
461		uint16_t pdownt_3d	: 1;
462		uint16_t pdownt_3c	: 1;
463		uint16_t pdownt_3b	: 1;
464		uint16_t pdownt_3a	: 1;
465		uint16_t pdownt_2d	: 1;
466		uint16_t pdownt_2c	: 1;
467		uint16_t pdownt_2b	: 1;
468		uint16_t pdownt_2a	: 1;
469		uint16_t pdownt_1d	: 1;
470		uint16_t pdownt_1c	: 1;
471		uint16_t pdownt_1b	: 1;
472		uint16_t pdownt_1a	: 1;
473		uint16_t pdownt_0d	: 1;
474		uint16_t pdownt_0c	: 1;
475		uint16_t pdownt_0b	: 1;
476		uint16_t pdownt_0a	: 1;
477#else
478#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
479#endif
480	} bits;
481} sr_tx_power_ctrl_h_t;
482
483typedef	union _sr_misc_power_ctrl_l {
484	uint16_t value;
485	struct {
486#if defined(_BIT_FIELDS_HTOL)
487		uint16_t res1		: 3;
488		uint16_t pdrtrim	: 1;
489		uint16_t pdownpecl0	: 1;
490		uint16_t pdownpecl1	: 1;
491		uint16_t pdownpecl2	: 1;
492		uint16_t pdownpecl3	: 1;
493		uint16_t pdownppll0	: 1;
494		uint16_t pdownppll1	: 1;
495		uint16_t pdownppll2	: 1;
496		uint16_t pdownppll3	: 1;
497		uint16_t res2		: 4;
498#elif defined(_BIT_FIELDS_LTOH)
499		uint16_t res2		: 4;
500		uint16_t pdownppll3	: 1;
501		uint16_t pdownppll2	: 1;
502		uint16_t pdownppll1	: 1;
503		uint16_t pdownppll0	: 1;
504		uint16_t pdownpecl3	: 1;
505		uint16_t pdownpecl2	: 1;
506		uint16_t pdownpecl1	: 1;
507		uint16_t pdownpecl0	: 1;
508		uint16_t pdrtrim	: 1;
509		uint16_t res1		: 3;
510#else
511#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
512#endif
513	} bits;
514} sr_misc_power_ctrl_l_t;
515
516typedef	union _misc_power_ctrl_h {
517	uint16_t value;
518	struct {
519#if defined(_BIT_FIELDS_HTOL)
520		uint16_t pdclkout0	: 1;
521		uint16_t pdclkout1	: 1;
522		uint16_t pdclkout2	: 1;
523		uint16_t pdclkout3	: 1;
524		uint16_t res1		: 12;
525#elif defined(_BIT_FIELDS_LTOH)
526		uint16_t res1		: 12;
527		uint16_t pdclkout3	: 1;
528		uint16_t pdclkout2	: 1;
529		uint16_t pdclkout1	: 1;
530		uint16_t pdclkout0	: 1;
531#else
532#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
533#endif
534	} bits;
535} misc_power_ctrl_h_t;
536
537typedef	union _sr_rx_tx_ctrl_l {
538	uint16_t value;
539	struct {
540#if defined(_BIT_FIELDS_HTOL)
541		uint16_t res1		: 2;
542		uint16_t rxpreswin	: 2;
543		uint16_t res2		: 1;
544		uint16_t risefall	: 3;
545		uint16_t res3		: 7;
546		uint16_t enstretch	: 1;
547#elif defined(_BIT_FIELDS_LTOH)
548		uint16_t enstretch	: 1;
549		uint16_t res3		: 7;
550		uint16_t risefall	: 3;
551		uint16_t res2		: 1;
552		uint16_t rxpreswin	: 2;
553		uint16_t res1		: 2;
554#else
555#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
556#endif
557	} bits;
558} sr_rx_tx_ctrl_l_t;
559
560typedef	union _sr_rx_tx_ctrl_h {
561	uint16_t value;
562	struct {
563#if defined(_BIT_FIELDS_HTOL)
564		uint16_t biascntl	: 1;
565		uint16_t res1		: 5;
566		uint16_t tdenfifo	: 1;
567		uint16_t tdws20		: 1;
568		uint16_t vmuxlo		: 2;
569		uint16_t vpulselo	: 2;
570		uint16_t res2		: 4;
571#elif defined(_BIT_FIELDS_LTOH)
572		uint16_t res2		: 4;
573		uint16_t vpulselo	: 2;
574		uint16_t vmuxlo		: 2;
575		uint16_t tdws20		: 1;
576		uint16_t tdenfifo	: 1;
577		uint16_t res1		: 5;
578		uint16_t biascntl	: 1;
579#else
580#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
581#endif
582	} bits;
583} sr_rx_tx_ctrl_h_t;
584
585#define	RXPRESWIN_52US_300BITTIMES	0
586#define	RXPRESWIN_53US_300BITTIMES	1
587#define	RXPRESWIN_54US_300BITTIMES	2
588#define	RXPRESWIN_55US_300BITTIMES	3
589
590typedef	union _sr_rx_tx_tuning_l {
591	uint16_t value;
592	struct {
593#if defined(_BIT_FIELDS_HTOL)
594		uint16_t rxeq		: 4;
595		uint16_t res1		: 12;
596#elif defined(_BIT_FIELDS_LTOH)
597		uint16_t res1		: 12;
598		uint16_t rxeq		: 4;
599#else
600#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
601#endif
602	} bits;
603} sr_rx_tx_tuning_l_t;
604
605typedef	union _sr_rx_tx_tuning_h {
606	uint16_t value;
607	struct {
608#if defined(_BIT_FIELDS_HTOL)
609		uint16_t res1		: 8;
610		uint16_t rp		: 2;
611		uint16_t rz		: 2;
612		uint16_t vtxlo		: 4;
613#elif defined(_BIT_FIELDS_LTOH)
614		uint16_t vtxlo		: 4;
615		uint16_t rz		: 2;
616		uint16_t rp		: 2;
617		uint16_t res1		: 8;
618#else
619#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
620#endif
621	} bits;
622} sr_rx_tx_tuning_h_t;
623
624typedef	union _sr_rx_syncchar_l {
625	uint16_t value;
626	struct {
627#if defined(_BIT_FIELDS_HTOL)
628		uint16_t syncchar_0_3	: 4;
629		uint16_t res1		: 2;
630		uint16_t syncmask	: 10;
631#elif defined(_BIT_FIELDS_LTOH)
632		uint16_t syncmask	: 10;
633		uint16_t res1		: 2;
634		uint16_t syncchar_0_3	: 4;
635#else
636#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
637#endif
638	} bits;
639} sr_rx_syncchar_l_t;
640
641typedef	union _sr_rx_syncchar_h {
642	uint16_t value;
643	struct {
644#if defined(_BIT_FIELDS_HTOL)
645		uint16_t res1		: 1;
646		uint16_t syncpol	: 1;
647		uint16_t res2		: 8;
648		uint16_t syncchar_4_10	: 6;
649#elif defined(_BIT_FIELDS_LTOH)
650		uint16_t syncchar_4_10	: 6;
651		uint16_t res2		: 8;
652		uint16_t syncpol	: 1;
653		uint16_t res1		: 1;
654#else
655#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
656#endif
657	} bits;
658} sr_rx_syncchar_h_t;
659
660typedef	union _sr_rx_tx_test_l {
661	uint16_t value;
662	struct {
663#if defined(_BIT_FIELDS_HTOL)
664		uint16_t res1		: 15;
665		uint16_t ref50		: 1;
666#elif defined(_BIT_FIELDS_LTOH)
667		uint16_t ref50		: 1;
668		uint16_t res1		: 15;
669#else
670#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
671#endif
672	} bits;
673} sr_rx_tx_test_l_t;
674
675typedef	union _sr_rx_tx_test_h {
676	uint16_t value;
677	struct {
678#if defined(_BIT_FIELDS_HTOL)
679		uint16_t res1		: 5;
680		uint16_t selftest	: 3;
681		uint16_t res2		: 8;
682#elif defined(_BIT_FIELDS_LTOH)
683		uint16_t res2		: 8;
684		uint16_t selftest	: 3;
685		uint16_t res1		: 5;
686#else
687#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
688#endif
689	} bits;
690} sr_rx_tx_test_h_t;
691
692typedef	union _sr_glue_ctrl0_l {
693	uint16_t value;
694	struct {
695#if defined(_BIT_FIELDS_HTOL)
696		uint16_t rxlos_test	: 1;
697		uint16_t res1		: 1;
698		uint16_t rxlosenable	: 1;
699		uint16_t fastresync	: 1;
700		uint16_t samplerate	: 4;
701		uint16_t thresholdcount	: 8;
702#elif defined(_BIT_FIELDS_LTOH)
703		uint16_t thresholdcount	: 8;
704		uint16_t samplerate	: 4;
705		uint16_t fastresync	: 1;
706		uint16_t rxlosenable	: 1;
707		uint16_t res1		: 1;
708		uint16_t rxlos_test	: 1;
709#else
710#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
711#endif
712	} bits;
713} sr_glue_ctrl0_l_t;
714
715typedef	union _sr_glue_ctrl0_h {
716	uint16_t value;
717	struct {
718#if defined(_BIT_FIELDS_HTOL)
719		uint16_t res1		: 5;
720		uint16_t bitlocktime	: 3;
721		uint16_t res2		: 8;
722#elif defined(_BIT_FIELDS_LTOH)
723		uint16_t res2		: 8;
724		uint16_t bitlocktime	: 3;
725		uint16_t res1		: 5;
726#else
727#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
728#endif
729	} bits;
730} sr_glue_ctrl0_h_t;
731
732#define	BITLOCKTIME_64_CYCLES		0
733#define	BITLOCKTIME_128_CYCLES		1
734#define	BITLOCKTIME_256_CYCLES		2
735#define	BITLOCKTIME_300_CYCLES		3
736#define	BITLOCKTIME_384_CYCLES		4
737#define	BITLOCKTIME_512_CYCLES		5
738#define	BITLOCKTIME_1024_CYCLES		6
739#define	BITLOCKTIME_2048_CYCLES		7
740
741typedef	union _sr_glue_ctrl1_l {
742	uint16_t value;
743	struct {
744#if defined(_BIT_FIELDS_HTOL)
745		uint16_t res1		: 14;
746		uint16_t inittime	: 2;
747#elif defined(_BIT_FIELDS_LTOH)
748		uint16_t inittime	: 2;
749		uint16_t res1		: 14;
750#else
751#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
752#endif
753	} bits;
754} sr_glue_ctrl1_l_t;
755
756typedef	union glue_ctrl1_h {
757	uint16_t value;
758	struct {
759#if defined(_BIT_FIELDS_HTOL)
760		uint16_t termr_cfg	: 2;
761		uint16_t termt_cfg	: 2;
762		uint16_t rtrimen	: 2;
763		uint16_t res1		: 10;
764#elif defined(_BIT_FIELDS_LTOH)
765		uint16_t res1		: 10;
766		uint16_t rtrimen	: 2;
767		uint16_t termt_cfg	: 2;
768		uint16_t termr_cfg	: 2;
769#else
770#error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
771#endif
772	} bits;
773} glue_ctrl1_h_t;
774
775#define	TERM_CFG_67OHM		0
776#define	TERM_CFG_72OHM		1
777#define	TERM_CFG_80OHM		2
778#define	TERM_CFG_87OHM		3
779#define	TERM_CFG_46OHM		4
780#define	TERM_CFG_48OHM		5
781#define	TERM_CFG_52OHM		6
782#define	TERM_CFG_55OHM		7
783
784#define	INITTIME_60US		0
785#define	INITTIME_120US		1
786#define	INITTIME_240US		2
787#define	INITTIME_480US		3
788
789#ifdef	__cplusplus
790}
791#endif
792
793#endif	/* _SYS_NXGE_NXGE_SR_HW_H */
794