144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 2289282175SSantwona Behera * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. 2344961713Sgirish */ 2444961713Sgirish 2544961713Sgirish #ifndef _SYS_NXGE_NXGE_PHY_HW_H 2644961713Sgirish #define _SYS_NXGE_NXGE_PHY_HW_H 2744961713Sgirish 2844961713Sgirish #ifdef __cplusplus 2944961713Sgirish extern "C" { 3044961713Sgirish #endif 3144961713Sgirish 3244961713Sgirish #include <nxge_defs.h> 3344961713Sgirish 3400161856Syc /* 3523b952a3SSantwona Behera * Clause 45 and Clause 22 port/phy addresses 0 through 5 are reserved 3623b952a3SSantwona Behera * for on-chip serdes. So here the starting port is 6. 3700161856Syc */ 3859ac0c16Sdavemq #define NXGE_MAX_PHY_PORTS 32 3923b952a3SSantwona Behera #define NXGE_EXT_PHY_PORT_ST 6 4059ac0c16Sdavemq 4159ac0c16Sdavemq #define NXGE_PMA_PMD_DEV_ADDR 1 4259ac0c16Sdavemq #define NXGE_PCS_DEV_ADDR 3 4359ac0c16Sdavemq #define NXGE_DEV_ID_REG_1 2 4459ac0c16Sdavemq #define NXGE_DEV_ID_REG_2 3 4559ac0c16Sdavemq #define NXGE_PHY_ID_REG_1 2 4659ac0c16Sdavemq #define NXGE_PHY_ID_REG_2 3 4759ac0c16Sdavemq 482d17280bSsbehera #define BCM8704_CHIP_ID 0x8704 492d17280bSsbehera #define BCM8706_CHIP_ID 0x8706 5052cdd236Ssbehera #define MRVL88X201X_CHIP_ID 0x5043 5189282175SSantwona Behera #define NLP2020_CHIP_ID 0x0211 522d17280bSsbehera 5330505775Ssbehera /* 5400161856Syc * Description of BCM_PHY_ID_MASK: 5530505775Ssbehera * The first nibble (bits 0 through 3) is changed with every revision 5630505775Ssbehera * of the silicon. So these bits are masked out to support future revisions 5730505775Ssbehera * of the same chip. The third nibble (bits 8 through 11) is changed for 5830505775Ssbehera * different chips of the same family. So these bits are masked out to 5930505775Ssbehera * support chips of the same family. 6030505775Ssbehera */ 6130505775Ssbehera #define BCM_PHY_ID_MASK 0xfffff0f0 6259ac0c16Sdavemq #define BCM8704_DEV_ID 0x206033 6359ac0c16Sdavemq #define BCM5464R_PHY_ID 0x2060b1 642d17280bSsbehera #define BCM8706_DEV_ID 0x206035 6559a835ddSjoycey #define BCM5482_PHY_ID 0x143bcb1 6652cdd236Ssbehera #define MARVELL_88X_201X_DEV_ID 0x1410d24 6752cdd236Ssbehera #define MARVELL_88X201X_PHY_ID (MARVELL_88X_201X_DEV_ID & BCM_PHY_ID_MASK) 6830505775Ssbehera #define PHY_BCM8704_FAMILY (BCM8704_DEV_ID & BCM_PHY_ID_MASK) 6930505775Ssbehera #define PHY_BCM5464R_FAMILY (BCM5464R_PHY_ID & BCM_PHY_ID_MASK) 7059a835ddSjoycey #define PHY_BCM5482_FAMILY (BCM5482_PHY_ID & BCM_PHY_ID_MASK) 7100161856Syc /* 7200161856Syc * The default value is 0xa19410, after masking out model and revision 7300161856Syc * (bits[9:0]) use 0xa19400 for any model or revision of the TN1010 7400161856Syc */ 7500161856Syc #define TN1010_DEV_ID 0xa19400 7600161856Syc /* 7700161856Syc * Description of TN1010_DEV_ID_MASK: 7800161856Syc * The device ID assigned to Teranetics is stored in TN1010 register 7900161856Syc * 1.2 and register 1.3 except bits[9:4] of register 1.3 for model number 8000161856Syc * and bits[3:0] of register 1.3 for revision numbers. Use mask 0xfffffc00 8100161856Syc * to mask off model number and revision number and keep TN1010's device 8200161856Syc * identifier 8300161856Syc */ 8400161856Syc #define TN1010_DEV_ID_MASK 0xfffffc00 8589282175SSantwona Behera /* 8689282175SSantwona Behera * The Netlogic device ID and mask: 8789282175SSantwona Behera * The device ID assigned to Netlogic is stored in AEL2020 register 8889282175SSantwona Behera * 1.2 and register 1.3 except bits[7:4] of register 1.3 have the model number 8989282175SSantwona Behera * and bits[3:0] of register 1.3 have the revision number. Use mask 0xffffff00 9089282175SSantwona Behera * to mask off model number and revision number and keep AEL2020 device 9189282175SSantwona Behera * identifier 9289282175SSantwona Behera */ 9389282175SSantwona Behera #define NLP2020_DEV_ID 0x3429000 9489282175SSantwona Behera #define NLP2020_DEV_ID_MASK 0xffffff00 9559ac0c16Sdavemq 9659ac0c16Sdavemq #define CLAUSE_45_TYPE 1 9759ac0c16Sdavemq #define CLAUSE_22_TYPE 2 9859ac0c16Sdavemq 9900161856Syc /* IEEE802.3 Clause45 and Clause22 MDIO port addresses */ 10000161856Syc #define NEPTUNE_CLAUSE22_PORT_ADDR_BASE 10 10100161856Syc #define NEPTUNE_CLAUSE45_PORT_ADDR_BASE 8 10200161856Syc #define N2_CLAUSE45_PORT_ADDR_BASE 16 10352cdd236Ssbehera #define MRVL88X2011_NEPTUNE_PORT_ADDR_BASE 8 10459ac0c16Sdavemq 1052d17280bSsbehera /* 1062d17280bSsbehera * Phy address for the second NIU port on Goa NEM card can be either 1072d17280bSsbehera * 20 or 17 1082d17280bSsbehera */ 10900161856Syc #define GOA_CLAUSE45_PORT_ADDR_BASE 16 11000161856Syc #define ALT_GOA_CLAUSE45_PORT1_ADDR 20 11189282175SSantwona Behera 11289282175SSantwona Behera /* 11389282175SSantwona Behera * Phy addresses for AEL2020 used in QSFP for RF systems 11489282175SSantwona Behera */ 11589282175SSantwona Behera #define NLP2020_CL45_PORT0_ADDR0 0x10 11689282175SSantwona Behera #define NLP2020_CL45_PORT0_ADDR1 0x12 11789282175SSantwona Behera #define NLP2020_CL45_PORT0_ADDR2 0x15 11889282175SSantwona Behera #define NLP2020_CL45_PORT0_ADDR3 0x17 11989282175SSantwona Behera #define NLP2020_CL45_PORT1_ADDR0 0x11 12089282175SSantwona Behera #define NLP2020_CL45_PORT1_ADDR1 0x13 12189282175SSantwona Behera #define NLP2020_CL45_PORT1_ADDR2 0x14 12289282175SSantwona Behera #define NLP2020_CL45_PORT1_ADDR3 0x16 12389282175SSantwona Behera 12459ac0c16Sdavemq /* 12559ac0c16Sdavemq * Phy addresses for Maramba support. Support for P0 will eventually 12659ac0c16Sdavemq * be removed. 12759ac0c16Sdavemq */ 12800161856Syc #define MARAMBA_P0_CLAUSE22_PORT_ADDR_BASE 10 12900161856Syc #define MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE 26 13000161856Syc #define MARAMBA_CLAUSE45_PORT_ADDR_BASE 16 13159ac0c16Sdavemq 13244961713Sgirish #define BCM8704_PMA_PMD_DEV_ADDR 1 13344961713Sgirish #define BCM8704_PCS_DEV_ADDR 3 13444961713Sgirish #define BCM8704_USER_DEV3_ADDR 3 13544961713Sgirish #define BCM8704_PHYXS_ADDR 4 13644961713Sgirish #define BCM8704_USER_DEV4_ADDR 4 13744961713Sgirish 13844961713Sgirish /* Definitions for BCM 5464R PHY chip */ 13944961713Sgirish 14044961713Sgirish #define BCM5464R_PHY_ECR 16 14144961713Sgirish #define BCM5464R_PHY_ESR 17 14244961713Sgirish #define BCM5464R_RXERR_CNT 18 14344961713Sgirish #define BCM5464R_FALSECS_CNT 19 14444961713Sgirish #define BCM5464R_RX_NOTOK_CNT 20 14544961713Sgirish #define BCM5464R_ER_DATA 21 14644961713Sgirish #define BCM5464R_RES 22 14744961713Sgirish #define BCM5464R_ER_ACC 23 14844961713Sgirish #define BCM5464R_AUX_CTL 24 14944961713Sgirish #define BCM5464R_AUX_S 25 15044961713Sgirish #define BCM5464R_INTR_S 26 15144961713Sgirish #define BCM5464R_INTR_M 27 15244961713Sgirish #define BCM5464R_MISC 28 15344961713Sgirish #define BCM5464R_MISC1 29 15444961713Sgirish #define BCM5464R_TESTR1 30 15544961713Sgirish 15644961713Sgirish #define PHY_BCM_5464R_OUI 0x001018 15744961713Sgirish #define PHY_BCM_5464R_MODEL 0x0B 15844961713Sgirish 15952cdd236Ssbehera /* MARVELL PHY Definitions */ 16052cdd236Ssbehera /* REG Offsets */ 16152cdd236Ssbehera #define MRVL_88X2011_USER_DEV1_ADDR 1 16252cdd236Ssbehera #define MRVL_88X2011_USER_DEV2_ADDR 2 16352cdd236Ssbehera #define MRVL_88X2011_USER_DEV3_ADDR 3 16452cdd236Ssbehera #define MRVL_88X2011_USER_DEV4_ADDR 4 16552cdd236Ssbehera #define MRVL_88X2011_PMA_PMD_CTL_1 0x0000 16652cdd236Ssbehera #define MRVL_88X2011_PMA_PMD_STAT_1 0x0001 16752cdd236Ssbehera #define MRVL_88X2011_10G_PMD_STAT_2 0x0008 16852cdd236Ssbehera #define MRVL_88X2011_10G_PMD_TX_DIS 0x0009 16952cdd236Ssbehera #define MRVL_88X2011_10G_XGXS_LANE_STAT 0x0018 17052cdd236Ssbehera #define MRVL_88X2011_GEN_CTL 0x8300 17152cdd236Ssbehera #define MRVL_88X2011_LED_BLINK_CTL 0x8303 17252cdd236Ssbehera #define MRVL_88X2011_LED_8_TO_11_CTL 0x8306 17352cdd236Ssbehera 17452cdd236Ssbehera /* MRVL88X2011 register control */ 17552cdd236Ssbehera #define MRVL_88X2011_ENA_PMDTX 0x0000 17652cdd236Ssbehera #define MRVL_88X2011_ENA_XFPREFCLK 0x0001 17752cdd236Ssbehera #define MRVL_88X2011_LOOPBACK 0x1 17852cdd236Ssbehera #define MRVL_88X2011_LED_ACT 0x1 17952cdd236Ssbehera #define MRVL_88X2011_LNK_STATUS_OK 0x4 18052cdd236Ssbehera #define MRVL_88X2011_LED_BLK_MASK 0x70 18152cdd236Ssbehera #define MRVL_88X2011_LED_BLK_SHIFT 4 18252cdd236Ssbehera #define MRVL_88X2011_LED_BLK34MS 0x0 18352cdd236Ssbehera #define MRVL_88X2011_LED_BLK67MS 0x1 18452cdd236Ssbehera #define MRVL_88X2011_LED_BLK134MS 0x2 18552cdd236Ssbehera #define MRVL_88X2011_LED_BLK269MS 0x3 18652cdd236Ssbehera #define MRVL_88X2011_LED_BLK538MS 0x4 18752cdd236Ssbehera #define MRVL_88X2011_LED_CTL_OFF 0x0 18852cdd236Ssbehera #define MRVL_88X2011_LED_CTL_PCS_ERR 0x2 18952cdd236Ssbehera #define MRVL_88X2011_LED_CTL_PCS_ACT 0x5 19052cdd236Ssbehera #define MRVL_88X2011_LED_CTL_MASK 0x7 19152cdd236Ssbehera #define MRVL_88X2011_LED(n, v) ((v)<<((n)*4)) 19252cdd236Ssbehera #define MRVL_88X2011_LED_STAT(n, v) ((v)>>((n)*4)) 19352cdd236Ssbehera 19444961713Sgirish /* 19544961713Sgirish * MII Register 16: PHY Extended Control Register 19644961713Sgirish */ 19744961713Sgirish 19844961713Sgirish typedef union _mii_phy_ecr_t { 19944961713Sgirish uint16_t value; 20044961713Sgirish struct { 20144961713Sgirish #ifdef _BIT_FIELDS_HTOL 20244961713Sgirish uint16_t mac_phy_if_mode : 1; 20344961713Sgirish uint16_t dis_automdicross : 1; 20444961713Sgirish uint16_t tx_dis : 1; 20544961713Sgirish uint16_t intr_dis : 1; 20644961713Sgirish uint16_t force_intr : 1; 20744961713Sgirish uint16_t bypass_encdec : 1; 20844961713Sgirish uint16_t bypass_scrdes : 1; 20944961713Sgirish uint16_t bypass_mlt3 : 1; 21044961713Sgirish uint16_t bypass_rx_sym : 1; 21144961713Sgirish uint16_t reset_scr : 1; 21244961713Sgirish uint16_t en_led_traffic : 1; 21344961713Sgirish uint16_t force_leds_on : 1; 21444961713Sgirish uint16_t force_leds_off : 1; 21544961713Sgirish uint16_t res : 2; 21644961713Sgirish uint16_t gmii_fifo_elas : 1; 21744961713Sgirish #else 21844961713Sgirish uint16_t gmii_fifo_elas : 1; 21944961713Sgirish uint16_t res : 2; 22044961713Sgirish uint16_t force_leds_off : 1; 22144961713Sgirish uint16_t force_leds_on : 1; 22244961713Sgirish uint16_t en_led_traffic : 1; 22344961713Sgirish uint16_t reset_scr : 1; 22444961713Sgirish uint16_t bypass_rx_sym : 1; 22544961713Sgirish uint16_t bypass_mlt3 : 1; 22644961713Sgirish uint16_t bypass_scrdes : 1; 22744961713Sgirish uint16_t bypass_encdec : 1; 22844961713Sgirish uint16_t force_intr : 1; 22944961713Sgirish uint16_t intr_dis : 1; 23044961713Sgirish uint16_t tx_dis : 1; 23144961713Sgirish uint16_t dis_automdicross : 1; 23244961713Sgirish uint16_t mac_phy_if_mode : 1; 23344961713Sgirish #endif 23444961713Sgirish } bits; 23544961713Sgirish } mii_phy_ecr_t, *p_mii_phy_ecr_t; 23644961713Sgirish 23744961713Sgirish /* 23844961713Sgirish * MII Register 17: PHY Extended Status Register 23944961713Sgirish */ 24044961713Sgirish typedef union _mii_phy_esr_t { 24144961713Sgirish uint16_t value; 24244961713Sgirish struct { 24344961713Sgirish #ifdef _BIT_FIELDS_HTOL 24444961713Sgirish uint16_t anbpsfm : 1; 24544961713Sgirish uint16_t wsdwngr : 1; 24644961713Sgirish uint16_t mdi_crst : 1; 24744961713Sgirish uint16_t intr_s : 1; 24844961713Sgirish uint16_t rmt_rx_s : 1; 24944961713Sgirish uint16_t loc_rx_s : 1; 25044961713Sgirish uint16_t locked : 1; 25144961713Sgirish uint16_t link_s : 1; 25244961713Sgirish uint16_t crc_err : 1; 25344961713Sgirish uint16_t cext_err : 1; 25444961713Sgirish uint16_t bad_ssd : 1; 25544961713Sgirish uint16_t bad_esd : 1; 25644961713Sgirish uint16_t rx_err : 1; 25744961713Sgirish uint16_t tx_err : 1; 25844961713Sgirish uint16_t lock_err : 1; 25944961713Sgirish uint16_t mlt3_cerr : 1; 26044961713Sgirish #else 26144961713Sgirish uint16_t mlt3_cerr : 1; 26244961713Sgirish uint16_t lock_err : 1; 26344961713Sgirish uint16_t tx_err : 1; 26444961713Sgirish uint16_t rx_err : 1; 26544961713Sgirish uint16_t bad_esd : 1; 26644961713Sgirish uint16_t bad_ssd : 1; 26744961713Sgirish uint16_t cext_err : 1; 26844961713Sgirish uint16_t crc_err : 1; 26944961713Sgirish uint16_t link_s : 1; 27044961713Sgirish uint16_t locked : 1; 27144961713Sgirish uint16_t loc_rx_s : 1; 27244961713Sgirish uint16_t rmt_rx_s : 1; 27344961713Sgirish uint16_t intr_s : 1; 27444961713Sgirish uint16_t mdi_crst : 1; 27544961713Sgirish uint16_t wsdwngr : 1; 27644961713Sgirish uint16_t anbpsfm : 1; 27744961713Sgirish #endif 27844961713Sgirish } bits; 27944961713Sgirish } mii_phy_esr_t, *p_mii_phy_esr_t; 28044961713Sgirish 28144961713Sgirish /* 28244961713Sgirish * MII Register 18: Receive Error Counter Register 28344961713Sgirish */ 28444961713Sgirish typedef union _mii_rxerr_cnt_t { 28544961713Sgirish uint16_t value; 28644961713Sgirish struct { 28744961713Sgirish uint16_t rx_err_cnt : 16; 28844961713Sgirish } bits; 28944961713Sgirish } mii_rxerr_cnt_t, *p_mii_rxerr_cnt_t; 29044961713Sgirish 29144961713Sgirish /* 29244961713Sgirish * MII Register 19: False Carrier Sense Counter Register 29344961713Sgirish */ 29444961713Sgirish typedef union _mii_falsecs_cnt_t { 29544961713Sgirish uint16_t value; 29644961713Sgirish struct { 29744961713Sgirish #ifdef _BIT_FIELDS_HTOL 29844961713Sgirish uint16_t res : 8; 29944961713Sgirish uint16_t false_cs_cnt : 8; 30044961713Sgirish #else 30144961713Sgirish uint16_t false_cs_cnt : 8; 30244961713Sgirish uint16_t res : 8; 30344961713Sgirish #endif 30444961713Sgirish } bits; 30544961713Sgirish } mii_falsecs_cnt_t, *p_mii_falsecs_cnt_t; 30644961713Sgirish 30744961713Sgirish /* 30844961713Sgirish * MII Register 20: Receiver NOT_OK Counter Register 30944961713Sgirish */ 31044961713Sgirish typedef union _mii_rx_notok_cnt_t { 31144961713Sgirish uint16_t value; 31244961713Sgirish struct { 31344961713Sgirish #ifdef _BIT_FIELDS_HTOL 31444961713Sgirish uint16_t l_rx_notok_cnt : 8; 31544961713Sgirish uint16_t r_rx_notok_cnt : 8; 31644961713Sgirish #else 31744961713Sgirish uint16_t r_rx_notok_cnt : 8; 31844961713Sgirish uint16_t l_rx_notok_cnt : 8; 31944961713Sgirish #endif 32044961713Sgirish } bits; 32144961713Sgirish } mii_rx_notok_cnt_t, *p_mii_rx_notok_t; 32244961713Sgirish 32344961713Sgirish /* 32444961713Sgirish * MII Register 21: Expansion Register Data Register 32544961713Sgirish */ 32644961713Sgirish typedef union _mii_er_data_t { 32744961713Sgirish uint16_t value; 32844961713Sgirish struct { 32944961713Sgirish uint16_t reg_data; 33044961713Sgirish } bits; 33144961713Sgirish } mii_er_data_t, *p_mii_er_data_t; 33244961713Sgirish 33344961713Sgirish /* 33444961713Sgirish * MII Register 23: Expansion Register Access Register 33544961713Sgirish */ 33644961713Sgirish typedef union _mii_er_acc_t { 33744961713Sgirish struct { 33844961713Sgirish #ifdef _BIT_FIELDS_HTOL 33944961713Sgirish uint16_t res : 4; 34044961713Sgirish uint16_t er_sel : 4; 34144961713Sgirish uint16_t er_acc : 8; 34244961713Sgirish #else 34344961713Sgirish uint16_t er_acc : 8; 34444961713Sgirish uint16_t er_sel : 4; 34544961713Sgirish uint16_t res : 4; 34644961713Sgirish #endif 34744961713Sgirish } bits; 34844961713Sgirish } mii_er_acc_t, *p_mii_er_acc_t; 34944961713Sgirish 35044961713Sgirish #define EXP_RXTX_PKT_CNT 0x0 35144961713Sgirish #define EXP_INTR_STAT 0x1 35244961713Sgirish #define MULTICOL_LED_SEL 0x4 35344961713Sgirish #define MULTICOL_LED_FLASH_RATE_CTL 0x5 35444961713Sgirish #define MULTICOL_LED_BLINK_CTL 0x6 35544961713Sgirish #define CABLE_DIAG_CTL 0x10 35644961713Sgirish #define CABLE_DIAG_RES 0x11 35744961713Sgirish #define CABLE_DIAG_LEN_CH_2_1 0x12 35844961713Sgirish #define CABLE_DIAG_LEN_CH_4_3 0x13 35944961713Sgirish 36044961713Sgirish /* 36144961713Sgirish * MII Register 24: Auxiliary Control Register 36244961713Sgirish */ 36344961713Sgirish typedef union _mii_aux_ctl_t { 36444961713Sgirish uint16_t value; 36544961713Sgirish struct { 36644961713Sgirish #ifdef _BIT_FIELDS_HTOL 36744961713Sgirish uint16_t ext_lb : 1; 36844961713Sgirish uint16_t ext_pkt_len : 1; 36944961713Sgirish uint16_t edge_rate_ctl_1000 : 2; 37044961713Sgirish uint16_t res : 1; 37144961713Sgirish uint16_t write_1 : 1; 37244961713Sgirish uint16_t res1 : 2; 37344961713Sgirish uint16_t dis_partial_resp : 1; 37444961713Sgirish uint16_t res2 : 1; 37544961713Sgirish uint16_t edge_rate_ctl_100 : 2; 37644961713Sgirish uint16_t diag_mode : 1; 37744961713Sgirish uint16_t shadow_reg_sel : 3; 37844961713Sgirish #else 37944961713Sgirish uint16_t shadow_reg_sel : 3; 38044961713Sgirish uint16_t diag_mode : 1; 38144961713Sgirish uint16_t edge_rate_ctl_100 : 2; 38244961713Sgirish uint16_t res2 : 1; 38344961713Sgirish uint16_t dis_partial_resp : 1; 38444961713Sgirish uint16_t res1 : 2; 38544961713Sgirish uint16_t write_1 : 1; 38644961713Sgirish uint16_t res : 1; 38744961713Sgirish uint16_t edge_rate_ctl_1000 : 2; 38844961713Sgirish uint16_t ext_pkt_len : 1; 38944961713Sgirish uint16_t ext_lb : 1; 39044961713Sgirish #endif 39144961713Sgirish } bits; 39244961713Sgirish } mii_aux_ctl_t, *p_mii_aux_ctl_t; 39344961713Sgirish 39444961713Sgirish #define AUX_REG 0x0 39544961713Sgirish #define AUX_10BASET 0x1 39644961713Sgirish #define AUX_PWR_CTL 0x2 39744961713Sgirish #define AUX_MISC_TEST 0x4 39844961713Sgirish #define AUX_MISC_CTL 0x7 39944961713Sgirish 40044961713Sgirish /* 40144961713Sgirish * MII Register 25: Auxiliary Status Summary Register 40244961713Sgirish */ 40344961713Sgirish typedef union _mii_aux_s_t { 40444961713Sgirish uint16_t value; 40544961713Sgirish struct { 40644961713Sgirish #ifdef _BIT_FIELDS_HTOL 40744961713Sgirish uint16_t an_complete : 1; 40844961713Sgirish uint16_t an_complete_ack : 1; 40944961713Sgirish uint16_t an_ack_detect : 1; 41044961713Sgirish uint16_t an_ability_detect : 1; 41144961713Sgirish uint16_t an_np_wait : 1; 41244961713Sgirish uint16_t an_hcd : 3; 41344961713Sgirish uint16_t pd_fault : 1; 41444961713Sgirish uint16_t rmt_fault : 1; 41544961713Sgirish uint16_t an_page_rx : 1; 41644961713Sgirish uint16_t lp_an_ability : 1; 41744961713Sgirish uint16_t lp_np_ability : 1; 41844961713Sgirish uint16_t link_s : 1; 41944961713Sgirish uint16_t pause_res_rx_dir : 1; 42044961713Sgirish uint16_t pause_res_tx_dir : 1; 42144961713Sgirish #else 42244961713Sgirish uint16_t pause_res_tx_dir : 1; 42344961713Sgirish uint16_t pause_res_rx_dir : 1; 42444961713Sgirish uint16_t link_s : 1; 42544961713Sgirish uint16_t lp_np_ability : 1; 42644961713Sgirish uint16_t lp_an_ability : 1; 42744961713Sgirish uint16_t an_page_rx : 1; 42844961713Sgirish uint16_t rmt_fault : 1; 42944961713Sgirish uint16_t pd_fault : 1; 43044961713Sgirish uint16_t an_hcd : 3; 43144961713Sgirish uint16_t an_np_wait : 1; 43244961713Sgirish uint16_t an_ability_detect : 1; 43344961713Sgirish uint16_t an_ack_detect : 1; 43444961713Sgirish uint16_t an_complete_ack : 1; 43544961713Sgirish uint16_t an_complete : 1; 43644961713Sgirish #endif 43744961713Sgirish } bits; 43844961713Sgirish } mii_aux_s_t, *p_mii_aux_s_t; 43944961713Sgirish 44044961713Sgirish /* 44144961713Sgirish * MII Register 26, 27: Interrupt Status and Mask Registers 44244961713Sgirish */ 44344961713Sgirish typedef union _mii_intr_t { 44444961713Sgirish uint16_t value; 44544961713Sgirish struct { 44644961713Sgirish #ifdef _BIT_FIELDS_HTOL 44744961713Sgirish uint16_t res : 1; 44844961713Sgirish uint16_t illegal_pair_swap : 1; 44944961713Sgirish uint16_t mdix_status_change : 1; 45044961713Sgirish uint16_t exceed_hicnt_thres : 1; 45144961713Sgirish uint16_t exceed_locnt_thres : 1; 45244961713Sgirish uint16_t an_page_rx : 1; 45344961713Sgirish uint16_t hcd_nolink : 1; 45444961713Sgirish uint16_t no_hcd : 1; 45544961713Sgirish uint16_t neg_unsupported_hcd : 1; 45644961713Sgirish uint16_t scr_sync_err : 1; 45744961713Sgirish uint16_t rmt_rx_status_change : 1; 45844961713Sgirish uint16_t loc_rx_status_change : 1; 45944961713Sgirish uint16_t duplex_mode_change : 1; 46044961713Sgirish uint16_t link_speed_change : 1; 46144961713Sgirish uint16_t link_status_change : 1; 46244961713Sgirish uint16_t crc_err : 1; 46344961713Sgirish #else 46444961713Sgirish uint16_t crc_err : 1; 46544961713Sgirish uint16_t link_status_change : 1; 46644961713Sgirish uint16_t link_speed_change : 1; 46744961713Sgirish uint16_t duplex_mode_change : 1; 46844961713Sgirish uint16_t loc_rx_status_change : 1; 46944961713Sgirish uint16_t rmt_rx_status_change : 1; 47044961713Sgirish uint16_t scr_sync_err : 1; 47144961713Sgirish uint16_t neg_unsupported_hcd : 1; 47244961713Sgirish uint16_t no_hcd : 1; 47344961713Sgirish uint16_t hcd_nolink : 1; 47444961713Sgirish uint16_t an_page_rx : 1; 47544961713Sgirish uint16_t exceed_locnt_thres : 1; 47644961713Sgirish uint16_t exceed_hicnt_thres : 1; 47744961713Sgirish uint16_t mdix_status_change : 1; 47844961713Sgirish uint16_t illegal_pair_swap : 1; 47944961713Sgirish uint16_t res : 1; 48044961713Sgirish #endif 48144961713Sgirish } bits; 48244961713Sgirish } mii_intr_t, *p_mii_intr_t; 48344961713Sgirish 48444961713Sgirish /* 48544961713Sgirish * MII Register 28: Register 1C Access Register 48644961713Sgirish */ 48744961713Sgirish typedef union _mii_misc_t { 48844961713Sgirish uint16_t value; 48944961713Sgirish struct { 49044961713Sgirish #ifdef _BIT_FIELDS_HTOL 49144961713Sgirish uint16_t w_en : 1; 49244961713Sgirish uint16_t shadow_reg_sel : 5; 49344961713Sgirish uint16_t data : 10; 49444961713Sgirish #else 49544961713Sgirish uint16_t data : 10; 49644961713Sgirish uint16_t shadow_reg_sel : 5; 49744961713Sgirish uint16_t w_en : 1; 49844961713Sgirish #endif 49944961713Sgirish } bits; 50044961713Sgirish } mii_misc_t, *p_mii_misc_t; 50144961713Sgirish 50244961713Sgirish #define LINK_LED_MODE 0x2 50344961713Sgirish #define CLK_ALIGN_CTL 0x3 50444961713Sgirish #define WIRE_SP_RETRY 0x4 50544961713Sgirish #define CLK125 0x5 50644961713Sgirish #define LED_STATUS 0x8 50744961713Sgirish #define LED_CONTROL 0x9 50844961713Sgirish #define AUTO_PWR_DOWN 0xA 50944961713Sgirish #define LED_SEL1 0xD 51044961713Sgirish #define LED_SEL2 0xE 51144961713Sgirish 51244961713Sgirish /* 51344961713Sgirish * MII Register 29: Master/Slave Seed / HCD Status Register 51444961713Sgirish */ 51544961713Sgirish 51644961713Sgirish typedef union _mii_misc1_t { 51744961713Sgirish uint16_t value; 51844961713Sgirish struct { 51944961713Sgirish #ifdef _BIT_FIELDS_HTOL 52044961713Sgirish uint16_t en_shadow_reg : 1; 52144961713Sgirish uint16_t data : 15; 52244961713Sgirish #else 52344961713Sgirish uint16_t data : 15; 52444961713Sgirish uint16_t en_shadow_reg : 1; 52544961713Sgirish #endif 52644961713Sgirish } bits; 52744961713Sgirish } mii_misc1_t, *p_mii_misc1_t; 52844961713Sgirish 52944961713Sgirish /* 53044961713Sgirish * MII Register 30: Test Register 1 53144961713Sgirish */ 53244961713Sgirish 53344961713Sgirish typedef union _mii_test1_t { 53444961713Sgirish uint16_t value; 53544961713Sgirish struct { 53644961713Sgirish #ifdef _BIT_FIELDS_HTOL 53744961713Sgirish uint16_t crc_err_cnt_sel : 1; 53844961713Sgirish uint16_t res : 7; 53944961713Sgirish uint16_t manual_swap_mdi_st : 1; 54044961713Sgirish uint16_t res1 : 7; 54144961713Sgirish #else 54244961713Sgirish uint16_t res1 : 7; 54344961713Sgirish uint16_t manual_swap_mdi_st : 1; 54444961713Sgirish uint16_t res : 7; 54544961713Sgirish uint16_t crc_err_cnt_sel : 1; 54644961713Sgirish #endif 54744961713Sgirish } bits; 54844961713Sgirish } mii_test1_t, *p_mii_test1_t; 54944961713Sgirish 55044961713Sgirish 55144961713Sgirish /* Definitions of BCM8704 */ 55244961713Sgirish 55344961713Sgirish #define BCM8704_PMD_CONTROL_REG 0 55444961713Sgirish #define BCM8704_PMD_STATUS_REG 0x1 55544961713Sgirish #define BCM8704_PMD_ID_0_REG 0x2 55644961713Sgirish #define BCM8704_PMD_ID_1_REG 0x3 55744961713Sgirish #define BCM8704_PMD_SPEED_ABIL_REG 0x4 55844961713Sgirish #define BCM8704_PMD_DEV_IN_PKG1_REG 0x5 55944961713Sgirish #define BCM8704_PMD_DEV_IN_PKG2_REG 0x6 56044961713Sgirish #define BCM8704_PMD_CONTROL2_REG 0x7 56144961713Sgirish #define BCM8704_PMD_STATUS2_REG 0x8 56244961713Sgirish #define BCM8704_PMD_TRANSMIT_DIS_REG 0x9 56344961713Sgirish #define BCM8704_PMD_RECEIVE_SIG_DETECT 0xa 56444961713Sgirish #define BCM8704_PMD_ORG_UNIQUE_ID_0_REG 0xe 56544961713Sgirish #define BCM8704_PMD_ORG_UNIQUE_ID_1_REG 0xf 56644961713Sgirish #define BCM8704_PCS_CONTROL_REG 0 56744961713Sgirish #define BCM8704_PCS_STATUS1_REG 0x1 56844961713Sgirish #define BCM8704_PCS_ID_0_REG 0x2 56944961713Sgirish #define BCM8704_PCS_ID_1_REG 0x3 57044961713Sgirish #define BCM8704_PCS_SPEED_ABILITY_REG 0x4 57144961713Sgirish #define BCM8704_PCS_DEV_IN_PKG1_REG 0x5 57244961713Sgirish #define BCM8704_PCS_DEV_IN_PKG2_REG 0x6 57344961713Sgirish #define BCM8704_PCS_CONTROL2_REG 0x7 57444961713Sgirish #define BCM8704_PCS_STATUS2_REG 0x8 57544961713Sgirish #define BCM8704_PCS_ORG_UNIQUE_ID_0_REG 0xe 57644961713Sgirish #define BCM8704_PCS_ORG_UNIQUE_ID_1_REG 0xf 57744961713Sgirish #define BCM8704_PCS_STATUS_REG 0x18 57844961713Sgirish #define BCM8704_10GBASE_R_PCS_STATUS_REG 0x20 57944961713Sgirish #define BCM8704_10GBASE_R_PCS_STATUS2_REG 0x21 58044961713Sgirish #define BCM8704_PHYXS_CONTROL_REG 0 58144961713Sgirish #define BCM8704_PHYXS_STATUS_REG 0x1 58244961713Sgirish #define BCM8704_PHY_ID_0_REG 0x2 58344961713Sgirish #define BCM8704_PHY_ID_1_REG 0x3 58444961713Sgirish #define BCM8704_PHYXS_SPEED_ABILITY_REG 0x4 58544961713Sgirish #define BCM8704_PHYXS_DEV_IN_PKG2_REG 0x5 58644961713Sgirish #define BCM8704_PHYXS_DEV_IN_PKG1_REG 0x6 58744961713Sgirish #define BCM8704_PHYXS_STATUS2_REG 0x8 58844961713Sgirish #define BCM8704_PHYXS_ORG_UNIQUE_ID_0_REG 0xe 58944961713Sgirish #define BCM8704_PHYXS_ORG_UNIQUE_ID_1_REG 0xf 59044961713Sgirish #define BCM8704_PHYXS_XGXS_LANE_STATUS_REG 0x18 59144961713Sgirish #define BCM8704_PHYXS_XGXS_TEST_CONTROL_REG 0x19 59244961713Sgirish #define BCM8704_USER_CONTROL_REG 0xC800 59344961713Sgirish #define BCM8704_USER_ANALOG_CLK_REG 0xC801 59444961713Sgirish #define BCM8704_USER_PMD_RX_CONTROL_REG 0xC802 59544961713Sgirish #define BCM8704_USER_PMD_TX_CONTROL_REG 0xC803 59644961713Sgirish #define BCM8704_USER_ANALOG_STATUS0_REG 0xC804 5972d17280bSsbehera #define BCM8704_CHIP_ID_REG 0xC807 59844961713Sgirish #define BCM8704_USER_OPTICS_DIGITAL_CTRL_REG 0xC808 59944961713Sgirish #define BCM8704_USER_RX2_CONTROL1_REG 0x80C6 60044961713Sgirish #define BCM8704_USER_RX1_CONTROL1_REG 0x80D6 60144961713Sgirish #define BCM8704_USER_RX0_CONTROL1_REG 0x80E6 60244961713Sgirish #define BCM8704_USER_TX_ALARM_STATUS_REG 0x9004 60344961713Sgirish 60444961713Sgirish /* Rx Channel Control1 Register bits */ 60544961713Sgirish #define BCM8704_RXPOL_FLIP 0x20 60644961713Sgirish 60744961713Sgirish typedef union _phyxs_control { 60844961713Sgirish uint16_t value; 60944961713Sgirish struct { 61044961713Sgirish #ifdef _BIT_FIELDS_HTOL 61144961713Sgirish uint16_t reset : 1; 61244961713Sgirish uint16_t loopback : 1; 61344961713Sgirish uint16_t speed_sel2 : 1; 61444961713Sgirish uint16_t res2 : 1; 61544961713Sgirish uint16_t low_power : 1; 61644961713Sgirish uint16_t res1 : 4; 61744961713Sgirish uint16_t speed_sel1 : 1; 61844961713Sgirish uint16_t speed_sel0 : 4; 61944961713Sgirish uint16_t res0 : 2; 62044961713Sgirish #else 62144961713Sgirish uint16_t res0 : 2; 62244961713Sgirish uint16_t speed_sel0 : 4; 62344961713Sgirish uint16_t speed_sel1 : 1; 62444961713Sgirish uint16_t res1 : 4; 62544961713Sgirish uint16_t low_power : 1; 62644961713Sgirish uint16_t res2 : 1; 62744961713Sgirish uint16_t speed_sel2 : 1; 62844961713Sgirish uint16_t loopback : 1; 62944961713Sgirish uint16_t reset : 1; 63044961713Sgirish #endif 63144961713Sgirish } bits; 63244961713Sgirish } phyxs_control_t, *p_phyxs_control_t, pcs_control_t, *p_pcs_control_t; 63344961713Sgirish 63444961713Sgirish 63544961713Sgirish /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc800) */ 63644961713Sgirish 63744961713Sgirish typedef union _control { 63844961713Sgirish uint16_t value; 63944961713Sgirish struct { 64044961713Sgirish #ifdef _BIT_FIELDS_HTOL 64144961713Sgirish uint16_t optxenb_lvl : 1; 64244961713Sgirish uint16_t optxrst_lvl : 1; 64344961713Sgirish uint16_t opbiasflt_lvl : 1; 64444961713Sgirish uint16_t obtmpflt_lvl : 1; 64544961713Sgirish uint16_t opprflt_lvl : 1; 64644961713Sgirish uint16_t optxflt_lvl : 1; 64744961713Sgirish uint16_t optrxlos_lvl : 1; 64844961713Sgirish uint16_t oprxflt_lvl : 1; 64944961713Sgirish uint16_t optxon_lvl : 1; 65044961713Sgirish uint16_t res1 : 7; 65144961713Sgirish #else 65244961713Sgirish uint16_t res1 : 7; 65344961713Sgirish uint16_t optxon_lvl : 1; 65444961713Sgirish uint16_t oprxflt_lvl : 1; 65544961713Sgirish uint16_t optrxlos_lvl : 1; 65644961713Sgirish uint16_t optxflt_lvl : 1; 65744961713Sgirish uint16_t opprflt_lvl : 1; 65844961713Sgirish uint16_t obtmpflt_lvl : 1; 65944961713Sgirish uint16_t opbiasflt_lvl : 1; 66044961713Sgirish uint16_t optxrst_lvl : 1; 66144961713Sgirish uint16_t optxenb_lvl : 1; 66244961713Sgirish #endif 66344961713Sgirish } bits; 66444961713Sgirish } control_t, *p_control_t; 66544961713Sgirish 66644961713Sgirish typedef union _pmd_tx_control { 66744961713Sgirish uint16_t value; 66844961713Sgirish struct { 66944961713Sgirish #ifdef _BIT_FIELDS_HTOL 67044961713Sgirish uint16_t res1 : 7; 67144961713Sgirish uint16_t xfp_clken : 1; 67244961713Sgirish uint16_t tx_dac_txd : 2; 67344961713Sgirish uint16_t tx_dac_txck : 2; 67444961713Sgirish uint16_t tsd_lpwren : 1; 67544961713Sgirish uint16_t tsck_lpwren : 1; 67644961713Sgirish uint16_t cmu_lpwren : 1; 67744961713Sgirish uint16_t sfiforst : 1; 67844961713Sgirish #else 67944961713Sgirish uint16_t sfiforst : 1; 68044961713Sgirish uint16_t cmu_lpwren : 1; 68144961713Sgirish uint16_t tsck_lpwren : 1; 68244961713Sgirish uint16_t tsd_lpwren : 1; 68344961713Sgirish uint16_t tx_dac_txck : 2; 68444961713Sgirish uint16_t tx_dac_txd : 2; 68544961713Sgirish uint16_t xfp_clken : 1; 68644961713Sgirish uint16_t res1 : 7; 68744961713Sgirish #endif 68844961713Sgirish } bits; 68944961713Sgirish } pmd_tx_control_t, *p_pmd_tx_control_t; 69044961713Sgirish 69144961713Sgirish 69244961713Sgirish /* PMD/Optics Digital Control Register (Dev=3 Addr=0xc808) */ 69344961713Sgirish 69444961713Sgirish typedef union _optics_dcntr { 69544961713Sgirish uint16_t value; 69644961713Sgirish struct { 69744961713Sgirish #ifdef _BIT_FIELDS_HTOL 69844961713Sgirish uint16_t fault_mode : 1; 69944961713Sgirish uint16_t tx_pwrdown : 1; 70044961713Sgirish uint16_t rx_pwrdown : 1; 70144961713Sgirish uint16_t ext_flt_en : 1; 70244961713Sgirish uint16_t opt_rst : 1; 70344961713Sgirish uint16_t pcs_tx_inv_b : 1; 70444961713Sgirish uint16_t pcs_rx_inv : 1; 70544961713Sgirish uint16_t res3 : 2; 70644961713Sgirish uint16_t gpio_sel : 2; 70744961713Sgirish uint16_t res2 : 1; 70844961713Sgirish uint16_t lpbk_err_dis : 1; 70944961713Sgirish uint16_t res1 : 2; 71044961713Sgirish uint16_t txonoff_pwdwn_dis : 1; 71144961713Sgirish #else 71244961713Sgirish uint16_t txonoff_pwdwn_dis : 1; 71344961713Sgirish uint16_t res1 : 2; 71444961713Sgirish uint16_t lpbk_err_dis : 1; 71544961713Sgirish uint16_t res2 : 1; 71644961713Sgirish uint16_t gpio_sel : 2; 71744961713Sgirish uint16_t res3 : 2; 71844961713Sgirish uint16_t pcs_rx_inv : 1; 71944961713Sgirish uint16_t pcs_tx_inv_b : 1; 72044961713Sgirish uint16_t opt_rst : 1; 72144961713Sgirish uint16_t ext_flt_en : 1; 72244961713Sgirish uint16_t rx_pwrdown : 1; 72344961713Sgirish uint16_t tx_pwrdown : 1; 72444961713Sgirish uint16_t fault_mode : 1; 72544961713Sgirish #endif 72644961713Sgirish } bits; 72744961713Sgirish } optics_dcntr_t, *p_optics_dcntr_t; 72844961713Sgirish 72944961713Sgirish /* PMD Receive Signal Detect Register (Dev = 1 Register Address = 0x000A) */ 73044961713Sgirish 73144961713Sgirish #define PMD_RX_SIG_DET3 0x10 73244961713Sgirish #define PMD_RX_SIG_DET2 0x08 73344961713Sgirish #define PMD_RX_SIG_DET1 0x04 73444961713Sgirish #define PMD_RX_SIG_DET0 0x02 73544961713Sgirish #define GLOB_PMD_RX_SIG_OK 0x01 73644961713Sgirish 73744961713Sgirish /* 10GBase-R PCS Status Register (Dev = 3, Register Address = 0x0020) */ 73844961713Sgirish 73944961713Sgirish #define PCS_10GBASE_RX_LINK_STATUS 0x1000 74044961713Sgirish #define PCS_PRBS31_ABLE 0x0004 74144961713Sgirish #define PCS_10GBASE_R_HI_BER 0x0002 74244961713Sgirish #define PCS_10GBASE_R_PCS_BLK_LOCK 0x0001 74344961713Sgirish 74444961713Sgirish /* XGXS Lane Status Register (Dev = 4, Register Address = 0x0018) */ 74544961713Sgirish 74644961713Sgirish #define XGXS_LANE_ALIGN_STATUS 0x1000 74744961713Sgirish #define XGXS_PATTERN_TEST_ABILITY 0x0800 74844961713Sgirish #define XGXS_LANE3_SYNC 0x0008 74944961713Sgirish #define XGXS_LANE2_SYNC 0x0004 75044961713Sgirish #define XGXS_LANE1_SYNC 0x0002 75144961713Sgirish #define XGXS_LANE0_SYNC 0x0001 75252cdd236Ssbehera #define XGXS_LANE_STAT_MAGIC 0x0400 75344961713Sgirish 75400161856Syc 75500161856Syc /* Teranetics TN1010 Definitions */ 75600161856Syc 75700161856Syc /* Teranetics TN1010 PHY MMD Addresses */ 75800161856Syc #define TN1010_PMA_PMD_DEV_ADDR 1 75900161856Syc #define TN1010_PCS_DEV_ADDR 3 76000161856Syc #define TN1010_PHYXS_DEV_ADDR 4 76100161856Syc #define TN1010_AUTONEG_DEV_ADDR 7 76200161856Syc #define TN1010_VENDOR_MMD1_DEV_ADDR 30 76300161856Syc 76400161856Syc /* TN1010 PCS Control Register */ 76500161856Syc typedef union _tn1010_pcs_ctrl { 76600161856Syc uint16_t value; 76700161856Syc struct { 76800161856Syc #ifdef _BIT_FIELDS_HTOL 76900161856Syc uint16_t reset : 1; /* bit 15 */ 77000161856Syc uint16_t loopback : 1; /* bit 14 */ 77100161856Syc uint16_t speed_sel2 : 1; 77200161856Syc uint16_t res2 : 1; 77300161856Syc uint16_t low_power : 1; 77400161856Syc uint16_t res1 : 4; 77500161856Syc uint16_t speed_sel1 : 1; /* bit 6 */ 77600161856Syc uint16_t speed_sel0 : 4; /* bits[5:2] */ 77700161856Syc uint16_t res0 : 2; 77800161856Syc #else 77900161856Syc uint16_t res0 : 2; 78000161856Syc uint16_t speed_sel0 : 4; /* bits[5:2] */ 78100161856Syc uint16_t speed_sel1 : 1; /* bit 6 */ 78200161856Syc uint16_t res1 : 4; 78300161856Syc uint16_t low_power : 1; 78400161856Syc uint16_t res2 : 1; 78500161856Syc uint16_t speed_sel2 : 1; 78600161856Syc uint16_t loopback : 1; /* bit 14 */ 78700161856Syc uint16_t reset : 1; /* bit 15 */ 78800161856Syc #endif 78900161856Syc } bits; 79000161856Syc } tn1010_phyxs_ctrl_t, *p_tn1010_phyxs_ctrl_t; 79100161856Syc 79200161856Syc /* TN1010 PHY XS Control Register */ 79300161856Syc typedef union _tn1010_phyxs_ctrl { 79400161856Syc uint16_t value; 79500161856Syc struct { 79600161856Syc #ifdef _BIT_FIELDS_HTOL 79700161856Syc uint16_t reset : 1; /* bit 15 */ 79800161856Syc uint16_t loopback : 1; /* bit 14 */ 79900161856Syc uint16_t speed_sel2 : 1; 80000161856Syc uint16_t res2 : 1; 80100161856Syc uint16_t low_power : 1; 80200161856Syc uint16_t res1 : 4; 80300161856Syc uint16_t speed_sel1 : 1; /* bit 6 */ 80400161856Syc uint16_t speed_sel0 : 4; /* bits[5:2] */ 80500161856Syc uint16_t res0 : 2; 80600161856Syc #else 80700161856Syc uint16_t res0 : 2; 80800161856Syc uint16_t speed_sel0 : 4; /* bits[5:2] */ 80900161856Syc uint16_t speed_sel1 : 1; /* bit 6 */ 81000161856Syc uint16_t res1 : 4; 81100161856Syc uint16_t low_power : 1; 81200161856Syc uint16_t res2 : 1; 81300161856Syc uint16_t speed_sel2 : 1; 81400161856Syc uint16_t loopback : 1; /* bit 14 */ 81500161856Syc uint16_t reset : 1; /* bit 15 */ 81600161856Syc #endif 81700161856Syc } bits; 81800161856Syc } tn1010_pcs_ctrl_t, *p_tn1010_pcs_ctrl_t; 81900161856Syc 82000161856Syc /* TN1010 VENDOR MMD1 GPHY Control register 30.310 */ 82100161856Syc #define TN1010_SGMII_LOOPBACK 1 82200161856Syc #define TN1010_DEEP_LOOPBACK 2 82300161856Syc 82400161856Syc #define TN1010_PMD_CONTROL_REG 0 82500161856Syc #define TN1010_PMD_STATUS_REG 1 82600161856Syc #define TN1010_PMD_ID_HIGH_REG 2 82700161856Syc #define TN1010_PMD_ID_LOW_REG 3 82800161856Syc #define TN1010_PMD_SPEED_ABIL_REG 4 82900161856Syc #define TN1010_PMD_DEV_IN_PKG1_REG 5 83000161856Syc #define TN1010_PMD_DEV_IN_PKG2_REG 6 83100161856Syc #define TN1010_PMD_CONTROL2_REG 7 83200161856Syc #define TN1010_PMD_STATUS2_REG 8 83300161856Syc #define TN1010_PMD_TRANSMIT_DIS_REG 9 83400161856Syc #define TN1010_PMD_RECEIVE_SIG_DETECT 10 83500161856Syc #define TN1010_PMD_ORG_UNIQUE_ID_0_REG 14 83600161856Syc #define TN1010_PMD_ORG_UNIQUE_ID_1_REG 15 83700161856Syc #define TN1010_PCS_CONTROL_REG 0 83800161856Syc #define TN1010_PCS_STATUS1_REG 1 83900161856Syc #define TN1010_PCS_ID_HIGH_REG 2 84000161856Syc #define TN1010_PCS_ID_LOW_REG 3 84100161856Syc #define TN1010_PCS_SPEED_ABILITY_REG 4 84200161856Syc #define TN1010_PCS_DEV_IN_PKG1_REG 5 84300161856Syc #define TN1010_PCS_DEV_IN_PKG2_REG 6 84400161856Syc #define TN1010_PCS_CONTROL2_REG 7 84500161856Syc #define TN1010_PCS_STATUS2_REG 8 84600161856Syc #define TN1010_PCS_ORG_UNIQUE_ID_0_REG 14 84700161856Syc #define TN1010_PCS_ORG_UNIQUE_ID_1_REG 15 84800161856Syc #define TN1010_PCS_10GBASE_R_T_STATUS1_REG 32 84900161856Syc #define TN1010_PCS_10GBASE_R_T_STATUS2_REG 33 85000161856Syc #define TN1010_PHYXS_CONTROL_REG 0 85100161856Syc #define TN1010_PHYXS_STATUS_REG 1 85200161856Syc #define TN1010_PHY_ID_HIGH_REG 2 85300161856Syc #define TN1010_PHY_ID_LOW_REG 3 85400161856Syc #define TN1010_PHYXS_SPEED_ABILITY_REG 4 85500161856Syc #define TN1010_PHYXS_DEV_IN_PKG2_REG 5 85600161856Syc #define TN1010_PHYXS_DEV_IN_PKG1_REG 6 85700161856Syc #define TN1010_PHYXS_STATUS2_REG 8 85800161856Syc #define TN1010_PHYXS_ORG_UNIQUE_ID_0_REG 14 85900161856Syc #define TN1010_PHYXS_ORG_UNIQUE_ID_1_REG 15 86000161856Syc #define TN1010_PHYXS_XGXS_LANE_STATUS_REG 24 86100161856Syc #define TN1010_PHYXS_XGXS_TEST_CONTROL_REG 25 86200161856Syc 86300161856Syc #define TN1010_AUTONEG_CONTROL_REG 0 86400161856Syc #define TN1010_AUTONEG_STATUS_REG 1 86500161856Syc #define TN1010_AUTONEG_ID_HIGH_REG 2 86600161856Syc #define TN1010_AUTONEG_ID_LOW_REG 3 86700161856Syc #define TN1010_AUTONEG_DEV_IN_PKG1_REG 5 86800161856Syc #define TN1010_AUTUNEG_DEV_IN_PKG2_REG 6 86900161856Syc #define TN1010_AUTONEG_ORG_UNIQUE_ID_0_REG 14 87000161856Syc #define TN1010_AUTONEG_ORG_UNIQUE_ID_1_REG 15 87100161856Syc #define TN1010_AUTONEG_ADVERTISE_REG 16 87200161856Syc #define TN1010_AUTONEG_PARTNER_ABILITY_REG 19 87300161856Syc 87400161856Syc #define TN1010_VENDOR_MMD1_CONTROL_REG 0 87500161856Syc #define TN1010_VENDOR_MMD1_STATUS_REG 1 87600161856Syc #define TN1010_VENDOR_MMD1_ID_HIGH 2 87700161856Syc #define TN1010_VENDOR_MMD1_ID_LOW 3 87800161856Syc #define TN1010_VENDOR_MMD1_DEV_STATUS_REG 8 87900161856Syc #define TN1010_VENDOR_MMD1_FNS_CONTROL_RER 9 88000161856Syc #define TN1010_VENDOR_MMD1_PKG_ID_0_REG 14 88100161856Syc #define TN1010_VENDOR_MMD1_PKG_ID_1_REG 15 88200161856Syc #define TN1010_VENDOR_MMD1_GPHY_CTRL 310 88300161856Syc 88400161856Syc /* Bits definitions of TN1010_AUTONEG_CONTROL_REG */ 88500161856Syc #define TN1010_AN_CTRL_RESET_BIT 0x8000 /* Reset */ 88600161856Syc #define TN1010_AN_CTRL_EN_BIT 0x1000 /* Enable autoneg */ 88700161856Syc #define TN1010_AN_CTRL_RESTART_BIT 0x200 /* Restart autoneg */ 88800161856Syc #define TN1010_AN_LINK_STAT_BIT 0x4 /* Link status */ 88900161856Syc 89000161856Syc /* Bits definitions of TN1010_PHYXS_CONTROL_REG */ 89100161856Syc #define TN1010_VENDOR_MMD1_AN_STAT_BITS 0xC0 89200161856Syc 89300161856Syc /* 89400161856Syc * Shift right 6 bits so bits[7:6] becomes [1:0]. 89500161856Syc * Bits[7:6] of TN1010_VENDOR_MND1_STATUS_REG are for autoneg status 89600161856Syc * 00 in progress 89700161856Syc * 01 completed 89800161856Syc * 10 reserved 89900161856Syc * 11 failed 90000161856Syc */ 90100161856Syc #define TN1010_VENDOR_MMD1_AN_STAT_SHIFT 6 90200161856Syc 90300161856Syc /* Bit 4 of TN1010_VENDOR_MMD1_STATUS_REG is speed. 0: 10G, 1: 1G */ 90400161856Syc #define TN1010_VENDOR_MMD1_AN_SPEED_BIT 0x10 90500161856Syc 90600161856Syc /* Shift right 4 bits so bit4 becomes bit0 */ 90700161856Syc #define TN1010_VENDOR_MMD1_AN_SPEED_SHIFT 4 90800161856Syc 90989282175SSantwona Behera /* 91089282175SSantwona Behera * Definitions for Netlogic AEL2020 PHY 91189282175SSantwona Behera */ 91289282175SSantwona Behera #define NLP2020_PMA_PMD_ADDR 1 91389282175SSantwona Behera #define NLP2020_PMA_PMD_CTL_REG 0 91489282175SSantwona Behera #define NLP2020_PMA_PMD_PHY_RST 0x8000 91589282175SSantwona Behera 91689282175SSantwona Behera #define NLP2020_PMA_PMD_STAT1_REG 0x0001 91789282175SSantwona Behera #define NLP2020_PMA_PMD_LINK_UP 0x0004 91889282175SSantwona Behera 91989282175SSantwona Behera #define NLP2020_PMA_PMD_RX_SIG_DET_REG 0x000A 92089282175SSantwona Behera #define NLP2020_PMA_PMD_RX_SIG_ON 0x0001 92189282175SSantwona Behera 92289282175SSantwona Behera #define NLP2020_PMA_PMD_STAT2_REG 0x0008 92389282175SSantwona Behera 92489282175SSantwona Behera #define NLP2020_OPT_SET_REG 0xC017 92589282175SSantwona Behera #define NLP2020_RXLOS_ACT_H 0x0020 92689282175SSantwona Behera 92789282175SSantwona Behera #define NLP2020_TX_DRV_CTL1_REG 0xC241 92889282175SSantwona Behera #define NLP2020_TX_DRV_CTL1_PREEMP_EN 0xA000 92989282175SSantwona Behera 93089282175SSantwona Behera #define NLP2020_TX_DRV_CTL2_REG 0xC243 93189282175SSantwona Behera #define NLP2020_TX_DRV_CTL2_EMP_VAL 0xFFD3 93289282175SSantwona Behera 93389282175SSantwona Behera #define NLP2020_UC_CTL_REG 0xD092 93489282175SSantwona Behera #define NLP2020_UC_CTL_STOP 1 93589282175SSantwona Behera #define NLP2020_UC_CTL_START 0 93689282175SSantwona Behera 93789282175SSantwona Behera #define NLP2020_UC_PC_START_REG 0xD080 93889282175SSantwona Behera #define NLP2020_UC_PC_START_VAL 0x100 93989282175SSantwona Behera 94089282175SSantwona Behera #define NLP2020_PHY_PCS_ADDR 3 94189282175SSantwona Behera #define NLP2020_PHY_PCS_STAT1_REG 0x0001 94289282175SSantwona Behera #define NLP2020_PHY_PCS_LINK_UP 0x0004 94389282175SSantwona Behera 94489282175SSantwona Behera #define NLP2020_PHY_PCS_10GBR_STAT1_REG 0x0020 94589282175SSantwona Behera #define NLP2020_PHY_PCS_10GBR_RX_LINK_UP 0x1000 94689282175SSantwona Behera 94789282175SSantwona Behera #define NLP2020_PHY_PCS_STAT2_REG 0x0008 94889282175SSantwona Behera 94989282175SSantwona Behera #define NLP2020_PHY_XS_ADDR 4 95089282175SSantwona Behera #define NLP2020_PHY_XS_STAT1_REG 0x0001 95189282175SSantwona Behera #define NLP2020_PHY_XS_LINK_UP 0x0004 95289282175SSantwona Behera 95389282175SSantwona Behera #define NLP2020_PHY_XS_LN_ST_REG 0x0018 95489282175SSantwona Behera #define NLP2020_PHY_XS_LN_ALIGN_SYNC 0x100f 95589282175SSantwona Behera 95689282175SSantwona Behera #define NLP2020_PHY_XS_STAT2_REG 0x0008 95789282175SSantwona Behera 95889282175SSantwona Behera #define NLP2020_GPIO_ADDR 1 95989282175SSantwona Behera #define NLP2020_GPIO_CTL_REG 0xC108 96089282175SSantwona Behera #define NLP2020_GPIO_STAT_REG 0xC10C 96189282175SSantwona Behera #define NLP2020_GPIO_STAT_MD_SHIFT 0x0004 96289282175SSantwona Behera #define NLP2020_GPIO_STAT_MD_MASK 0x00f0 96389282175SSantwona Behera #define NLP2020_GPIO_PT3_CFG_REG 0xC113 96489282175SSantwona Behera 96589282175SSantwona Behera #define NLP2020_GPIO_ACT 0x0a00 96689282175SSantwona Behera #define NLP2020_GPIO_INACT 0x0b00 96789282175SSantwona Behera 96889282175SSantwona Behera #define NLP2020_I2C_SNOOP_DEV_ADDR 1 96989282175SSantwona Behera #define NLP2020_I2C_SNOOP_ADDR_REG 0xC30A 97089282175SSantwona Behera #define NLP2020_I2C_SNOOP_DATA_REG 0xC30B 97189282175SSantwona Behera #define NLP2020_I2C_SNOOP_STAT_REG 0xC30C 97289282175SSantwona Behera #define NLP2020_XCVR_I2C_ADDR 0x00A0 97389282175SSantwona Behera #define NLP2020_XCVR_I2C_ADDR_SH 0x0008 97489282175SSantwona Behera 97589282175SSantwona Behera /* 97689282175SSantwona Behera * QSFP defines 97789282175SSantwona Behera */ 97889282175SSantwona Behera #define SFPP_COPPER_TWINAX 0x21 97989282175SSantwona Behera #define SFPP_FIBER 0x7 98089282175SSantwona Behera #define QSFP_FIBER 0xC 98189282175SSantwona Behera #define QSFP_COPPER_TWINAX 0x21 98289282175SSantwona Behera 98389282175SSantwona Behera #define QSFP_MSA_CONN_REG 130 98489282175SSantwona Behera #define QSFP_MSA_LPM_REG 93 98589282175SSantwona Behera #define QSFP_MSA_LEN_REG 0x92 98689282175SSantwona Behera #define QSFP_MSA_LPM_HIGH 0x1 98789282175SSantwona Behera 98889282175SSantwona Behera typedef enum { 98989282175SSantwona Behera NXGE_NLP_CONN_FIBER, 99089282175SSantwona Behera NXGE_NLP_CONN_COPPER_LT_7M, 99189282175SSantwona Behera NXGE_NLP_CONN_COPPER_7M_ABOVE 99289282175SSantwona Behera } nxge_nlp_conn_t; 99389282175SSantwona Behera 99489282175SSantwona Behera /* 99589282175SSantwona Behera * struct for PHY addr-value pairs 99689282175SSantwona Behera */ 99789282175SSantwona Behera typedef struct _nxge_nlp_initseq_t { 99889282175SSantwona Behera uint32_t dev_reg; 99989282175SSantwona Behera uint16_t val; 100089282175SSantwona Behera } nxge_nlp_initseq_t, *p_nxge_nlp_initseq_t; 100100161856Syc 1002*9d587972SSantwona Behera /* 1003*9d587972SSantwona Behera * struct for PHY dev, register and value triple properties 1004*9d587972SSantwona Behera */ 1005*9d587972SSantwona Behera typedef struct _nxge_phy_mdio_val_t { 1006*9d587972SSantwona Behera uint16_t dev; 1007*9d587972SSantwona Behera uint16_t reg; 1008*9d587972SSantwona Behera uint16_t val; 1009*9d587972SSantwona Behera } nxge_phy_mdio_val_t, *p_nxge_phy_mdio_val_t; 1010*9d587972SSantwona Behera 1011*9d587972SSantwona Behera /* 1012*9d587972SSantwona Behera * struct for PHY register configurable property 1013*9d587972SSantwona Behera */ 1014*9d587972SSantwona Behera typedef struct _nxge_phy_prop_t { 1015*9d587972SSantwona Behera int cnt; 1016*9d587972SSantwona Behera p_nxge_phy_mdio_val_t arr; 1017*9d587972SSantwona Behera } nxge_phy_prop_t, *p_nxge_phy_prop_t; 1018*9d587972SSantwona Behera 101944961713Sgirish #ifdef __cplusplus 102044961713Sgirish } 102144961713Sgirish #endif 102244961713Sgirish 102344961713Sgirish #endif /* _SYS_NXGE_NXGE_PHY_HW_H */ 1024