1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_MII_H_ 27 #define _SYS_NXGE_NXGE_MII_H_ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Configuration Register space. 37 */ 38 39 #define MII_BMCR 0 40 #define MII_BMSR 1 41 #define MII_IDR1 2 42 #define MII_IDR2 3 43 #define MII_ANAR 4 44 #define MII_ANLPAR 5 45 #define MII_ANER 6 46 #define MII_NPTXR 7 47 #define MII_LPRXNPR 8 48 #define MII_GCR 9 49 #define MII_GSR 10 50 #define MII_RES0 11 51 #define MII_RES1 12 52 #define MII_RES2 13 53 #define MII_RES3 14 54 #define MII_ESR 15 55 #define MII_SHADOW 0x1c 56 /* Shadow register definition */ 57 #define MII_MODE_CONTROL_REG 0x1f 58 59 #define NXGE_MAX_MII_REGS 32 60 61 /* 62 * Configuration Register space. 63 */ 64 typedef struct _mii_regs { 65 uchar_t bmcr; /* Basic mode control register */ 66 uchar_t bmsr; /* Basic mode status register */ 67 uchar_t idr1; /* Phy identifier register 1 */ 68 uchar_t idr2; /* Phy identifier register 2 */ 69 uchar_t anar; /* Auto-Negotiation advertisement register */ 70 uchar_t anlpar; /* Auto-Negotiation link Partner ability reg */ 71 uchar_t aner; /* Auto-Negotiation expansion register */ 72 uchar_t nptxr; /* Next page transmit register */ 73 uchar_t lprxnpr; /* Link partner received next page register */ 74 uchar_t gcr; /* Gigabit basic mode control register. */ 75 uchar_t gsr; /* Gigabit basic mode status register */ 76 uchar_t mii_res1[4]; /* For future use by MII working group */ 77 uchar_t esr; /* Extended status register. */ 78 uchar_t vendor_res[12]; /* For future use by Phy Vendors */ 79 uchar_t shadow; 80 uchar_t vendor_res2[3]; /* For future use by Phy Vendors */ 81 } mii_regs_t, *p_mii_regs_t; 82 83 /* 84 * MII Register 0: Basic mode control register. 85 */ 86 #define BMCR_RES 0x003f /* Unused... */ 87 #define BMCR_SSEL_MSB 0x0040 /* Used to manually select speed */ 88 /* (with * bit 6) when auto-neg */ 89 /* disabled */ 90 #define BMCR_COL_TEST 0x0080 /* Collision test */ 91 #define BMCR_DPLX_MD 0x0100 /* Full duplex */ 92 #define BMCR_RESTART_AN 0x0200 /* Auto negotiation restart */ 93 #define BMCR_ISOLATE 0x0400 /* Disconnect BCM5464R from MII */ 94 #define BMCR_PDOWN 0x0800 /* Powerdown the BCM5464R */ 95 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 96 #define BMCR_SSEL_LSB 0x2000 /* Used to manually select speed */ 97 /* (with bit 13) when auto-neg */ 98 /* disabled */ 99 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 100 #define BMCR_RESET 0x8000 /* Reset the BCM5464R */ 101 102 typedef union _mii_bmcr { 103 uint16_t value; 104 struct { 105 #if defined(_BIT_FIELDS_HTOL) 106 uint16_t reset:1; 107 uint16_t loopback:1; 108 uint16_t speed_sel:1; 109 uint16_t enable_autoneg:1; 110 uint16_t power_down:1; 111 uint16_t isolate:1; 112 uint16_t restart_autoneg:1; 113 uint16_t duplex_mode:1; 114 uint16_t col_test:1; 115 uint16_t speed_1000_sel:1; 116 uint16_t res1:6; 117 #elif defined(_BIT_FIELDS_LTOH) 118 uint16_t res1:6; 119 uint16_t speed_1000_sel:1; 120 uint16_t col_test:1; 121 uint16_t duplex_mode:1; 122 uint16_t restart_autoneg:1; 123 uint16_t isolate:1; 124 uint16_t power_down:1; 125 uint16_t enable_autoneg:1; 126 uint16_t speed_sel:1; 127 uint16_t loopback:1; 128 uint16_t reset:1; 129 #endif 130 } bits; 131 } mii_bmcr_t, *p_mii_bmcr_t; 132 133 /* 134 * MII Register 1: Basic mode status register. 135 */ 136 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 137 #define BMSR_JCD 0x0002 /* Jabber detected */ 138 #define BMSR_LSTATUS 0x0004 /* Link status */ 139 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 140 #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 141 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 142 #define BMSR_MF_PRE_SUP 0x0040 /* Preamble for MIF frame suppressed, */ 143 /* always 1 for BCM5464R */ 144 #define BMSR_RESV 0x0080 /* Unused... */ 145 #define BMSR_ESTAT 0x0100 /* Contains IEEE extended status reg */ 146 #define BMSR_100BASE2HALF 0x0200 /* Can do 100mbps, 2k pkts half-dplx */ 147 #define BMSR_100BASE2FULL 0x0400 /* Can do 100mbps, 2k pkts full-dplx */ 148 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 149 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 150 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 151 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 152 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 153 154 typedef union _mii_bmsr { 155 uint16_t value; 156 struct { 157 #if defined(_BIT_FIELDS_HTOL) 158 uint16_t link_100T4:1; 159 uint16_t link_100fdx:1; 160 uint16_t link_100hdx:1; 161 uint16_t link_10fdx:1; 162 uint16_t link_10hdx:1; 163 uint16_t res2:2; 164 uint16_t extend_status:1; 165 uint16_t res1:1; 166 uint16_t preamble_supress:1; 167 uint16_t auto_neg_complete:1; 168 uint16_t remote_fault:1; 169 uint16_t auto_neg_able:1; 170 uint16_t link_status:1; 171 uint16_t jabber_detect:1; 172 uint16_t ext_cap:1; 173 #elif defined(_BIT_FIELDS_LTOH) 174 int16_t ext_cap:1; 175 uint16_t jabber_detect:1; 176 uint16_t link_status:1; 177 uint16_t auto_neg_able:1; 178 uint16_t remote_fault:1; 179 uint16_t auto_neg_complete:1; 180 uint16_t preamble_supress:1; 181 uint16_t res1:1; 182 uint16_t extend_status:1; 183 uint16_t res2:2; 184 uint16_t link_10hdx:1; 185 uint16_t link_10fdx:1; 186 uint16_t link_100hdx:1; 187 uint16_t link_100fdx:1; 188 uint16_t link_100T4:1; 189 #endif 190 } bits; 191 } mii_bmsr_t, *p_mii_bmsr_t; 192 193 /* 194 * MII Register 2: Physical Identifier 1. 195 */ 196 /* contains BCM OUI bits [3:18] */ 197 typedef union _mii_idr1 { 198 uint16_t value; 199 struct { 200 uint16_t ieee_address:16; 201 } bits; 202 } mii_idr1_t, *p_mii_idr1_t; 203 204 /* 205 * MII Register 3: Physical Identifier 2. 206 */ 207 typedef union _mii_idr2 { 208 uint16_t value; 209 struct { 210 #if defined(_BIT_FIELDS_HTOL) 211 uint16_t ieee_address:6; 212 uint16_t model_no:6; 213 uint16_t rev_no:4; 214 #elif defined(_BIT_FIELDS_LTOH) 215 uint16_t rev_no:4; 216 uint16_t model_no:6; 217 uint16_t ieee_address:6; 218 #endif 219 } bits; 220 } mii_idr2_t, *p_mii_idr2_t; 221 222 /* 223 * MII Register 4: Auto-negotiation advertisement register. 224 */ 225 #define ADVERTISE_SLCT 0x001f /* Selector bits for proto, 0x01 */ 226 /* indicates IEEE 802.3 CSMA/CD phy */ 227 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 228 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 229 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 230 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 231 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 232 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets. set to */ 233 /* 0, BCM5464R not 100BASE-T4 capable */ 234 #define ADVERTISE_RES1 0x0400 /* Unused... */ 235 #define ADVERTISE_ASM_PAUS 0x0800 /* advertise asymmetric pause */ 236 #define ADVERTISE_PAUS 0x1000 /* can do full dplx pause */ 237 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 238 #define ADVERTISE_RES0 0x4000 /* Unused... */ 239 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 240 241 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 242 ADVERTISE_CSMA) 243 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 244 ADVERTISE_100HALF | ADVERTISE_100FULL) 245 246 typedef union _mii_anar { 247 uint16_t value; 248 struct { 249 #if defined(_BIT_FIELDS_HTOL) 250 uint16_t np_indication:1; 251 uint16_t acknowledge:1; 252 uint16_t remote_fault:1; 253 uint16_t res1:1; 254 uint16_t cap_asmpause:1; 255 uint16_t cap_pause:1; 256 uint16_t cap_100T4:1; 257 uint16_t cap_100fdx:1; 258 uint16_t cap_100hdx:1; 259 uint16_t cap_10fdx:1; 260 uint16_t cap_10hdx:1; 261 uint16_t selector:5; 262 #elif defined(_BIT_FIELDS_LTOH) 263 uint16_t selector:5; 264 uint16_t cap_10hdx:1; 265 uint16_t cap_10fdx:1; 266 uint16_t cap_100hdx:1; 267 uint16_t cap_100fdx:1; 268 uint16_t cap_100T4:1; 269 uint16_t cap_pause:1; 270 uint16_t cap_asmpause:1; 271 uint16_t res1:1; 272 uint16_t remote_fault:1; 273 uint16_t acknowledge:1; 274 uint16_t np_indication:1; 275 #endif 276 } bits; 277 } mii_anar_t, *p_mii_anar_t; 278 279 /* 280 * MII Register 5: Auto-negotiation link partner ability register. 281 */ 282 #define LPA_SLCT 0x001f /* Same as advertise selector */ 283 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 284 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 285 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 286 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 287 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 288 #define LPA_RES1 0x0400 /* Unused... */ 289 #define LPA_ASM_PAUS 0x0800 /* advertise asymmetric pause */ 290 #define LPA__PAUS 0x1000 /* can do full dplx pause */ 291 #define LPA_RFAULT 0x2000 /* Link partner faulted */ 292 #define LPA_LPACK 0x4000 /* Link partner acked us */ 293 #define LPA_NPAGE 0x8000 /* Next page bit */ 294 295 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 296 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 297 298 typedef mii_anar_t mii_anlpar_t, *pmii_anlpar_t; 299 300 /* 301 * MII Register 6: Auto-negotiation expansion register. 302 */ 303 #define EXPANSION_LP_AN_ABLE 0x0001 /* Link partner has auto-neg cap */ 304 #define EXPANSION_PG_RX 0x0002 /* Got new RX page code word */ 305 #define EXPANSION_NP_ABLE 0x0004 /* This enables npage words */ 306 #define EXPANSION_LPNP_ABLE 0x0008 /* Link partner supports npage */ 307 #define EXPANSION_MFAULTS 0x0010 /* Multiple link faults detected */ 308 #define EXPANSION_RESV 0xffe0 /* Unused... */ 309 310 typedef union _mii_aner { 311 uint16_t value; 312 struct { 313 #if defined(_BIT_FIELDS_HTOL) 314 uint16_t res:11; 315 uint16_t mlf:1; 316 uint16_t lp_np_able:1; 317 uint16_t np_able:1; 318 uint16_t page_rx:1; 319 uint16_t lp_an_able:1; 320 #else 321 uint16_t lp_an_able:1; 322 uint16_t page_rx:1; 323 uint16_t np_able:1; 324 uint16_t lp_np_able:1; 325 uint16_t mlf:1; 326 uint16_t res:11; 327 #endif 328 } bits; 329 } mii_aner_t, *p_mii_aner_t; 330 331 /* 332 * MII Register 7: Next page transmit register. 333 */ 334 typedef union _mii_nptxr { 335 uint16_t value; 336 struct { 337 #if defined(_BIT_FIELDS_HTOL) 338 uint16_t np:1; 339 uint16_t res:1; 340 uint16_t msgp:1; 341 uint16_t ack2:1; 342 uint16_t toggle:1; 343 uint16_t res1:11; 344 #else 345 uint16_t res1:11; 346 uint16_t toggle:1; 347 uint16_t ack2:1; 348 uint16_t msgp:1; 349 uint16_t res:1; 350 uint16_t np:1; 351 #endif 352 } bits; 353 } mii_nptxr_t, *p_mii_nptxr_t; 354 355 /* 356 * MII Register 8: Link partner received next page register. 357 */ 358 typedef union _mii_lprxnpr { 359 uint16_t value; 360 struct { 361 #if defined(_BIT_FIELDS_HTOL) 362 uint16_t np:1; 363 uint16_t ack:1; 364 uint16_t msgp:1; 365 uint16_t ack2:1; 366 uint16_t toggle:1; 367 uint16_t mcf:11; 368 #else 369 uint16_t mcf:11; 370 uint16_t toggle:1; 371 uint16_t ack2:1; 372 uint16_t msgp:1; 373 uint16_t ack:1; 374 uint16_t np:1; 375 #endif 376 } bits; 377 } mii_lprxnpr_t, *p_mii_lprxnpr_t; 378 379 /* 380 * MII Register 9: 1000BaseT control register. 381 */ 382 typedef union _mii_gcr { 383 uint16_t value; 384 struct { 385 #if defined(_BIT_FIELDS_HTOL) 386 uint16_t test_mode:3; 387 uint16_t ms_mode_en:1; 388 uint16_t master:1; 389 uint16_t dte_or_repeater:1; 390 uint16_t link_1000fdx:1; 391 uint16_t link_1000hdx:1; 392 uint16_t res:8; 393 #else 394 uint16_t res:8; 395 uint16_t link_1000hdx:1; 396 uint16_t link_1000fdx:1; 397 uint16_t dte_or_repeater:1; 398 uint16_t master:1; 399 uint16_t ms_mode_en:1; 400 uint16_t test_mode:3; 401 #endif 402 } bits; 403 } mii_gcr_t, *p_mii_gcr_t; 404 405 /* 406 * MII Register 10: 1000BaseT status register. 407 */ 408 typedef union _mii_gsr { 409 uint16_t value; 410 struct { 411 #if defined(_BIT_FIELDS_HTOL) 412 uint16_t ms_config_fault:1; 413 uint16_t ms_resolve:1; 414 uint16_t local_rx_status:1; 415 uint16_t remote_rx_status:1; 416 uint16_t link_1000fdx:1; 417 uint16_t link_1000hdx:1; 418 uint16_t res:2; 419 uint16_t idle_err_cnt:8; 420 #else 421 uint16_t idle_err_cnt:8; 422 uint16_t res:2; 423 uint16_t link_1000hdx:1; 424 uint16_t link_1000fdx:1; 425 uint16_t remote_rx_status:1; 426 uint16_t local_rx_status:1; 427 uint16_t ms_resolve:1; 428 uint16_t ms_config_fault:1; 429 #endif 430 } bits; 431 } mii_gsr_t, *p_mii_gsr_t; 432 433 /* 434 * MII Register 15: Extended status register. 435 */ 436 typedef union _mii_esr { 437 uint16_t value; 438 struct { 439 #if defined(_BIT_FIELDS_HTOL) 440 uint16_t link_1000Xfdx:1; 441 uint16_t link_1000Xhdx:1; 442 uint16_t link_1000fdx:1; 443 uint16_t link_1000hdx:1; 444 uint16_t res:12; 445 #else 446 uint16_t res:12; 447 uint16_t link_1000hdx:1; 448 uint16_t link_1000fdx:1; 449 uint16_t link_1000Xhdx:1; 450 uint16_t link_1000Xfdx:1; 451 #endif 452 } bits; 453 } mii_esr_t, *p_mii_esr_t; 454 455 #define NXGE_MODE_SELECT_FIBER 0x01 456 /* Shadow regiser 0x11111 */ 457 typedef union _mii_mode_control_stat { 458 uint16_t value; 459 struct { 460 #if defined(_BIT_FIELDS_HTOL) 461 uint16_t write_enable:1; 462 uint16_t shadow:5; 463 uint16_t rsv:1; 464 uint16_t change:1; 465 uint16_t copper:1; 466 uint16_t fiber:1; 467 uint16_t copper_energy:1; 468 uint16_t fiber_signal:1; 469 uint16_t rsv1:1; 470 uint16_t mode:2; 471 uint16_t enable:1; 472 #elif defined(_BIT_FIELDS_LTOH) 473 uint16_t enable:1; 474 uint16_t mode:2; 475 uint16_t rsv1:1; 476 uint16_t fiber_signal:1; 477 uint16_t copper_energy:1; 478 uint16_t fiber:1; 479 uint16_t copper:1; 480 uint16_t change:1; 481 uint16_t rsv:1; 482 uint16_t shadow:5; 483 uint16_t write_enable:1; 484 #endif 485 } bits; 486 } mii_mode_control_stat_t, *p_mode_control_stat_t; 487 488 #ifdef __cplusplus 489 } 490 #endif 491 492 #endif /* _SYS_NXGE_NXGE_MII_H_ */ 493