xref: /illumos-gate/usr/src/uts/common/sys/nxge/nxge_mac_hw.h (revision d81011f02f402699c2c79353f81696ccee019b5c)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_MAC_NXGE_MAC_HW_H
27 #define	_SYS_MAC_NXGE_MAC_HW_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #include <nxge_defs.h>
36 
37 /* -------------------------- From May's template --------------------------- */
38 
39 #define	NXGE_1GETHERMIN			255
40 #define	NXGE_ETHERMIN			97
41 #define	NXGE_MAX_HEADER			250
42 
43 /* Hardware reset */
44 typedef enum  {
45 	NXGE_TX_DISABLE,			/* Disable Tx side */
46 	NXGE_RX_DISABLE,			/* Disable Rx side */
47 	NXGE_CHIP_RESET				/* Full chip reset */
48 } nxge_reset_t;
49 
50 #define	NXGE_DELAY_AFTER_TXRX		10000	/* 10ms after idling rx/tx */
51 #define	NXGE_DELAY_AFTER_RESET		1000	/* 1ms after the reset */
52 #define	NXGE_DELAY_AFTER_EE_RESET	10000	/* 10ms after EEPROM reset */
53 #define	NXGE_DELAY_AFTER_LINK_RESET	13	/* 13 Us after link reset */
54 #define	NXGE_LINK_RESETS		8	/* Max PHY resets to wait for */
55 						/* linkup */
56 
57 #define	FILTER_M_CTL 			0xDCEF1
58 #define	HASH_BITS			8
59 #define	NMCFILTER_BITS			(1 << HASH_BITS)
60 #define	HASH_REG_WIDTH			16
61 #define	BROADCAST_HASH_WORD		0x0f
62 #define	BROADCAST_HASH_BIT		0x8000
63 #define	NMCFILTER_REGS			NMCFILTER_BITS / HASH_REG_WIDTH
64 					/* Number of multicast filter regs */
65 
66 /* -------------------------------------------------------------------------- */
67 
68 #define	XMAC_PORT_0			0
69 #define	XMAC_PORT_1			1
70 #define	BMAC_PORT_0			2
71 #define	BMAC_PORT_1			3
72 
73 #define	MAC_RESET_WAIT			10	/* usecs */
74 
75 #define	MAC_ADDR_REG_MASK		0xFFFF
76 
77 /*
78  * Neptune port PHY type and Speed encoding.
79  *
80  * Per port, 4 bits are reserved for port speed (1G/10G) and 4 bits
81  * are reserved for port PHY type (Copper/Fibre). Bits 0 thru 3 are for port0
82  * speed, bits 4 thru 7 are for port1 speed, bits 8 thru 11 are for port2 speed
83  * and bits 12 thru 15 are for port3 speed. Thus, the first 16 bits hold the
84  * speed encoding for the 4 ports. The next 16 bits (16 thru 31) hold the phy
85  * type encoding for the ports 0 thru 3.
86  *
87  *  p3phy  p2phy  p1phy  p0phy  p3spd p2spd  p1spd p0spd
88  *    |      |      |      |      |     |      |     |
89  *   ---    ---    ---    ---    ---   ---    ---   ---
90  *  /   \  /   \  /   \  /   \  /   \ /   \  /   \ /   \
91  * 31..28 27..24 23..20 19..16 15..12 11.. 8 7.. 4 3.. 0
92  */
93 
94 #define	NXGE_PORT_SPD_NONE	0x0
95 #define	NXGE_PORT_SPD_1G	0x1
96 #define	NXGE_PORT_SPD_10G	0x2
97 #define	NXGE_PORT_SPD_RSVD	0x7
98 
99 #define	NXGE_PHY_NONE		0x0
100 #define	NXGE_PHY_COPPER		0x1
101 #define	NXGE_PHY_FIBRE		0x2
102 #define	NXGE_PHY_SERDES		0x3
103 #define	NXGE_PHY_RGMII_FIBER	0x4
104 #define	NXGE_PHY_RSVD		0x7
105 
106 #define	NXGE_PORT_SPD_SHIFT	0
107 #define	NXGE_PORT_SPD_MASK	0x0f
108 
109 #define	NXGE_PHY_SHIFT		16
110 #define	NXGE_PHY_MASK		0x0f0000
111 
112 #define	NXGE_PORT_1G_COPPER	(NXGE_PORT_SPD_1G |	\
113 	(NXGE_PHY_COPPER << NXGE_PHY_SHIFT))
114 #define	NXGE_PORT_10G_COPPER	(NXGE_PORT_SPD_10G |	\
115 	(NXGE_PHY_COPPER << NXGE_PHY_SHIFT))
116 #define	NXGE_PORT_1G_FIBRE	(NXGE_PORT_SPD_1G |	\
117 	(NXGE_PHY_FIBRE << NXGE_PHY_SHIFT))
118 #define	NXGE_PORT_10G_FIBRE	(NXGE_PORT_SPD_10G |	\
119 	(NXGE_PHY_FIBRE << NXGE_PHY_SHIFT))
120 #define	NXGE_PORT_1G_SERDES	(NXGE_PORT_SPD_1G |	\
121 	(NXGE_PHY_SERDES << NXGE_PHY_SHIFT))
122 #define	NXGE_PORT_10G_SERDES	(NXGE_PORT_SPD_10G |	\
123 	(NXGE_PHY_SERDES << NXGE_PHY_SHIFT))
124 #define	NXGE_PORT_1G_RGMII_FIBER	(NXGE_PORT_SPD_1G |	\
125 	(NXGE_PHY_RGMII_FIBER << NXGE_PHY_SHIFT))
126 #define	NXGE_PORT_NONE		(NXGE_PORT_SPD_NONE |	\
127 	(NXGE_PHY_NONE << NXGE_PHY_SHIFT))
128 #define	NXGE_PORT_RSVD		(NXGE_PORT_SPD_RSVD |	\
129 	(NXGE_PHY_RSVD << NXGE_PHY_SHIFT))
130 
131 #define	NXGE_PORT_TYPE_MASK	(NXGE_PORT_SPD_MASK | NXGE_PHY_MASK)
132 
133 /* number of bits used for phy/spd encoding per port */
134 #define	NXGE_PORT_TYPE_SHIFT	4
135 
136 /* Network Modes */
137 
138 typedef enum nxge_network_mode {
139 	NET_2_10GE_FIBER = 1,
140 	NET_2_10GE_COPPER,
141 	NET_1_10GE_FIBER_3_1GE_COPPER,
142 	NET_1_10GE_COPPER_3_1GE_COPPER,
143 	NET_1_10GE_FIBER_3_1GE_FIBER,
144 	NET_1_10GE_COPPER_3_1GE_FIBER,
145 	NET_2_1GE_FIBER_2_1GE_COPPER,
146 	NET_QGE_FIBER,
147 	NET_QGE_COPPER
148 } nxge_network_mode_t;
149 
150 typedef	enum nxge_port {
151 	PORT_TYPE_XMAC = 1,
152 	PORT_TYPE_BMAC
153 } nxge_port_t;
154 
155 typedef	enum nxge_port_mode {
156 	PORT_1G_COPPER = 1,
157 	PORT_1G_FIBER,
158 	PORT_10G_COPPER,
159 	PORT_10G_FIBER,
160 	PORT_10G_SERDES,
161 	PORT_1G_SERDES,
162 	PORT_1G_RGMII_FIBER
163 } nxge_port_mode_t;
164 
165 typedef	enum nxge_linkchk_mode {
166 	LINKCHK_INTR = 1,
167 	LINKCHK_TIMER
168 } nxge_linkchk_mode_t;
169 
170 typedef enum {
171 	LINK_INTR_STOP,
172 	LINK_INTR_START
173 } link_intr_enable_t, *link_intr_enable_pt;
174 
175 typedef	enum {
176 	LINK_MONITOR_STOP,
177 	LINK_MONITOR_START,
178 	LINK_MONITOR_STOPPING
179 } link_mon_enable_t, *link_mon_enable_pt;
180 
181 typedef enum {
182 	NO_XCVR,
183 	INT_MII_XCVR,
184 	EXT_MII_XCVR,
185 	PCS_XCVR,
186 	XPCS_XCVR
187 } xcvr_inuse_t;
188 
189 /* macros for port offset calculations */
190 
191 #define	PORT_1_OFFSET			0x6000
192 #define	PORT_GT_1_OFFSET		0x4000
193 
194 /* XMAC address macros */
195 
196 #define	XMAC_ADDR_OFFSET_0		0
197 #define	XMAC_ADDR_OFFSET_1		0x6000
198 
199 #define	XMAC_ADDR_OFFSET(port_num)\
200 	(XMAC_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET))
201 
202 #define	XMAC_REG_ADDR(port_num, reg)\
203 	(FZC_MAC + (XMAC_ADDR_OFFSET(port_num)) + (reg))
204 
205 #define	XMAC_PORT_ADDR(port_num)\
206 	(FZC_MAC + XMAC_ADDR_OFFSET(port_num))
207 
208 /* BMAC address macros */
209 
210 #define	BMAC_ADDR_OFFSET_2		0x0C000
211 #define	BMAC_ADDR_OFFSET_3		0x10000
212 
213 #define	BMAC_ADDR_OFFSET(port_num)\
214 	(BMAC_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET))
215 
216 #define	BMAC_REG_ADDR(port_num, reg)\
217 	(FZC_MAC + (BMAC_ADDR_OFFSET(port_num)) + (reg))
218 
219 #define	BMAC_PORT_ADDR(port_num)\
220 	(FZC_MAC + BMAC_ADDR_OFFSET(port_num))
221 
222 /* PCS address macros */
223 
224 #define	PCS_ADDR_OFFSET_0		0x04000
225 #define	PCS_ADDR_OFFSET_1		0x0A000
226 #define	PCS_ADDR_OFFSET_2		0x0E000
227 #define	PCS_ADDR_OFFSET_3		0x12000
228 
229 #define	PCS_ADDR_OFFSET(port_num)\
230 	((port_num <= 1) ? \
231 	(PCS_ADDR_OFFSET_0 + (port_num) * PORT_1_OFFSET) : \
232 	(PCS_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET)))
233 
234 #define	PCS_REG_ADDR(port_num, reg)\
235 	(FZC_MAC + (PCS_ADDR_OFFSET((port_num)) + (reg)))
236 
237 #define	PCS_PORT_ADDR(port_num)\
238 	(FZC_MAC + (PCS_ADDR_OFFSET(port_num)))
239 
240 /* XPCS address macros */
241 
242 #define	XPCS_ADDR_OFFSET_0		0x02000
243 #define	XPCS_ADDR_OFFSET_1		0x08000
244 #define	XPCS_ADDR_OFFSET(port_num)\
245 	(XPCS_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET))
246 
247 #define	XPCS_ADDR(port_num, reg)\
248 	(FZC_MAC + (XPCS_ADDR_OFFSET((port_num)) + (reg)))
249 
250 #define	XPCS_PORT_ADDR(port_num)\
251 	(FZC_MAC + (XPCS_ADDR_OFFSET(port_num)))
252 
253 /* ESR address macro */
254 #define	ESR_ADDR_OFFSET		0x14000
255 #define	ESR_ADDR(reg)\
256 	(FZC_MAC + (ESR_ADDR_OFFSET) + (reg))
257 
258 /* MIF address macros */
259 #define	MIF_ADDR_OFFSET		0x16000
260 #define	MIF_ADDR(reg)\
261 	(FZC_MAC + (MIF_ADDR_OFFSET) + (reg))
262 
263 /* BMAC registers offset */
264 #define	BTXMAC_SW_RST_REG		0x000	/* TX MAC software reset */
265 #define	BRXMAC_SW_RST_REG		0x008	/* RX MAC software reset */
266 #define	MAC_SEND_PAUSE_REG		0x010	/* send pause command */
267 #define	BTXMAC_STATUS_REG		0x020	/* TX MAC status */
268 #define	BRXMAC_STATUS_REG		0x028	/* RX MAC status */
269 #define	BMAC_CTRL_STAT_REG		0x030	/* MAC control status */
270 #define	BTXMAC_STAT_MSK_REG		0x040	/* TX MAC mask */
271 #define	BRXMAC_STAT_MSK_REG		0x048	/* RX MAC mask */
272 #define	BMAC_C_S_MSK_REG		0x050	/* MAC control mask */
273 #define	TXMAC_CONFIG_REG		0x060	/* TX MAC config */
274 /* cfg register bitmap */
275 
276 typedef union _btxmac_config_t {
277 	uint64_t value;
278 
279 	struct {
280 #if defined(_BIG_ENDIAN)
281 		uint32_t msw;	/* Most significant word */
282 		uint32_t lsw;	/* Least significant word */
283 #elif defined(_LITTLE_ENDIAN)
284 		uint32_t lsw;	/* Least significant word */
285 		uint32_t msw;	/* Most significant word */
286 #endif
287 	} val;
288 	struct {
289 #if defined(_BIG_ENDIAN)
290 		uint32_t	w1;
291 #endif
292 		struct {
293 #if defined(_BIT_FIELDS_HTOL)
294 			uint32_t rsrvd	: 22;
295 			uint32_t hdx_ctrl2	: 1;
296 			uint32_t no_fcs	: 1;
297 			uint32_t hdx_ctrl	: 7;
298 			uint32_t txmac_enable	: 1;
299 #elif defined(_BIT_FIELDS_LTOH)
300 			uint32_t txmac_enable	: 1;
301 			uint32_t hdx_ctrl	: 7;
302 			uint32_t no_fcs	: 1;
303 			uint32_t hdx_ctrl2	: 1;
304 			uint32_t rsrvd	: 22;
305 #endif
306 		} w0;
307 
308 #if defined(_LITTLE_ENDIAN)
309 		uint32_t	w1;
310 #endif
311 	} bits;
312 } btxmac_config_t, *p_btxmac_config_t;
313 
314 #define	RXMAC_CONFIG_REG		0x068	/* RX MAC config */
315 
316 typedef union _brxmac_config_t {
317 	uint64_t value;
318 
319 	struct {
320 #if defined(_BIG_ENDIAN)
321 		uint32_t msw;	/* Most significant word */
322 		uint32_t lsw;	/* Least significant word */
323 #elif defined(_LITTLE_ENDIAN)
324 		uint32_t lsw;	/* Least significant word */
325 		uint32_t msw;	/* Most significant word */
326 #endif
327 	} val;
328 	struct {
329 #if defined(_BIG_ENDIAN)
330 		uint32_t	w1;
331 #endif
332 		struct {
333 #if defined(_BIT_FIELDS_HTOL)
334 			uint32_t rsrvd	: 20;
335 			uint32_t mac_reg_sw_test : 2;
336 			uint32_t mac2ipp_pkt_cnt_en : 1;
337 			uint32_t rx_crs_extend_en : 1;
338 			uint32_t error_chk_dis	: 1;
339 			uint32_t addr_filter_en	: 1;
340 			uint32_t hash_filter_en	: 1;
341 			uint32_t promiscuous_group	: 1;
342 			uint32_t promiscuous	: 1;
343 			uint32_t strip_fcs	: 1;
344 			uint32_t strip_pad	: 1;
345 			uint32_t rxmac_enable	: 1;
346 #elif defined(_BIT_FIELDS_LTOH)
347 			uint32_t rxmac_enable	: 1;
348 			uint32_t strip_pad	: 1;
349 			uint32_t strip_fcs	: 1;
350 			uint32_t promiscuous	: 1;
351 			uint32_t promiscuous_group	: 1;
352 			uint32_t hash_filter_en	: 1;
353 			uint32_t addr_filter_en	: 1;
354 			uint32_t error_chk_dis	: 1;
355 			uint32_t rx_crs_extend_en : 1;
356 			uint32_t mac2ipp_pkt_cnt_en : 1;
357 			uint32_t mac_reg_sw_test : 2;
358 			uint32_t rsrvd	: 20;
359 #endif
360 		} w0;
361 
362 #if defined(_LITTLE_ENDIAN)
363 		uint32_t	w1;
364 #endif
365 	} bits;
366 } brxmac_config_t, *p_brxmac_config_t;
367 
368 #define	MAC_CTRL_CONFIG_REG		0x070	/* MAC control config */
369 #define	MAC_XIF_CONFIG_REG		0x078	/* XIF config */
370 
371 typedef union _bxif_config_t {
372 	uint64_t value;
373 
374 	struct {
375 #if defined(_BIG_ENDIAN)
376 		uint32_t msw;	/* Most significant word */
377 		uint32_t lsw;	/* Least significant word */
378 #elif defined(_LITTLE_ENDIAN)
379 		uint32_t lsw;	/* Least significant word */
380 		uint32_t msw;	/* Most significant word */
381 #endif
382 	} val;
383 	struct {
384 #if defined(_BIG_ENDIAN)
385 		uint32_t	w1;
386 #endif
387 		struct {
388 #if defined(_BIT_FIELDS_HTOL)
389 			uint32_t rsrvd2		: 24;
390 			uint32_t sel_clk_25mhz	: 1;
391 			uint32_t led_polarity	: 1;
392 			uint32_t force_led_on	: 1;
393 			uint32_t used		: 1;
394 			uint32_t gmii_mode	: 1;
395 			uint32_t rsrvd		: 1;
396 			uint32_t loopback	: 1;
397 			uint32_t tx_output_en	: 1;
398 #elif defined(_BIT_FIELDS_LTOH)
399 			uint32_t tx_output_en	: 1;
400 			uint32_t loopback	: 1;
401 			uint32_t rsrvd		: 1;
402 			uint32_t gmii_mode	: 1;
403 			uint32_t used		: 1;
404 			uint32_t force_led_on	: 1;
405 			uint32_t led_polarity	: 1;
406 			uint32_t sel_clk_25mhz	: 1;
407 			uint32_t rsrvd2		: 24;
408 #endif
409 		} w0;
410 
411 #if defined(_LITTLE_ENDIAN)
412 		uint32_t	w1;
413 #endif
414 	} bits;
415 } bxif_config_t, *p_bxif_config_t;
416 
417 #define	BMAC_MIN_REG			0x0a0	/* min frame size */
418 #define	BMAC_MAX_REG			0x0a8	/* max frame size reg */
419 #define	MAC_PA_SIZE_REG			0x0b0	/* num of preamble bytes */
420 #define	MAC_CTRL_TYPE_REG		0x0c8	/* type field of MAC ctrl */
421 #define	BMAC_ADDR0_REG			0x100	/* MAC unique ad0 reg (HI 0) */
422 #define	BMAC_ADDR1_REG			0x108	/* MAC unique ad1 reg */
423 #define	BMAC_ADDR2_REG			0x110	/* MAC unique ad2 reg */
424 #define	BMAC_ADDR3_REG			0x118	/* MAC alt ad0 reg (HI 1) */
425 #define	BMAC_ADDR4_REG			0x120	/* MAC alt ad0 reg */
426 #define	BMAC_ADDR5_REG			0x128	/* MAC alt ad0 reg */
427 #define	BMAC_ADDR6_REG			0x130	/* MAC alt ad1 reg (HI 2) */
428 #define	BMAC_ADDR7_REG			0x138	/* MAC alt ad1 reg */
429 #define	BMAC_ADDR8_REG			0x140	/* MAC alt ad1 reg */
430 #define	BMAC_ADDR9_REG			0x148	/* MAC alt ad2 reg (HI 3) */
431 #define	BMAC_ADDR10_REG			0x150	/* MAC alt ad2 reg */
432 #define	BMAC_ADDR11_REG			0x158	/* MAC alt ad2 reg */
433 #define	BMAC_ADDR12_REG			0x160	/* MAC alt ad3 reg (HI 4) */
434 #define	BMAC_ADDR13_REG			0x168	/* MAC alt ad3 reg */
435 #define	BMAC_ADDR14_REG			0x170	/* MAC alt ad3 reg */
436 #define	BMAC_ADDR15_REG			0x178	/* MAC alt ad4 reg (HI 5) */
437 #define	BMAC_ADDR16_REG			0x180	/* MAC alt ad4 reg */
438 #define	BMAC_ADDR17_REG			0x188	/* MAC alt ad4 reg */
439 #define	BMAC_ADDR18_REG			0x190	/* MAC alt ad5 reg (HI 6) */
440 #define	BMAC_ADDR19_REG			0x198	/* MAC alt ad5 reg */
441 #define	BMAC_ADDR20_REG			0x1a0	/* MAC alt ad5 reg */
442 #define	BMAC_ADDR21_REG			0x1a8	/* MAC alt ad6 reg (HI 7) */
443 #define	BMAC_ADDR22_REG			0x1b0	/* MAC alt ad6 reg */
444 #define	BMAC_ADDR23_REG			0x1b8	/* MAC alt ad6 reg */
445 #define	MAC_FC_ADDR0_REG		0x268	/* FC frame addr0 (HI 0, p3) */
446 #define	MAC_FC_ADDR1_REG		0x270	/* FC frame addr1 */
447 #define	MAC_FC_ADDR2_REG		0x278	/* FC frame addr2 */
448 #define	MAC_ADDR_FILT0_REG		0x298	/* bits [47:32] (HI 0, p2) */
449 #define	MAC_ADDR_FILT1_REG		0x2a0	/* bits [31:16] */
450 #define	MAC_ADDR_FILT2_REG		0x2a8	/* bits [15:0]  */
451 #define	MAC_ADDR_FILT12_MASK_REG 	0x2b0	/* addr filter 2 & 1 mask */
452 #define	MAC_ADDR_FILT00_MASK_REG	0x2b8	/* addr filter 0 mask */
453 #define	MAC_HASH_TBL0_REG		0x2c0	/* hash table 0 reg */
454 #define	MAC_HASH_TBL1_REG		0x2c8	/* hash table 1 reg */
455 #define	MAC_HASH_TBL2_REG		0x2d0	/* hash table 2 reg */
456 #define	MAC_HASH_TBL3_REG		0x2d8	/* hash table 3 reg */
457 #define	MAC_HASH_TBL4_REG		0x2e0	/* hash table 4 reg */
458 #define	MAC_HASH_TBL5_REG		0x2e8	/* hash table 5 reg */
459 #define	MAC_HASH_TBL6_REG		0x2f0	/* hash table 6 reg */
460 #define	MAC_HASH_TBL7_REG		0x2f8	/* hash table 7 reg */
461 #define	MAC_HASH_TBL8_REG		0x300	/* hash table 8 reg */
462 #define	MAC_HASH_TBL9_REG		0x308	/* hash table 9 reg */
463 #define	MAC_HASH_TBL10_REG		0x310	/* hash table 10 reg */
464 #define	MAC_HASH_TBL11_REG		0x318	/* hash table 11 reg */
465 #define	MAC_HASH_TBL12_REG		0x320	/* hash table 12 reg */
466 #define	MAC_HASH_TBL13_REG		0x328	/* hash table 13 reg */
467 #define	MAC_HASH_TBL14_REG		0x330	/* hash table 14 reg */
468 #define	MAC_HASH_TBL15_REG		0x338	/* hash table 15 reg */
469 #define	RXMAC_FRM_CNT_REG		0x370	/* receive frame counter */
470 #define	MAC_LEN_ER_CNT_REG		0x378	/* length error counter */
471 #define	BMAC_AL_ER_CNT_REG		0x380	/* alignment error counter */
472 #define	BMAC_CRC_ER_CNT_REG		0x388	/* FCS error counter */
473 #define	BMAC_CD_VIO_CNT_REG		0x390	/* RX code violation err */
474 #define	BMAC_SM_REG			0x3a0	/* (ro) state machine reg */
475 #define	BMAC_ALTAD_CMPEN_REG		0x3f8	/* Alt addr compare enable */
476 #define	BMAC_HOST_INF0_REG		0x400	/* Host info */
477 						/* (own da, add filter, fc) */
478 #define	BMAC_HOST_INF1_REG		0x408	/* Host info (alt ad 0) */
479 #define	BMAC_HOST_INF2_REG		0x410	/* Host info (alt ad 1) */
480 #define	BMAC_HOST_INF3_REG		0x418	/* Host info (alt ad 2) */
481 #define	BMAC_HOST_INF4_REG		0x420	/* Host info (alt ad 3) */
482 #define	BMAC_HOST_INF5_REG		0x428	/* Host info (alt ad 4) */
483 #define	BMAC_HOST_INF6_REG		0x430	/* Host info (alt ad 5) */
484 #define	BMAC_HOST_INF7_REG		0x438	/* Host info (alt ad 6) */
485 #define	BMAC_HOST_INF8_REG		0x440	/* Host info (hash hit, miss) */
486 #define	BTXMAC_BYTE_CNT_REG		0x448	/* Tx byte count */
487 #define	BTXMAC_FRM_CNT_REG		0x450	/* frame count */
488 #define	BRXMAC_BYTE_CNT_REG		0x458	/* Rx byte count */
489 /* x ranges from 0 to 6 (BMAC_MAX_ALT_ADDR_ENTRY - 1) */
490 #define	BMAC_ALT_ADDR0N_REG_ADDR(x)	(BMAC_ADDR3_REG + (x) * 24)
491 #define	BMAC_ALT_ADDR1N_REG_ADDR(x)	(BMAC_ADDR3_REG + 8 + (x) * 24)
492 #define	BMAC_ALT_ADDR2N_REG_ADDR(x)	(BMAC_ADDR3_REG + 0x10 + (x) * 24)
493 #define	BMAC_HASH_TBLN_REG_ADDR(x)	(MAC_HASH_TBL0_REG + (x) * 8)
494 #define	BMAC_HOST_INFN_REG_ADDR(x)	(BMAC_HOST_INF0_REG + (x) * 8)
495 
496 /* XMAC registers offset */
497 #define	XTXMAC_SW_RST_REG		0x000	/* XTX MAC soft reset */
498 #define	XRXMAC_SW_RST_REG		0x008	/* XRX MAC soft reset */
499 #define	XTXMAC_STATUS_REG		0x020	/* XTX MAC status */
500 #define	XRXMAC_STATUS_REG		0x028	/* XRX MAC status */
501 #define	XMAC_CTRL_STAT_REG		0x030	/* Control / Status */
502 #define	XTXMAC_STAT_MSK_REG		0x040	/* XTX MAC Status mask */
503 #define	XRXMAC_STAT_MSK_REG		0x048	/* XRX MAC Status mask */
504 #define	XMAC_C_S_MSK_REG		0x050	/* Control / Status mask */
505 #define	XMAC_CONFIG_REG			0x060	/* Configuration */
506 
507 /* xmac config bit fields */
508 typedef union _xmac_cfg_t {
509 	uint64_t value;
510 
511 	struct {
512 #if defined(_BIG_ENDIAN)
513 		uint32_t msw;	/* Most significant word */
514 		uint32_t lsw;	/* Least significant word */
515 #elif defined(_LITTLE_ENDIAN)
516 		uint32_t lsw;	/* Least significant word */
517 		uint32_t msw;	/* Most significant word */
518 #endif
519 	} val;
520 	struct {
521 #if defined(_BIG_ENDIAN)
522 		uint32_t	w1;
523 #endif
524 		struct {
525 #if defined(_BIT_FIELDS_HTOL)
526 		uint32_t sel_clk_25mhz : 1;
527 		uint32_t pcs_bypass	: 1;
528 		uint32_t xpcs_bypass	: 1;
529 		uint32_t mii_gmii_mode	: 2;
530 		uint32_t lfs_disable	: 1;
531 		uint32_t loopback	: 1;
532 		uint32_t tx_output_en	: 1;
533 		uint32_t sel_por_clk_src : 1;
534 		uint32_t led_polarity	: 1;
535 		uint32_t force_led_on	: 1;
536 		uint32_t pass_fctl_frames : 1;
537 		uint32_t recv_pause_en	: 1;
538 		uint32_t mac2ipp_pkt_cnt_en : 1;
539 		uint32_t strip_crc	: 1;
540 		uint32_t addr_filter_en	: 1;
541 		uint32_t hash_filter_en	: 1;
542 		uint32_t code_viol_chk_dis	: 1;
543 		uint32_t reserved_mcast	: 1;
544 		uint32_t rx_crc_chk_dis	: 1;
545 		uint32_t error_chk_dis	: 1;
546 		uint32_t promisc_grp	: 1;
547 		uint32_t promiscuous	: 1;
548 		uint32_t rx_mac_enable	: 1;
549 		uint32_t warning_msg_en	: 1;
550 		uint32_t used		: 3;
551 		uint32_t always_no_crc	: 1;
552 		uint32_t var_min_ipg_en	: 1;
553 		uint32_t strech_mode	: 1;
554 		uint32_t tx_enable	: 1;
555 #elif defined(_BIT_FIELDS_LTOH)
556 		uint32_t tx_enable	: 1;
557 		uint32_t strech_mode	: 1;
558 		uint32_t var_min_ipg_en	: 1;
559 		uint32_t always_no_crc	: 1;
560 		uint32_t used		: 3;
561 		uint32_t warning_msg_en	: 1;
562 		uint32_t rx_mac_enable	: 1;
563 		uint32_t promiscuous	: 1;
564 		uint32_t promisc_grp	: 1;
565 		uint32_t error_chk_dis	: 1;
566 		uint32_t rx_crc_chk_dis	: 1;
567 		uint32_t reserved_mcast	: 1;
568 		uint32_t code_viol_chk_dis	: 1;
569 		uint32_t hash_filter_en	: 1;
570 		uint32_t addr_filter_en	: 1;
571 		uint32_t strip_crc	: 1;
572 		uint32_t mac2ipp_pkt_cnt_en : 1;
573 		uint32_t recv_pause_en	: 1;
574 		uint32_t pass_fctl_frames : 1;
575 		uint32_t force_led_on	: 1;
576 		uint32_t led_polarity	: 1;
577 		uint32_t sel_por_clk_src : 1;
578 		uint32_t tx_output_en	: 1;
579 		uint32_t loopback	: 1;
580 		uint32_t lfs_disable	: 1;
581 		uint32_t mii_gmii_mode	: 2;
582 		uint32_t xpcs_bypass	: 1;
583 		uint32_t pcs_bypass	: 1;
584 		uint32_t sel_clk_25mhz : 1;
585 #endif
586 		} w0;
587 
588 #if defined(_LITTLE_ENDIAN)
589 		uint32_t	w1;
590 #endif
591 	} bits;
592 } xmac_cfg_t, *p_xmac_cfg_t;
593 
594 #define	XMAC_IPG_REG			0x080	/* Inter-Packet-Gap */
595 #define	XMAC_MIN_REG			0x088	/* min frame size register */
596 #define	XMAC_MAX_REG			0x090	/* max frame/burst size */
597 #define	XMAC_ADDR0_REG			0x0a0	/* [47:32] of MAC addr (HI17) */
598 #define	XMAC_ADDR1_REG			0x0a8	/* [31:16] of MAC addr */
599 #define	XMAC_ADDR2_REG			0x0b0	/* [15:0] of MAC addr */
600 #define	XRXMAC_BT_CNT_REG		0x100	/* bytes received / 8 */
601 #define	XRXMAC_BC_FRM_CNT_REG		0x108	/* good BC frames received */
602 #define	XRXMAC_MC_FRM_CNT_REG		0x110	/* good MC frames received */
603 #define	XRXMAC_FRAG_CNT_REG		0x118	/* frag frames rejected */
604 #define	XRXMAC_HIST_CNT1_REG		0x120	/* 64 bytes frames */
605 #define	XRXMAC_HIST_CNT2_REG		0x128	/* 65-127 bytes frames */
606 #define	XRXMAC_HIST_CNT3_REG		0x130	/* 128-255 bytes frames */
607 #define	XRXMAC_HIST_CNT4_REG		0x138	/* 256-511 bytes frames */
608 #define	XRXMAC_HIST_CNT5_REG		0x140	/* 512-1023 bytes frames */
609 #define	XRXMAC_HIST_CNT6_REG		0x148	/* 1024-1522 bytes frames */
610 #define	XRXMAC_MPSZER_CNT_REG		0x150	/* frames > maxframesize */
611 #define	XRXMAC_CRC_ER_CNT_REG		0x158	/* frames failed CRC */
612 #define	XRXMAC_CD_VIO_CNT_REG		0x160	/* frames with code vio */
613 #define	XRXMAC_AL_ER_CNT_REG		0x168	/* frames with align error */
614 #define	XTXMAC_FRM_CNT_REG		0x170	/* tx frames */
615 #define	XTXMAC_BYTE_CNT_REG		0x178	/* tx bytes / 8 */
616 #define	XMAC_LINK_FLT_CNT_REG		0x180	/* link faults */
617 #define	XRXMAC_HIST_CNT7_REG		0x188	/* MAC2IPP/>1523 bytes frames */
618 #define	XMAC_SM_REG			0x1a8	/* State machine */
619 #define	XMAC_INTERN1_REG		0x1b0	/* internal signals for diag */
620 #define	XMAC_INTERN2_REG		0x1b8	/* internal signals for diag */
621 #define	XMAC_ADDR_CMPEN_REG		0x208	/* alt MAC addr check */
622 #define	XMAC_ADDR3_REG			0x218	/* alt MAC addr 0 (HI 0) */
623 #define	XMAC_ADDR4_REG			0x220	/* alt MAC addr 0 */
624 #define	XMAC_ADDR5_REG			0x228	/* alt MAC addr 0 */
625 #define	XMAC_ADDR6_REG			0x230	/* alt MAC addr 1 (HI 1) */
626 #define	XMAC_ADDR7_REG			0x238	/* alt MAC addr 1 */
627 #define	XMAC_ADDR8_REG			0x240	/* alt MAC addr 1 */
628 #define	XMAC_ADDR9_REG			0x248	/* alt MAC addr 2 (HI 2) */
629 #define	XMAC_ADDR10_REG			0x250	/* alt MAC addr 2 */
630 #define	XMAC_ADDR11_REG			0x258	/* alt MAC addr 2 */
631 #define	XMAC_ADDR12_REG			0x260	/* alt MAC addr 3 (HI 3) */
632 #define	XMAC_ADDR13_REG			0x268	/* alt MAC addr 3 */
633 #define	XMAC_ADDR14_REG			0x270	/* alt MAC addr 3 */
634 #define	XMAC_ADDR15_REG			0x278	/* alt MAC addr 4 (HI 4) */
635 #define	XMAC_ADDR16_REG			0x280	/* alt MAC addr 4 */
636 #define	XMAC_ADDR17_REG			0x288	/* alt MAC addr 4 */
637 #define	XMAC_ADDR18_REG			0x290	/* alt MAC addr 5 (HI 5) */
638 #define	XMAC_ADDR19_REG			0x298	/* alt MAC addr 5 */
639 #define	XMAC_ADDR20_REG			0x2a0	/* alt MAC addr 5 */
640 #define	XMAC_ADDR21_REG			0x2a8	/* alt MAC addr 6 (HI 6) */
641 #define	XMAC_ADDR22_REG			0x2b0	/* alt MAC addr 6 */
642 #define	XMAC_ADDR23_REG			0x2b8	/* alt MAC addr 6 */
643 #define	XMAC_ADDR24_REG			0x2c0	/* alt MAC addr 7 (HI 7) */
644 #define	XMAC_ADDR25_REG			0x2c8	/* alt MAC addr 7 */
645 #define	XMAC_ADDR26_REG			0x2d0	/* alt MAC addr 7 */
646 #define	XMAC_ADDR27_REG			0x2d8	/* alt MAC addr 8 (HI 8) */
647 #define	XMAC_ADDR28_REG			0x2e0	/* alt MAC addr 8 */
648 #define	XMAC_ADDR29_REG			0x2e8	/* alt MAC addr 8 */
649 #define	XMAC_ADDR30_REG			0x2f0	/* alt MAC addr 9 (HI 9) */
650 #define	XMAC_ADDR31_REG			0x2f8	/* alt MAC addr 9 */
651 #define	XMAC_ADDR32_REG			0x300	/* alt MAC addr 9 */
652 #define	XMAC_ADDR33_REG			0x308	/* alt MAC addr 10 (HI 10) */
653 #define	XMAC_ADDR34_REG			0x310	/* alt MAC addr 10 */
654 #define	XMAC_ADDR35_REG			0x318	/* alt MAC addr 10 */
655 #define	XMAC_ADDR36_REG			0x320	/* alt MAC addr 11 (HI 11) */
656 #define	XMAC_ADDR37_REG			0x328	/* alt MAC addr 11 */
657 #define	XMAC_ADDR38_REG			0x330	/* alt MAC addr 11 */
658 #define	XMAC_ADDR39_REG			0x338	/* alt MAC addr 12 (HI 12) */
659 #define	XMAC_ADDR40_REG			0x340	/* alt MAC addr 12 */
660 #define	XMAC_ADDR41_REG			0x348	/* alt MAC addr 12 */
661 #define	XMAC_ADDR42_REG			0x350	/* alt MAC addr 13 (HI 13) */
662 #define	XMAC_ADDR43_REG			0x358	/* alt MAC addr 13 */
663 #define	XMAC_ADDR44_REG			0x360	/* alt MAC addr 13 */
664 #define	XMAC_ADDR45_REG			0x368	/* alt MAC addr 14 (HI 14) */
665 #define	XMAC_ADDR46_REG			0x370	/* alt MAC addr 14 */
666 #define	XMAC_ADDR47_REG			0x378	/* alt MAC addr 14 */
667 #define	XMAC_ADDR48_REG			0x380	/* alt MAC addr 15 (HI 15) */
668 #define	XMAC_ADDR49_REG			0x388	/* alt MAC addr 15 */
669 #define	XMAC_ADDR50_REG			0x390	/* alt MAC addr 15 */
670 #define	XMAC_ADDR_FILT0_REG		0x818	/* [47:32] addr filter (HI18) */
671 #define	XMAC_ADDR_FILT1_REG		0x820	/* [31:16] of addr filter */
672 #define	XMAC_ADDR_FILT2_REG		0x828	/* [15:0] of addr filter */
673 #define	XMAC_ADDR_FILT12_MASK_REG 	0x830	/* addr filter 2 & 1 mask */
674 #define	XMAC_ADDR_FILT0_MASK_REG	0x838	/* addr filter 0 mask */
675 #define	XMAC_HASH_TBL0_REG		0x840	/* hash table 0 reg */
676 #define	XMAC_HASH_TBL1_REG		0x848	/* hash table 1 reg */
677 #define	XMAC_HASH_TBL2_REG		0x850	/* hash table 2 reg */
678 #define	XMAC_HASH_TBL3_REG		0x858	/* hash table 3 reg */
679 #define	XMAC_HASH_TBL4_REG		0x860	/* hash table 4 reg */
680 #define	XMAC_HASH_TBL5_REG		0x868	/* hash table 5 reg */
681 #define	XMAC_HASH_TBL6_REG		0x870	/* hash table 6 reg */
682 #define	XMAC_HASH_TBL7_REG		0x878	/* hash table 7 reg */
683 #define	XMAC_HASH_TBL8_REG		0x880	/* hash table 8 reg */
684 #define	XMAC_HASH_TBL9_REG		0x888	/* hash table 9 reg */
685 #define	XMAC_HASH_TBL10_REG		0x890	/* hash table 10 reg */
686 #define	XMAC_HASH_TBL11_REG		0x898	/* hash table 11 reg */
687 #define	XMAC_HASH_TBL12_REG		0x8a0	/* hash table 12 reg */
688 #define	XMAC_HASH_TBL13_REG		0x8a8	/* hash table 13 reg */
689 #define	XMAC_HASH_TBL14_REG		0x8b0	/* hash table 14 reg */
690 #define	XMAC_HASH_TBL15_REG		0x8b8	/* hash table 15 reg */
691 #define	XMAC_HOST_INF0_REG		0x900	/* Host info 0 (alt ad 0) */
692 #define	XMAC_HOST_INF1_REG		0x908	/* Host info 1 (alt ad 1) */
693 #define	XMAC_HOST_INF2_REG		0x910	/* Host info 2 (alt ad 2) */
694 #define	XMAC_HOST_INF3_REG		0x918	/* Host info 3 (alt ad 3) */
695 #define	XMAC_HOST_INF4_REG		0x920	/* Host info 4 (alt ad 4) */
696 #define	XMAC_HOST_INF5_REG		0x928	/* Host info 5 (alt ad 5) */
697 #define	XMAC_HOST_INF6_REG		0x930	/* Host info 6 (alt ad 6) */
698 #define	XMAC_HOST_INF7_REG		0x938	/* Host info 7 (alt ad 7) */
699 #define	XMAC_HOST_INF8_REG		0x940	/* Host info 8 (alt ad 8) */
700 #define	XMAC_HOST_INF9_REG		0x948	/* Host info 9 (alt ad 9) */
701 #define	XMAC_HOST_INF10_REG		0x950	/* Host info 10 (alt ad 10) */
702 #define	XMAC_HOST_INF11_REG		0x958	/* Host info 11 (alt ad 11) */
703 #define	XMAC_HOST_INF12_REG		0x960	/* Host info 12 (alt ad 12) */
704 #define	XMAC_HOST_INF13_REG		0x968	/* Host info 13 (alt ad 13) */
705 #define	XMAC_HOST_INF14_REG		0x970	/* Host info 14 (alt ad 14) */
706 #define	XMAC_HOST_INF15_REG		0x978	/* Host info 15 (alt ad 15) */
707 #define	XMAC_HOST_INF16_REG		0x980	/* Host info 16 (hash hit) */
708 #define	XMAC_HOST_INF17_REG		0x988	/* Host info 17 (own da) */
709 #define	XMAC_HOST_INF18_REG		0x990	/* Host info 18 (filter hit) */
710 #define	XMAC_HOST_INF19_REG		0x998	/* Host info 19 (fc hit) */
711 #define	XMAC_PA_DATA0_REG		0xb80	/* preamble [31:0] */
712 #define	XMAC_PA_DATA1_REG		0xb88	/* preamble [63:32] */
713 #define	XMAC_DEBUG_SEL_REG		0xb90	/* debug select */
714 #define	XMAC_TRAINING_VECT_REG		0xb98	/* training vector */
715 /* x ranges from 0 to 15 (XMAC_MAX_ALT_ADDR_ENTRY - 1) */
716 #define	XMAC_ALT_ADDR0N_REG_ADDR(x)	(XMAC_ADDR3_REG + (x) * 24)
717 #define	XMAC_ALT_ADDR1N_REG_ADDR(x)	(XMAC_ADDR3_REG + 8 + (x) * 24)
718 #define	XMAC_ALT_ADDR2N_REG_ADDR(x)	(XMAC_ADDR3_REG + 16 + (x) * 24)
719 #define	XMAC_HASH_TBLN_REG_ADDR(x)	(XMAC_HASH_TBL0_REG + (x) * 8)
720 #define	XMAC_HOST_INFN_REG_ADDR(x)	(XMAC_HOST_INF0_REG + (x) * 8)
721 
722 /* MIF registers offset */
723 #define	MIF_BB_MDC_REG			0	   /* MIF bit-bang clock */
724 #define	MIF_BB_MDO_REG			0x008	   /* MIF bit-bang data */
725 #define	MIF_BB_MDO_EN_REG		0x010	   /* MIF bit-bang output en */
726 #define	MIF_OUTPUT_FRAME_REG		0x018	   /* MIF frame/output reg */
727 #define	MIF_CONFIG_REG			0x020	   /* MIF config reg */
728 #define	MIF_POLL_STATUS_REG		0x028	   /* MIF poll status reg */
729 #define	MIF_POLL_MASK_REG		0x030	   /* MIF poll mask reg */
730 #define	MIF_STATE_MACHINE_REG		0x038	   /* MIF state machine reg */
731 #define	MIF_STATUS_REG			0x040	   /* MIF status reg */
732 #define	MIF_MASK_REG			0x048	   /* MIF mask reg */
733 
734 
735 /* PCS registers offset */
736 #define	PCS_MII_CTRL_REG		0	   /* PCS MII control reg */
737 #define	PCS_MII_STATUS_REG		0x008	   /* PCS MII status reg */
738 #define	PCS_MII_ADVERT_REG		0x010	   /* PCS MII advertisement */
739 #define	PCS_MII_LPA_REG			0x018	   /* link partner ability */
740 #define	PCS_CONFIG_REG			0x020	   /* PCS config reg */
741 #define	PCS_STATE_MACHINE_REG		0x028	   /* PCS state machine */
742 #define	PCS_INTR_STATUS_REG		0x030	/* PCS interrupt status */
743 #define	PCS_DATAPATH_MODE_REG		0x0a0	   /* datapath mode reg */
744 #define	PCS_PACKET_COUNT_REG		0x0c0	   /* PCS packet counter */
745 
746 #define	XPCS_CTRL_1_REG			0	/* Control */
747 #define	XPCS_STATUS_1_REG		0x008
748 #define	XPCS_DEV_ID_REG			0x010	/* 32bits IEEE manufacture ID */
749 #define	XPCS_SPEED_ABILITY_REG		0x018
750 #define	XPCS_DEV_IN_PKG_REG		0x020
751 #define	XPCS_CTRL_2_REG			0x028
752 #define	XPCS_STATUS_2_REG		0x030
753 #define	XPCS_PKG_ID_REG			0x038	/* Package ID */
754 #define	XPCS_STATUS_REG			0x040
755 #define	XPCS_TEST_CTRL_REG		0x048
756 #define	XPCS_CFG_VENDOR_1_REG		0x050
757 #define	XPCS_DIAG_VENDOR_2_REG		0x058
758 #define	XPCS_MASK_1_REG			0x060
759 #define	XPCS_PKT_CNTR_REG		0x068
760 #define	XPCS_TX_STATE_MC_REG		0x070
761 #define	XPCS_DESKEW_ERR_CNTR_REG	0x078
762 #define	XPCS_SYM_ERR_CNTR_L0_L1_REG	0x080
763 #define	XPCS_SYM_ERR_CNTR_L2_L3_REG	0x088
764 #define	XPCS_TRAINING_VECTOR_REG	0x090
765 
766 /* ESR registers offset */
767 #define	ESR_RESET_REG			0
768 #define	ESR_CONFIG_REG			0x008
769 #define	ESR_0_PLL_CONFIG_REG		0x010
770 #define	ESR_0_CONTROL_REG		0x018
771 #define	ESR_0_TEST_CONFIG_REG		0x020
772 #define	ESR_1_PLL_CONFIG_REG		0x028
773 #define	ESR_1_CONTROL_REG		0x030
774 #define	ESR_1_TEST_CONFIG_REG		0x038
775 #define	ESR_ENET_RGMII_CFG_REG		0x040
776 #define	ESR_INTERNAL_SIGNALS_REG	0x800
777 #define	ESR_DEBUG_SEL_REG		0x808
778 
779 
780 /* Reset Register */
781 #define	MAC_SEND_PAUSE_TIME_MASK	0x0000FFFF /* value of pause time */
782 #define	MAC_SEND_PAUSE_SEND		0x00010000 /* send pause flow ctrl */
783 
784 /* Tx MAC Status Register */
785 #define	MAC_TX_FRAME_XMIT		0x00000001 /* successful tx frame */
786 #define	MAC_TX_UNDERRUN			0x00000002 /* starvation in xmit */
787 #define	MAC_TX_MAX_PACKET_ERR		0x00000004 /* TX frame exceeds max */
788 #define	MAC_TX_BYTE_CNT_EXP		0x00000400 /* TX byte cnt overflow */
789 #define	MAC_TX_FRAME_CNT_EXP		0x00000800 /* Tx frame cnt overflow */
790 
791 /* Rx MAC Status Register */
792 #define	MAC_RX_FRAME_RECV		0x00000001 /* successful rx frame */
793 #define	MAC_RX_OVERFLOW			0x00000002 /* RX FIFO overflow */
794 #define	MAC_RX_FRAME_COUNT		0x00000004 /* rx frame cnt rollover */
795 #define	MAC_RX_ALIGN_ERR		0x00000008 /* alignment err rollover */
796 #define	MAC_RX_CRC_ERR			0x00000010 /* crc error cnt rollover */
797 #define	MAC_RX_LEN_ERR			0x00000020 /* length err cnt rollover */
798 #define	MAC_RX_VIOL_ERR			0x00000040 /* code vio err rollover */
799 #define	MAC_RX_BYTE_CNT_EXP		0x00000080 /* RX MAC byte rollover */
800 
801 /* MAC Control Status Register */
802 #define	MAC_CTRL_PAUSE_RECEIVED		0x00000001 /* successful pause frame */
803 #define	MAC_CTRL_PAUSE_STATE		0x00000002 /* notpause-->pause */
804 #define	MAC_CTRL_NOPAUSE_STATE		0x00000004 /* pause-->notpause */
805 #define	MAC_CTRL_PAUSE_TIME_MASK	0xFFFF0000 /* value of pause time */
806 #define	MAC_CTRL_PAUSE_TIME_SHIFT	16
807 
808 /* Tx MAC Configuration Register */
809 #define	MAC_TX_CFG_TXMAC_ENABLE		0x00000001 /* enable TX MAC. */
810 #define	MAC_TX_CFG_NO_FCS		0x00000100 /* TX not generate CRC */
811 
812 /* Rx MAC Configuration Register */
813 #define	MAC_RX_CFG_RXMAC_ENABLE		0x00000001 /* enable RX MAC */
814 #define	MAC_RX_CFG_STRIP_PAD		0x00000002 /* not supported, set to 0 */
815 #define	MAC_RX_CFG_STRIP_FCS		0x00000004 /* strip last 4bytes (CRC) */
816 #define	MAC_RX_CFG_PROMISC		0x00000008 /* promisc mode enable */
817 #define	MAC_RX_CFG_PROMISC_GROUP  	0x00000010 /* accept all MC frames */
818 #define	MAC_RX_CFG_HASH_FILTER_EN	0x00000020 /* use hash table */
819 #define	MAC_RX_CFG_ADDR_FILTER_EN    	0x00000040 /* use address filter */
820 #define	MAC_RX_CFG_DISABLE_DISCARD	0x00000080 /* do not set abort bit */
821 #define	MAC_RX_MAC2IPP_PKT_CNT_EN	0x00000200 /* rx pkt cnt -> BMAC-IPP */
822 #define	MAC_RX_MAC_REG_RW_TEST_MASK	0x00000c00 /* BMAC reg RW test */
823 #define	MAC_RX_MAC_REG_RW_TEST_SHIFT	10
824 
825 /* MAC Control Configuration Register */
826 #define	MAC_CTRL_CFG_SEND_PAUSE_EN	0x00000001 /* send pause flow ctrl */
827 #define	MAC_CTRL_CFG_RECV_PAUSE_EN	0x00000002 /* receive pause flow ctrl */
828 #define	MAC_CTRL_CFG_PASS_CTRL		0x00000004 /* accept MAC ctrl pkts */
829 
830 /* MAC XIF Configuration Register */
831 #define	MAC_XIF_TX_OUTPUT_EN		0x00000001 /* enable Tx output driver */
832 #define	MAC_XIF_MII_INT_LOOPBACK	0x00000002 /* loopback GMII xmit data */
833 #define	MAC_XIF_GMII_MODE		0x00000008 /* operates with GMII clks */
834 #define	MAC_XIF_LINK_LED		0x00000020 /* LINKLED# active (low) */
835 #define	MAC_XIF_LED_POLARITY		0x00000040 /* LED polarity */
836 #define	MAC_XIF_SEL_CLK_25MHZ		0x00000080 /* Select 10/100Mbps */
837 
838 /* MAC IPG Registers */
839 #define	BMAC_MIN_FRAME_MASK		0x3FF	   /* 10-bit reg */
840 
841 /* MAC Max Frame Size Register */
842 #define	BMAC_MAX_BURST_MASK    		0x3FFF0000 /* max burst size [30:16] */
843 #define	BMAC_MAX_BURST_SHIFT   		16
844 #define	BMAC_MAX_FRAME_MASK    		0x00007FFF /* max frame size [14:0] */
845 #define	BMAC_MAX_FRAME_SHIFT   		0
846 
847 /* MAC Preamble size register */
848 #define	BMAC_PA_SIZE_MASK		0x000003FF
849 	/* # of preable bytes TxMAC sends at the beginning of each frame */
850 
851 /*
852  * mac address registers:
853  *	register	contains			comparison
854  *	--------	--------			----------
855  *	0		16 MSB of primary MAC addr	[47:32] of DA field
856  *	1		16 middle bits ""		[31:16] of DA field
857  *	2		16 LSB ""			[15:0] of DA field
858  *	3*x		16MSB of alt MAC addr 1-7	[47:32] of DA field
859  *	4*x		16 middle bits ""		[31:16]
860  *	5*x		16 LSB ""			[15:0]
861  *	42		16 MSB of MAC CTRL addr		[47:32] of DA.
862  *	43		16 middle bits ""		[31:16]
863  *	44		16 LSB ""			[15:0]
864  *	MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
865  *	if there is a match, MAC will set the bit for alternative address
866  *	filter pass [15]
867  *
868  *	here is the map of registers given MAC address notation: a:b:c:d:e:f
869  *			ab		cd		ef
870  *	primary addr	reg 2		reg 1		reg 0
871  *	alt addr 1	reg 5		reg 4		reg 3
872  *	alt addr x	reg 5*x		reg 4*x		reg 3*x
873  *	|		|		|		|
874  *	|		|		|		|
875  *	alt addr 7	reg 23		reg 22		reg 21
876  *	ctrl addr	reg 44		reg 43		reg 42
877  */
878 
879 #define	BMAC_ALT_ADDR_BASE		0x118
880 #define	BMAC_MAX_ALT_ADDR_ENTRY		7	   /* 7 alternate MAC addr */
881 #define	BMAC_MAX_ADDR_ENTRY		(BMAC_MAX_ALT_ADDR_ENTRY + 1)
882 
883 /* hash table registers */
884 #define	MAC_MAX_HASH_ENTRY		16
885 
886 /* 27-bit register has the current state for key state machines in the MAC */
887 #define	MAC_SM_RLM_MASK			0x07800000
888 #define	MAC_SM_RLM_SHIFT		23
889 #define	MAC_SM_RX_FC_MASK		0x00700000
890 #define	MAC_SM_RX_FC_SHIFT		20
891 #define	MAC_SM_TLM_MASK			0x000F0000
892 #define	MAC_SM_TLM_SHIFT		16
893 #define	MAC_SM_ENCAP_SM_MASK		0x0000F000
894 #define	MAC_SM_ENCAP_SM_SHIFT		12
895 #define	MAC_SM_TX_REQ_MASK		0x00000C00
896 #define	MAC_SM_TX_REQ_SHIFT		10
897 #define	MAC_SM_TX_FC_MASK		0x000003C0
898 #define	MAC_SM_TX_FC_SHIFT		6
899 #define	MAC_SM_FIFO_WRITE_SEL_MASK	0x00000038
900 #define	MAC_SM_FIFO_WRITE_SEL_SHIFT	3
901 #define	MAC_SM_TX_FIFO_EMPTY_MASK	0x00000007
902 #define	MAC_SM_TX_FIFO_EMPTY_SHIFT	0
903 
904 #define	BMAC_ADDR0_CMPEN		0x00000001
905 #define	BMAC_ADDRN_CMPEN(x)		(BMAC_ADDR0_CMP_EN << (x))
906 
907 /* MAC Host Info Table Registers */
908 #define	BMAC_MAX_HOST_INFO_ENTRY	9 	/* 9 host entries */
909 
910 /*
911  * ********************* XMAC registers *********************************
912  */
913 
914 /* Reset Register */
915 #define	XTXMAC_SOFT_RST			0x00000001 /* XTX MAC software reset */
916 #define	XTXMAC_REG_RST			0x00000002 /* XTX MAC registers reset */
917 #define	XRXMAC_SOFT_RST			0x00000001 /* XRX MAC software reset */
918 #define	XRXMAC_REG_RST			0x00000002 /* XRX MAC registers reset */
919 
920 /* XTX MAC Status Register */
921 #define	XMAC_TX_FRAME_XMIT		0x00000001 /* successful tx frame */
922 #define	XMAC_TX_UNDERRUN		0x00000002 /* starvation in xmit */
923 #define	XMAC_TX_MAX_PACKET_ERR		0x00000004 /* XTX frame exceeds max */
924 #define	XMAC_TX_OVERFLOW		0x00000008 /* XTX byte cnt overflow */
925 #define	XMAC_TX_FIFO_XFR_ERR		0x00000010 /* xtlm state mach error */
926 #define	XMAC_TX_BYTE_CNT_EXP		0x00000400 /* XTX byte cnt overflow */
927 #define	XMAC_TX_FRAME_CNT_EXP		0x00000800 /* XTX frame cnt overflow */
928 
929 /* XRX MAC Status Register */
930 #define	XMAC_RX_FRAME_RCVD		0x00000001 /* successful rx frame */
931 #define	XMAC_RX_OVERFLOW		0x00000002 /* RX FIFO overflow */
932 #define	XMAC_RX_UNDERFLOW		0x00000004 /* RX FIFO underrun */
933 #define	XMAC_RX_CRC_ERR_CNT_EXP		0x00000008 /* crc error cnt rollover */
934 #define	XMAC_RX_LEN_ERR_CNT_EXP		0x00000010 /* length err cnt rollover */
935 #define	XMAC_RX_VIOL_ERR_CNT_EXP	0x00000020 /* code vio err rollover */
936 #define	XMAC_RX_OCT_CNT_EXP		0x00000040 /* XRX MAC byte rollover */
937 #define	XMAC_RX_HST_CNT1_EXP		0x00000080 /* XRX MAC hist1 rollover */
938 #define	XMAC_RX_HST_CNT2_EXP		0x00000100 /* XRX MAC hist2 rollover */
939 #define	XMAC_RX_HST_CNT3_EXP		0x00000200 /* XRX MAC hist3 rollover */
940 #define	XMAC_RX_HST_CNT4_EXP		0x00000400 /* XRX MAC hist4 rollover */
941 #define	XMAC_RX_HST_CNT5_EXP		0x00000800 /* XRX MAC hist5 rollover */
942 #define	XMAC_RX_HST_CNT6_EXP		0x00001000 /* XRX MAC hist6 rollover */
943 #define	XMAC_RX_BCAST_CNT_EXP		0x00002000 /* XRX BC cnt rollover */
944 #define	XMAC_RX_MCAST_CNT_EXP		0x00004000 /* XRX MC cnt rollover */
945 #define	XMAC_RX_FRAG_CNT_EXP		0x00008000 /* fragment cnt rollover */
946 #define	XMAC_RX_ALIGNERR_CNT_EXP	0x00010000 /* framealign err rollover */
947 #define	XMAC_RX_LINK_FLT_CNT_EXP	0x00020000 /* link fault cnt rollover */
948 #define	XMAC_RX_REMOTE_FLT_DET		0x00040000 /* Remote Fault detected */
949 #define	XMAC_RX_LOCAL_FLT_DET		0x00080000 /* Local Fault detected */
950 #define	XMAC_RX_HST_CNT7_EXP		0x00100000 /* XRX MAC hist7 rollover */
951 
952 
953 #define	XMAC_CTRL_PAUSE_RCVD		0x00000001 /* successful pause frame */
954 #define	XMAC_CTRL_PAUSE_STATE		0x00000002 /* notpause-->pause */
955 #define	XMAC_CTRL_NOPAUSE_STATE		0x00000004 /* pause-->notpause */
956 #define	XMAC_CTRL_PAUSE_TIME_MASK	0xFFFF0000 /* value of pause time */
957 #define	XMAC_CTRL_PAUSE_TIME_SHIFT	16
958 
959 /* XMAC Configuration Register */
960 #define	XMAC_CONFIG_TX_BIT_MASK		0x000000ff /* bits [7:0] */
961 #define	XMAC_CONFIG_RX_BIT_MASK		0x001fff00 /* bits [20:8] */
962 #define	XMAC_CONFIG_XIF_BIT_MASK	0xffe00000 /* bits [31:21] */
963 
964 /* XTX MAC config bits */
965 #define	XMAC_TX_CFG_TX_ENABLE		0x00000001 /* enable XTX MAC */
966 #define	XMAC_TX_CFG_STRETCH_MD		0x00000002 /* WAN application */
967 #define	XMAC_TX_CFG_VAR_MIN_IPG_EN	0x00000004 /* Transmit pkts < minpsz */
968 #define	XMAC_TX_CFG_ALWAYS_NO_CRC	0x00000008 /* No CRC generated */
969 
970 #define	XMAC_WARNING_MSG_ENABLE		0x00000080 /* Sim warning msg enable */
971 
972 /* XRX MAC config bits */
973 #define	XMAC_RX_CFG_RX_ENABLE		0x00000100 /* enable XRX MAC */
974 #define	XMAC_RX_CFG_PROMISC		0x00000200 /* promisc mode enable */
975 #define	XMAC_RX_CFG_PROMISC_GROUP  	0x00000400 /* accept all MC frames */
976 #define	XMAC_RX_CFG_ERR_CHK_DISABLE	0x00000800 /* do not set abort bit */
977 #define	XMAC_RX_CFG_CRC_CHK_DISABLE	0x00001000 /* disable CRC logic */
978 #define	XMAC_RX_CFG_RESERVED_MCAST	0x00002000 /* reserved MCaddr compare */
979 #define	XMAC_RX_CFG_CD_VIO_CHK		0x00004000 /* rx code violation chk */
980 #define	XMAC_RX_CFG_HASH_FILTER_EN	0x00008000 /* use hash table */
981 #define	XMAC_RX_CFG_ADDR_FILTER_EN	0x00010000 /* use alt addr filter */
982 #define	XMAC_RX_CFG_STRIP_CRC		0x00020000 /* strip last 4bytes (CRC) */
983 #define	XMAC_RX_MAC2IPP_PKT_CNT_EN	0x00040000 /* histo_cntr7 cnt mode */
984 #define	XMAC_RX_CFG_RX_PAUSE_EN		0x00080000 /* receive pause flow ctrl */
985 #define	XMAC_RX_CFG_PASS_FLOW_CTRL	0x00100000 /* accept MAC ctrl pkts */
986 
987 
988 /* MAC transceiver (XIF) configuration registers */
989 
990 #define	XMAC_XIF_FORCE_LED_ON		0x00200000 /* Force Link LED on */
991 #define	XMAC_XIF_LED_POLARITY		0x00400000 /* LED polarity */
992 #define	XMAC_XIF_SEL_POR_CLK_SRC	0x00800000 /* Select POR clk src */
993 #define	XMAC_XIF_TX_OUTPUT_EN		0x01000000 /* enable MII/GMII modes */
994 #define	XMAC_XIF_LOOPBACK		0x02000000 /* loopback xmac xgmii tx */
995 #define	XMAC_XIF_LFS_DISABLE		0x04000000 /* disable link fault sig */
996 #define	XMAC_XIF_MII_MODE_MASK		0x18000000 /* MII/GMII/XGMII mode */
997 #define	XMAC_XIF_MII_MODE_SHIFT		27
998 #define	XMAC_XIF_XGMII_MODE		0x00
999 #define	XMAC_XIF_GMII_MODE		0x01
1000 #define	XMAC_XIF_MII_MODE		0x02
1001 #define	XMAC_XIF_ILLEGAL_MODE		0x03
1002 #define	XMAC_XIF_XPCS_BYPASS		0x20000000 /* use external xpcs */
1003 #define	XMAC_XIF_1G_PCS_BYPASS		0x40000000 /* use external pcs */
1004 #define	XMAC_XIF_SEL_CLK_25MHZ		0x80000000 /* 25Mhz clk for 100mbps */
1005 
1006 /* IPG register */
1007 #define	XMAC_IPG_VALUE_MASK		0x00000007 /* IPG in XGMII mode */
1008 #define	XMAC_IPG_VALUE_SHIFT		0
1009 #define	XMAC_IPG_VALUE1_MASK		0x0000ff00 /* IPG in GMII/MII mode */
1010 #define	XMAC_IPG_VALUE1_SHIFT		8
1011 #define	XMAC_IPG_STRETCH_RATIO_MASK	0x001f0000
1012 #define	XMAC_IPG_STRETCH_RATIO_SHIFT	16
1013 #define	XMAC_IPG_STRETCH_CONST_MASK	0x00e00000
1014 #define	XMAC_IPG_STRETCH_CONST_SHIFT	21
1015 
1016 #define	IPG_12_15_BYTE			3
1017 #define	IPG_16_19_BYTE			4
1018 #define	IPG_20_23_BYTE			5
1019 #define	IPG1_12_BYTES			10
1020 #define	IPG1_13_BYTES			11
1021 #define	IPG1_14_BYTES			12
1022 #define	IPG1_15_BYTES			13
1023 #define	IPG1_16_BYTES			14
1024 
1025 
1026 #define	XMAC_MIN_TX_FRM_SZ_MASK		0x3ff	   /* Min tx frame size */
1027 #define	XMAC_MIN_TX_FRM_SZ_SHIFT	0
1028 #define	XMAC_SLOT_TIME_MASK		0x0003fc00 /* slot time */
1029 #define	XMAC_SLOT_TIME_SHIFT		10
1030 #define	XMAC_MIN_RX_FRM_SZ_MASK		0x3ff00000 /* Min rx frame size */
1031 #define	XMAC_MIN_RX_FRM_SZ_SHIFT	20
1032 #define	XMAC_MAX_FRM_SZ_MASK		0x00003fff /* max tx frame size */
1033 
1034 /* State Machine Register */
1035 #define	XMAC_SM_TX_LNK_MGMT_MASK	0x00000007
1036 #define	XMAC_SM_TX_LNK_MGMT_SHIFT	0
1037 #define	XMAC_SM_SOP_DETECT		0x00000008
1038 #define	XMAC_SM_LNK_FLT_SIG_MASK	0x00000030
1039 #define	XMAC_SM_LNK_FLT_SIG_SHIFT	4
1040 #define	XMAC_SM_MII_GMII_MD_RX_LNK	0x00000040
1041 #define	XMAC_SM_XGMII_MD_RX_LNK		0x00000080
1042 #define	XMAC_SM_XGMII_ONLY_VAL_SIG	0x00000100
1043 #define	XMAC_SM_ALT_ADR_N_HSH_FN_SIG	0x00000200
1044 #define	XMAC_SM_RXMAC_IPP_STAT_MASK	0x00001c00
1045 #define	XMAC_SM_RXMAC_IPP_STAT_SHIFT	10
1046 #define	XMAC_SM_RXFIFO_WPTR_CLK_MASK	0x007c0000
1047 #define	XMAC_SM_RXFIFO_WPTR_CLK_SHIFT	18
1048 #define	XMAC_SM_RXFIFO_RPTR_CLK_MASK	0x0F800000
1049 #define	XMAC_SM_RXFIFO_RPTR_CLK_SHIFT	23
1050 #define	XMAC_SM_TXFIFO_FULL_CLK		0x10000000
1051 #define	XMAC_SM_TXFIFO_EMPTY_CLK	0x20000000
1052 #define	XMAC_SM_RXFIFO_FULL_CLK		0x40000000
1053 #define	XMAC_SM_RXFIFO_EMPTY_CLK	0x80000000
1054 
1055 /* Internal Signals 1 Register */
1056 #define	XMAC_IS1_OPP_TXMAC_STAT_MASK	0x0000000F
1057 #define	XMAC_IS1_OPP_TXMAC_STAT_SHIFT	0
1058 #define	XMAC_IS1_OPP_TXMAC_ABORT	0x00000010
1059 #define	XMAC_IS1_OPP_TXMAC_TAG 		0x00000020
1060 #define	XMAC_IS1_OPP_TXMAC_ACK		0x00000040
1061 #define	XMAC_IS1_TXMAC_OPP_REQ		0x00000080
1062 #define	XMAC_IS1_RXMAC_IPP_STAT_MASK	0x0FFFFF00
1063 #define	XMAC_IS1_RXMAC_IPP_STAT_SHIFT	8
1064 #define	XMAC_IS1_RXMAC_IPP_CTRL		0x10000000
1065 #define	XMAC_IS1_RXMAC_IPP_TAG		0x20000000
1066 #define	XMAC_IS1_IPP_RXMAC_REQ		0x40000000
1067 #define	XMAC_IS1_RXMAC_IPP_ACK		0x80000000
1068 
1069 /* Internal Signals 2 Register */
1070 #define	XMAC_IS2_TX_HB_TIMER_MASK	0x0000000F
1071 #define	XMAC_IS2_TX_HB_TIMER_SHIFT	0
1072 #define	XMAC_IS2_RX_HB_TIMER_MASK	0x000000F0
1073 #define	XMAC_IS2_RX_HB_TIMER_SHIFT	4
1074 #define	XMAC_IS2_XPCS_RXC_MASK		0x0000FF00
1075 #define	XMAC_IS2_XPCS_RXC_SHIFT		8
1076 #define	XMAC_IS2_XPCS_TXC_MASK		0x00FF0000
1077 #define	XMAC_IS2_XPCS_TXC_SHIFT		16
1078 #define	XMAC_IS2_LOCAL_FLT_OC_SYNC	0x01000000
1079 #define	XMAC_IS2_RMT_FLT_OC_SYNC	0x02000000
1080 
1081 /* Register size masking */
1082 
1083 #define	XTXMAC_FRM_CNT_MASK		0xFFFFFFFF
1084 #define	XTXMAC_BYTE_CNT_MASK		0xFFFFFFFF
1085 #define	XRXMAC_CRC_ER_CNT_MASK		0x000000FF
1086 #define	XRXMAC_MPSZER_CNT_MASK		0x000000FF
1087 #define	XRXMAC_CD_VIO_CNT_MASK		0x000000FF
1088 #define	XRXMAC_BT_CNT_MASK		0xFFFFFFFF
1089 #define	XRXMAC_HIST_CNT1_MASK		0x001FFFFF
1090 #define	XRXMAC_HIST_CNT2_MASK		0x001FFFFF
1091 #define	XRXMAC_HIST_CNT3_MASK		0x000FFFFF
1092 #define	XRXMAC_HIST_CNT4_MASK		0x0007FFFF
1093 #define	XRXMAC_HIST_CNT5_MASK		0x0003FFFF
1094 #define	XRXMAC_HIST_CNT6_MASK		0x0001FFFF
1095 #define	XRXMAC_BC_FRM_CNT_MASK		0x001FFFFF
1096 #define	XRXMAC_MC_FRM_CNT_MASK		0x001FFFFF
1097 #define	XRXMAC_FRAG_CNT_MASK		0x001FFFFF
1098 #define	XRXMAC_AL_ER_CNT_MASK		0x000000FF
1099 #define	XMAC_LINK_FLT_CNT_MASK		0x000000FF
1100 #define	BTXMAC_FRM_CNT_MASK		0x001FFFFF
1101 #define	BTXMAC_BYTE_CNT_MASK		0x07FFFFFF
1102 #define	RXMAC_FRM_CNT_MASK		0x0000FFFF
1103 #define	BRXMAC_BYTE_CNT_MASK		0x07FFFFFF
1104 #define	BMAC_AL_ER_CNT_MASK		0x0000FFFF
1105 #define	MAC_LEN_ER_CNT_MASK		0x0000FFFF
1106 #define	BMAC_CRC_ER_CNT_MASK		0x0000FFFF
1107 #define	BMAC_CD_VIO_CNT_MASK		0x0000FFFF
1108 #define	XMAC_XPCS_DESKEW_ERR_CNT_MASK	0x000000FF
1109 #define	XMAC_XPCS_SYM_ERR_CNT_L0_MASK	0x0000FFFF
1110 #define	XMAC_XPCS_SYM_ERR_CNT_L1_MASK	0xFFFF0000
1111 #define	XMAC_XPCS_SYM_ERR_CNT_L1_SHIFT	16
1112 #define	XMAC_XPCS_SYM_ERR_CNT_L2_MASK	0x0000FFFF
1113 #define	XMAC_XPCS_SYM_ERR_CNT_L3_MASK	0xFFFF0000
1114 #define	XMAC_XPCS_SYM_ERR_CNT_L3_SHIFT	16
1115 
1116 /* Alternate MAC address registers */
1117 #define	XMAC_MAX_ALT_ADDR_ENTRY		16	   /* 16 alternate MAC addrs */
1118 #define	XMAC_MAX_ADDR_ENTRY		(XMAC_MAX_ALT_ADDR_ENTRY + 1)
1119 
1120 /* Max / Min parameters for Neptune MAC */
1121 
1122 #define	MAC_MAX_ALT_ADDR_ENTRY		XMAC_MAX_ALT_ADDR_ENTRY
1123 #define	MAC_MAX_HOST_INFO_ENTRY		XMAC_MAX_HOST_INFO_ENTRY
1124 
1125 /* HostInfo entry for the unique MAC address */
1126 #define	XMAC_UNIQUE_HOST_INFO_ENTRY	17
1127 #define	BMAC_UNIQUE_HOST_INFO_ENTRY	0
1128 
1129 /* HostInfo entry for the multicat address */
1130 #define	XMAC_MULTI_HOST_INFO_ENTRY	16
1131 #define	BMAC_MULTI_HOST_INFO_ENTRY	8
1132 
1133 /* XMAC Host Info Register */
1134 typedef union hostinfo {
1135 
1136 	uint64_t value;
1137 
1138 	struct {
1139 #if defined(_BIG_ENDIAN)
1140 		uint32_t msw;	/* Most significant word */
1141 		uint32_t lsw;	/* Least significant word */
1142 #elif defined(_LITTLE_ENDIAN)
1143 		uint32_t lsw;	/* Least significant word */
1144 		uint32_t msw;	/* Most significant word */
1145 #endif
1146 	} val;
1147 	struct {
1148 #if defined(_BIG_ENDIAN)
1149 		uint32_t	w1;
1150 #endif
1151 		struct {
1152 #if defined(_BIT_FIELDS_HTOL)
1153 		uint32_t reserved2	: 23;
1154 		uint32_t mac_pref	: 1;
1155 		uint32_t reserved1	: 5;
1156 		uint32_t rdc_tbl_num	: 3;
1157 #elif defined(_BIT_FIELDS_LTOH)
1158 		uint32_t rdc_tbl_num	: 3;
1159 		uint32_t reserved1	: 5;
1160 		uint32_t mac_pref	: 1;
1161 		uint32_t reserved2	: 23;
1162 #endif
1163 		} w0;
1164 
1165 #if defined(_LITTLE_ENDIAN)
1166 		uint32_t	w1;
1167 #endif
1168 	} bits;
1169 
1170 } hostinfo_t;
1171 
1172 typedef union hostinfo *hostinfo_pt;
1173 
1174 #define	XMAC_HI_RDC_TBL_NUM_MASK	0x00000007
1175 #define	XMAC_HI_MAC_PREF		0x00000100
1176 
1177 #define	XMAC_MAX_HOST_INFO_ENTRY	20	   /* 20 host entries */
1178 
1179 /*
1180  * ******************** MIF registers *********************************
1181  */
1182 
1183 /*
1184  * 32-bit register serves as an instruction register when the MIF is
1185  * programmed in frame mode. load this register w/ a valid instruction
1186  * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1187  * execution completion. during a read operation, this register will also
1188  * contain the 16-bit data returned by the transceiver. unless specified
1189  * otherwise, fields are considered "don't care" when polling for
1190  * completion.
1191  */
1192 
1193 #define	MIF_FRAME_START_MASK		0xC0000000 /* start of frame mask */
1194 #define	MIF_FRAME_ST_22			0x40000000 /* STart of frame, Cl 22 */
1195 #define	MIF_FRAME_ST_45			0x00000000 /* STart of frame, Cl 45 */
1196 #define	MIF_FRAME_OPCODE_MASK		0x30000000 /* opcode */
1197 #define	MIF_FRAME_OP_READ_22		0x20000000 /* read OPcode, Cl 22 */
1198 #define	MIF_FRAME_OP_WRITE_22		0x10000000 /* write OPcode, Cl 22 */
1199 #define	MIF_FRAME_OP_ADDR_45		0x00000000 /* addr of reg to access */
1200 #define	MIF_FRAME_OP_READ_45		0x30000000 /* read OPcode, Cl 45 */
1201 #define	MIF_FRAME_OP_WRITE_45		0x10000000 /* write OPcode, Cl 45 */
1202 #define	MIF_FRAME_OP_P_R_I_A_45		0x10000000 /* post-read-inc-addr */
1203 #define	MIF_FRAME_PHY_ADDR_MASK		0x0F800000 /* phy address mask */
1204 #define	MIF_FRAME_PHY_ADDR_SHIFT	23
1205 #define	MIF_FRAME_REG_ADDR_MASK		0x007C0000 /* reg addr in Cl 22 */
1206 						/* dev addr in Cl 45 */
1207 #define	MIF_FRAME_REG_ADDR_SHIFT	18
1208 #define	MIF_FRAME_TURN_AROUND_MSB	0x00020000 /* turn around, MSB. */
1209 #define	MIF_FRAME_TURN_AROUND_LSB	0x00010000 /* turn around, LSB. */
1210 #define	MIF_FRAME_DATA_MASK		0x0000FFFF /* instruction payload */
1211 
1212 /* Clause 45 frame field values */
1213 #define	FRAME45_ST		0
1214 #define	FRAME45_OP_ADDR		0
1215 #define	FRAME45_OP_WRITE	1
1216 #define	FRAME45_OP_READ_INC	2
1217 #define	FRAME45_OP_READ		3
1218 
1219 typedef union _mif_frame_t {
1220 
1221 	uint64_t value;
1222 
1223 	struct {
1224 #if defined(_BIG_ENDIAN)
1225 		uint32_t msw;	/* Most significant word */
1226 		uint32_t lsw;	/* Least significant word */
1227 #elif defined(_LITTLE_ENDIAN)
1228 		uint32_t lsw;	/* Least significant word */
1229 		uint32_t msw;	/* Most significant word */
1230 #endif
1231 	} val;
1232 	struct {
1233 #if defined(_BIG_ENDIAN)
1234 		uint32_t	w1;
1235 #endif
1236 		struct {
1237 #if defined(_BIT_FIELDS_HTOL)
1238 		uint32_t st		: 2;
1239 		uint32_t op		: 2;
1240 		uint32_t phyad		: 5;
1241 		uint32_t regad		: 5;
1242 		uint32_t ta_msb		: 1;
1243 		uint32_t ta_lsb		: 1;
1244 		uint32_t data		: 16;
1245 #elif defined(_BIT_FIELDS_LTOH)
1246 		uint32_t data		: 16;
1247 		uint32_t ta_lsb		: 1;
1248 		uint32_t ta_msb		: 1;
1249 		uint32_t regad		: 5;
1250 		uint32_t phyad		: 5;
1251 		uint32_t op		: 2;
1252 		uint32_t st		: 2;
1253 #endif
1254 		} w0;
1255 
1256 #if defined(_LITTLE_ENDIAN)
1257 		uint32_t	w1;
1258 #endif
1259 	} bits;
1260 } mif_frame_t;
1261 
1262 #define	MIF_CFG_POLL_EN			0x00000008 /* enable polling */
1263 #define	MIF_CFG_BB_MODE			0x00000010 /* bit-bang mode */
1264 #define	MIF_CFG_POLL_REG_MASK		0x000003E0 /* reg addr to be polled */
1265 #define	MIF_CFG_POLL_REG_SHIFT		5
1266 #define	MIF_CFG_POLL_PHY_MASK		0x00007C00 /* XCVR addr to be polled */
1267 #define	MIF_CFG_POLL_PHY_SHIFT		10
1268 #define	MIF_CFG_INDIRECT_MODE		0x0000800
1269 					/* used to decide if Cl 22 */
1270 					/* or Cl 45 frame is */
1271 					/* constructed. */
1272 					/* 1 = Clause 45,ST = '00' */
1273 					/* 0 = Clause 22,ST = '01' */
1274 #define	MIF_CFG_ATCE_GE_EN	0x00010000 /* Enable ATCA gigabit mode */
1275 
1276 typedef union _mif_cfg_t {
1277 
1278 	uint64_t value;
1279 
1280 	struct {
1281 #if defined(_BIG_ENDIAN)
1282 		uint32_t msw;	/* Most significant word */
1283 		uint32_t lsw;	/* Least significant word */
1284 
1285 #elif defined(_LITTLE_ENDIAN)
1286 		uint32_t lsw;	/* Least significant word */
1287 		uint32_t msw;	/* Most significant word */
1288 #endif
1289 	} val;
1290 	struct {
1291 #if defined(_BIG_ENDIAN)
1292 		uint32_t	w1;
1293 #endif
1294 		struct {
1295 #if defined(_BIT_FIELDS_HTOL)
1296 		uint32_t res2		: 15;
1297 		uint32_t atca_ge	: 1;
1298 		uint32_t indirect_md	: 1;
1299 		uint32_t phy_addr	: 5;
1300 		uint32_t reg_addr	: 5;
1301 		uint32_t bb_mode	: 1;
1302 		uint32_t poll_en	: 1;
1303 		uint32_t res1		: 2;
1304 		uint32_t res		: 1;
1305 #elif defined(_BIT_FIELDS_LTOH)
1306 		uint32_t res		: 1;
1307 		uint32_t res1		: 2;
1308 		uint32_t poll_en	: 1;
1309 		uint32_t bb_mode	: 1;
1310 		uint32_t reg_addr	: 5;
1311 		uint32_t phy_addr	: 5;
1312 		uint32_t indirect_md	: 1;
1313 		uint32_t atca_ge	: 1;
1314 		uint32_t res2		: 15;
1315 #endif
1316 		} w0;
1317 
1318 #if defined(_LITTLE_ENDIAN)
1319 		uint32_t	w1;
1320 #endif
1321 	} bits;
1322 
1323 } mif_cfg_t;
1324 
1325 #define	MIF_POLL_STATUS_DATA_MASK	0xffff0000
1326 #define	MIF_POLL_STATUS_STAT_MASK	0x0000ffff
1327 
1328 typedef union _mif_poll_stat_t {
1329 	uint64_t value;
1330 
1331 	struct {
1332 #if defined(_BIG_ENDIAN)
1333 		uint32_t msw;	/* Most significant word */
1334 		uint32_t lsw;	/* Least significant word */
1335 #elif defined(_LITTLE_ENDIAN)
1336 		uint32_t lsw;	/* Least significant word */
1337 		uint32_t msw;	/* Most significant word */
1338 #endif
1339 	} val;
1340 	struct {
1341 #if defined(_BIG_ENDIAN)
1342 		uint32_t	w1;
1343 #endif
1344 		struct {
1345 #if defined(_BIT_FIELDS_HTOL)
1346 		uint16_t data;
1347 		uint16_t status;
1348 #elif defined(_BIT_FIELDS_LTOH)
1349 		uint16_t status;
1350 		uint16_t data;
1351 #endif
1352 		} w0;
1353 
1354 #if defined(_LITTLE_ENDIAN)
1355 		uint32_t	w1;
1356 #endif
1357 	} bits;
1358 } mif_poll_stat_t;
1359 
1360 
1361 #define	MIF_POLL_MASK_MASK	0x0000ffff
1362 
1363 typedef union _mif_poll_mask_t {
1364 	uint64_t value;
1365 
1366 	struct {
1367 #if defined(_BIG_ENDIAN)
1368 		uint32_t msw;	/* Most significant word */
1369 		uint32_t lsw;	/* Least significant word */
1370 #elif defined(_LITTLE_ENDIAN)
1371 		uint32_t lsw;	/* Least significant word */
1372 		uint32_t msw;	/* Most significant word */
1373 #endif
1374 	} val;
1375 	struct {
1376 #if defined(_BIG_ENDIAN)
1377 		uint32_t	w1;
1378 #endif
1379 		struct {
1380 #if defined(_BIT_FIELDS_HTOL)
1381 		uint16_t rsvd;
1382 		uint16_t mask;
1383 #elif defined(_BIT_FIELDS_LTOH)
1384 		uint16_t mask;
1385 		uint16_t rsvd;
1386 #endif
1387 		} w0;
1388 
1389 #if defined(_LITTLE_ENDIAN)
1390 		uint32_t	w1;
1391 #endif
1392 	} bits;
1393 } mif_poll_mask_t;
1394 
1395 #define	MIF_STATUS_INIT_DONE_MASK	0x00000001
1396 #define	MIF_STATUS_XGE_ERR0_MASK	0x00000002
1397 #define	MIF_STATUS_XGE_ERR1_MASK	0x00000004
1398 #define	MIF_STATUS_PEU_ERR_MASK		0x00000008
1399 #define	MIF_STATUS_EXT_PHY_INTR0_MASK	0x00000010
1400 #define	MIF_STATUS_EXT_PHY_INTR1_MASK	0x00000020
1401 
1402 typedef union _mif_stat_t {
1403 	uint64_t value;
1404 
1405 	struct {
1406 #if defined(_BIG_ENDIAN)
1407 		uint32_t msw;	/* Most significant word */
1408 		uint32_t lsw;	/* Least significant word */
1409 #elif defined(_LITTLE_ENDIAN)
1410 		uint32_t lsw;	/* Least significant word */
1411 		uint32_t msw;	/* Most significant word */
1412 #endif
1413 	} val;
1414 	struct {
1415 #if defined(_BIG_ENDIAN)
1416 		uint32_t	w1;
1417 #endif
1418 		struct {
1419 #if defined(_BIT_FIELDS_HTOL)
1420 		uint32_t rsvd:26;
1421 		uint32_t ext_phy_intr_flag1:1;
1422 		uint32_t ext_phy_intr_flag0:1;
1423 		uint32_t peu_err:1;
1424 		uint32_t xge_err1:1;
1425 		uint32_t xge_err0:1;
1426 		uint32_t mif_init_done_stat:1;
1427 
1428 #elif defined(_BIT_FIELDS_LTOH)
1429 		uint32_t mif_init_done_stat:1;
1430 		uint32_t xge_err0:1;
1431 		uint32_t xge_err1:1;
1432 		uint32_t ext_phy_intr_flag0:1;
1433 		uint32_t ext_phy_intr_flag1:1;
1434 		uint32_t rsvd:26;
1435 #endif
1436 		} w0;
1437 
1438 #if defined(_LITTLE_ENDIAN)
1439 		uint32_t	w1;
1440 #endif
1441 	} bits;
1442 } mif_stat_t;
1443 
1444 /* MIF State Machine Register */
1445 
1446 #define	MIF_SM_EXECUTION_MASK		0x0000003f /* execution state */
1447 #define	MIF_SM_EXECUTION_SHIFT		0
1448 #define	MIF_SM_CONTROL_MASK		0x000001c0 /* control state */
1449 #define	MIF_SM_CONTROL_MASK_SHIFT	6
1450 #define	MIF_SM_MDI			0x00000200
1451 #define	MIF_SM_MDO			0x00000400
1452 #define	MIF_SM_MDO_EN			0x00000800
1453 #define	MIF_SM_MDC			0x00001000
1454 #define	MIF_SM_MDI_0			0x00002000
1455 #define	MIF_SM_MDI_1			0x00004000
1456 #define	MIF_SM_MDI_2			0x00008000
1457 #define	MIF_SM_PORT_ADDR_MASK		0x001f0000
1458 #define	MIF_SM_PORT_ADDR_SHIFT		16
1459 #define	MIF_SM_INT_SIG_MASK		0xffe00000
1460 #define	MIF_SM_INT_SIG_SHIFT		21
1461 
1462 
1463 /*
1464  * ******************** PCS registers *********************************
1465  */
1466 
1467 /* PCS Registers */
1468 #define	PCS_MII_CTRL_1000_SEL		0x0040	   /* reads 1. ignored on wr */
1469 #define	PCS_MII_CTRL_COLLISION_TEST	0x0080	   /* COL signal */
1470 #define	PCS_MII_CTRL_DUPLEX		0x0100	   /* forced 0x0. */
1471 #define	PCS_MII_RESTART_AUTONEG		0x0200	   /* self clearing. */
1472 #define	PCS_MII_ISOLATE			0x0400	   /* read 0. ignored on wr */
1473 #define	PCS_MII_POWER_DOWN		0x0800	   /* read 0. ignored on wr */
1474 #define	PCS_MII_AUTONEG_EN		0x1000	   /* autonegotiation */
1475 #define	PCS_MII_10_100_SEL		0x2000	   /* read 0. ignored on wr */
1476 #define	PCS_MII_RESET			0x8000	   /* reset PCS. */
1477 
1478 typedef union _pcs_ctrl_t {
1479 	uint64_t value;
1480 
1481 	struct {
1482 #if defined(_BIG_ENDIAN)
1483 		uint32_t msw;	/* Most significant word */
1484 		uint32_t lsw;	/* Least significant word */
1485 #elif defined(_LITTLE_ENDIAN)
1486 		uint32_t lsw;	/* Least significant word */
1487 		uint32_t msw;	/* Most significant word */
1488 #endif
1489 	} val;
1490 	struct {
1491 #if defined(_BIG_ENDIAN)
1492 		uint32_t	w1;
1493 #endif
1494 		struct {
1495 #if defined(_BIT_FIELDS_HTOL)
1496 			uint32_t res0		: 16;
1497 			uint32_t reset		: 1;
1498 			uint32_t res1		: 1;
1499 			uint32_t sel_10_100	: 1;
1500 			uint32_t an_enable	: 1;
1501 			uint32_t pwr_down	: 1;
1502 			uint32_t isolate	: 1;
1503 			uint32_t restart_an	: 1;
1504 			uint32_t duplex		: 1;
1505 			uint32_t col_test	: 1;
1506 			uint32_t sel_1000	: 1;
1507 			uint32_t res2		: 6;
1508 #elif defined(_BIT_FIELDS_LTOH)
1509 			uint32_t res2		: 6;
1510 			uint32_t sel_1000	: 1;
1511 			uint32_t col_test	: 1;
1512 			uint32_t duplex		: 1;
1513 			uint32_t restart_an	: 1;
1514 			uint32_t isolate	: 1;
1515 			uint32_t pwr_down	: 1;
1516 			uint32_t an_enable	: 1;
1517 			uint32_t sel_10_100	: 1;
1518 			uint32_t res1		: 1;
1519 			uint32_t reset		: 1;
1520 			uint32_t res0		: 16;
1521 #endif
1522 		} w0;
1523 
1524 #if defined(_LITTLE_ENDIAN)
1525 		uint32_t	w1;
1526 #endif
1527 	} bits;
1528 } pcs_ctrl_t;
1529 
1530 #define	PCS_MII_STATUS_EXTEND_CAP	0x0001	   /* reads 0 */
1531 #define	PCS_MII_STATUS_JABBER_DETECT	0x0002	   /* reads 0 */
1532 #define	PCS_MII_STATUS_LINK_STATUS	0x0004	   /* link status */
1533 #define	PCS_MII_STATUS_AUTONEG_ABLE	0x0008	   /* reads 1 */
1534 #define	PCS_MII_STATUS_REMOTE_FAULT	0x0010	   /* remote fault detected */
1535 #define	PCS_MII_STATUS_AUTONEG_COMP	0x0020	   /* auto-neg completed */
1536 #define	PCS_MII_STATUS_EXTEND_STATUS	0x0100	   /* 1000 Base-X PHY */
1537 
1538 typedef union _pcs_stat_t {
1539 	uint64_t value;
1540 
1541 	struct {
1542 #if defined(_BIG_ENDIAN)
1543 		uint32_t msw;	/* Most significant word */
1544 		uint32_t lsw;	/* Least significant word */
1545 #elif defined(_LITTLE_ENDIAN)
1546 		uint32_t lsw;	/* Least significant word */
1547 		uint32_t msw;	/* Most significant word */
1548 #endif
1549 	} val;
1550 	struct {
1551 #if defined(_BIG_ENDIAN)
1552 		uint32_t	w1;
1553 #endif
1554 		struct {
1555 #if defined(_BIT_FIELDS_HTOL)
1556 		uint32_t res0		: 23;
1557 		uint32_t ext_stat	: 1;
1558 		uint32_t res1		: 2;
1559 		uint32_t an_complete	: 1;
1560 		uint32_t remote_fault	: 1;
1561 		uint32_t an_able	: 1;
1562 		uint32_t link_stat	: 1;
1563 		uint32_t jabber_detect	: 1;
1564 		uint32_t ext_cap	: 1;
1565 #elif defined(_BIT_FIELDS_LTOH)
1566 		uint32_t ext_cap	: 1;
1567 		uint32_t jabber_detect	: 1;
1568 		uint32_t link_stat	: 1;
1569 		uint32_t an_able	: 1;
1570 		uint32_t remote_fault	: 1;
1571 		uint32_t an_complete	: 1;
1572 		uint32_t res1		: 2;
1573 		uint32_t ext_stat	: 1;
1574 		uint32_t res0		: 23;
1575 #endif
1576 		} w0;
1577 
1578 #if defined(_LITTLE_ENDIAN)
1579 		uint32_t	w1;
1580 #endif
1581 	} bits;
1582 } pcs_stat_t;
1583 
1584 #define	PCS_MII_ADVERT_FD		0x0020	   /* advertise full duplex */
1585 #define	PCS_MII_ADVERT_HD		0x0040	   /* advertise half-duplex */
1586 #define	PCS_MII_ADVERT_SYM_PAUSE	0x0080	   /* advertise PAUSE sym */
1587 #define	PCS_MII_ADVERT_ASYM_PAUSE	0x0100	   /* advertises PAUSE asym */
1588 #define	PCS_MII_ADVERT_RF_MASK		0x3000	   /* remote fault */
1589 #define	PCS_MII_ADVERT_RF_SHIFT		12
1590 #define	PCS_MII_ADVERT_ACK		0x4000	   /* (ro) */
1591 #define	PCS_MII_ADVERT_NEXT_PAGE	0x8000	   /* (ro) forced 0x0 */
1592 
1593 #define	PCS_MII_LPA_FD			PCS_MII_ADVERT_FD
1594 #define	PCS_MII_LPA_HD			PCS_MII_ADVERT_HD
1595 #define	PCS_MII_LPA_SYM_PAUSE		PCS_MII_ADVERT_SYM_PAUSE
1596 #define	PCS_MII_LPA_ASYM_PAUSE		PCS_MII_ADVERT_ASYM_PAUSE
1597 #define	PCS_MII_LPA_RF_MASK		PCS_MII_ADVERT_RF_MASK
1598 #define	PCS_MII_LPA_RF_SHIFT		PCS_MII_ADVERT_RF_SHIFT
1599 #define	PCS_MII_LPA_ACK			PCS_MII_ADVERT_ACK
1600 #define	PCS_MII_LPA_NEXT_PAGE		PCS_MII_ADVERT_NEXT_PAGE
1601 
1602 typedef union _pcs_anar_t {
1603 	uint64_t value;
1604 
1605 	struct {
1606 #if defined(_BIG_ENDIAN)
1607 		uint32_t msw;	/* Most significant word */
1608 		uint32_t lsw;	/* Least significant word */
1609 #elif defined(_LITTLE_ENDIAN)
1610 		uint32_t lsw;	/* Least significant word */
1611 		uint32_t msw;	/* Most significant word */
1612 #endif
1613 	} val;
1614 	struct {
1615 #if defined(_BIG_ENDIAN)
1616 		uint32_t	w1;
1617 #endif
1618 		struct {
1619 #if defined(_BIT_FIELDS_HTOL)
1620 		uint32_t res0		: 16;
1621 		uint32_t next_page	: 1;
1622 		uint32_t ack		: 1;
1623 		uint32_t remote_fault	: 2;
1624 		uint32_t res1		: 3;
1625 		uint32_t asm_pause	: 1;
1626 		uint32_t pause		: 1;
1627 		uint32_t half_duplex	: 1;
1628 		uint32_t full_duplex	: 1;
1629 		uint32_t res2		: 5;
1630 #elif defined(_BIT_FIELDS_LTOH)
1631 		uint32_t res2		: 5;
1632 		uint32_t full_duplex	: 1;
1633 		uint32_t half_duplex	: 1;
1634 		uint32_t pause		: 1;
1635 		uint32_t asm_pause	: 1;
1636 		uint32_t res1		: 3;
1637 		uint32_t remore_fault	: 2;
1638 		uint32_t ack		: 1;
1639 		uint32_t next_page	: 1;
1640 		uint32_t res0		: 16;
1641 #endif
1642 		} w0;
1643 
1644 #if defined(_LITTLE_ENDIAN)
1645 		uint32_t	w1;
1646 #endif
1647 	} bits;
1648 } pcs_anar_t, *p_pcs_anar_t;
1649 
1650 #define	PCS_CFG_EN			0x0001	   /* enable PCS. */
1651 #define	PCS_CFG_SD_OVERRIDE		0x0002
1652 #define	PCS_CFG_SD_ACTIVE_LOW		0x0004	   /* sig detect active low */
1653 #define	PCS_CFG_JITTER_STUDY_MASK	0x0018	   /* jitter measurements */
1654 #define	PCS_CFG_JITTER_STUDY_SHIFT	4
1655 #define	PCS_CFG_10MS_TIMER_OVERRIDE	0x0020	   /* shortens autoneg timer */
1656 #define	PCS_CFG_MASK			0x0040	   /* PCS global mask bit */
1657 
1658 typedef union _pcs_cfg_t {
1659 	uint64_t value;
1660 
1661 	struct {
1662 #if defined(_BIG_ENDIAN)
1663 		uint32_t msw;	/* Most significant word */
1664 		uint32_t lsw;	/* Least significant word */
1665 #elif defined(_LITTLE_ENDIAN)
1666 		uint32_t lsw;	/* Least significant word */
1667 		uint32_t msw;	/* Most significant word */
1668 #endif
1669 	} val;
1670 	struct {
1671 #if defined(_BIG_ENDIAN)
1672 		uint32_t	w1;
1673 #endif
1674 		struct {
1675 #if defined(_BIT_FIELDS_HTOL)
1676 		uint32_t res0			: 25;
1677 		uint32_t mask			: 1;
1678 		uint32_t override_10ms_timer	: 1;
1679 		uint32_t jitter_study		: 2;
1680 		uint32_t sig_det_a_low		: 1;
1681 		uint32_t sig_det_override	: 1;
1682 		uint32_t enable			: 1;
1683 #elif defined(_BIT_FIELDS_LTOH)
1684 		uint32_t enable			: 1;
1685 		uint32_t sig_det_override	: 1;
1686 		uint32_t sig_det_a_low		: 1;
1687 		uint32_t jitter_study		: 2;
1688 		uint32_t override_10ms_timer	: 1;
1689 		uint32_t mask			: 1;
1690 		uint32_t res0			: 25;
1691 #endif
1692 		} w0;
1693 
1694 #if defined(_LITTLE_ENDIAN)
1695 		uint32_t	w1;
1696 #endif
1697 	} bits;
1698 } pcs_cfg_t, *p_pcs_cfg_t;
1699 
1700 
1701 /* used for diagnostic purposes. bits 20-22 autoclear on read */
1702 #define	PCS_SM_TX_STATE_MASK		0x0000000F /* Tx idle state mask */
1703 #define	PCS_SM_TX_STATE_SHIFT		0
1704 #define	PCS_SM_RX_STATE_MASK		0x000000F0 /* Rx idle state mask */
1705 #define	PCS_SM_RX_STATE_SHIFT		4
1706 #define	PCS_SM_WORD_SYNC_STATE_MASK	0x00000700 /* loss of sync state mask */
1707 #define	PCS_SM_WORD_SYNC_STATE_SHIFT	8
1708 #define	PCS_SM_SEQ_DETECT_STATE_MASK	0x00001800 /* sequence detect */
1709 #define	PCS_SM_SEQ_DETECT_STATE_SHIFT	11
1710 #define	PCS_SM_LINK_STATE_MASK		0x0001E000 /* link state */
1711 #define	PCS_SM_LINK_STATE_SHIFT		13
1712 #define	PCS_SM_LOSS_LINK_C		0x00100000 /* loss of link */
1713 #define	PCS_SM_LOSS_LINK_SYNC		0x00200000 /* loss of sync */
1714 #define	PCS_SM_LOSS_SIGNAL_DETECT	0x00400000 /* signal detect fail */
1715 #define	PCS_SM_NO_LINK_BREAKLINK	0x01000000 /* receipt of breaklink */
1716 #define	PCS_SM_NO_LINK_SERDES		0x02000000 /* serdes initializing */
1717 #define	PCS_SM_NO_LINK_C		0x04000000 /* C codes not stable */
1718 #define	PCS_SM_NO_LINK_SYNC		0x08000000 /* word sync not achieved */
1719 #define	PCS_SM_NO_LINK_WAIT_C		0x10000000 /* waiting for C codes */
1720 #define	PCS_SM_NO_LINK_NO_IDLE		0x20000000 /* linkpartner send C code */
1721 
1722 typedef union _pcs_stat_mc_t {
1723 	uint64_t value;
1724 
1725 	struct {
1726 #if defined(_BIG_ENDIAN)
1727 		uint32_t msw;	/* Most significant word */
1728 		uint32_t lsw;	/* Least significant word */
1729 #elif defined(_LITTLE_ENDIAN)
1730 		uint32_t lsw;	/* Least significant word */
1731 		uint32_t msw;	/* Most significant word */
1732 #endif
1733 	} val;
1734 	struct {
1735 #if defined(_BIG_ENDIAN)
1736 		uint32_t	w1;
1737 #endif
1738 		struct {
1739 #if defined(_BIT_FIELDS_HTOL)
1740 		uint32_t res2		: 2;
1741 		uint32_t lnk_dwn_ni	: 1;
1742 		uint32_t lnk_dwn_wc	: 1;
1743 		uint32_t lnk_dwn_ls	: 1;
1744 		uint32_t lnk_dwn_nc	: 1;
1745 		uint32_t lnk_dwn_ser	: 1;
1746 		uint32_t lnk_loss_bc	: 1;
1747 		uint32_t res1		: 1;
1748 		uint32_t loss_sd	: 1;
1749 		uint32_t lnk_loss_sync	: 1;
1750 		uint32_t lnk_loss_c	: 1;
1751 		uint32_t res0		: 3;
1752 		uint32_t link_cfg_stat	: 4;
1753 		uint32_t seq_detc_stat	: 2;
1754 		uint32_t word_sync	: 3;
1755 		uint32_t rx_ctrl	: 4;
1756 		uint32_t tx_ctrl	: 4;
1757 #elif defined(_BIT_FIELDS_LTOH)
1758 		uint32_t tx_ctrl	: 4;
1759 		uint32_t rx_ctrl	: 4;
1760 		uint32_t word_sync	: 3;
1761 		uint32_t seq_detc_stat	: 2;
1762 		uint32_t link_cfg_stat	: 4;
1763 		uint32_t res0		: 3;
1764 		uint32_t lnk_loss_c	: 1;
1765 		uint32_t lnk_loss_sync	: 1;
1766 		uint32_t loss_sd	: 1;
1767 		uint32_t res1		: 1;
1768 		uint32_t lnk_loss_bc	: 1;
1769 		uint32_t lnk_dwn_ser	: 1;
1770 		uint32_t lnk_dwn_nc	: 1;
1771 		uint32_t lnk_dwn_ls	: 1;
1772 		uint32_t lnk_dwn_wc	: 1;
1773 		uint32_t lnk_dwn_ni	: 1;
1774 		uint32_t res2		: 2;
1775 #endif
1776 		} w0;
1777 
1778 #if defined(_LITTLE_ENDIAN)
1779 		uint32_t	w1;
1780 #endif
1781 	} bits;
1782 } pcs_stat_mc_t, *p_pcs_stat_mc_t;
1783 
1784 #define	PCS_INTR_STATUS_LINK_CHANGE	0x04	/* link status has changed */
1785 
1786 /*
1787  * control which network interface is used. no more than one bit should
1788  * be set.
1789  */
1790 #define	PCS_DATAPATH_MODE_PCS		0	   /* Internal PCS is used */
1791 #define	PCS_DATAPATH_MODE_MII		0x00000002 /* GMII/RGMII is selected. */
1792 
1793 #define	PCS_PACKET_COUNT_TX_MASK	0x000007FF /* pkts xmitted by PCS */
1794 #define	PCS_PACKET_COUNT_RX_MASK	0x07FF0000 /* pkts recvd by PCS */
1795 #define	PCS_PACKET_COUNT_RX_SHIFT	16
1796 
1797 /*
1798  * ******************** XPCS registers *********************************
1799  */
1800 
1801 /* XPCS Base 10G Control1 Register */
1802 #define	XPCS_CTRL1_RST			0x8000 /* Self clearing reset. */
1803 #define	XPCS_CTRL1_LOOPBK		0x4000 /* xpcs Loopback */
1804 #define	XPCS_CTRL1_SPEED_SEL_3		0x2000 /* 1 indicates 10G speed */
1805 #define	XPCS_CTRL1_LOW_PWR		0x0800 /* low power mode. */
1806 #define	XPCS_CTRL1_SPEED_SEL_1		0x0040 /* 1 indicates 10G speed */
1807 #define	XPCS_CTRL1_SPEED_SEL_0_MASK	0x003c /* 0 indicates 10G speed. */
1808 #define	XPCS_CTRL1_SPEED_SEL_0_SHIFT	2
1809 
1810 
1811 
1812 typedef union _xpcs_ctrl1_t {
1813 	uint64_t value;
1814 
1815 	struct {
1816 #if defined(_BIG_ENDIAN)
1817 		uint32_t msw;	/* Most significant word */
1818 		uint32_t lsw;	/* Least significant word */
1819 #elif defined(_LITTLE_ENDIAN)
1820 		uint32_t lsw;	/* Least significant word */
1821 		uint32_t msw;	/* Most significant word */
1822 #endif
1823 	} val;
1824 	struct {
1825 #if defined(_BIG_ENDIAN)
1826 		uint32_t	w1;
1827 #endif
1828 		struct {
1829 #if defined(_BIT_FIELDS_HTOL)
1830 		uint32_t res3		: 16;
1831 		uint32_t reset		: 1;
1832 		uint32_t csr_lb		: 1;
1833 		uint32_t csr_speed_sel3	: 1;
1834 		uint32_t res2		: 1;
1835 		uint32_t csr_low_pwr	: 1;
1836 		uint32_t res1		: 4;
1837 		uint32_t csr_speed_sel1	: 1;
1838 		uint32_t csr_speed_sel0	: 4;
1839 		uint32_t res0		: 2;
1840 #elif defined(_BIT_FIELDS_LTOH)
1841 		uint32_t res0		: 2;
1842 		uint32_t csr_speed_sel0	: 4;
1843 		uint32_t csr_speed_sel1	: 1;
1844 		uint32_t res1		: 4;
1845 		uint32_t csr_low_pwr	: 1;
1846 		uint32_t res2		: 1;
1847 		uint32_t csr_speed_sel3	: 1;
1848 		uint32_t csr_lb		: 1;
1849 		uint32_t reset		: 1;
1850 		uint32_t res3		: 16;
1851 #endif
1852 		} w0;
1853 
1854 #if defined(_LITTLE_ENDIAN)
1855 		uint32_t	w1;
1856 #endif
1857 	} bits;
1858 } xpcs_ctrl1_t;
1859 
1860 
1861 /* XPCS Base 10G Status1 Register (Read Only) */
1862 #define	XPCS_STATUS1_FAULT		0x0080
1863 #define	XPCS_STATUS1_RX_LINK_STATUS_UP	0x0004 /* Link status interrupt */
1864 #define	XPCS_STATUS1_LOW_POWER_ABILITY	0x0002 /* low power mode */
1865 
1866 
1867 typedef	union _xpcs_stat1_t {
1868 	uint64_t value;
1869 
1870 	struct {
1871 #if defined(_BIG_ENDIAN)
1872 		uint32_t msw;	/* Most significant word */
1873 		uint32_t lsw;	/* Least significant word */
1874 #elif defined(_LITTLE_ENDIAN)
1875 		uint32_t lsw;	/* Least significant word */
1876 		uint32_t msw;	/* Most significant word */
1877 #endif
1878 	} val;
1879 	struct {
1880 #if defined(_BIG_ENDIAN)
1881 		uint32_t	w1;
1882 #endif
1883 		struct {
1884 #if defined(_BIT_FIELDS_HTOL)
1885 		uint32_t res4			: 16;
1886 		uint32_t res3			: 8;
1887 		uint32_t csr_fault		: 1;
1888 		uint32_t res1			: 4;
1889 		uint32_t csr_rx_link_stat	: 1;
1890 		uint32_t csr_low_pwr_ability	: 1;
1891 		uint32_t res0			: 1;
1892 #elif defined(_BIT_FIELDS_LTOH)
1893 		uint32_t res0			: 1;
1894 		uint32_t csr_low_pwr_ability	: 1;
1895 		uint32_t csr_rx_link_stat	: 1;
1896 		uint32_t res1			: 4;
1897 		uint32_t csr_fault		: 1;
1898 		uint32_t res3			: 8;
1899 		uint32_t res4			: 16;
1900 #endif
1901 		} w0;
1902 
1903 #if defined(_LITTLE_ENDIAN)
1904 		uint32_t	w1;
1905 #endif
1906 	} bits;
1907 } xpcs_stat1_t;
1908 
1909 
1910 /* XPCS Base Speed Ability Register. Indicates 10G capability */
1911 #define	XPCS_SPEED_ABILITY_10_GIG	0x0001
1912 
1913 
1914 typedef	union _xpcs_speed_ab_t {
1915 	uint64_t value;
1916 
1917 	struct {
1918 #if defined(_BIG_ENDIAN)
1919 		uint32_t msw;	/* Most significant word */
1920 		uint32_t lsw;	/* Least significant word */
1921 #elif defined(_LITTLE_ENDIAN)
1922 		uint32_t lsw;	/* Least significant word */
1923 		uint32_t msw;	/* Most significant word */
1924 #endif
1925 	} val;
1926 	struct {
1927 #if defined(_BIG_ENDIAN)
1928 		uint32_t	w1;
1929 #endif
1930 		struct {
1931 #if defined(_BIT_FIELDS_HTOL)
1932 		uint32_t res1		: 16;
1933 		uint32_t res0		: 15;
1934 		uint32_t csr_10gig	: 1;
1935 #elif defined(_BIT_FIELDS_LTOH)
1936 		uint32_t csr_10gig	: 1;
1937 		uint32_t res0		: 15;
1938 		uint32_t res1		: 16;
1939 #endif
1940 		} w0;
1941 
1942 #if defined(_LITTLE_ENDIAN)
1943 		uint32_t	w1;
1944 #endif
1945 	} bits;
1946 } xpcs_speed_ab_t;
1947 
1948 
1949 /* XPCS Base 10G Devices in Package Register */
1950 #define	XPCS_DEV_IN_PKG_CSR_VENDOR2	0x80000000
1951 #define	XPCS_DEV_IN_PKG_CSR_VENDOR1	0x40000000
1952 #define	XPCS_DEV_IN_PKG_DTE_XS		0x00000020
1953 #define	XPCS_DEV_IN_PKG_PHY_XS		0x00000010
1954 #define	XPCS_DEV_IN_PKG_PCS		0x00000008
1955 #define	XPCS_DEV_IN_PKG_WIS		0x00000004
1956 #define	XPCS_DEV_IN_PKG_PMD_PMA		0x00000002
1957 #define	XPCS_DEV_IN_PKG_CLS_22_REG	0x00000000
1958 
1959 
1960 
1961 typedef	union _xpcs_dev_in_pkg_t {
1962 	uint64_t value;
1963 
1964 	struct {
1965 #if defined(_BIG_ENDIAN)
1966 		uint32_t msw;	/* Most significant word */
1967 		uint32_t lsw;	/* Least significant word */
1968 #elif defined(_LITTLE_ENDIAN)
1969 		uint32_t lsw;	/* Least significant word */
1970 		uint32_t msw;	/* Most significant word */
1971 #endif
1972 	} val;
1973 	struct {
1974 #if defined(_BIG_ENDIAN)
1975 		uint32_t	w1;
1976 #endif
1977 		struct {
1978 #if defined(_BIT_FIELDS_HTOL)
1979 		uint32_t csr_vendor2	: 1;
1980 		uint32_t csr_vendor1	: 1;
1981 		uint32_t res1		: 14;
1982 		uint32_t res0		: 10;
1983 		uint32_t dte_xs		: 1;
1984 		uint32_t phy_xs		: 1;
1985 		uint32_t pcs		: 1;
1986 		uint32_t wis		: 1;
1987 		uint32_t pmd_pma	: 1;
1988 		uint32_t clause_22_reg	: 1;
1989 #elif defined(_BIT_FIELDS_LTOH)
1990 		uint32_t clause_22_reg	: 1;
1991 		uint32_t pmd_pma	: 1;
1992 		uint32_t wis		: 1;
1993 		uint32_t pcs		: 1;
1994 		uint32_t phy_xs		: 1;
1995 		uint32_t dte_xs		: 1;
1996 		uint32_t res0		: 10;
1997 		uint32_t res1		: 14;
1998 		uint32_t csr_vendor1	: 1;
1999 		uint32_t csr_vendor2	: 1;
2000 #endif
2001 		} w0;
2002 
2003 #if defined(_LITTLE_ENDIAN)
2004 		uint32_t	w1;
2005 #endif
2006 	} bits;
2007 } xpcs_dev_in_pkg_t;
2008 
2009 
2010 /* XPCS Base 10G Control2 Register */
2011 #define	XPCS_PSC_SEL_MASK		0x0003
2012 #define	PSC_SEL_10G_BASE_X_PCS		0x0001
2013 
2014 
2015 typedef	union _xpcs_ctrl2_t {
2016 	uint64_t value;
2017 
2018 	struct {
2019 #if defined(_BIG_ENDIAN)
2020 		uint32_t msw;	/* Most significant word */
2021 		uint32_t lsw;	/* Least significant word */
2022 #elif defined(_LITTLE_ENDIAN)
2023 		uint32_t lsw;	/* Least significant word */
2024 		uint32_t msw;	/* Most significant word */
2025 #endif
2026 	} val;
2027 	struct {
2028 #if defined(_BIG_ENDIAN)
2029 		uint32_t	w1;
2030 #endif
2031 		struct {
2032 #if defined(_BIT_FIELDS_HTOL)
2033 		uint32_t res1		: 16;
2034 		uint32_t res0		: 14;
2035 		uint32_t csr_psc_sel	: 2;
2036 #elif defined(_BIT_FIELDS_LTOH)
2037 		uint32_t csr_psc_sel	: 2;
2038 		uint32_t res0		: 14;
2039 		uint32_t res1		: 16;
2040 #endif
2041 		} w0;
2042 
2043 #if defined(_LITTLE_ENDIAN)
2044 		uint32_t	w1;
2045 #endif
2046 	} bits;
2047 } xpcs_ctrl2_t;
2048 
2049 
2050 /* XPCS Base10G Status2 Register */
2051 #define	XPCS_STATUS2_DEV_PRESENT_MASK	0xc000	/* ?????? */
2052 #define	XPCS_STATUS2_TX_FAULT		0x0800	/* Fault on tx path */
2053 #define	XPCS_STATUS2_RX_FAULT		0x0400	/* Fault on rx path */
2054 #define	XPCS_STATUS2_TEN_GBASE_W	0x0004	/* 10G-Base-W */
2055 #define	XPCS_STATUS2_TEN_GBASE_X	0x0002	/* 10G-Base-X */
2056 #define	XPCS_STATUS2_TEN_GBASE_R	0x0001	/* 10G-Base-R */
2057 
2058 typedef	union _xpcs_stat2_t {
2059 	uint64_t value;
2060 
2061 	struct {
2062 #if defined(_BIG_ENDIAN)
2063 		uint32_t msw;	/* Most significant word */
2064 		uint32_t lsw;	/* Least significant word */
2065 #elif defined(_LITTLE_ENDIAN)
2066 		uint32_t lsw;	/* Least significant word */
2067 		uint32_t msw;	/* Most significant word */
2068 #endif
2069 	} val;
2070 	struct {
2071 #if defined(_BIG_ENDIAN)
2072 		uint32_t	w1;
2073 #endif
2074 		struct {
2075 #if defined(_BIT_FIELDS_HTOL)
2076 		uint32_t res2		: 16;
2077 		uint32_t csr_dev_pres	: 2;
2078 		uint32_t res1		: 2;
2079 		uint32_t csr_tx_fault	: 1;
2080 		uint32_t csr_rx_fault	: 1;
2081 		uint32_t res0		: 7;
2082 		uint32_t ten_gbase_w	: 1;
2083 		uint32_t ten_gbase_x	: 1;
2084 		uint32_t ten_gbase_r	: 1;
2085 #elif defined(_BIT_FIELDS_LTOH)
2086 		uint32_t ten_gbase_r	: 1;
2087 		uint32_t ten_gbase_x	: 1;
2088 		uint32_t ten_gbase_w	: 1;
2089 		uint32_t res0		: 7;
2090 		uint32_t csr_rx_fault	: 1;
2091 		uint32_t csr_tx_fault	: 1;
2092 		uint32_t res1		: 2;
2093 		uint32_t csr_dev_pres	: 2;
2094 		uint32_t res2		: 16;
2095 #endif
2096 		} w0;
2097 
2098 #if defined(_LITTLE_ENDIAN)
2099 		uint32_t	w1;
2100 #endif
2101 	} bits;
2102 } xpcs_stat2_t;
2103 
2104 
2105 
2106 /* XPCS Base10G Status Register */
2107 #define	XPCS_STATUS_LANE_ALIGN		0x1000 /* 10GBaseX PCS rx lanes align */
2108 #define	XPCS_STATUS_PATTERN_TEST_ABLE	0x0800 /* able to generate patterns. */
2109 #define	XPCS_STATUS_LANE3_SYNC		0x0008 /* Lane 3 is synchronized */
2110 #define	XPCS_STATUS_LANE2_SYNC		0x0004 /* Lane 2 is synchronized */
2111 #define	XPCS_STATUS_LANE1_SYNC		0x0002 /* Lane 1 is synchronized */
2112 #define	XPCS_STATUS_LANE0_SYNC		0x0001 /* Lane 0 is synchronized */
2113 
2114 typedef	union _xpcs_stat_t {
2115 	uint64_t value;
2116 
2117 	struct {
2118 #if defined(_BIG_ENDIAN)
2119 		uint32_t msw;	/* Most significant word */
2120 		uint32_t lsw;	/* Least significant word */
2121 #elif defined(_LITTLE_ENDIAN)
2122 		uint32_t lsw;	/* Least significant word */
2123 		uint32_t msw;	/* Most significant word */
2124 #endif
2125 	} val;
2126 	struct {
2127 #if defined(_BIG_ENDIAN)
2128 		uint32_t	w1;
2129 #endif
2130 		struct {
2131 #if defined(_BIT_FIELDS_HTOL)
2132 		uint32_t res2			: 16;
2133 		uint32_t res1			: 3;
2134 		uint32_t csr_lane_align		: 1;
2135 		uint32_t csr_pattern_test_able	: 1;
2136 		uint32_t res0			: 7;
2137 		uint32_t csr_lane3_sync		: 1;
2138 		uint32_t csr_lane2_sync		: 1;
2139 		uint32_t csr_lane1_sync		: 1;
2140 		uint32_t csr_lane0_sync		: 1;
2141 #elif defined(_BIT_FIELDS_LTOH)
2142 		uint32_t csr_lane0_sync		: 1;
2143 		uint32_t csr_lane1_sync		: 1;
2144 		uint32_t csr_lane2_sync		: 1;
2145 		uint32_t csr_lane3_sync		: 1;
2146 		uint32_t res0			: 7;
2147 		uint32_t csr_pat_test_able	: 1;
2148 		uint32_t csr_lane_align		: 1;
2149 		uint32_t res1			: 3;
2150 		uint32_t res2			: 16;
2151 #endif
2152 		} w0;
2153 
2154 #if defined(_LITTLE_ENDIAN)
2155 		uint32_t	w1;
2156 #endif
2157 	} bits;
2158 } xpcs_stat_t;
2159 
2160 /* XPCS Base10G Test Control Register */
2161 #define	XPCS_TEST_CTRL_TX_TEST_ENABLE		0x0004
2162 #define	XPCS_TEST_CTRL_TEST_PATTERN_SEL_MASK	0x0003
2163 #define	TEST_PATTERN_HIGH_FREQ			0
2164 #define	TEST_PATTERN_LOW_FREQ			1
2165 #define	TEST_PATTERN_MIXED_FREQ			2
2166 
2167 typedef	union _xpcs_test_ctl_t {
2168 	uint64_t value;
2169 
2170 	struct {
2171 #if defined(_BIG_ENDIAN)
2172 		uint32_t msw;	/* Most significant word */
2173 		uint32_t lsw;	/* Least significant word */
2174 #elif defined(_LITTLE_ENDIAN)
2175 		uint32_t lsw;	/* Least significant word */
2176 		uint32_t msw;	/* Most significant word */
2177 #endif
2178 	} val;
2179 	struct {
2180 #if defined(_BIG_ENDIAN)
2181 		uint32_t	w1;
2182 #endif
2183 		struct {
2184 #if defined(_BIT_FIELDS_HTOL)
2185 		uint32_t res1			: 16;
2186 		uint32_t res0			: 13;
2187 		uint32_t csr_tx_test_en		: 1;
2188 		uint32_t csr_test_pat_sel	: 2;
2189 #elif defined(_BIT_FIELDS_LTOH)
2190 		uint32_t csr_test_pat_sel	: 2;
2191 		uint32_t csr_tx_test_en		: 1;
2192 		uint32_t res0			: 13;
2193 		uint32_t res1			: 16;
2194 #endif
2195 		} w0;
2196 
2197 #if defined(_LITTLE_ENDIAN)
2198 		uint32_t	w1;
2199 #endif
2200 	} bits;
2201 } xpcs_test_ctl_t;
2202 
2203 /* XPCS Base10G Diagnostic Register */
2204 #define	XPCS_DIAG_EB_ALIGN_ERR3		0x40
2205 #define	XPCS_DIAG_EB_ALIGN_ERR2		0x20
2206 #define	XPCS_DIAG_EB_ALIGN_ERR1		0x10
2207 #define	XPCS_DIAG_EB_DESKEW_OK		0x08
2208 #define	XPCS_DIAG_EB_ALIGN_DET3		0x04
2209 #define	XPCS_DIAG_EB_ALIGN_DET2		0x02
2210 #define	XPCS_DIAG_EB_ALIGN_DET1		0x01
2211 #define	XPCS_DIAG_EB_DESKEW_LOSS	0
2212 
2213 #define	XPCS_DIAG_SYNC_3_INVALID	0x8
2214 #define	XPCS_DIAG_SYNC_2_INVALID	0x4
2215 #define	XPCS_DIAG_SYNC_1_INVALID	0x2
2216 #define	XPCS_DIAG_SYNC_IN_SYNC		0x1
2217 #define	XPCS_DIAG_SYNC_LOSS_SYNC	0
2218 
2219 #define	XPCS_RX_SM_RECEIVE_STATE	1
2220 #define	XPCS_RX_SM_FAULT_STATE		0
2221 
2222 typedef	union _xpcs_diag_t {
2223 	uint64_t value;
2224 
2225 	struct {
2226 #if defined(_BIG_ENDIAN)
2227 		uint32_t msw;	/* Most significant word */
2228 		uint32_t lsw;	/* Least significant word */
2229 #elif defined(_LITTLE_ENDIAN)
2230 		uint32_t lsw;	/* Least significant word */
2231 		uint32_t msw;	/* Most significant word */
2232 #endif
2233 	} val;
2234 	struct {
2235 #if defined(_BIG_ENDIAN)
2236 		uint32_t	w1;
2237 #endif
2238 		struct {
2239 #if defined(_BIT_FIELDS_HTOL)
2240 		uint32_t res1			: 7;
2241 		uint32_t sync_sm_lane3		: 4;
2242 		uint32_t sync_sm_lane2		: 4;
2243 		uint32_t sync_sm_lane1		: 4;
2244 		uint32_t sync_sm_lane0		: 4;
2245 		uint32_t elastic_buffer_sm	: 8;
2246 		uint32_t receive_sm		: 1;
2247 #elif defined(_BIT_FIELDS_LTOH)
2248 		uint32_t receive_sm		: 1;
2249 		uint32_t elastic_buffer_sm	: 8;
2250 		uint32_t sync_sm_lane0		: 4;
2251 		uint32_t sync_sm_lane1		: 4;
2252 		uint32_t sync_sm_lane2		: 4;
2253 		uint32_t sync_sm_lane3		: 4;
2254 		uint32_t res1			: 7;
2255 #endif
2256 		} w0;
2257 
2258 #if defined(_LITTLE_ENDIAN)
2259 		uint32_t	w1;
2260 #endif
2261 	} bits;
2262 } xpcs_diag_t;
2263 
2264 /* XPCS Base10G Tx State Machine Register */
2265 #define	XPCS_TX_SM_SEND_UNDERRUN	0x9
2266 #define	XPCS_TX_SM_SEND_RANDOM_Q	0x8
2267 #define	XPCS_TX_SM_SEND_RANDOM_K	0x7
2268 #define	XPCS_TX_SM_SEND_RANDOM_A	0x6
2269 #define	XPCS_TX_SM_SEND_RANDOM_R	0x5
2270 #define	XPCS_TX_SM_SEND_Q		0x4
2271 #define	XPCS_TX_SM_SEND_K		0x3
2272 #define	XPCS_TX_SM_SEND_A		0x2
2273 #define	XPCS_TX_SM_SEND_SDP		0x1
2274 #define	XPCS_TX_SM_SEND_DATA		0
2275 
2276 /* XPCS Base10G Configuration Register */
2277 #define	XPCS_CFG_VENDOR_DBG_SEL_MASK	0x78
2278 #define	XPCS_CFG_VENDOR_DBG_SEL_SHIFT	3
2279 #define	XPCS_CFG_BYPASS_SIG_DETECT	0x0004
2280 #define	XPCS_CFG_ENABLE_TX_BUFFERS	0x0002
2281 #define	XPCS_CFG_XPCS_ENABLE		0x0001
2282 
2283 typedef	union _xpcs_config_t {
2284 	uint64_t value;
2285 
2286 	struct {
2287 #if defined(_BIG_ENDIAN)
2288 		uint32_t msw;	/* Most significant word */
2289 		uint32_t lsw;	/* Least significant word */
2290 #elif defined(_LITTLE_ENDIAN)
2291 		uint32_t lsw;	/* Least significant word */
2292 		uint32_t msw;	/* Most significant word */
2293 #endif
2294 	} val;
2295 	struct {
2296 #if defined(_BIG_ENDIAN)
2297 		uint32_t	w1;
2298 #endif
2299 		struct {
2300 #if defined(_BIT_FIELDS_HTOL)
2301 		uint32_t res1			: 16;
2302 		uint32_t res0			: 9;
2303 		uint32_t csr_vendor_dbg_sel	: 4;
2304 		uint32_t csr_bypass_sig_detect	: 1;
2305 		uint32_t csr_en_tx_buf		: 1;
2306 		uint32_t csr_xpcs_en		: 1;
2307 #elif defined(_BIT_FIELDS_LTOH)
2308 		uint32_t csr_xpcs_en		: 1;
2309 		uint32_t csr_en_tx_buf		: 1;
2310 		uint32_t csr_bypass_sig_detect	: 1;
2311 		uint32_t csr_vendor_dbg_sel	: 4;
2312 		uint32_t res0			: 9;
2313 		uint32_t res1			: 16;
2314 #endif
2315 		} w0;
2316 
2317 #if defined(_LITTLE_ENDIAN)
2318 		uint32_t	w1;
2319 #endif
2320 	} bits;
2321 } xpcs_config_t;
2322 
2323 
2324 
2325 /* XPCS Base10G Mask1 Register */
2326 #define	XPCS_MASK1_FAULT_MASK		0x0080	/* mask fault interrupt. */
2327 #define	XPCS_MASK1_RX_LINK_STATUS_MASK	0x0040	/* mask linkstat interrupt */
2328 
2329 /* XPCS Base10G Packet Counter */
2330 #define	XPCS_PKT_CNTR_TX_PKT_CNT_MASK	0xffff0000
2331 #define	XPCS_PKT_CNTR_TX_PKT_CNT_SHIFT	16
2332 #define	XPCS_PKT_CNTR_RX_PKT_CNT_MASK	0x0000ffff
2333 #define	XPCS_PKT_CNTR_RX_PKT_CNT_SHIFT	0
2334 
2335 /* XPCS Base10G TX State Machine status register */
2336 #define	XPCS_TX_STATE_MC_TX_STATE_MASK	0x0f
2337 #define	XPCS_DESKEW_ERR_CNTR_MASK	0xff
2338 
2339 /* XPCS Base10G Lane symbol error counters */
2340 #define	XPCS_SYM_ERR_CNT_L1_MASK  0xffff0000
2341 #define	XPCS_SYM_ERR_CNT_L0_MASK  0x0000ffff
2342 #define	XPCS_SYM_ERR_CNT_L3_MASK  0xffff0000
2343 #define	XPCS_SYM_ERR_CNT_L2_MASK  0x0000ffff
2344 
2345 #define	XPCS_SYM_ERR_CNT_MULTIPLIER	16
2346 
2347 /* ESR Reset Register */
2348 #define	ESR_RESET_1			2
2349 #define	ESR_RESET_0			1
2350 
2351 /* ESR Configuration Register */
2352 #define	ESR_BLUNT_END_LOOPBACK		2
2353 #define	ESR_FORCE_SERDES_SERDES_RDY	1
2354 
2355 /* ESR Neptune Serdes PLL Configuration */
2356 #define	ESR_PLL_CFG_FBDIV_0		0x1
2357 #define	ESR_PLL_CFG_FBDIV_1		0x2
2358 #define	ESR_PLL_CFG_FBDIV_2		0x4
2359 #define	ESR_PLL_CFG_HALF_RATE_0		0x8
2360 #define	ESR_PLL_CFG_HALF_RATE_1		0x10
2361 #define	ESR_PLL_CFG_HALF_RATE_2		0x20
2362 #define	ESR_PLL_CFG_HALF_RATE_3		0x40
2363 #define	ESR_PLL_CFG_1G_SERDES		(ESR_PLL_CFG_FBDIV_0 | \
2364 					ESR_PLL_CFG_HALF_RATE_0 | \
2365 					ESR_PLL_CFG_HALF_RATE_1 | \
2366 					ESR_PLL_CFG_HALF_RATE_2 | \
2367 					ESR_PLL_CFG_HALF_RATE_3)
2368 
2369 /* ESR Neptune Serdes Control Register */
2370 #define	ESR_CTL_EN_SYNCDET_0		0x00000001
2371 #define	ESR_CTL_EN_SYNCDET_1		0x00000002
2372 #define	ESR_CTL_EN_SYNCDET_2		0x00000004
2373 #define	ESR_CTL_EN_SYNCDET_3		0x00000008
2374 #define	ESR_CTL_OUT_EMPH_0_MASK		0x00000070
2375 #define	ESR_CTL_OUT_EMPH_0_SHIFT	4
2376 #define	ESR_CTL_OUT_EMPH_1_MASK		0x00000380
2377 #define	ESR_CTL_OUT_EMPH_1_SHIFT	7
2378 #define	ESR_CTL_OUT_EMPH_2_MASK		0x00001c00
2379 #define	ESR_CTL_OUT_EMPH_2_SHIFT	10
2380 #define	ESR_CTL_OUT_EMPH_3_MASK		0x0000e000
2381 #define	ESR_CTL_OUT_EMPH_3_SHIFT	13
2382 #define	ESR_CTL_LOSADJ_0_MASK		0x00070000
2383 #define	ESR_CTL_LOSADJ_0_SHIFT		16
2384 #define	ESR_CTL_LOSADJ_1_MASK		0x00380000
2385 #define	ESR_CTL_LOSADJ_1_SHIFT		19
2386 #define	ESR_CTL_LOSADJ_2_MASK		0x01c00000
2387 #define	ESR_CTL_LOSADJ_2_SHIFT		22
2388 #define	ESR_CTL_LOSADJ_3_MASK		0x0e000000
2389 #define	ESR_CTL_LOSADJ_3_SHIFT		25
2390 #define	ESR_CTL_RXITERM_0		0x10000000
2391 #define	ESR_CTL_RXITERM_1		0x20000000
2392 #define	ESR_CTL_RXITERM_2		0x40000000
2393 #define	ESR_CTL_RXITERM_3		0x80000000
2394 #define	ESR_CTL_1G_SERDES		(ESR_CTL_EN_SYNCDET_0 | \
2395 					ESR_CTL_EN_SYNCDET_1 |	\
2396 					ESR_CTL_EN_SYNCDET_2 |	\
2397 					ESR_CTL_EN_SYNCDET_3 |  \
2398 					(0x1 << ESR_CTL_OUT_EMPH_0_SHIFT) | \
2399 					(0x1 << ESR_CTL_OUT_EMPH_1_SHIFT) | \
2400 					(0x1 << ESR_CTL_OUT_EMPH_2_SHIFT) | \
2401 					(0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \
2402 					(0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \
2403 					(0x1 << ESR_CTL_LOSADJ_0_SHIFT) | \
2404 					(0x1 << ESR_CTL_LOSADJ_1_SHIFT) | \
2405 					(0x1 << ESR_CTL_LOSADJ_2_SHIFT) | \
2406 					(0x1 << ESR_CTL_LOSADJ_3_SHIFT))
2407 
2408 /* ESR Neptune Serdes Test Configuration Register */
2409 #define	ESR_TSTCFG_LBTEST_MD_0_MASK	0x00000003
2410 #define	ESR_TSTCFG_LBTEST_MD_0_SHIFT	0
2411 #define	ESR_TSTCFG_LBTEST_MD_1_MASK	0x0000000c
2412 #define	ESR_TSTCFG_LBTEST_MD_1_SHIFT	2
2413 #define	ESR_TSTCFG_LBTEST_MD_2_MASK	0x00000030
2414 #define	ESR_TSTCFG_LBTEST_MD_2_SHIFT	4
2415 #define	ESR_TSTCFG_LBTEST_MD_3_MASK	0x000000c0
2416 #define	ESR_TSTCFG_LBTEST_MD_3_SHIFT	6
2417 #define	ESR_TSTCFG_LBTEST_PAD		(ESR_PAD_LOOPBACK_CH3 | \
2418 					ESR_PAD_LOOPBACK_CH2 | \
2419 					ESR_PAD_LOOPBACK_CH1 | \
2420 					ESR_PAD_LOOPBACK_CH0)
2421 
2422 /* ESR Neptune Ethernet RGMII Configuration Register */
2423 #define	ESR_RGMII_PT0_IN_USE		0x00000001
2424 #define	ESR_RGMII_PT1_IN_USE		0x00000002
2425 #define	ESR_RGMII_PT2_IN_USE		0x00000004
2426 #define	ESR_RGMII_PT3_IN_USE		0x00000008
2427 #define	ESR_RGMII_REG_RW_TEST		0x00000010
2428 
2429 /* ESR Internal Signals Observation Register */
2430 #define	ESR_SIG_MASK			0xFFFFFFFF
2431 #define	ESR_SIG_P0_BITS_MASK		0x33E0000F
2432 #define	ESR_SIG_P1_BITS_MASK		0x0C1F00F0
2433 #define	ESR_SIG_SERDES_RDY0_P0		0x20000000
2434 #define	ESR_SIG_DETECT0_P0		0x10000000
2435 #define	ESR_SIG_SERDES_RDY0_P1		0x08000000
2436 #define	ESR_SIG_DETECT0_P1		0x04000000
2437 #define	ESR_SIG_XSERDES_RDY_P0		0x02000000
2438 #define	ESR_SIG_XDETECT_P0_CH3		0x01000000
2439 #define	ESR_SIG_XDETECT_P0_CH2		0x00800000
2440 #define	ESR_SIG_XDETECT_P0_CH1		0x00400000
2441 #define	ESR_SIG_XDETECT_P0_CH0		0x00200000
2442 #define	ESR_SIG_XSERDES_RDY_P1		0x00100000
2443 #define	ESR_SIG_XDETECT_P1_CH3		0x00080000
2444 #define	ESR_SIG_XDETECT_P1_CH2		0x00040000
2445 #define	ESR_SIG_XDETECT_P1_CH1		0x00020000
2446 #define	ESR_SIG_XDETECT_P1_CH0		0x00010000
2447 #define	ESR_SIG_LOS_P1_CH3		0x00000080
2448 #define	ESR_SIG_LOS_P1_CH2		0x00000040
2449 #define	ESR_SIG_LOS_P1_CH1		0x00000020
2450 #define	ESR_SIG_LOS_P1_CH0		0x00000010
2451 #define	ESR_SIG_LOS_P0_CH3		0x00000008
2452 #define	ESR_SIG_LOS_P0_CH2		0x00000004
2453 #define	ESR_SIG_LOS_P0_CH1		0x00000002
2454 #define	ESR_SIG_LOS_P0_CH0		0x00000001
2455 #define	ESR_SIG_P0_BITS_MASK_1G		(ESR_SIG_SERDES_RDY0_P0 | \
2456 					ESR_SIG_DETECT0_P0)
2457 #define	ESR_SIG_P1_BITS_MASK_1G		(ESR_SIG_SERDES_RDY0_P1 | \
2458 					ESR_SIG_DETECT0_P1)
2459 
2460 /* ESR Debug Selection Register */
2461 #define	ESR_DEBUG_SEL_MASK		0x00000003f
2462 
2463 /* ESR Test Configuration Register */
2464 #define	ESR_NO_LOOPBACK_CH3		(0x0 << 6)
2465 #define	ESR_EWRAP_CH3			(0x1 << 6)
2466 #define	ESR_PAD_LOOPBACK_CH3		(0x2 << 6)
2467 #define	ESR_REVLOOPBACK_CH3		(0x3 << 6)
2468 #define	ESR_NO_LOOPBACK_CH2		(0x0 << 4)
2469 #define	ESR_EWRAP_CH2			(0x1 << 4)
2470 #define	ESR_PAD_LOOPBACK_CH2		(0x2 << 4)
2471 #define	ESR_REVLOOPBACK_CH2		(0x3 << 4)
2472 #define	ESR_NO_LOOPBACK_CH1		(0x0 << 2)
2473 #define	ESR_EWRAP_CH1			(0x1 << 2)
2474 #define	ESR_PAD_LOOPBACK_CH1		(0x2 << 2)
2475 #define	ESR_REVLOOPBACK_CH1		(0x3 << 2)
2476 #define	ESR_NO_LOOPBACK_CH0		0x0
2477 #define	ESR_EWRAP_CH0			0x1
2478 #define	ESR_PAD_LOOPBACK_CH0		0x2
2479 #define	ESR_REVLOOPBACK_CH0		0x3
2480 
2481 /* convert values */
2482 #define	NXGE_BASE(x, y)	\
2483 	(((y) << (x ## _SHIFT)) & (x ## _MASK))
2484 
2485 #define	NXGE_VAL_GET(fieldname, regval)		\
2486 	(((regval) & ((fieldname) ## _MASK)) >> ((fieldname) ## _SHIFT))
2487 
2488 #define	NXGE_VAL_SET(fieldname, regval, val)		\
2489 {							\
2490 	(regval) &= ~((fieldname) ## _MASK);		\
2491 	(regval) |= ((val) << (fieldname ## _SHIFT)); 	\
2492 }
2493 
2494 
2495 #ifdef	__cplusplus
2496 }
2497 #endif
2498 
2499 #endif	/* _SYS_MAC_NXGE_MAC_HW_H */
2500