1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MAC_NXGE_MAC_HW_H 27 #define _SYS_MAC_NXGE_MAC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 37 /* -------------------------- From May's template --------------------------- */ 38 39 #define NXGE_1GETHERMIN 255 40 #define NXGE_ETHERMIN 97 41 #define NXGE_MAX_HEADER 250 42 43 /* Hardware reset */ 44 typedef enum { 45 NXGE_TX_DISABLE, /* Disable Tx side */ 46 NXGE_RX_DISABLE, /* Disable Rx side */ 47 NXGE_CHIP_RESET /* Full chip reset */ 48 } nxge_reset_t; 49 50 #define NXGE_DELAY_AFTER_TXRX 10000 /* 10ms after idling rx/tx */ 51 #define NXGE_DELAY_AFTER_RESET 1000 /* 1ms after the reset */ 52 #define NXGE_DELAY_AFTER_EE_RESET 10000 /* 10ms after EEPROM reset */ 53 #define NXGE_DELAY_AFTER_LINK_RESET 13 /* 13 Us after link reset */ 54 #define NXGE_LINK_RESETS 8 /* Max PHY resets to wait for */ 55 /* linkup */ 56 57 #define FILTER_M_CTL 0xDCEF1 58 #define HASH_BITS 8 59 #define NMCFILTER_BITS (1 << HASH_BITS) 60 #define HASH_REG_WIDTH 16 61 #define BROADCAST_HASH_WORD 0x0f 62 #define BROADCAST_HASH_BIT 0x8000 63 #define NMCFILTER_REGS NMCFILTER_BITS / HASH_REG_WIDTH 64 /* Number of multicast filter regs */ 65 66 /* -------------------------------------------------------------------------- */ 67 68 #define XMAC_PORT_0 0 69 #define XMAC_PORT_1 1 70 #define BMAC_PORT_0 2 71 #define BMAC_PORT_1 3 72 73 #define MAC_RESET_WAIT 10 /* usecs */ 74 75 #define MAC_ADDR_REG_MASK 0xFFFF 76 77 /* Network Modes */ 78 79 typedef enum nxge_network_mode { 80 NET_2_10GE_FIBER = 1, 81 NET_2_10GE_COPPER, 82 NET_1_10GE_FIBER_3_1GE_COPPER, 83 NET_1_10GE_COPPER_3_1GE_COPPER, 84 NET_1_10GE_FIBER_3_1GE_FIBER, 85 NET_1_10GE_COPPER_3_1GE_FIBER, 86 NET_2_1GE_FIBER_2_1GE_COPPER, 87 NET_QGE_FIBER, 88 NET_QGE_COPPER 89 } nxge_network_mode_t; 90 91 typedef enum nxge_port { 92 PORT_TYPE_XMAC = 1, 93 PORT_TYPE_BMAC 94 } nxge_port_t; 95 96 typedef enum nxge_port_mode { 97 PORT_1G_COPPER = 1, 98 PORT_1G_FIBER, 99 PORT_10G_COPPER, 100 PORT_10G_FIBER 101 } nxge_port_mode_t; 102 103 typedef enum nxge_linkchk_mode { 104 LINKCHK_INTR = 1, 105 LINKCHK_TIMER 106 } nxge_linkchk_mode_t; 107 108 typedef enum { 109 LINK_INTR_STOP, 110 LINK_INTR_START 111 } link_intr_enable_t, *link_intr_enable_pt; 112 113 typedef enum { 114 LINK_MONITOR_STOP, 115 LINK_MONITOR_START, 116 LINK_MONITOR_STOPPING 117 } link_mon_enable_t, *link_mon_enable_pt; 118 119 typedef enum { 120 NO_XCVR, 121 INT_MII_XCVR, 122 EXT_MII_XCVR, 123 PCS_XCVR, 124 XPCS_XCVR 125 } xcvr_inuse_t; 126 127 /* macros for port offset calculations */ 128 129 #define PORT_1_OFFSET 0x6000 130 #define PORT_GT_1_OFFSET 0x4000 131 132 /* XMAC address macros */ 133 134 #define XMAC_ADDR_OFFSET_0 0 135 #define XMAC_ADDR_OFFSET_1 0x6000 136 137 #define XMAC_ADDR_OFFSET(port_num)\ 138 (XMAC_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET)) 139 140 #define XMAC_REG_ADDR(port_num, reg)\ 141 (FZC_MAC + (XMAC_ADDR_OFFSET(port_num)) + (reg)) 142 143 #define XMAC_PORT_ADDR(port_num)\ 144 (FZC_MAC + XMAC_ADDR_OFFSET(port_num)) 145 146 /* BMAC address macros */ 147 148 #define BMAC_ADDR_OFFSET_2 0x0C000 149 #define BMAC_ADDR_OFFSET_3 0x10000 150 151 #define BMAC_ADDR_OFFSET(port_num)\ 152 (BMAC_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET)) 153 154 #define BMAC_REG_ADDR(port_num, reg)\ 155 (FZC_MAC + (BMAC_ADDR_OFFSET(port_num)) + (reg)) 156 157 #define BMAC_PORT_ADDR(port_num)\ 158 (FZC_MAC + BMAC_ADDR_OFFSET(port_num)) 159 160 /* PCS address macros */ 161 162 #define PCS_ADDR_OFFSET_0 0x04000 163 #define PCS_ADDR_OFFSET_1 0x0A000 164 #define PCS_ADDR_OFFSET_2 0x0E000 165 #define PCS_ADDR_OFFSET_3 0x12000 166 167 #define PCS_ADDR_OFFSET(port_num)\ 168 ((port_num <= 1) ? \ 169 (PCS_ADDR_OFFSET_0 + (port_num) * PORT_1_OFFSET) : \ 170 (PCS_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET))) 171 172 #define PCS_REG_ADDR(port_num, reg)\ 173 (FZC_MAC + (PCS_ADDR_OFFSET((port_num)) + (reg))) 174 175 #define PCS_PORT_ADDR(port_num)\ 176 (FZC_MAC + (PCS_ADDR_OFFSET(port_num))) 177 178 /* XPCS address macros */ 179 180 #define XPCS_ADDR_OFFSET_0 0x02000 181 #define XPCS_ADDR_OFFSET_1 0x08000 182 #define XPCS_ADDR_OFFSET(port_num)\ 183 (XPCS_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET)) 184 185 #define XPCS_ADDR(port_num, reg)\ 186 (FZC_MAC + (XPCS_ADDR_OFFSET((port_num)) + (reg))) 187 188 #define XPCS_PORT_ADDR(port_num)\ 189 (FZC_MAC + (XPCS_ADDR_OFFSET(port_num))) 190 191 /* ESR address macro */ 192 #define ESR_ADDR_OFFSET 0x14000 193 #define ESR_ADDR(reg)\ 194 (FZC_MAC + (ESR_ADDR_OFFSET) + (reg)) 195 196 /* MIF address macros */ 197 #define MIF_ADDR_OFFSET 0x16000 198 #define MIF_ADDR(reg)\ 199 (FZC_MAC + (MIF_ADDR_OFFSET) + (reg)) 200 201 /* BMAC registers offset */ 202 #define BTXMAC_SW_RST_REG 0x000 /* TX MAC software reset */ 203 #define BRXMAC_SW_RST_REG 0x008 /* RX MAC software reset */ 204 #define MAC_SEND_PAUSE_REG 0x010 /* send pause command */ 205 #define BTXMAC_STATUS_REG 0x020 /* TX MAC status */ 206 #define BRXMAC_STATUS_REG 0x028 /* RX MAC status */ 207 #define BMAC_CTRL_STAT_REG 0x030 /* MAC control status */ 208 #define BTXMAC_STAT_MSK_REG 0x040 /* TX MAC mask */ 209 #define BRXMAC_STAT_MSK_REG 0x048 /* RX MAC mask */ 210 #define BMAC_C_S_MSK_REG 0x050 /* MAC control mask */ 211 #define TXMAC_CONFIG_REG 0x060 /* TX MAC config */ 212 /* cfg register bitmap */ 213 214 typedef union _btxmac_config_t { 215 uint64_t value; 216 217 struct { 218 #if defined(_BIG_ENDIAN) 219 uint32_t msw; /* Most significant word */ 220 uint32_t lsw; /* Least significant word */ 221 #elif defined(_LITTLE_ENDIAN) 222 uint32_t lsw; /* Least significant word */ 223 uint32_t msw; /* Most significant word */ 224 #endif 225 } val; 226 struct { 227 #if defined(_BIG_ENDIAN) 228 uint32_t w1; 229 #endif 230 struct { 231 #if defined(_BIT_FIELDS_HTOL) 232 uint32_t rsrvd : 22; 233 uint32_t hdx_ctrl2 : 1; 234 uint32_t no_fcs : 1; 235 uint32_t hdx_ctrl : 7; 236 uint32_t txmac_enable : 1; 237 #elif defined(_BIT_FIELDS_LTOH) 238 uint32_t txmac_enable : 1; 239 uint32_t hdx_ctrl : 7; 240 uint32_t no_fcs : 1; 241 uint32_t hdx_ctrl2 : 1; 242 uint32_t rsrvd : 22; 243 #endif 244 } w0; 245 246 #if defined(_LITTLE_ENDIAN) 247 uint32_t w1; 248 #endif 249 } bits; 250 } btxmac_config_t, *p_btxmac_config_t; 251 252 #define RXMAC_CONFIG_REG 0x068 /* RX MAC config */ 253 254 typedef union _brxmac_config_t { 255 uint64_t value; 256 257 struct { 258 #if defined(_BIG_ENDIAN) 259 uint32_t msw; /* Most significant word */ 260 uint32_t lsw; /* Least significant word */ 261 #elif defined(_LITTLE_ENDIAN) 262 uint32_t lsw; /* Least significant word */ 263 uint32_t msw; /* Most significant word */ 264 #endif 265 } val; 266 struct { 267 #if defined(_BIG_ENDIAN) 268 uint32_t w1; 269 #endif 270 struct { 271 #if defined(_BIT_FIELDS_HTOL) 272 uint32_t rsrvd : 20; 273 uint32_t mac_reg_sw_test : 2; 274 uint32_t mac2ipp_pkt_cnt_en : 1; 275 uint32_t rx_crs_extend_en : 1; 276 uint32_t error_chk_dis : 1; 277 uint32_t addr_filter_en : 1; 278 uint32_t hash_filter_en : 1; 279 uint32_t promiscuous_group : 1; 280 uint32_t promiscuous : 1; 281 uint32_t strip_fcs : 1; 282 uint32_t strip_pad : 1; 283 uint32_t rxmac_enable : 1; 284 #elif defined(_BIT_FIELDS_LTOH) 285 uint32_t rxmac_enable : 1; 286 uint32_t strip_pad : 1; 287 uint32_t strip_fcs : 1; 288 uint32_t promiscuous : 1; 289 uint32_t promiscuous_group : 1; 290 uint32_t hash_filter_en : 1; 291 uint32_t addr_filter_en : 1; 292 uint32_t error_chk_dis : 1; 293 uint32_t rx_crs_extend_en : 1; 294 uint32_t mac2ipp_pkt_cnt_en : 1; 295 uint32_t mac_reg_sw_test : 2; 296 uint32_t rsrvd : 20; 297 #endif 298 } w0; 299 300 #if defined(_LITTLE_ENDIAN) 301 uint32_t w1; 302 #endif 303 } bits; 304 } brxmac_config_t, *p_brxmac_config_t; 305 306 #define MAC_CTRL_CONFIG_REG 0x070 /* MAC control config */ 307 #define MAC_XIF_CONFIG_REG 0x078 /* XIF config */ 308 309 typedef union _bxif_config_t { 310 uint64_t value; 311 312 struct { 313 #if defined(_BIG_ENDIAN) 314 uint32_t msw; /* Most significant word */ 315 uint32_t lsw; /* Least significant word */ 316 #elif defined(_LITTLE_ENDIAN) 317 uint32_t lsw; /* Least significant word */ 318 uint32_t msw; /* Most significant word */ 319 #endif 320 } val; 321 struct { 322 #if defined(_BIG_ENDIAN) 323 uint32_t w1; 324 #endif 325 struct { 326 #if defined(_BIT_FIELDS_HTOL) 327 uint32_t rsrvd2 : 24; 328 uint32_t sel_clk_25mhz : 1; 329 uint32_t led_polarity : 1; 330 uint32_t force_led_on : 1; 331 uint32_t used : 1; 332 uint32_t gmii_mode : 1; 333 uint32_t rsrvd : 1; 334 uint32_t loopback : 1; 335 uint32_t tx_output_en : 1; 336 #elif defined(_BIT_FIELDS_LTOH) 337 uint32_t tx_output_en : 1; 338 uint32_t loopback : 1; 339 uint32_t rsrvd : 1; 340 uint32_t gmii_mode : 1; 341 uint32_t used : 1; 342 uint32_t force_led_on : 1; 343 uint32_t led_polarity : 1; 344 uint32_t sel_clk_25mhz : 1; 345 uint32_t rsrvd2 : 24; 346 #endif 347 } w0; 348 349 #if defined(_LITTLE_ENDIAN) 350 uint32_t w1; 351 #endif 352 } bits; 353 } bxif_config_t, *p_bxif_config_t; 354 355 #define BMAC_MIN_REG 0x0a0 /* min frame size */ 356 #define BMAC_MAX_REG 0x0a8 /* max frame size reg */ 357 #define MAC_PA_SIZE_REG 0x0b0 /* num of preamble bytes */ 358 #define MAC_CTRL_TYPE_REG 0x0c8 /* type field of MAC ctrl */ 359 #define BMAC_ADDR0_REG 0x100 /* MAC unique ad0 reg (HI 0) */ 360 #define BMAC_ADDR1_REG 0x108 /* MAC unique ad1 reg */ 361 #define BMAC_ADDR2_REG 0x110 /* MAC unique ad2 reg */ 362 #define BMAC_ADDR3_REG 0x118 /* MAC alt ad0 reg (HI 1) */ 363 #define BMAC_ADDR4_REG 0x120 /* MAC alt ad0 reg */ 364 #define BMAC_ADDR5_REG 0x128 /* MAC alt ad0 reg */ 365 #define BMAC_ADDR6_REG 0x130 /* MAC alt ad1 reg (HI 2) */ 366 #define BMAC_ADDR7_REG 0x138 /* MAC alt ad1 reg */ 367 #define BMAC_ADDR8_REG 0x140 /* MAC alt ad1 reg */ 368 #define BMAC_ADDR9_REG 0x148 /* MAC alt ad2 reg (HI 3) */ 369 #define BMAC_ADDR10_REG 0x150 /* MAC alt ad2 reg */ 370 #define BMAC_ADDR11_REG 0x158 /* MAC alt ad2 reg */ 371 #define BMAC_ADDR12_REG 0x160 /* MAC alt ad3 reg (HI 4) */ 372 #define BMAC_ADDR13_REG 0x168 /* MAC alt ad3 reg */ 373 #define BMAC_ADDR14_REG 0x170 /* MAC alt ad3 reg */ 374 #define BMAC_ADDR15_REG 0x178 /* MAC alt ad4 reg (HI 5) */ 375 #define BMAC_ADDR16_REG 0x180 /* MAC alt ad4 reg */ 376 #define BMAC_ADDR17_REG 0x188 /* MAC alt ad4 reg */ 377 #define BMAC_ADDR18_REG 0x190 /* MAC alt ad5 reg (HI 6) */ 378 #define BMAC_ADDR19_REG 0x198 /* MAC alt ad5 reg */ 379 #define BMAC_ADDR20_REG 0x1a0 /* MAC alt ad5 reg */ 380 #define BMAC_ADDR21_REG 0x1a8 /* MAC alt ad6 reg (HI 7) */ 381 #define BMAC_ADDR22_REG 0x1b0 /* MAC alt ad6 reg */ 382 #define BMAC_ADDR23_REG 0x1b8 /* MAC alt ad6 reg */ 383 #define MAC_FC_ADDR0_REG 0x268 /* FC frame addr0 (HI 0, p3) */ 384 #define MAC_FC_ADDR1_REG 0x270 /* FC frame addr1 */ 385 #define MAC_FC_ADDR2_REG 0x278 /* FC frame addr2 */ 386 #define MAC_ADDR_FILT0_REG 0x298 /* bits [47:32] (HI 0, p2) */ 387 #define MAC_ADDR_FILT1_REG 0x2a0 /* bits [31:16] */ 388 #define MAC_ADDR_FILT2_REG 0x2a8 /* bits [15:0] */ 389 #define MAC_ADDR_FILT12_MASK_REG 0x2b0 /* addr filter 2 & 1 mask */ 390 #define MAC_ADDR_FILT00_MASK_REG 0x2b8 /* addr filter 0 mask */ 391 #define MAC_HASH_TBL0_REG 0x2c0 /* hash table 0 reg */ 392 #define MAC_HASH_TBL1_REG 0x2c8 /* hash table 1 reg */ 393 #define MAC_HASH_TBL2_REG 0x2d0 /* hash table 2 reg */ 394 #define MAC_HASH_TBL3_REG 0x2d8 /* hash table 3 reg */ 395 #define MAC_HASH_TBL4_REG 0x2e0 /* hash table 4 reg */ 396 #define MAC_HASH_TBL5_REG 0x2e8 /* hash table 5 reg */ 397 #define MAC_HASH_TBL6_REG 0x2f0 /* hash table 6 reg */ 398 #define MAC_HASH_TBL7_REG 0x2f8 /* hash table 7 reg */ 399 #define MAC_HASH_TBL8_REG 0x300 /* hash table 8 reg */ 400 #define MAC_HASH_TBL9_REG 0x308 /* hash table 9 reg */ 401 #define MAC_HASH_TBL10_REG 0x310 /* hash table 10 reg */ 402 #define MAC_HASH_TBL11_REG 0x318 /* hash table 11 reg */ 403 #define MAC_HASH_TBL12_REG 0x320 /* hash table 12 reg */ 404 #define MAC_HASH_TBL13_REG 0x328 /* hash table 13 reg */ 405 #define MAC_HASH_TBL14_REG 0x330 /* hash table 14 reg */ 406 #define MAC_HASH_TBL15_REG 0x338 /* hash table 15 reg */ 407 #define RXMAC_FRM_CNT_REG 0x370 /* receive frame counter */ 408 #define MAC_LEN_ER_CNT_REG 0x378 /* length error counter */ 409 #define BMAC_AL_ER_CNT_REG 0x380 /* alignment error counter */ 410 #define BMAC_CRC_ER_CNT_REG 0x388 /* FCS error counter */ 411 #define BMAC_CD_VIO_CNT_REG 0x390 /* RX code violation err */ 412 #define BMAC_SM_REG 0x3a0 /* (ro) state machine reg */ 413 #define BMAC_ALTAD_CMPEN_REG 0x3f8 /* Alt addr compare enable */ 414 #define BMAC_HOST_INF0_REG 0x400 /* Host info */ 415 /* (own da, add filter, fc) */ 416 #define BMAC_HOST_INF1_REG 0x408 /* Host info (alt ad 0) */ 417 #define BMAC_HOST_INF2_REG 0x410 /* Host info (alt ad 1) */ 418 #define BMAC_HOST_INF3_REG 0x418 /* Host info (alt ad 2) */ 419 #define BMAC_HOST_INF4_REG 0x420 /* Host info (alt ad 3) */ 420 #define BMAC_HOST_INF5_REG 0x428 /* Host info (alt ad 4) */ 421 #define BMAC_HOST_INF6_REG 0x430 /* Host info (alt ad 5) */ 422 #define BMAC_HOST_INF7_REG 0x438 /* Host info (alt ad 6) */ 423 #define BMAC_HOST_INF8_REG 0x440 /* Host info (hash hit, miss) */ 424 #define BTXMAC_BYTE_CNT_REG 0x448 /* Tx byte count */ 425 #define BTXMAC_FRM_CNT_REG 0x450 /* frame count */ 426 #define BRXMAC_BYTE_CNT_REG 0x458 /* Rx byte count */ 427 /* x ranges from 0 to 6 (BMAC_MAX_ALT_ADDR_ENTRY - 1) */ 428 #define BMAC_ALT_ADDR0N_REG_ADDR(x) (BMAC_ADDR3_REG + (x) * 24) 429 #define BMAC_ALT_ADDR1N_REG_ADDR(x) (BMAC_ADDR3_REG + 8 + (x) * 24) 430 #define BMAC_ALT_ADDR2N_REG_ADDR(x) (BMAC_ADDR3_REG + 0x10 + (x) * 24) 431 #define BMAC_HASH_TBLN_REG_ADDR(x) (MAC_HASH_TBL0_REG + (x) * 8) 432 #define BMAC_HOST_INFN_REG_ADDR(x) (BMAC_HOST_INF0_REG + (x) * 8) 433 434 /* XMAC registers offset */ 435 #define XTXMAC_SW_RST_REG 0x000 /* XTX MAC soft reset */ 436 #define XRXMAC_SW_RST_REG 0x008 /* XRX MAC soft reset */ 437 #define XTXMAC_STATUS_REG 0x020 /* XTX MAC status */ 438 #define XRXMAC_STATUS_REG 0x028 /* XRX MAC status */ 439 #define XMAC_CTRL_STAT_REG 0x030 /* Control / Status */ 440 #define XTXMAC_STAT_MSK_REG 0x040 /* XTX MAC Status mask */ 441 #define XRXMAC_STAT_MSK_REG 0x048 /* XRX MAC Status mask */ 442 #define XMAC_C_S_MSK_REG 0x050 /* Control / Status mask */ 443 #define XMAC_CONFIG_REG 0x060 /* Configuration */ 444 445 /* xmac config bit fields */ 446 typedef union _xmac_cfg_t { 447 uint64_t value; 448 449 struct { 450 #if defined(_BIG_ENDIAN) 451 uint32_t msw; /* Most significant word */ 452 uint32_t lsw; /* Least significant word */ 453 #elif defined(_LITTLE_ENDIAN) 454 uint32_t lsw; /* Least significant word */ 455 uint32_t msw; /* Most significant word */ 456 #endif 457 } val; 458 struct { 459 #if defined(_BIG_ENDIAN) 460 uint32_t w1; 461 #endif 462 struct { 463 #if defined(_BIT_FIELDS_HTOL) 464 uint32_t sel_clk_25mhz : 1; 465 uint32_t pcs_bypass : 1; 466 uint32_t xpcs_bypass : 1; 467 uint32_t mii_gmii_mode : 2; 468 uint32_t lfs_disable : 1; 469 uint32_t loopback : 1; 470 uint32_t tx_output_en : 1; 471 uint32_t sel_por_clk_src : 1; 472 uint32_t led_polarity : 1; 473 uint32_t force_led_on : 1; 474 uint32_t pass_fctl_frames : 1; 475 uint32_t recv_pause_en : 1; 476 uint32_t mac2ipp_pkt_cnt_en : 1; 477 uint32_t strip_crc : 1; 478 uint32_t addr_filter_en : 1; 479 uint32_t hash_filter_en : 1; 480 uint32_t code_viol_chk_dis : 1; 481 uint32_t reserved_mcast : 1; 482 uint32_t rx_crc_chk_dis : 1; 483 uint32_t error_chk_dis : 1; 484 uint32_t promisc_grp : 1; 485 uint32_t promiscuous : 1; 486 uint32_t rx_mac_enable : 1; 487 uint32_t warning_msg_en : 1; 488 uint32_t used : 3; 489 uint32_t always_no_crc : 1; 490 uint32_t var_min_ipg_en : 1; 491 uint32_t strech_mode : 1; 492 uint32_t tx_enable : 1; 493 #elif defined(_BIT_FIELDS_LTOH) 494 uint32_t tx_enable : 1; 495 uint32_t strech_mode : 1; 496 uint32_t var_min_ipg_en : 1; 497 uint32_t always_no_crc : 1; 498 uint32_t used : 3; 499 uint32_t warning_msg_en : 1; 500 uint32_t rx_mac_enable : 1; 501 uint32_t promiscuous : 1; 502 uint32_t promisc_grp : 1; 503 uint32_t error_chk_dis : 1; 504 uint32_t rx_crc_chk_dis : 1; 505 uint32_t reserved_mcast : 1; 506 uint32_t code_viol_chk_dis : 1; 507 uint32_t hash_filter_en : 1; 508 uint32_t addr_filter_en : 1; 509 uint32_t strip_crc : 1; 510 uint32_t mac2ipp_pkt_cnt_en : 1; 511 uint32_t recv_pause_en : 1; 512 uint32_t pass_fctl_frames : 1; 513 uint32_t force_led_on : 1; 514 uint32_t led_polarity : 1; 515 uint32_t sel_por_clk_src : 1; 516 uint32_t tx_output_en : 1; 517 uint32_t loopback : 1; 518 uint32_t lfs_disable : 1; 519 uint32_t mii_gmii_mode : 2; 520 uint32_t xpcs_bypass : 1; 521 uint32_t pcs_bypass : 1; 522 uint32_t sel_clk_25mhz : 1; 523 #endif 524 } w0; 525 526 #if defined(_LITTLE_ENDIAN) 527 uint32_t w1; 528 #endif 529 } bits; 530 } xmac_cfg_t, *p_xmac_cfg_t; 531 532 #define XMAC_IPG_REG 0x080 /* Inter-Packet-Gap */ 533 #define XMAC_MIN_REG 0x088 /* min frame size register */ 534 #define XMAC_MAX_REG 0x090 /* max frame/burst size */ 535 #define XMAC_ADDR0_REG 0x0a0 /* [47:32] of MAC addr (HI17) */ 536 #define XMAC_ADDR1_REG 0x0a8 /* [31:16] of MAC addr */ 537 #define XMAC_ADDR2_REG 0x0b0 /* [15:0] of MAC addr */ 538 #define XRXMAC_BT_CNT_REG 0x100 /* bytes received / 8 */ 539 #define XRXMAC_BC_FRM_CNT_REG 0x108 /* good BC frames received */ 540 #define XRXMAC_MC_FRM_CNT_REG 0x110 /* good MC frames received */ 541 #define XRXMAC_FRAG_CNT_REG 0x118 /* frag frames rejected */ 542 #define XRXMAC_HIST_CNT1_REG 0x120 /* 64 bytes frames */ 543 #define XRXMAC_HIST_CNT2_REG 0x128 /* 65-127 bytes frames */ 544 #define XRXMAC_HIST_CNT3_REG 0x130 /* 128-255 bytes frames */ 545 #define XRXMAC_HIST_CNT4_REG 0x138 /* 256-511 bytes frames */ 546 #define XRXMAC_HIST_CNT5_REG 0x140 /* 512-1023 bytes frames */ 547 #define XRXMAC_HIST_CNT6_REG 0x148 /* 1024-1522 bytes frames */ 548 #define XRXMAC_MPSZER_CNT_REG 0x150 /* frames > maxframesize */ 549 #define XRXMAC_CRC_ER_CNT_REG 0x158 /* frames failed CRC */ 550 #define XRXMAC_CD_VIO_CNT_REG 0x160 /* frames with code vio */ 551 #define XRXMAC_AL_ER_CNT_REG 0x168 /* frames with align error */ 552 #define XTXMAC_FRM_CNT_REG 0x170 /* tx frames */ 553 #define XTXMAC_BYTE_CNT_REG 0x178 /* tx bytes / 8 */ 554 #define XMAC_LINK_FLT_CNT_REG 0x180 /* link faults */ 555 #define XRXMAC_HIST_CNT7_REG 0x188 /* MAC2IPP/>1523 bytes frames */ 556 #define XMAC_SM_REG 0x1a8 /* State machine */ 557 #define XMAC_INTERN1_REG 0x1b0 /* internal signals for diag */ 558 #define XMAC_INTERN2_REG 0x1b8 /* internal signals for diag */ 559 #define XMAC_ADDR_CMPEN_REG 0x208 /* alt MAC addr check */ 560 #define XMAC_ADDR3_REG 0x218 /* alt MAC addr 0 (HI 0) */ 561 #define XMAC_ADDR4_REG 0x220 /* alt MAC addr 0 */ 562 #define XMAC_ADDR5_REG 0x228 /* alt MAC addr 0 */ 563 #define XMAC_ADDR6_REG 0x230 /* alt MAC addr 1 (HI 1) */ 564 #define XMAC_ADDR7_REG 0x238 /* alt MAC addr 1 */ 565 #define XMAC_ADDR8_REG 0x240 /* alt MAC addr 1 */ 566 #define XMAC_ADDR9_REG 0x248 /* alt MAC addr 2 (HI 2) */ 567 #define XMAC_ADDR10_REG 0x250 /* alt MAC addr 2 */ 568 #define XMAC_ADDR11_REG 0x258 /* alt MAC addr 2 */ 569 #define XMAC_ADDR12_REG 0x260 /* alt MAC addr 3 (HI 3) */ 570 #define XMAC_ADDR13_REG 0x268 /* alt MAC addr 3 */ 571 #define XMAC_ADDR14_REG 0x270 /* alt MAC addr 3 */ 572 #define XMAC_ADDR15_REG 0x278 /* alt MAC addr 4 (HI 4) */ 573 #define XMAC_ADDR16_REG 0x280 /* alt MAC addr 4 */ 574 #define XMAC_ADDR17_REG 0x288 /* alt MAC addr 4 */ 575 #define XMAC_ADDR18_REG 0x290 /* alt MAC addr 5 (HI 5) */ 576 #define XMAC_ADDR19_REG 0x298 /* alt MAC addr 5 */ 577 #define XMAC_ADDR20_REG 0x2a0 /* alt MAC addr 5 */ 578 #define XMAC_ADDR21_REG 0x2a8 /* alt MAC addr 6 (HI 6) */ 579 #define XMAC_ADDR22_REG 0x2b0 /* alt MAC addr 6 */ 580 #define XMAC_ADDR23_REG 0x2b8 /* alt MAC addr 6 */ 581 #define XMAC_ADDR24_REG 0x2c0 /* alt MAC addr 7 (HI 7) */ 582 #define XMAC_ADDR25_REG 0x2c8 /* alt MAC addr 7 */ 583 #define XMAC_ADDR26_REG 0x2d0 /* alt MAC addr 7 */ 584 #define XMAC_ADDR27_REG 0x2d8 /* alt MAC addr 8 (HI 8) */ 585 #define XMAC_ADDR28_REG 0x2e0 /* alt MAC addr 8 */ 586 #define XMAC_ADDR29_REG 0x2e8 /* alt MAC addr 8 */ 587 #define XMAC_ADDR30_REG 0x2f0 /* alt MAC addr 9 (HI 9) */ 588 #define XMAC_ADDR31_REG 0x2f8 /* alt MAC addr 9 */ 589 #define XMAC_ADDR32_REG 0x300 /* alt MAC addr 9 */ 590 #define XMAC_ADDR33_REG 0x308 /* alt MAC addr 10 (HI 10) */ 591 #define XMAC_ADDR34_REG 0x310 /* alt MAC addr 10 */ 592 #define XMAC_ADDR35_REG 0x318 /* alt MAC addr 10 */ 593 #define XMAC_ADDR36_REG 0x320 /* alt MAC addr 11 (HI 11) */ 594 #define XMAC_ADDR37_REG 0x328 /* alt MAC addr 11 */ 595 #define XMAC_ADDR38_REG 0x330 /* alt MAC addr 11 */ 596 #define XMAC_ADDR39_REG 0x338 /* alt MAC addr 12 (HI 12) */ 597 #define XMAC_ADDR40_REG 0x340 /* alt MAC addr 12 */ 598 #define XMAC_ADDR41_REG 0x348 /* alt MAC addr 12 */ 599 #define XMAC_ADDR42_REG 0x350 /* alt MAC addr 13 (HI 13) */ 600 #define XMAC_ADDR43_REG 0x358 /* alt MAC addr 13 */ 601 #define XMAC_ADDR44_REG 0x360 /* alt MAC addr 13 */ 602 #define XMAC_ADDR45_REG 0x368 /* alt MAC addr 14 (HI 14) */ 603 #define XMAC_ADDR46_REG 0x370 /* alt MAC addr 14 */ 604 #define XMAC_ADDR47_REG 0x378 /* alt MAC addr 14 */ 605 #define XMAC_ADDR48_REG 0x380 /* alt MAC addr 15 (HI 15) */ 606 #define XMAC_ADDR49_REG 0x388 /* alt MAC addr 15 */ 607 #define XMAC_ADDR50_REG 0x390 /* alt MAC addr 15 */ 608 #define XMAC_ADDR_FILT0_REG 0x818 /* [47:32] addr filter (HI18) */ 609 #define XMAC_ADDR_FILT1_REG 0x820 /* [31:16] of addr filter */ 610 #define XMAC_ADDR_FILT2_REG 0x828 /* [15:0] of addr filter */ 611 #define XMAC_ADDR_FILT12_MASK_REG 0x830 /* addr filter 2 & 1 mask */ 612 #define XMAC_ADDR_FILT0_MASK_REG 0x838 /* addr filter 0 mask */ 613 #define XMAC_HASH_TBL0_REG 0x840 /* hash table 0 reg */ 614 #define XMAC_HASH_TBL1_REG 0x848 /* hash table 1 reg */ 615 #define XMAC_HASH_TBL2_REG 0x850 /* hash table 2 reg */ 616 #define XMAC_HASH_TBL3_REG 0x858 /* hash table 3 reg */ 617 #define XMAC_HASH_TBL4_REG 0x860 /* hash table 4 reg */ 618 #define XMAC_HASH_TBL5_REG 0x868 /* hash table 5 reg */ 619 #define XMAC_HASH_TBL6_REG 0x870 /* hash table 6 reg */ 620 #define XMAC_HASH_TBL7_REG 0x878 /* hash table 7 reg */ 621 #define XMAC_HASH_TBL8_REG 0x880 /* hash table 8 reg */ 622 #define XMAC_HASH_TBL9_REG 0x888 /* hash table 9 reg */ 623 #define XMAC_HASH_TBL10_REG 0x890 /* hash table 10 reg */ 624 #define XMAC_HASH_TBL11_REG 0x898 /* hash table 11 reg */ 625 #define XMAC_HASH_TBL12_REG 0x8a0 /* hash table 12 reg */ 626 #define XMAC_HASH_TBL13_REG 0x8a8 /* hash table 13 reg */ 627 #define XMAC_HASH_TBL14_REG 0x8b0 /* hash table 14 reg */ 628 #define XMAC_HASH_TBL15_REG 0x8b8 /* hash table 15 reg */ 629 #define XMAC_HOST_INF0_REG 0x900 /* Host info 0 (alt ad 0) */ 630 #define XMAC_HOST_INF1_REG 0x908 /* Host info 1 (alt ad 1) */ 631 #define XMAC_HOST_INF2_REG 0x910 /* Host info 2 (alt ad 2) */ 632 #define XMAC_HOST_INF3_REG 0x918 /* Host info 3 (alt ad 3) */ 633 #define XMAC_HOST_INF4_REG 0x920 /* Host info 4 (alt ad 4) */ 634 #define XMAC_HOST_INF5_REG 0x928 /* Host info 5 (alt ad 5) */ 635 #define XMAC_HOST_INF6_REG 0x930 /* Host info 6 (alt ad 6) */ 636 #define XMAC_HOST_INF7_REG 0x938 /* Host info 7 (alt ad 7) */ 637 #define XMAC_HOST_INF8_REG 0x940 /* Host info 8 (alt ad 8) */ 638 #define XMAC_HOST_INF9_REG 0x948 /* Host info 9 (alt ad 9) */ 639 #define XMAC_HOST_INF10_REG 0x950 /* Host info 10 (alt ad 10) */ 640 #define XMAC_HOST_INF11_REG 0x958 /* Host info 11 (alt ad 11) */ 641 #define XMAC_HOST_INF12_REG 0x960 /* Host info 12 (alt ad 12) */ 642 #define XMAC_HOST_INF13_REG 0x968 /* Host info 13 (alt ad 13) */ 643 #define XMAC_HOST_INF14_REG 0x970 /* Host info 14 (alt ad 14) */ 644 #define XMAC_HOST_INF15_REG 0x978 /* Host info 15 (alt ad 15) */ 645 #define XMAC_HOST_INF16_REG 0x980 /* Host info 16 (hash hit) */ 646 #define XMAC_HOST_INF17_REG 0x988 /* Host info 17 (own da) */ 647 #define XMAC_HOST_INF18_REG 0x990 /* Host info 18 (filter hit) */ 648 #define XMAC_HOST_INF19_REG 0x998 /* Host info 19 (fc hit) */ 649 #define XMAC_PA_DATA0_REG 0xb80 /* preamble [31:0] */ 650 #define XMAC_PA_DATA1_REG 0xb88 /* preamble [63:32] */ 651 #define XMAC_DEBUG_SEL_REG 0xb90 /* debug select */ 652 #define XMAC_TRAINING_VECT_REG 0xb98 /* training vector */ 653 /* x ranges from 0 to 15 (XMAC_MAX_ALT_ADDR_ENTRY - 1) */ 654 #define XMAC_ALT_ADDR0N_REG_ADDR(x) (XMAC_ADDR3_REG + (x) * 24) 655 #define XMAC_ALT_ADDR1N_REG_ADDR(x) (XMAC_ADDR3_REG + 8 + (x) * 24) 656 #define XMAC_ALT_ADDR2N_REG_ADDR(x) (XMAC_ADDR3_REG + 16 + (x) * 24) 657 #define XMAC_HASH_TBLN_REG_ADDR(x) (XMAC_HASH_TBL0_REG + (x) * 8) 658 #define XMAC_HOST_INFN_REG_ADDR(x) (XMAC_HOST_INF0_REG + (x) * 8) 659 660 /* MIF registers offset */ 661 #define MIF_BB_MDC_REG 0 /* MIF bit-bang clock */ 662 #define MIF_BB_MDO_REG 0x008 /* MIF bit-bang data */ 663 #define MIF_BB_MDO_EN_REG 0x010 /* MIF bit-bang output en */ 664 #define MIF_OUTPUT_FRAME_REG 0x018 /* MIF frame/output reg */ 665 #define MIF_CONFIG_REG 0x020 /* MIF config reg */ 666 #define MIF_POLL_STATUS_REG 0x028 /* MIF poll status reg */ 667 #define MIF_POLL_MASK_REG 0x030 /* MIF poll mask reg */ 668 #define MIF_STATE_MACHINE_REG 0x038 /* MIF state machine reg */ 669 #define MIF_STATUS_REG 0x040 /* MIF status reg */ 670 #define MIF_MASK_REG 0x048 /* MIF mask reg */ 671 672 673 /* PCS registers offset */ 674 #define PCS_MII_CTRL_REG 0 /* PCS MII control reg */ 675 #define PCS_MII_STATUS_REG 0x008 /* PCS MII status reg */ 676 #define PCS_MII_ADVERT_REG 0x010 /* PCS MII advertisement */ 677 #define PCS_MII_LPA_REG 0x018 /* link partner ability */ 678 #define PCS_CONFIG_REG 0x020 /* PCS config reg */ 679 #define PCS_STATE_MACHINE_REG 0x028 /* PCS state machine */ 680 #define PCS_INTR_STATUS_REG 0x030 /* PCS interrupt status */ 681 #define PCS_DATAPATH_MODE_REG 0x0a0 /* datapath mode reg */ 682 #define PCS_PACKET_COUNT_REG 0x0c0 /* PCS packet counter */ 683 684 #define XPCS_CTRL_1_REG 0 /* Control */ 685 #define XPCS_STATUS_1_REG 0x008 686 #define XPCS_DEV_ID_REG 0x010 /* 32bits IEEE manufacture ID */ 687 #define XPCS_SPEED_ABILITY_REG 0x018 688 #define XPCS_DEV_IN_PKG_REG 0x020 689 #define XPCS_CTRL_2_REG 0x028 690 #define XPCS_STATUS_2_REG 0x030 691 #define XPCS_PKG_ID_REG 0x038 /* Package ID */ 692 #define XPCS_STATUS_REG 0x040 693 #define XPCS_TEST_CTRL_REG 0x048 694 #define XPCS_CFG_VENDOR_1_REG 0x050 695 #define XPCS_DIAG_VENDOR_2_REG 0x058 696 #define XPCS_MASK_1_REG 0x060 697 #define XPCS_PKT_CNTR_REG 0x068 698 #define XPCS_TX_STATE_MC_REG 0x070 699 #define XPCS_DESKEW_ERR_CNTR_REG 0x078 700 #define XPCS_SYM_ERR_CNTR_L0_L1_REG 0x080 701 #define XPCS_SYM_ERR_CNTR_L2_L3_REG 0x088 702 #define XPCS_TRAINING_VECTOR_REG 0x090 703 704 /* ESR registers offset */ 705 #define ESR_RESET_REG 0 706 #define ESR_CONFIG_REG 0x008 707 #define ESR_0_PLL_CONFIG_REG 0x010 708 #define ESR_0_CONTROL_REG 0x018 709 #define ESR_0_TEST_CONFIG_REG 0x020 710 #define ESR_1_PLL_CONFIG_REG 0x028 711 #define ESR_1_CONTROL_REG 0x030 712 #define ESR_1_TEST_CONFIG_REG 0x038 713 #define ESR_ENET_RGMII_CFG_REG 0x040 714 #define ESR_INTERNAL_SIGNALS_REG 0x800 715 #define ESR_DEBUG_SEL_REG 0x808 716 717 718 /* Reset Register */ 719 #define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time */ 720 #define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl */ 721 722 /* Tx MAC Status Register */ 723 #define MAC_TX_FRAME_XMIT 0x00000001 /* successful tx frame */ 724 #define MAC_TX_UNDERRUN 0x00000002 /* starvation in xmit */ 725 #define MAC_TX_MAX_PACKET_ERR 0x00000004 /* TX frame exceeds max */ 726 #define MAC_TX_BYTE_CNT_EXP 0x00000400 /* TX byte cnt overflow */ 727 #define MAC_TX_FRAME_CNT_EXP 0x00000800 /* Tx frame cnt overflow */ 728 729 /* Rx MAC Status Register */ 730 #define MAC_RX_FRAME_RECV 0x00000001 /* successful rx frame */ 731 #define MAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 732 #define MAC_RX_FRAME_COUNT 0x00000004 /* rx frame cnt rollover */ 733 #define MAC_RX_ALIGN_ERR 0x00000008 /* alignment err rollover */ 734 #define MAC_RX_CRC_ERR 0x00000010 /* crc error cnt rollover */ 735 #define MAC_RX_LEN_ERR 0x00000020 /* length err cnt rollover */ 736 #define MAC_RX_VIOL_ERR 0x00000040 /* code vio err rollover */ 737 #define MAC_RX_BYTE_CNT_EXP 0x00000080 /* RX MAC byte rollover */ 738 739 /* MAC Control Status Register */ 740 #define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful pause frame */ 741 #define MAC_CTRL_PAUSE_STATE 0x00000002 /* notpause-->pause */ 742 #define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* pause-->notpause */ 743 #define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time */ 744 #define MAC_CTRL_PAUSE_TIME_SHIFT 16 745 746 /* Tx MAC Configuration Register */ 747 #define MAC_TX_CFG_TXMAC_ENABLE 0x00000001 /* enable TX MAC. */ 748 #define MAC_TX_CFG_NO_FCS 0x00000100 /* TX not generate CRC */ 749 750 /* Rx MAC Configuration Register */ 751 #define MAC_RX_CFG_RXMAC_ENABLE 0x00000001 /* enable RX MAC */ 752 #define MAC_RX_CFG_STRIP_PAD 0x00000002 /* not supported, set to 0 */ 753 #define MAC_RX_CFG_STRIP_FCS 0x00000004 /* strip last 4bytes (CRC) */ 754 #define MAC_RX_CFG_PROMISC 0x00000008 /* promisc mode enable */ 755 #define MAC_RX_CFG_PROMISC_GROUP 0x00000010 /* accept all MC frames */ 756 #define MAC_RX_CFG_HASH_FILTER_EN 0x00000020 /* use hash table */ 757 #define MAC_RX_CFG_ADDR_FILTER_EN 0x00000040 /* use address filter */ 758 #define MAC_RX_CFG_DISABLE_DISCARD 0x00000080 /* do not set abort bit */ 759 #define MAC_RX_MAC2IPP_PKT_CNT_EN 0x00000200 /* rx pkt cnt -> BMAC-IPP */ 760 #define MAC_RX_MAC_REG_RW_TEST_MASK 0x00000c00 /* BMAC reg RW test */ 761 #define MAC_RX_MAC_REG_RW_TEST_SHIFT 10 762 763 /* MAC Control Configuration Register */ 764 #define MAC_CTRL_CFG_SEND_PAUSE_EN 0x00000001 /* send pause flow ctrl */ 765 #define MAC_CTRL_CFG_RECV_PAUSE_EN 0x00000002 /* receive pause flow ctrl */ 766 #define MAC_CTRL_CFG_PASS_CTRL 0x00000004 /* accept MAC ctrl pkts */ 767 768 /* MAC XIF Configuration Register */ 769 #define MAC_XIF_TX_OUTPUT_EN 0x00000001 /* enable Tx output driver */ 770 #define MAC_XIF_MII_INT_LOOPBACK 0x00000002 /* loopback GMII xmit data */ 771 #define MAC_XIF_GMII_MODE 0x00000008 /* operates with GMII clks */ 772 #define MAC_XIF_LINK_LED 0x00000020 /* LINKLED# active (low) */ 773 #define MAC_XIF_LED_POLARITY 0x00000040 /* LED polarity */ 774 #define MAC_XIF_SEL_CLK_25MHZ 0x00000080 /* Select 10/100Mbps */ 775 776 /* MAC IPG Registers */ 777 #define BMAC_MIN_FRAME_MASK 0x3FF /* 10-bit reg */ 778 779 /* MAC Max Frame Size Register */ 780 #define BMAC_MAX_BURST_MASK 0x3FFF0000 /* max burst size [30:16] */ 781 #define BMAC_MAX_BURST_SHIFT 16 782 #define BMAC_MAX_FRAME_MASK 0x00007FFF /* max frame size [14:0] */ 783 #define BMAC_MAX_FRAME_SHIFT 0 784 785 /* MAC Preamble size register */ 786 #define BMAC_PA_SIZE_MASK 0x000003FF 787 /* # of preable bytes TxMAC sends at the beginning of each frame */ 788 789 /* 790 * mac address registers: 791 * register contains comparison 792 * -------- -------- ---------- 793 * 0 16 MSB of primary MAC addr [47:32] of DA field 794 * 1 16 middle bits "" [31:16] of DA field 795 * 2 16 LSB "" [15:0] of DA field 796 * 3*x 16MSB of alt MAC addr 1-7 [47:32] of DA field 797 * 4*x 16 middle bits "" [31:16] 798 * 5*x 16 LSB "" [15:0] 799 * 42 16 MSB of MAC CTRL addr [47:32] of DA. 800 * 43 16 middle bits "" [31:16] 801 * 44 16 LSB "" [15:0] 802 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames. 803 * if there is a match, MAC will set the bit for alternative address 804 * filter pass [15] 805 * 806 * here is the map of registers given MAC address notation: a:b:c:d:e:f 807 * ab cd ef 808 * primary addr reg 2 reg 1 reg 0 809 * alt addr 1 reg 5 reg 4 reg 3 810 * alt addr x reg 5*x reg 4*x reg 3*x 811 * | | | | 812 * | | | | 813 * alt addr 7 reg 23 reg 22 reg 21 814 * ctrl addr reg 44 reg 43 reg 42 815 */ 816 817 #define BMAC_ALT_ADDR_BASE 0x118 818 #define BMAC_MAX_ALT_ADDR_ENTRY 7 /* 7 alternate MAC addr */ 819 #define BMAC_MAX_ADDR_ENTRY (BMAC_MAX_ALT_ADDR_ENTRY + 1) 820 821 /* hash table registers */ 822 #define MAC_MAX_HASH_ENTRY 16 823 824 /* 27-bit register has the current state for key state machines in the MAC */ 825 #define MAC_SM_RLM_MASK 0x07800000 826 #define MAC_SM_RLM_SHIFT 23 827 #define MAC_SM_RX_FC_MASK 0x00700000 828 #define MAC_SM_RX_FC_SHIFT 20 829 #define MAC_SM_TLM_MASK 0x000F0000 830 #define MAC_SM_TLM_SHIFT 16 831 #define MAC_SM_ENCAP_SM_MASK 0x0000F000 832 #define MAC_SM_ENCAP_SM_SHIFT 12 833 #define MAC_SM_TX_REQ_MASK 0x00000C00 834 #define MAC_SM_TX_REQ_SHIFT 10 835 #define MAC_SM_TX_FC_MASK 0x000003C0 836 #define MAC_SM_TX_FC_SHIFT 6 837 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038 838 #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3 839 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007 840 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0 841 842 #define BMAC_ADDR0_CMPEN 0x00000001 843 #define BMAC_ADDRN_CMPEN(x) (BMAC_ADDR0_CMP_EN << (x)) 844 845 /* MAC Host Info Table Registers */ 846 #define BMAC_MAX_HOST_INFO_ENTRY 9 /* 9 host entries */ 847 848 /* 849 * ********************* XMAC registers ********************************* 850 */ 851 852 /* Reset Register */ 853 #define XTXMAC_SOFT_RST 0x00000001 /* XTX MAC software reset */ 854 #define XTXMAC_REG_RST 0x00000002 /* XTX MAC registers reset */ 855 #define XRXMAC_SOFT_RST 0x00000001 /* XRX MAC software reset */ 856 #define XRXMAC_REG_RST 0x00000002 /* XRX MAC registers reset */ 857 858 /* XTX MAC Status Register */ 859 #define XMAC_TX_FRAME_XMIT 0x00000001 /* successful tx frame */ 860 #define XMAC_TX_UNDERRUN 0x00000002 /* starvation in xmit */ 861 #define XMAC_TX_MAX_PACKET_ERR 0x00000004 /* XTX frame exceeds max */ 862 #define XMAC_TX_OVERFLOW 0x00000008 /* XTX byte cnt overflow */ 863 #define XMAC_TX_FIFO_XFR_ERR 0x00000010 /* xtlm state mach error */ 864 #define XMAC_TX_BYTE_CNT_EXP 0x00000400 /* XTX byte cnt overflow */ 865 #define XMAC_TX_FRAME_CNT_EXP 0x00000800 /* XTX frame cnt overflow */ 866 867 /* XRX MAC Status Register */ 868 #define XMAC_RX_FRAME_RCVD 0x00000001 /* successful rx frame */ 869 #define XMAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 870 #define XMAC_RX_UNDERFLOW 0x00000004 /* RX FIFO underrun */ 871 #define XMAC_RX_CRC_ERR_CNT_EXP 0x00000008 /* crc error cnt rollover */ 872 #define XMAC_RX_LEN_ERR_CNT_EXP 0x00000010 /* length err cnt rollover */ 873 #define XMAC_RX_VIOL_ERR_CNT_EXP 0x00000020 /* code vio err rollover */ 874 #define XMAC_RX_OCT_CNT_EXP 0x00000040 /* XRX MAC byte rollover */ 875 #define XMAC_RX_HST_CNT1_EXP 0x00000080 /* XRX MAC hist1 rollover */ 876 #define XMAC_RX_HST_CNT2_EXP 0x00000100 /* XRX MAC hist2 rollover */ 877 #define XMAC_RX_HST_CNT3_EXP 0x00000200 /* XRX MAC hist3 rollover */ 878 #define XMAC_RX_HST_CNT4_EXP 0x00000400 /* XRX MAC hist4 rollover */ 879 #define XMAC_RX_HST_CNT5_EXP 0x00000800 /* XRX MAC hist5 rollover */ 880 #define XMAC_RX_HST_CNT6_EXP 0x00001000 /* XRX MAC hist6 rollover */ 881 #define XMAC_RX_BCAST_CNT_EXP 0x00002000 /* XRX BC cnt rollover */ 882 #define XMAC_RX_MCAST_CNT_EXP 0x00004000 /* XRX MC cnt rollover */ 883 #define XMAC_RX_FRAG_CNT_EXP 0x00008000 /* fragment cnt rollover */ 884 #define XMAC_RX_ALIGNERR_CNT_EXP 0x00010000 /* framealign err rollover */ 885 #define XMAC_RX_LINK_FLT_CNT_EXP 0x00020000 /* link fault cnt rollover */ 886 #define XMAC_RX_REMOTE_FLT_DET 0x00040000 /* Remote Fault detected */ 887 #define XMAC_RX_LOCAL_FLT_DET 0x00080000 /* Local Fault detected */ 888 #define XMAC_RX_HST_CNT7_EXP 0x00100000 /* XRX MAC hist7 rollover */ 889 890 891 #define XMAC_CTRL_PAUSE_RCVD 0x00000001 /* successful pause frame */ 892 #define XMAC_CTRL_PAUSE_STATE 0x00000002 /* notpause-->pause */ 893 #define XMAC_CTRL_NOPAUSE_STATE 0x00000004 /* pause-->notpause */ 894 #define XMAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time */ 895 #define XMAC_CTRL_PAUSE_TIME_SHIFT 16 896 897 /* XMAC Configuration Register */ 898 #define XMAC_CONFIG_TX_BIT_MASK 0x000000ff /* bits [7:0] */ 899 #define XMAC_CONFIG_RX_BIT_MASK 0x001fff00 /* bits [20:8] */ 900 #define XMAC_CONFIG_XIF_BIT_MASK 0xffe00000 /* bits [31:21] */ 901 902 /* XTX MAC config bits */ 903 #define XMAC_TX_CFG_TX_ENABLE 0x00000001 /* enable XTX MAC */ 904 #define XMAC_TX_CFG_STRETCH_MD 0x00000002 /* WAN application */ 905 #define XMAC_TX_CFG_VAR_MIN_IPG_EN 0x00000004 /* Transmit pkts < minpsz */ 906 #define XMAC_TX_CFG_ALWAYS_NO_CRC 0x00000008 /* No CRC generated */ 907 908 #define XMAC_WARNING_MSG_ENABLE 0x00000080 /* Sim warning msg enable */ 909 910 /* XRX MAC config bits */ 911 #define XMAC_RX_CFG_RX_ENABLE 0x00000100 /* enable XRX MAC */ 912 #define XMAC_RX_CFG_PROMISC 0x00000200 /* promisc mode enable */ 913 #define XMAC_RX_CFG_PROMISC_GROUP 0x00000400 /* accept all MC frames */ 914 #define XMAC_RX_CFG_ERR_CHK_DISABLE 0x00000800 /* do not set abort bit */ 915 #define XMAC_RX_CFG_CRC_CHK_DISABLE 0x00001000 /* disable CRC logic */ 916 #define XMAC_RX_CFG_RESERVED_MCAST 0x00002000 /* reserved MCaddr compare */ 917 #define XMAC_RX_CFG_CD_VIO_CHK 0x00004000 /* rx code violation chk */ 918 #define XMAC_RX_CFG_HASH_FILTER_EN 0x00008000 /* use hash table */ 919 #define XMAC_RX_CFG_ADDR_FILTER_EN 0x00010000 /* use alt addr filter */ 920 #define XMAC_RX_CFG_STRIP_CRC 0x00020000 /* strip last 4bytes (CRC) */ 921 #define XMAC_RX_MAC2IPP_PKT_CNT_EN 0x00040000 /* histo_cntr7 cnt mode */ 922 #define XMAC_RX_CFG_RX_PAUSE_EN 0x00080000 /* receive pause flow ctrl */ 923 #define XMAC_RX_CFG_PASS_FLOW_CTRL 0x00100000 /* accept MAC ctrl pkts */ 924 925 926 /* MAC transceiver (XIF) configuration registers */ 927 928 #define XMAC_XIF_FORCE_LED_ON 0x00200000 /* Force Link LED on */ 929 #define XMAC_XIF_LED_POLARITY 0x00400000 /* LED polarity */ 930 #define XMAC_XIF_SEL_POR_CLK_SRC 0x00800000 /* Select POR clk src */ 931 #define XMAC_XIF_TX_OUTPUT_EN 0x01000000 /* enable MII/GMII modes */ 932 #define XMAC_XIF_LOOPBACK 0x02000000 /* loopback xmac xgmii tx */ 933 #define XMAC_XIF_LFS_DISABLE 0x04000000 /* disable link fault sig */ 934 #define XMAC_XIF_MII_MODE_MASK 0x18000000 /* MII/GMII/XGMII mode */ 935 #define XMAC_XIF_MII_MODE_SHIFT 27 936 #define XMAC_XIF_XGMII_MODE 0x00 937 #define XMAC_XIF_GMII_MODE 0x01 938 #define XMAC_XIF_MII_MODE 0x02 939 #define XMAC_XIF_ILLEGAL_MODE 0x03 940 #define XMAC_XIF_XPCS_BYPASS 0x20000000 /* use external xpcs */ 941 #define XMAC_XIF_1G_PCS_BYPASS 0x40000000 /* use external pcs */ 942 #define XMAC_XIF_SEL_CLK_25MHZ 0x80000000 /* 25Mhz clk for 100mbps */ 943 944 /* IPG register */ 945 #define XMAC_IPG_VALUE_MASK 0x00000007 /* IPG in XGMII mode */ 946 #define XMAC_IPG_VALUE_SHIFT 0 947 #define XMAC_IPG_VALUE1_MASK 0x0000ff00 /* IPG in GMII/MII mode */ 948 #define XMAC_IPG_VALUE1_SHIFT 8 949 #define XMAC_IPG_STRETCH_RATIO_MASK 0x001f0000 950 #define XMAC_IPG_STRETCH_RATIO_SHIFT 16 951 #define XMAC_IPG_STRETCH_CONST_MASK 0x00e00000 952 #define XMAC_IPG_STRETCH_CONST_SHIFT 21 953 954 #define IPG_12_15_BYTE 3 955 #define IPG_16_19_BYTE 4 956 #define IPG_20_23_BYTE 5 957 #define IPG1_12_BYTES 10 958 #define IPG1_13_BYTES 11 959 #define IPG1_14_BYTES 12 960 #define IPG1_15_BYTES 13 961 #define IPG1_16_BYTES 14 962 963 964 #define XMAC_MIN_TX_FRM_SZ_MASK 0x3ff /* Min tx frame size */ 965 #define XMAC_MIN_TX_FRM_SZ_SHIFT 0 966 #define XMAC_SLOT_TIME_MASK 0x0003fc00 /* slot time */ 967 #define XMAC_SLOT_TIME_SHIFT 10 968 #define XMAC_MIN_RX_FRM_SZ_MASK 0x3ff00000 /* Min rx frame size */ 969 #define XMAC_MIN_RX_FRM_SZ_SHIFT 20 970 #define XMAC_MAX_FRM_SZ_MASK 0x00003fff /* max tx frame size */ 971 972 /* State Machine Register */ 973 #define XMAC_SM_TX_LNK_MGMT_MASK 0x00000007 974 #define XMAC_SM_TX_LNK_MGMT_SHIFT 0 975 #define XMAC_SM_SOP_DETECT 0x00000008 976 #define XMAC_SM_LNK_FLT_SIG_MASK 0x00000030 977 #define XMAC_SM_LNK_FLT_SIG_SHIFT 4 978 #define XMAC_SM_MII_GMII_MD_RX_LNK 0x00000040 979 #define XMAC_SM_XGMII_MD_RX_LNK 0x00000080 980 #define XMAC_SM_XGMII_ONLY_VAL_SIG 0x00000100 981 #define XMAC_SM_ALT_ADR_N_HSH_FN_SIG 0x00000200 982 #define XMAC_SM_RXMAC_IPP_STAT_MASK 0x00001c00 983 #define XMAC_SM_RXMAC_IPP_STAT_SHIFT 10 984 #define XMAC_SM_RXFIFO_WPTR_CLK_MASK 0x007c0000 985 #define XMAC_SM_RXFIFO_WPTR_CLK_SHIFT 18 986 #define XMAC_SM_RXFIFO_RPTR_CLK_MASK 0x0F800000 987 #define XMAC_SM_RXFIFO_RPTR_CLK_SHIFT 23 988 #define XMAC_SM_TXFIFO_FULL_CLK 0x10000000 989 #define XMAC_SM_TXFIFO_EMPTY_CLK 0x20000000 990 #define XMAC_SM_RXFIFO_FULL_CLK 0x40000000 991 #define XMAC_SM_RXFIFO_EMPTY_CLK 0x80000000 992 993 /* Internal Signals 1 Register */ 994 #define XMAC_IS1_OPP_TXMAC_STAT_MASK 0x0000000F 995 #define XMAC_IS1_OPP_TXMAC_STAT_SHIFT 0 996 #define XMAC_IS1_OPP_TXMAC_ABORT 0x00000010 997 #define XMAC_IS1_OPP_TXMAC_TAG 0x00000020 998 #define XMAC_IS1_OPP_TXMAC_ACK 0x00000040 999 #define XMAC_IS1_TXMAC_OPP_REQ 0x00000080 1000 #define XMAC_IS1_RXMAC_IPP_STAT_MASK 0x0FFFFF00 1001 #define XMAC_IS1_RXMAC_IPP_STAT_SHIFT 8 1002 #define XMAC_IS1_RXMAC_IPP_CTRL 0x10000000 1003 #define XMAC_IS1_RXMAC_IPP_TAG 0x20000000 1004 #define XMAC_IS1_IPP_RXMAC_REQ 0x40000000 1005 #define XMAC_IS1_RXMAC_IPP_ACK 0x80000000 1006 1007 /* Internal Signals 2 Register */ 1008 #define XMAC_IS2_TX_HB_TIMER_MASK 0x0000000F 1009 #define XMAC_IS2_TX_HB_TIMER_SHIFT 0 1010 #define XMAC_IS2_RX_HB_TIMER_MASK 0x000000F0 1011 #define XMAC_IS2_RX_HB_TIMER_SHIFT 4 1012 #define XMAC_IS2_XPCS_RXC_MASK 0x0000FF00 1013 #define XMAC_IS2_XPCS_RXC_SHIFT 8 1014 #define XMAC_IS2_XPCS_TXC_MASK 0x00FF0000 1015 #define XMAC_IS2_XPCS_TXC_SHIFT 16 1016 #define XMAC_IS2_LOCAL_FLT_OC_SYNC 0x01000000 1017 #define XMAC_IS2_RMT_FLT_OC_SYNC 0x02000000 1018 1019 /* Register size masking */ 1020 1021 #define XTXMAC_FRM_CNT_MASK 0xFFFFFFFF 1022 #define XTXMAC_BYTE_CNT_MASK 0xFFFFFFFF 1023 #define XRXMAC_CRC_ER_CNT_MASK 0x000000FF 1024 #define XRXMAC_MPSZER_CNT_MASK 0x000000FF 1025 #define XRXMAC_CD_VIO_CNT_MASK 0x000000FF 1026 #define XRXMAC_BT_CNT_MASK 0xFFFFFFFF 1027 #define XRXMAC_HIST_CNT1_MASK 0x001FFFFF 1028 #define XRXMAC_HIST_CNT2_MASK 0x001FFFFF 1029 #define XRXMAC_HIST_CNT3_MASK 0x000FFFFF 1030 #define XRXMAC_HIST_CNT4_MASK 0x0007FFFF 1031 #define XRXMAC_HIST_CNT5_MASK 0x0003FFFF 1032 #define XRXMAC_HIST_CNT6_MASK 0x0001FFFF 1033 #define XRXMAC_BC_FRM_CNT_MASK 0x001FFFFF 1034 #define XRXMAC_MC_FRM_CNT_MASK 0x001FFFFF 1035 #define XRXMAC_FRAG_CNT_MASK 0x001FFFFF 1036 #define XRXMAC_AL_ER_CNT_MASK 0x000000FF 1037 #define XMAC_LINK_FLT_CNT_MASK 0x000000FF 1038 #define BTXMAC_FRM_CNT_MASK 0x001FFFFF 1039 #define BTXMAC_BYTE_CNT_MASK 0x07FFFFFF 1040 #define RXMAC_FRM_CNT_MASK 0x0000FFFF 1041 #define BRXMAC_BYTE_CNT_MASK 0x07FFFFFF 1042 #define BMAC_AL_ER_CNT_MASK 0x0000FFFF 1043 #define MAC_LEN_ER_CNT_MASK 0x0000FFFF 1044 #define BMAC_CRC_ER_CNT_MASK 0x0000FFFF 1045 #define BMAC_CD_VIO_CNT_MASK 0x0000FFFF 1046 #define XMAC_XPCS_DESKEW_ERR_CNT_MASK 0x000000FF 1047 #define XMAC_XPCS_SYM_ERR_CNT_L0_MASK 0x0000FFFF 1048 #define XMAC_XPCS_SYM_ERR_CNT_L1_MASK 0xFFFF0000 1049 #define XMAC_XPCS_SYM_ERR_CNT_L1_SHIFT 16 1050 #define XMAC_XPCS_SYM_ERR_CNT_L2_MASK 0x0000FFFF 1051 #define XMAC_XPCS_SYM_ERR_CNT_L3_MASK 0xFFFF0000 1052 #define XMAC_XPCS_SYM_ERR_CNT_L3_SHIFT 16 1053 1054 /* Alternate MAC address registers */ 1055 #define XMAC_MAX_ALT_ADDR_ENTRY 16 /* 16 alternate MAC addrs */ 1056 #define XMAC_MAX_ADDR_ENTRY (XMAC_MAX_ALT_ADDR_ENTRY + 1) 1057 1058 /* Max / Min parameters for Neptune MAC */ 1059 1060 #define MAC_MAX_ALT_ADDR_ENTRY XMAC_MAX_ALT_ADDR_ENTRY 1061 #define MAC_MAX_HOST_INFO_ENTRY XMAC_MAX_HOST_INFO_ENTRY 1062 1063 /* HostInfo entry for the unique MAC address */ 1064 #define XMAC_UNIQUE_HOST_INFO_ENTRY 17 1065 #define BMAC_UNIQUE_HOST_INFO_ENTRY 0 1066 1067 /* HostInfo entry for the multicat address */ 1068 #define XMAC_MULTI_HOST_INFO_ENTRY 16 1069 #define BMAC_MULTI_HOST_INFO_ENTRY 8 1070 1071 /* XMAC Host Info Register */ 1072 typedef union hostinfo { 1073 1074 uint64_t value; 1075 1076 struct { 1077 #if defined(_BIG_ENDIAN) 1078 uint32_t msw; /* Most significant word */ 1079 uint32_t lsw; /* Least significant word */ 1080 #elif defined(_LITTLE_ENDIAN) 1081 uint32_t lsw; /* Least significant word */ 1082 uint32_t msw; /* Most significant word */ 1083 #endif 1084 } val; 1085 struct { 1086 #if defined(_BIG_ENDIAN) 1087 uint32_t w1; 1088 #endif 1089 struct { 1090 #if defined(_BIT_FIELDS_HTOL) 1091 uint32_t reserved2 : 23; 1092 uint32_t mac_pref : 1; 1093 uint32_t reserved1 : 5; 1094 uint32_t rdc_tbl_num : 3; 1095 #elif defined(_BIT_FIELDS_LTOH) 1096 uint32_t rdc_tbl_num : 3; 1097 uint32_t reserved1 : 5; 1098 uint32_t mac_pref : 1; 1099 uint32_t reserved2 : 23; 1100 #endif 1101 } w0; 1102 1103 #if defined(_LITTLE_ENDIAN) 1104 uint32_t w1; 1105 #endif 1106 } bits; 1107 1108 } hostinfo_t; 1109 1110 typedef union hostinfo *hostinfo_pt; 1111 1112 #define XMAC_HI_RDC_TBL_NUM_MASK 0x00000007 1113 #define XMAC_HI_MAC_PREF 0x00000100 1114 1115 #define XMAC_MAX_HOST_INFO_ENTRY 20 /* 20 host entries */ 1116 1117 /* 1118 * ******************** MIF registers ********************************* 1119 */ 1120 1121 /* 1122 * 32-bit register serves as an instruction register when the MIF is 1123 * programmed in frame mode. load this register w/ a valid instruction 1124 * (as per IEEE 802.3u MII spec). poll this register to check for instruction 1125 * execution completion. during a read operation, this register will also 1126 * contain the 16-bit data returned by the transceiver. unless specified 1127 * otherwise, fields are considered "don't care" when polling for 1128 * completion. 1129 */ 1130 1131 #define MIF_FRAME_START_MASK 0xC0000000 /* start of frame mask */ 1132 #define MIF_FRAME_ST_22 0x40000000 /* STart of frame, Cl 22 */ 1133 #define MIF_FRAME_ST_45 0x00000000 /* STart of frame, Cl 45 */ 1134 #define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode */ 1135 #define MIF_FRAME_OP_READ_22 0x20000000 /* read OPcode, Cl 22 */ 1136 #define MIF_FRAME_OP_WRITE_22 0x10000000 /* write OPcode, Cl 22 */ 1137 #define MIF_FRAME_OP_ADDR_45 0x00000000 /* addr of reg to access */ 1138 #define MIF_FRAME_OP_READ_45 0x30000000 /* read OPcode, Cl 45 */ 1139 #define MIF_FRAME_OP_WRITE_45 0x10000000 /* write OPcode, Cl 45 */ 1140 #define MIF_FRAME_OP_P_R_I_A_45 0x10000000 /* post-read-inc-addr */ 1141 #define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address mask */ 1142 #define MIF_FRAME_PHY_ADDR_SHIFT 23 1143 #define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* reg addr in Cl 22 */ 1144 /* dev addr in Cl 45 */ 1145 #define MIF_FRAME_REG_ADDR_SHIFT 18 1146 #define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB. */ 1147 #define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB. */ 1148 #define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload */ 1149 1150 /* Clause 45 frame field values */ 1151 #define FRAME45_ST 0 1152 #define FRAME45_OP_ADDR 0 1153 #define FRAME45_OP_WRITE 1 1154 #define FRAME45_OP_READ_INC 2 1155 #define FRAME45_OP_READ 3 1156 1157 typedef union _mif_frame_t { 1158 1159 uint64_t value; 1160 1161 struct { 1162 #if defined(_BIG_ENDIAN) 1163 uint32_t msw; /* Most significant word */ 1164 uint32_t lsw; /* Least significant word */ 1165 #elif defined(_LITTLE_ENDIAN) 1166 uint32_t lsw; /* Least significant word */ 1167 uint32_t msw; /* Most significant word */ 1168 #endif 1169 } val; 1170 struct { 1171 #if defined(_BIG_ENDIAN) 1172 uint32_t w1; 1173 #endif 1174 struct { 1175 #if defined(_BIT_FIELDS_HTOL) 1176 uint32_t st : 2; 1177 uint32_t op : 2; 1178 uint32_t phyad : 5; 1179 uint32_t regad : 5; 1180 uint32_t ta_msb : 1; 1181 uint32_t ta_lsb : 1; 1182 uint32_t data : 16; 1183 #elif defined(_BIT_FIELDS_LTOH) 1184 uint32_t data : 16; 1185 uint32_t ta_lsb : 1; 1186 uint32_t ta_msb : 1; 1187 uint32_t regad : 5; 1188 uint32_t phyad : 5; 1189 uint32_t op : 2; 1190 uint32_t st : 2; 1191 #endif 1192 } w0; 1193 1194 #if defined(_LITTLE_ENDIAN) 1195 uint32_t w1; 1196 #endif 1197 } bits; 1198 } mif_frame_t; 1199 1200 #define MIF_CFG_POLL_EN 0x00000008 /* enable polling */ 1201 #define MIF_CFG_BB_MODE 0x00000010 /* bit-bang mode */ 1202 #define MIF_CFG_POLL_REG_MASK 0x000003E0 /* reg addr to be polled */ 1203 #define MIF_CFG_POLL_REG_SHIFT 5 1204 #define MIF_CFG_POLL_PHY_MASK 0x00007C00 /* XCVR addr to be polled */ 1205 #define MIF_CFG_POLL_PHY_SHIFT 10 1206 #define MIF_CFG_INDIRECT_MODE 0x0000800 1207 /* used to decide if Cl 22 */ 1208 /* or Cl 45 frame is */ 1209 /* constructed. */ 1210 /* 1 = Clause 45,ST = '00' */ 1211 /* 0 = Clause 22,ST = '01' */ 1212 #define MIF_CFG_ATCE_GE_EN 0x00010000 /* Enable ATCA gigabit mode */ 1213 1214 typedef union _mif_cfg_t { 1215 1216 uint64_t value; 1217 1218 struct { 1219 #if defined(_BIG_ENDIAN) 1220 uint32_t msw; /* Most significant word */ 1221 uint32_t lsw; /* Least significant word */ 1222 1223 #elif defined(_LITTLE_ENDIAN) 1224 uint32_t lsw; /* Least significant word */ 1225 uint32_t msw; /* Most significant word */ 1226 #endif 1227 } val; 1228 struct { 1229 #if defined(_BIG_ENDIAN) 1230 uint32_t w1; 1231 #endif 1232 struct { 1233 #if defined(_BIT_FIELDS_HTOL) 1234 uint32_t res2 : 15; 1235 uint32_t atca_ge : 1; 1236 uint32_t indirect_md : 1; 1237 uint32_t phy_addr : 5; 1238 uint32_t reg_addr : 5; 1239 uint32_t bb_mode : 1; 1240 uint32_t poll_en : 1; 1241 uint32_t res1 : 2; 1242 uint32_t res : 1; 1243 #elif defined(_BIT_FIELDS_LTOH) 1244 uint32_t res : 1; 1245 uint32_t res1 : 2; 1246 uint32_t poll_en : 1; 1247 uint32_t bb_mode : 1; 1248 uint32_t reg_addr : 5; 1249 uint32_t phy_addr : 5; 1250 uint32_t indirect_md : 1; 1251 uint32_t atca_ge : 1; 1252 uint32_t res2 : 15; 1253 #endif 1254 } w0; 1255 1256 #if defined(_LITTLE_ENDIAN) 1257 uint32_t w1; 1258 #endif 1259 } bits; 1260 1261 } mif_cfg_t; 1262 1263 #define MIF_POLL_STATUS_DATA_MASK 0xffff0000 1264 #define MIF_POLL_STATUS_STAT_MASK 0x0000ffff 1265 1266 typedef union _mif_poll_stat_t { 1267 uint64_t value; 1268 1269 struct { 1270 #if defined(_BIG_ENDIAN) 1271 uint32_t msw; /* Most significant word */ 1272 uint32_t lsw; /* Least significant word */ 1273 #elif defined(_LITTLE_ENDIAN) 1274 uint32_t lsw; /* Least significant word */ 1275 uint32_t msw; /* Most significant word */ 1276 #endif 1277 } val; 1278 struct { 1279 #if defined(_BIG_ENDIAN) 1280 uint32_t w1; 1281 #endif 1282 struct { 1283 #if defined(_BIT_FIELDS_HTOL) 1284 uint16_t data; 1285 uint16_t status; 1286 #elif defined(_BIT_FIELDS_LTOH) 1287 uint16_t status; 1288 uint16_t data; 1289 #endif 1290 } w0; 1291 1292 #if defined(_LITTLE_ENDIAN) 1293 uint32_t w1; 1294 #endif 1295 } bits; 1296 } mif_poll_stat_t; 1297 1298 1299 #define MIF_POLL_MASK_MASK 0x0000ffff 1300 1301 typedef union _mif_poll_mask_t { 1302 uint64_t value; 1303 1304 struct { 1305 #if defined(_BIG_ENDIAN) 1306 uint32_t msw; /* Most significant word */ 1307 uint32_t lsw; /* Least significant word */ 1308 #elif defined(_LITTLE_ENDIAN) 1309 uint32_t lsw; /* Least significant word */ 1310 uint32_t msw; /* Most significant word */ 1311 #endif 1312 } val; 1313 struct { 1314 #if defined(_BIG_ENDIAN) 1315 uint32_t w1; 1316 #endif 1317 struct { 1318 #if defined(_BIT_FIELDS_HTOL) 1319 uint16_t rsvd; 1320 uint16_t mask; 1321 #elif defined(_BIT_FIELDS_LTOH) 1322 uint16_t mask; 1323 uint16_t rsvd; 1324 #endif 1325 } w0; 1326 1327 #if defined(_LITTLE_ENDIAN) 1328 uint32_t w1; 1329 #endif 1330 } bits; 1331 } mif_poll_mask_t; 1332 1333 #define MIF_STATUS_INIT_DONE_MASK 0x00000001 1334 #define MIF_STATUS_XGE_ERR0_MASK 0x00000002 1335 #define MIF_STATUS_XGE_ERR1_MASK 0x00000004 1336 #define MIF_STATUS_PEU_ERR_MASK 0x00000008 1337 #define MIF_STATUS_EXT_PHY_INTR0_MASK 0x00000010 1338 #define MIF_STATUS_EXT_PHY_INTR1_MASK 0x00000020 1339 1340 typedef union _mif_stat_t { 1341 uint64_t value; 1342 1343 struct { 1344 #if defined(_BIG_ENDIAN) 1345 uint32_t msw; /* Most significant word */ 1346 uint32_t lsw; /* Least significant word */ 1347 #elif defined(_LITTLE_ENDIAN) 1348 uint32_t lsw; /* Least significant word */ 1349 uint32_t msw; /* Most significant word */ 1350 #endif 1351 } val; 1352 struct { 1353 #if defined(_BIG_ENDIAN) 1354 uint32_t w1; 1355 #endif 1356 struct { 1357 #if defined(_BIT_FIELDS_HTOL) 1358 uint32_t rsvd:26; 1359 uint32_t ext_phy_intr_flag1:1; 1360 uint32_t ext_phy_intr_flag0:1; 1361 uint32_t peu_err:1; 1362 uint32_t xge_err1:1; 1363 uint32_t xge_err0:1; 1364 uint32_t mif_init_done_stat:1; 1365 1366 #elif defined(_BIT_FIELDS_LTOH) 1367 uint32_t mif_init_done_stat:1; 1368 uint32_t xge_err0:1; 1369 uint32_t xge_err1:1; 1370 uint32_t ext_phy_intr_flag0:1; 1371 uint32_t ext_phy_intr_flag1:1; 1372 uint32_t rsvd:26; 1373 #endif 1374 } w0; 1375 1376 #if defined(_LITTLE_ENDIAN) 1377 uint32_t w1; 1378 #endif 1379 } bits; 1380 } mif_stat_t; 1381 1382 /* MIF State Machine Register */ 1383 1384 #define MIF_SM_EXECUTION_MASK 0x0000003f /* execution state */ 1385 #define MIF_SM_EXECUTION_SHIFT 0 1386 #define MIF_SM_CONTROL_MASK 0x000001c0 /* control state */ 1387 #define MIF_SM_CONTROL_MASK_SHIFT 6 1388 #define MIF_SM_MDI 0x00000200 1389 #define MIF_SM_MDO 0x00000400 1390 #define MIF_SM_MDO_EN 0x00000800 1391 #define MIF_SM_MDC 0x00001000 1392 #define MIF_SM_MDI_0 0x00002000 1393 #define MIF_SM_MDI_1 0x00004000 1394 #define MIF_SM_MDI_2 0x00008000 1395 #define MIF_SM_PORT_ADDR_MASK 0x001f0000 1396 #define MIF_SM_PORT_ADDR_SHIFT 16 1397 #define MIF_SM_INT_SIG_MASK 0xffe00000 1398 #define MIF_SM_INT_SIG_SHIFT 21 1399 1400 1401 /* 1402 * ******************** PCS registers ********************************* 1403 */ 1404 1405 /* PCS Registers */ 1406 #define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on wr */ 1407 #define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal */ 1408 #define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. */ 1409 #define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing. */ 1410 #define PCS_MII_ISOLATE 0x0400 /* read 0. ignored on wr */ 1411 #define PCS_MII_POWER_DOWN 0x0800 /* read 0. ignored on wr */ 1412 #define PCS_MII_AUTONEG_EN 0x1000 /* autonegotiation */ 1413 #define PCS_MII_10_100_SEL 0x2000 /* read 0. ignored on wr */ 1414 #define PCS_MII_RESET 0x8000 /* reset PCS. */ 1415 1416 typedef union _pcs_ctrl_t { 1417 uint64_t value; 1418 1419 struct { 1420 #if defined(_BIG_ENDIAN) 1421 uint32_t msw; /* Most significant word */ 1422 uint32_t lsw; /* Least significant word */ 1423 #elif defined(_LITTLE_ENDIAN) 1424 uint32_t lsw; /* Least significant word */ 1425 uint32_t msw; /* Most significant word */ 1426 #endif 1427 } val; 1428 struct { 1429 #if defined(_BIG_ENDIAN) 1430 uint32_t w1; 1431 #endif 1432 struct { 1433 #if defined(_BIT_FIELDS_HTOL) 1434 uint32_t res0 : 16; 1435 uint32_t reset : 1; 1436 uint32_t res1 : 1; 1437 uint32_t sel_10_100 : 1; 1438 uint32_t an_enable : 1; 1439 uint32_t pwr_down : 1; 1440 uint32_t isolate : 1; 1441 uint32_t restart_an : 1; 1442 uint32_t duplex : 1; 1443 uint32_t col_test : 1; 1444 uint32_t sel_1000 : 1; 1445 uint32_t res2 : 6; 1446 #elif defined(_BIT_FIELDS_LTOH) 1447 uint32_t res2 : 6; 1448 uint32_t sel_1000 : 1; 1449 uint32_t col_test : 1; 1450 uint32_t duplex : 1; 1451 uint32_t restart_an : 1; 1452 uint32_t isolate : 1; 1453 uint32_t pwr_down : 1; 1454 uint32_t an_enable : 1; 1455 uint32_t sel_10_100 : 1; 1456 uint32_t res1 : 1; 1457 uint32_t reset : 1; 1458 uint32_t res0 : 16; 1459 #endif 1460 } w0; 1461 1462 #if defined(_LITTLE_ENDIAN) 1463 uint32_t w1; 1464 #endif 1465 } bits; 1466 } pcs_ctrl_t; 1467 1468 #define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */ 1469 #define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */ 1470 #define PCS_MII_STATUS_LINK_STATUS 0x0004 /* link status */ 1471 #define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 */ 1472 #define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* remote fault detected */ 1473 #define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* auto-neg completed */ 1474 #define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* 1000 Base-X PHY */ 1475 1476 typedef union _pcs_stat_t { 1477 uint64_t value; 1478 1479 struct { 1480 #if defined(_BIG_ENDIAN) 1481 uint32_t msw; /* Most significant word */ 1482 uint32_t lsw; /* Least significant word */ 1483 #elif defined(_LITTLE_ENDIAN) 1484 uint32_t lsw; /* Least significant word */ 1485 uint32_t msw; /* Most significant word */ 1486 #endif 1487 } val; 1488 struct { 1489 #if defined(_BIG_ENDIAN) 1490 uint32_t w1; 1491 #endif 1492 struct { 1493 #if defined(_BIT_FIELDS_HTOL) 1494 uint32_t res0 : 23; 1495 uint32_t ext_stat : 1; 1496 uint32_t res1 : 2; 1497 uint32_t an_complete : 1; 1498 uint32_t remote_fault : 1; 1499 uint32_t an_able : 1; 1500 uint32_t link_stat : 1; 1501 uint32_t jabber_detect : 1; 1502 uint32_t ext_cap : 1; 1503 #elif defined(_BIT_FIELDS_LTOH) 1504 uint32_t ext_cap : 1; 1505 uint32_t jabber_detect : 1; 1506 uint32_t link_stat : 1; 1507 uint32_t an_able : 1; 1508 uint32_t remote_fault : 1; 1509 uint32_t an_complete : 1; 1510 uint32_t res1 : 2; 1511 uint32_t ext_stat : 1; 1512 uint32_t res0 : 23; 1513 #endif 1514 } w0; 1515 1516 #if defined(_LITTLE_ENDIAN) 1517 uint32_t w1; 1518 #endif 1519 } bits; 1520 } pcs_stat_t; 1521 1522 #define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex */ 1523 #define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex */ 1524 #define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE sym */ 1525 #define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE asym */ 1526 #define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault */ 1527 #define PCS_MII_ADVERT_RF_SHIFT 12 1528 #define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */ 1529 #define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */ 1530 1531 #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD 1532 #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD 1533 #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE 1534 #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE 1535 #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK 1536 #define PCS_MII_LPA_RF_SHIFT PCS_MII_ADVERT_RF_SHIFT 1537 #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK 1538 #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE 1539 1540 typedef union _pcs_anar_t { 1541 uint64_t value; 1542 1543 struct { 1544 #if defined(_BIG_ENDIAN) 1545 uint32_t msw; /* Most significant word */ 1546 uint32_t lsw; /* Least significant word */ 1547 #elif defined(_LITTLE_ENDIAN) 1548 uint32_t lsw; /* Least significant word */ 1549 uint32_t msw; /* Most significant word */ 1550 #endif 1551 } val; 1552 struct { 1553 #if defined(_BIG_ENDIAN) 1554 uint32_t w1; 1555 #endif 1556 struct { 1557 #if defined(_BIT_FIELDS_HTOL) 1558 uint32_t res0 : 16; 1559 uint32_t next_page : 1; 1560 uint32_t ack : 1; 1561 uint32_t remote_fault : 2; 1562 uint32_t res1 : 3; 1563 uint32_t asm_pause : 1; 1564 uint32_t pause : 1; 1565 uint32_t half_duplex : 1; 1566 uint32_t full_duplex : 1; 1567 uint32_t res2 : 5; 1568 #elif defined(_BIT_FIELDS_LTOH) 1569 uint32_t res2 : 5; 1570 uint32_t full_duplex : 1; 1571 uint32_t half_duplex : 1; 1572 uint32_t pause : 1; 1573 uint32_t asm_pause : 1; 1574 uint32_t res1 : 3; 1575 uint32_t remore_fault : 2; 1576 uint32_t ack : 1; 1577 uint32_t next_page : 1; 1578 uint32_t res0 : 16; 1579 #endif 1580 } w0; 1581 1582 #if defined(_LITTLE_ENDIAN) 1583 uint32_t w1; 1584 #endif 1585 } bits; 1586 } pcs_anar_t, *p_pcs_anar_t; 1587 1588 #define PCS_CFG_EN 0x0001 /* enable PCS. */ 1589 #define PCS_CFG_SD_OVERRIDE 0x0002 1590 #define PCS_CFG_SD_ACTIVE_LOW 0x0004 /* sig detect active low */ 1591 #define PCS_CFG_JITTER_STUDY_MASK 0x0018 /* jitter measurements */ 1592 #define PCS_CFG_JITTER_STUDY_SHIFT 4 1593 #define PCS_CFG_10MS_TIMER_OVERRIDE 0x0020 /* shortens autoneg timer */ 1594 #define PCS_CFG_MASK 0x0040 /* PCS global mask bit */ 1595 1596 typedef union _pcs_cfg_t { 1597 uint64_t value; 1598 1599 struct { 1600 #if defined(_BIG_ENDIAN) 1601 uint32_t msw; /* Most significant word */ 1602 uint32_t lsw; /* Least significant word */ 1603 #elif defined(_LITTLE_ENDIAN) 1604 uint32_t lsw; /* Least significant word */ 1605 uint32_t msw; /* Most significant word */ 1606 #endif 1607 } val; 1608 struct { 1609 #if defined(_BIG_ENDIAN) 1610 uint32_t w1; 1611 #endif 1612 struct { 1613 #if defined(_BIT_FIELDS_HTOL) 1614 uint32_t res0 : 25; 1615 uint32_t mask : 1; 1616 uint32_t override_10ms_timer : 1; 1617 uint32_t jitter_study : 2; 1618 uint32_t sig_det_a_low : 1; 1619 uint32_t sig_det_override : 1; 1620 uint32_t enable : 1; 1621 #elif defined(_BIT_FIELDS_LTOH) 1622 uint32_t enable : 1; 1623 uint32_t sig_det_override : 1; 1624 uint32_t sig_det_a_low : 1; 1625 uint32_t jitter_study : 2; 1626 uint32_t override_10ms_timer : 1; 1627 uint32_t mask : 1; 1628 uint32_t res0 : 25; 1629 #endif 1630 } w0; 1631 1632 #if defined(_LITTLE_ENDIAN) 1633 uint32_t w1; 1634 #endif 1635 } bits; 1636 } pcs_cfg_t, *p_pcs_cfg_t; 1637 1638 1639 /* used for diagnostic purposes. bits 20-22 autoclear on read */ 1640 #define PCS_SM_TX_STATE_MASK 0x0000000F /* Tx idle state mask */ 1641 #define PCS_SM_TX_STATE_SHIFT 0 1642 #define PCS_SM_RX_STATE_MASK 0x000000F0 /* Rx idle state mask */ 1643 #define PCS_SM_RX_STATE_SHIFT 4 1644 #define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* loss of sync state mask */ 1645 #define PCS_SM_WORD_SYNC_STATE_SHIFT 8 1646 #define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* sequence detect */ 1647 #define PCS_SM_SEQ_DETECT_STATE_SHIFT 11 1648 #define PCS_SM_LINK_STATE_MASK 0x0001E000 /* link state */ 1649 #define PCS_SM_LINK_STATE_SHIFT 13 1650 #define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link */ 1651 #define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of sync */ 1652 #define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect fail */ 1653 #define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* receipt of breaklink */ 1654 #define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes initializing */ 1655 #define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable */ 1656 #define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not achieved */ 1657 #define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes */ 1658 #define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* linkpartner send C code */ 1659 1660 typedef union _pcs_stat_mc_t { 1661 uint64_t value; 1662 1663 struct { 1664 #if defined(_BIG_ENDIAN) 1665 uint32_t msw; /* Most significant word */ 1666 uint32_t lsw; /* Least significant word */ 1667 #elif defined(_LITTLE_ENDIAN) 1668 uint32_t lsw; /* Least significant word */ 1669 uint32_t msw; /* Most significant word */ 1670 #endif 1671 } val; 1672 struct { 1673 #if defined(_BIG_ENDIAN) 1674 uint32_t w1; 1675 #endif 1676 struct { 1677 #if defined(_BIT_FIELDS_HTOL) 1678 uint32_t res2 : 2; 1679 uint32_t lnk_dwn_ni : 1; 1680 uint32_t lnk_dwn_wc : 1; 1681 uint32_t lnk_dwn_ls : 1; 1682 uint32_t lnk_dwn_nc : 1; 1683 uint32_t lnk_dwn_ser : 1; 1684 uint32_t lnk_loss_bc : 1; 1685 uint32_t res1 : 1; 1686 uint32_t loss_sd : 1; 1687 uint32_t lnk_loss_sync : 1; 1688 uint32_t lnk_loss_c : 1; 1689 uint32_t res0 : 3; 1690 uint32_t link_cfg_stat : 4; 1691 uint32_t seq_detc_stat : 2; 1692 uint32_t word_sync : 3; 1693 uint32_t rx_ctrl : 4; 1694 uint32_t tx_ctrl : 4; 1695 #elif defined(_BIT_FIELDS_LTOH) 1696 uint32_t tx_ctrl : 4; 1697 uint32_t rx_ctrl : 4; 1698 uint32_t word_sync : 3; 1699 uint32_t seq_detc_stat : 2; 1700 uint32_t link_cfg_stat : 4; 1701 uint32_t res0 : 3; 1702 uint32_t lnk_loss_c : 1; 1703 uint32_t lnk_loss_sync : 1; 1704 uint32_t loss_sd : 1; 1705 uint32_t res1 : 1; 1706 uint32_t lnk_loss_bc : 1; 1707 uint32_t lnk_dwn_ser : 1; 1708 uint32_t lnk_dwn_nc : 1; 1709 uint32_t lnk_dwn_ls : 1; 1710 uint32_t lnk_dwn_wc : 1; 1711 uint32_t lnk_dwn_ni : 1; 1712 uint32_t res2 : 2; 1713 #endif 1714 } w0; 1715 1716 #if defined(_LITTLE_ENDIAN) 1717 uint32_t w1; 1718 #endif 1719 } bits; 1720 } pcs_stat_mc_t, *p_pcs_stat_mc_t; 1721 1722 #define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed */ 1723 1724 /* 1725 * control which network interface is used. no more than one bit should 1726 * be set. 1727 */ 1728 #define PCS_DATAPATH_MODE_PCS 0 /* Internal PCS is used */ 1729 #define PCS_DATAPATH_MODE_MII 0x00000002 /* GMII/RGMII is selected. */ 1730 1731 #define PCS_PACKET_COUNT_TX_MASK 0x000007FF /* pkts xmitted by PCS */ 1732 #define PCS_PACKET_COUNT_RX_MASK 0x07FF0000 /* pkts recvd by PCS */ 1733 #define PCS_PACKET_COUNT_RX_SHIFT 16 1734 1735 /* 1736 * ******************** XPCS registers ********************************* 1737 */ 1738 1739 /* XPCS Base 10G Control1 Register */ 1740 #define XPCS_CTRL1_RST 0x8000 /* Self clearing reset. */ 1741 #define XPCS_CTRL1_LOOPBK 0x4000 /* xpcs Loopback */ 1742 #define XPCS_CTRL1_SPEED_SEL_3 0x2000 /* 1 indicates 10G speed */ 1743 #define XPCS_CTRL1_LOW_PWR 0x0800 /* low power mode. */ 1744 #define XPCS_CTRL1_SPEED_SEL_1 0x0040 /* 1 indicates 10G speed */ 1745 #define XPCS_CTRL1_SPEED_SEL_0_MASK 0x003c /* 0 indicates 10G speed. */ 1746 #define XPCS_CTRL1_SPEED_SEL_0_SHIFT 2 1747 1748 1749 1750 typedef union _xpcs_ctrl1_t { 1751 uint64_t value; 1752 1753 struct { 1754 #if defined(_BIG_ENDIAN) 1755 uint32_t msw; /* Most significant word */ 1756 uint32_t lsw; /* Least significant word */ 1757 #elif defined(_LITTLE_ENDIAN) 1758 uint32_t lsw; /* Least significant word */ 1759 uint32_t msw; /* Most significant word */ 1760 #endif 1761 } val; 1762 struct { 1763 #if defined(_BIG_ENDIAN) 1764 uint32_t w1; 1765 #endif 1766 struct { 1767 #if defined(_BIT_FIELDS_HTOL) 1768 uint32_t res3 : 16; 1769 uint32_t reset : 1; 1770 uint32_t csr_lb : 1; 1771 uint32_t csr_speed_sel3 : 1; 1772 uint32_t res2 : 1; 1773 uint32_t csr_low_pwr : 1; 1774 uint32_t res1 : 4; 1775 uint32_t csr_speed_sel1 : 1; 1776 uint32_t csr_speed_sel0 : 4; 1777 uint32_t res0 : 2; 1778 #elif defined(_BIT_FIELDS_LTOH) 1779 uint32_t res0 : 2; 1780 uint32_t csr_speed_sel0 : 4; 1781 uint32_t csr_speed_sel1 : 1; 1782 uint32_t res1 : 4; 1783 uint32_t csr_low_pwr : 1; 1784 uint32_t res2 : 1; 1785 uint32_t csr_speed_sel3 : 1; 1786 uint32_t csr_lb : 1; 1787 uint32_t reset : 1; 1788 uint32_t res3 : 16; 1789 #endif 1790 } w0; 1791 1792 #if defined(_LITTLE_ENDIAN) 1793 uint32_t w1; 1794 #endif 1795 } bits; 1796 } xpcs_ctrl1_t; 1797 1798 1799 /* XPCS Base 10G Status1 Register (Read Only) */ 1800 #define XPCS_STATUS1_FAULT 0x0080 1801 #define XPCS_STATUS1_RX_LINK_STATUS_UP 0x0004 /* Link status interrupt */ 1802 #define XPCS_STATUS1_LOW_POWER_ABILITY 0x0002 /* low power mode */ 1803 1804 1805 typedef union _xpcs_stat1_t { 1806 uint64_t value; 1807 1808 struct { 1809 #if defined(_BIG_ENDIAN) 1810 uint32_t msw; /* Most significant word */ 1811 uint32_t lsw; /* Least significant word */ 1812 #elif defined(_LITTLE_ENDIAN) 1813 uint32_t lsw; /* Least significant word */ 1814 uint32_t msw; /* Most significant word */ 1815 #endif 1816 } val; 1817 struct { 1818 #if defined(_BIG_ENDIAN) 1819 uint32_t w1; 1820 #endif 1821 struct { 1822 #if defined(_BIT_FIELDS_HTOL) 1823 uint32_t res4 : 16; 1824 uint32_t res3 : 8; 1825 uint32_t csr_fault : 1; 1826 uint32_t res1 : 4; 1827 uint32_t csr_rx_link_stat : 1; 1828 uint32_t csr_low_pwr_ability : 1; 1829 uint32_t res0 : 1; 1830 #elif defined(_BIT_FIELDS_LTOH) 1831 uint32_t res0 : 1; 1832 uint32_t csr_low_pwr_ability : 1; 1833 uint32_t csr_rx_link_stat : 1; 1834 uint32_t res1 : 4; 1835 uint32_t csr_fault : 1; 1836 uint32_t res3 : 8; 1837 uint32_t res4 : 16; 1838 #endif 1839 } w0; 1840 1841 #if defined(_LITTLE_ENDIAN) 1842 uint32_t w1; 1843 #endif 1844 } bits; 1845 } xpcs_stat1_t; 1846 1847 1848 /* XPCS Base Speed Ability Register. Indicates 10G capability */ 1849 #define XPCS_SPEED_ABILITY_10_GIG 0x0001 1850 1851 1852 typedef union _xpcs_speed_ab_t { 1853 uint64_t value; 1854 1855 struct { 1856 #if defined(_BIG_ENDIAN) 1857 uint32_t msw; /* Most significant word */ 1858 uint32_t lsw; /* Least significant word */ 1859 #elif defined(_LITTLE_ENDIAN) 1860 uint32_t lsw; /* Least significant word */ 1861 uint32_t msw; /* Most significant word */ 1862 #endif 1863 } val; 1864 struct { 1865 #if defined(_BIG_ENDIAN) 1866 uint32_t w1; 1867 #endif 1868 struct { 1869 #if defined(_BIT_FIELDS_HTOL) 1870 uint32_t res1 : 16; 1871 uint32_t res0 : 15; 1872 uint32_t csr_10gig : 1; 1873 #elif defined(_BIT_FIELDS_LTOH) 1874 uint32_t csr_10gig : 1; 1875 uint32_t res0 : 15; 1876 uint32_t res1 : 16; 1877 #endif 1878 } w0; 1879 1880 #if defined(_LITTLE_ENDIAN) 1881 uint32_t w1; 1882 #endif 1883 } bits; 1884 } xpcs_speed_ab_t; 1885 1886 1887 /* XPCS Base 10G Devices in Package Register */ 1888 #define XPCS_DEV_IN_PKG_CSR_VENDOR2 0x80000000 1889 #define XPCS_DEV_IN_PKG_CSR_VENDOR1 0x40000000 1890 #define XPCS_DEV_IN_PKG_DTE_XS 0x00000020 1891 #define XPCS_DEV_IN_PKG_PHY_XS 0x00000010 1892 #define XPCS_DEV_IN_PKG_PCS 0x00000008 1893 #define XPCS_DEV_IN_PKG_WIS 0x00000004 1894 #define XPCS_DEV_IN_PKG_PMD_PMA 0x00000002 1895 #define XPCS_DEV_IN_PKG_CLS_22_REG 0x00000000 1896 1897 1898 1899 typedef union _xpcs_dev_in_pkg_t { 1900 uint64_t value; 1901 1902 struct { 1903 #if defined(_BIG_ENDIAN) 1904 uint32_t msw; /* Most significant word */ 1905 uint32_t lsw; /* Least significant word */ 1906 #elif defined(_LITTLE_ENDIAN) 1907 uint32_t lsw; /* Least significant word */ 1908 uint32_t msw; /* Most significant word */ 1909 #endif 1910 } val; 1911 struct { 1912 #if defined(_BIG_ENDIAN) 1913 uint32_t w1; 1914 #endif 1915 struct { 1916 #if defined(_BIT_FIELDS_HTOL) 1917 uint32_t csr_vendor2 : 1; 1918 uint32_t csr_vendor1 : 1; 1919 uint32_t res1 : 14; 1920 uint32_t res0 : 10; 1921 uint32_t dte_xs : 1; 1922 uint32_t phy_xs : 1; 1923 uint32_t pcs : 1; 1924 uint32_t wis : 1; 1925 uint32_t pmd_pma : 1; 1926 uint32_t clause_22_reg : 1; 1927 #elif defined(_BIT_FIELDS_LTOH) 1928 uint32_t clause_22_reg : 1; 1929 uint32_t pmd_pma : 1; 1930 uint32_t wis : 1; 1931 uint32_t pcs : 1; 1932 uint32_t phy_xs : 1; 1933 uint32_t dte_xs : 1; 1934 uint32_t res0 : 10; 1935 uint32_t res1 : 14; 1936 uint32_t csr_vendor1 : 1; 1937 uint32_t csr_vendor2 : 1; 1938 #endif 1939 } w0; 1940 1941 #if defined(_LITTLE_ENDIAN) 1942 uint32_t w1; 1943 #endif 1944 } bits; 1945 } xpcs_dev_in_pkg_t; 1946 1947 1948 /* XPCS Base 10G Control2 Register */ 1949 #define XPCS_PSC_SEL_MASK 0x0003 1950 #define PSC_SEL_10G_BASE_X_PCS 0x0001 1951 1952 1953 typedef union _xpcs_ctrl2_t { 1954 uint64_t value; 1955 1956 struct { 1957 #if defined(_BIG_ENDIAN) 1958 uint32_t msw; /* Most significant word */ 1959 uint32_t lsw; /* Least significant word */ 1960 #elif defined(_LITTLE_ENDIAN) 1961 uint32_t lsw; /* Least significant word */ 1962 uint32_t msw; /* Most significant word */ 1963 #endif 1964 } val; 1965 struct { 1966 #if defined(_BIG_ENDIAN) 1967 uint32_t w1; 1968 #endif 1969 struct { 1970 #if defined(_BIT_FIELDS_HTOL) 1971 uint32_t res1 : 16; 1972 uint32_t res0 : 14; 1973 uint32_t csr_psc_sel : 2; 1974 #elif defined(_BIT_FIELDS_LTOH) 1975 uint32_t csr_psc_sel : 2; 1976 uint32_t res0 : 14; 1977 uint32_t res1 : 16; 1978 #endif 1979 } w0; 1980 1981 #if defined(_LITTLE_ENDIAN) 1982 uint32_t w1; 1983 #endif 1984 } bits; 1985 } xpcs_ctrl2_t; 1986 1987 1988 /* XPCS Base10G Status2 Register */ 1989 #define XPCS_STATUS2_DEV_PRESENT_MASK 0xc000 /* ?????? */ 1990 #define XPCS_STATUS2_TX_FAULT 0x0800 /* Fault on tx path */ 1991 #define XPCS_STATUS2_RX_FAULT 0x0400 /* Fault on rx path */ 1992 #define XPCS_STATUS2_TEN_GBASE_W 0x0004 /* 10G-Base-W */ 1993 #define XPCS_STATUS2_TEN_GBASE_X 0x0002 /* 10G-Base-X */ 1994 #define XPCS_STATUS2_TEN_GBASE_R 0x0001 /* 10G-Base-R */ 1995 1996 typedef union _xpcs_stat2_t { 1997 uint64_t value; 1998 1999 struct { 2000 #if defined(_BIG_ENDIAN) 2001 uint32_t msw; /* Most significant word */ 2002 uint32_t lsw; /* Least significant word */ 2003 #elif defined(_LITTLE_ENDIAN) 2004 uint32_t lsw; /* Least significant word */ 2005 uint32_t msw; /* Most significant word */ 2006 #endif 2007 } val; 2008 struct { 2009 #if defined(_BIG_ENDIAN) 2010 uint32_t w1; 2011 #endif 2012 struct { 2013 #if defined(_BIT_FIELDS_HTOL) 2014 uint32_t res2 : 16; 2015 uint32_t csr_dev_pres : 2; 2016 uint32_t res1 : 2; 2017 uint32_t csr_tx_fault : 1; 2018 uint32_t csr_rx_fault : 1; 2019 uint32_t res0 : 7; 2020 uint32_t ten_gbase_w : 1; 2021 uint32_t ten_gbase_x : 1; 2022 uint32_t ten_gbase_r : 1; 2023 #elif defined(_BIT_FIELDS_LTOH) 2024 uint32_t ten_gbase_r : 1; 2025 uint32_t ten_gbase_x : 1; 2026 uint32_t ten_gbase_w : 1; 2027 uint32_t res0 : 7; 2028 uint32_t csr_rx_fault : 1; 2029 uint32_t csr_tx_fault : 1; 2030 uint32_t res1 : 2; 2031 uint32_t csr_dev_pres : 2; 2032 uint32_t res2 : 16; 2033 #endif 2034 } w0; 2035 2036 #if defined(_LITTLE_ENDIAN) 2037 uint32_t w1; 2038 #endif 2039 } bits; 2040 } xpcs_stat2_t; 2041 2042 2043 2044 /* XPCS Base10G Status Register */ 2045 #define XPCS_STATUS_LANE_ALIGN 0x1000 /* 10GBaseX PCS rx lanes align */ 2046 #define XPCS_STATUS_PATTERN_TEST_ABLE 0x0800 /* able to generate patterns. */ 2047 #define XPCS_STATUS_LANE3_SYNC 0x0008 /* Lane 3 is synchronized */ 2048 #define XPCS_STATUS_LANE2_SYNC 0x0004 /* Lane 2 is synchronized */ 2049 #define XPCS_STATUS_LANE1_SYNC 0x0002 /* Lane 1 is synchronized */ 2050 #define XPCS_STATUS_LANE0_SYNC 0x0001 /* Lane 0 is synchronized */ 2051 2052 typedef union _xpcs_stat_t { 2053 uint64_t value; 2054 2055 struct { 2056 #if defined(_BIG_ENDIAN) 2057 uint32_t msw; /* Most significant word */ 2058 uint32_t lsw; /* Least significant word */ 2059 #elif defined(_LITTLE_ENDIAN) 2060 uint32_t lsw; /* Least significant word */ 2061 uint32_t msw; /* Most significant word */ 2062 #endif 2063 } val; 2064 struct { 2065 #if defined(_BIG_ENDIAN) 2066 uint32_t w1; 2067 #endif 2068 struct { 2069 #if defined(_BIT_FIELDS_HTOL) 2070 uint32_t res2 : 16; 2071 uint32_t res1 : 3; 2072 uint32_t csr_lane_align : 1; 2073 uint32_t csr_pattern_test_able : 1; 2074 uint32_t res0 : 7; 2075 uint32_t csr_lane3_sync : 1; 2076 uint32_t csr_lane2_sync : 1; 2077 uint32_t csr_lane1_sync : 1; 2078 uint32_t csr_lane0_sync : 1; 2079 #elif defined(_BIT_FIELDS_LTOH) 2080 uint32_t csr_lane0_sync : 1; 2081 uint32_t csr_lane1_sync : 1; 2082 uint32_t csr_lane2_sync : 1; 2083 uint32_t csr_lane3_sync : 1; 2084 uint32_t res0 : 7; 2085 uint32_t csr_pat_test_able : 1; 2086 uint32_t csr_lane_align : 1; 2087 uint32_t res1 : 3; 2088 uint32_t res2 : 16; 2089 #endif 2090 } w0; 2091 2092 #if defined(_LITTLE_ENDIAN) 2093 uint32_t w1; 2094 #endif 2095 } bits; 2096 } xpcs_stat_t; 2097 2098 /* XPCS Base10G Test Control Register */ 2099 #define XPCS_TEST_CTRL_TX_TEST_ENABLE 0x0004 2100 #define XPCS_TEST_CTRL_TEST_PATTERN_SEL_MASK 0x0003 2101 #define TEST_PATTERN_HIGH_FREQ 0 2102 #define TEST_PATTERN_LOW_FREQ 1 2103 #define TEST_PATTERN_MIXED_FREQ 2 2104 2105 typedef union _xpcs_test_ctl_t { 2106 uint64_t value; 2107 2108 struct { 2109 #if defined(_BIG_ENDIAN) 2110 uint32_t msw; /* Most significant word */ 2111 uint32_t lsw; /* Least significant word */ 2112 #elif defined(_LITTLE_ENDIAN) 2113 uint32_t lsw; /* Least significant word */ 2114 uint32_t msw; /* Most significant word */ 2115 #endif 2116 } val; 2117 struct { 2118 #if defined(_BIG_ENDIAN) 2119 uint32_t w1; 2120 #endif 2121 struct { 2122 #if defined(_BIT_FIELDS_HTOL) 2123 uint32_t res1 : 16; 2124 uint32_t res0 : 13; 2125 uint32_t csr_tx_test_en : 1; 2126 uint32_t csr_test_pat_sel : 2; 2127 #elif defined(_BIT_FIELDS_LTOH) 2128 uint32_t csr_test_pat_sel : 2; 2129 uint32_t csr_tx_test_en : 1; 2130 uint32_t res0 : 13; 2131 uint32_t res1 : 16; 2132 #endif 2133 } w0; 2134 2135 #if defined(_LITTLE_ENDIAN) 2136 uint32_t w1; 2137 #endif 2138 } bits; 2139 } xpcs_test_ctl_t; 2140 2141 /* XPCS Base10G Diagnostic Register */ 2142 #define XPCS_DIAG_EB_ALIGN_ERR3 0x40 2143 #define XPCS_DIAG_EB_ALIGN_ERR2 0x20 2144 #define XPCS_DIAG_EB_ALIGN_ERR1 0x10 2145 #define XPCS_DIAG_EB_DESKEW_OK 0x08 2146 #define XPCS_DIAG_EB_ALIGN_DET3 0x04 2147 #define XPCS_DIAG_EB_ALIGN_DET2 0x02 2148 #define XPCS_DIAG_EB_ALIGN_DET1 0x01 2149 #define XPCS_DIAG_EB_DESKEW_LOSS 0 2150 2151 #define XPCS_DIAG_SYNC_3_INVALID 0x8 2152 #define XPCS_DIAG_SYNC_2_INVALID 0x4 2153 #define XPCS_DIAG_SYNC_1_INVALID 0x2 2154 #define XPCS_DIAG_SYNC_IN_SYNC 0x1 2155 #define XPCS_DIAG_SYNC_LOSS_SYNC 0 2156 2157 #define XPCS_RX_SM_RECEIVE_STATE 1 2158 #define XPCS_RX_SM_FAULT_STATE 0 2159 2160 typedef union _xpcs_diag_t { 2161 uint64_t value; 2162 2163 struct { 2164 #if defined(_BIG_ENDIAN) 2165 uint32_t msw; /* Most significant word */ 2166 uint32_t lsw; /* Least significant word */ 2167 #elif defined(_LITTLE_ENDIAN) 2168 uint32_t lsw; /* Least significant word */ 2169 uint32_t msw; /* Most significant word */ 2170 #endif 2171 } val; 2172 struct { 2173 #if defined(_BIG_ENDIAN) 2174 uint32_t w1; 2175 #endif 2176 struct { 2177 #if defined(_BIT_FIELDS_HTOL) 2178 uint32_t res1 : 7; 2179 uint32_t sync_sm_lane3 : 4; 2180 uint32_t sync_sm_lane2 : 4; 2181 uint32_t sync_sm_lane1 : 4; 2182 uint32_t sync_sm_lane0 : 4; 2183 uint32_t elastic_buffer_sm : 8; 2184 uint32_t receive_sm : 1; 2185 #elif defined(_BIT_FIELDS_LTOH) 2186 uint32_t receive_sm : 1; 2187 uint32_t elastic_buffer_sm : 8; 2188 uint32_t sync_sm_lane0 : 4; 2189 uint32_t sync_sm_lane1 : 4; 2190 uint32_t sync_sm_lane2 : 4; 2191 uint32_t sync_sm_lane3 : 4; 2192 uint32_t res1 : 7; 2193 #endif 2194 } w0; 2195 2196 #if defined(_LITTLE_ENDIAN) 2197 uint32_t w1; 2198 #endif 2199 } bits; 2200 } xpcs_diag_t; 2201 2202 /* XPCS Base10G Tx State Machine Register */ 2203 #define XPCS_TX_SM_SEND_UNDERRUN 0x9 2204 #define XPCS_TX_SM_SEND_RANDOM_Q 0x8 2205 #define XPCS_TX_SM_SEND_RANDOM_K 0x7 2206 #define XPCS_TX_SM_SEND_RANDOM_A 0x6 2207 #define XPCS_TX_SM_SEND_RANDOM_R 0x5 2208 #define XPCS_TX_SM_SEND_Q 0x4 2209 #define XPCS_TX_SM_SEND_K 0x3 2210 #define XPCS_TX_SM_SEND_A 0x2 2211 #define XPCS_TX_SM_SEND_SDP 0x1 2212 #define XPCS_TX_SM_SEND_DATA 0 2213 2214 /* XPCS Base10G Configuration Register */ 2215 #define XPCS_CFG_VENDOR_DBG_SEL_MASK 0x78 2216 #define XPCS_CFG_VENDOR_DBG_SEL_SHIFT 3 2217 #define XPCS_CFG_BYPASS_SIG_DETECT 0x0004 2218 #define XPCS_CFG_ENABLE_TX_BUFFERS 0x0002 2219 #define XPCS_CFG_XPCS_ENABLE 0x0001 2220 2221 typedef union _xpcs_config_t { 2222 uint64_t value; 2223 2224 struct { 2225 #if defined(_BIG_ENDIAN) 2226 uint32_t msw; /* Most significant word */ 2227 uint32_t lsw; /* Least significant word */ 2228 #elif defined(_LITTLE_ENDIAN) 2229 uint32_t lsw; /* Least significant word */ 2230 uint32_t msw; /* Most significant word */ 2231 #endif 2232 } val; 2233 struct { 2234 #if defined(_BIG_ENDIAN) 2235 uint32_t w1; 2236 #endif 2237 struct { 2238 #if defined(_BIT_FIELDS_HTOL) 2239 uint32_t res1 : 16; 2240 uint32_t res0 : 9; 2241 uint32_t csr_vendor_dbg_sel : 4; 2242 uint32_t csr_bypass_sig_detect : 1; 2243 uint32_t csr_en_tx_buf : 1; 2244 uint32_t csr_xpcs_en : 1; 2245 #elif defined(_BIT_FIELDS_LTOH) 2246 uint32_t csr_xpcs_en : 1; 2247 uint32_t csr_en_tx_buf : 1; 2248 uint32_t csr_bypass_sig_detect : 1; 2249 uint32_t csr_vendor_dbg_sel : 4; 2250 uint32_t res0 : 9; 2251 uint32_t res1 : 16; 2252 #endif 2253 } w0; 2254 2255 #if defined(_LITTLE_ENDIAN) 2256 uint32_t w1; 2257 #endif 2258 } bits; 2259 } xpcs_config_t; 2260 2261 2262 2263 /* XPCS Base10G Mask1 Register */ 2264 #define XPCS_MASK1_FAULT_MASK 0x0080 /* mask fault interrupt. */ 2265 #define XPCS_MASK1_RX_LINK_STATUS_MASK 0x0040 /* mask linkstat interrupt */ 2266 2267 /* XPCS Base10G Packet Counter */ 2268 #define XPCS_PKT_CNTR_TX_PKT_CNT_MASK 0xffff0000 2269 #define XPCS_PKT_CNTR_TX_PKT_CNT_SHIFT 16 2270 #define XPCS_PKT_CNTR_RX_PKT_CNT_MASK 0x0000ffff 2271 #define XPCS_PKT_CNTR_RX_PKT_CNT_SHIFT 0 2272 2273 /* XPCS Base10G TX State Machine status register */ 2274 #define XPCS_TX_STATE_MC_TX_STATE_MASK 0x0f 2275 #define XPCS_DESKEW_ERR_CNTR_MASK 0xff 2276 2277 /* XPCS Base10G Lane symbol error counters */ 2278 #define XPCS_SYM_ERR_CNT_L1_MASK 0xffff0000 2279 #define XPCS_SYM_ERR_CNT_L0_MASK 0x0000ffff 2280 #define XPCS_SYM_ERR_CNT_L3_MASK 0xffff0000 2281 #define XPCS_SYM_ERR_CNT_L2_MASK 0x0000ffff 2282 2283 #define XPCS_SYM_ERR_CNT_MULTIPLIER 16 2284 2285 /* ESR Reset Register */ 2286 #define ESR_RESET_1 2 2287 #define ESR_RESET_0 1 2288 2289 /* ESR Configuration Register */ 2290 #define ESR_BLUNT_END_LOOPBACK 2 2291 #define ESR_FORCE_SERDES_SERDES_RDY 1 2292 2293 /* ESR Neptune Serdes PLL Configuration */ 2294 #define ESR_PLL_CFG_FBDIV_0 0x1 2295 #define ESR_PLL_CFG_FBDIV_1 0x2 2296 #define ESR_PLL_CFG_FBDIV_2 0x4 2297 #define ESR_PLL_CFG_HALF_RATE_0 0x8 2298 #define ESR_PLL_CFG_HALF_RATE_1 0x10 2299 #define ESR_PLL_CFG_HALF_RATE_2 0x20 2300 #define ESR_PLL_CFG_HALF_RATE_3 0x40 2301 2302 /* ESR Neptune Serdes Control Register */ 2303 #define ESR_CTL_EN_SYNCDET_0 0x00000001 2304 #define ESR_CTL_EN_SYNCDET_1 0x00000002 2305 #define ESR_CTL_EN_SYNCDET_2 0x00000004 2306 #define ESR_CTL_EN_SYNCDET_3 0x00000008 2307 #define ESR_CTL_OUT_EMPH_0_MASK 0x00000070 2308 #define ESR_CTL_OUT_EMPH_0_SHIFT 4 2309 #define ESR_CTL_OUT_EMPH_1_MASK 0x00000380 2310 #define ESR_CTL_OUT_EMPH_1_SHIFT 7 2311 #define ESR_CTL_OUT_EMPH_2_MASK 0x00001c00 2312 #define ESR_CTL_OUT_EMPH_2_SHIFT 10 2313 #define ESR_CTL_OUT_EMPH_3_MASK 0x0000e000 2314 #define ESR_CTL_OUT_EMPH_3_SHIFT 13 2315 #define ESR_CTL_LOSADJ_0_MASK 0x00070000 2316 #define ESR_CTL_LOSADJ_0_SHIFT 16 2317 #define ESR_CTL_LOSADJ_1_MASK 0x00380000 2318 #define ESR_CTL_LOSADJ_1_SHIFT 19 2319 #define ESR_CTL_LOSADJ_2_MASK 0x01c00000 2320 #define ESR_CTL_LOSADJ_2_SHIFT 22 2321 #define ESR_CTL_LOSADJ_3_MASK 0x0e000000 2322 #define ESR_CTL_LOSADJ_3_SHIFT 25 2323 #define ESR_CTL_RXITERM_0 0x10000000 2324 #define ESR_CTL_RXITERM_1 0x20000000 2325 #define ESR_CTL_RXITERM_2 0x40000000 2326 #define ESR_CTL_RXITERM_3 0x80000000 2327 2328 /* ESR Neptune Serdes Test Configuration Register */ 2329 #define ESR_TSTCFG_LBTEST_MD_0_MASK 0x00000003 2330 #define ESR_TSTCFG_LBTEST_MD_0_SHIFT 0 2331 #define ESR_TSTCFG_LBTEST_MD_1_MASK 0x0000000c 2332 #define ESR_TSTCFG_LBTEST_MD_1_SHIFT 2 2333 #define ESR_TSTCFG_LBTEST_MD_2_MASK 0x00000030 2334 #define ESR_TSTCFG_LBTEST_MD_2_SHIFT 4 2335 #define ESR_TSTCFG_LBTEST_MD_3_MASK 0x000000c0 2336 #define ESR_TSTCFG_LBTEST_MD_3_SHIFT 6 2337 2338 /* ESR Neptune Ethernet RGMII Configuration Register */ 2339 #define ESR_RGMII_PT0_IN_USE 0x00000001 2340 #define ESR_RGMII_PT1_IN_USE 0x00000002 2341 #define ESR_RGMII_PT2_IN_USE 0x00000004 2342 #define ESR_RGMII_PT3_IN_USE 0x00000008 2343 #define ESR_RGMII_REG_RW_TEST 0x00000010 2344 2345 /* ESR Internal Signals Observation Register */ 2346 #define ESR_SIG_MASK 0xFFFFFFFF 2347 #define ESR_SIG_P0_BITS_MASK 0x33E0000F 2348 #define ESR_SIG_P1_BITS_MASK 0x0C1F00F0 2349 #define ESR_SIG_SERDES_RDY0_P0 0x20000000 2350 #define ESR_SIG_DETECT0_P0 0x10000000 2351 #define ESR_SIG_SERDES_RDY0_P1 0x08000000 2352 #define ESR_SIG_DETECT0_P1 0x04000000 2353 #define ESR_SIG_XSERDES_RDY_P0 0x02000000 2354 #define ESR_SIG_XDETECT_P0_CH3 0x01000000 2355 #define ESR_SIG_XDETECT_P0_CH2 0x00800000 2356 #define ESR_SIG_XDETECT_P0_CH1 0x00400000 2357 #define ESR_SIG_XDETECT_P0_CH0 0x00200000 2358 #define ESR_SIG_XSERDES_RDY_P1 0x00100000 2359 #define ESR_SIG_XDETECT_P1_CH3 0x00080000 2360 #define ESR_SIG_XDETECT_P1_CH2 0x00040000 2361 #define ESR_SIG_XDETECT_P1_CH1 0x00020000 2362 #define ESR_SIG_XDETECT_P1_CH0 0x00010000 2363 #define ESR_SIG_LOS_P1_CH3 0x00000080 2364 #define ESR_SIG_LOS_P1_CH2 0x00000040 2365 #define ESR_SIG_LOS_P1_CH1 0x00000020 2366 #define ESR_SIG_LOS_P1_CH0 0x00000010 2367 #define ESR_SIG_LOS_P0_CH3 0x00000008 2368 #define ESR_SIG_LOS_P0_CH2 0x00000004 2369 #define ESR_SIG_LOS_P0_CH1 0x00000002 2370 #define ESR_SIG_LOS_P0_CH0 0x00000001 2371 2372 /* ESR Debug Selection Register */ 2373 #define ESR_DEBUG_SEL_MASK 0x00000003f 2374 2375 /* ESR Test Configuration Register */ 2376 #define ESR_NO_LOOPBACK_CH3 (0x0 << 6) 2377 #define ESR_EWRAP_CH3 (0x1 << 6) 2378 #define ESR_PAD_LOOPBACK_CH3 (0x2 << 6) 2379 #define ESR_REVLOOPBACK_CH3 (0x3 << 6) 2380 #define ESR_NO_LOOPBACK_CH2 (0x0 << 4) 2381 #define ESR_EWRAP_CH2 (0x1 << 4) 2382 #define ESR_PAD_LOOPBACK_CH2 (0x2 << 4) 2383 #define ESR_REVLOOPBACK_CH2 (0x3 << 4) 2384 #define ESR_NO_LOOPBACK_CH1 (0x0 << 2) 2385 #define ESR_EWRAP_CH1 (0x1 << 2) 2386 #define ESR_PAD_LOOPBACK_CH1 (0x2 << 2) 2387 #define ESR_REVLOOPBACK_CH1 (0x3 << 2) 2388 #define ESR_NO_LOOPBACK_CH0 0x0 2389 #define ESR_EWRAP_CH0 0x1 2390 #define ESR_PAD_LOOPBACK_CH0 0x2 2391 #define ESR_REVLOOPBACK_CH0 0x3 2392 2393 /* convert values */ 2394 #define NXGE_BASE(x, y) \ 2395 (((y) << (x ## _SHIFT)) & (x ## _MASK)) 2396 2397 #define NXGE_VAL_GET(fieldname, regval) \ 2398 (((regval) & ((fieldname) ## _MASK)) >> ((fieldname) ## _SHIFT)) 2399 2400 #define NXGE_VAL_SET(fieldname, regval, val) \ 2401 { \ 2402 (regval) &= ~((fieldname) ## _MASK); \ 2403 (regval) |= ((val) << (fieldname ## _SHIFT)); \ 2404 } 2405 2406 2407 #ifdef __cplusplus 2408 } 2409 #endif 2410 2411 #endif /* _SYS_MAC_NXGE_MAC_HW_H */ 2412