1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MAC_NXGE_MAC_HW_H 27 #define _SYS_MAC_NXGE_MAC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 37 /* -------------------------- From May's template --------------------------- */ 38 39 #define NXGE_1GETHERMIN 255 40 #define NXGE_ETHERMIN 97 41 #define NXGE_MAX_HEADER 250 42 43 /* Hardware reset */ 44 typedef enum { 45 NXGE_TX_DISABLE, /* Disable Tx side */ 46 NXGE_RX_DISABLE, /* Disable Rx side */ 47 NXGE_CHIP_RESET /* Full chip reset */ 48 } nxge_reset_t; 49 50 #define NXGE_DELAY_AFTER_TXRX 10000 /* 10ms after idling rx/tx */ 51 #define NXGE_DELAY_AFTER_RESET 1000 /* 1ms after the reset */ 52 #define NXGE_DELAY_AFTER_EE_RESET 10000 /* 10ms after EEPROM reset */ 53 #define NXGE_DELAY_AFTER_LINK_RESET 13 /* 13 Us after link reset */ 54 #define NXGE_LINK_RESETS 8 /* Max PHY resets to wait for */ 55 /* linkup */ 56 57 #define FILTER_M_CTL 0xDCEF1 58 #define HASH_BITS 8 59 #define NMCFILTER_BITS (1 << HASH_BITS) 60 #define HASH_REG_WIDTH 16 61 #define BROADCAST_HASH_WORD 0x0f 62 #define BROADCAST_HASH_BIT 0x8000 63 #define NMCFILTER_REGS NMCFILTER_BITS / HASH_REG_WIDTH 64 /* Number of multicast filter regs */ 65 66 /* -------------------------------------------------------------------------- */ 67 68 #define XMAC_PORT_0 0 69 #define XMAC_PORT_1 1 70 #define BMAC_PORT_0 2 71 #define BMAC_PORT_1 3 72 73 #define MAC_RESET_WAIT 10 /* usecs */ 74 75 #define MAC_ADDR_REG_MASK 0xFFFF 76 77 /* 78 * Neptune port PHY type and Speed encoding. 79 * 80 * Per port, 4 bits are reserved for port speed (1G/10G) and 4 bits 81 * are reserved for port PHY type (Copper/Fibre). Bits 0 thru 3 are for port0 82 * speed, bits 4 thru 7 are for port1 speed, bits 8 thru 11 are for port2 speed 83 * and bits 12 thru 15 are for port3 speed. Thus, the first 16 bits hold the 84 * speed encoding for the 4 ports. The next 16 bits (16 thru 31) hold the phy 85 * type encoding for the ports 0 thru 3. 86 * 87 * p3phy p2phy p1phy p0phy p3spd p2spd p1spd p0spd 88 * | | | | | | | | 89 * --- --- --- --- --- --- --- --- 90 * / \ / \ / \ / \ / \ / \ / \ / \ 91 * 31..28 27..24 23..20 19..16 15..12 11.. 8 7.. 4 3.. 0 92 */ 93 #define NXGE_PORT_SPD_NONE 0x0 94 #define NXGE_PORT_SPD_1G 0x1 95 #define NXGE_PORT_SPD_10G 0x2 96 #define NXGE_PORT_SPD_RSVD 0x7 97 98 #define NXGE_PHY_NONE 0x0 99 #define NXGE_PHY_COPPER 0x1 100 #define NXGE_PHY_FIBRE 0x2 101 #define NXGE_PHY_RSVD 0x7 102 103 #define NXGE_PORT_SPD_SHIFT 0 104 #define NXGE_PORT_SPD_MASK 0x0f 105 106 #define NXGE_PHY_SHIFT 16 107 #define NXGE_PHY_MASK 0x0f0000 108 109 #define NXGE_PORT_1G_COPPER (NXGE_PORT_SPD_1G | \ 110 (NXGE_PHY_COPPER << NXGE_PHY_SHIFT)) 111 #define NXGE_PORT_10G_COPPER (NXGE_PORT_SPD_10G | \ 112 (NXGE_PHY_COPPER << NXGE_PHY_SHIFT)) 113 #define NXGE_PORT_1G_FIBRE (NXGE_PORT_SPD_1G | \ 114 (NXGE_PHY_FIBRE << NXGE_PHY_SHIFT)) 115 #define NXGE_PORT_10G_FIBRE (NXGE_PORT_SPD_10G | \ 116 (NXGE_PHY_FIBRE << NXGE_PHY_SHIFT)) 117 #define NXGE_PORT_NONE (NXGE_PORT_SPD_NONE | \ 118 (NXGE_PHY_NONE << NXGE_PHY_SHIFT)) 119 #define NXGE_PORT_RSVD (NXGE_PORT_SPD_RSVD | \ 120 (NXGE_PHY_RSVD << NXGE_PHY_SHIFT)) 121 122 #define NXGE_PORT_TYPE_MASK (NXGE_PORT_SPD_MASK | NXGE_PHY_MASK) 123 124 /* number of bits used for phy/spd encoding per port */ 125 #define NXGE_PORT_TYPE_SHIFT 4 126 127 /* Network Modes */ 128 129 typedef enum nxge_network_mode { 130 NET_2_10GE_FIBER = 1, 131 NET_2_10GE_COPPER, 132 NET_1_10GE_FIBER_3_1GE_COPPER, 133 NET_1_10GE_COPPER_3_1GE_COPPER, 134 NET_1_10GE_FIBER_3_1GE_FIBER, 135 NET_1_10GE_COPPER_3_1GE_FIBER, 136 NET_2_1GE_FIBER_2_1GE_COPPER, 137 NET_QGE_FIBER, 138 NET_QGE_COPPER 139 } nxge_network_mode_t; 140 141 typedef enum nxge_port { 142 PORT_TYPE_XMAC = 1, 143 PORT_TYPE_BMAC 144 } nxge_port_t; 145 146 typedef enum nxge_port_mode { 147 PORT_1G_COPPER = 1, 148 PORT_1G_FIBER, 149 PORT_10G_COPPER, 150 PORT_10G_FIBER 151 } nxge_port_mode_t; 152 153 typedef enum nxge_linkchk_mode { 154 LINKCHK_INTR = 1, 155 LINKCHK_TIMER 156 } nxge_linkchk_mode_t; 157 158 typedef enum { 159 LINK_INTR_STOP, 160 LINK_INTR_START 161 } link_intr_enable_t, *link_intr_enable_pt; 162 163 typedef enum { 164 LINK_MONITOR_STOP, 165 LINK_MONITOR_START, 166 LINK_MONITOR_STOPPING 167 } link_mon_enable_t, *link_mon_enable_pt; 168 169 typedef enum { 170 NO_XCVR, 171 INT_MII_XCVR, 172 EXT_MII_XCVR, 173 PCS_XCVR, 174 XPCS_XCVR 175 } xcvr_inuse_t; 176 177 /* macros for port offset calculations */ 178 179 #define PORT_1_OFFSET 0x6000 180 #define PORT_GT_1_OFFSET 0x4000 181 182 /* XMAC address macros */ 183 184 #define XMAC_ADDR_OFFSET_0 0 185 #define XMAC_ADDR_OFFSET_1 0x6000 186 187 #define XMAC_ADDR_OFFSET(port_num)\ 188 (XMAC_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET)) 189 190 #define XMAC_REG_ADDR(port_num, reg)\ 191 (FZC_MAC + (XMAC_ADDR_OFFSET(port_num)) + (reg)) 192 193 #define XMAC_PORT_ADDR(port_num)\ 194 (FZC_MAC + XMAC_ADDR_OFFSET(port_num)) 195 196 /* BMAC address macros */ 197 198 #define BMAC_ADDR_OFFSET_2 0x0C000 199 #define BMAC_ADDR_OFFSET_3 0x10000 200 201 #define BMAC_ADDR_OFFSET(port_num)\ 202 (BMAC_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET)) 203 204 #define BMAC_REG_ADDR(port_num, reg)\ 205 (FZC_MAC + (BMAC_ADDR_OFFSET(port_num)) + (reg)) 206 207 #define BMAC_PORT_ADDR(port_num)\ 208 (FZC_MAC + BMAC_ADDR_OFFSET(port_num)) 209 210 /* PCS address macros */ 211 212 #define PCS_ADDR_OFFSET_0 0x04000 213 #define PCS_ADDR_OFFSET_1 0x0A000 214 #define PCS_ADDR_OFFSET_2 0x0E000 215 #define PCS_ADDR_OFFSET_3 0x12000 216 217 #define PCS_ADDR_OFFSET(port_num)\ 218 ((port_num <= 1) ? \ 219 (PCS_ADDR_OFFSET_0 + (port_num) * PORT_1_OFFSET) : \ 220 (PCS_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET))) 221 222 #define PCS_REG_ADDR(port_num, reg)\ 223 (FZC_MAC + (PCS_ADDR_OFFSET((port_num)) + (reg))) 224 225 #define PCS_PORT_ADDR(port_num)\ 226 (FZC_MAC + (PCS_ADDR_OFFSET(port_num))) 227 228 /* XPCS address macros */ 229 230 #define XPCS_ADDR_OFFSET_0 0x02000 231 #define XPCS_ADDR_OFFSET_1 0x08000 232 #define XPCS_ADDR_OFFSET(port_num)\ 233 (XPCS_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET)) 234 235 #define XPCS_ADDR(port_num, reg)\ 236 (FZC_MAC + (XPCS_ADDR_OFFSET((port_num)) + (reg))) 237 238 #define XPCS_PORT_ADDR(port_num)\ 239 (FZC_MAC + (XPCS_ADDR_OFFSET(port_num))) 240 241 /* ESR address macro */ 242 #define ESR_ADDR_OFFSET 0x14000 243 #define ESR_ADDR(reg)\ 244 (FZC_MAC + (ESR_ADDR_OFFSET) + (reg)) 245 246 /* MIF address macros */ 247 #define MIF_ADDR_OFFSET 0x16000 248 #define MIF_ADDR(reg)\ 249 (FZC_MAC + (MIF_ADDR_OFFSET) + (reg)) 250 251 /* BMAC registers offset */ 252 #define BTXMAC_SW_RST_REG 0x000 /* TX MAC software reset */ 253 #define BRXMAC_SW_RST_REG 0x008 /* RX MAC software reset */ 254 #define MAC_SEND_PAUSE_REG 0x010 /* send pause command */ 255 #define BTXMAC_STATUS_REG 0x020 /* TX MAC status */ 256 #define BRXMAC_STATUS_REG 0x028 /* RX MAC status */ 257 #define BMAC_CTRL_STAT_REG 0x030 /* MAC control status */ 258 #define BTXMAC_STAT_MSK_REG 0x040 /* TX MAC mask */ 259 #define BRXMAC_STAT_MSK_REG 0x048 /* RX MAC mask */ 260 #define BMAC_C_S_MSK_REG 0x050 /* MAC control mask */ 261 #define TXMAC_CONFIG_REG 0x060 /* TX MAC config */ 262 /* cfg register bitmap */ 263 264 typedef union _btxmac_config_t { 265 uint64_t value; 266 267 struct { 268 #if defined(_BIG_ENDIAN) 269 uint32_t msw; /* Most significant word */ 270 uint32_t lsw; /* Least significant word */ 271 #elif defined(_LITTLE_ENDIAN) 272 uint32_t lsw; /* Least significant word */ 273 uint32_t msw; /* Most significant word */ 274 #endif 275 } val; 276 struct { 277 #if defined(_BIG_ENDIAN) 278 uint32_t w1; 279 #endif 280 struct { 281 #if defined(_BIT_FIELDS_HTOL) 282 uint32_t rsrvd : 22; 283 uint32_t hdx_ctrl2 : 1; 284 uint32_t no_fcs : 1; 285 uint32_t hdx_ctrl : 7; 286 uint32_t txmac_enable : 1; 287 #elif defined(_BIT_FIELDS_LTOH) 288 uint32_t txmac_enable : 1; 289 uint32_t hdx_ctrl : 7; 290 uint32_t no_fcs : 1; 291 uint32_t hdx_ctrl2 : 1; 292 uint32_t rsrvd : 22; 293 #endif 294 } w0; 295 296 #if defined(_LITTLE_ENDIAN) 297 uint32_t w1; 298 #endif 299 } bits; 300 } btxmac_config_t, *p_btxmac_config_t; 301 302 #define RXMAC_CONFIG_REG 0x068 /* RX MAC config */ 303 304 typedef union _brxmac_config_t { 305 uint64_t value; 306 307 struct { 308 #if defined(_BIG_ENDIAN) 309 uint32_t msw; /* Most significant word */ 310 uint32_t lsw; /* Least significant word */ 311 #elif defined(_LITTLE_ENDIAN) 312 uint32_t lsw; /* Least significant word */ 313 uint32_t msw; /* Most significant word */ 314 #endif 315 } val; 316 struct { 317 #if defined(_BIG_ENDIAN) 318 uint32_t w1; 319 #endif 320 struct { 321 #if defined(_BIT_FIELDS_HTOL) 322 uint32_t rsrvd : 20; 323 uint32_t mac_reg_sw_test : 2; 324 uint32_t mac2ipp_pkt_cnt_en : 1; 325 uint32_t rx_crs_extend_en : 1; 326 uint32_t error_chk_dis : 1; 327 uint32_t addr_filter_en : 1; 328 uint32_t hash_filter_en : 1; 329 uint32_t promiscuous_group : 1; 330 uint32_t promiscuous : 1; 331 uint32_t strip_fcs : 1; 332 uint32_t strip_pad : 1; 333 uint32_t rxmac_enable : 1; 334 #elif defined(_BIT_FIELDS_LTOH) 335 uint32_t rxmac_enable : 1; 336 uint32_t strip_pad : 1; 337 uint32_t strip_fcs : 1; 338 uint32_t promiscuous : 1; 339 uint32_t promiscuous_group : 1; 340 uint32_t hash_filter_en : 1; 341 uint32_t addr_filter_en : 1; 342 uint32_t error_chk_dis : 1; 343 uint32_t rx_crs_extend_en : 1; 344 uint32_t mac2ipp_pkt_cnt_en : 1; 345 uint32_t mac_reg_sw_test : 2; 346 uint32_t rsrvd : 20; 347 #endif 348 } w0; 349 350 #if defined(_LITTLE_ENDIAN) 351 uint32_t w1; 352 #endif 353 } bits; 354 } brxmac_config_t, *p_brxmac_config_t; 355 356 #define MAC_CTRL_CONFIG_REG 0x070 /* MAC control config */ 357 #define MAC_XIF_CONFIG_REG 0x078 /* XIF config */ 358 359 typedef union _bxif_config_t { 360 uint64_t value; 361 362 struct { 363 #if defined(_BIG_ENDIAN) 364 uint32_t msw; /* Most significant word */ 365 uint32_t lsw; /* Least significant word */ 366 #elif defined(_LITTLE_ENDIAN) 367 uint32_t lsw; /* Least significant word */ 368 uint32_t msw; /* Most significant word */ 369 #endif 370 } val; 371 struct { 372 #if defined(_BIG_ENDIAN) 373 uint32_t w1; 374 #endif 375 struct { 376 #if defined(_BIT_FIELDS_HTOL) 377 uint32_t rsrvd2 : 24; 378 uint32_t sel_clk_25mhz : 1; 379 uint32_t led_polarity : 1; 380 uint32_t force_led_on : 1; 381 uint32_t used : 1; 382 uint32_t gmii_mode : 1; 383 uint32_t rsrvd : 1; 384 uint32_t loopback : 1; 385 uint32_t tx_output_en : 1; 386 #elif defined(_BIT_FIELDS_LTOH) 387 uint32_t tx_output_en : 1; 388 uint32_t loopback : 1; 389 uint32_t rsrvd : 1; 390 uint32_t gmii_mode : 1; 391 uint32_t used : 1; 392 uint32_t force_led_on : 1; 393 uint32_t led_polarity : 1; 394 uint32_t sel_clk_25mhz : 1; 395 uint32_t rsrvd2 : 24; 396 #endif 397 } w0; 398 399 #if defined(_LITTLE_ENDIAN) 400 uint32_t w1; 401 #endif 402 } bits; 403 } bxif_config_t, *p_bxif_config_t; 404 405 #define BMAC_MIN_REG 0x0a0 /* min frame size */ 406 #define BMAC_MAX_REG 0x0a8 /* max frame size reg */ 407 #define MAC_PA_SIZE_REG 0x0b0 /* num of preamble bytes */ 408 #define MAC_CTRL_TYPE_REG 0x0c8 /* type field of MAC ctrl */ 409 #define BMAC_ADDR0_REG 0x100 /* MAC unique ad0 reg (HI 0) */ 410 #define BMAC_ADDR1_REG 0x108 /* MAC unique ad1 reg */ 411 #define BMAC_ADDR2_REG 0x110 /* MAC unique ad2 reg */ 412 #define BMAC_ADDR3_REG 0x118 /* MAC alt ad0 reg (HI 1) */ 413 #define BMAC_ADDR4_REG 0x120 /* MAC alt ad0 reg */ 414 #define BMAC_ADDR5_REG 0x128 /* MAC alt ad0 reg */ 415 #define BMAC_ADDR6_REG 0x130 /* MAC alt ad1 reg (HI 2) */ 416 #define BMAC_ADDR7_REG 0x138 /* MAC alt ad1 reg */ 417 #define BMAC_ADDR8_REG 0x140 /* MAC alt ad1 reg */ 418 #define BMAC_ADDR9_REG 0x148 /* MAC alt ad2 reg (HI 3) */ 419 #define BMAC_ADDR10_REG 0x150 /* MAC alt ad2 reg */ 420 #define BMAC_ADDR11_REG 0x158 /* MAC alt ad2 reg */ 421 #define BMAC_ADDR12_REG 0x160 /* MAC alt ad3 reg (HI 4) */ 422 #define BMAC_ADDR13_REG 0x168 /* MAC alt ad3 reg */ 423 #define BMAC_ADDR14_REG 0x170 /* MAC alt ad3 reg */ 424 #define BMAC_ADDR15_REG 0x178 /* MAC alt ad4 reg (HI 5) */ 425 #define BMAC_ADDR16_REG 0x180 /* MAC alt ad4 reg */ 426 #define BMAC_ADDR17_REG 0x188 /* MAC alt ad4 reg */ 427 #define BMAC_ADDR18_REG 0x190 /* MAC alt ad5 reg (HI 6) */ 428 #define BMAC_ADDR19_REG 0x198 /* MAC alt ad5 reg */ 429 #define BMAC_ADDR20_REG 0x1a0 /* MAC alt ad5 reg */ 430 #define BMAC_ADDR21_REG 0x1a8 /* MAC alt ad6 reg (HI 7) */ 431 #define BMAC_ADDR22_REG 0x1b0 /* MAC alt ad6 reg */ 432 #define BMAC_ADDR23_REG 0x1b8 /* MAC alt ad6 reg */ 433 #define MAC_FC_ADDR0_REG 0x268 /* FC frame addr0 (HI 0, p3) */ 434 #define MAC_FC_ADDR1_REG 0x270 /* FC frame addr1 */ 435 #define MAC_FC_ADDR2_REG 0x278 /* FC frame addr2 */ 436 #define MAC_ADDR_FILT0_REG 0x298 /* bits [47:32] (HI 0, p2) */ 437 #define MAC_ADDR_FILT1_REG 0x2a0 /* bits [31:16] */ 438 #define MAC_ADDR_FILT2_REG 0x2a8 /* bits [15:0] */ 439 #define MAC_ADDR_FILT12_MASK_REG 0x2b0 /* addr filter 2 & 1 mask */ 440 #define MAC_ADDR_FILT00_MASK_REG 0x2b8 /* addr filter 0 mask */ 441 #define MAC_HASH_TBL0_REG 0x2c0 /* hash table 0 reg */ 442 #define MAC_HASH_TBL1_REG 0x2c8 /* hash table 1 reg */ 443 #define MAC_HASH_TBL2_REG 0x2d0 /* hash table 2 reg */ 444 #define MAC_HASH_TBL3_REG 0x2d8 /* hash table 3 reg */ 445 #define MAC_HASH_TBL4_REG 0x2e0 /* hash table 4 reg */ 446 #define MAC_HASH_TBL5_REG 0x2e8 /* hash table 5 reg */ 447 #define MAC_HASH_TBL6_REG 0x2f0 /* hash table 6 reg */ 448 #define MAC_HASH_TBL7_REG 0x2f8 /* hash table 7 reg */ 449 #define MAC_HASH_TBL8_REG 0x300 /* hash table 8 reg */ 450 #define MAC_HASH_TBL9_REG 0x308 /* hash table 9 reg */ 451 #define MAC_HASH_TBL10_REG 0x310 /* hash table 10 reg */ 452 #define MAC_HASH_TBL11_REG 0x318 /* hash table 11 reg */ 453 #define MAC_HASH_TBL12_REG 0x320 /* hash table 12 reg */ 454 #define MAC_HASH_TBL13_REG 0x328 /* hash table 13 reg */ 455 #define MAC_HASH_TBL14_REG 0x330 /* hash table 14 reg */ 456 #define MAC_HASH_TBL15_REG 0x338 /* hash table 15 reg */ 457 #define RXMAC_FRM_CNT_REG 0x370 /* receive frame counter */ 458 #define MAC_LEN_ER_CNT_REG 0x378 /* length error counter */ 459 #define BMAC_AL_ER_CNT_REG 0x380 /* alignment error counter */ 460 #define BMAC_CRC_ER_CNT_REG 0x388 /* FCS error counter */ 461 #define BMAC_CD_VIO_CNT_REG 0x390 /* RX code violation err */ 462 #define BMAC_SM_REG 0x3a0 /* (ro) state machine reg */ 463 #define BMAC_ALTAD_CMPEN_REG 0x3f8 /* Alt addr compare enable */ 464 #define BMAC_HOST_INF0_REG 0x400 /* Host info */ 465 /* (own da, add filter, fc) */ 466 #define BMAC_HOST_INF1_REG 0x408 /* Host info (alt ad 0) */ 467 #define BMAC_HOST_INF2_REG 0x410 /* Host info (alt ad 1) */ 468 #define BMAC_HOST_INF3_REG 0x418 /* Host info (alt ad 2) */ 469 #define BMAC_HOST_INF4_REG 0x420 /* Host info (alt ad 3) */ 470 #define BMAC_HOST_INF5_REG 0x428 /* Host info (alt ad 4) */ 471 #define BMAC_HOST_INF6_REG 0x430 /* Host info (alt ad 5) */ 472 #define BMAC_HOST_INF7_REG 0x438 /* Host info (alt ad 6) */ 473 #define BMAC_HOST_INF8_REG 0x440 /* Host info (hash hit, miss) */ 474 #define BTXMAC_BYTE_CNT_REG 0x448 /* Tx byte count */ 475 #define BTXMAC_FRM_CNT_REG 0x450 /* frame count */ 476 #define BRXMAC_BYTE_CNT_REG 0x458 /* Rx byte count */ 477 /* x ranges from 0 to 6 (BMAC_MAX_ALT_ADDR_ENTRY - 1) */ 478 #define BMAC_ALT_ADDR0N_REG_ADDR(x) (BMAC_ADDR3_REG + (x) * 24) 479 #define BMAC_ALT_ADDR1N_REG_ADDR(x) (BMAC_ADDR3_REG + 8 + (x) * 24) 480 #define BMAC_ALT_ADDR2N_REG_ADDR(x) (BMAC_ADDR3_REG + 0x10 + (x) * 24) 481 #define BMAC_HASH_TBLN_REG_ADDR(x) (MAC_HASH_TBL0_REG + (x) * 8) 482 #define BMAC_HOST_INFN_REG_ADDR(x) (BMAC_HOST_INF0_REG + (x) * 8) 483 484 /* XMAC registers offset */ 485 #define XTXMAC_SW_RST_REG 0x000 /* XTX MAC soft reset */ 486 #define XRXMAC_SW_RST_REG 0x008 /* XRX MAC soft reset */ 487 #define XTXMAC_STATUS_REG 0x020 /* XTX MAC status */ 488 #define XRXMAC_STATUS_REG 0x028 /* XRX MAC status */ 489 #define XMAC_CTRL_STAT_REG 0x030 /* Control / Status */ 490 #define XTXMAC_STAT_MSK_REG 0x040 /* XTX MAC Status mask */ 491 #define XRXMAC_STAT_MSK_REG 0x048 /* XRX MAC Status mask */ 492 #define XMAC_C_S_MSK_REG 0x050 /* Control / Status mask */ 493 #define XMAC_CONFIG_REG 0x060 /* Configuration */ 494 495 /* xmac config bit fields */ 496 typedef union _xmac_cfg_t { 497 uint64_t value; 498 499 struct { 500 #if defined(_BIG_ENDIAN) 501 uint32_t msw; /* Most significant word */ 502 uint32_t lsw; /* Least significant word */ 503 #elif defined(_LITTLE_ENDIAN) 504 uint32_t lsw; /* Least significant word */ 505 uint32_t msw; /* Most significant word */ 506 #endif 507 } val; 508 struct { 509 #if defined(_BIG_ENDIAN) 510 uint32_t w1; 511 #endif 512 struct { 513 #if defined(_BIT_FIELDS_HTOL) 514 uint32_t sel_clk_25mhz : 1; 515 uint32_t pcs_bypass : 1; 516 uint32_t xpcs_bypass : 1; 517 uint32_t mii_gmii_mode : 2; 518 uint32_t lfs_disable : 1; 519 uint32_t loopback : 1; 520 uint32_t tx_output_en : 1; 521 uint32_t sel_por_clk_src : 1; 522 uint32_t led_polarity : 1; 523 uint32_t force_led_on : 1; 524 uint32_t pass_fctl_frames : 1; 525 uint32_t recv_pause_en : 1; 526 uint32_t mac2ipp_pkt_cnt_en : 1; 527 uint32_t strip_crc : 1; 528 uint32_t addr_filter_en : 1; 529 uint32_t hash_filter_en : 1; 530 uint32_t code_viol_chk_dis : 1; 531 uint32_t reserved_mcast : 1; 532 uint32_t rx_crc_chk_dis : 1; 533 uint32_t error_chk_dis : 1; 534 uint32_t promisc_grp : 1; 535 uint32_t promiscuous : 1; 536 uint32_t rx_mac_enable : 1; 537 uint32_t warning_msg_en : 1; 538 uint32_t used : 3; 539 uint32_t always_no_crc : 1; 540 uint32_t var_min_ipg_en : 1; 541 uint32_t strech_mode : 1; 542 uint32_t tx_enable : 1; 543 #elif defined(_BIT_FIELDS_LTOH) 544 uint32_t tx_enable : 1; 545 uint32_t strech_mode : 1; 546 uint32_t var_min_ipg_en : 1; 547 uint32_t always_no_crc : 1; 548 uint32_t used : 3; 549 uint32_t warning_msg_en : 1; 550 uint32_t rx_mac_enable : 1; 551 uint32_t promiscuous : 1; 552 uint32_t promisc_grp : 1; 553 uint32_t error_chk_dis : 1; 554 uint32_t rx_crc_chk_dis : 1; 555 uint32_t reserved_mcast : 1; 556 uint32_t code_viol_chk_dis : 1; 557 uint32_t hash_filter_en : 1; 558 uint32_t addr_filter_en : 1; 559 uint32_t strip_crc : 1; 560 uint32_t mac2ipp_pkt_cnt_en : 1; 561 uint32_t recv_pause_en : 1; 562 uint32_t pass_fctl_frames : 1; 563 uint32_t force_led_on : 1; 564 uint32_t led_polarity : 1; 565 uint32_t sel_por_clk_src : 1; 566 uint32_t tx_output_en : 1; 567 uint32_t loopback : 1; 568 uint32_t lfs_disable : 1; 569 uint32_t mii_gmii_mode : 2; 570 uint32_t xpcs_bypass : 1; 571 uint32_t pcs_bypass : 1; 572 uint32_t sel_clk_25mhz : 1; 573 #endif 574 } w0; 575 576 #if defined(_LITTLE_ENDIAN) 577 uint32_t w1; 578 #endif 579 } bits; 580 } xmac_cfg_t, *p_xmac_cfg_t; 581 582 #define XMAC_IPG_REG 0x080 /* Inter-Packet-Gap */ 583 #define XMAC_MIN_REG 0x088 /* min frame size register */ 584 #define XMAC_MAX_REG 0x090 /* max frame/burst size */ 585 #define XMAC_ADDR0_REG 0x0a0 /* [47:32] of MAC addr (HI17) */ 586 #define XMAC_ADDR1_REG 0x0a8 /* [31:16] of MAC addr */ 587 #define XMAC_ADDR2_REG 0x0b0 /* [15:0] of MAC addr */ 588 #define XRXMAC_BT_CNT_REG 0x100 /* bytes received / 8 */ 589 #define XRXMAC_BC_FRM_CNT_REG 0x108 /* good BC frames received */ 590 #define XRXMAC_MC_FRM_CNT_REG 0x110 /* good MC frames received */ 591 #define XRXMAC_FRAG_CNT_REG 0x118 /* frag frames rejected */ 592 #define XRXMAC_HIST_CNT1_REG 0x120 /* 64 bytes frames */ 593 #define XRXMAC_HIST_CNT2_REG 0x128 /* 65-127 bytes frames */ 594 #define XRXMAC_HIST_CNT3_REG 0x130 /* 128-255 bytes frames */ 595 #define XRXMAC_HIST_CNT4_REG 0x138 /* 256-511 bytes frames */ 596 #define XRXMAC_HIST_CNT5_REG 0x140 /* 512-1023 bytes frames */ 597 #define XRXMAC_HIST_CNT6_REG 0x148 /* 1024-1522 bytes frames */ 598 #define XRXMAC_MPSZER_CNT_REG 0x150 /* frames > maxframesize */ 599 #define XRXMAC_CRC_ER_CNT_REG 0x158 /* frames failed CRC */ 600 #define XRXMAC_CD_VIO_CNT_REG 0x160 /* frames with code vio */ 601 #define XRXMAC_AL_ER_CNT_REG 0x168 /* frames with align error */ 602 #define XTXMAC_FRM_CNT_REG 0x170 /* tx frames */ 603 #define XTXMAC_BYTE_CNT_REG 0x178 /* tx bytes / 8 */ 604 #define XMAC_LINK_FLT_CNT_REG 0x180 /* link faults */ 605 #define XRXMAC_HIST_CNT7_REG 0x188 /* MAC2IPP/>1523 bytes frames */ 606 #define XMAC_SM_REG 0x1a8 /* State machine */ 607 #define XMAC_INTERN1_REG 0x1b0 /* internal signals for diag */ 608 #define XMAC_INTERN2_REG 0x1b8 /* internal signals for diag */ 609 #define XMAC_ADDR_CMPEN_REG 0x208 /* alt MAC addr check */ 610 #define XMAC_ADDR3_REG 0x218 /* alt MAC addr 0 (HI 0) */ 611 #define XMAC_ADDR4_REG 0x220 /* alt MAC addr 0 */ 612 #define XMAC_ADDR5_REG 0x228 /* alt MAC addr 0 */ 613 #define XMAC_ADDR6_REG 0x230 /* alt MAC addr 1 (HI 1) */ 614 #define XMAC_ADDR7_REG 0x238 /* alt MAC addr 1 */ 615 #define XMAC_ADDR8_REG 0x240 /* alt MAC addr 1 */ 616 #define XMAC_ADDR9_REG 0x248 /* alt MAC addr 2 (HI 2) */ 617 #define XMAC_ADDR10_REG 0x250 /* alt MAC addr 2 */ 618 #define XMAC_ADDR11_REG 0x258 /* alt MAC addr 2 */ 619 #define XMAC_ADDR12_REG 0x260 /* alt MAC addr 3 (HI 3) */ 620 #define XMAC_ADDR13_REG 0x268 /* alt MAC addr 3 */ 621 #define XMAC_ADDR14_REG 0x270 /* alt MAC addr 3 */ 622 #define XMAC_ADDR15_REG 0x278 /* alt MAC addr 4 (HI 4) */ 623 #define XMAC_ADDR16_REG 0x280 /* alt MAC addr 4 */ 624 #define XMAC_ADDR17_REG 0x288 /* alt MAC addr 4 */ 625 #define XMAC_ADDR18_REG 0x290 /* alt MAC addr 5 (HI 5) */ 626 #define XMAC_ADDR19_REG 0x298 /* alt MAC addr 5 */ 627 #define XMAC_ADDR20_REG 0x2a0 /* alt MAC addr 5 */ 628 #define XMAC_ADDR21_REG 0x2a8 /* alt MAC addr 6 (HI 6) */ 629 #define XMAC_ADDR22_REG 0x2b0 /* alt MAC addr 6 */ 630 #define XMAC_ADDR23_REG 0x2b8 /* alt MAC addr 6 */ 631 #define XMAC_ADDR24_REG 0x2c0 /* alt MAC addr 7 (HI 7) */ 632 #define XMAC_ADDR25_REG 0x2c8 /* alt MAC addr 7 */ 633 #define XMAC_ADDR26_REG 0x2d0 /* alt MAC addr 7 */ 634 #define XMAC_ADDR27_REG 0x2d8 /* alt MAC addr 8 (HI 8) */ 635 #define XMAC_ADDR28_REG 0x2e0 /* alt MAC addr 8 */ 636 #define XMAC_ADDR29_REG 0x2e8 /* alt MAC addr 8 */ 637 #define XMAC_ADDR30_REG 0x2f0 /* alt MAC addr 9 (HI 9) */ 638 #define XMAC_ADDR31_REG 0x2f8 /* alt MAC addr 9 */ 639 #define XMAC_ADDR32_REG 0x300 /* alt MAC addr 9 */ 640 #define XMAC_ADDR33_REG 0x308 /* alt MAC addr 10 (HI 10) */ 641 #define XMAC_ADDR34_REG 0x310 /* alt MAC addr 10 */ 642 #define XMAC_ADDR35_REG 0x318 /* alt MAC addr 10 */ 643 #define XMAC_ADDR36_REG 0x320 /* alt MAC addr 11 (HI 11) */ 644 #define XMAC_ADDR37_REG 0x328 /* alt MAC addr 11 */ 645 #define XMAC_ADDR38_REG 0x330 /* alt MAC addr 11 */ 646 #define XMAC_ADDR39_REG 0x338 /* alt MAC addr 12 (HI 12) */ 647 #define XMAC_ADDR40_REG 0x340 /* alt MAC addr 12 */ 648 #define XMAC_ADDR41_REG 0x348 /* alt MAC addr 12 */ 649 #define XMAC_ADDR42_REG 0x350 /* alt MAC addr 13 (HI 13) */ 650 #define XMAC_ADDR43_REG 0x358 /* alt MAC addr 13 */ 651 #define XMAC_ADDR44_REG 0x360 /* alt MAC addr 13 */ 652 #define XMAC_ADDR45_REG 0x368 /* alt MAC addr 14 (HI 14) */ 653 #define XMAC_ADDR46_REG 0x370 /* alt MAC addr 14 */ 654 #define XMAC_ADDR47_REG 0x378 /* alt MAC addr 14 */ 655 #define XMAC_ADDR48_REG 0x380 /* alt MAC addr 15 (HI 15) */ 656 #define XMAC_ADDR49_REG 0x388 /* alt MAC addr 15 */ 657 #define XMAC_ADDR50_REG 0x390 /* alt MAC addr 15 */ 658 #define XMAC_ADDR_FILT0_REG 0x818 /* [47:32] addr filter (HI18) */ 659 #define XMAC_ADDR_FILT1_REG 0x820 /* [31:16] of addr filter */ 660 #define XMAC_ADDR_FILT2_REG 0x828 /* [15:0] of addr filter */ 661 #define XMAC_ADDR_FILT12_MASK_REG 0x830 /* addr filter 2 & 1 mask */ 662 #define XMAC_ADDR_FILT0_MASK_REG 0x838 /* addr filter 0 mask */ 663 #define XMAC_HASH_TBL0_REG 0x840 /* hash table 0 reg */ 664 #define XMAC_HASH_TBL1_REG 0x848 /* hash table 1 reg */ 665 #define XMAC_HASH_TBL2_REG 0x850 /* hash table 2 reg */ 666 #define XMAC_HASH_TBL3_REG 0x858 /* hash table 3 reg */ 667 #define XMAC_HASH_TBL4_REG 0x860 /* hash table 4 reg */ 668 #define XMAC_HASH_TBL5_REG 0x868 /* hash table 5 reg */ 669 #define XMAC_HASH_TBL6_REG 0x870 /* hash table 6 reg */ 670 #define XMAC_HASH_TBL7_REG 0x878 /* hash table 7 reg */ 671 #define XMAC_HASH_TBL8_REG 0x880 /* hash table 8 reg */ 672 #define XMAC_HASH_TBL9_REG 0x888 /* hash table 9 reg */ 673 #define XMAC_HASH_TBL10_REG 0x890 /* hash table 10 reg */ 674 #define XMAC_HASH_TBL11_REG 0x898 /* hash table 11 reg */ 675 #define XMAC_HASH_TBL12_REG 0x8a0 /* hash table 12 reg */ 676 #define XMAC_HASH_TBL13_REG 0x8a8 /* hash table 13 reg */ 677 #define XMAC_HASH_TBL14_REG 0x8b0 /* hash table 14 reg */ 678 #define XMAC_HASH_TBL15_REG 0x8b8 /* hash table 15 reg */ 679 #define XMAC_HOST_INF0_REG 0x900 /* Host info 0 (alt ad 0) */ 680 #define XMAC_HOST_INF1_REG 0x908 /* Host info 1 (alt ad 1) */ 681 #define XMAC_HOST_INF2_REG 0x910 /* Host info 2 (alt ad 2) */ 682 #define XMAC_HOST_INF3_REG 0x918 /* Host info 3 (alt ad 3) */ 683 #define XMAC_HOST_INF4_REG 0x920 /* Host info 4 (alt ad 4) */ 684 #define XMAC_HOST_INF5_REG 0x928 /* Host info 5 (alt ad 5) */ 685 #define XMAC_HOST_INF6_REG 0x930 /* Host info 6 (alt ad 6) */ 686 #define XMAC_HOST_INF7_REG 0x938 /* Host info 7 (alt ad 7) */ 687 #define XMAC_HOST_INF8_REG 0x940 /* Host info 8 (alt ad 8) */ 688 #define XMAC_HOST_INF9_REG 0x948 /* Host info 9 (alt ad 9) */ 689 #define XMAC_HOST_INF10_REG 0x950 /* Host info 10 (alt ad 10) */ 690 #define XMAC_HOST_INF11_REG 0x958 /* Host info 11 (alt ad 11) */ 691 #define XMAC_HOST_INF12_REG 0x960 /* Host info 12 (alt ad 12) */ 692 #define XMAC_HOST_INF13_REG 0x968 /* Host info 13 (alt ad 13) */ 693 #define XMAC_HOST_INF14_REG 0x970 /* Host info 14 (alt ad 14) */ 694 #define XMAC_HOST_INF15_REG 0x978 /* Host info 15 (alt ad 15) */ 695 #define XMAC_HOST_INF16_REG 0x980 /* Host info 16 (hash hit) */ 696 #define XMAC_HOST_INF17_REG 0x988 /* Host info 17 (own da) */ 697 #define XMAC_HOST_INF18_REG 0x990 /* Host info 18 (filter hit) */ 698 #define XMAC_HOST_INF19_REG 0x998 /* Host info 19 (fc hit) */ 699 #define XMAC_PA_DATA0_REG 0xb80 /* preamble [31:0] */ 700 #define XMAC_PA_DATA1_REG 0xb88 /* preamble [63:32] */ 701 #define XMAC_DEBUG_SEL_REG 0xb90 /* debug select */ 702 #define XMAC_TRAINING_VECT_REG 0xb98 /* training vector */ 703 /* x ranges from 0 to 15 (XMAC_MAX_ALT_ADDR_ENTRY - 1) */ 704 #define XMAC_ALT_ADDR0N_REG_ADDR(x) (XMAC_ADDR3_REG + (x) * 24) 705 #define XMAC_ALT_ADDR1N_REG_ADDR(x) (XMAC_ADDR3_REG + 8 + (x) * 24) 706 #define XMAC_ALT_ADDR2N_REG_ADDR(x) (XMAC_ADDR3_REG + 16 + (x) * 24) 707 #define XMAC_HASH_TBLN_REG_ADDR(x) (XMAC_HASH_TBL0_REG + (x) * 8) 708 #define XMAC_HOST_INFN_REG_ADDR(x) (XMAC_HOST_INF0_REG + (x) * 8) 709 710 /* MIF registers offset */ 711 #define MIF_BB_MDC_REG 0 /* MIF bit-bang clock */ 712 #define MIF_BB_MDO_REG 0x008 /* MIF bit-bang data */ 713 #define MIF_BB_MDO_EN_REG 0x010 /* MIF bit-bang output en */ 714 #define MIF_OUTPUT_FRAME_REG 0x018 /* MIF frame/output reg */ 715 #define MIF_CONFIG_REG 0x020 /* MIF config reg */ 716 #define MIF_POLL_STATUS_REG 0x028 /* MIF poll status reg */ 717 #define MIF_POLL_MASK_REG 0x030 /* MIF poll mask reg */ 718 #define MIF_STATE_MACHINE_REG 0x038 /* MIF state machine reg */ 719 #define MIF_STATUS_REG 0x040 /* MIF status reg */ 720 #define MIF_MASK_REG 0x048 /* MIF mask reg */ 721 722 723 /* PCS registers offset */ 724 #define PCS_MII_CTRL_REG 0 /* PCS MII control reg */ 725 #define PCS_MII_STATUS_REG 0x008 /* PCS MII status reg */ 726 #define PCS_MII_ADVERT_REG 0x010 /* PCS MII advertisement */ 727 #define PCS_MII_LPA_REG 0x018 /* link partner ability */ 728 #define PCS_CONFIG_REG 0x020 /* PCS config reg */ 729 #define PCS_STATE_MACHINE_REG 0x028 /* PCS state machine */ 730 #define PCS_INTR_STATUS_REG 0x030 /* PCS interrupt status */ 731 #define PCS_DATAPATH_MODE_REG 0x0a0 /* datapath mode reg */ 732 #define PCS_PACKET_COUNT_REG 0x0c0 /* PCS packet counter */ 733 734 #define XPCS_CTRL_1_REG 0 /* Control */ 735 #define XPCS_STATUS_1_REG 0x008 736 #define XPCS_DEV_ID_REG 0x010 /* 32bits IEEE manufacture ID */ 737 #define XPCS_SPEED_ABILITY_REG 0x018 738 #define XPCS_DEV_IN_PKG_REG 0x020 739 #define XPCS_CTRL_2_REG 0x028 740 #define XPCS_STATUS_2_REG 0x030 741 #define XPCS_PKG_ID_REG 0x038 /* Package ID */ 742 #define XPCS_STATUS_REG 0x040 743 #define XPCS_TEST_CTRL_REG 0x048 744 #define XPCS_CFG_VENDOR_1_REG 0x050 745 #define XPCS_DIAG_VENDOR_2_REG 0x058 746 #define XPCS_MASK_1_REG 0x060 747 #define XPCS_PKT_CNTR_REG 0x068 748 #define XPCS_TX_STATE_MC_REG 0x070 749 #define XPCS_DESKEW_ERR_CNTR_REG 0x078 750 #define XPCS_SYM_ERR_CNTR_L0_L1_REG 0x080 751 #define XPCS_SYM_ERR_CNTR_L2_L3_REG 0x088 752 #define XPCS_TRAINING_VECTOR_REG 0x090 753 754 /* ESR registers offset */ 755 #define ESR_RESET_REG 0 756 #define ESR_CONFIG_REG 0x008 757 #define ESR_0_PLL_CONFIG_REG 0x010 758 #define ESR_0_CONTROL_REG 0x018 759 #define ESR_0_TEST_CONFIG_REG 0x020 760 #define ESR_1_PLL_CONFIG_REG 0x028 761 #define ESR_1_CONTROL_REG 0x030 762 #define ESR_1_TEST_CONFIG_REG 0x038 763 #define ESR_ENET_RGMII_CFG_REG 0x040 764 #define ESR_INTERNAL_SIGNALS_REG 0x800 765 #define ESR_DEBUG_SEL_REG 0x808 766 767 768 /* Reset Register */ 769 #define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time */ 770 #define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl */ 771 772 /* Tx MAC Status Register */ 773 #define MAC_TX_FRAME_XMIT 0x00000001 /* successful tx frame */ 774 #define MAC_TX_UNDERRUN 0x00000002 /* starvation in xmit */ 775 #define MAC_TX_MAX_PACKET_ERR 0x00000004 /* TX frame exceeds max */ 776 #define MAC_TX_BYTE_CNT_EXP 0x00000400 /* TX byte cnt overflow */ 777 #define MAC_TX_FRAME_CNT_EXP 0x00000800 /* Tx frame cnt overflow */ 778 779 /* Rx MAC Status Register */ 780 #define MAC_RX_FRAME_RECV 0x00000001 /* successful rx frame */ 781 #define MAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 782 #define MAC_RX_FRAME_COUNT 0x00000004 /* rx frame cnt rollover */ 783 #define MAC_RX_ALIGN_ERR 0x00000008 /* alignment err rollover */ 784 #define MAC_RX_CRC_ERR 0x00000010 /* crc error cnt rollover */ 785 #define MAC_RX_LEN_ERR 0x00000020 /* length err cnt rollover */ 786 #define MAC_RX_VIOL_ERR 0x00000040 /* code vio err rollover */ 787 #define MAC_RX_BYTE_CNT_EXP 0x00000080 /* RX MAC byte rollover */ 788 789 /* MAC Control Status Register */ 790 #define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful pause frame */ 791 #define MAC_CTRL_PAUSE_STATE 0x00000002 /* notpause-->pause */ 792 #define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* pause-->notpause */ 793 #define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time */ 794 #define MAC_CTRL_PAUSE_TIME_SHIFT 16 795 796 /* Tx MAC Configuration Register */ 797 #define MAC_TX_CFG_TXMAC_ENABLE 0x00000001 /* enable TX MAC. */ 798 #define MAC_TX_CFG_NO_FCS 0x00000100 /* TX not generate CRC */ 799 800 /* Rx MAC Configuration Register */ 801 #define MAC_RX_CFG_RXMAC_ENABLE 0x00000001 /* enable RX MAC */ 802 #define MAC_RX_CFG_STRIP_PAD 0x00000002 /* not supported, set to 0 */ 803 #define MAC_RX_CFG_STRIP_FCS 0x00000004 /* strip last 4bytes (CRC) */ 804 #define MAC_RX_CFG_PROMISC 0x00000008 /* promisc mode enable */ 805 #define MAC_RX_CFG_PROMISC_GROUP 0x00000010 /* accept all MC frames */ 806 #define MAC_RX_CFG_HASH_FILTER_EN 0x00000020 /* use hash table */ 807 #define MAC_RX_CFG_ADDR_FILTER_EN 0x00000040 /* use address filter */ 808 #define MAC_RX_CFG_DISABLE_DISCARD 0x00000080 /* do not set abort bit */ 809 #define MAC_RX_MAC2IPP_PKT_CNT_EN 0x00000200 /* rx pkt cnt -> BMAC-IPP */ 810 #define MAC_RX_MAC_REG_RW_TEST_MASK 0x00000c00 /* BMAC reg RW test */ 811 #define MAC_RX_MAC_REG_RW_TEST_SHIFT 10 812 813 /* MAC Control Configuration Register */ 814 #define MAC_CTRL_CFG_SEND_PAUSE_EN 0x00000001 /* send pause flow ctrl */ 815 #define MAC_CTRL_CFG_RECV_PAUSE_EN 0x00000002 /* receive pause flow ctrl */ 816 #define MAC_CTRL_CFG_PASS_CTRL 0x00000004 /* accept MAC ctrl pkts */ 817 818 /* MAC XIF Configuration Register */ 819 #define MAC_XIF_TX_OUTPUT_EN 0x00000001 /* enable Tx output driver */ 820 #define MAC_XIF_MII_INT_LOOPBACK 0x00000002 /* loopback GMII xmit data */ 821 #define MAC_XIF_GMII_MODE 0x00000008 /* operates with GMII clks */ 822 #define MAC_XIF_LINK_LED 0x00000020 /* LINKLED# active (low) */ 823 #define MAC_XIF_LED_POLARITY 0x00000040 /* LED polarity */ 824 #define MAC_XIF_SEL_CLK_25MHZ 0x00000080 /* Select 10/100Mbps */ 825 826 /* MAC IPG Registers */ 827 #define BMAC_MIN_FRAME_MASK 0x3FF /* 10-bit reg */ 828 829 /* MAC Max Frame Size Register */ 830 #define BMAC_MAX_BURST_MASK 0x3FFF0000 /* max burst size [30:16] */ 831 #define BMAC_MAX_BURST_SHIFT 16 832 #define BMAC_MAX_FRAME_MASK 0x00007FFF /* max frame size [14:0] */ 833 #define BMAC_MAX_FRAME_SHIFT 0 834 835 /* MAC Preamble size register */ 836 #define BMAC_PA_SIZE_MASK 0x000003FF 837 /* # of preable bytes TxMAC sends at the beginning of each frame */ 838 839 /* 840 * mac address registers: 841 * register contains comparison 842 * -------- -------- ---------- 843 * 0 16 MSB of primary MAC addr [47:32] of DA field 844 * 1 16 middle bits "" [31:16] of DA field 845 * 2 16 LSB "" [15:0] of DA field 846 * 3*x 16MSB of alt MAC addr 1-7 [47:32] of DA field 847 * 4*x 16 middle bits "" [31:16] 848 * 5*x 16 LSB "" [15:0] 849 * 42 16 MSB of MAC CTRL addr [47:32] of DA. 850 * 43 16 middle bits "" [31:16] 851 * 44 16 LSB "" [15:0] 852 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames. 853 * if there is a match, MAC will set the bit for alternative address 854 * filter pass [15] 855 * 856 * here is the map of registers given MAC address notation: a:b:c:d:e:f 857 * ab cd ef 858 * primary addr reg 2 reg 1 reg 0 859 * alt addr 1 reg 5 reg 4 reg 3 860 * alt addr x reg 5*x reg 4*x reg 3*x 861 * | | | | 862 * | | | | 863 * alt addr 7 reg 23 reg 22 reg 21 864 * ctrl addr reg 44 reg 43 reg 42 865 */ 866 867 #define BMAC_ALT_ADDR_BASE 0x118 868 #define BMAC_MAX_ALT_ADDR_ENTRY 7 /* 7 alternate MAC addr */ 869 #define BMAC_MAX_ADDR_ENTRY (BMAC_MAX_ALT_ADDR_ENTRY + 1) 870 871 /* hash table registers */ 872 #define MAC_MAX_HASH_ENTRY 16 873 874 /* 27-bit register has the current state for key state machines in the MAC */ 875 #define MAC_SM_RLM_MASK 0x07800000 876 #define MAC_SM_RLM_SHIFT 23 877 #define MAC_SM_RX_FC_MASK 0x00700000 878 #define MAC_SM_RX_FC_SHIFT 20 879 #define MAC_SM_TLM_MASK 0x000F0000 880 #define MAC_SM_TLM_SHIFT 16 881 #define MAC_SM_ENCAP_SM_MASK 0x0000F000 882 #define MAC_SM_ENCAP_SM_SHIFT 12 883 #define MAC_SM_TX_REQ_MASK 0x00000C00 884 #define MAC_SM_TX_REQ_SHIFT 10 885 #define MAC_SM_TX_FC_MASK 0x000003C0 886 #define MAC_SM_TX_FC_SHIFT 6 887 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038 888 #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3 889 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007 890 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0 891 892 #define BMAC_ADDR0_CMPEN 0x00000001 893 #define BMAC_ADDRN_CMPEN(x) (BMAC_ADDR0_CMP_EN << (x)) 894 895 /* MAC Host Info Table Registers */ 896 #define BMAC_MAX_HOST_INFO_ENTRY 9 /* 9 host entries */ 897 898 /* 899 * ********************* XMAC registers ********************************* 900 */ 901 902 /* Reset Register */ 903 #define XTXMAC_SOFT_RST 0x00000001 /* XTX MAC software reset */ 904 #define XTXMAC_REG_RST 0x00000002 /* XTX MAC registers reset */ 905 #define XRXMAC_SOFT_RST 0x00000001 /* XRX MAC software reset */ 906 #define XRXMAC_REG_RST 0x00000002 /* XRX MAC registers reset */ 907 908 /* XTX MAC Status Register */ 909 #define XMAC_TX_FRAME_XMIT 0x00000001 /* successful tx frame */ 910 #define XMAC_TX_UNDERRUN 0x00000002 /* starvation in xmit */ 911 #define XMAC_TX_MAX_PACKET_ERR 0x00000004 /* XTX frame exceeds max */ 912 #define XMAC_TX_OVERFLOW 0x00000008 /* XTX byte cnt overflow */ 913 #define XMAC_TX_FIFO_XFR_ERR 0x00000010 /* xtlm state mach error */ 914 #define XMAC_TX_BYTE_CNT_EXP 0x00000400 /* XTX byte cnt overflow */ 915 #define XMAC_TX_FRAME_CNT_EXP 0x00000800 /* XTX frame cnt overflow */ 916 917 /* XRX MAC Status Register */ 918 #define XMAC_RX_FRAME_RCVD 0x00000001 /* successful rx frame */ 919 #define XMAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 920 #define XMAC_RX_UNDERFLOW 0x00000004 /* RX FIFO underrun */ 921 #define XMAC_RX_CRC_ERR_CNT_EXP 0x00000008 /* crc error cnt rollover */ 922 #define XMAC_RX_LEN_ERR_CNT_EXP 0x00000010 /* length err cnt rollover */ 923 #define XMAC_RX_VIOL_ERR_CNT_EXP 0x00000020 /* code vio err rollover */ 924 #define XMAC_RX_OCT_CNT_EXP 0x00000040 /* XRX MAC byte rollover */ 925 #define XMAC_RX_HST_CNT1_EXP 0x00000080 /* XRX MAC hist1 rollover */ 926 #define XMAC_RX_HST_CNT2_EXP 0x00000100 /* XRX MAC hist2 rollover */ 927 #define XMAC_RX_HST_CNT3_EXP 0x00000200 /* XRX MAC hist3 rollover */ 928 #define XMAC_RX_HST_CNT4_EXP 0x00000400 /* XRX MAC hist4 rollover */ 929 #define XMAC_RX_HST_CNT5_EXP 0x00000800 /* XRX MAC hist5 rollover */ 930 #define XMAC_RX_HST_CNT6_EXP 0x00001000 /* XRX MAC hist6 rollover */ 931 #define XMAC_RX_BCAST_CNT_EXP 0x00002000 /* XRX BC cnt rollover */ 932 #define XMAC_RX_MCAST_CNT_EXP 0x00004000 /* XRX MC cnt rollover */ 933 #define XMAC_RX_FRAG_CNT_EXP 0x00008000 /* fragment cnt rollover */ 934 #define XMAC_RX_ALIGNERR_CNT_EXP 0x00010000 /* framealign err rollover */ 935 #define XMAC_RX_LINK_FLT_CNT_EXP 0x00020000 /* link fault cnt rollover */ 936 #define XMAC_RX_REMOTE_FLT_DET 0x00040000 /* Remote Fault detected */ 937 #define XMAC_RX_LOCAL_FLT_DET 0x00080000 /* Local Fault detected */ 938 #define XMAC_RX_HST_CNT7_EXP 0x00100000 /* XRX MAC hist7 rollover */ 939 940 941 #define XMAC_CTRL_PAUSE_RCVD 0x00000001 /* successful pause frame */ 942 #define XMAC_CTRL_PAUSE_STATE 0x00000002 /* notpause-->pause */ 943 #define XMAC_CTRL_NOPAUSE_STATE 0x00000004 /* pause-->notpause */ 944 #define XMAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time */ 945 #define XMAC_CTRL_PAUSE_TIME_SHIFT 16 946 947 /* XMAC Configuration Register */ 948 #define XMAC_CONFIG_TX_BIT_MASK 0x000000ff /* bits [7:0] */ 949 #define XMAC_CONFIG_RX_BIT_MASK 0x001fff00 /* bits [20:8] */ 950 #define XMAC_CONFIG_XIF_BIT_MASK 0xffe00000 /* bits [31:21] */ 951 952 /* XTX MAC config bits */ 953 #define XMAC_TX_CFG_TX_ENABLE 0x00000001 /* enable XTX MAC */ 954 #define XMAC_TX_CFG_STRETCH_MD 0x00000002 /* WAN application */ 955 #define XMAC_TX_CFG_VAR_MIN_IPG_EN 0x00000004 /* Transmit pkts < minpsz */ 956 #define XMAC_TX_CFG_ALWAYS_NO_CRC 0x00000008 /* No CRC generated */ 957 958 #define XMAC_WARNING_MSG_ENABLE 0x00000080 /* Sim warning msg enable */ 959 960 /* XRX MAC config bits */ 961 #define XMAC_RX_CFG_RX_ENABLE 0x00000100 /* enable XRX MAC */ 962 #define XMAC_RX_CFG_PROMISC 0x00000200 /* promisc mode enable */ 963 #define XMAC_RX_CFG_PROMISC_GROUP 0x00000400 /* accept all MC frames */ 964 #define XMAC_RX_CFG_ERR_CHK_DISABLE 0x00000800 /* do not set abort bit */ 965 #define XMAC_RX_CFG_CRC_CHK_DISABLE 0x00001000 /* disable CRC logic */ 966 #define XMAC_RX_CFG_RESERVED_MCAST 0x00002000 /* reserved MCaddr compare */ 967 #define XMAC_RX_CFG_CD_VIO_CHK 0x00004000 /* rx code violation chk */ 968 #define XMAC_RX_CFG_HASH_FILTER_EN 0x00008000 /* use hash table */ 969 #define XMAC_RX_CFG_ADDR_FILTER_EN 0x00010000 /* use alt addr filter */ 970 #define XMAC_RX_CFG_STRIP_CRC 0x00020000 /* strip last 4bytes (CRC) */ 971 #define XMAC_RX_MAC2IPP_PKT_CNT_EN 0x00040000 /* histo_cntr7 cnt mode */ 972 #define XMAC_RX_CFG_RX_PAUSE_EN 0x00080000 /* receive pause flow ctrl */ 973 #define XMAC_RX_CFG_PASS_FLOW_CTRL 0x00100000 /* accept MAC ctrl pkts */ 974 975 976 /* MAC transceiver (XIF) configuration registers */ 977 978 #define XMAC_XIF_FORCE_LED_ON 0x00200000 /* Force Link LED on */ 979 #define XMAC_XIF_LED_POLARITY 0x00400000 /* LED polarity */ 980 #define XMAC_XIF_SEL_POR_CLK_SRC 0x00800000 /* Select POR clk src */ 981 #define XMAC_XIF_TX_OUTPUT_EN 0x01000000 /* enable MII/GMII modes */ 982 #define XMAC_XIF_LOOPBACK 0x02000000 /* loopback xmac xgmii tx */ 983 #define XMAC_XIF_LFS_DISABLE 0x04000000 /* disable link fault sig */ 984 #define XMAC_XIF_MII_MODE_MASK 0x18000000 /* MII/GMII/XGMII mode */ 985 #define XMAC_XIF_MII_MODE_SHIFT 27 986 #define XMAC_XIF_XGMII_MODE 0x00 987 #define XMAC_XIF_GMII_MODE 0x01 988 #define XMAC_XIF_MII_MODE 0x02 989 #define XMAC_XIF_ILLEGAL_MODE 0x03 990 #define XMAC_XIF_XPCS_BYPASS 0x20000000 /* use external xpcs */ 991 #define XMAC_XIF_1G_PCS_BYPASS 0x40000000 /* use external pcs */ 992 #define XMAC_XIF_SEL_CLK_25MHZ 0x80000000 /* 25Mhz clk for 100mbps */ 993 994 /* IPG register */ 995 #define XMAC_IPG_VALUE_MASK 0x00000007 /* IPG in XGMII mode */ 996 #define XMAC_IPG_VALUE_SHIFT 0 997 #define XMAC_IPG_VALUE1_MASK 0x0000ff00 /* IPG in GMII/MII mode */ 998 #define XMAC_IPG_VALUE1_SHIFT 8 999 #define XMAC_IPG_STRETCH_RATIO_MASK 0x001f0000 1000 #define XMAC_IPG_STRETCH_RATIO_SHIFT 16 1001 #define XMAC_IPG_STRETCH_CONST_MASK 0x00e00000 1002 #define XMAC_IPG_STRETCH_CONST_SHIFT 21 1003 1004 #define IPG_12_15_BYTE 3 1005 #define IPG_16_19_BYTE 4 1006 #define IPG_20_23_BYTE 5 1007 #define IPG1_12_BYTES 10 1008 #define IPG1_13_BYTES 11 1009 #define IPG1_14_BYTES 12 1010 #define IPG1_15_BYTES 13 1011 #define IPG1_16_BYTES 14 1012 1013 1014 #define XMAC_MIN_TX_FRM_SZ_MASK 0x3ff /* Min tx frame size */ 1015 #define XMAC_MIN_TX_FRM_SZ_SHIFT 0 1016 #define XMAC_SLOT_TIME_MASK 0x0003fc00 /* slot time */ 1017 #define XMAC_SLOT_TIME_SHIFT 10 1018 #define XMAC_MIN_RX_FRM_SZ_MASK 0x3ff00000 /* Min rx frame size */ 1019 #define XMAC_MIN_RX_FRM_SZ_SHIFT 20 1020 #define XMAC_MAX_FRM_SZ_MASK 0x00003fff /* max tx frame size */ 1021 1022 /* State Machine Register */ 1023 #define XMAC_SM_TX_LNK_MGMT_MASK 0x00000007 1024 #define XMAC_SM_TX_LNK_MGMT_SHIFT 0 1025 #define XMAC_SM_SOP_DETECT 0x00000008 1026 #define XMAC_SM_LNK_FLT_SIG_MASK 0x00000030 1027 #define XMAC_SM_LNK_FLT_SIG_SHIFT 4 1028 #define XMAC_SM_MII_GMII_MD_RX_LNK 0x00000040 1029 #define XMAC_SM_XGMII_MD_RX_LNK 0x00000080 1030 #define XMAC_SM_XGMII_ONLY_VAL_SIG 0x00000100 1031 #define XMAC_SM_ALT_ADR_N_HSH_FN_SIG 0x00000200 1032 #define XMAC_SM_RXMAC_IPP_STAT_MASK 0x00001c00 1033 #define XMAC_SM_RXMAC_IPP_STAT_SHIFT 10 1034 #define XMAC_SM_RXFIFO_WPTR_CLK_MASK 0x007c0000 1035 #define XMAC_SM_RXFIFO_WPTR_CLK_SHIFT 18 1036 #define XMAC_SM_RXFIFO_RPTR_CLK_MASK 0x0F800000 1037 #define XMAC_SM_RXFIFO_RPTR_CLK_SHIFT 23 1038 #define XMAC_SM_TXFIFO_FULL_CLK 0x10000000 1039 #define XMAC_SM_TXFIFO_EMPTY_CLK 0x20000000 1040 #define XMAC_SM_RXFIFO_FULL_CLK 0x40000000 1041 #define XMAC_SM_RXFIFO_EMPTY_CLK 0x80000000 1042 1043 /* Internal Signals 1 Register */ 1044 #define XMAC_IS1_OPP_TXMAC_STAT_MASK 0x0000000F 1045 #define XMAC_IS1_OPP_TXMAC_STAT_SHIFT 0 1046 #define XMAC_IS1_OPP_TXMAC_ABORT 0x00000010 1047 #define XMAC_IS1_OPP_TXMAC_TAG 0x00000020 1048 #define XMAC_IS1_OPP_TXMAC_ACK 0x00000040 1049 #define XMAC_IS1_TXMAC_OPP_REQ 0x00000080 1050 #define XMAC_IS1_RXMAC_IPP_STAT_MASK 0x0FFFFF00 1051 #define XMAC_IS1_RXMAC_IPP_STAT_SHIFT 8 1052 #define XMAC_IS1_RXMAC_IPP_CTRL 0x10000000 1053 #define XMAC_IS1_RXMAC_IPP_TAG 0x20000000 1054 #define XMAC_IS1_IPP_RXMAC_REQ 0x40000000 1055 #define XMAC_IS1_RXMAC_IPP_ACK 0x80000000 1056 1057 /* Internal Signals 2 Register */ 1058 #define XMAC_IS2_TX_HB_TIMER_MASK 0x0000000F 1059 #define XMAC_IS2_TX_HB_TIMER_SHIFT 0 1060 #define XMAC_IS2_RX_HB_TIMER_MASK 0x000000F0 1061 #define XMAC_IS2_RX_HB_TIMER_SHIFT 4 1062 #define XMAC_IS2_XPCS_RXC_MASK 0x0000FF00 1063 #define XMAC_IS2_XPCS_RXC_SHIFT 8 1064 #define XMAC_IS2_XPCS_TXC_MASK 0x00FF0000 1065 #define XMAC_IS2_XPCS_TXC_SHIFT 16 1066 #define XMAC_IS2_LOCAL_FLT_OC_SYNC 0x01000000 1067 #define XMAC_IS2_RMT_FLT_OC_SYNC 0x02000000 1068 1069 /* Register size masking */ 1070 1071 #define XTXMAC_FRM_CNT_MASK 0xFFFFFFFF 1072 #define XTXMAC_BYTE_CNT_MASK 0xFFFFFFFF 1073 #define XRXMAC_CRC_ER_CNT_MASK 0x000000FF 1074 #define XRXMAC_MPSZER_CNT_MASK 0x000000FF 1075 #define XRXMAC_CD_VIO_CNT_MASK 0x000000FF 1076 #define XRXMAC_BT_CNT_MASK 0xFFFFFFFF 1077 #define XRXMAC_HIST_CNT1_MASK 0x001FFFFF 1078 #define XRXMAC_HIST_CNT2_MASK 0x001FFFFF 1079 #define XRXMAC_HIST_CNT3_MASK 0x000FFFFF 1080 #define XRXMAC_HIST_CNT4_MASK 0x0007FFFF 1081 #define XRXMAC_HIST_CNT5_MASK 0x0003FFFF 1082 #define XRXMAC_HIST_CNT6_MASK 0x0001FFFF 1083 #define XRXMAC_BC_FRM_CNT_MASK 0x001FFFFF 1084 #define XRXMAC_MC_FRM_CNT_MASK 0x001FFFFF 1085 #define XRXMAC_FRAG_CNT_MASK 0x001FFFFF 1086 #define XRXMAC_AL_ER_CNT_MASK 0x000000FF 1087 #define XMAC_LINK_FLT_CNT_MASK 0x000000FF 1088 #define BTXMAC_FRM_CNT_MASK 0x001FFFFF 1089 #define BTXMAC_BYTE_CNT_MASK 0x07FFFFFF 1090 #define RXMAC_FRM_CNT_MASK 0x0000FFFF 1091 #define BRXMAC_BYTE_CNT_MASK 0x07FFFFFF 1092 #define BMAC_AL_ER_CNT_MASK 0x0000FFFF 1093 #define MAC_LEN_ER_CNT_MASK 0x0000FFFF 1094 #define BMAC_CRC_ER_CNT_MASK 0x0000FFFF 1095 #define BMAC_CD_VIO_CNT_MASK 0x0000FFFF 1096 #define XMAC_XPCS_DESKEW_ERR_CNT_MASK 0x000000FF 1097 #define XMAC_XPCS_SYM_ERR_CNT_L0_MASK 0x0000FFFF 1098 #define XMAC_XPCS_SYM_ERR_CNT_L1_MASK 0xFFFF0000 1099 #define XMAC_XPCS_SYM_ERR_CNT_L1_SHIFT 16 1100 #define XMAC_XPCS_SYM_ERR_CNT_L2_MASK 0x0000FFFF 1101 #define XMAC_XPCS_SYM_ERR_CNT_L3_MASK 0xFFFF0000 1102 #define XMAC_XPCS_SYM_ERR_CNT_L3_SHIFT 16 1103 1104 /* Alternate MAC address registers */ 1105 #define XMAC_MAX_ALT_ADDR_ENTRY 16 /* 16 alternate MAC addrs */ 1106 #define XMAC_MAX_ADDR_ENTRY (XMAC_MAX_ALT_ADDR_ENTRY + 1) 1107 1108 /* Max / Min parameters for Neptune MAC */ 1109 1110 #define MAC_MAX_ALT_ADDR_ENTRY XMAC_MAX_ALT_ADDR_ENTRY 1111 #define MAC_MAX_HOST_INFO_ENTRY XMAC_MAX_HOST_INFO_ENTRY 1112 1113 /* HostInfo entry for the unique MAC address */ 1114 #define XMAC_UNIQUE_HOST_INFO_ENTRY 17 1115 #define BMAC_UNIQUE_HOST_INFO_ENTRY 0 1116 1117 /* HostInfo entry for the multicat address */ 1118 #define XMAC_MULTI_HOST_INFO_ENTRY 16 1119 #define BMAC_MULTI_HOST_INFO_ENTRY 8 1120 1121 /* XMAC Host Info Register */ 1122 typedef union hostinfo { 1123 1124 uint64_t value; 1125 1126 struct { 1127 #if defined(_BIG_ENDIAN) 1128 uint32_t msw; /* Most significant word */ 1129 uint32_t lsw; /* Least significant word */ 1130 #elif defined(_LITTLE_ENDIAN) 1131 uint32_t lsw; /* Least significant word */ 1132 uint32_t msw; /* Most significant word */ 1133 #endif 1134 } val; 1135 struct { 1136 #if defined(_BIG_ENDIAN) 1137 uint32_t w1; 1138 #endif 1139 struct { 1140 #if defined(_BIT_FIELDS_HTOL) 1141 uint32_t reserved2 : 23; 1142 uint32_t mac_pref : 1; 1143 uint32_t reserved1 : 5; 1144 uint32_t rdc_tbl_num : 3; 1145 #elif defined(_BIT_FIELDS_LTOH) 1146 uint32_t rdc_tbl_num : 3; 1147 uint32_t reserved1 : 5; 1148 uint32_t mac_pref : 1; 1149 uint32_t reserved2 : 23; 1150 #endif 1151 } w0; 1152 1153 #if defined(_LITTLE_ENDIAN) 1154 uint32_t w1; 1155 #endif 1156 } bits; 1157 1158 } hostinfo_t; 1159 1160 typedef union hostinfo *hostinfo_pt; 1161 1162 #define XMAC_HI_RDC_TBL_NUM_MASK 0x00000007 1163 #define XMAC_HI_MAC_PREF 0x00000100 1164 1165 #define XMAC_MAX_HOST_INFO_ENTRY 20 /* 20 host entries */ 1166 1167 /* 1168 * ******************** MIF registers ********************************* 1169 */ 1170 1171 /* 1172 * 32-bit register serves as an instruction register when the MIF is 1173 * programmed in frame mode. load this register w/ a valid instruction 1174 * (as per IEEE 802.3u MII spec). poll this register to check for instruction 1175 * execution completion. during a read operation, this register will also 1176 * contain the 16-bit data returned by the transceiver. unless specified 1177 * otherwise, fields are considered "don't care" when polling for 1178 * completion. 1179 */ 1180 1181 #define MIF_FRAME_START_MASK 0xC0000000 /* start of frame mask */ 1182 #define MIF_FRAME_ST_22 0x40000000 /* STart of frame, Cl 22 */ 1183 #define MIF_FRAME_ST_45 0x00000000 /* STart of frame, Cl 45 */ 1184 #define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode */ 1185 #define MIF_FRAME_OP_READ_22 0x20000000 /* read OPcode, Cl 22 */ 1186 #define MIF_FRAME_OP_WRITE_22 0x10000000 /* write OPcode, Cl 22 */ 1187 #define MIF_FRAME_OP_ADDR_45 0x00000000 /* addr of reg to access */ 1188 #define MIF_FRAME_OP_READ_45 0x30000000 /* read OPcode, Cl 45 */ 1189 #define MIF_FRAME_OP_WRITE_45 0x10000000 /* write OPcode, Cl 45 */ 1190 #define MIF_FRAME_OP_P_R_I_A_45 0x10000000 /* post-read-inc-addr */ 1191 #define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address mask */ 1192 #define MIF_FRAME_PHY_ADDR_SHIFT 23 1193 #define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* reg addr in Cl 22 */ 1194 /* dev addr in Cl 45 */ 1195 #define MIF_FRAME_REG_ADDR_SHIFT 18 1196 #define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB. */ 1197 #define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB. */ 1198 #define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload */ 1199 1200 /* Clause 45 frame field values */ 1201 #define FRAME45_ST 0 1202 #define FRAME45_OP_ADDR 0 1203 #define FRAME45_OP_WRITE 1 1204 #define FRAME45_OP_READ_INC 2 1205 #define FRAME45_OP_READ 3 1206 1207 typedef union _mif_frame_t { 1208 1209 uint64_t value; 1210 1211 struct { 1212 #if defined(_BIG_ENDIAN) 1213 uint32_t msw; /* Most significant word */ 1214 uint32_t lsw; /* Least significant word */ 1215 #elif defined(_LITTLE_ENDIAN) 1216 uint32_t lsw; /* Least significant word */ 1217 uint32_t msw; /* Most significant word */ 1218 #endif 1219 } val; 1220 struct { 1221 #if defined(_BIG_ENDIAN) 1222 uint32_t w1; 1223 #endif 1224 struct { 1225 #if defined(_BIT_FIELDS_HTOL) 1226 uint32_t st : 2; 1227 uint32_t op : 2; 1228 uint32_t phyad : 5; 1229 uint32_t regad : 5; 1230 uint32_t ta_msb : 1; 1231 uint32_t ta_lsb : 1; 1232 uint32_t data : 16; 1233 #elif defined(_BIT_FIELDS_LTOH) 1234 uint32_t data : 16; 1235 uint32_t ta_lsb : 1; 1236 uint32_t ta_msb : 1; 1237 uint32_t regad : 5; 1238 uint32_t phyad : 5; 1239 uint32_t op : 2; 1240 uint32_t st : 2; 1241 #endif 1242 } w0; 1243 1244 #if defined(_LITTLE_ENDIAN) 1245 uint32_t w1; 1246 #endif 1247 } bits; 1248 } mif_frame_t; 1249 1250 #define MIF_CFG_POLL_EN 0x00000008 /* enable polling */ 1251 #define MIF_CFG_BB_MODE 0x00000010 /* bit-bang mode */ 1252 #define MIF_CFG_POLL_REG_MASK 0x000003E0 /* reg addr to be polled */ 1253 #define MIF_CFG_POLL_REG_SHIFT 5 1254 #define MIF_CFG_POLL_PHY_MASK 0x00007C00 /* XCVR addr to be polled */ 1255 #define MIF_CFG_POLL_PHY_SHIFT 10 1256 #define MIF_CFG_INDIRECT_MODE 0x0000800 1257 /* used to decide if Cl 22 */ 1258 /* or Cl 45 frame is */ 1259 /* constructed. */ 1260 /* 1 = Clause 45,ST = '00' */ 1261 /* 0 = Clause 22,ST = '01' */ 1262 #define MIF_CFG_ATCE_GE_EN 0x00010000 /* Enable ATCA gigabit mode */ 1263 1264 typedef union _mif_cfg_t { 1265 1266 uint64_t value; 1267 1268 struct { 1269 #if defined(_BIG_ENDIAN) 1270 uint32_t msw; /* Most significant word */ 1271 uint32_t lsw; /* Least significant word */ 1272 1273 #elif defined(_LITTLE_ENDIAN) 1274 uint32_t lsw; /* Least significant word */ 1275 uint32_t msw; /* Most significant word */ 1276 #endif 1277 } val; 1278 struct { 1279 #if defined(_BIG_ENDIAN) 1280 uint32_t w1; 1281 #endif 1282 struct { 1283 #if defined(_BIT_FIELDS_HTOL) 1284 uint32_t res2 : 15; 1285 uint32_t atca_ge : 1; 1286 uint32_t indirect_md : 1; 1287 uint32_t phy_addr : 5; 1288 uint32_t reg_addr : 5; 1289 uint32_t bb_mode : 1; 1290 uint32_t poll_en : 1; 1291 uint32_t res1 : 2; 1292 uint32_t res : 1; 1293 #elif defined(_BIT_FIELDS_LTOH) 1294 uint32_t res : 1; 1295 uint32_t res1 : 2; 1296 uint32_t poll_en : 1; 1297 uint32_t bb_mode : 1; 1298 uint32_t reg_addr : 5; 1299 uint32_t phy_addr : 5; 1300 uint32_t indirect_md : 1; 1301 uint32_t atca_ge : 1; 1302 uint32_t res2 : 15; 1303 #endif 1304 } w0; 1305 1306 #if defined(_LITTLE_ENDIAN) 1307 uint32_t w1; 1308 #endif 1309 } bits; 1310 1311 } mif_cfg_t; 1312 1313 #define MIF_POLL_STATUS_DATA_MASK 0xffff0000 1314 #define MIF_POLL_STATUS_STAT_MASK 0x0000ffff 1315 1316 typedef union _mif_poll_stat_t { 1317 uint64_t value; 1318 1319 struct { 1320 #if defined(_BIG_ENDIAN) 1321 uint32_t msw; /* Most significant word */ 1322 uint32_t lsw; /* Least significant word */ 1323 #elif defined(_LITTLE_ENDIAN) 1324 uint32_t lsw; /* Least significant word */ 1325 uint32_t msw; /* Most significant word */ 1326 #endif 1327 } val; 1328 struct { 1329 #if defined(_BIG_ENDIAN) 1330 uint32_t w1; 1331 #endif 1332 struct { 1333 #if defined(_BIT_FIELDS_HTOL) 1334 uint16_t data; 1335 uint16_t status; 1336 #elif defined(_BIT_FIELDS_LTOH) 1337 uint16_t status; 1338 uint16_t data; 1339 #endif 1340 } w0; 1341 1342 #if defined(_LITTLE_ENDIAN) 1343 uint32_t w1; 1344 #endif 1345 } bits; 1346 } mif_poll_stat_t; 1347 1348 1349 #define MIF_POLL_MASK_MASK 0x0000ffff 1350 1351 typedef union _mif_poll_mask_t { 1352 uint64_t value; 1353 1354 struct { 1355 #if defined(_BIG_ENDIAN) 1356 uint32_t msw; /* Most significant word */ 1357 uint32_t lsw; /* Least significant word */ 1358 #elif defined(_LITTLE_ENDIAN) 1359 uint32_t lsw; /* Least significant word */ 1360 uint32_t msw; /* Most significant word */ 1361 #endif 1362 } val; 1363 struct { 1364 #if defined(_BIG_ENDIAN) 1365 uint32_t w1; 1366 #endif 1367 struct { 1368 #if defined(_BIT_FIELDS_HTOL) 1369 uint16_t rsvd; 1370 uint16_t mask; 1371 #elif defined(_BIT_FIELDS_LTOH) 1372 uint16_t mask; 1373 uint16_t rsvd; 1374 #endif 1375 } w0; 1376 1377 #if defined(_LITTLE_ENDIAN) 1378 uint32_t w1; 1379 #endif 1380 } bits; 1381 } mif_poll_mask_t; 1382 1383 #define MIF_STATUS_INIT_DONE_MASK 0x00000001 1384 #define MIF_STATUS_XGE_ERR0_MASK 0x00000002 1385 #define MIF_STATUS_XGE_ERR1_MASK 0x00000004 1386 #define MIF_STATUS_PEU_ERR_MASK 0x00000008 1387 #define MIF_STATUS_EXT_PHY_INTR0_MASK 0x00000010 1388 #define MIF_STATUS_EXT_PHY_INTR1_MASK 0x00000020 1389 1390 typedef union _mif_stat_t { 1391 uint64_t value; 1392 1393 struct { 1394 #if defined(_BIG_ENDIAN) 1395 uint32_t msw; /* Most significant word */ 1396 uint32_t lsw; /* Least significant word */ 1397 #elif defined(_LITTLE_ENDIAN) 1398 uint32_t lsw; /* Least significant word */ 1399 uint32_t msw; /* Most significant word */ 1400 #endif 1401 } val; 1402 struct { 1403 #if defined(_BIG_ENDIAN) 1404 uint32_t w1; 1405 #endif 1406 struct { 1407 #if defined(_BIT_FIELDS_HTOL) 1408 uint32_t rsvd:26; 1409 uint32_t ext_phy_intr_flag1:1; 1410 uint32_t ext_phy_intr_flag0:1; 1411 uint32_t peu_err:1; 1412 uint32_t xge_err1:1; 1413 uint32_t xge_err0:1; 1414 uint32_t mif_init_done_stat:1; 1415 1416 #elif defined(_BIT_FIELDS_LTOH) 1417 uint32_t mif_init_done_stat:1; 1418 uint32_t xge_err0:1; 1419 uint32_t xge_err1:1; 1420 uint32_t ext_phy_intr_flag0:1; 1421 uint32_t ext_phy_intr_flag1:1; 1422 uint32_t rsvd:26; 1423 #endif 1424 } w0; 1425 1426 #if defined(_LITTLE_ENDIAN) 1427 uint32_t w1; 1428 #endif 1429 } bits; 1430 } mif_stat_t; 1431 1432 /* MIF State Machine Register */ 1433 1434 #define MIF_SM_EXECUTION_MASK 0x0000003f /* execution state */ 1435 #define MIF_SM_EXECUTION_SHIFT 0 1436 #define MIF_SM_CONTROL_MASK 0x000001c0 /* control state */ 1437 #define MIF_SM_CONTROL_MASK_SHIFT 6 1438 #define MIF_SM_MDI 0x00000200 1439 #define MIF_SM_MDO 0x00000400 1440 #define MIF_SM_MDO_EN 0x00000800 1441 #define MIF_SM_MDC 0x00001000 1442 #define MIF_SM_MDI_0 0x00002000 1443 #define MIF_SM_MDI_1 0x00004000 1444 #define MIF_SM_MDI_2 0x00008000 1445 #define MIF_SM_PORT_ADDR_MASK 0x001f0000 1446 #define MIF_SM_PORT_ADDR_SHIFT 16 1447 #define MIF_SM_INT_SIG_MASK 0xffe00000 1448 #define MIF_SM_INT_SIG_SHIFT 21 1449 1450 1451 /* 1452 * ******************** PCS registers ********************************* 1453 */ 1454 1455 /* PCS Registers */ 1456 #define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on wr */ 1457 #define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal */ 1458 #define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. */ 1459 #define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing. */ 1460 #define PCS_MII_ISOLATE 0x0400 /* read 0. ignored on wr */ 1461 #define PCS_MII_POWER_DOWN 0x0800 /* read 0. ignored on wr */ 1462 #define PCS_MII_AUTONEG_EN 0x1000 /* autonegotiation */ 1463 #define PCS_MII_10_100_SEL 0x2000 /* read 0. ignored on wr */ 1464 #define PCS_MII_RESET 0x8000 /* reset PCS. */ 1465 1466 typedef union _pcs_ctrl_t { 1467 uint64_t value; 1468 1469 struct { 1470 #if defined(_BIG_ENDIAN) 1471 uint32_t msw; /* Most significant word */ 1472 uint32_t lsw; /* Least significant word */ 1473 #elif defined(_LITTLE_ENDIAN) 1474 uint32_t lsw; /* Least significant word */ 1475 uint32_t msw; /* Most significant word */ 1476 #endif 1477 } val; 1478 struct { 1479 #if defined(_BIG_ENDIAN) 1480 uint32_t w1; 1481 #endif 1482 struct { 1483 #if defined(_BIT_FIELDS_HTOL) 1484 uint32_t res0 : 16; 1485 uint32_t reset : 1; 1486 uint32_t res1 : 1; 1487 uint32_t sel_10_100 : 1; 1488 uint32_t an_enable : 1; 1489 uint32_t pwr_down : 1; 1490 uint32_t isolate : 1; 1491 uint32_t restart_an : 1; 1492 uint32_t duplex : 1; 1493 uint32_t col_test : 1; 1494 uint32_t sel_1000 : 1; 1495 uint32_t res2 : 6; 1496 #elif defined(_BIT_FIELDS_LTOH) 1497 uint32_t res2 : 6; 1498 uint32_t sel_1000 : 1; 1499 uint32_t col_test : 1; 1500 uint32_t duplex : 1; 1501 uint32_t restart_an : 1; 1502 uint32_t isolate : 1; 1503 uint32_t pwr_down : 1; 1504 uint32_t an_enable : 1; 1505 uint32_t sel_10_100 : 1; 1506 uint32_t res1 : 1; 1507 uint32_t reset : 1; 1508 uint32_t res0 : 16; 1509 #endif 1510 } w0; 1511 1512 #if defined(_LITTLE_ENDIAN) 1513 uint32_t w1; 1514 #endif 1515 } bits; 1516 } pcs_ctrl_t; 1517 1518 #define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */ 1519 #define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */ 1520 #define PCS_MII_STATUS_LINK_STATUS 0x0004 /* link status */ 1521 #define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 */ 1522 #define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* remote fault detected */ 1523 #define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* auto-neg completed */ 1524 #define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* 1000 Base-X PHY */ 1525 1526 typedef union _pcs_stat_t { 1527 uint64_t value; 1528 1529 struct { 1530 #if defined(_BIG_ENDIAN) 1531 uint32_t msw; /* Most significant word */ 1532 uint32_t lsw; /* Least significant word */ 1533 #elif defined(_LITTLE_ENDIAN) 1534 uint32_t lsw; /* Least significant word */ 1535 uint32_t msw; /* Most significant word */ 1536 #endif 1537 } val; 1538 struct { 1539 #if defined(_BIG_ENDIAN) 1540 uint32_t w1; 1541 #endif 1542 struct { 1543 #if defined(_BIT_FIELDS_HTOL) 1544 uint32_t res0 : 23; 1545 uint32_t ext_stat : 1; 1546 uint32_t res1 : 2; 1547 uint32_t an_complete : 1; 1548 uint32_t remote_fault : 1; 1549 uint32_t an_able : 1; 1550 uint32_t link_stat : 1; 1551 uint32_t jabber_detect : 1; 1552 uint32_t ext_cap : 1; 1553 #elif defined(_BIT_FIELDS_LTOH) 1554 uint32_t ext_cap : 1; 1555 uint32_t jabber_detect : 1; 1556 uint32_t link_stat : 1; 1557 uint32_t an_able : 1; 1558 uint32_t remote_fault : 1; 1559 uint32_t an_complete : 1; 1560 uint32_t res1 : 2; 1561 uint32_t ext_stat : 1; 1562 uint32_t res0 : 23; 1563 #endif 1564 } w0; 1565 1566 #if defined(_LITTLE_ENDIAN) 1567 uint32_t w1; 1568 #endif 1569 } bits; 1570 } pcs_stat_t; 1571 1572 #define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex */ 1573 #define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex */ 1574 #define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE sym */ 1575 #define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE asym */ 1576 #define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault */ 1577 #define PCS_MII_ADVERT_RF_SHIFT 12 1578 #define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */ 1579 #define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */ 1580 1581 #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD 1582 #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD 1583 #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE 1584 #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE 1585 #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK 1586 #define PCS_MII_LPA_RF_SHIFT PCS_MII_ADVERT_RF_SHIFT 1587 #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK 1588 #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE 1589 1590 typedef union _pcs_anar_t { 1591 uint64_t value; 1592 1593 struct { 1594 #if defined(_BIG_ENDIAN) 1595 uint32_t msw; /* Most significant word */ 1596 uint32_t lsw; /* Least significant word */ 1597 #elif defined(_LITTLE_ENDIAN) 1598 uint32_t lsw; /* Least significant word */ 1599 uint32_t msw; /* Most significant word */ 1600 #endif 1601 } val; 1602 struct { 1603 #if defined(_BIG_ENDIAN) 1604 uint32_t w1; 1605 #endif 1606 struct { 1607 #if defined(_BIT_FIELDS_HTOL) 1608 uint32_t res0 : 16; 1609 uint32_t next_page : 1; 1610 uint32_t ack : 1; 1611 uint32_t remote_fault : 2; 1612 uint32_t res1 : 3; 1613 uint32_t asm_pause : 1; 1614 uint32_t pause : 1; 1615 uint32_t half_duplex : 1; 1616 uint32_t full_duplex : 1; 1617 uint32_t res2 : 5; 1618 #elif defined(_BIT_FIELDS_LTOH) 1619 uint32_t res2 : 5; 1620 uint32_t full_duplex : 1; 1621 uint32_t half_duplex : 1; 1622 uint32_t pause : 1; 1623 uint32_t asm_pause : 1; 1624 uint32_t res1 : 3; 1625 uint32_t remore_fault : 2; 1626 uint32_t ack : 1; 1627 uint32_t next_page : 1; 1628 uint32_t res0 : 16; 1629 #endif 1630 } w0; 1631 1632 #if defined(_LITTLE_ENDIAN) 1633 uint32_t w1; 1634 #endif 1635 } bits; 1636 } pcs_anar_t, *p_pcs_anar_t; 1637 1638 #define PCS_CFG_EN 0x0001 /* enable PCS. */ 1639 #define PCS_CFG_SD_OVERRIDE 0x0002 1640 #define PCS_CFG_SD_ACTIVE_LOW 0x0004 /* sig detect active low */ 1641 #define PCS_CFG_JITTER_STUDY_MASK 0x0018 /* jitter measurements */ 1642 #define PCS_CFG_JITTER_STUDY_SHIFT 4 1643 #define PCS_CFG_10MS_TIMER_OVERRIDE 0x0020 /* shortens autoneg timer */ 1644 #define PCS_CFG_MASK 0x0040 /* PCS global mask bit */ 1645 1646 typedef union _pcs_cfg_t { 1647 uint64_t value; 1648 1649 struct { 1650 #if defined(_BIG_ENDIAN) 1651 uint32_t msw; /* Most significant word */ 1652 uint32_t lsw; /* Least significant word */ 1653 #elif defined(_LITTLE_ENDIAN) 1654 uint32_t lsw; /* Least significant word */ 1655 uint32_t msw; /* Most significant word */ 1656 #endif 1657 } val; 1658 struct { 1659 #if defined(_BIG_ENDIAN) 1660 uint32_t w1; 1661 #endif 1662 struct { 1663 #if defined(_BIT_FIELDS_HTOL) 1664 uint32_t res0 : 25; 1665 uint32_t mask : 1; 1666 uint32_t override_10ms_timer : 1; 1667 uint32_t jitter_study : 2; 1668 uint32_t sig_det_a_low : 1; 1669 uint32_t sig_det_override : 1; 1670 uint32_t enable : 1; 1671 #elif defined(_BIT_FIELDS_LTOH) 1672 uint32_t enable : 1; 1673 uint32_t sig_det_override : 1; 1674 uint32_t sig_det_a_low : 1; 1675 uint32_t jitter_study : 2; 1676 uint32_t override_10ms_timer : 1; 1677 uint32_t mask : 1; 1678 uint32_t res0 : 25; 1679 #endif 1680 } w0; 1681 1682 #if defined(_LITTLE_ENDIAN) 1683 uint32_t w1; 1684 #endif 1685 } bits; 1686 } pcs_cfg_t, *p_pcs_cfg_t; 1687 1688 1689 /* used for diagnostic purposes. bits 20-22 autoclear on read */ 1690 #define PCS_SM_TX_STATE_MASK 0x0000000F /* Tx idle state mask */ 1691 #define PCS_SM_TX_STATE_SHIFT 0 1692 #define PCS_SM_RX_STATE_MASK 0x000000F0 /* Rx idle state mask */ 1693 #define PCS_SM_RX_STATE_SHIFT 4 1694 #define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* loss of sync state mask */ 1695 #define PCS_SM_WORD_SYNC_STATE_SHIFT 8 1696 #define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* sequence detect */ 1697 #define PCS_SM_SEQ_DETECT_STATE_SHIFT 11 1698 #define PCS_SM_LINK_STATE_MASK 0x0001E000 /* link state */ 1699 #define PCS_SM_LINK_STATE_SHIFT 13 1700 #define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link */ 1701 #define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of sync */ 1702 #define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect fail */ 1703 #define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* receipt of breaklink */ 1704 #define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes initializing */ 1705 #define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable */ 1706 #define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not achieved */ 1707 #define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes */ 1708 #define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* linkpartner send C code */ 1709 1710 typedef union _pcs_stat_mc_t { 1711 uint64_t value; 1712 1713 struct { 1714 #if defined(_BIG_ENDIAN) 1715 uint32_t msw; /* Most significant word */ 1716 uint32_t lsw; /* Least significant word */ 1717 #elif defined(_LITTLE_ENDIAN) 1718 uint32_t lsw; /* Least significant word */ 1719 uint32_t msw; /* Most significant word */ 1720 #endif 1721 } val; 1722 struct { 1723 #if defined(_BIG_ENDIAN) 1724 uint32_t w1; 1725 #endif 1726 struct { 1727 #if defined(_BIT_FIELDS_HTOL) 1728 uint32_t res2 : 2; 1729 uint32_t lnk_dwn_ni : 1; 1730 uint32_t lnk_dwn_wc : 1; 1731 uint32_t lnk_dwn_ls : 1; 1732 uint32_t lnk_dwn_nc : 1; 1733 uint32_t lnk_dwn_ser : 1; 1734 uint32_t lnk_loss_bc : 1; 1735 uint32_t res1 : 1; 1736 uint32_t loss_sd : 1; 1737 uint32_t lnk_loss_sync : 1; 1738 uint32_t lnk_loss_c : 1; 1739 uint32_t res0 : 3; 1740 uint32_t link_cfg_stat : 4; 1741 uint32_t seq_detc_stat : 2; 1742 uint32_t word_sync : 3; 1743 uint32_t rx_ctrl : 4; 1744 uint32_t tx_ctrl : 4; 1745 #elif defined(_BIT_FIELDS_LTOH) 1746 uint32_t tx_ctrl : 4; 1747 uint32_t rx_ctrl : 4; 1748 uint32_t word_sync : 3; 1749 uint32_t seq_detc_stat : 2; 1750 uint32_t link_cfg_stat : 4; 1751 uint32_t res0 : 3; 1752 uint32_t lnk_loss_c : 1; 1753 uint32_t lnk_loss_sync : 1; 1754 uint32_t loss_sd : 1; 1755 uint32_t res1 : 1; 1756 uint32_t lnk_loss_bc : 1; 1757 uint32_t lnk_dwn_ser : 1; 1758 uint32_t lnk_dwn_nc : 1; 1759 uint32_t lnk_dwn_ls : 1; 1760 uint32_t lnk_dwn_wc : 1; 1761 uint32_t lnk_dwn_ni : 1; 1762 uint32_t res2 : 2; 1763 #endif 1764 } w0; 1765 1766 #if defined(_LITTLE_ENDIAN) 1767 uint32_t w1; 1768 #endif 1769 } bits; 1770 } pcs_stat_mc_t, *p_pcs_stat_mc_t; 1771 1772 #define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed */ 1773 1774 /* 1775 * control which network interface is used. no more than one bit should 1776 * be set. 1777 */ 1778 #define PCS_DATAPATH_MODE_PCS 0 /* Internal PCS is used */ 1779 #define PCS_DATAPATH_MODE_MII 0x00000002 /* GMII/RGMII is selected. */ 1780 1781 #define PCS_PACKET_COUNT_TX_MASK 0x000007FF /* pkts xmitted by PCS */ 1782 #define PCS_PACKET_COUNT_RX_MASK 0x07FF0000 /* pkts recvd by PCS */ 1783 #define PCS_PACKET_COUNT_RX_SHIFT 16 1784 1785 /* 1786 * ******************** XPCS registers ********************************* 1787 */ 1788 1789 /* XPCS Base 10G Control1 Register */ 1790 #define XPCS_CTRL1_RST 0x8000 /* Self clearing reset. */ 1791 #define XPCS_CTRL1_LOOPBK 0x4000 /* xpcs Loopback */ 1792 #define XPCS_CTRL1_SPEED_SEL_3 0x2000 /* 1 indicates 10G speed */ 1793 #define XPCS_CTRL1_LOW_PWR 0x0800 /* low power mode. */ 1794 #define XPCS_CTRL1_SPEED_SEL_1 0x0040 /* 1 indicates 10G speed */ 1795 #define XPCS_CTRL1_SPEED_SEL_0_MASK 0x003c /* 0 indicates 10G speed. */ 1796 #define XPCS_CTRL1_SPEED_SEL_0_SHIFT 2 1797 1798 1799 1800 typedef union _xpcs_ctrl1_t { 1801 uint64_t value; 1802 1803 struct { 1804 #if defined(_BIG_ENDIAN) 1805 uint32_t msw; /* Most significant word */ 1806 uint32_t lsw; /* Least significant word */ 1807 #elif defined(_LITTLE_ENDIAN) 1808 uint32_t lsw; /* Least significant word */ 1809 uint32_t msw; /* Most significant word */ 1810 #endif 1811 } val; 1812 struct { 1813 #if defined(_BIG_ENDIAN) 1814 uint32_t w1; 1815 #endif 1816 struct { 1817 #if defined(_BIT_FIELDS_HTOL) 1818 uint32_t res3 : 16; 1819 uint32_t reset : 1; 1820 uint32_t csr_lb : 1; 1821 uint32_t csr_speed_sel3 : 1; 1822 uint32_t res2 : 1; 1823 uint32_t csr_low_pwr : 1; 1824 uint32_t res1 : 4; 1825 uint32_t csr_speed_sel1 : 1; 1826 uint32_t csr_speed_sel0 : 4; 1827 uint32_t res0 : 2; 1828 #elif defined(_BIT_FIELDS_LTOH) 1829 uint32_t res0 : 2; 1830 uint32_t csr_speed_sel0 : 4; 1831 uint32_t csr_speed_sel1 : 1; 1832 uint32_t res1 : 4; 1833 uint32_t csr_low_pwr : 1; 1834 uint32_t res2 : 1; 1835 uint32_t csr_speed_sel3 : 1; 1836 uint32_t csr_lb : 1; 1837 uint32_t reset : 1; 1838 uint32_t res3 : 16; 1839 #endif 1840 } w0; 1841 1842 #if defined(_LITTLE_ENDIAN) 1843 uint32_t w1; 1844 #endif 1845 } bits; 1846 } xpcs_ctrl1_t; 1847 1848 1849 /* XPCS Base 10G Status1 Register (Read Only) */ 1850 #define XPCS_STATUS1_FAULT 0x0080 1851 #define XPCS_STATUS1_RX_LINK_STATUS_UP 0x0004 /* Link status interrupt */ 1852 #define XPCS_STATUS1_LOW_POWER_ABILITY 0x0002 /* low power mode */ 1853 1854 1855 typedef union _xpcs_stat1_t { 1856 uint64_t value; 1857 1858 struct { 1859 #if defined(_BIG_ENDIAN) 1860 uint32_t msw; /* Most significant word */ 1861 uint32_t lsw; /* Least significant word */ 1862 #elif defined(_LITTLE_ENDIAN) 1863 uint32_t lsw; /* Least significant word */ 1864 uint32_t msw; /* Most significant word */ 1865 #endif 1866 } val; 1867 struct { 1868 #if defined(_BIG_ENDIAN) 1869 uint32_t w1; 1870 #endif 1871 struct { 1872 #if defined(_BIT_FIELDS_HTOL) 1873 uint32_t res4 : 16; 1874 uint32_t res3 : 8; 1875 uint32_t csr_fault : 1; 1876 uint32_t res1 : 4; 1877 uint32_t csr_rx_link_stat : 1; 1878 uint32_t csr_low_pwr_ability : 1; 1879 uint32_t res0 : 1; 1880 #elif defined(_BIT_FIELDS_LTOH) 1881 uint32_t res0 : 1; 1882 uint32_t csr_low_pwr_ability : 1; 1883 uint32_t csr_rx_link_stat : 1; 1884 uint32_t res1 : 4; 1885 uint32_t csr_fault : 1; 1886 uint32_t res3 : 8; 1887 uint32_t res4 : 16; 1888 #endif 1889 } w0; 1890 1891 #if defined(_LITTLE_ENDIAN) 1892 uint32_t w1; 1893 #endif 1894 } bits; 1895 } xpcs_stat1_t; 1896 1897 1898 /* XPCS Base Speed Ability Register. Indicates 10G capability */ 1899 #define XPCS_SPEED_ABILITY_10_GIG 0x0001 1900 1901 1902 typedef union _xpcs_speed_ab_t { 1903 uint64_t value; 1904 1905 struct { 1906 #if defined(_BIG_ENDIAN) 1907 uint32_t msw; /* Most significant word */ 1908 uint32_t lsw; /* Least significant word */ 1909 #elif defined(_LITTLE_ENDIAN) 1910 uint32_t lsw; /* Least significant word */ 1911 uint32_t msw; /* Most significant word */ 1912 #endif 1913 } val; 1914 struct { 1915 #if defined(_BIG_ENDIAN) 1916 uint32_t w1; 1917 #endif 1918 struct { 1919 #if defined(_BIT_FIELDS_HTOL) 1920 uint32_t res1 : 16; 1921 uint32_t res0 : 15; 1922 uint32_t csr_10gig : 1; 1923 #elif defined(_BIT_FIELDS_LTOH) 1924 uint32_t csr_10gig : 1; 1925 uint32_t res0 : 15; 1926 uint32_t res1 : 16; 1927 #endif 1928 } w0; 1929 1930 #if defined(_LITTLE_ENDIAN) 1931 uint32_t w1; 1932 #endif 1933 } bits; 1934 } xpcs_speed_ab_t; 1935 1936 1937 /* XPCS Base 10G Devices in Package Register */ 1938 #define XPCS_DEV_IN_PKG_CSR_VENDOR2 0x80000000 1939 #define XPCS_DEV_IN_PKG_CSR_VENDOR1 0x40000000 1940 #define XPCS_DEV_IN_PKG_DTE_XS 0x00000020 1941 #define XPCS_DEV_IN_PKG_PHY_XS 0x00000010 1942 #define XPCS_DEV_IN_PKG_PCS 0x00000008 1943 #define XPCS_DEV_IN_PKG_WIS 0x00000004 1944 #define XPCS_DEV_IN_PKG_PMD_PMA 0x00000002 1945 #define XPCS_DEV_IN_PKG_CLS_22_REG 0x00000000 1946 1947 1948 1949 typedef union _xpcs_dev_in_pkg_t { 1950 uint64_t value; 1951 1952 struct { 1953 #if defined(_BIG_ENDIAN) 1954 uint32_t msw; /* Most significant word */ 1955 uint32_t lsw; /* Least significant word */ 1956 #elif defined(_LITTLE_ENDIAN) 1957 uint32_t lsw; /* Least significant word */ 1958 uint32_t msw; /* Most significant word */ 1959 #endif 1960 } val; 1961 struct { 1962 #if defined(_BIG_ENDIAN) 1963 uint32_t w1; 1964 #endif 1965 struct { 1966 #if defined(_BIT_FIELDS_HTOL) 1967 uint32_t csr_vendor2 : 1; 1968 uint32_t csr_vendor1 : 1; 1969 uint32_t res1 : 14; 1970 uint32_t res0 : 10; 1971 uint32_t dte_xs : 1; 1972 uint32_t phy_xs : 1; 1973 uint32_t pcs : 1; 1974 uint32_t wis : 1; 1975 uint32_t pmd_pma : 1; 1976 uint32_t clause_22_reg : 1; 1977 #elif defined(_BIT_FIELDS_LTOH) 1978 uint32_t clause_22_reg : 1; 1979 uint32_t pmd_pma : 1; 1980 uint32_t wis : 1; 1981 uint32_t pcs : 1; 1982 uint32_t phy_xs : 1; 1983 uint32_t dte_xs : 1; 1984 uint32_t res0 : 10; 1985 uint32_t res1 : 14; 1986 uint32_t csr_vendor1 : 1; 1987 uint32_t csr_vendor2 : 1; 1988 #endif 1989 } w0; 1990 1991 #if defined(_LITTLE_ENDIAN) 1992 uint32_t w1; 1993 #endif 1994 } bits; 1995 } xpcs_dev_in_pkg_t; 1996 1997 1998 /* XPCS Base 10G Control2 Register */ 1999 #define XPCS_PSC_SEL_MASK 0x0003 2000 #define PSC_SEL_10G_BASE_X_PCS 0x0001 2001 2002 2003 typedef union _xpcs_ctrl2_t { 2004 uint64_t value; 2005 2006 struct { 2007 #if defined(_BIG_ENDIAN) 2008 uint32_t msw; /* Most significant word */ 2009 uint32_t lsw; /* Least significant word */ 2010 #elif defined(_LITTLE_ENDIAN) 2011 uint32_t lsw; /* Least significant word */ 2012 uint32_t msw; /* Most significant word */ 2013 #endif 2014 } val; 2015 struct { 2016 #if defined(_BIG_ENDIAN) 2017 uint32_t w1; 2018 #endif 2019 struct { 2020 #if defined(_BIT_FIELDS_HTOL) 2021 uint32_t res1 : 16; 2022 uint32_t res0 : 14; 2023 uint32_t csr_psc_sel : 2; 2024 #elif defined(_BIT_FIELDS_LTOH) 2025 uint32_t csr_psc_sel : 2; 2026 uint32_t res0 : 14; 2027 uint32_t res1 : 16; 2028 #endif 2029 } w0; 2030 2031 #if defined(_LITTLE_ENDIAN) 2032 uint32_t w1; 2033 #endif 2034 } bits; 2035 } xpcs_ctrl2_t; 2036 2037 2038 /* XPCS Base10G Status2 Register */ 2039 #define XPCS_STATUS2_DEV_PRESENT_MASK 0xc000 /* ?????? */ 2040 #define XPCS_STATUS2_TX_FAULT 0x0800 /* Fault on tx path */ 2041 #define XPCS_STATUS2_RX_FAULT 0x0400 /* Fault on rx path */ 2042 #define XPCS_STATUS2_TEN_GBASE_W 0x0004 /* 10G-Base-W */ 2043 #define XPCS_STATUS2_TEN_GBASE_X 0x0002 /* 10G-Base-X */ 2044 #define XPCS_STATUS2_TEN_GBASE_R 0x0001 /* 10G-Base-R */ 2045 2046 typedef union _xpcs_stat2_t { 2047 uint64_t value; 2048 2049 struct { 2050 #if defined(_BIG_ENDIAN) 2051 uint32_t msw; /* Most significant word */ 2052 uint32_t lsw; /* Least significant word */ 2053 #elif defined(_LITTLE_ENDIAN) 2054 uint32_t lsw; /* Least significant word */ 2055 uint32_t msw; /* Most significant word */ 2056 #endif 2057 } val; 2058 struct { 2059 #if defined(_BIG_ENDIAN) 2060 uint32_t w1; 2061 #endif 2062 struct { 2063 #if defined(_BIT_FIELDS_HTOL) 2064 uint32_t res2 : 16; 2065 uint32_t csr_dev_pres : 2; 2066 uint32_t res1 : 2; 2067 uint32_t csr_tx_fault : 1; 2068 uint32_t csr_rx_fault : 1; 2069 uint32_t res0 : 7; 2070 uint32_t ten_gbase_w : 1; 2071 uint32_t ten_gbase_x : 1; 2072 uint32_t ten_gbase_r : 1; 2073 #elif defined(_BIT_FIELDS_LTOH) 2074 uint32_t ten_gbase_r : 1; 2075 uint32_t ten_gbase_x : 1; 2076 uint32_t ten_gbase_w : 1; 2077 uint32_t res0 : 7; 2078 uint32_t csr_rx_fault : 1; 2079 uint32_t csr_tx_fault : 1; 2080 uint32_t res1 : 2; 2081 uint32_t csr_dev_pres : 2; 2082 uint32_t res2 : 16; 2083 #endif 2084 } w0; 2085 2086 #if defined(_LITTLE_ENDIAN) 2087 uint32_t w1; 2088 #endif 2089 } bits; 2090 } xpcs_stat2_t; 2091 2092 2093 2094 /* XPCS Base10G Status Register */ 2095 #define XPCS_STATUS_LANE_ALIGN 0x1000 /* 10GBaseX PCS rx lanes align */ 2096 #define XPCS_STATUS_PATTERN_TEST_ABLE 0x0800 /* able to generate patterns. */ 2097 #define XPCS_STATUS_LANE3_SYNC 0x0008 /* Lane 3 is synchronized */ 2098 #define XPCS_STATUS_LANE2_SYNC 0x0004 /* Lane 2 is synchronized */ 2099 #define XPCS_STATUS_LANE1_SYNC 0x0002 /* Lane 1 is synchronized */ 2100 #define XPCS_STATUS_LANE0_SYNC 0x0001 /* Lane 0 is synchronized */ 2101 2102 typedef union _xpcs_stat_t { 2103 uint64_t value; 2104 2105 struct { 2106 #if defined(_BIG_ENDIAN) 2107 uint32_t msw; /* Most significant word */ 2108 uint32_t lsw; /* Least significant word */ 2109 #elif defined(_LITTLE_ENDIAN) 2110 uint32_t lsw; /* Least significant word */ 2111 uint32_t msw; /* Most significant word */ 2112 #endif 2113 } val; 2114 struct { 2115 #if defined(_BIG_ENDIAN) 2116 uint32_t w1; 2117 #endif 2118 struct { 2119 #if defined(_BIT_FIELDS_HTOL) 2120 uint32_t res2 : 16; 2121 uint32_t res1 : 3; 2122 uint32_t csr_lane_align : 1; 2123 uint32_t csr_pattern_test_able : 1; 2124 uint32_t res0 : 7; 2125 uint32_t csr_lane3_sync : 1; 2126 uint32_t csr_lane2_sync : 1; 2127 uint32_t csr_lane1_sync : 1; 2128 uint32_t csr_lane0_sync : 1; 2129 #elif defined(_BIT_FIELDS_LTOH) 2130 uint32_t csr_lane0_sync : 1; 2131 uint32_t csr_lane1_sync : 1; 2132 uint32_t csr_lane2_sync : 1; 2133 uint32_t csr_lane3_sync : 1; 2134 uint32_t res0 : 7; 2135 uint32_t csr_pat_test_able : 1; 2136 uint32_t csr_lane_align : 1; 2137 uint32_t res1 : 3; 2138 uint32_t res2 : 16; 2139 #endif 2140 } w0; 2141 2142 #if defined(_LITTLE_ENDIAN) 2143 uint32_t w1; 2144 #endif 2145 } bits; 2146 } xpcs_stat_t; 2147 2148 /* XPCS Base10G Test Control Register */ 2149 #define XPCS_TEST_CTRL_TX_TEST_ENABLE 0x0004 2150 #define XPCS_TEST_CTRL_TEST_PATTERN_SEL_MASK 0x0003 2151 #define TEST_PATTERN_HIGH_FREQ 0 2152 #define TEST_PATTERN_LOW_FREQ 1 2153 #define TEST_PATTERN_MIXED_FREQ 2 2154 2155 typedef union _xpcs_test_ctl_t { 2156 uint64_t value; 2157 2158 struct { 2159 #if defined(_BIG_ENDIAN) 2160 uint32_t msw; /* Most significant word */ 2161 uint32_t lsw; /* Least significant word */ 2162 #elif defined(_LITTLE_ENDIAN) 2163 uint32_t lsw; /* Least significant word */ 2164 uint32_t msw; /* Most significant word */ 2165 #endif 2166 } val; 2167 struct { 2168 #if defined(_BIG_ENDIAN) 2169 uint32_t w1; 2170 #endif 2171 struct { 2172 #if defined(_BIT_FIELDS_HTOL) 2173 uint32_t res1 : 16; 2174 uint32_t res0 : 13; 2175 uint32_t csr_tx_test_en : 1; 2176 uint32_t csr_test_pat_sel : 2; 2177 #elif defined(_BIT_FIELDS_LTOH) 2178 uint32_t csr_test_pat_sel : 2; 2179 uint32_t csr_tx_test_en : 1; 2180 uint32_t res0 : 13; 2181 uint32_t res1 : 16; 2182 #endif 2183 } w0; 2184 2185 #if defined(_LITTLE_ENDIAN) 2186 uint32_t w1; 2187 #endif 2188 } bits; 2189 } xpcs_test_ctl_t; 2190 2191 /* XPCS Base10G Diagnostic Register */ 2192 #define XPCS_DIAG_EB_ALIGN_ERR3 0x40 2193 #define XPCS_DIAG_EB_ALIGN_ERR2 0x20 2194 #define XPCS_DIAG_EB_ALIGN_ERR1 0x10 2195 #define XPCS_DIAG_EB_DESKEW_OK 0x08 2196 #define XPCS_DIAG_EB_ALIGN_DET3 0x04 2197 #define XPCS_DIAG_EB_ALIGN_DET2 0x02 2198 #define XPCS_DIAG_EB_ALIGN_DET1 0x01 2199 #define XPCS_DIAG_EB_DESKEW_LOSS 0 2200 2201 #define XPCS_DIAG_SYNC_3_INVALID 0x8 2202 #define XPCS_DIAG_SYNC_2_INVALID 0x4 2203 #define XPCS_DIAG_SYNC_1_INVALID 0x2 2204 #define XPCS_DIAG_SYNC_IN_SYNC 0x1 2205 #define XPCS_DIAG_SYNC_LOSS_SYNC 0 2206 2207 #define XPCS_RX_SM_RECEIVE_STATE 1 2208 #define XPCS_RX_SM_FAULT_STATE 0 2209 2210 typedef union _xpcs_diag_t { 2211 uint64_t value; 2212 2213 struct { 2214 #if defined(_BIG_ENDIAN) 2215 uint32_t msw; /* Most significant word */ 2216 uint32_t lsw; /* Least significant word */ 2217 #elif defined(_LITTLE_ENDIAN) 2218 uint32_t lsw; /* Least significant word */ 2219 uint32_t msw; /* Most significant word */ 2220 #endif 2221 } val; 2222 struct { 2223 #if defined(_BIG_ENDIAN) 2224 uint32_t w1; 2225 #endif 2226 struct { 2227 #if defined(_BIT_FIELDS_HTOL) 2228 uint32_t res1 : 7; 2229 uint32_t sync_sm_lane3 : 4; 2230 uint32_t sync_sm_lane2 : 4; 2231 uint32_t sync_sm_lane1 : 4; 2232 uint32_t sync_sm_lane0 : 4; 2233 uint32_t elastic_buffer_sm : 8; 2234 uint32_t receive_sm : 1; 2235 #elif defined(_BIT_FIELDS_LTOH) 2236 uint32_t receive_sm : 1; 2237 uint32_t elastic_buffer_sm : 8; 2238 uint32_t sync_sm_lane0 : 4; 2239 uint32_t sync_sm_lane1 : 4; 2240 uint32_t sync_sm_lane2 : 4; 2241 uint32_t sync_sm_lane3 : 4; 2242 uint32_t res1 : 7; 2243 #endif 2244 } w0; 2245 2246 #if defined(_LITTLE_ENDIAN) 2247 uint32_t w1; 2248 #endif 2249 } bits; 2250 } xpcs_diag_t; 2251 2252 /* XPCS Base10G Tx State Machine Register */ 2253 #define XPCS_TX_SM_SEND_UNDERRUN 0x9 2254 #define XPCS_TX_SM_SEND_RANDOM_Q 0x8 2255 #define XPCS_TX_SM_SEND_RANDOM_K 0x7 2256 #define XPCS_TX_SM_SEND_RANDOM_A 0x6 2257 #define XPCS_TX_SM_SEND_RANDOM_R 0x5 2258 #define XPCS_TX_SM_SEND_Q 0x4 2259 #define XPCS_TX_SM_SEND_K 0x3 2260 #define XPCS_TX_SM_SEND_A 0x2 2261 #define XPCS_TX_SM_SEND_SDP 0x1 2262 #define XPCS_TX_SM_SEND_DATA 0 2263 2264 /* XPCS Base10G Configuration Register */ 2265 #define XPCS_CFG_VENDOR_DBG_SEL_MASK 0x78 2266 #define XPCS_CFG_VENDOR_DBG_SEL_SHIFT 3 2267 #define XPCS_CFG_BYPASS_SIG_DETECT 0x0004 2268 #define XPCS_CFG_ENABLE_TX_BUFFERS 0x0002 2269 #define XPCS_CFG_XPCS_ENABLE 0x0001 2270 2271 typedef union _xpcs_config_t { 2272 uint64_t value; 2273 2274 struct { 2275 #if defined(_BIG_ENDIAN) 2276 uint32_t msw; /* Most significant word */ 2277 uint32_t lsw; /* Least significant word */ 2278 #elif defined(_LITTLE_ENDIAN) 2279 uint32_t lsw; /* Least significant word */ 2280 uint32_t msw; /* Most significant word */ 2281 #endif 2282 } val; 2283 struct { 2284 #if defined(_BIG_ENDIAN) 2285 uint32_t w1; 2286 #endif 2287 struct { 2288 #if defined(_BIT_FIELDS_HTOL) 2289 uint32_t res1 : 16; 2290 uint32_t res0 : 9; 2291 uint32_t csr_vendor_dbg_sel : 4; 2292 uint32_t csr_bypass_sig_detect : 1; 2293 uint32_t csr_en_tx_buf : 1; 2294 uint32_t csr_xpcs_en : 1; 2295 #elif defined(_BIT_FIELDS_LTOH) 2296 uint32_t csr_xpcs_en : 1; 2297 uint32_t csr_en_tx_buf : 1; 2298 uint32_t csr_bypass_sig_detect : 1; 2299 uint32_t csr_vendor_dbg_sel : 4; 2300 uint32_t res0 : 9; 2301 uint32_t res1 : 16; 2302 #endif 2303 } w0; 2304 2305 #if defined(_LITTLE_ENDIAN) 2306 uint32_t w1; 2307 #endif 2308 } bits; 2309 } xpcs_config_t; 2310 2311 2312 2313 /* XPCS Base10G Mask1 Register */ 2314 #define XPCS_MASK1_FAULT_MASK 0x0080 /* mask fault interrupt. */ 2315 #define XPCS_MASK1_RX_LINK_STATUS_MASK 0x0040 /* mask linkstat interrupt */ 2316 2317 /* XPCS Base10G Packet Counter */ 2318 #define XPCS_PKT_CNTR_TX_PKT_CNT_MASK 0xffff0000 2319 #define XPCS_PKT_CNTR_TX_PKT_CNT_SHIFT 16 2320 #define XPCS_PKT_CNTR_RX_PKT_CNT_MASK 0x0000ffff 2321 #define XPCS_PKT_CNTR_RX_PKT_CNT_SHIFT 0 2322 2323 /* XPCS Base10G TX State Machine status register */ 2324 #define XPCS_TX_STATE_MC_TX_STATE_MASK 0x0f 2325 #define XPCS_DESKEW_ERR_CNTR_MASK 0xff 2326 2327 /* XPCS Base10G Lane symbol error counters */ 2328 #define XPCS_SYM_ERR_CNT_L1_MASK 0xffff0000 2329 #define XPCS_SYM_ERR_CNT_L0_MASK 0x0000ffff 2330 #define XPCS_SYM_ERR_CNT_L3_MASK 0xffff0000 2331 #define XPCS_SYM_ERR_CNT_L2_MASK 0x0000ffff 2332 2333 #define XPCS_SYM_ERR_CNT_MULTIPLIER 16 2334 2335 /* ESR Reset Register */ 2336 #define ESR_RESET_1 2 2337 #define ESR_RESET_0 1 2338 2339 /* ESR Configuration Register */ 2340 #define ESR_BLUNT_END_LOOPBACK 2 2341 #define ESR_FORCE_SERDES_SERDES_RDY 1 2342 2343 /* ESR Neptune Serdes PLL Configuration */ 2344 #define ESR_PLL_CFG_FBDIV_0 0x1 2345 #define ESR_PLL_CFG_FBDIV_1 0x2 2346 #define ESR_PLL_CFG_FBDIV_2 0x4 2347 #define ESR_PLL_CFG_HALF_RATE_0 0x8 2348 #define ESR_PLL_CFG_HALF_RATE_1 0x10 2349 #define ESR_PLL_CFG_HALF_RATE_2 0x20 2350 #define ESR_PLL_CFG_HALF_RATE_3 0x40 2351 2352 /* ESR Neptune Serdes Control Register */ 2353 #define ESR_CTL_EN_SYNCDET_0 0x00000001 2354 #define ESR_CTL_EN_SYNCDET_1 0x00000002 2355 #define ESR_CTL_EN_SYNCDET_2 0x00000004 2356 #define ESR_CTL_EN_SYNCDET_3 0x00000008 2357 #define ESR_CTL_OUT_EMPH_0_MASK 0x00000070 2358 #define ESR_CTL_OUT_EMPH_0_SHIFT 4 2359 #define ESR_CTL_OUT_EMPH_1_MASK 0x00000380 2360 #define ESR_CTL_OUT_EMPH_1_SHIFT 7 2361 #define ESR_CTL_OUT_EMPH_2_MASK 0x00001c00 2362 #define ESR_CTL_OUT_EMPH_2_SHIFT 10 2363 #define ESR_CTL_OUT_EMPH_3_MASK 0x0000e000 2364 #define ESR_CTL_OUT_EMPH_3_SHIFT 13 2365 #define ESR_CTL_LOSADJ_0_MASK 0x00070000 2366 #define ESR_CTL_LOSADJ_0_SHIFT 16 2367 #define ESR_CTL_LOSADJ_1_MASK 0x00380000 2368 #define ESR_CTL_LOSADJ_1_SHIFT 19 2369 #define ESR_CTL_LOSADJ_2_MASK 0x01c00000 2370 #define ESR_CTL_LOSADJ_2_SHIFT 22 2371 #define ESR_CTL_LOSADJ_3_MASK 0x0e000000 2372 #define ESR_CTL_LOSADJ_3_SHIFT 25 2373 #define ESR_CTL_RXITERM_0 0x10000000 2374 #define ESR_CTL_RXITERM_1 0x20000000 2375 #define ESR_CTL_RXITERM_2 0x40000000 2376 #define ESR_CTL_RXITERM_3 0x80000000 2377 2378 /* ESR Neptune Serdes Test Configuration Register */ 2379 #define ESR_TSTCFG_LBTEST_MD_0_MASK 0x00000003 2380 #define ESR_TSTCFG_LBTEST_MD_0_SHIFT 0 2381 #define ESR_TSTCFG_LBTEST_MD_1_MASK 0x0000000c 2382 #define ESR_TSTCFG_LBTEST_MD_1_SHIFT 2 2383 #define ESR_TSTCFG_LBTEST_MD_2_MASK 0x00000030 2384 #define ESR_TSTCFG_LBTEST_MD_2_SHIFT 4 2385 #define ESR_TSTCFG_LBTEST_MD_3_MASK 0x000000c0 2386 #define ESR_TSTCFG_LBTEST_MD_3_SHIFT 6 2387 2388 /* ESR Neptune Ethernet RGMII Configuration Register */ 2389 #define ESR_RGMII_PT0_IN_USE 0x00000001 2390 #define ESR_RGMII_PT1_IN_USE 0x00000002 2391 #define ESR_RGMII_PT2_IN_USE 0x00000004 2392 #define ESR_RGMII_PT3_IN_USE 0x00000008 2393 #define ESR_RGMII_REG_RW_TEST 0x00000010 2394 2395 /* ESR Internal Signals Observation Register */ 2396 #define ESR_SIG_MASK 0xFFFFFFFF 2397 #define ESR_SIG_P0_BITS_MASK 0x33E0000F 2398 #define ESR_SIG_P1_BITS_MASK 0x0C1F00F0 2399 #define ESR_SIG_SERDES_RDY0_P0 0x20000000 2400 #define ESR_SIG_DETECT0_P0 0x10000000 2401 #define ESR_SIG_SERDES_RDY0_P1 0x08000000 2402 #define ESR_SIG_DETECT0_P1 0x04000000 2403 #define ESR_SIG_XSERDES_RDY_P0 0x02000000 2404 #define ESR_SIG_XDETECT_P0_CH3 0x01000000 2405 #define ESR_SIG_XDETECT_P0_CH2 0x00800000 2406 #define ESR_SIG_XDETECT_P0_CH1 0x00400000 2407 #define ESR_SIG_XDETECT_P0_CH0 0x00200000 2408 #define ESR_SIG_XSERDES_RDY_P1 0x00100000 2409 #define ESR_SIG_XDETECT_P1_CH3 0x00080000 2410 #define ESR_SIG_XDETECT_P1_CH2 0x00040000 2411 #define ESR_SIG_XDETECT_P1_CH1 0x00020000 2412 #define ESR_SIG_XDETECT_P1_CH0 0x00010000 2413 #define ESR_SIG_LOS_P1_CH3 0x00000080 2414 #define ESR_SIG_LOS_P1_CH2 0x00000040 2415 #define ESR_SIG_LOS_P1_CH1 0x00000020 2416 #define ESR_SIG_LOS_P1_CH0 0x00000010 2417 #define ESR_SIG_LOS_P0_CH3 0x00000008 2418 #define ESR_SIG_LOS_P0_CH2 0x00000004 2419 #define ESR_SIG_LOS_P0_CH1 0x00000002 2420 #define ESR_SIG_LOS_P0_CH0 0x00000001 2421 2422 /* ESR Debug Selection Register */ 2423 #define ESR_DEBUG_SEL_MASK 0x00000003f 2424 2425 /* ESR Test Configuration Register */ 2426 #define ESR_NO_LOOPBACK_CH3 (0x0 << 6) 2427 #define ESR_EWRAP_CH3 (0x1 << 6) 2428 #define ESR_PAD_LOOPBACK_CH3 (0x2 << 6) 2429 #define ESR_REVLOOPBACK_CH3 (0x3 << 6) 2430 #define ESR_NO_LOOPBACK_CH2 (0x0 << 4) 2431 #define ESR_EWRAP_CH2 (0x1 << 4) 2432 #define ESR_PAD_LOOPBACK_CH2 (0x2 << 4) 2433 #define ESR_REVLOOPBACK_CH2 (0x3 << 4) 2434 #define ESR_NO_LOOPBACK_CH1 (0x0 << 2) 2435 #define ESR_EWRAP_CH1 (0x1 << 2) 2436 #define ESR_PAD_LOOPBACK_CH1 (0x2 << 2) 2437 #define ESR_REVLOOPBACK_CH1 (0x3 << 2) 2438 #define ESR_NO_LOOPBACK_CH0 0x0 2439 #define ESR_EWRAP_CH0 0x1 2440 #define ESR_PAD_LOOPBACK_CH0 0x2 2441 #define ESR_REVLOOPBACK_CH0 0x3 2442 2443 /* convert values */ 2444 #define NXGE_BASE(x, y) \ 2445 (((y) << (x ## _SHIFT)) & (x ## _MASK)) 2446 2447 #define NXGE_VAL_GET(fieldname, regval) \ 2448 (((regval) & ((fieldname) ## _MASK)) >> ((fieldname) ## _SHIFT)) 2449 2450 #define NXGE_VAL_SET(fieldname, regval, val) \ 2451 { \ 2452 (regval) &= ~((fieldname) ## _MASK); \ 2453 (regval) |= ((val) << (fieldname ## _SHIFT)); \ 2454 } 2455 2456 2457 #ifdef __cplusplus 2458 } 2459 #endif 2460 2461 #endif /* _SYS_MAC_NXGE_MAC_HW_H */ 2462