1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#ifndef	_SYS_MAC_NXGE_MAC_HW_H
27#define	_SYS_MAC_NXGE_MAC_HW_H
28
29#pragma ident	"%Z%%M%	%I%	%E% SMI"
30
31#ifdef	__cplusplus
32extern "C" {
33#endif
34
35#include <nxge_defs.h>
36
37/* -------------------------- From May's template --------------------------- */
38
39#define	NXGE_1GETHERMIN			255
40#define	NXGE_ETHERMIN			97
41#define	NXGE_MAX_HEADER			250
42
43/* Hardware reset */
44typedef enum  {
45	NXGE_TX_DISABLE,			/* Disable Tx side */
46	NXGE_RX_DISABLE,			/* Disable Rx side */
47	NXGE_CHIP_RESET				/* Full chip reset */
48} nxge_reset_t;
49
50#define	NXGE_DELAY_AFTER_TXRX		10000	/* 10ms after idling rx/tx */
51#define	NXGE_DELAY_AFTER_RESET		1000	/* 1ms after the reset */
52#define	NXGE_DELAY_AFTER_EE_RESET	10000	/* 10ms after EEPROM reset */
53#define	NXGE_DELAY_AFTER_LINK_RESET	13	/* 13 Us after link reset */
54#define	NXGE_LINK_RESETS		8	/* Max PHY resets to wait for */
55						/* linkup */
56
57#define	FILTER_M_CTL 			0xDCEF1
58#define	HASH_BITS			8
59#define	NMCFILTER_BITS			(1 << HASH_BITS)
60#define	HASH_REG_WIDTH			16
61#define	BROADCAST_HASH_WORD		0x0f
62#define	BROADCAST_HASH_BIT		0x8000
63#define	NMCFILTER_REGS			NMCFILTER_BITS / HASH_REG_WIDTH
64					/* Number of multicast filter regs */
65
66/* -------------------------------------------------------------------------- */
67
68#define	XMAC_PORT_0			0
69#define	XMAC_PORT_1			1
70#define	BMAC_PORT_0			2
71#define	BMAC_PORT_1			3
72
73#define	MAC_RESET_WAIT			10	/* usecs */
74
75#define	MAC_ADDR_REG_MASK		0xFFFF
76
77/*
78 * Neptune port PHY type and Speed encoding.
79 *
80 * Per port, 4 bits are reserved for port speed (1G/10G) and 4 bits
81 * are reserved for port PHY type (Copper/Fibre). Bits 0 thru 3 are for port0
82 * speed, bits 4 thru 7 are for port1 speed, bits 8 thru 11 are for port2 speed
83 * and bits 12 thru 15 are for port3 speed. Thus, the first 16 bits hold the
84 * speed encoding for the 4 ports. The next 16 bits (16 thru 31) hold the phy
85 * type encoding for the ports 0 thru 3.
86 *
87 *  p3phy  p2phy  p1phy  p0phy  p3spd p2spd  p1spd p0spd
88 *    |      |      |      |      |     |      |     |
89 *   ---    ---    ---    ---    ---   ---    ---   ---
90 *  /   \  /   \  /   \  /   \  /   \ /   \  /   \ /   \
91 * 31..28 27..24 23..20 19..16 15..12 11.. 8 7.. 4 3.. 0
92 */
93
94#define	NXGE_PORT_SPD_NONE	0x0
95#define	NXGE_PORT_SPD_1G	0x1
96#define	NXGE_PORT_SPD_10G	0x2
97#define	NXGE_PORT_SPD_RSVD	0x7
98
99#define	NXGE_PHY_NONE		0x0
100#define	NXGE_PHY_COPPER		0x1
101#define	NXGE_PHY_FIBRE		0x2
102#define	NXGE_PHY_SERDES		0x3
103#define	NXGE_PHY_RGMII_FIBER	0x4
104#define	NXGE_PHY_TN1010		0x5
105#define	NXGE_PHY_RSVD		0x7
106
107#define	NXGE_PORT_SPD_SHIFT	0
108#define	NXGE_PORT_SPD_MASK	0x0f
109
110#define	NXGE_PHY_SHIFT		16
111#define	NXGE_PHY_MASK		0x0f0000
112
113/*
114 * "xgc" as a possible value for the device property "phy-type"
115 * was intended for the portmode == PORT_10G_COPPER case. But
116 * the first 10G copper network I/O device available is the
117 * TN1010 based copper XAUI card and we use PORT_10G_TN1010 or
118 * PORT_1G_TN1010 as the portmode, so PORT_10G_COPPER is never
119 * used as portmode. The driver code related to PORT_10G_COPPER
120 * is kept in the driver as a place holder for possble future
121 * 10G copper devices.
122 */
123#define	NXGE_PORT_10G_COPPER	(NXGE_PORT_SPD_10G |	\
124	(NXGE_PHY_COPPER << NXGE_PHY_SHIFT))
125
126#define	NXGE_PORT_1G_COPPER	(NXGE_PORT_SPD_1G |	\
127	(NXGE_PHY_COPPER << NXGE_PHY_SHIFT))
128#define	NXGE_PORT_1G_FIBRE	(NXGE_PORT_SPD_1G |	\
129	(NXGE_PHY_FIBRE << NXGE_PHY_SHIFT))
130#define	NXGE_PORT_10G_FIBRE	(NXGE_PORT_SPD_10G |	\
131	(NXGE_PHY_FIBRE << NXGE_PHY_SHIFT))
132#define	NXGE_PORT_1G_SERDES	(NXGE_PORT_SPD_1G |	\
133	(NXGE_PHY_SERDES << NXGE_PHY_SHIFT))
134#define	NXGE_PORT_10G_SERDES	(NXGE_PORT_SPD_10G |	\
135	(NXGE_PHY_SERDES << NXGE_PHY_SHIFT))
136#define	NXGE_PORT_1G_RGMII_FIBER	(NXGE_PORT_SPD_1G |	\
137	(NXGE_PHY_RGMII_FIBER << NXGE_PHY_SHIFT))
138
139/* The speed of TN1010 will be determined by each nxge instance */
140#define	NXGE_PORT_TN1010	(NXGE_PORT_SPD_NONE |	\
141	(NXGE_PHY_TN1010 << NXGE_PHY_SHIFT))
142
143#define	NXGE_PORT_NONE		(NXGE_PORT_SPD_NONE |	\
144	(NXGE_PHY_NONE << NXGE_PHY_SHIFT))
145#define	NXGE_PORT_RSVD		(NXGE_PORT_SPD_RSVD |	\
146	(NXGE_PHY_RSVD << NXGE_PHY_SHIFT))
147
148#define	NXGE_PORT_TYPE_MASK	(NXGE_PORT_SPD_MASK | NXGE_PHY_MASK)
149
150/* number of bits used for phy/spd encoding per port */
151#define	NXGE_PORT_TYPE_SHIFT	4
152
153/* Network Modes */
154
155typedef enum nxge_network_mode {
156	NET_2_10GE_FIBER = 1,
157	NET_2_10GE_COPPER,
158	NET_1_10GE_FIBER_3_1GE_COPPER,
159	NET_1_10GE_COPPER_3_1GE_COPPER,
160	NET_1_10GE_FIBER_3_1GE_FIBER,
161	NET_1_10GE_COPPER_3_1GE_FIBER,
162	NET_2_1GE_FIBER_2_1GE_COPPER,
163	NET_QGE_FIBER,
164	NET_QGE_COPPER
165} nxge_network_mode_t;
166
167typedef	enum nxge_port {
168	PORT_TYPE_XMAC = 1,
169	PORT_TYPE_BMAC,
170	PORT_TYPE_LOGICAL
171} nxge_port_t;
172
173typedef	enum nxge_port_mode {
174	PORT_1G_COPPER = 1,
175	PORT_1G_FIBER,
176	PORT_10G_COPPER,
177	PORT_10G_FIBER,
178	PORT_10G_SERDES,	/* Port0 or 1 of Alonso or Monza */
179	PORT_1G_SERDES,		/* Port0 or 1 of Alonso or Monza */
180	PORT_1G_RGMII_FIBER,	/* Port2 or 3 of Alonso or ARTM  */
181	PORT_HSP_MODE,
182	PORT_LOGICAL,
183	PORT_1G_TN1010,		/* Teranetics PHY in 1G mode */
184	PORT_10G_TN1010		/* Teranetics PHY in 10G mode */
185} nxge_port_mode_t;
186
187typedef	enum nxge_linkchk_mode {
188	LINKCHK_INTR = 1,
189	LINKCHK_TIMER
190} nxge_linkchk_mode_t;
191
192typedef enum {
193	LINK_INTR_STOP,
194	LINK_INTR_START
195} link_intr_enable_t, *link_intr_enable_pt;
196
197typedef	enum {
198	LINK_MONITOR_STOP,
199	LINK_MONITOR_START,
200	LINK_MONITOR_STOPPING
201} link_mon_enable_t, *link_mon_enable_pt;
202
203typedef enum {
204	NO_XCVR,
205	INT_MII_XCVR,
206	EXT_MII_XCVR,
207	PCS_XCVR,
208	XPCS_XCVR,
209	HSP_XCVR,
210	LOGICAL_XCVR
211} xcvr_inuse_t;
212
213/* macros for port offset calculations */
214
215#define	PORT_1_OFFSET			0x6000
216#define	PORT_GT_1_OFFSET		0x4000
217
218/* XMAC address macros */
219
220#define	XMAC_ADDR_OFFSET_0		0
221#define	XMAC_ADDR_OFFSET_1		0x6000
222
223#define	XMAC_ADDR_OFFSET(port_num)\
224	(XMAC_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET))
225
226#define	XMAC_REG_ADDR(port_num, reg)\
227	(FZC_MAC + (XMAC_ADDR_OFFSET(port_num)) + (reg))
228
229#define	XMAC_PORT_ADDR(port_num)\
230	(FZC_MAC + XMAC_ADDR_OFFSET(port_num))
231
232/* BMAC address macros */
233
234#define	BMAC_ADDR_OFFSET_2		0x0C000
235#define	BMAC_ADDR_OFFSET_3		0x10000
236
237#define	BMAC_ADDR_OFFSET(port_num)\
238	(BMAC_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET))
239
240#define	BMAC_REG_ADDR(port_num, reg)\
241	(FZC_MAC + (BMAC_ADDR_OFFSET(port_num)) + (reg))
242
243#define	BMAC_PORT_ADDR(port_num)\
244	(FZC_MAC + BMAC_ADDR_OFFSET(port_num))
245
246/* PCS address macros */
247
248#define	PCS_ADDR_OFFSET_0		0x04000
249#define	PCS_ADDR_OFFSET_1		0x0A000
250#define	PCS_ADDR_OFFSET_2		0x0E000
251#define	PCS_ADDR_OFFSET_3		0x12000
252
253#define	PCS_ADDR_OFFSET(port_num)\
254	((port_num <= 1) ? \
255	(PCS_ADDR_OFFSET_0 + (port_num) * PORT_1_OFFSET) : \
256	(PCS_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET)))
257
258#define	PCS_REG_ADDR(port_num, reg)\
259	(FZC_MAC + (PCS_ADDR_OFFSET((port_num)) + (reg)))
260
261#define	PCS_PORT_ADDR(port_num)\
262	(FZC_MAC + (PCS_ADDR_OFFSET(port_num)))
263
264/* XPCS address macros */
265
266#define	XPCS_ADDR_OFFSET_0		0x02000
267#define	XPCS_ADDR_OFFSET_1		0x08000
268#define	XPCS_ADDR_OFFSET(port_num)\
269	(XPCS_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET))
270
271#define	XPCS_ADDR(port_num, reg)\
272	(FZC_MAC + (XPCS_ADDR_OFFSET((port_num)) + (reg)))
273
274#define	XPCS_PORT_ADDR(port_num)\
275	(FZC_MAC + (XPCS_ADDR_OFFSET(port_num)))
276
277/* ESR address macro */
278#define	ESR_ADDR_OFFSET		0x14000
279#define	ESR_ADDR(reg)\
280	(FZC_MAC + (ESR_ADDR_OFFSET) + (reg))
281
282/* MIF address macros */
283#define	MIF_ADDR_OFFSET		0x16000
284#define	MIF_ADDR(reg)\
285	(FZC_MAC + (MIF_ADDR_OFFSET) + (reg))
286
287/* BMAC registers offset */
288#define	BTXMAC_SW_RST_REG		0x000	/* TX MAC software reset */
289#define	BRXMAC_SW_RST_REG		0x008	/* RX MAC software reset */
290#define	MAC_SEND_PAUSE_REG		0x010	/* send pause command */
291#define	BTXMAC_STATUS_REG		0x020	/* TX MAC status */
292#define	BRXMAC_STATUS_REG		0x028	/* RX MAC status */
293#define	BMAC_CTRL_STAT_REG		0x030	/* MAC control status */
294#define	BTXMAC_STAT_MSK_REG		0x040	/* TX MAC mask */
295#define	BRXMAC_STAT_MSK_REG		0x048	/* RX MAC mask */
296#define	BMAC_C_S_MSK_REG		0x050	/* MAC control mask */
297#define	TXMAC_CONFIG_REG		0x060	/* TX MAC config */
298/* cfg register bitmap */
299
300typedef union _btxmac_config_t {
301	uint64_t value;
302
303	struct {
304#if defined(_BIG_ENDIAN)
305		uint32_t msw;	/* Most significant word */
306		uint32_t lsw;	/* Least significant word */
307#elif defined(_LITTLE_ENDIAN)
308		uint32_t lsw;	/* Least significant word */
309		uint32_t msw;	/* Most significant word */
310#endif
311	} val;
312	struct {
313#if defined(_BIG_ENDIAN)
314		uint32_t	w1;
315#endif
316		struct {
317#if defined(_BIT_FIELDS_HTOL)
318			uint32_t rsrvd	: 22;
319			uint32_t hdx_ctrl2	: 1;
320			uint32_t no_fcs	: 1;
321			uint32_t hdx_ctrl	: 7;
322			uint32_t txmac_enable	: 1;
323#elif defined(_BIT_FIELDS_LTOH)
324			uint32_t txmac_enable	: 1;
325			uint32_t hdx_ctrl	: 7;
326			uint32_t no_fcs	: 1;
327			uint32_t hdx_ctrl2	: 1;
328			uint32_t rsrvd	: 22;
329#endif
330		} w0;
331
332#if defined(_LITTLE_ENDIAN)
333		uint32_t	w1;
334#endif
335	} bits;
336} btxmac_config_t, *p_btxmac_config_t;
337
338#define	RXMAC_CONFIG_REG		0x068	/* RX MAC config */
339
340typedef union _brxmac_config_t {
341	uint64_t value;
342
343	struct {
344#if defined(_BIG_ENDIAN)
345		uint32_t msw;	/* Most significant word */
346		uint32_t lsw;	/* Least significant word */
347#elif defined(_LITTLE_ENDIAN)
348		uint32_t lsw;	/* Least significant word */
349		uint32_t msw;	/* Most significant word */
350#endif
351	} val;
352	struct {
353#if defined(_BIG_ENDIAN)
354		uint32_t	w1;
355#endif
356		struct {
357#if defined(_BIT_FIELDS_HTOL)
358			uint32_t rsrvd	: 20;
359			uint32_t mac_reg_sw_test : 2;
360			uint32_t mac2ipp_pkt_cnt_en : 1;
361			uint32_t rx_crs_extend_en : 1;
362			uint32_t error_chk_dis	: 1;
363			uint32_t addr_filter_en	: 1;
364			uint32_t hash_filter_en	: 1;
365			uint32_t promiscuous_group	: 1;
366			uint32_t promiscuous	: 1;
367			uint32_t strip_fcs	: 1;
368			uint32_t strip_pad	: 1;
369			uint32_t rxmac_enable	: 1;
370#elif defined(_BIT_FIELDS_LTOH)
371			uint32_t rxmac_enable	: 1;
372			uint32_t strip_pad	: 1;
373			uint32_t strip_fcs	: 1;
374			uint32_t promiscuous	: 1;
375			uint32_t promiscuous_group	: 1;
376			uint32_t hash_filter_en	: 1;
377			uint32_t addr_filter_en	: 1;
378			uint32_t error_chk_dis	: 1;
379			uint32_t rx_crs_extend_en : 1;
380			uint32_t mac2ipp_pkt_cnt_en : 1;
381			uint32_t mac_reg_sw_test : 2;
382			uint32_t rsrvd	: 20;
383#endif
384		} w0;
385
386#if defined(_LITTLE_ENDIAN)
387		uint32_t	w1;
388#endif
389	} bits;
390} brxmac_config_t, *p_brxmac_config_t;
391
392#define	MAC_CTRL_CONFIG_REG		0x070	/* MAC control config */
393#define	MAC_XIF_CONFIG_REG		0x078	/* XIF config */
394
395typedef union _bxif_config_t {
396	uint64_t value;
397
398	struct {
399#if defined(_BIG_ENDIAN)
400		uint32_t msw;	/* Most significant word */
401		uint32_t lsw;	/* Least significant word */
402#elif defined(_LITTLE_ENDIAN)
403		uint32_t lsw;	/* Least significant word */
404		uint32_t msw;	/* Most significant word */
405#endif
406	} val;
407	struct {
408#if defined(_BIG_ENDIAN)
409		uint32_t	w1;
410#endif
411		struct {
412#if defined(_BIT_FIELDS_HTOL)
413			uint32_t rsrvd2		: 24;
414			uint32_t sel_clk_25mhz	: 1;
415			uint32_t led_polarity	: 1;
416			uint32_t force_led_on	: 1;
417			uint32_t used		: 1;
418			uint32_t gmii_mode	: 1;
419			uint32_t rsrvd		: 1;
420			uint32_t loopback	: 1;
421			uint32_t tx_output_en	: 1;
422#elif defined(_BIT_FIELDS_LTOH)
423			uint32_t tx_output_en	: 1;
424			uint32_t loopback	: 1;
425			uint32_t rsrvd		: 1;
426			uint32_t gmii_mode	: 1;
427			uint32_t used		: 1;
428			uint32_t force_led_on	: 1;
429			uint32_t led_polarity	: 1;
430			uint32_t sel_clk_25mhz	: 1;
431			uint32_t rsrvd2		: 24;
432#endif
433		} w0;
434
435#if defined(_LITTLE_ENDIAN)
436		uint32_t	w1;
437#endif
438	} bits;
439} bxif_config_t, *p_bxif_config_t;
440
441#define	BMAC_MIN_REG			0x0a0	/* min frame size */
442#define	BMAC_MAX_REG			0x0a8	/* max frame size reg */
443#define	MAC_PA_SIZE_REG			0x0b0	/* num of preamble bytes */
444#define	MAC_CTRL_TYPE_REG		0x0c8	/* type field of MAC ctrl */
445#define	BMAC_ADDR0_REG			0x100	/* MAC unique ad0 reg (HI 0) */
446#define	BMAC_ADDR1_REG			0x108	/* MAC unique ad1 reg */
447#define	BMAC_ADDR2_REG			0x110	/* MAC unique ad2 reg */
448#define	BMAC_ADDR3_REG			0x118	/* MAC alt ad0 reg (HI 1) */
449#define	BMAC_ADDR4_REG			0x120	/* MAC alt ad0 reg */
450#define	BMAC_ADDR5_REG			0x128	/* MAC alt ad0 reg */
451#define	BMAC_ADDR6_REG			0x130	/* MAC alt ad1 reg (HI 2) */
452#define	BMAC_ADDR7_REG			0x138	/* MAC alt ad1 reg */
453#define	BMAC_ADDR8_REG			0x140	/* MAC alt ad1 reg */
454#define	BMAC_ADDR9_REG			0x148	/* MAC alt ad2 reg (HI 3) */
455#define	BMAC_ADDR10_REG			0x150	/* MAC alt ad2 reg */
456#define	BMAC_ADDR11_REG			0x158	/* MAC alt ad2 reg */
457#define	BMAC_ADDR12_REG			0x160	/* MAC alt ad3 reg (HI 4) */
458#define	BMAC_ADDR13_REG			0x168	/* MAC alt ad3 reg */
459#define	BMAC_ADDR14_REG			0x170	/* MAC alt ad3 reg */
460#define	BMAC_ADDR15_REG			0x178	/* MAC alt ad4 reg (HI 5) */
461#define	BMAC_ADDR16_REG			0x180	/* MAC alt ad4 reg */
462#define	BMAC_ADDR17_REG			0x188	/* MAC alt ad4 reg */
463#define	BMAC_ADDR18_REG			0x190	/* MAC alt ad5 reg (HI 6) */
464#define	BMAC_ADDR19_REG			0x198	/* MAC alt ad5 reg */
465#define	BMAC_ADDR20_REG			0x1a0	/* MAC alt ad5 reg */
466#define	BMAC_ADDR21_REG			0x1a8	/* MAC alt ad6 reg (HI 7) */
467#define	BMAC_ADDR22_REG			0x1b0	/* MAC alt ad6 reg */
468#define	BMAC_ADDR23_REG			0x1b8	/* MAC alt ad6 reg */
469#define	MAC_FC_ADDR0_REG		0x268	/* FC frame addr0 (HI 0, p3) */
470#define	MAC_FC_ADDR1_REG		0x270	/* FC frame addr1 */
471#define	MAC_FC_ADDR2_REG		0x278	/* FC frame addr2 */
472#define	MAC_ADDR_FILT0_REG		0x298	/* bits [47:32] (HI 0, p2) */
473#define	MAC_ADDR_FILT1_REG		0x2a0	/* bits [31:16] */
474#define	MAC_ADDR_FILT2_REG		0x2a8	/* bits [15:0]  */
475#define	MAC_ADDR_FILT12_MASK_REG 	0x2b0	/* addr filter 2 & 1 mask */
476#define	MAC_ADDR_FILT00_MASK_REG	0x2b8	/* addr filter 0 mask */
477#define	MAC_HASH_TBL0_REG		0x2c0	/* hash table 0 reg */
478#define	MAC_HASH_TBL1_REG		0x2c8	/* hash table 1 reg */
479#define	MAC_HASH_TBL2_REG		0x2d0	/* hash table 2 reg */
480#define	MAC_HASH_TBL3_REG		0x2d8	/* hash table 3 reg */
481#define	MAC_HASH_TBL4_REG		0x2e0	/* hash table 4 reg */
482#define	MAC_HASH_TBL5_REG		0x2e8	/* hash table 5 reg */
483#define	MAC_HASH_TBL6_REG		0x2f0	/* hash table 6 reg */
484#define	MAC_HASH_TBL7_REG		0x2f8	/* hash table 7 reg */
485#define	MAC_HASH_TBL8_REG		0x300	/* hash table 8 reg */
486#define	MAC_HASH_TBL9_REG		0x308	/* hash table 9 reg */
487#define	MAC_HASH_TBL10_REG		0x310	/* hash table 10 reg */
488#define	MAC_HASH_TBL11_REG		0x318	/* hash table 11 reg */
489#define	MAC_HASH_TBL12_REG		0x320	/* hash table 12 reg */
490#define	MAC_HASH_TBL13_REG		0x328	/* hash table 13 reg */
491#define	MAC_HASH_TBL14_REG		0x330	/* hash table 14 reg */
492#define	MAC_HASH_TBL15_REG		0x338	/* hash table 15 reg */
493#define	RXMAC_FRM_CNT_REG		0x370	/* receive frame counter */
494#define	MAC_LEN_ER_CNT_REG		0x378	/* length error counter */
495#define	BMAC_AL_ER_CNT_REG		0x380	/* alignment error counter */
496#define	BMAC_CRC_ER_CNT_REG		0x388	/* FCS error counter */
497#define	BMAC_CD_VIO_CNT_REG		0x390	/* RX code violation err */
498#define	BMAC_SM_REG			0x3a0	/* (ro) state machine reg */
499#define	BMAC_ALTAD_CMPEN_REG		0x3f8	/* Alt addr compare enable */
500#define	BMAC_HOST_INF0_REG		0x400	/* Host info */
501						/* (own da, add filter, fc) */
502#define	BMAC_HOST_INF1_REG		0x408	/* Host info (alt ad 0) */
503#define	BMAC_HOST_INF2_REG		0x410	/* Host info (alt ad 1) */
504#define	BMAC_HOST_INF3_REG		0x418	/* Host info (alt ad 2) */
505#define	BMAC_HOST_INF4_REG		0x420	/* Host info (alt ad 3) */
506#define	BMAC_HOST_INF5_REG		0x428	/* Host info (alt ad 4) */
507#define	BMAC_HOST_INF6_REG		0x430	/* Host info (alt ad 5) */
508#define	BMAC_HOST_INF7_REG		0x438	/* Host info (alt ad 6) */
509#define	BMAC_HOST_INF8_REG		0x440	/* Host info (hash hit, miss) */
510#define	BTXMAC_BYTE_CNT_REG		0x448	/* Tx byte count */
511#define	BTXMAC_FRM_CNT_REG		0x450	/* frame count */
512#define	BRXMAC_BYTE_CNT_REG		0x458	/* Rx byte count */
513/* x ranges from 0 to 6 (BMAC_MAX_ALT_ADDR_ENTRY - 1) */
514#define	BMAC_ALT_ADDR0N_REG_ADDR(x)	(BMAC_ADDR3_REG + (x) * 24)
515#define	BMAC_ALT_ADDR1N_REG_ADDR(x)	(BMAC_ADDR3_REG + 8 + (x) * 24)
516#define	BMAC_ALT_ADDR2N_REG_ADDR(x)	(BMAC_ADDR3_REG + 0x10 + (x) * 24)
517#define	BMAC_HASH_TBLN_REG_ADDR(x)	(MAC_HASH_TBL0_REG + (x) * 8)
518#define	BMAC_HOST_INFN_REG_ADDR(x)	(BMAC_HOST_INF0_REG + (x) * 8)
519
520/* XMAC registers offset */
521#define	XTXMAC_SW_RST_REG		0x000	/* XTX MAC soft reset */
522#define	XRXMAC_SW_RST_REG		0x008	/* XRX MAC soft reset */
523#define	XTXMAC_STATUS_REG		0x020	/* XTX MAC status */
524#define	XRXMAC_STATUS_REG		0x028	/* XRX MAC status */
525#define	XMAC_CTRL_STAT_REG		0x030	/* Control / Status */
526#define	XTXMAC_STAT_MSK_REG		0x040	/* XTX MAC Status mask */
527#define	XRXMAC_STAT_MSK_REG		0x048	/* XRX MAC Status mask */
528#define	XMAC_C_S_MSK_REG		0x050	/* Control / Status mask */
529#define	XMAC_CONFIG_REG			0x060	/* Configuration */
530
531/* xmac config bit fields */
532typedef union _xmac_cfg_t {
533	uint64_t value;
534
535	struct {
536#if defined(_BIG_ENDIAN)
537		uint32_t msw;	/* Most significant word */
538		uint32_t lsw;	/* Least significant word */
539#elif defined(_LITTLE_ENDIAN)
540		uint32_t lsw;	/* Least significant word */
541		uint32_t msw;	/* Most significant word */
542#endif
543	} val;
544	struct {
545#if defined(_BIG_ENDIAN)
546		uint32_t	w1;
547#endif
548		struct {
549#if defined(_BIT_FIELDS_HTOL)
550		uint32_t sel_clk_25mhz : 1;
551		uint32_t pcs_bypass	: 1;
552		uint32_t xpcs_bypass	: 1;
553		uint32_t mii_gmii_mode	: 2;
554		uint32_t lfs_disable	: 1;
555		uint32_t loopback	: 1;
556		uint32_t tx_output_en	: 1;
557		uint32_t sel_por_clk_src : 1;
558		uint32_t led_polarity	: 1;
559		uint32_t force_led_on	: 1;
560		uint32_t pass_fctl_frames : 1;
561		uint32_t recv_pause_en	: 1;
562		uint32_t mac2ipp_pkt_cnt_en : 1;
563		uint32_t strip_crc	: 1;
564		uint32_t addr_filter_en	: 1;
565		uint32_t hash_filter_en	: 1;
566		uint32_t code_viol_chk_dis	: 1;
567		uint32_t reserved_mcast	: 1;
568		uint32_t rx_crc_chk_dis	: 1;
569		uint32_t error_chk_dis	: 1;
570		uint32_t promisc_grp	: 1;
571		uint32_t promiscuous	: 1;
572		uint32_t rx_mac_enable	: 1;
573		uint32_t warning_msg_en	: 1;
574		uint32_t used		: 3;
575		uint32_t always_no_crc	: 1;
576		uint32_t var_min_ipg_en	: 1;
577		uint32_t strech_mode	: 1;
578		uint32_t tx_enable	: 1;
579#elif defined(_BIT_FIELDS_LTOH)
580		uint32_t tx_enable	: 1;
581		uint32_t strech_mode	: 1;
582		uint32_t var_min_ipg_en	: 1;
583		uint32_t always_no_crc	: 1;
584		uint32_t used		: 3;
585		uint32_t warning_msg_en	: 1;
586		uint32_t rx_mac_enable	: 1;
587		uint32_t promiscuous	: 1;
588		uint32_t promisc_grp	: 1;
589		uint32_t error_chk_dis	: 1;
590		uint32_t rx_crc_chk_dis	: 1;
591		uint32_t reserved_mcast	: 1;
592		uint32_t code_viol_chk_dis	: 1;
593		uint32_t hash_filter_en	: 1;
594		uint32_t addr_filter_en	: 1;
595		uint32_t strip_crc	: 1;
596		uint32_t mac2ipp_pkt_cnt_en : 1;
597		uint32_t recv_pause_en	: 1;
598		uint32_t pass_fctl_frames : 1;
599		uint32_t force_led_on	: 1;
600		uint32_t led_polarity	: 1;
601		uint32_t sel_por_clk_src : 1;
602		uint32_t tx_output_en	: 1;
603		uint32_t loopback	: 1;
604		uint32_t lfs_disable	: 1;
605		uint32_t mii_gmii_mode	: 2;
606		uint32_t xpcs_bypass	: 1;
607		uint32_t pcs_bypass	: 1;
608		uint32_t sel_clk_25mhz : 1;
609#endif
610		} w0;
611
612#if defined(_LITTLE_ENDIAN)
613		uint32_t	w1;
614#endif
615	} bits;
616} xmac_cfg_t, *p_xmac_cfg_t;
617
618#define	XMAC_IPG_REG			0x080	/* Inter-Packet-Gap */
619#define	XMAC_MIN_REG			0x088	/* min frame size register */
620#define	XMAC_MAX_REG			0x090	/* max frame/burst size */
621#define	XMAC_ADDR0_REG			0x0a0	/* [47:32] of MAC addr (HI17) */
622#define	XMAC_ADDR1_REG			0x0a8	/* [31:16] of MAC addr */
623#define	XMAC_ADDR2_REG			0x0b0	/* [15:0] of MAC addr */
624#define	XRXMAC_BT_CNT_REG		0x100	/* bytes received / 8 */
625#define	XRXMAC_BC_FRM_CNT_REG		0x108	/* good BC frames received */
626#define	XRXMAC_MC_FRM_CNT_REG		0x110	/* good MC frames received */
627#define	XRXMAC_FRAG_CNT_REG		0x118	/* frag frames rejected */
628#define	XRXMAC_HIST_CNT1_REG		0x120	/* 64 bytes frames */
629#define	XRXMAC_HIST_CNT2_REG		0x128	/* 65-127 bytes frames */
630#define	XRXMAC_HIST_CNT3_REG		0x130	/* 128-255 bytes frames */
631#define	XRXMAC_HIST_CNT4_REG		0x138	/* 256-511 bytes frames */
632#define	XRXMAC_HIST_CNT5_REG		0x140	/* 512-1023 bytes frames */
633#define	XRXMAC_HIST_CNT6_REG		0x148	/* 1024-1522 bytes frames */
634#define	XRXMAC_MPSZER_CNT_REG		0x150	/* frames > maxframesize */
635#define	XRXMAC_CRC_ER_CNT_REG		0x158	/* frames failed CRC */
636#define	XRXMAC_CD_VIO_CNT_REG		0x160	/* frames with code vio */
637#define	XRXMAC_AL_ER_CNT_REG		0x168	/* frames with align error */
638#define	XTXMAC_FRM_CNT_REG		0x170	/* tx frames */
639#define	XTXMAC_BYTE_CNT_REG		0x178	/* tx bytes / 8 */
640#define	XMAC_LINK_FLT_CNT_REG		0x180	/* link faults */
641#define	XRXMAC_HIST_CNT7_REG		0x188	/* MAC2IPP/>1523 bytes frames */
642#define	XMAC_SM_REG			0x1a8	/* State machine */
643#define	XMAC_INTERN1_REG		0x1b0	/* internal signals for diag */
644#define	XMAC_INTERN2_REG		0x1b8	/* internal signals for diag */
645#define	XMAC_ADDR_CMPEN_REG		0x208	/* alt MAC addr check */
646#define	XMAC_ADDR3_REG			0x218	/* alt MAC addr 0 (HI 0) */
647#define	XMAC_ADDR4_REG			0x220	/* alt MAC addr 0 */
648#define	XMAC_ADDR5_REG			0x228	/* alt MAC addr 0 */
649#define	XMAC_ADDR6_REG			0x230	/* alt MAC addr 1 (HI 1) */
650#define	XMAC_ADDR7_REG			0x238	/* alt MAC addr 1 */
651#define	XMAC_ADDR8_REG			0x240	/* alt MAC addr 1 */
652#define	XMAC_ADDR9_REG			0x248	/* alt MAC addr 2 (HI 2) */
653#define	XMAC_ADDR10_REG			0x250	/* alt MAC addr 2 */
654#define	XMAC_ADDR11_REG			0x258	/* alt MAC addr 2 */
655#define	XMAC_ADDR12_REG			0x260	/* alt MAC addr 3 (HI 3) */
656#define	XMAC_ADDR13_REG			0x268	/* alt MAC addr 3 */
657#define	XMAC_ADDR14_REG			0x270	/* alt MAC addr 3 */
658#define	XMAC_ADDR15_REG			0x278	/* alt MAC addr 4 (HI 4) */
659#define	XMAC_ADDR16_REG			0x280	/* alt MAC addr 4 */
660#define	XMAC_ADDR17_REG			0x288	/* alt MAC addr 4 */
661#define	XMAC_ADDR18_REG			0x290	/* alt MAC addr 5 (HI 5) */
662#define	XMAC_ADDR19_REG			0x298	/* alt MAC addr 5 */
663#define	XMAC_ADDR20_REG			0x2a0	/* alt MAC addr 5 */
664#define	XMAC_ADDR21_REG			0x2a8	/* alt MAC addr 6 (HI 6) */
665#define	XMAC_ADDR22_REG			0x2b0	/* alt MAC addr 6 */
666#define	XMAC_ADDR23_REG			0x2b8	/* alt MAC addr 6 */
667#define	XMAC_ADDR24_REG			0x2c0	/* alt MAC addr 7 (HI 7) */
668#define	XMAC_ADDR25_REG			0x2c8	/* alt MAC addr 7 */
669#define	XMAC_ADDR26_REG			0x2d0	/* alt MAC addr 7 */
670#define	XMAC_ADDR27_REG			0x2d8	/* alt MAC addr 8 (HI 8) */
671#define	XMAC_ADDR28_REG			0x2e0	/* alt MAC addr 8 */
672#define	XMAC_ADDR29_REG			0x2e8	/* alt MAC addr 8 */
673#define	XMAC_ADDR30_REG			0x2f0	/* alt MAC addr 9 (HI 9) */
674#define	XMAC_ADDR31_REG			0x2f8	/* alt MAC addr 9 */
675#define	XMAC_ADDR32_REG			0x300	/* alt MAC addr 9 */
676#define	XMAC_ADDR33_REG			0x308	/* alt MAC addr 10 (HI 10) */
677#define	XMAC_ADDR34_REG			0x310	/* alt MAC addr 10 */
678#define	XMAC_ADDR35_REG			0x318	/* alt MAC addr 10 */
679#define	XMAC_ADDR36_REG			0x320	/* alt MAC addr 11 (HI 11) */
680#define	XMAC_ADDR37_REG			0x328	/* alt MAC addr 11 */
681#define	XMAC_ADDR38_REG			0x330	/* alt MAC addr 11 */
682#define	XMAC_ADDR39_REG			0x338	/* alt MAC addr 12 (HI 12) */
683#define	XMAC_ADDR40_REG			0x340	/* alt MAC addr 12 */
684#define	XMAC_ADDR41_REG			0x348	/* alt MAC addr 12 */
685#define	XMAC_ADDR42_REG			0x350	/* alt MAC addr 13 (HI 13) */
686#define	XMAC_ADDR43_REG			0x358	/* alt MAC addr 13 */
687#define	XMAC_ADDR44_REG			0x360	/* alt MAC addr 13 */
688#define	XMAC_ADDR45_REG			0x368	/* alt MAC addr 14 (HI 14) */
689#define	XMAC_ADDR46_REG			0x370	/* alt MAC addr 14 */
690#define	XMAC_ADDR47_REG			0x378	/* alt MAC addr 14 */
691#define	XMAC_ADDR48_REG			0x380	/* alt MAC addr 15 (HI 15) */
692#define	XMAC_ADDR49_REG			0x388	/* alt MAC addr 15 */
693#define	XMAC_ADDR50_REG			0x390	/* alt MAC addr 15 */
694#define	XMAC_ADDR_FILT0_REG		0x818	/* [47:32] addr filter (HI18) */
695#define	XMAC_ADDR_FILT1_REG		0x820	/* [31:16] of addr filter */
696#define	XMAC_ADDR_FILT2_REG		0x828	/* [15:0] of addr filter */
697#define	XMAC_ADDR_FILT12_MASK_REG 	0x830	/* addr filter 2 & 1 mask */
698#define	XMAC_ADDR_FILT0_MASK_REG	0x838	/* addr filter 0 mask */
699#define	XMAC_HASH_TBL0_REG		0x840	/* hash table 0 reg */
700#define	XMAC_HASH_TBL1_REG		0x848	/* hash table 1 reg */
701#define	XMAC_HASH_TBL2_REG		0x850	/* hash table 2 reg */
702#define	XMAC_HASH_TBL3_REG		0x858	/* hash table 3 reg */
703#define	XMAC_HASH_TBL4_REG		0x860	/* hash table 4 reg */
704#define	XMAC_HASH_TBL5_REG		0x868	/* hash table 5 reg */
705#define	XMAC_HASH_TBL6_REG		0x870	/* hash table 6 reg */
706#define	XMAC_HASH_TBL7_REG		0x878	/* hash table 7 reg */
707#define	XMAC_HASH_TBL8_REG		0x880	/* hash table 8 reg */
708#define	XMAC_HASH_TBL9_REG		0x888	/* hash table 9 reg */
709#define	XMAC_HASH_TBL10_REG		0x890	/* hash table 10 reg */
710#define	XMAC_HASH_TBL11_REG		0x898	/* hash table 11 reg */
711#define	XMAC_HASH_TBL12_REG		0x8a0	/* hash table 12 reg */
712#define	XMAC_HASH_TBL13_REG		0x8a8	/* hash table 13 reg */
713#define	XMAC_HASH_TBL14_REG		0x8b0	/* hash table 14 reg */
714#define	XMAC_HASH_TBL15_REG		0x8b8	/* hash table 15 reg */
715#define	XMAC_HOST_INF0_REG		0x900	/* Host info 0 (alt ad 0) */
716#define	XMAC_HOST_INF1_REG		0x908	/* Host info 1 (alt ad 1) */
717#define	XMAC_HOST_INF2_REG		0x910	/* Host info 2 (alt ad 2) */
718#define	XMAC_HOST_INF3_REG		0x918	/* Host info 3 (alt ad 3) */
719#define	XMAC_HOST_INF4_REG		0x920	/* Host info 4 (alt ad 4) */
720#define	XMAC_HOST_INF5_REG		0x928	/* Host info 5 (alt ad 5) */
721#define	XMAC_HOST_INF6_REG		0x930	/* Host info 6 (alt ad 6) */
722#define	XMAC_HOST_INF7_REG		0x938	/* Host info 7 (alt ad 7) */
723#define	XMAC_HOST_INF8_REG		0x940	/* Host info 8 (alt ad 8) */
724#define	XMAC_HOST_INF9_REG		0x948	/* Host info 9 (alt ad 9) */
725#define	XMAC_HOST_INF10_REG		0x950	/* Host info 10 (alt ad 10) */
726#define	XMAC_HOST_INF11_REG		0x958	/* Host info 11 (alt ad 11) */
727#define	XMAC_HOST_INF12_REG		0x960	/* Host info 12 (alt ad 12) */
728#define	XMAC_HOST_INF13_REG		0x968	/* Host info 13 (alt ad 13) */
729#define	XMAC_HOST_INF14_REG		0x970	/* Host info 14 (alt ad 14) */
730#define	XMAC_HOST_INF15_REG		0x978	/* Host info 15 (alt ad 15) */
731#define	XMAC_HOST_INF16_REG		0x980	/* Host info 16 (hash hit) */
732#define	XMAC_HOST_INF17_REG		0x988	/* Host info 17 (own da) */
733#define	XMAC_HOST_INF18_REG		0x990	/* Host info 18 (filter hit) */
734#define	XMAC_HOST_INF19_REG		0x998	/* Host info 19 (fc hit) */
735#define	XMAC_PA_DATA0_REG		0xb80	/* preamble [31:0] */
736#define	XMAC_PA_DATA1_REG		0xb88	/* preamble [63:32] */
737#define	XMAC_DEBUG_SEL_REG		0xb90	/* debug select */
738#define	XMAC_TRAINING_VECT_REG		0xb98	/* training vector */
739/* x ranges from 0 to 15 (XMAC_MAX_ALT_ADDR_ENTRY - 1) */
740#define	XMAC_ALT_ADDR0N_REG_ADDR(x)	(XMAC_ADDR3_REG + (x) * 24)
741#define	XMAC_ALT_ADDR1N_REG_ADDR(x)	(XMAC_ADDR3_REG + 8 + (x) * 24)
742#define	XMAC_ALT_ADDR2N_REG_ADDR(x)	(XMAC_ADDR3_REG + 16 + (x) * 24)
743#define	XMAC_HASH_TBLN_REG_ADDR(x)	(XMAC_HASH_TBL0_REG + (x) * 8)
744#define	XMAC_HOST_INFN_REG_ADDR(x)	(XMAC_HOST_INF0_REG + (x) * 8)
745
746/* MIF registers offset */
747#define	MIF_BB_MDC_REG			0	   /* MIF bit-bang clock */
748#define	MIF_BB_MDO_REG			0x008	   /* MIF bit-bang data */
749#define	MIF_BB_MDO_EN_REG		0x010	   /* MIF bit-bang output en */
750#define	MIF_OUTPUT_FRAME_REG		0x018	   /* MIF frame/output reg */
751#define	MIF_CONFIG_REG			0x020	   /* MIF config reg */
752#define	MIF_POLL_STATUS_REG		0x028	   /* MIF poll status reg */
753#define	MIF_POLL_MASK_REG		0x030	   /* MIF poll mask reg */
754#define	MIF_STATE_MACHINE_REG		0x038	   /* MIF state machine reg */
755#define	MIF_STATUS_REG			0x040	   /* MIF status reg */
756#define	MIF_MASK_REG			0x048	   /* MIF mask reg */
757
758
759/* PCS registers offset */
760#define	PCS_MII_CTRL_REG		0	   /* PCS MII control reg */
761#define	PCS_MII_STATUS_REG		0x008	   /* PCS MII status reg */
762#define	PCS_MII_ADVERT_REG		0x010	   /* PCS MII advertisement */
763#define	PCS_MII_LPA_REG			0x018	   /* link partner ability */
764#define	PCS_CONFIG_REG			0x020	   /* PCS config reg */
765#define	PCS_STATE_MACHINE_REG		0x028	   /* PCS state machine */
766#define	PCS_INTR_STATUS_REG		0x030	/* PCS interrupt status */
767#define	PCS_DATAPATH_MODE_REG		0x0a0	   /* datapath mode reg */
768#define	PCS_PACKET_COUNT_REG		0x0c0	   /* PCS packet counter */
769
770#define	XPCS_CTRL_1_REG			0	/* Control */
771#define	XPCS_STATUS_1_REG		0x008
772#define	XPCS_DEV_ID_REG			0x010	/* 32bits IEEE manufacture ID */
773#define	XPCS_SPEED_ABILITY_REG		0x018
774#define	XPCS_DEV_IN_PKG_REG		0x020
775#define	XPCS_CTRL_2_REG			0x028
776#define	XPCS_STATUS_2_REG		0x030
777#define	XPCS_PKG_ID_REG			0x038	/* Package ID */
778#define	XPCS_STATUS_REG			0x040
779#define	XPCS_TEST_CTRL_REG		0x048
780#define	XPCS_CFG_VENDOR_1_REG		0x050
781#define	XPCS_DIAG_VENDOR_2_REG		0x058
782#define	XPCS_MASK_1_REG			0x060
783#define	XPCS_PKT_CNTR_REG		0x068
784#define	XPCS_TX_STATE_MC_REG		0x070
785#define	XPCS_DESKEW_ERR_CNTR_REG	0x078
786#define	XPCS_SYM_ERR_CNTR_L0_L1_REG	0x080
787#define	XPCS_SYM_ERR_CNTR_L2_L3_REG	0x088
788#define	XPCS_TRAINING_VECTOR_REG	0x090
789
790/* ESR registers offset */
791#define	ESR_RESET_REG			0
792#define	ESR_CONFIG_REG			0x008
793#define	ESR_0_PLL_CONFIG_REG		0x010
794#define	ESR_0_CONTROL_REG		0x018
795#define	ESR_0_TEST_CONFIG_REG		0x020
796#define	ESR_1_PLL_CONFIG_REG		0x028
797#define	ESR_1_CONTROL_REG		0x030
798#define	ESR_1_TEST_CONFIG_REG		0x038
799#define	ESR_ENET_RGMII_CFG_REG		0x040
800#define	ESR_INTERNAL_SIGNALS_REG	0x800
801#define	ESR_DEBUG_SEL_REG		0x808
802
803
804/* Reset Register */
805#define	MAC_SEND_PAUSE_TIME_MASK	0x0000FFFF /* value of pause time */
806#define	MAC_SEND_PAUSE_SEND		0x00010000 /* send pause flow ctrl */
807
808/* Tx MAC Status Register */
809#define	MAC_TX_FRAME_XMIT		0x00000001 /* successful tx frame */
810#define	MAC_TX_UNDERRUN			0x00000002 /* starvation in xmit */
811#define	MAC_TX_MAX_PACKET_ERR		0x00000004 /* TX frame exceeds max */
812#define	MAC_TX_BYTE_CNT_EXP		0x00000400 /* TX byte cnt overflow */
813#define	MAC_TX_FRAME_CNT_EXP		0x00000800 /* Tx frame cnt overflow */
814
815/* Rx MAC Status Register */
816#define	MAC_RX_FRAME_RECV		0x00000001 /* successful rx frame */
817#define	MAC_RX_OVERFLOW			0x00000002 /* RX FIFO overflow */
818#define	MAC_RX_FRAME_COUNT		0x00000004 /* rx frame cnt rollover */
819#define	MAC_RX_ALIGN_ERR		0x00000008 /* alignment err rollover */
820#define	MAC_RX_CRC_ERR			0x00000010 /* crc error cnt rollover */
821#define	MAC_RX_LEN_ERR			0x00000020 /* length err cnt rollover */
822#define	MAC_RX_VIOL_ERR			0x00000040 /* code vio err rollover */
823#define	MAC_RX_BYTE_CNT_EXP		0x00000080 /* RX MAC byte rollover */
824
825/* MAC Control Status Register */
826#define	MAC_CTRL_PAUSE_RECEIVED		0x00000001 /* successful pause frame */
827#define	MAC_CTRL_PAUSE_STATE		0x00000002 /* notpause-->pause */
828#define	MAC_CTRL_NOPAUSE_STATE		0x00000004 /* pause-->notpause */
829#define	MAC_CTRL_PAUSE_TIME_MASK	0xFFFF0000 /* value of pause time */
830#define	MAC_CTRL_PAUSE_TIME_SHIFT	16
831
832/* Tx MAC Configuration Register */
833#define	MAC_TX_CFG_TXMAC_ENABLE		0x00000001 /* enable TX MAC. */
834#define	MAC_TX_CFG_NO_FCS		0x00000100 /* TX not generate CRC */
835
836/* Rx MAC Configuration Register */
837#define	MAC_RX_CFG_RXMAC_ENABLE		0x00000001 /* enable RX MAC */
838#define	MAC_RX_CFG_STRIP_PAD		0x00000002 /* not supported, set to 0 */
839#define	MAC_RX_CFG_STRIP_FCS		0x00000004 /* strip last 4bytes (CRC) */
840#define	MAC_RX_CFG_PROMISC		0x00000008 /* promisc mode enable */
841#define	MAC_RX_CFG_PROMISC_GROUP  	0x00000010 /* accept all MC frames */
842#define	MAC_RX_CFG_HASH_FILTER_EN	0x00000020 /* use hash table */
843#define	MAC_RX_CFG_ADDR_FILTER_EN    	0x00000040 /* use address filter */
844#define	MAC_RX_CFG_DISABLE_DISCARD	0x00000080 /* do not set abort bit */
845#define	MAC_RX_MAC2IPP_PKT_CNT_EN	0x00000200 /* rx pkt cnt -> BMAC-IPP */
846#define	MAC_RX_MAC_REG_RW_TEST_MASK	0x00000c00 /* BMAC reg RW test */
847#define	MAC_RX_MAC_REG_RW_TEST_SHIFT	10
848
849/* MAC Control Configuration Register */
850#define	MAC_CTRL_CFG_SEND_PAUSE_EN	0x00000001 /* send pause flow ctrl */
851#define	MAC_CTRL_CFG_RECV_PAUSE_EN	0x00000002 /* receive pause flow ctrl */
852#define	MAC_CTRL_CFG_PASS_CTRL		0x00000004 /* accept MAC ctrl pkts */
853
854/* MAC XIF Configuration Register */
855#define	MAC_XIF_TX_OUTPUT_EN		0x00000001 /* enable Tx output driver */
856#define	MAC_XIF_MII_INT_LOOPBACK	0x00000002 /* loopback GMII xmit data */
857#define	MAC_XIF_GMII_MODE		0x00000008 /* operates with GMII clks */
858#define	MAC_XIF_LINK_LED		0x00000020 /* LINKLED# active (low) */
859#define	MAC_XIF_LED_POLARITY		0x00000040 /* LED polarity */
860#define	MAC_XIF_SEL_CLK_25MHZ		0x00000080 /* Select 10/100Mbps */
861
862/* MAC IPG Registers */
863#define	BMAC_MIN_FRAME_MASK		0x3FF	   /* 10-bit reg */
864
865/* MAC Max Frame Size Register */
866#define	BMAC_MAX_BURST_MASK    		0x3FFF0000 /* max burst size [30:16] */
867#define	BMAC_MAX_BURST_SHIFT   		16
868#define	BMAC_MAX_FRAME_MASK    		0x00007FFF /* max frame size [14:0] */
869#define	BMAC_MAX_FRAME_SHIFT   		0
870
871/* MAC Preamble size register */
872#define	BMAC_PA_SIZE_MASK		0x000003FF
873	/* # of preable bytes TxMAC sends at the beginning of each frame */
874
875/*
876 * mac address registers:
877 *	register	contains			comparison
878 *	--------	--------			----------
879 *	0		16 MSB of primary MAC addr	[47:32] of DA field
880 *	1		16 middle bits ""		[31:16] of DA field
881 *	2		16 LSB ""			[15:0] of DA field
882 *	3*x		16MSB of alt MAC addr 1-7	[47:32] of DA field
883 *	4*x		16 middle bits ""		[31:16]
884 *	5*x		16 LSB ""			[15:0]
885 *	42		16 MSB of MAC CTRL addr		[47:32] of DA.
886 *	43		16 middle bits ""		[31:16]
887 *	44		16 LSB ""			[15:0]
888 *	MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
889 *	if there is a match, MAC will set the bit for alternative address
890 *	filter pass [15]
891 *
892 *	here is the map of registers given MAC address notation: a:b:c:d:e:f
893 *			ab		cd		ef
894 *	primary addr	reg 2		reg 1		reg 0
895 *	alt addr 1	reg 5		reg 4		reg 3
896 *	alt addr x	reg 5*x		reg 4*x		reg 3*x
897 *	|		|		|		|
898 *	|		|		|		|
899 *	alt addr 7	reg 23		reg 22		reg 21
900 *	ctrl addr	reg 44		reg 43		reg 42
901 */
902
903#define	BMAC_ALT_ADDR_BASE		0x118
904#define	BMAC_MAX_ALT_ADDR_ENTRY		7	   /* 7 alternate MAC addr */
905#define	BMAC_MAX_ADDR_ENTRY		(BMAC_MAX_ALT_ADDR_ENTRY + 1)
906
907/* hash table registers */
908#define	MAC_MAX_HASH_ENTRY		16
909
910/* 27-bit register has the current state for key state machines in the MAC */
911#define	MAC_SM_RLM_MASK			0x07800000
912#define	MAC_SM_RLM_SHIFT		23
913#define	MAC_SM_RX_FC_MASK		0x00700000
914#define	MAC_SM_RX_FC_SHIFT		20
915#define	MAC_SM_TLM_MASK			0x000F0000
916#define	MAC_SM_TLM_SHIFT		16
917#define	MAC_SM_ENCAP_SM_MASK		0x0000F000
918#define	MAC_SM_ENCAP_SM_SHIFT		12
919#define	MAC_SM_TX_REQ_MASK		0x00000C00
920#define	MAC_SM_TX_REQ_SHIFT		10
921#define	MAC_SM_TX_FC_MASK		0x000003C0
922#define	MAC_SM_TX_FC_SHIFT		6
923#define	MAC_SM_FIFO_WRITE_SEL_MASK	0x00000038
924#define	MAC_SM_FIFO_WRITE_SEL_SHIFT	3
925#define	MAC_SM_TX_FIFO_EMPTY_MASK	0x00000007
926#define	MAC_SM_TX_FIFO_EMPTY_SHIFT	0
927
928#define	BMAC_ADDR0_CMPEN		0x00000001
929#define	BMAC_ADDRN_CMPEN(x)		(BMAC_ADDR0_CMP_EN << (x))
930
931/* MAC Host Info Table Registers */
932#define	BMAC_MAX_HOST_INFO_ENTRY	9 	/* 9 host entries */
933
934/*
935 * ********************* XMAC registers *********************************
936 */
937
938/* Reset Register */
939#define	XTXMAC_SOFT_RST			0x00000001 /* XTX MAC software reset */
940#define	XTXMAC_REG_RST			0x00000002 /* XTX MAC registers reset */
941#define	XRXMAC_SOFT_RST			0x00000001 /* XRX MAC software reset */
942#define	XRXMAC_REG_RST			0x00000002 /* XRX MAC registers reset */
943
944/* XTX MAC Status Register */
945#define	XMAC_TX_FRAME_XMIT		0x00000001 /* successful tx frame */
946#define	XMAC_TX_UNDERRUN		0x00000002 /* starvation in xmit */
947#define	XMAC_TX_MAX_PACKET_ERR		0x00000004 /* XTX frame exceeds max */
948#define	XMAC_TX_OVERFLOW		0x00000008 /* XTX byte cnt overflow */
949#define	XMAC_TX_FIFO_XFR_ERR		0x00000010 /* xtlm state mach error */
950#define	XMAC_TX_BYTE_CNT_EXP		0x00000400 /* XTX byte cnt overflow */
951#define	XMAC_TX_FRAME_CNT_EXP		0x00000800 /* XTX frame cnt overflow */
952
953/* XRX MAC Status Register */
954#define	XMAC_RX_FRAME_RCVD		0x00000001 /* successful rx frame */
955#define	XMAC_RX_OVERFLOW		0x00000002 /* RX FIFO overflow */
956#define	XMAC_RX_UNDERFLOW		0x00000004 /* RX FIFO underrun */
957#define	XMAC_RX_CRC_ERR_CNT_EXP		0x00000008 /* crc error cnt rollover */
958#define	XMAC_RX_LEN_ERR_CNT_EXP		0x00000010 /* length err cnt rollover */
959#define	XMAC_RX_VIOL_ERR_CNT_EXP	0x00000020 /* code vio err rollover */
960#define	XMAC_RX_OCT_CNT_EXP		0x00000040 /* XRX MAC byte rollover */
961#define	XMAC_RX_HST_CNT1_EXP		0x00000080 /* XRX MAC hist1 rollover */
962#define	XMAC_RX_HST_CNT2_EXP		0x00000100 /* XRX MAC hist2 rollover */
963#define	XMAC_RX_HST_CNT3_EXP		0x00000200 /* XRX MAC hist3 rollover */
964#define	XMAC_RX_HST_CNT4_EXP		0x00000400 /* XRX MAC hist4 rollover */
965#define	XMAC_RX_HST_CNT5_EXP		0x00000800 /* XRX MAC hist5 rollover */
966#define	XMAC_RX_HST_CNT6_EXP		0x00001000 /* XRX MAC hist6 rollover */
967#define	XMAC_RX_BCAST_CNT_EXP		0x00002000 /* XRX BC cnt rollover */
968#define	XMAC_RX_MCAST_CNT_EXP		0x00004000 /* XRX MC cnt rollover */
969#define	XMAC_RX_FRAG_CNT_EXP		0x00008000 /* fragment cnt rollover */
970#define	XMAC_RX_ALIGNERR_CNT_EXP	0x00010000 /* framealign err rollover */
971#define	XMAC_RX_LINK_FLT_CNT_EXP	0x00020000 /* link fault cnt rollover */
972#define	XMAC_RX_REMOTE_FLT_DET		0x00040000 /* Remote Fault detected */
973#define	XMAC_RX_LOCAL_FLT_DET		0x00080000 /* Local Fault detected */
974#define	XMAC_RX_HST_CNT7_EXP		0x00100000 /* XRX MAC hist7 rollover */
975
976
977#define	XMAC_CTRL_PAUSE_RCVD		0x00000001 /* successful pause frame */
978#define	XMAC_CTRL_PAUSE_STATE		0x00000002 /* notpause-->pause */
979#define	XMAC_CTRL_NOPAUSE_STATE		0x00000004 /* pause-->notpause */
980#define	XMAC_CTRL_PAUSE_TIME_MASK	0xFFFF0000 /* value of pause time */
981#define	XMAC_CTRL_PAUSE_TIME_SHIFT	16
982
983/* XMAC Configuration Register */
984#define	XMAC_CONFIG_TX_BIT_MASK		0x000000ff /* bits [7:0] */
985#define	XMAC_CONFIG_RX_BIT_MASK		0x001fff00 /* bits [20:8] */
986#define	XMAC_CONFIG_XIF_BIT_MASK	0xffe00000 /* bits [31:21] */
987
988/* XTX MAC config bits */
989#define	XMAC_TX_CFG_TX_ENABLE		0x00000001 /* enable XTX MAC */
990#define	XMAC_TX_CFG_STRETCH_MD		0x00000002 /* WAN application */
991#define	XMAC_TX_CFG_VAR_MIN_IPG_EN	0x00000004 /* Transmit pkts < minpsz */
992#define	XMAC_TX_CFG_ALWAYS_NO_CRC	0x00000008 /* No CRC generated */
993
994#define	XMAC_WARNING_MSG_ENABLE		0x00000080 /* Sim warning msg enable */
995
996/* XRX MAC config bits */
997#define	XMAC_RX_CFG_RX_ENABLE		0x00000100 /* enable XRX MAC */
998#define	XMAC_RX_CFG_PROMISC		0x00000200 /* promisc mode enable */
999#define	XMAC_RX_CFG_PROMISC_GROUP  	0x00000400 /* accept all MC frames */
1000#define	XMAC_RX_CFG_ERR_CHK_DISABLE	0x00000800 /* do not set abort bit */
1001#define	XMAC_RX_CFG_CRC_CHK_DISABLE	0x00001000 /* disable CRC logic */
1002#define	XMAC_RX_CFG_RESERVED_MCAST	0x00002000 /* reserved MCaddr compare */
1003#define	XMAC_RX_CFG_CD_VIO_CHK		0x00004000 /* rx code violation chk */
1004#define	XMAC_RX_CFG_HASH_FILTER_EN	0x00008000 /* use hash table */
1005#define	XMAC_RX_CFG_ADDR_FILTER_EN	0x00010000 /* use alt addr filter */
1006#define	XMAC_RX_CFG_STRIP_CRC		0x00020000 /* strip last 4bytes (CRC) */
1007#define	XMAC_RX_MAC2IPP_PKT_CNT_EN	0x00040000 /* histo_cntr7 cnt mode */
1008#define	XMAC_RX_CFG_RX_PAUSE_EN		0x00080000 /* receive pause flow ctrl */
1009#define	XMAC_RX_CFG_PASS_FLOW_CTRL	0x00100000 /* accept MAC ctrl pkts */
1010
1011
1012/* MAC transceiver (XIF) configuration registers */
1013
1014#define	XMAC_XIF_FORCE_LED_ON		0x00200000 /* Force Link LED on */
1015#define	XMAC_XIF_LED_POLARITY		0x00400000 /* LED polarity */
1016#define	XMAC_XIF_SEL_POR_CLK_SRC	0x00800000 /* Select POR clk src */
1017#define	XMAC_XIF_TX_OUTPUT_EN		0x01000000 /* enable MII/GMII modes */
1018#define	XMAC_XIF_LOOPBACK		0x02000000 /* loopback xmac xgmii tx */
1019#define	XMAC_XIF_LFS_DISABLE		0x04000000 /* disable link fault sig */
1020#define	XMAC_XIF_MII_MODE_MASK		0x18000000 /* MII/GMII/XGMII mode */
1021#define	XMAC_XIF_MII_MODE_SHIFT		27
1022#define	XMAC_XIF_XGMII_MODE		0x00
1023#define	XMAC_XIF_GMII_MODE		0x01
1024#define	XMAC_XIF_MII_MODE		0x02
1025#define	XMAC_XIF_ILLEGAL_MODE		0x03
1026#define	XMAC_XIF_XPCS_BYPASS		0x20000000 /* use external xpcs */
1027#define	XMAC_XIF_1G_PCS_BYPASS		0x40000000 /* use external pcs */
1028#define	XMAC_XIF_SEL_CLK_25MHZ		0x80000000 /* 25Mhz clk for 100mbps */
1029
1030/* IPG register */
1031#define	XMAC_IPG_VALUE_MASK		0x00000007 /* IPG in XGMII mode */
1032#define	XMAC_IPG_VALUE_SHIFT		0
1033#define	XMAC_IPG_VALUE1_MASK		0x0000ff00 /* IPG in GMII/MII mode */
1034#define	XMAC_IPG_VALUE1_SHIFT		8
1035#define	XMAC_IPG_STRETCH_RATIO_MASK	0x001f0000
1036#define	XMAC_IPG_STRETCH_RATIO_SHIFT	16
1037#define	XMAC_IPG_STRETCH_CONST_MASK	0x00e00000
1038#define	XMAC_IPG_STRETCH_CONST_SHIFT	21
1039
1040#define	IPG_12_15_BYTE			3
1041#define	IPG_16_19_BYTE			4
1042#define	IPG_20_23_BYTE			5
1043#define	IPG1_12_BYTES			10
1044#define	IPG1_13_BYTES			11
1045#define	IPG1_14_BYTES			12
1046#define	IPG1_15_BYTES			13
1047#define	IPG1_16_BYTES			14
1048
1049
1050#define	XMAC_MIN_TX_FRM_SZ_MASK		0x3ff	   /* Min tx frame size */
1051#define	XMAC_MIN_TX_FRM_SZ_SHIFT	0
1052#define	XMAC_SLOT_TIME_MASK		0x0003fc00 /* slot time */
1053#define	XMAC_SLOT_TIME_SHIFT		10
1054#define	XMAC_MIN_RX_FRM_SZ_MASK		0x3ff00000 /* Min rx frame size */
1055#define	XMAC_MIN_RX_FRM_SZ_SHIFT	20
1056#define	XMAC_MAX_FRM_SZ_MASK		0x00003fff /* max tx frame size */
1057
1058/* State Machine Register */
1059#define	XMAC_SM_TX_LNK_MGMT_MASK	0x00000007
1060#define	XMAC_SM_TX_LNK_MGMT_SHIFT	0
1061#define	XMAC_SM_SOP_DETECT		0x00000008
1062#define	XMAC_SM_LNK_FLT_SIG_MASK	0x00000030
1063#define	XMAC_SM_LNK_FLT_SIG_SHIFT	4
1064#define	XMAC_SM_MII_GMII_MD_RX_LNK	0x00000040
1065#define	XMAC_SM_XGMII_MD_RX_LNK		0x00000080
1066#define	XMAC_SM_XGMII_ONLY_VAL_SIG	0x00000100
1067#define	XMAC_SM_ALT_ADR_N_HSH_FN_SIG	0x00000200
1068#define	XMAC_SM_RXMAC_IPP_STAT_MASK	0x00001c00
1069#define	XMAC_SM_RXMAC_IPP_STAT_SHIFT	10
1070#define	XMAC_SM_RXFIFO_WPTR_CLK_MASK	0x007c0000
1071#define	XMAC_SM_RXFIFO_WPTR_CLK_SHIFT	18
1072#define	XMAC_SM_RXFIFO_RPTR_CLK_MASK	0x0F800000
1073#define	XMAC_SM_RXFIFO_RPTR_CLK_SHIFT	23
1074#define	XMAC_SM_TXFIFO_FULL_CLK		0x10000000
1075#define	XMAC_SM_TXFIFO_EMPTY_CLK	0x20000000
1076#define	XMAC_SM_RXFIFO_FULL_CLK		0x40000000
1077#define	XMAC_SM_RXFIFO_EMPTY_CLK	0x80000000
1078
1079/* Internal Signals 1 Register */
1080#define	XMAC_IS1_OPP_TXMAC_STAT_MASK	0x0000000F
1081#define	XMAC_IS1_OPP_TXMAC_STAT_SHIFT	0
1082#define	XMAC_IS1_OPP_TXMAC_ABORT	0x00000010
1083#define	XMAC_IS1_OPP_TXMAC_TAG 		0x00000020
1084#define	XMAC_IS1_OPP_TXMAC_ACK		0x00000040
1085#define	XMAC_IS1_TXMAC_OPP_REQ		0x00000080
1086#define	XMAC_IS1_RXMAC_IPP_STAT_MASK	0x0FFFFF00
1087#define	XMAC_IS1_RXMAC_IPP_STAT_SHIFT	8
1088#define	XMAC_IS1_RXMAC_IPP_CTRL		0x10000000
1089#define	XMAC_IS1_RXMAC_IPP_TAG		0x20000000
1090#define	XMAC_IS1_IPP_RXMAC_REQ		0x40000000
1091#define	XMAC_IS1_RXMAC_IPP_ACK		0x80000000
1092
1093/* Internal Signals 2 Register */
1094#define	XMAC_IS2_TX_HB_TIMER_MASK	0x0000000F
1095#define	XMAC_IS2_TX_HB_TIMER_SHIFT	0
1096#define	XMAC_IS2_RX_HB_TIMER_MASK	0x000000F0
1097#define	XMAC_IS2_RX_HB_TIMER_SHIFT	4
1098#define	XMAC_IS2_XPCS_RXC_MASK		0x0000FF00
1099#define	XMAC_IS2_XPCS_RXC_SHIFT		8
1100#define	XMAC_IS2_XPCS_TXC_MASK		0x00FF0000
1101#define	XMAC_IS2_XPCS_TXC_SHIFT		16
1102#define	XMAC_IS2_LOCAL_FLT_OC_SYNC	0x01000000
1103#define	XMAC_IS2_RMT_FLT_OC_SYNC	0x02000000
1104
1105/* Register size masking */
1106
1107#define	XTXMAC_FRM_CNT_MASK		0xFFFFFFFF
1108#define	XTXMAC_BYTE_CNT_MASK		0xFFFFFFFF
1109#define	XRXMAC_CRC_ER_CNT_MASK		0x000000FF
1110#define	XRXMAC_MPSZER_CNT_MASK		0x000000FF
1111#define	XRXMAC_CD_VIO_CNT_MASK		0x000000FF
1112#define	XRXMAC_BT_CNT_MASK		0xFFFFFFFF
1113#define	XRXMAC_HIST_CNT1_MASK		0x001FFFFF
1114#define	XRXMAC_HIST_CNT2_MASK		0x001FFFFF
1115#define	XRXMAC_HIST_CNT3_MASK		0x000FFFFF
1116#define	XRXMAC_HIST_CNT4_MASK		0x0007FFFF
1117#define	XRXMAC_HIST_CNT5_MASK		0x0003FFFF
1118#define	XRXMAC_HIST_CNT6_MASK		0x0001FFFF
1119#define	XRXMAC_HIST_CNT7_MASK		0x07FFFFFF
1120#define	XRXMAC_BC_FRM_CNT_MASK		0x001FFFFF
1121#define	XRXMAC_MC_FRM_CNT_MASK		0x001FFFFF
1122#define	XRXMAC_FRAG_CNT_MASK		0x001FFFFF
1123#define	XRXMAC_AL_ER_CNT_MASK		0x000000FF
1124#define	XMAC_LINK_FLT_CNT_MASK		0x000000FF
1125#define	BTXMAC_FRM_CNT_MASK		0x001FFFFF
1126#define	BTXMAC_BYTE_CNT_MASK		0x07FFFFFF
1127#define	RXMAC_FRM_CNT_MASK		0x0000FFFF
1128#define	BRXMAC_BYTE_CNT_MASK		0x07FFFFFF
1129#define	BMAC_AL_ER_CNT_MASK		0x0000FFFF
1130#define	MAC_LEN_ER_CNT_MASK		0x0000FFFF
1131#define	BMAC_CRC_ER_CNT_MASK		0x0000FFFF
1132#define	BMAC_CD_VIO_CNT_MASK		0x0000FFFF
1133#define	XMAC_XPCS_DESKEW_ERR_CNT_MASK	0x000000FF
1134#define	XMAC_XPCS_SYM_ERR_CNT_L0_MASK	0x0000FFFF
1135#define	XMAC_XPCS_SYM_ERR_CNT_L1_MASK	0xFFFF0000
1136#define	XMAC_XPCS_SYM_ERR_CNT_L1_SHIFT	16
1137#define	XMAC_XPCS_SYM_ERR_CNT_L2_MASK	0x0000FFFF
1138#define	XMAC_XPCS_SYM_ERR_CNT_L3_MASK	0xFFFF0000
1139#define	XMAC_XPCS_SYM_ERR_CNT_L3_SHIFT	16
1140
1141/* Alternate MAC address registers */
1142#define	XMAC_MAX_ALT_ADDR_ENTRY		16	   /* 16 alternate MAC addrs */
1143#define	XMAC_MAX_ADDR_ENTRY		(XMAC_MAX_ALT_ADDR_ENTRY + 1)
1144
1145/* Max / Min parameters for Neptune MAC */
1146
1147#define	MAC_MAX_ALT_ADDR_ENTRY		XMAC_MAX_ALT_ADDR_ENTRY
1148#define	MAC_MAX_HOST_INFO_ENTRY		XMAC_MAX_HOST_INFO_ENTRY
1149
1150/* HostInfo entry for the unique MAC address */
1151#define	XMAC_UNIQUE_HOST_INFO_ENTRY	17
1152#define	BMAC_UNIQUE_HOST_INFO_ENTRY	0
1153
1154/* HostInfo entry for the multicat address */
1155#define	XMAC_MULTI_HOST_INFO_ENTRY	16
1156#define	BMAC_MULTI_HOST_INFO_ENTRY	8
1157
1158/* XMAC Host Info Register */
1159typedef union hostinfo {
1160
1161	uint64_t value;
1162
1163	struct {
1164#if defined(_BIG_ENDIAN)
1165		uint32_t msw;	/* Most significant word */
1166		uint32_t lsw;	/* Least significant word */
1167#elif defined(_LITTLE_ENDIAN)
1168		uint32_t lsw;	/* Least significant word */
1169		uint32_t msw;	/* Most significant word */
1170#endif
1171	} val;
1172	struct {
1173#if defined(_BIG_ENDIAN)
1174		uint32_t	w1;
1175#endif
1176		struct {
1177#if defined(_BIT_FIELDS_HTOL)
1178		uint32_t reserved2	: 23;
1179		uint32_t mac_pref	: 1;
1180		uint32_t reserved1	: 5;
1181		uint32_t rdc_tbl_num	: 3;
1182#elif defined(_BIT_FIELDS_LTOH)
1183		uint32_t rdc_tbl_num	: 3;
1184		uint32_t reserved1	: 5;
1185		uint32_t mac_pref	: 1;
1186		uint32_t reserved2	: 23;
1187#endif
1188		} w0;
1189
1190#if defined(_LITTLE_ENDIAN)
1191		uint32_t	w1;
1192#endif
1193	} bits;
1194
1195} hostinfo_t;
1196
1197typedef union hostinfo *hostinfo_pt;
1198
1199#define	XMAC_HI_RDC_TBL_NUM_MASK	0x00000007
1200#define	XMAC_HI_MAC_PREF		0x00000100
1201
1202#define	XMAC_MAX_HOST_INFO_ENTRY	20	   /* 20 host entries */
1203
1204/*
1205 * ******************** MIF registers *********************************
1206 */
1207
1208/*
1209 * 32-bit register serves as an instruction register when the MIF is
1210 * programmed in frame mode. load this register w/ a valid instruction
1211 * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1212 * execution completion. during a read operation, this register will also
1213 * contain the 16-bit data returned by the transceiver. unless specified
1214 * otherwise, fields are considered "don't care" when polling for
1215 * completion.
1216 */
1217
1218#define	MIF_FRAME_START_MASK		0xC0000000 /* start of frame mask */
1219#define	MIF_FRAME_ST_22			0x40000000 /* STart of frame, Cl 22 */
1220#define	MIF_FRAME_ST_45			0x00000000 /* STart of frame, Cl 45 */
1221#define	MIF_FRAME_OPCODE_MASK		0x30000000 /* opcode */
1222#define	MIF_FRAME_OP_READ_22		0x20000000 /* read OPcode, Cl 22 */
1223#define	MIF_FRAME_OP_WRITE_22		0x10000000 /* write OPcode, Cl 22 */
1224#define	MIF_FRAME_OP_ADDR_45		0x00000000 /* addr of reg to access */
1225#define	MIF_FRAME_OP_READ_45		0x30000000 /* read OPcode, Cl 45 */
1226#define	MIF_FRAME_OP_WRITE_45		0x10000000 /* write OPcode, Cl 45 */
1227#define	MIF_FRAME_OP_P_R_I_A_45		0x10000000 /* post-read-inc-addr */
1228#define	MIF_FRAME_PHY_ADDR_MASK		0x0F800000 /* phy address mask */
1229#define	MIF_FRAME_PHY_ADDR_SHIFT	23
1230#define	MIF_FRAME_REG_ADDR_MASK		0x007C0000 /* reg addr in Cl 22 */
1231						/* dev addr in Cl 45 */
1232#define	MIF_FRAME_REG_ADDR_SHIFT	18
1233#define	MIF_FRAME_TURN_AROUND_MSB	0x00020000 /* turn around, MSB. */
1234#define	MIF_FRAME_TURN_AROUND_LSB	0x00010000 /* turn around, LSB. */
1235#define	MIF_FRAME_DATA_MASK		0x0000FFFF /* instruction payload */
1236
1237/* Clause 45 frame field values */
1238#define	FRAME45_ST		0
1239#define	FRAME45_OP_ADDR		0
1240#define	FRAME45_OP_WRITE	1
1241#define	FRAME45_OP_READ_INC	2
1242#define	FRAME45_OP_READ		3
1243
1244typedef union _mif_frame_t {
1245
1246	uint64_t value;
1247
1248	struct {
1249#if defined(_BIG_ENDIAN)
1250		uint32_t msw;	/* Most significant word */
1251		uint32_t lsw;	/* Least significant word */
1252#elif defined(_LITTLE_ENDIAN)
1253		uint32_t lsw;	/* Least significant word */
1254		uint32_t msw;	/* Most significant word */
1255#endif
1256	} val;
1257	struct {
1258#if defined(_BIG_ENDIAN)
1259		uint32_t	w1;
1260#endif
1261		struct {
1262#if defined(_BIT_FIELDS_HTOL)
1263		uint32_t st		: 2;
1264		uint32_t op		: 2;
1265		uint32_t phyad		: 5;
1266		uint32_t regad		: 5;
1267		uint32_t ta_msb		: 1;
1268		uint32_t ta_lsb		: 1;
1269		uint32_t data		: 16;
1270#elif defined(_BIT_FIELDS_LTOH)
1271		uint32_t data		: 16;
1272		uint32_t ta_lsb		: 1;
1273		uint32_t ta_msb		: 1;
1274		uint32_t regad		: 5;
1275		uint32_t phyad		: 5;
1276		uint32_t op		: 2;
1277		uint32_t st		: 2;
1278#endif
1279		} w0;
1280
1281#if defined(_LITTLE_ENDIAN)
1282		uint32_t	w1;
1283#endif
1284	} bits;
1285} mif_frame_t;
1286
1287#define	MIF_CFG_POLL_EN			0x00000008 /* enable polling */
1288#define	MIF_CFG_BB_MODE			0x00000010 /* bit-bang mode */
1289#define	MIF_CFG_POLL_REG_MASK		0x000003E0 /* reg addr to be polled */
1290#define	MIF_CFG_POLL_REG_SHIFT		5
1291#define	MIF_CFG_POLL_PHY_MASK		0x00007C00 /* XCVR addr to be polled */
1292#define	MIF_CFG_POLL_PHY_SHIFT		10
1293#define	MIF_CFG_INDIRECT_MODE		0x0000800
1294					/* used to decide if Cl 22 */
1295					/* or Cl 45 frame is */
1296					/* constructed. */
1297					/* 1 = Clause 45,ST = '00' */
1298					/* 0 = Clause 22,ST = '01' */
1299#define	MIF_CFG_ATCE_GE_EN	0x00010000 /* Enable ATCA gigabit mode */
1300
1301typedef union _mif_cfg_t {
1302
1303	uint64_t value;
1304
1305	struct {
1306#if defined(_BIG_ENDIAN)
1307		uint32_t msw;	/* Most significant word */
1308		uint32_t lsw;	/* Least significant word */
1309
1310#elif defined(_LITTLE_ENDIAN)
1311		uint32_t lsw;	/* Least significant word */
1312		uint32_t msw;	/* Most significant word */
1313#endif
1314	} val;
1315	struct {
1316#if defined(_BIG_ENDIAN)
1317		uint32_t	w1;
1318#endif
1319		struct {
1320#if defined(_BIT_FIELDS_HTOL)
1321		uint32_t res2		: 15;
1322		uint32_t atca_ge	: 1;
1323		uint32_t indirect_md	: 1;
1324		uint32_t phy_addr	: 5;
1325		uint32_t reg_addr	: 5;
1326		uint32_t bb_mode	: 1;
1327		uint32_t poll_en	: 1;
1328		uint32_t res1		: 2;
1329		uint32_t res		: 1;
1330#elif defined(_BIT_FIELDS_LTOH)
1331		uint32_t res		: 1;
1332		uint32_t res1		: 2;
1333		uint32_t poll_en	: 1;
1334		uint32_t bb_mode	: 1;
1335		uint32_t reg_addr	: 5;
1336		uint32_t phy_addr	: 5;
1337		uint32_t indirect_md	: 1;
1338		uint32_t atca_ge	: 1;
1339		uint32_t res2		: 15;
1340#endif
1341		} w0;
1342
1343#if defined(_LITTLE_ENDIAN)
1344		uint32_t	w1;
1345#endif
1346	} bits;
1347
1348} mif_cfg_t;
1349
1350#define	MIF_POLL_STATUS_DATA_MASK	0xffff0000
1351#define	MIF_POLL_STATUS_STAT_MASK	0x0000ffff
1352
1353typedef union _mif_poll_stat_t {
1354	uint64_t value;
1355
1356	struct {
1357#if defined(_BIG_ENDIAN)
1358		uint32_t msw;	/* Most significant word */
1359		uint32_t lsw;	/* Least significant word */
1360#elif defined(_LITTLE_ENDIAN)
1361		uint32_t lsw;	/* Least significant word */
1362		uint32_t msw;	/* Most significant word */
1363#endif
1364	} val;
1365	struct {
1366#if defined(_BIG_ENDIAN)
1367		uint32_t	w1;
1368#endif
1369		struct {
1370#if defined(_BIT_FIELDS_HTOL)
1371		uint16_t data;
1372		uint16_t status;
1373#elif defined(_BIT_FIELDS_LTOH)
1374		uint16_t status;
1375		uint16_t data;
1376#endif
1377		} w0;
1378
1379#if defined(_LITTLE_ENDIAN)
1380		uint32_t	w1;
1381#endif
1382	} bits;
1383} mif_poll_stat_t;
1384
1385
1386#define	MIF_POLL_MASK_MASK	0x0000ffff
1387
1388typedef union _mif_poll_mask_t {
1389	uint64_t value;
1390
1391	struct {
1392#if defined(_BIG_ENDIAN)
1393		uint32_t msw;	/* Most significant word */
1394		uint32_t lsw;	/* Least significant word */
1395#elif defined(_LITTLE_ENDIAN)
1396		uint32_t lsw;	/* Least significant word */
1397		uint32_t msw;	/* Most significant word */
1398#endif
1399	} val;
1400	struct {
1401#if defined(_BIG_ENDIAN)
1402		uint32_t	w1;
1403#endif
1404		struct {
1405#if defined(_BIT_FIELDS_HTOL)
1406		uint16_t rsvd;
1407		uint16_t mask;
1408#elif defined(_BIT_FIELDS_LTOH)
1409		uint16_t mask;
1410		uint16_t rsvd;
1411#endif
1412		} w0;
1413
1414#if defined(_LITTLE_ENDIAN)
1415		uint32_t	w1;
1416#endif
1417	} bits;
1418} mif_poll_mask_t;
1419
1420#define	MIF_STATUS_INIT_DONE_MASK	0x00000001
1421#define	MIF_STATUS_XGE_ERR0_MASK	0x00000002
1422#define	MIF_STATUS_XGE_ERR1_MASK	0x00000004
1423#define	MIF_STATUS_PEU_ERR_MASK		0x00000008
1424#define	MIF_STATUS_EXT_PHY_INTR0_MASK	0x00000010
1425#define	MIF_STATUS_EXT_PHY_INTR1_MASK	0x00000020
1426
1427typedef union _mif_stat_t {
1428	uint64_t value;
1429
1430	struct {
1431#if defined(_BIG_ENDIAN)
1432		uint32_t msw;	/* Most significant word */
1433		uint32_t lsw;	/* Least significant word */
1434#elif defined(_LITTLE_ENDIAN)
1435		uint32_t lsw;	/* Least significant word */
1436		uint32_t msw;	/* Most significant word */
1437#endif
1438	} val;
1439	struct {
1440#if defined(_BIG_ENDIAN)
1441		uint32_t	w1;
1442#endif
1443		struct {
1444#if defined(_BIT_FIELDS_HTOL)
1445		uint32_t rsvd:26;
1446		uint32_t ext_phy_intr_flag1:1;
1447		uint32_t ext_phy_intr_flag0:1;
1448		uint32_t peu_err:1;
1449		uint32_t xge_err1:1;
1450		uint32_t xge_err0:1;
1451		uint32_t mif_init_done_stat:1;
1452
1453#elif defined(_BIT_FIELDS_LTOH)
1454		uint32_t mif_init_done_stat:1;
1455		uint32_t xge_err0:1;
1456		uint32_t xge_err1:1;
1457		uint32_t ext_phy_intr_flag0:1;
1458		uint32_t ext_phy_intr_flag1:1;
1459		uint32_t rsvd:26;
1460#endif
1461		} w0;
1462
1463#if defined(_LITTLE_ENDIAN)
1464		uint32_t	w1;
1465#endif
1466	} bits;
1467} mif_stat_t;
1468
1469/* MIF State Machine Register */
1470
1471#define	MIF_SM_EXECUTION_MASK		0x0000003f /* execution state */
1472#define	MIF_SM_EXECUTION_SHIFT		0
1473#define	MIF_SM_CONTROL_MASK		0x000001c0 /* control state */
1474#define	MIF_SM_CONTROL_MASK_SHIFT	6
1475#define	MIF_SM_MDI			0x00000200
1476#define	MIF_SM_MDO			0x00000400
1477#define	MIF_SM_MDO_EN			0x00000800
1478#define	MIF_SM_MDC			0x00001000
1479#define	MIF_SM_MDI_0			0x00002000
1480#define	MIF_SM_MDI_1			0x00004000
1481#define	MIF_SM_MDI_2			0x00008000
1482#define	MIF_SM_PORT_ADDR_MASK		0x001f0000
1483#define	MIF_SM_PORT_ADDR_SHIFT		16
1484#define	MIF_SM_INT_SIG_MASK		0xffe00000
1485#define	MIF_SM_INT_SIG_SHIFT		21
1486
1487
1488/*
1489 * ******************** PCS registers *********************************
1490 */
1491
1492/* PCS Registers */
1493#define	PCS_MII_CTRL_1000_SEL		0x0040	   /* reads 1. ignored on wr */
1494#define	PCS_MII_CTRL_COLLISION_TEST	0x0080	   /* COL signal */
1495#define	PCS_MII_CTRL_DUPLEX		0x0100	   /* forced 0x0. */
1496#define	PCS_MII_RESTART_AUTONEG		0x0200	   /* self clearing. */
1497#define	PCS_MII_ISOLATE			0x0400	   /* read 0. ignored on wr */
1498#define	PCS_MII_POWER_DOWN		0x0800	   /* read 0. ignored on wr */
1499#define	PCS_MII_AUTONEG_EN		0x1000	   /* autonegotiation */
1500#define	PCS_MII_10_100_SEL		0x2000	   /* read 0. ignored on wr */
1501#define	PCS_MII_RESET			0x8000	   /* reset PCS. */
1502
1503typedef union _pcs_ctrl_t {
1504	uint64_t value;
1505
1506	struct {
1507#if defined(_BIG_ENDIAN)
1508		uint32_t msw;	/* Most significant word */
1509		uint32_t lsw;	/* Least significant word */
1510#elif defined(_LITTLE_ENDIAN)
1511		uint32_t lsw;	/* Least significant word */
1512		uint32_t msw;	/* Most significant word */
1513#endif
1514	} val;
1515	struct {
1516#if defined(_BIG_ENDIAN)
1517		uint32_t	w1;
1518#endif
1519		struct {
1520#if defined(_BIT_FIELDS_HTOL)
1521			uint32_t res0		: 16;
1522			uint32_t reset		: 1;
1523			uint32_t res1		: 1;
1524			uint32_t sel_10_100	: 1;
1525			uint32_t an_enable	: 1;
1526			uint32_t pwr_down	: 1;
1527			uint32_t isolate	: 1;
1528			uint32_t restart_an	: 1;
1529			uint32_t duplex		: 1;
1530			uint32_t col_test	: 1;
1531			uint32_t sel_1000	: 1;
1532			uint32_t res2		: 6;
1533#elif defined(_BIT_FIELDS_LTOH)
1534			uint32_t res2		: 6;
1535			uint32_t sel_1000	: 1;
1536			uint32_t col_test	: 1;
1537			uint32_t duplex		: 1;
1538			uint32_t restart_an	: 1;
1539			uint32_t isolate	: 1;
1540			uint32_t pwr_down	: 1;
1541			uint32_t an_enable	: 1;
1542			uint32_t sel_10_100	: 1;
1543			uint32_t res1		: 1;
1544			uint32_t reset		: 1;
1545			uint32_t res0		: 16;
1546#endif
1547		} w0;
1548
1549#if defined(_LITTLE_ENDIAN)
1550		uint32_t	w1;
1551#endif
1552	} bits;
1553} pcs_ctrl_t;
1554
1555#define	PCS_MII_STATUS_EXTEND_CAP	0x0001	   /* reads 0 */
1556#define	PCS_MII_STATUS_JABBER_DETECT	0x0002	   /* reads 0 */
1557#define	PCS_MII_STATUS_LINK_STATUS	0x0004	   /* link status */
1558#define	PCS_MII_STATUS_AUTONEG_ABLE	0x0008	   /* reads 1 */
1559#define	PCS_MII_STATUS_REMOTE_FAULT	0x0010	   /* remote fault detected */
1560#define	PCS_MII_STATUS_AUTONEG_COMP	0x0020	   /* auto-neg completed */
1561#define	PCS_MII_STATUS_EXTEND_STATUS	0x0100	   /* 1000 Base-X PHY */
1562
1563typedef union _pcs_stat_t {
1564	uint64_t value;
1565
1566	struct {
1567#if defined(_BIG_ENDIAN)
1568		uint32_t msw;	/* Most significant word */
1569		uint32_t lsw;	/* Least significant word */
1570#elif defined(_LITTLE_ENDIAN)
1571		uint32_t lsw;	/* Least significant word */
1572		uint32_t msw;	/* Most significant word */
1573#endif
1574	} val;
1575	struct {
1576#if defined(_BIG_ENDIAN)
1577		uint32_t	w1;
1578#endif
1579		struct {
1580#if defined(_BIT_FIELDS_HTOL)
1581		uint32_t res0		: 23;
1582		uint32_t ext_stat	: 1;
1583		uint32_t res1		: 2;
1584		uint32_t an_complete	: 1;
1585		uint32_t remote_fault	: 1;
1586		uint32_t an_able	: 1;
1587		uint32_t link_stat	: 1;
1588		uint32_t jabber_detect	: 1;
1589		uint32_t ext_cap	: 1;
1590#elif defined(_BIT_FIELDS_LTOH)
1591		uint32_t ext_cap	: 1;
1592		uint32_t jabber_detect	: 1;
1593		uint32_t link_stat	: 1;
1594		uint32_t an_able	: 1;
1595		uint32_t remote_fault	: 1;
1596		uint32_t an_complete	: 1;
1597		uint32_t res1		: 2;
1598		uint32_t ext_stat	: 1;
1599		uint32_t res0		: 23;
1600#endif
1601		} w0;
1602
1603#if defined(_LITTLE_ENDIAN)
1604		uint32_t	w1;
1605#endif
1606	} bits;
1607} pcs_stat_t;
1608
1609#define	PCS_MII_ADVERT_FD		0x0020	   /* advertise full duplex */
1610#define	PCS_MII_ADVERT_HD		0x0040	   /* advertise half-duplex */
1611#define	PCS_MII_ADVERT_SYM_PAUSE	0x0080	   /* advertise PAUSE sym */
1612#define	PCS_MII_ADVERT_ASYM_PAUSE	0x0100	   /* advertises PAUSE asym */
1613#define	PCS_MII_ADVERT_RF_MASK		0x3000	   /* remote fault */
1614#define	PCS_MII_ADVERT_RF_SHIFT		12
1615#define	PCS_MII_ADVERT_ACK		0x4000	   /* (ro) */
1616#define	PCS_MII_ADVERT_NEXT_PAGE	0x8000	   /* (ro) forced 0x0 */
1617
1618#define	PCS_MII_LPA_FD			PCS_MII_ADVERT_FD
1619#define	PCS_MII_LPA_HD			PCS_MII_ADVERT_HD
1620#define	PCS_MII_LPA_SYM_PAUSE		PCS_MII_ADVERT_SYM_PAUSE
1621#define	PCS_MII_LPA_ASYM_PAUSE		PCS_MII_ADVERT_ASYM_PAUSE
1622#define	PCS_MII_LPA_RF_MASK		PCS_MII_ADVERT_RF_MASK
1623#define	PCS_MII_LPA_RF_SHIFT		PCS_MII_ADVERT_RF_SHIFT
1624#define	PCS_MII_LPA_ACK			PCS_MII_ADVERT_ACK
1625#define	PCS_MII_LPA_NEXT_PAGE		PCS_MII_ADVERT_NEXT_PAGE
1626
1627typedef union _pcs_anar_t {
1628	uint64_t value;
1629
1630	struct {
1631#if defined(_BIG_ENDIAN)
1632		uint32_t msw;	/* Most significant word */
1633		uint32_t lsw;	/* Least significant word */
1634#elif defined(_LITTLE_ENDIAN)
1635		uint32_t lsw;	/* Least significant word */
1636		uint32_t msw;	/* Most significant word */
1637#endif
1638	} val;
1639	struct {
1640#if defined(_BIG_ENDIAN)
1641		uint32_t	w1;
1642#endif
1643		struct {
1644#if defined(_BIT_FIELDS_HTOL)
1645		uint32_t res0		: 16;
1646		uint32_t next_page	: 1;
1647		uint32_t ack		: 1;
1648		uint32_t remote_fault	: 2;
1649		uint32_t res1		: 3;
1650		uint32_t asm_pause	: 1;
1651		uint32_t pause		: 1;
1652		uint32_t half_duplex	: 1;
1653		uint32_t full_duplex	: 1;
1654		uint32_t res2		: 5;
1655#elif defined(_BIT_FIELDS_LTOH)
1656		uint32_t res2		: 5;
1657		uint32_t full_duplex	: 1;
1658		uint32_t half_duplex	: 1;
1659		uint32_t pause		: 1;
1660		uint32_t asm_pause	: 1;
1661		uint32_t res1		: 3;
1662		uint32_t remore_fault	: 2;
1663		uint32_t ack		: 1;
1664		uint32_t next_page	: 1;
1665		uint32_t res0		: 16;
1666#endif
1667		} w0;
1668
1669#if defined(_LITTLE_ENDIAN)
1670		uint32_t	w1;
1671#endif
1672	} bits;
1673} pcs_anar_t, *p_pcs_anar_t;
1674
1675#define	PCS_CFG_EN			0x0001	   /* enable PCS. */
1676#define	PCS_CFG_SD_OVERRIDE		0x0002
1677#define	PCS_CFG_SD_ACTIVE_LOW		0x0004	   /* sig detect active low */
1678#define	PCS_CFG_JITTER_STUDY_MASK	0x0018	   /* jitter measurements */
1679#define	PCS_CFG_JITTER_STUDY_SHIFT	4
1680#define	PCS_CFG_10MS_TIMER_OVERRIDE	0x0020	   /* shortens autoneg timer */
1681#define	PCS_CFG_MASK			0x0040	   /* PCS global mask bit */
1682
1683typedef union _pcs_cfg_t {
1684	uint64_t value;
1685
1686	struct {
1687#if defined(_BIG_ENDIAN)
1688		uint32_t msw;	/* Most significant word */
1689		uint32_t lsw;	/* Least significant word */
1690#elif defined(_LITTLE_ENDIAN)
1691		uint32_t lsw;	/* Least significant word */
1692		uint32_t msw;	/* Most significant word */
1693#endif
1694	} val;
1695	struct {
1696#if defined(_BIG_ENDIAN)
1697		uint32_t	w1;
1698#endif
1699		struct {
1700#if defined(_BIT_FIELDS_HTOL)
1701		uint32_t res0			: 25;
1702		uint32_t mask			: 1;
1703		uint32_t override_10ms_timer	: 1;
1704		uint32_t jitter_study		: 2;
1705		uint32_t sig_det_a_low		: 1;
1706		uint32_t sig_det_override	: 1;
1707		uint32_t enable			: 1;
1708#elif defined(_BIT_FIELDS_LTOH)
1709		uint32_t enable			: 1;
1710		uint32_t sig_det_override	: 1;
1711		uint32_t sig_det_a_low		: 1;
1712		uint32_t jitter_study		: 2;
1713		uint32_t override_10ms_timer	: 1;
1714		uint32_t mask			: 1;
1715		uint32_t res0			: 25;
1716#endif
1717		} w0;
1718
1719#if defined(_LITTLE_ENDIAN)
1720		uint32_t	w1;
1721#endif
1722	} bits;
1723} pcs_cfg_t, *p_pcs_cfg_t;
1724
1725
1726/* used for diagnostic purposes. bits 20-22 autoclear on read */
1727#define	PCS_SM_TX_STATE_MASK		0x0000000F /* Tx idle state mask */
1728#define	PCS_SM_TX_STATE_SHIFT		0
1729#define	PCS_SM_RX_STATE_MASK		0x000000F0 /* Rx idle state mask */
1730#define	PCS_SM_RX_STATE_SHIFT		4
1731#define	PCS_SM_WORD_SYNC_STATE_MASK	0x00000700 /* loss of sync state mask */
1732#define	PCS_SM_WORD_SYNC_STATE_SHIFT	8
1733#define	PCS_SM_SEQ_DETECT_STATE_MASK	0x00001800 /* sequence detect */
1734#define	PCS_SM_SEQ_DETECT_STATE_SHIFT	11
1735#define	PCS_SM_LINK_STATE_MASK		0x0001E000 /* link state */
1736#define	PCS_SM_LINK_STATE_SHIFT		13
1737#define	PCS_SM_LOSS_LINK_C		0x00100000 /* loss of link */
1738#define	PCS_SM_LOSS_LINK_SYNC		0x00200000 /* loss of sync */
1739#define	PCS_SM_LOSS_SIGNAL_DETECT	0x00400000 /* signal detect fail */
1740#define	PCS_SM_NO_LINK_BREAKLINK	0x01000000 /* receipt of breaklink */
1741#define	PCS_SM_NO_LINK_SERDES		0x02000000 /* serdes initializing */
1742#define	PCS_SM_NO_LINK_C		0x04000000 /* C codes not stable */
1743#define	PCS_SM_NO_LINK_SYNC		0x08000000 /* word sync not achieved */
1744#define	PCS_SM_NO_LINK_WAIT_C		0x10000000 /* waiting for C codes */
1745#define	PCS_SM_NO_LINK_NO_IDLE		0x20000000 /* linkpartner send C code */
1746
1747typedef union _pcs_stat_mc_t {
1748	uint64_t value;
1749
1750	struct {
1751#if defined(_BIG_ENDIAN)
1752		uint32_t msw;	/* Most significant word */
1753		uint32_t lsw;	/* Least significant word */
1754#elif defined(_LITTLE_ENDIAN)
1755		uint32_t lsw;	/* Least significant word */
1756		uint32_t msw;	/* Most significant word */
1757#endif
1758	} val;
1759	struct {
1760#if defined(_BIG_ENDIAN)
1761		uint32_t	w1;
1762#endif
1763		struct {
1764#if defined(_BIT_FIELDS_HTOL)
1765		uint32_t res2		: 2;
1766		uint32_t lnk_dwn_ni	: 1;
1767		uint32_t lnk_dwn_wc	: 1;
1768		uint32_t lnk_dwn_ls	: 1;
1769		uint32_t lnk_dwn_nc	: 1;
1770		uint32_t lnk_dwn_ser	: 1;
1771		uint32_t lnk_loss_bc	: 1;
1772		uint32_t res1		: 1;
1773		uint32_t loss_sd	: 1;
1774		uint32_t lnk_loss_sync	: 1;
1775		uint32_t lnk_loss_c	: 1;
1776		uint32_t res0		: 3;
1777		uint32_t link_cfg_stat	: 4;
1778		uint32_t seq_detc_stat	: 2;
1779		uint32_t word_sync	: 3;
1780		uint32_t rx_ctrl	: 4;
1781		uint32_t tx_ctrl	: 4;
1782#elif defined(_BIT_FIELDS_LTOH)
1783		uint32_t tx_ctrl	: 4;
1784		uint32_t rx_ctrl	: 4;
1785		uint32_t word_sync	: 3;
1786		uint32_t seq_detc_stat	: 2;
1787		uint32_t link_cfg_stat	: 4;
1788		uint32_t res0		: 3;
1789		uint32_t lnk_loss_c	: 1;
1790		uint32_t lnk_loss_sync	: 1;
1791		uint32_t loss_sd	: 1;
1792		uint32_t res1		: 1;
1793		uint32_t lnk_loss_bc	: 1;
1794		uint32_t lnk_dwn_ser	: 1;
1795		uint32_t lnk_dwn_nc	: 1;
1796		uint32_t lnk_dwn_ls	: 1;
1797		uint32_t lnk_dwn_wc	: 1;
1798		uint32_t lnk_dwn_ni	: 1;
1799		uint32_t res2		: 2;
1800#endif
1801		} w0;
1802
1803#if defined(_LITTLE_ENDIAN)
1804		uint32_t	w1;
1805#endif
1806	} bits;
1807} pcs_stat_mc_t, *p_pcs_stat_mc_t;
1808
1809#define	PCS_INTR_STATUS_LINK_CHANGE	0x04	/* link status has changed */
1810
1811/*
1812 * control which network interface is used. no more than one bit should
1813 * be set.
1814 */
1815#define	PCS_DATAPATH_MODE_PCS		0	   /* Internal PCS is used */
1816#define	PCS_DATAPATH_MODE_MII		0x00000002 /* GMII/RGMII is selected. */
1817
1818#define	PCS_PACKET_COUNT_TX_MASK	0x000007FF /* pkts xmitted by PCS */
1819#define	PCS_PACKET_COUNT_RX_MASK	0x07FF0000 /* pkts recvd by PCS */
1820#define	PCS_PACKET_COUNT_RX_SHIFT	16
1821
1822/*
1823 * ******************** XPCS registers *********************************
1824 */
1825
1826/* XPCS Base 10G Control1 Register */
1827#define	XPCS_CTRL1_RST			0x8000 /* Self clearing reset. */
1828#define	XPCS_CTRL1_LOOPBK		0x4000 /* xpcs Loopback */
1829#define	XPCS_CTRL1_SPEED_SEL_3		0x2000 /* 1 indicates 10G speed */
1830#define	XPCS_CTRL1_LOW_PWR		0x0800 /* low power mode. */
1831#define	XPCS_CTRL1_SPEED_SEL_1		0x0040 /* 1 indicates 10G speed */
1832#define	XPCS_CTRL1_SPEED_SEL_0_MASK	0x003c /* 0 indicates 10G speed. */
1833#define	XPCS_CTRL1_SPEED_SEL_0_SHIFT	2
1834
1835
1836
1837typedef union _xpcs_ctrl1_t {
1838	uint64_t value;
1839
1840	struct {
1841#if defined(_BIG_ENDIAN)
1842		uint32_t msw;	/* Most significant word */
1843		uint32_t lsw;	/* Least significant word */
1844#elif defined(_LITTLE_ENDIAN)
1845		uint32_t lsw;	/* Least significant word */
1846		uint32_t msw;	/* Most significant word */
1847#endif
1848	} val;
1849	struct {
1850#if defined(_BIG_ENDIAN)
1851		uint32_t	w1;
1852#endif
1853		struct {
1854#if defined(_BIT_FIELDS_HTOL)
1855		uint32_t res3		: 16;
1856		uint32_t reset		: 1;
1857		uint32_t csr_lb		: 1;
1858		uint32_t csr_speed_sel3	: 1;
1859		uint32_t res2		: 1;
1860		uint32_t csr_low_pwr	: 1;
1861		uint32_t res1		: 4;
1862		uint32_t csr_speed_sel1	: 1;
1863		uint32_t csr_speed_sel0	: 4;
1864		uint32_t res0		: 2;
1865#elif defined(_BIT_FIELDS_LTOH)
1866		uint32_t res0		: 2;
1867		uint32_t csr_speed_sel0	: 4;
1868		uint32_t csr_speed_sel1	: 1;
1869		uint32_t res1		: 4;
1870		uint32_t csr_low_pwr	: 1;
1871		uint32_t res2		: 1;
1872		uint32_t csr_speed_sel3	: 1;
1873		uint32_t csr_lb		: 1;
1874		uint32_t reset		: 1;
1875		uint32_t res3		: 16;
1876#endif
1877		} w0;
1878
1879#if defined(_LITTLE_ENDIAN)
1880		uint32_t	w1;
1881#endif
1882	} bits;
1883} xpcs_ctrl1_t;
1884
1885
1886/* XPCS Base 10G Status1 Register (Read Only) */
1887#define	XPCS_STATUS1_FAULT		0x0080
1888#define	XPCS_STATUS1_RX_LINK_STATUS_UP	0x0004 /* Link status interrupt */
1889#define	XPCS_STATUS1_LOW_POWER_ABILITY	0x0002 /* low power mode */
1890#define	XPCS_STATUS_RX_LINK_STATUS_UP	0x1000 /* Link status interrupt */
1891
1892
1893typedef	union _xpcs_stat1_t {
1894	uint64_t value;
1895
1896	struct {
1897#if defined(_BIG_ENDIAN)
1898		uint32_t msw;	/* Most significant word */
1899		uint32_t lsw;	/* Least significant word */
1900#elif defined(_LITTLE_ENDIAN)
1901		uint32_t lsw;	/* Least significant word */
1902		uint32_t msw;	/* Most significant word */
1903#endif
1904	} val;
1905	struct {
1906#if defined(_BIG_ENDIAN)
1907		uint32_t	w1;
1908#endif
1909		struct {
1910#if defined(_BIT_FIELDS_HTOL)
1911		uint32_t res4			: 16;
1912		uint32_t res3			: 8;
1913		uint32_t csr_fault		: 1;
1914		uint32_t res1			: 4;
1915		uint32_t csr_rx_link_stat	: 1;
1916		uint32_t csr_low_pwr_ability	: 1;
1917		uint32_t res0			: 1;
1918#elif defined(_BIT_FIELDS_LTOH)
1919		uint32_t res0			: 1;
1920		uint32_t csr_low_pwr_ability	: 1;
1921		uint32_t csr_rx_link_stat	: 1;
1922		uint32_t res1			: 4;
1923		uint32_t csr_fault		: 1;
1924		uint32_t res3			: 8;
1925		uint32_t res4			: 16;
1926#endif
1927		} w0;
1928
1929#if defined(_LITTLE_ENDIAN)
1930		uint32_t	w1;
1931#endif
1932	} bits;
1933} xpcs_stat1_t;
1934
1935
1936/* XPCS Base Speed Ability Register. Indicates 10G capability */
1937#define	XPCS_SPEED_ABILITY_10_GIG	0x0001
1938
1939
1940typedef	union _xpcs_speed_ab_t {
1941	uint64_t value;
1942
1943	struct {
1944#if defined(_BIG_ENDIAN)
1945		uint32_t msw;	/* Most significant word */
1946		uint32_t lsw;	/* Least significant word */
1947#elif defined(_LITTLE_ENDIAN)
1948		uint32_t lsw;	/* Least significant word */
1949		uint32_t msw;	/* Most significant word */
1950#endif
1951	} val;
1952	struct {
1953#if defined(_BIG_ENDIAN)
1954		uint32_t	w1;
1955#endif
1956		struct {
1957#if defined(_BIT_FIELDS_HTOL)
1958		uint32_t res1		: 16;
1959		uint32_t res0		: 15;
1960		uint32_t csr_10gig	: 1;
1961#elif defined(_BIT_FIELDS_LTOH)
1962		uint32_t csr_10gig	: 1;
1963		uint32_t res0		: 15;
1964		uint32_t res1		: 16;
1965#endif
1966		} w0;
1967
1968#if defined(_LITTLE_ENDIAN)
1969		uint32_t	w1;
1970#endif
1971	} bits;
1972} xpcs_speed_ab_t;
1973
1974
1975/* XPCS Base 10G Devices in Package Register */
1976#define	XPCS_DEV_IN_PKG_CSR_VENDOR2	0x80000000
1977#define	XPCS_DEV_IN_PKG_CSR_VENDOR1	0x40000000
1978#define	XPCS_DEV_IN_PKG_DTE_XS		0x00000020
1979#define	XPCS_DEV_IN_PKG_PHY_XS		0x00000010
1980#define	XPCS_DEV_IN_PKG_PCS		0x00000008
1981#define	XPCS_DEV_IN_PKG_WIS		0x00000004
1982#define	XPCS_DEV_IN_PKG_PMD_PMA		0x00000002
1983#define	XPCS_DEV_IN_PKG_CLS_22_REG	0x00000000
1984
1985
1986
1987typedef	union _xpcs_dev_in_pkg_t {
1988	uint64_t value;
1989
1990	struct {
1991#if defined(_BIG_ENDIAN)
1992		uint32_t msw;	/* Most significant word */
1993		uint32_t lsw;	/* Least significant word */
1994#elif defined(_LITTLE_ENDIAN)
1995		uint32_t lsw;	/* Least significant word */
1996		uint32_t msw;	/* Most significant word */
1997#endif
1998	} val;
1999	struct {
2000#if defined(_BIG_ENDIAN)
2001		uint32_t	w1;
2002#endif
2003		struct {
2004#if defined(_BIT_FIELDS_HTOL)
2005		uint32_t csr_vendor2	: 1;
2006		uint32_t csr_vendor1	: 1;
2007		uint32_t res1		: 14;
2008		uint32_t res0		: 10;
2009		uint32_t dte_xs		: 1;
2010		uint32_t phy_xs		: 1;
2011		uint32_t pcs		: 1;
2012		uint32_t wis		: 1;
2013		uint32_t pmd_pma	: 1;
2014		uint32_t clause_22_reg	: 1;
2015#elif defined(_BIT_FIELDS_LTOH)
2016		uint32_t clause_22_reg	: 1;
2017		uint32_t pmd_pma	: 1;
2018		uint32_t wis		: 1;
2019		uint32_t pcs		: 1;
2020		uint32_t phy_xs		: 1;
2021		uint32_t dte_xs		: 1;
2022		uint32_t res0		: 10;
2023		uint32_t res1		: 14;
2024		uint32_t csr_vendor1	: 1;
2025		uint32_t csr_vendor2	: 1;
2026#endif
2027		} w0;
2028
2029#if defined(_LITTLE_ENDIAN)
2030		uint32_t	w1;
2031#endif
2032	} bits;
2033} xpcs_dev_in_pkg_t;
2034
2035
2036/* XPCS Base 10G Control2 Register */
2037#define	XPCS_PSC_SEL_MASK		0x0003
2038#define	PSC_SEL_10G_BASE_X_PCS		0x0001
2039
2040
2041typedef	union _xpcs_ctrl2_t {
2042	uint64_t value;
2043
2044	struct {
2045#if defined(_BIG_ENDIAN)
2046		uint32_t msw;	/* Most significant word */
2047		uint32_t lsw;	/* Least significant word */
2048#elif defined(_LITTLE_ENDIAN)
2049		uint32_t lsw;	/* Least significant word */
2050		uint32_t msw;	/* Most significant word */
2051#endif
2052	} val;
2053	struct {
2054#if defined(_BIG_ENDIAN)
2055		uint32_t	w1;
2056#endif
2057		struct {
2058#if defined(_BIT_FIELDS_HTOL)
2059		uint32_t res1		: 16;
2060		uint32_t res0		: 14;
2061		uint32_t csr_psc_sel	: 2;
2062#elif defined(_BIT_FIELDS_LTOH)
2063		uint32_t csr_psc_sel	: 2;
2064		uint32_t res0		: 14;
2065		uint32_t res1		: 16;
2066#endif
2067		} w0;
2068
2069#if defined(_LITTLE_ENDIAN)
2070		uint32_t	w1;
2071#endif
2072	} bits;
2073} xpcs_ctrl2_t;
2074
2075
2076/* XPCS Base10G Status2 Register */
2077#define	XPCS_STATUS2_DEV_PRESENT_MASK	0xc000	/* ?????? */
2078#define	XPCS_STATUS2_TX_FAULT		0x0800	/* Fault on tx path */
2079#define	XPCS_STATUS2_RX_FAULT		0x0400	/* Fault on rx path */
2080#define	XPCS_STATUS2_TEN_GBASE_W	0x0004	/* 10G-Base-W */
2081#define	XPCS_STATUS2_TEN_GBASE_X	0x0002	/* 10G-Base-X */
2082#define	XPCS_STATUS2_TEN_GBASE_R	0x0001	/* 10G-Base-R */
2083
2084typedef	union _xpcs_stat2_t {
2085	uint64_t value;
2086
2087	struct {
2088#if defined(_BIG_ENDIAN)
2089		uint32_t msw;	/* Most significant word */
2090		uint32_t lsw;	/* Least significant word */
2091#elif defined(_LITTLE_ENDIAN)
2092		uint32_t lsw;	/* Least significant word */
2093		uint32_t msw;	/* Most significant word */
2094#endif
2095	} val;
2096	struct {
2097#if defined(_BIG_ENDIAN)
2098		uint32_t	w1;
2099#endif
2100		struct {
2101#if defined(_BIT_FIELDS_HTOL)
2102		uint32_t res2		: 16;
2103		uint32_t csr_dev_pres	: 2;
2104		uint32_t res1		: 2;
2105		uint32_t csr_tx_fault	: 1;
2106		uint32_t csr_rx_fault	: 1;
2107		uint32_t res0		: 7;
2108		uint32_t ten_gbase_w	: 1;
2109		uint32_t ten_gbase_x	: 1;
2110		uint32_t ten_gbase_r	: 1;
2111#elif defined(_BIT_FIELDS_LTOH)
2112		uint32_t ten_gbase_r	: 1;
2113		uint32_t ten_gbase_x	: 1;
2114		uint32_t ten_gbase_w	: 1;
2115		uint32_t res0		: 7;
2116		uint32_t csr_rx_fault	: 1;
2117		uint32_t csr_tx_fault	: 1;
2118		uint32_t res1		: 2;
2119		uint32_t csr_dev_pres	: 2;
2120		uint32_t res2		: 16;
2121#endif
2122		} w0;
2123
2124#if defined(_LITTLE_ENDIAN)
2125		uint32_t	w1;
2126#endif
2127	} bits;
2128} xpcs_stat2_t;
2129
2130
2131
2132/* XPCS Base10G Status Register */
2133#define	XPCS_STATUS_LANE_ALIGN		0x1000 /* 10GBaseX PCS rx lanes align */
2134#define	XPCS_STATUS_PATTERN_TEST_ABLE	0x0800 /* able to generate patterns. */
2135#define	XPCS_STATUS_LANE3_SYNC		0x0008 /* Lane 3 is synchronized */
2136#define	XPCS_STATUS_LANE2_SYNC		0x0004 /* Lane 2 is synchronized */
2137#define	XPCS_STATUS_LANE1_SYNC		0x0002 /* Lane 1 is synchronized */
2138#define	XPCS_STATUS_LANE0_SYNC		0x0001 /* Lane 0 is synchronized */
2139
2140typedef	union _xpcs_stat_t {
2141	uint64_t value;
2142
2143	struct {
2144#if defined(_BIG_ENDIAN)
2145		uint32_t msw;	/* Most significant word */
2146		uint32_t lsw;	/* Least significant word */
2147#elif defined(_LITTLE_ENDIAN)
2148		uint32_t lsw;	/* Least significant word */
2149		uint32_t msw;	/* Most significant word */
2150#endif
2151	} val;
2152	struct {
2153#if defined(_BIG_ENDIAN)
2154		uint32_t	w1;
2155#endif
2156		struct {
2157#if defined(_BIT_FIELDS_HTOL)
2158		uint32_t res2			: 16;
2159		uint32_t res1			: 3;
2160		uint32_t csr_lane_align		: 1;
2161		uint32_t csr_pattern_test_able	: 1;
2162		uint32_t res0			: 7;
2163		uint32_t csr_lane3_sync		: 1;
2164		uint32_t csr_lane2_sync		: 1;
2165		uint32_t csr_lane1_sync		: 1;
2166		uint32_t csr_lane0_sync		: 1;
2167#elif defined(_BIT_FIELDS_LTOH)
2168		uint32_t csr_lane0_sync		: 1;
2169		uint32_t csr_lane1_sync		: 1;
2170		uint32_t csr_lane2_sync		: 1;
2171		uint32_t csr_lane3_sync		: 1;
2172		uint32_t res0			: 7;
2173		uint32_t csr_pat_test_able	: 1;
2174		uint32_t csr_lane_align		: 1;
2175		uint32_t res1			: 3;
2176		uint32_t res2			: 16;
2177#endif
2178		} w0;
2179
2180#if defined(_LITTLE_ENDIAN)
2181		uint32_t	w1;
2182#endif
2183	} bits;
2184} xpcs_stat_t;
2185
2186/* XPCS Base10G Test Control Register */
2187#define	XPCS_TEST_CTRL_TX_TEST_ENABLE		0x0004
2188#define	XPCS_TEST_CTRL_TEST_PATTERN_SEL_MASK	0x0003
2189#define	TEST_PATTERN_HIGH_FREQ			0
2190#define	TEST_PATTERN_LOW_FREQ			1
2191#define	TEST_PATTERN_MIXED_FREQ			2
2192
2193typedef	union _xpcs_test_ctl_t {
2194	uint64_t value;
2195
2196	struct {
2197#if defined(_BIG_ENDIAN)
2198		uint32_t msw;	/* Most significant word */
2199		uint32_t lsw;	/* Least significant word */
2200#elif defined(_LITTLE_ENDIAN)
2201		uint32_t lsw;	/* Least significant word */
2202		uint32_t msw;	/* Most significant word */
2203#endif
2204	} val;
2205	struct {
2206#if defined(_BIG_ENDIAN)
2207		uint32_t	w1;
2208#endif
2209		struct {
2210#if defined(_BIT_FIELDS_HTOL)
2211		uint32_t res1			: 16;
2212		uint32_t res0			: 13;
2213		uint32_t csr_tx_test_en		: 1;
2214		uint32_t csr_test_pat_sel	: 2;
2215#elif defined(_BIT_FIELDS_LTOH)
2216		uint32_t csr_test_pat_sel	: 2;
2217		uint32_t csr_tx_test_en		: 1;
2218		uint32_t res0			: 13;
2219		uint32_t res1			: 16;
2220#endif
2221		} w0;
2222
2223#if defined(_LITTLE_ENDIAN)
2224		uint32_t	w1;
2225#endif
2226	} bits;
2227} xpcs_test_ctl_t;
2228
2229/* XPCS Base10G Diagnostic Register */
2230#define	XPCS_DIAG_EB_ALIGN_ERR3		0x40
2231#define	XPCS_DIAG_EB_ALIGN_ERR2		0x20
2232#define	XPCS_DIAG_EB_ALIGN_ERR1		0x10
2233#define	XPCS_DIAG_EB_DESKEW_OK		0x08
2234#define	XPCS_DIAG_EB_ALIGN_DET3		0x04
2235#define	XPCS_DIAG_EB_ALIGN_DET2		0x02
2236#define	XPCS_DIAG_EB_ALIGN_DET1		0x01
2237#define	XPCS_DIAG_EB_DESKEW_LOSS	0
2238
2239#define	XPCS_DIAG_SYNC_3_INVALID	0x8
2240#define	XPCS_DIAG_SYNC_2_INVALID	0x4
2241#define	XPCS_DIAG_SYNC_1_INVALID	0x2
2242#define	XPCS_DIAG_SYNC_IN_SYNC		0x1
2243#define	XPCS_DIAG_SYNC_LOSS_SYNC	0
2244
2245#define	XPCS_RX_SM_RECEIVE_STATE	1
2246#define	XPCS_RX_SM_FAULT_STATE		0
2247
2248typedef	union _xpcs_diag_t {
2249	uint64_t value;
2250
2251	struct {
2252#if defined(_BIG_ENDIAN)
2253		uint32_t msw;	/* Most significant word */
2254		uint32_t lsw;	/* Least significant word */
2255#elif defined(_LITTLE_ENDIAN)
2256		uint32_t lsw;	/* Least significant word */
2257		uint32_t msw;	/* Most significant word */
2258#endif
2259	} val;
2260	struct {
2261#if defined(_BIG_ENDIAN)
2262		uint32_t	w1;
2263#endif
2264		struct {
2265#if defined(_BIT_FIELDS_HTOL)
2266		uint32_t res1			: 7;
2267		uint32_t sync_sm_lane3		: 4;
2268		uint32_t sync_sm_lane2		: 4;
2269		uint32_t sync_sm_lane1		: 4;
2270		uint32_t sync_sm_lane0		: 4;
2271		uint32_t elastic_buffer_sm	: 8;
2272		uint32_t receive_sm		: 1;
2273#elif defined(_BIT_FIELDS_LTOH)
2274		uint32_t receive_sm		: 1;
2275		uint32_t elastic_buffer_sm	: 8;
2276		uint32_t sync_sm_lane0		: 4;
2277		uint32_t sync_sm_lane1		: 4;
2278		uint32_t sync_sm_lane2		: 4;
2279		uint32_t sync_sm_lane3		: 4;
2280		uint32_t res1			: 7;
2281#endif
2282		} w0;
2283
2284#if defined(_LITTLE_ENDIAN)
2285		uint32_t	w1;
2286#endif
2287	} bits;
2288} xpcs_diag_t;
2289
2290/* XPCS Base10G Tx State Machine Register */
2291#define	XPCS_TX_SM_SEND_UNDERRUN	0x9
2292#define	XPCS_TX_SM_SEND_RANDOM_Q	0x8
2293#define	XPCS_TX_SM_SEND_RANDOM_K	0x7
2294#define	XPCS_TX_SM_SEND_RANDOM_A	0x6
2295#define	XPCS_TX_SM_SEND_RANDOM_R	0x5
2296#define	XPCS_TX_SM_SEND_Q		0x4
2297#define	XPCS_TX_SM_SEND_K		0x3
2298#define	XPCS_TX_SM_SEND_A		0x2
2299#define	XPCS_TX_SM_SEND_SDP		0x1
2300#define	XPCS_TX_SM_SEND_DATA		0
2301
2302/* XPCS Base10G Configuration Register */
2303#define	XPCS_CFG_VENDOR_DBG_SEL_MASK	0x78
2304#define	XPCS_CFG_VENDOR_DBG_SEL_SHIFT	3
2305#define	XPCS_CFG_BYPASS_SIG_DETECT	0x0004
2306#define	XPCS_CFG_ENABLE_TX_BUFFERS	0x0002
2307#define	XPCS_CFG_XPCS_ENABLE		0x0001
2308
2309typedef	union _xpcs_config_t {
2310	uint64_t value;
2311
2312	struct {
2313#if defined(_BIG_ENDIAN)
2314		uint32_t msw;	/* Most significant word */
2315		uint32_t lsw;	/* Least significant word */
2316#elif defined(_LITTLE_ENDIAN)
2317		uint32_t lsw;	/* Least significant word */
2318		uint32_t msw;	/* Most significant word */
2319#endif
2320	} val;
2321	struct {
2322#if defined(_BIG_ENDIAN)
2323		uint32_t	w1;
2324#endif
2325		struct {
2326#if defined(_BIT_FIELDS_HTOL)
2327		uint32_t res1			: 16;
2328		uint32_t res0			: 9;
2329		uint32_t csr_vendor_dbg_sel	: 4;
2330		uint32_t csr_bypass_sig_detect	: 1;
2331		uint32_t csr_en_tx_buf		: 1;
2332		uint32_t csr_xpcs_en		: 1;
2333#elif defined(_BIT_FIELDS_LTOH)
2334		uint32_t csr_xpcs_en		: 1;
2335		uint32_t csr_en_tx_buf		: 1;
2336		uint32_t csr_bypass_sig_detect	: 1;
2337		uint32_t csr_vendor_dbg_sel	: 4;
2338		uint32_t res0			: 9;
2339		uint32_t res1			: 16;
2340#endif
2341		} w0;
2342
2343#if defined(_LITTLE_ENDIAN)
2344		uint32_t	w1;
2345#endif
2346	} bits;
2347} xpcs_config_t;
2348
2349
2350
2351/* XPCS Base10G Mask1 Register */
2352#define	XPCS_MASK1_FAULT_MASK		0x0080	/* mask fault interrupt. */
2353#define	XPCS_MASK1_RX_LINK_STATUS_MASK	0x0040	/* mask linkstat interrupt */
2354
2355/* XPCS Base10G Packet Counter */
2356#define	XPCS_PKT_CNTR_TX_PKT_CNT_MASK	0xffff0000
2357#define	XPCS_PKT_CNTR_TX_PKT_CNT_SHIFT	16
2358#define	XPCS_PKT_CNTR_RX_PKT_CNT_MASK	0x0000ffff
2359#define	XPCS_PKT_CNTR_RX_PKT_CNT_SHIFT	0
2360
2361/* XPCS Base10G TX State Machine status register */
2362#define	XPCS_TX_STATE_MC_TX_STATE_MASK	0x0f
2363#define	XPCS_DESKEW_ERR_CNTR_MASK	0xff
2364
2365/* XPCS Base10G Lane symbol error counters */
2366#define	XPCS_SYM_ERR_CNT_L1_MASK  0xffff0000
2367#define	XPCS_SYM_ERR_CNT_L0_MASK  0x0000ffff
2368#define	XPCS_SYM_ERR_CNT_L3_MASK  0xffff0000
2369#define	XPCS_SYM_ERR_CNT_L2_MASK  0x0000ffff
2370
2371#define	XPCS_SYM_ERR_CNT_MULTIPLIER	16
2372
2373/* ESR Reset Register */
2374#define	ESR_RESET_1			2
2375#define	ESR_RESET_0			1
2376
2377/* ESR Configuration Register */
2378#define	ESR_BLUNT_END_LOOPBACK		2
2379#define	ESR_FORCE_SERDES_SERDES_RDY	1
2380
2381/* ESR Neptune Serdes PLL Configuration */
2382#define	ESR_PLL_CFG_FBDIV_0		0x1
2383#define	ESR_PLL_CFG_FBDIV_1		0x2
2384#define	ESR_PLL_CFG_FBDIV_2		0x4
2385#define	ESR_PLL_CFG_HALF_RATE_0		0x8
2386#define	ESR_PLL_CFG_HALF_RATE_1		0x10
2387#define	ESR_PLL_CFG_HALF_RATE_2		0x20
2388#define	ESR_PLL_CFG_HALF_RATE_3		0x40
2389#define	ESR_PLL_CFG_1G_SERDES		(ESR_PLL_CFG_FBDIV_0 |		\
2390					ESR_PLL_CFG_HALF_RATE_0 |	\
2391					ESR_PLL_CFG_HALF_RATE_1 |	\
2392					ESR_PLL_CFG_HALF_RATE_2 |	\
2393					ESR_PLL_CFG_HALF_RATE_3)
2394
2395#define	ESR_PLL_CFG_10G_SERDES		ESR_PLL_CFG_FBDIV_2
2396
2397/* ESR Neptune Serdes Control Register */
2398#define	ESR_CTL_EN_SYNCDET_0		0x00000001
2399#define	ESR_CTL_EN_SYNCDET_1		0x00000002
2400#define	ESR_CTL_EN_SYNCDET_2		0x00000004
2401#define	ESR_CTL_EN_SYNCDET_3		0x00000008
2402#define	ESR_CTL_OUT_EMPH_0_MASK		0x00000070
2403#define	ESR_CTL_OUT_EMPH_0_SHIFT	4
2404#define	ESR_CTL_OUT_EMPH_1_MASK		0x00000380
2405#define	ESR_CTL_OUT_EMPH_1_SHIFT	7
2406#define	ESR_CTL_OUT_EMPH_2_MASK		0x00001c00
2407#define	ESR_CTL_OUT_EMPH_2_SHIFT	10
2408#define	ESR_CTL_OUT_EMPH_3_MASK		0x0000e000
2409#define	ESR_CTL_OUT_EMPH_3_SHIFT	13
2410#define	ESR_CTL_LOSADJ_0_MASK		0x00070000
2411#define	ESR_CTL_LOSADJ_0_SHIFT		16
2412#define	ESR_CTL_LOSADJ_1_MASK		0x00380000
2413#define	ESR_CTL_LOSADJ_1_SHIFT		19
2414#define	ESR_CTL_LOSADJ_2_MASK		0x01c00000
2415#define	ESR_CTL_LOSADJ_2_SHIFT		22
2416#define	ESR_CTL_LOSADJ_3_MASK		0x0e000000
2417#define	ESR_CTL_LOSADJ_3_SHIFT		25
2418#define	ESR_CTL_RXITERM_0		0x10000000
2419#define	ESR_CTL_RXITERM_1		0x20000000
2420#define	ESR_CTL_RXITERM_2		0x40000000
2421#define	ESR_CTL_RXITERM_3		0x80000000
2422#define	ESR_CTL_1G_SERDES		(ESR_CTL_EN_SYNCDET_0 | \
2423					ESR_CTL_EN_SYNCDET_1 |	\
2424					ESR_CTL_EN_SYNCDET_2 |	\
2425					ESR_CTL_EN_SYNCDET_3 |  \
2426					(0x1 << ESR_CTL_OUT_EMPH_0_SHIFT) | \
2427					(0x1 << ESR_CTL_OUT_EMPH_1_SHIFT) | \
2428					(0x1 << ESR_CTL_OUT_EMPH_2_SHIFT) | \
2429					(0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \
2430					(0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \
2431					(0x1 << ESR_CTL_LOSADJ_0_SHIFT) | \
2432					(0x1 << ESR_CTL_LOSADJ_1_SHIFT) | \
2433					(0x1 << ESR_CTL_LOSADJ_2_SHIFT) | \
2434					(0x1 << ESR_CTL_LOSADJ_3_SHIFT))
2435
2436/* ESR Neptune Serdes Test Configuration Register */
2437#define	ESR_TSTCFG_LBTEST_MD_0_MASK	0x00000003
2438#define	ESR_TSTCFG_LBTEST_MD_0_SHIFT	0
2439#define	ESR_TSTCFG_LBTEST_MD_1_MASK	0x0000000c
2440#define	ESR_TSTCFG_LBTEST_MD_1_SHIFT	2
2441#define	ESR_TSTCFG_LBTEST_MD_2_MASK	0x00000030
2442#define	ESR_TSTCFG_LBTEST_MD_2_SHIFT	4
2443#define	ESR_TSTCFG_LBTEST_MD_3_MASK	0x000000c0
2444#define	ESR_TSTCFG_LBTEST_MD_3_SHIFT	6
2445#define	ESR_TSTCFG_LBTEST_PAD		(ESR_PAD_LOOPBACK_CH3 | \
2446					ESR_PAD_LOOPBACK_CH2 | \
2447					ESR_PAD_LOOPBACK_CH1 | \
2448					ESR_PAD_LOOPBACK_CH0)
2449
2450/* ESR Neptune Ethernet RGMII Configuration Register */
2451#define	ESR_RGMII_PT0_IN_USE		0x00000001
2452#define	ESR_RGMII_PT1_IN_USE		0x00000002
2453#define	ESR_RGMII_PT2_IN_USE		0x00000004
2454#define	ESR_RGMII_PT3_IN_USE		0x00000008
2455#define	ESR_RGMII_REG_RW_TEST		0x00000010
2456
2457/* ESR Internal Signals Observation Register */
2458#define	ESR_SIG_MASK			0xFFFFFFFF
2459#define	ESR_SIG_P0_BITS_MASK		0x33E0000F
2460#define	ESR_SIG_P1_BITS_MASK		0x0C1F00F0
2461#define	ESR_SIG_SERDES_RDY0_P0		0x20000000
2462#define	ESR_SIG_DETECT0_P0		0x10000000
2463#define	ESR_SIG_SERDES_RDY0_P1		0x08000000
2464#define	ESR_SIG_DETECT0_P1		0x04000000
2465#define	ESR_SIG_XSERDES_RDY_P0		0x02000000
2466#define	ESR_SIG_XDETECT_P0_CH3		0x01000000
2467#define	ESR_SIG_XDETECT_P0_CH2		0x00800000
2468#define	ESR_SIG_XDETECT_P0_CH1		0x00400000
2469#define	ESR_SIG_XDETECT_P0_CH0		0x00200000
2470#define	ESR_SIG_XSERDES_RDY_P1		0x00100000
2471#define	ESR_SIG_XDETECT_P1_CH3		0x00080000
2472#define	ESR_SIG_XDETECT_P1_CH2		0x00040000
2473#define	ESR_SIG_XDETECT_P1_CH1		0x00020000
2474#define	ESR_SIG_XDETECT_P1_CH0		0x00010000
2475#define	ESR_SIG_LOS_P1_CH3		0x00000080
2476#define	ESR_SIG_LOS_P1_CH2		0x00000040
2477#define	ESR_SIG_LOS_P1_CH1		0x00000020
2478#define	ESR_SIG_LOS_P1_CH0		0x00000010
2479#define	ESR_SIG_LOS_P0_CH3		0x00000008
2480#define	ESR_SIG_LOS_P0_CH2		0x00000004
2481#define	ESR_SIG_LOS_P0_CH1		0x00000002
2482#define	ESR_SIG_LOS_P0_CH0		0x00000001
2483#define	ESR_SIG_P0_BITS_MASK_1G		(ESR_SIG_SERDES_RDY0_P0 | \
2484					ESR_SIG_DETECT0_P0)
2485#define	ESR_SIG_P1_BITS_MASK_1G		(ESR_SIG_SERDES_RDY0_P1 | \
2486					ESR_SIG_DETECT0_P1)
2487
2488/* ESR Debug Selection Register */
2489#define	ESR_DEBUG_SEL_MASK		0x00000003f
2490
2491/* ESR Test Configuration Register */
2492#define	ESR_NO_LOOPBACK_CH3		(0x0 << 6)
2493#define	ESR_EWRAP_CH3			(0x1 << 6)
2494#define	ESR_PAD_LOOPBACK_CH3		(0x2 << 6)
2495#define	ESR_REVLOOPBACK_CH3		(0x3 << 6)
2496#define	ESR_NO_LOOPBACK_CH2		(0x0 << 4)
2497#define	ESR_EWRAP_CH2			(0x1 << 4)
2498#define	ESR_PAD_LOOPBACK_CH2		(0x2 << 4)
2499#define	ESR_REVLOOPBACK_CH2		(0x3 << 4)
2500#define	ESR_NO_LOOPBACK_CH1		(0x0 << 2)
2501#define	ESR_EWRAP_CH1			(0x1 << 2)
2502#define	ESR_PAD_LOOPBACK_CH1		(0x2 << 2)
2503#define	ESR_REVLOOPBACK_CH1		(0x3 << 2)
2504#define	ESR_NO_LOOPBACK_CH0		0x0
2505#define	ESR_EWRAP_CH0			0x1
2506#define	ESR_PAD_LOOPBACK_CH0		0x2
2507#define	ESR_REVLOOPBACK_CH0		0x3
2508
2509/* convert values */
2510#define	NXGE_BASE(x, y)	\
2511	(((y) << (x ## _SHIFT)) & (x ## _MASK))
2512
2513#define	NXGE_VAL_GET(fieldname, regval)		\
2514	(((regval) & ((fieldname) ## _MASK)) >> ((fieldname) ## _SHIFT))
2515
2516#define	NXGE_VAL_SET(fieldname, regval, val)		\
2517{							\
2518	(regval) &= ~((fieldname) ## _MASK);		\
2519	(regval) |= ((val) << (fieldname ## _SHIFT)); 	\
2520}
2521
2522
2523#ifdef	__cplusplus
2524}
2525#endif
2526
2527#endif	/* _SYS_MAC_NXGE_MAC_HW_H */
2528