1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#ifndef	_SYS_NXGE_NXGE_MAC_H
27#define	_SYS_NXGE_NXGE_MAC_H
28
29#pragma ident	"%Z%%M%	%I%	%E% SMI"
30
31#ifdef	__cplusplus
32extern "C" {
33#endif
34
35#include <nxge_mac_hw.h>
36#include <npi_mac.h>
37
38#define	NXGE_MTU_DEFAULT_MAX	1522	/* 0x5f2 */
39#define	NXGE_DEFAULT_MTU	1500	/* 0x5dc */
40#define	NXGE_MIN_MAC_FRAMESIZE	64
41#define	NXGE_MAX_MAC_FRAMESIZE	NXGE_MTU_DEFAULT_MAX
42/*
43 * Maximum MTU: maximum frame size supported by the
44 * hardware (9216) - (22).
45 * (22 = ether header size (including VLAN) - CRC size (4)).
46 */
47#define	NXGE_EHEADER_VLAN_CRC	(sizeof (struct ether_header) + ETHERFCSL + 4)
48#define	NXGE_MAXIMUM_MTU	(TX_JUMBO_MTU - NXGE_EHEADER_VLAN_CRC)
49
50#define	NXGE_XMAC_TX_INTRS	(ICFG_XMAC_TX_ALL & \
51					~(ICFG_XMAC_TX_FRAME_XMIT |\
52					ICFG_XMAC_TX_BYTE_CNT_EXP |\
53					ICFG_XMAC_TX_FRAME_CNT_EXP))
54#define	NXGE_XMAC_RX_INTRS	(ICFG_XMAC_RX_ALL & \
55					~(ICFG_XMAC_RX_FRAME_RCVD |\
56					ICFG_XMAC_RX_OCT_CNT_EXP |\
57					ICFG_XMAC_RX_HST_CNT1_EXP |\
58					ICFG_XMAC_RX_HST_CNT2_EXP |\
59					ICFG_XMAC_RX_HST_CNT3_EXP |\
60					ICFG_XMAC_RX_HST_CNT4_EXP |\
61					ICFG_XMAC_RX_HST_CNT5_EXP |\
62					ICFG_XMAC_RX_HST_CNT6_EXP |\
63					ICFG_XMAC_RX_BCAST_CNT_EXP |\
64					ICFG_XMAC_RX_MCAST_CNT_EXP |\
65					ICFG_XMAC_RX_HST_CNT7_EXP))
66#define	NXGE_BMAC_TX_INTRS	(ICFG_BMAC_TX_ALL & \
67					~(ICFG_BMAC_TX_FRAME_SENT |\
68					ICFG_BMAC_TX_BYTE_CNT_EXP |\
69					ICFG_BMAC_TX_FRAME_CNT_EXP))
70#define	NXGE_BMAC_RX_INTRS	(ICFG_BMAC_RX_ALL & \
71					~(ICFG_BMAC_RX_FRAME_RCVD |\
72					ICFG_BMAC_RX_FRAME_CNT_EXP |\
73					ICFG_BMAC_RX_BYTE_CNT_EXP))
74
75typedef enum  {
76	LINK_NO_CHANGE,
77	LINK_IS_UP,
78	LINK_IS_DOWN
79} nxge_link_state_t;
80
81/* Common MAC statistics */
82
83typedef	struct _nxge_mac_stats {
84	/*
85	 * MTU size
86	 */
87	uint32_t	mac_mtu;
88	uint16_t	rev_id;
89
90	/*
91	 * Transciever state informations.
92	 */
93	uint32_t	xcvr_inits;
94	xcvr_inuse_t	xcvr_inuse;
95	uint32_t	xcvr_portn;
96	uint32_t	xcvr_id;
97	uint32_t	serdes_inits;
98	uint32_t	serdes_portn;
99	uint32_t	cap_autoneg;
100	uint32_t	cap_10gfdx;
101	uint32_t	cap_10ghdx;
102	uint32_t	cap_1000fdx;
103	uint32_t	cap_1000hdx;
104	uint32_t	cap_100T4;
105	uint32_t	cap_100fdx;
106	uint32_t	cap_100hdx;
107	uint32_t	cap_10fdx;
108	uint32_t	cap_10hdx;
109	uint32_t	cap_asmpause;
110	uint32_t	cap_pause;
111
112	/*
113	 * Advertised capabilities.
114	 */
115	uint32_t	adv_cap_autoneg;
116	uint32_t	adv_cap_10gfdx;
117	uint32_t	adv_cap_10ghdx;
118	uint32_t	adv_cap_1000fdx;
119	uint32_t	adv_cap_1000hdx;
120	uint32_t	adv_cap_100T4;
121	uint32_t	adv_cap_100fdx;
122	uint32_t	adv_cap_100hdx;
123	uint32_t	adv_cap_10fdx;
124	uint32_t	adv_cap_10hdx;
125	uint32_t	adv_cap_asmpause;
126	uint32_t	adv_cap_pause;
127
128	/*
129	 * Link partner capabilities.
130	 */
131	uint32_t	lp_cap_autoneg;
132	uint32_t	lp_cap_10gfdx;
133	uint32_t	lp_cap_10ghdx;
134	uint32_t	lp_cap_1000fdx;
135	uint32_t	lp_cap_1000hdx;
136	uint32_t	lp_cap_100T4;
137	uint32_t	lp_cap_100fdx;
138	uint32_t	lp_cap_100hdx;
139	uint32_t	lp_cap_10fdx;
140	uint32_t	lp_cap_10hdx;
141	uint32_t	lp_cap_asmpause;
142	uint32_t	lp_cap_pause;
143
144	/*
145	 * Physical link statistics.
146	 */
147	uint32_t	link_T4;
148	uint32_t	link_speed;
149	uint32_t	link_duplex;
150	uint32_t	link_asmpause;
151	uint32_t	link_pause;
152	uint32_t	link_up;
153
154	/* Promiscous mode */
155	boolean_t	promisc;
156} nxge_mac_stats_t;
157
158/* XMAC Statistics */
159
160typedef	struct _nxge_xmac_stats {
161	uint32_t tx_frame_cnt;
162	uint32_t tx_underflow_err;
163	uint32_t tx_maxpktsize_err;
164	uint32_t tx_overflow_err;
165	uint32_t tx_fifo_xfr_err;
166	uint64_t tx_byte_cnt;
167	uint32_t rx_frame_cnt;
168	uint32_t rx_underflow_err;
169	uint32_t rx_overflow_err;
170	uint32_t rx_crc_err_cnt;
171	uint32_t rx_len_err_cnt;
172	uint32_t rx_viol_err_cnt;
173	uint64_t rx_byte_cnt;
174	uint64_t rx_hist1_cnt;
175	uint64_t rx_hist2_cnt;
176	uint64_t rx_hist3_cnt;
177	uint64_t rx_hist4_cnt;
178	uint64_t rx_hist5_cnt;
179	uint64_t rx_hist6_cnt;
180	uint64_t rx_hist7_cnt;
181	uint64_t rx_broadcast_cnt;
182	uint64_t rx_mult_cnt;
183	uint32_t rx_frag_cnt;
184	uint32_t rx_frame_align_err_cnt;
185	uint32_t rx_linkfault_err_cnt;
186	uint32_t rx_remotefault_err;
187	uint32_t rx_localfault_err;
188	uint32_t rx_pause_cnt;
189	uint32_t tx_pause_state;
190	uint32_t tx_nopause_state;
191	uint32_t xpcs_deskew_err_cnt;
192	uint32_t xpcs_ln0_symbol_err_cnt;
193	uint32_t xpcs_ln1_symbol_err_cnt;
194	uint32_t xpcs_ln2_symbol_err_cnt;
195	uint32_t xpcs_ln3_symbol_err_cnt;
196} nxge_xmac_stats_t, *p_nxge_xmac_stats_t;
197
198/* BMAC Statistics */
199
200typedef	struct _nxge_bmac_stats {
201	uint64_t tx_frame_cnt;
202	uint32_t tx_underrun_err;
203	uint32_t tx_max_pkt_err;
204	uint64_t tx_byte_cnt;
205	uint64_t rx_frame_cnt;
206	uint64_t rx_byte_cnt;
207	uint32_t rx_overflow_err;
208	uint32_t rx_align_err_cnt;
209	uint32_t rx_crc_err_cnt;
210	uint32_t rx_len_err_cnt;
211	uint32_t rx_viol_err_cnt;
212	uint32_t rx_pause_cnt;
213	uint32_t tx_pause_state;
214	uint32_t tx_nopause_state;
215} nxge_bmac_stats_t, *p_nxge_bmac_stats_t;
216
217typedef struct _hash_filter_t {
218	uint_t hash_ref_cnt;
219	uint16_t hash_filter_regs[NMCFILTER_REGS];
220	uint32_t hash_bit_ref_cnt[NMCFILTER_BITS];
221} hash_filter_t, *p_hash_filter_t;
222
223typedef	struct _nxge_mac {
224	uint8_t			portnum;
225	nxge_port_t		porttype;
226	nxge_port_mode_t	portmode;
227	nxge_linkchk_mode_t	linkchkmode;
228	boolean_t		is_jumbo;
229	uint32_t		tx_config;
230	uint32_t		rx_config;
231	uint32_t		xif_config;
232	uint32_t		tx_iconfig;
233	uint32_t		rx_iconfig;
234	uint32_t		ctl_iconfig;
235	uint16_t		minframesize;
236	uint16_t		maxframesize;
237	uint16_t		maxburstsize;
238	uint16_t		ctrltype;
239	uint16_t		pa_size;
240	uint8_t			ipg[3];
241	struct ether_addr	mac_addr;
242	struct ether_addr	alt_mac_addr[MAC_MAX_ALT_ADDR_ENTRY];
243	struct ether_addr	mac_addr_filter;
244	uint16_t		hashtab[MAC_MAX_HASH_ENTRY];
245	hostinfo_t		hostinfo[MAC_MAX_HOST_INFO_ENTRY];
246	nxge_mac_stats_t	*mac_stats;
247	nxge_xmac_stats_t	*xmac_stats;
248	nxge_bmac_stats_t	*bmac_stats;
249	uint32_t		default_mtu;
250} nxge_mac_t;
251
252#ifdef	__cplusplus
253}
254#endif
255
256#endif	/* _SYS_NXGE_NXGE_MAC_H */
257