1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#ifndef	_SYS_NXGE_NXGE_IMPL_H
27#define	_SYS_NXGE_NXGE_IMPL_H
28
29#ifdef	__cplusplus
30extern "C" {
31#endif
32
33/*
34 * NIU HV API version definitions.
35 *
36 * If additional major (HV API) is to be supported,
37 * please increment NIU_MAJOR_HI.
38 * If additional minor # is to be supported,
39 * please increment NIU_MINOR_HI.
40 */
41#define	NIU_MAJOR_HI		2
42#define	NIU_MINOR_HI		1
43#define	NIU_MAJOR_VER		1
44#define	NIU_MINOR_VER		1
45#define	NIU_MAJOR_VER_2		2
46
47#if defined(sun4v)
48
49/*
50 * NIU HV API v1.0 definitions
51 */
52#define	N2NIU_RX_LP_CONF		0x142
53#define	N2NIU_RX_LP_INFO		0x143
54#define	N2NIU_TX_LP_CONF		0x144
55#define	N2NIU_TX_LP_INFO		0x145
56
57#endif /* defined(sun4v) */
58
59#ifndef _ASM
60
61#include	<sys/types.h>
62#include	<sys/byteorder.h>
63#include	<sys/debug.h>
64#include	<sys/stropts.h>
65#include	<sys/stream.h>
66#include	<sys/strlog.h>
67#include	<sys/strsubr.h>
68#include	<sys/cmn_err.h>
69#include	<sys/vtrace.h>
70#include	<sys/kmem.h>
71#include	<sys/ddi.h>
72#include	<sys/sunddi.h>
73#include	<sys/strsun.h>
74#include	<sys/stat.h>
75#include	<sys/cpu.h>
76#include	<sys/kstat.h>
77#include	<inet/common.h>
78#include	<inet/ip.h>
79#include	<sys/dlpi.h>
80#include	<inet/nd.h>
81#include	<netinet/in.h>
82#include	<sys/ethernet.h>
83#include	<sys/vlan.h>
84#include	<sys/pci.h>
85#include	<sys/taskq.h>
86#include	<sys/atomic.h>
87
88#include 	<sys/nxge/nxge_defs.h>
89#include 	<sys/nxge/nxge_hw.h>
90#include 	<sys/nxge/nxge_mac.h>
91#include	<sys/nxge/nxge_mii.h>
92#include	<sys/nxge/nxge_fm.h>
93#include	<sys/netlb.h>
94
95#include	<sys/ddi_intr.h>
96#include 	<sys/mac_provider.h>
97#include	<sys/mac_ether.h>
98
99#if	defined(sun4v)
100#include	<sys/hypervisor_api.h>
101#include 	<sys/machsystm.h>
102#include 	<sys/hsvc.h>
103#endif
104
105#include 	<sys/dld.h>
106
107/*
108 * Handy macros (taken from bge driver)
109 */
110#define	RBR_SIZE			4
111#define	DMA_COMMON_CHANNEL(area)	((area.dma_channel))
112#define	DMA_COMMON_VPTR(area)		((area.kaddrp))
113#define	DMA_COMMON_VPTR_INDEX(area, index)	\
114					(((char *)(area.kaddrp)) + \
115					(index * RBR_SIZE))
116#define	DMA_COMMON_HANDLE(area)		((area.dma_handle))
117#define	DMA_COMMON_ACC_HANDLE(area)	((area.acc_handle))
118#define	DMA_COMMON_IOADDR(area)		((area.dma_cookie.dmac_laddress))
119#define	DMA_COMMON_IOADDR_INDEX(area, index)	\
120					((area.dma_cookie.dmac_laddress) + \
121						(index * RBR_SIZE))
122
123#define	DMA_NPI_HANDLE(area)		((area.npi_handle)
124
125#define	DMA_COMMON_SYNC(area, flag)	((void) ddi_dma_sync((area).dma_handle,\
126						(area).offset, (area).alength, \
127						(flag)))
128#define	DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag)	\
129					((void) ddi_dma_sync((area).dma_handle,\
130					(area.offset + bufoffset), len, \
131					(flag)))
132
133#define	DMA_COMMON_SYNC_RBR_DESC(area, index, flag)	\
134				((void) ddi_dma_sync((area).dma_handle,\
135				(index * RBR_SIZE), RBR_SIZE,	\
136				(flag)))
137
138#define	DMA_COMMON_SYNC_RBR_DESC_MULTI(area, index, count, flag)	\
139			((void) ddi_dma_sync((area).dma_handle,\
140			(index * RBR_SIZE), count * RBR_SIZE,	\
141				(flag)))
142#define	DMA_COMMON_SYNC_ENTRY(area, index, flag)	\
143				((void) ddi_dma_sync((area).dma_handle,\
144				(index * (area).block_size),	\
145				(area).block_size, \
146				(flag)))
147
148#define	NEXT_ENTRY(index, wrap)		((index + 1) & wrap)
149#define	NEXT_ENTRY_PTR(ptr, first, last)	\
150					((ptr == last) ? first : (ptr + 1))
151
152/*
153 * NPI related macros
154 */
155#define	NXGE_DEV_NPI_HANDLE(nxgep)	(nxgep->npi_handle)
156
157#define	NPI_PCI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_pci_handle.regh = ah)
158#define	NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap)
159
160#define	NPI_ACC_HANDLE_SET(nxgep, ah)	(nxgep->npi_handle.regh = ah)
161#define	NPI_ADD_HANDLE_SET(nxgep, ap)	\
162		nxgep->npi_handle.is_vraddr = B_FALSE;	\
163		nxgep->npi_handle.function.instance = nxgep->instance;   \
164		nxgep->npi_handle.function.function = nxgep->function_num;   \
165		nxgep->npi_handle.nxgep = (void *) nxgep;   \
166		nxgep->npi_handle.regp = ap;
167
168#define	NPI_REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_reg_handle.regh = ah)
169#define	NPI_REG_ADD_HANDLE_SET(nxgep, ap)	\
170		nxgep->npi_reg_handle.is_vraddr = B_FALSE;	\
171		nxgep->npi_handle.function.instance = nxgep->instance;   \
172		nxgep->npi_handle.function.function = nxgep->function_num;   \
173		nxgep->npi_reg_handle.nxgep = (void *) nxgep;   \
174		nxgep->npi_reg_handle.regp = ap;
175
176#define	NPI_MSI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_msi_handle.regh = ah)
177#define	NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap)
178
179#define	NPI_VREG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_vreg_handle.regh = ah)
180#define	NPI_VREG_ADD_HANDLE_SET(nxgep, ap)	\
181		nxgep->npi_vreg_handle.is_vraddr = B_TRUE; \
182		nxgep->npi_handle.function.instance = nxgep->instance;   \
183		nxgep->npi_handle.function.function = nxgep->function_num;   \
184		nxgep->npi_vreg_handle.nxgep = (void *) nxgep;   \
185		nxgep->npi_vreg_handle.regp = ap;
186
187#define	NPI_V2REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_v2reg_handle.regh = ah)
188#define	NPI_V2REG_ADD_HANDLE_SET(nxgep, ap)	\
189		nxgep->npi_v2reg_handle.is_vraddr = B_TRUE; \
190		nxgep->npi_handle.function.instance = nxgep->instance;   \
191		nxgep->npi_handle.function.function = nxgep->function_num;   \
192		nxgep->npi_v2reg_handle.nxgep = (void *) nxgep;   \
193		nxgep->npi_v2reg_handle.regp = ap;
194
195#define	NPI_PCI_ACC_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regh)
196#define	NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp)
197#define	NPI_ACC_HANDLE_GET(nxgep) (nxgep->npi_handle.regh)
198#define	NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp)
199#define	NPI_REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regh)
200#define	NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp)
201#define	NPI_MSI_ACC_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regh)
202#define	NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp)
203#define	NPI_VREG_ACC_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regh)
204#define	NPI_VREG_ADD_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regp)
205#define	NPI_V2REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regh)
206#define	NPI_V2REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regp)
207
208#define	NPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->npi_handle.regh = ah)
209#define	NPI_DMA_ACC_HANDLE_GET(dmap) 	(dmap->npi_handle.regh)
210
211/*
212 * DMA handles.
213 */
214#define	NXGE_DESC_D_HANDLE_GET(desc)	(desc.dma_handle)
215#define	NXGE_DESC_D_IOADD_GET(desc)	(desc.dma_cookie.dmac_laddress)
216#define	NXGE_DMA_IOADD_GET(dma_cookie) (dma_cookie.dmac_laddress)
217#define	NXGE_DMA_AREA_IOADD_GET(dma_area) (dma_area.dma_cookie.dmac_laddress)
218
219#define	LDV_ON(ldv, vector)	((vector >> ldv) & 0x1)
220#define	LDV2_ON_1(ldv, vector)	((vector >> (ldv - 64)) & 0x1)
221#define	LDV2_ON_2(ldv, vector)	(((vector >> 5) >> (ldv - 64)) & 0x1)
222
223typedef uint32_t		nxge_status_t;
224
225typedef enum  {
226	IDLE,
227	PROGRESS,
228	CONFIGURED
229} dev_func_shared_t;
230
231typedef enum  {
232	DVMA,
233	DMA,
234	SDMA
235} dma_method_t;
236
237typedef enum  {
238	BKSIZE_4K,
239	BKSIZE_8K,
240	BKSIZE_16K,
241	BKSIZE_32K
242} nxge_rx_block_size_t;
243
244#ifdef TX_ONE_BUF
245#define	TX_BCOPY_MAX 1514
246#else
247#if	defined(sun4v) && defined(NIU_LP_WORKAROUND)
248#define	TX_BCOPY_MAX	4096
249#define	TX_BCOPY_SIZE	4096
250#else
251#define	TX_BCOPY_MAX	2048
252#define	TX_BCOPY_SIZE	2048
253#endif
254#endif
255
256#define	TX_STREAM_MIN 512
257#define	TX_FASTDVMA_MIN 1024
258
259/*
260 * Send repeated FMA ereports or display messages about some non-fatal
261 * hardware errors only the the first NXGE_ERROR_SHOW_MAX -1 times
262 */
263#define	NXGE_ERROR_SHOW_MAX	2
264
265
266/*
267 * Defaults
268 */
269#define	NXGE_RDC_RCR_THRESHOLD		32
270#define	NXGE_RDC_RCR_TIMEOUT		8
271
272#define	NXGE_RDC_RCR_THRESHOLD_MAX	1024
273#define	NXGE_RDC_RCR_TIMEOUT_MAX	64
274#define	NXGE_RDC_RCR_THRESHOLD_MIN	8
275#define	NXGE_RDC_RCR_TIMEOUT_MIN	1
276#define	NXGE_RCR_FULL_HEADER		1
277
278#define	NXGE_IS_VLAN_PACKET(ptr)				\
279	((((struct ether_vlan_header *)ptr)->ether_tpid) ==	\
280	htons(VLAN_ETHERTYPE))
281
282typedef enum {
283	NONE,
284	SMALL,
285	MEDIUM,
286	LARGE
287} dma_size_t;
288
289typedef enum {
290	USE_NONE,
291	USE_BCOPY,
292	USE_DVMA,
293	USE_DMA,
294	USE_SDMA
295} dma_type_t;
296
297typedef enum {
298	NOT_IN_USE,
299	HDR_BUF,
300	MTU_BUF,
301	RE_ASSEMBLY_BUF,
302	FREE_BUF
303} rx_page_state_t;
304
305struct _nxge_block_mv_t {
306	uint32_t msg_type;
307	dma_type_t dma_type;
308};
309
310typedef struct _nxge_block_mv_t nxge_block_mv_t, *p_nxge_block_mv_t;
311
312typedef enum {
313	NIU_TYPE_NONE = 0,
314
315	/* QGC NIC */
316	NEPTUNE_4_1GC =
317	    (NXGE_PORT_1G_COPPER |
318	    (NXGE_PORT_1G_COPPER << 4) |
319	    (NXGE_PORT_1G_COPPER << 8) |
320	    (NXGE_PORT_1G_COPPER << 12)),
321
322	/* Huron: 2 fiber XAUI cards */
323	NEPTUNE_2_10GF =
324	    (NXGE_PORT_10G_FIBRE |
325	    (NXGE_PORT_10G_FIBRE << 4) |
326	    (NXGE_PORT_NONE << 8) |
327	    (NXGE_PORT_NONE << 12)),
328
329	/* Huron: port0 is a TN1010 copper XAUI */
330	NEPTUNE_1_TN1010 =
331	    (NXGE_PORT_TN1010 |
332	    (NXGE_PORT_NONE << 4) |
333	    (NXGE_PORT_NONE << 8) |
334	    (NXGE_PORT_NONE << 12)),
335
336	/* Huron: port1 is a TN1010 copper XAUI */
337	NEPTUNE_1_NONE_1_TN1010 =
338	    (NXGE_PORT_NONE |
339	    (NXGE_PORT_TN1010 << 4) |
340	    (NXGE_PORT_NONE << 8) |
341	    (NXGE_PORT_NONE << 12)),
342
343	/* Huron: 2 TN1010 copper XAUI cards */
344	NEPTUNE_2_TN1010 =
345	    (NXGE_PORT_TN1010 |
346	    (NXGE_PORT_TN1010 << 4) |
347	    (NXGE_PORT_NONE << 8) |
348	    (NXGE_PORT_NONE << 12)),
349
350	/* Huron: port0 is fiber XAUI, port1 is copper XAUI */
351	NEPTUNE_1_10GF_1_TN1010 =
352	    (NXGE_PORT_10G_FIBRE |
353	    (NXGE_PORT_TN1010 << 4) |
354	    (NXGE_PORT_NONE << 8) |
355	    (NXGE_PORT_NONE << 12)),
356
357	/* Huron: port0 is copper XAUI, port1 is fiber XAUI */
358	NEPTUNE_1_TN1010_1_10GF =
359	    (NXGE_PORT_TN1010 |
360	    (NXGE_PORT_10G_FIBRE << 4) |
361	    (NXGE_PORT_NONE << 8) |
362	    (NXGE_PORT_NONE << 12)),
363
364	/* Maramba: port0 and port1 are fiber XAUIs */
365	NEPTUNE_2_10GF_2_1GC =
366	    (NXGE_PORT_10G_FIBRE |
367	    (NXGE_PORT_10G_FIBRE << 4) |
368	    (NXGE_PORT_1G_COPPER << 8) |
369	    (NXGE_PORT_1G_COPPER << 12)),
370
371	/* Maramba: port0 and port1 are copper TN1010 XAUIs */
372	NEPTUNE_2_TN1010_2_1GC =
373	    (NXGE_PORT_TN1010 |
374	    (NXGE_PORT_TN1010 << 4) |
375	    (NXGE_PORT_1G_COPPER << 8) |
376	    (NXGE_PORT_1G_COPPER << 12)),
377
378	/* Maramba: port0 is copper XAUI, port1 is Fiber XAUI */
379	NEPTUNE_1_TN1010_1_10GF_2_1GC =
380	    (NXGE_PORT_TN1010 |
381	    (NXGE_PORT_10G_FIBRE << 4) |
382	    (NXGE_PORT_1G_COPPER << 8) |
383	    (NXGE_PORT_1G_COPPER << 12)),
384
385	/* Maramba: port0 is fiber XAUI, port1 is copper XAUI */
386	NEPTUNE_1_10GF_1_TN1010_2_1GC =
387	    (NXGE_PORT_10G_FIBRE |
388	    (NXGE_PORT_TN1010 << 4) |
389	    (NXGE_PORT_1G_COPPER << 8) |
390	    (NXGE_PORT_1G_COPPER << 12)),
391
392	/* Maramba: port0 is fiber XAUI */
393	NEPTUNE_1_10GF_3_1GC =
394	    (NXGE_PORT_10G_FIBRE |
395	    (NXGE_PORT_1G_COPPER << 4) |
396	    (NXGE_PORT_1G_COPPER << 8) |
397	    (NXGE_PORT_1G_COPPER << 12)),
398
399	/* Maramba: port0 is TN1010 copper XAUI */
400	NEPTUNE_1_TN1010_3_1GC =
401	    (NXGE_PORT_TN1010 |
402	    (NXGE_PORT_1G_COPPER << 4) |
403	    (NXGE_PORT_1G_COPPER << 8) |
404	    (NXGE_PORT_1G_COPPER << 12)),
405
406	/* Maramba: port1 is fiber XAUI */
407	NEPTUNE_1_1GC_1_10GF_2_1GC =
408	    (NXGE_PORT_1G_COPPER |
409	    (NXGE_PORT_10G_FIBRE << 4) |
410	    (NXGE_PORT_1G_COPPER << 8) |
411	    (NXGE_PORT_1G_COPPER << 12)),
412
413	/* Maramba: port1 is TN1010 copper XAUI */
414	NEPTUNE_1_1GC_1_TN1010_2_1GC =
415	    (NXGE_PORT_1G_COPPER |
416	    (NXGE_PORT_TN1010 << 4) |
417	    (NXGE_PORT_1G_COPPER << 8) |
418	    (NXGE_PORT_1G_COPPER << 12)),
419
420	NEPTUNE_2_1GRF =
421	    (NXGE_PORT_NONE |
422	    (NXGE_PORT_NONE << 4) |
423	    (NXGE_PORT_1G_RGMII_FIBER << 8) |
424	    (NXGE_PORT_1G_RGMII_FIBER << 12)),
425
426	NEPTUNE_2_10GF_2_1GRF =
427	    (NXGE_PORT_10G_FIBRE |
428	    (NXGE_PORT_10G_FIBRE << 4) |
429	    (NXGE_PORT_1G_RGMII_FIBER << 8) |
430	    (NXGE_PORT_1G_RGMII_FIBER << 12)),
431
432	N2_NIU =
433	    (NXGE_PORT_RSVD |
434	    (NXGE_PORT_RSVD << 4) |
435	    (NXGE_PORT_RSVD << 8) |
436	    (NXGE_PORT_RSVD << 12))
437
438} niu_type_t;
439
440/*
441 * The niu_hw_type is for non-PHY related functions
442 * designed on various versions of NIU chips (i.e. RF/NIU has
443 * additional classification features and communicates with
444 * a different SerDes than N2/NIU).
445 */
446typedef enum {
447	NIU_HW_TYPE_DEFAULT = 0,	/* N2/NIU */
448	NIU_HW_TYPE_RF = 1,		/* RF/NIU */
449} niu_hw_type_t;
450
451/*
452 * P_NEPTUNE_GENERIC:
453 *	The cover-all case for Neptune (as opposed to NIU) where we do not
454 *	care the exact platform as we do not do anything that is platform
455 *	specific.
456 * P_NEPTUNE_ATLAS_2PORT:
457 *	Dual Port Fiber Neptune based NIC (2XGF)
458 * P_NEPTUNE_ATLAS_4PORT:
459 *	Quad Port Copper Neptune based NIC (QGC)
460 * P_NEPTUNE_NIU:
461 *	This is NIU. Could be Huron, Glendale, Monza or any other NIU based
462 *	platform.
463 */
464typedef enum {
465	P_NEPTUNE_NONE,
466	P_NEPTUNE_GENERIC,
467	P_NEPTUNE_ATLAS_2PORT,
468	P_NEPTUNE_ATLAS_4PORT,
469	P_NEPTUNE_MARAMBA_P0,
470	P_NEPTUNE_MARAMBA_P1,
471	P_NEPTUNE_ALONSO,
472	P_NEPTUNE_ROCK,
473	P_NEPTUNE_NIU
474} platform_type_t;
475
476#define	NXGE_IS_VALID_NEPTUNE_TYPE(nxgep) \
477	(((nxgep->platform_type) == P_NEPTUNE_ATLAS_2PORT) || \
478	    ((nxgep->platform_type) == P_NEPTUNE_ATLAS_4PORT) || \
479	    ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \
480	    ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1) || \
481	    ((nxgep->platform_type) == P_NEPTUNE_GENERIC) || \
482	    ((nxgep->platform_type) == P_NEPTUNE_ALONSO) || \
483	    ((nxgep->platform_type) == P_NEPTUNE_ROCK))
484
485#define	NXGE_IS_XAUI_PLATFORM(nxgep) \
486	(((nxgep->platform_type) == P_NEPTUNE_NIU) || \
487	    ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \
488	    ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1))
489
490
491typedef enum {
492	CFG_DEFAULT = 0,	/* default cfg */
493	CFG_EQUAL,	/* Equal */
494	CFG_FAIR,	/* Equal */
495	CFG_CLASSIFY,
496	CFG_L2_CLASSIFY,
497	CFG_L3_CLASSIFY,
498	CFG_L3_DISTRIBUTE,
499	CFG_L3_WEB,
500	CFG_L3_TCAM,
501	CFG_NOT_SPECIFIED,
502	CFG_CUSTOM	/* Custom */
503} cfg_type_t;
504
505typedef enum {
506	NO_MSG = 0x0,		/* No message output or storage. */
507	CONSOLE = 0x1,		/* Messages are go to the console. */
508	BUFFER = 0x2,		/* Messages are go to the system buffer. */
509	CON_BUF = 0x3,		/* Messages are go to the console and */
510				/* system buffer. */
511	VERBOSE = 0x4		/* Messages are go out only in VERBOSE node. */
512} out_msg_t, *p_out_msg_t;
513
514typedef enum {
515	DBG_NO_MSG = 0x0,	/* No message output or storage. */
516	DBG_CONSOLE = 0x1,	/* Messages are go to the console. */
517	DBG_BUFFER = 0x2,	/* Messages are go to the system buffer. */
518	DBG_CON_BUF = 0x3,	/* Messages are go to the console and */
519				/* system buffer. */
520	STR_LOG = 4		/* Sessage sent to streams logging driver. */
521} out_dbgmsg_t, *p_out_dbgmsg_t;
522
523typedef enum {
524	DDI_MEM_ALLOC,		/* default (use ddi_dma_mem_alloc) */
525	KMEM_ALLOC,		/* use kmem_alloc(). */
526	CONTIG_MEM_ALLOC	/* use contig_mem_alloc() (N2/NIU only) */
527} buf_alloc_type_t;
528
529#define	BUF_ALLOCATED		0x00000001
530#define	BUF_ALLOCATED_WAIT_FREE	0x00000002
531
532typedef struct ether_addr ether_addr_st, *p_ether_addr_t;
533typedef struct ether_header ether_header_t, *p_ether_header_t;
534typedef queue_t *p_queue_t;
535typedef mblk_t *p_mblk_t;
536
537/*
538 * Generic phy table to support different phy types.
539 *
540 * The argument for check_link is nxgep, which is passed to check_link
541 * as an argument to the timer routine.
542 */
543typedef struct _nxge_xcvr_table {
544	nxge_status_t	(*serdes_init)	();	/* Serdes init routine */
545	nxge_status_t	(*xcvr_init)	();	/* xcvr init routine */
546	nxge_status_t	(*link_intr_stop) ();	/* Link intr disable routine */
547	nxge_status_t	(*link_intr_start) ();	/* Link intr enable routine */
548	nxge_status_t	(*check_link) ();	/* Link check routine */
549
550	uint32_t	xcvr_inuse;
551} nxge_xcvr_table_t, *p_nxge_xcvr_table_t;
552
553/*
554 * Common DMA data elements.
555 */
556typedef struct _nxge_dma_pool_t nxge_dma_pool_t, *p_nxge_dma_pool_t;
557
558struct _nxge_dma_common_t {
559	uint16_t		dma_channel;
560	void			*kaddrp;
561	void			*last_kaddrp;
562	void			*ioaddr_pp;
563	void			*first_ioaddr_pp;
564	void			*last_ioaddr_pp;
565	ddi_dma_cookie_t 	dma_cookie;
566	uint32_t		ncookies;
567
568	ddi_dma_handle_t	dma_handle;
569	nxge_os_acc_handle_t	acc_handle;
570	npi_handle_t		npi_handle;
571
572	size_t			block_size;
573	uint32_t		nblocks;
574	size_t			alength;
575	uint_t			offset;
576	uint_t			dma_chunk_index;
577	void			*orig_ioaddr_pp;
578	uint64_t		orig_vatopa;
579	void			*orig_kaddrp;
580	size_t			orig_alength;
581	boolean_t		contig_alloc_type;
582	/*
583	 * Receive buffers may be allocated using
584	 * kmem_alloc(). The buffer free function
585	 * depends on its allocation function.
586	 */
587	boolean_t		kmem_alloc_type;
588	uint32_t		buf_alloc_state;
589	buf_alloc_type_t	buf_alloc_type;
590	p_nxge_dma_pool_t	rx_buf_pool_p;
591};
592
593typedef struct _nxge_t nxge_t, *p_nxge_t;
594typedef struct _nxge_dma_common_t nxge_dma_common_t, *p_nxge_dma_common_t;
595
596struct _nxge_dma_pool_t {
597	p_nxge_dma_common_t	*dma_buf_pool_p;
598	uint32_t		ndmas;
599	uint32_t		*num_chunks;
600	boolean_t		buf_allocated;
601};
602
603/*
604 * Each logical device (69):
605 *	- LDG #
606 *	- flag bits
607 *	- masks.
608 *	- interrupt handler function.
609 *
610 * Generic system interrupt handler with two arguments:
611 *	(nxge_sys_intr_t)
612 *	Per device instance data structure
613 *	Logical group data structure.
614 *
615 * Logical device interrupt handler with two arguments:
616 *	(nxge_ldv_intr_t)
617 *	Per device instance data structure
618 *	Logical device number
619 */
620typedef struct	_nxge_ldg_t nxge_ldg_t, *p_nxge_ldg_t;
621typedef struct	_nxge_ldv_t nxge_ldv_t, *p_nxge_ldv_t;
622typedef uint_t	(*nxge_sys_intr_t)(void *arg1, void *arg2);
623typedef uint_t	(*nxge_ldv_intr_t)(void *arg1, void *arg2);
624
625/*
626 * Each logical device Group (64) needs to have the following
627 * configurations:
628 *	- timer counter (6 bits)
629 *	- timer resolution (20 bits, number of system clocks)
630 *	- system data (7 bits)
631 */
632struct _nxge_ldg_t {
633	uint8_t			ldg;		/* logical group number */
634	uint8_t			vldg_index;
635	boolean_t		arm;
636	uint16_t		ldg_timer;	/* counter */
637	uint8_t			func;
638	uint8_t			vector;
639	uint8_t			intdata;
640	uint8_t			nldvs;
641	p_nxge_ldv_t		ldvp;
642	nxge_sys_intr_t		sys_intr_handler;
643	p_nxge_t		nxgep;
644	uint32_t		htable_idx;
645};
646
647struct _nxge_ldv_t {
648	uint8_t			ldg_assigned;
649	uint8_t			ldv;
650	boolean_t		is_rxdma;
651	boolean_t		is_txdma;
652	boolean_t		is_mif;
653	boolean_t		is_mac;
654	boolean_t		is_syserr;
655	boolean_t		use_timer;
656	uint8_t			channel;
657	uint8_t			vdma_index;
658	uint8_t			func;
659	p_nxge_ldg_t		ldgp;
660	uint8_t			ldv_flags;
661	uint8_t			ldv_ldf_masks;
662	nxge_ldv_intr_t		ldv_intr_handler;
663	p_nxge_t		nxgep;
664};
665
666typedef struct _nxge_logical_page_t {
667	uint16_t		dma;
668	uint16_t		page;
669	boolean_t		valid;
670	uint64_t		mask;
671	uint64_t		value;
672	uint64_t		reloc;
673	uint32_t		handle;
674} nxge_logical_page_t, *p_nxge_logical_page_t;
675
676/*
677 * (Internal) return values from ioctl subroutines.
678 */
679enum nxge_ioc_reply {
680	IOC_INVAL = -1,				/* bad, NAK with EINVAL	*/
681	IOC_DONE,				/* OK, reply sent	*/
682	IOC_ACK,				/* OK, just send ACK	*/
683	IOC_REPLY,				/* OK, just send reply	*/
684	IOC_RESTART_ACK,			/* OK, restart & ACK	*/
685	IOC_RESTART_REPLY			/* OK, restart & reply	*/
686};
687
688typedef struct _pci_cfg_t {
689	uint16_t vendorid;
690	uint16_t devid;
691	uint16_t command;
692	uint16_t status;
693	uint8_t  revid;
694	uint8_t  res0;
695	uint16_t junk1;
696	uint8_t  cache_line;
697	uint8_t  latency;
698	uint8_t  header;
699	uint8_t  bist;
700	uint32_t base;
701	uint32_t base14;
702	uint32_t base18;
703	uint32_t base1c;
704	uint32_t base20;
705	uint32_t base24;
706	uint32_t base28;
707	uint32_t base2c;
708	uint32_t base30;
709	uint32_t res1[2];
710	uint8_t int_line;
711	uint8_t int_pin;
712	uint8_t	min_gnt;
713	uint8_t max_lat;
714} pci_cfg_t, *p_pci_cfg_t;
715
716typedef struct _dev_regs_t {
717	nxge_os_acc_handle_t	nxge_pciregh;	/* PCI config DDI IO handle */
718	p_pci_cfg_t		nxge_pciregp;	/* mapped PCI registers */
719
720	nxge_os_acc_handle_t	nxge_regh;	/* device DDI IO (BAR 0) */
721	void			*nxge_regp;	/* mapped device registers */
722
723	nxge_os_acc_handle_t	nxge_msix_regh;	/* MSI/X DDI handle (BAR 2) */
724	void 			*nxge_msix_regp; /* MSI/X register */
725
726	nxge_os_acc_handle_t	nxge_vir_regh;	/* virtualization (BAR 4) */
727	unsigned char		*nxge_vir_regp;	/* virtualization register */
728
729	nxge_os_acc_handle_t	nxge_vir2_regh;	/* second virtualization */
730	unsigned char		*nxge_vir2_regp; /* second virtualization */
731
732	nxge_os_acc_handle_t	nxge_romh;	/* fcode rom handle */
733	unsigned char		*nxge_romp;	/* fcode pointer */
734} dev_regs_t, *p_dev_regs_t;
735
736
737typedef struct _nxge_mac_addr_t {
738	ether_addr_t	addr;
739	uint_t		flags;
740} nxge_mac_addr_t;
741
742/*
743 * The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac)
744 * for each XMAC port and supports 1 unique MAC and 7 alternate MACs
745 * for each BMAC port.  The number of MACs assigned by the factory is
746 * different and is as follows,
747 * 	BMAC port:		   num_factory_mmac = num_mmac = 7
748 *	XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15
749 *	XMAC port on a 4-port NIC: num_factory_mmac = 7
750 * So num_factory_mmac is smaller than num_mmac.  nxge_m_mmac_add uses
751 * num_mmac and nxge_m_mmac_reserve uses num_factory_mmac.
752 *
753 * total_factory_macs is the total number of factory MACs, including
754 * the unique MAC, assigned to a Neptune based NIC card, it is 32.
755 */
756typedef struct _nxge_mmac_t {
757	uint8_t		total_factory_macs;
758	uint8_t		num_mmac;
759	uint8_t		num_factory_mmac;
760	nxge_mac_addr_t	mac_pool[XMAC_MAX_ADDR_ENTRY];
761	ether_addr_t	factory_mac_pool[XMAC_MAX_ADDR_ENTRY];
762	uint8_t		naddrfree;  /* number of alt mac addr available */
763} nxge_mmac_t;
764
765/*
766 * mmac stats structure
767 */
768typedef struct _nxge_mmac_stats_t {
769	uint8_t mmac_max_cnt;
770	uint8_t	mmac_avail_cnt;
771	struct ether_addr mmac_avail_pool[16];
772} nxge_mmac_stats_t, *p_nxge_mmac_stats_t;
773
774/*
775 * Copied from mac.h. Should be cleaned up by driver.
776 */
777#define	MMAC_SLOT_USED		0x1   /* address slot used */
778#define	MMAC_VENDOR_ADDR	0x2   /* address returned is vendor supplied */
779
780
781#define	NXGE_MAX_MMAC_ADDRS	32
782#define	NXGE_NUM_MMAC_ADDRS	8
783#define	NXGE_NUM_OF_PORTS_QUAD	4
784#define	NXGE_NUM_OF_PORTS_DUAL	2
785
786#define	NXGE_QGC_LP_BM_STR		"501-7606"
787#define	NXGE_2XGF_LP_BM_STR		"501-7283"
788#define	NXGE_QGC_PEM_BM_STR		"501-7765"
789#define	NXGE_2XGF_PEM_BM_STR		"501-7626"
790#define	NXGE_ALONSO_BM_STR		"373-0202-01"
791#define	NXGE_ALONSO_MODEL_STR		"SUNW,CP3220"
792#define	NXGE_RFEM_BM_STR		"501-7961-01"
793#define	NXGE_RFEM_MODEL_STR		"SUNW,pcie-rfem"
794#define	NXGE_ARTM_BM_STR		"375-3544-01"
795#define	NXGE_ARTM_MODEL_STR		"SUNW,pcie-artm"
796/* ROCK OBP creates a compatible property for ROCK */
797#define	NXGE_ROCK_COMPATIBLE		"SUNW,rock-pciex108e,abcd"
798#define	NXGE_EROM_LEN			1048576
799
800#include 	<sys/nxge/nxge_common_impl.h>
801#include 	<sys/nxge/nxge_common.h>
802#include	<sys/nxge/nxge_txc.h>
803#include	<sys/nxge/nxge_rxdma.h>
804#include	<sys/nxge/nxge_txdma.h>
805#include	<sys/nxge/nxge_fflp.h>
806#include	<sys/nxge/nxge_ipp.h>
807#include	<sys/nxge/nxge_zcp.h>
808#include	<sys/nxge/nxge_fzc.h>
809#include	<sys/nxge/nxge_flow.h>
810#include	<sys/nxge/nxge_virtual.h>
811
812#include	<npi_espc.h>
813#include	<npi_vir.h>
814
815#include 	<sys/nxge/nxge.h>
816
817#include	<sys/modctl.h>
818#include	<sys/pattr.h>
819
820extern int secpolicy_net_config(const cred_t *, boolean_t);
821extern void nxge_fm_report_error(p_nxge_t, uint8_t,
822			uint8_t, nxge_fm_ereport_id_t);
823extern int fm_check_acc_handle(ddi_acc_handle_t);
824extern int fm_check_dma_handle(ddi_dma_handle_t);
825
826/* nxge_classify.c */
827nxge_status_t nxge_classify_init(p_nxge_t);
828nxge_status_t nxge_classify_uninit(p_nxge_t);
829nxge_status_t nxge_set_hw_classify_config(p_nxge_t);
830nxge_status_t nxge_classify_exit_sw(p_nxge_t);
831
832/* nxge_fflp.c */
833void nxge_put_tcam(p_nxge_t, p_mblk_t);
834void nxge_get_tcam(p_nxge_t, p_mblk_t);
835nxge_status_t nxge_classify_init_hw(p_nxge_t);
836nxge_status_t nxge_classify_init_sw(p_nxge_t);
837nxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t);
838nxge_status_t nxge_fflp_ip_class_config(p_nxge_t, tcam_class_t,
839				    uint32_t);
840
841nxge_status_t nxge_fflp_ip_class_config_get(p_nxge_t,
842				    tcam_class_t,
843				    uint32_t *);
844
845nxge_status_t nxge_cfg_ip_cls_flow_key(p_nxge_t, tcam_class_t,
846				    uint32_t);
847
848nxge_status_t nxge_fflp_ip_usr_class_config(p_nxge_t, tcam_class_t,
849				    uint32_t);
850
851uint64_t nxge_classify_get_cfg_value(p_nxge_t, uint8_t, uint8_t);
852nxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *);
853nxge_status_t nxge_fflp_config_tcam_enable(p_nxge_t);
854nxge_status_t nxge_fflp_config_tcam_disable(p_nxge_t);
855
856nxge_status_t nxge_fflp_config_hash_lookup_enable(p_nxge_t);
857nxge_status_t nxge_fflp_config_hash_lookup_disable(p_nxge_t);
858
859nxge_status_t nxge_fflp_config_llc_snap_enable(p_nxge_t);
860nxge_status_t nxge_fflp_config_llc_snap_disable(p_nxge_t);
861
862nxge_status_t nxge_logical_mac_assign_rdc_table(p_nxge_t, uint8_t);
863nxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t);
864
865nxge_status_t nxge_fflp_set_hash1(p_nxge_t, uint32_t);
866
867nxge_status_t nxge_fflp_set_hash2(p_nxge_t, uint16_t);
868
869nxge_status_t nxge_fflp_init_hostinfo(p_nxge_t);
870
871void nxge_handle_tcam_fragment_bug(p_nxge_t);
872int nxge_rxclass_ioctl(p_nxge_t, queue_t *, mblk_t *);
873int nxge_rxhash_ioctl(p_nxge_t, queue_t *, mblk_t *);
874
875nxge_status_t nxge_fflp_hw_reset(p_nxge_t);
876nxge_status_t nxge_fflp_handle_sys_errors(p_nxge_t);
877nxge_status_t nxge_zcp_handle_sys_errors(p_nxge_t);
878
879/* nxge_kstats.c */
880void nxge_init_statsp(p_nxge_t);
881void nxge_setup_kstats(p_nxge_t);
882void nxge_setup_rdc_kstats(p_nxge_t, int);
883void nxge_setup_tdc_kstats(p_nxge_t, int);
884void nxge_destroy_kstats(p_nxge_t);
885int nxge_port_kstat_update(kstat_t *, int);
886void nxge_save_cntrs(p_nxge_t);
887
888int nxge_m_stat(void *arg, uint_t, uint64_t *);
889int nxge_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
890int nxge_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
891
892/* nxge_hw.c */
893void
894nxge_hw_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
895void nxge_loopback_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
896nxge_status_t nxge_global_reset(p_nxge_t);
897uint_t nxge_intr(void *, void *);
898void nxge_intr_enable(p_nxge_t);
899void nxge_intr_disable(p_nxge_t);
900void nxge_hw_blank(void *arg, time_t, uint_t);
901void nxge_hw_id_init(p_nxge_t);
902void nxge_hw_init_niu_common(p_nxge_t);
903void nxge_intr_hw_enable(p_nxge_t);
904void nxge_intr_hw_disable(p_nxge_t);
905void nxge_hw_stop(p_nxge_t);
906void nxge_check_hw_state(p_nxge_t);
907
908void nxge_rxdma_channel_put64(nxge_os_acc_handle_t,
909	void *, uint32_t, uint16_t,
910	uint64_t);
911uint64_t nxge_rxdma_channel_get64(nxge_os_acc_handle_t, void *,
912	uint32_t, uint16_t);
913
914
915void nxge_get32(p_nxge_t, p_mblk_t);
916void nxge_put32(p_nxge_t, p_mblk_t);
917
918void nxge_hw_set_mac_modes(p_nxge_t);
919
920/* nxge_send.c. */
921uint_t nxge_reschedule(caddr_t);
922mblk_t *nxge_tx_ring_send(void *, mblk_t *);
923int nxge_start(p_nxge_t, p_tx_ring_t, p_mblk_t);
924
925/* nxge_rxdma.c */
926nxge_status_t nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t,
927					    uint8_t, uint8_t);
928
929nxge_status_t nxge_rxdma_cfg_port_default_rdc(p_nxge_t,
930				    uint8_t, uint8_t);
931nxge_status_t nxge_rxdma_cfg_rcr_threshold(p_nxge_t, uint8_t,
932				    uint16_t);
933nxge_status_t nxge_rxdma_cfg_rcr_timeout(p_nxge_t, uint8_t,
934				    uint16_t, uint8_t);
935
936/* nxge_ndd.c */
937void nxge_get_param_soft_properties(p_nxge_t);
938void nxge_copy_hw_default_to_param(p_nxge_t);
939void nxge_copy_param_hw_to_config(p_nxge_t);
940void nxge_setup_param(p_nxge_t);
941void nxge_init_param(p_nxge_t);
942void nxge_destroy_param(p_nxge_t);
943boolean_t nxge_check_rxdma_rdcgrp_member(p_nxge_t, uint8_t, uint8_t);
944boolean_t nxge_check_rxdma_port_member(p_nxge_t, uint8_t);
945boolean_t nxge_check_rdcgrp_port_member(p_nxge_t, uint8_t);
946
947boolean_t nxge_check_txdma_port_member(p_nxge_t, uint8_t);
948
949int nxge_param_get_generic(p_nxge_t, queue_t *, mblk_t *, caddr_t);
950int nxge_param_set_generic(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t);
951int nxge_get_default(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
952int nxge_set_default(p_nxge_t, queue_t *, p_mblk_t, char *, caddr_t);
953int nxge_nd_get_names(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
954int nxge_mk_mblk_tail_space(p_mblk_t, p_mblk_t *, size_t);
955long nxge_strtol(char *, char **, int);
956boolean_t nxge_param_get_instance(queue_t *, mblk_t *);
957void nxge_param_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
958boolean_t nxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t);
959void nxge_nd_free(caddr_t *);
960int nxge_nd_getset(p_nxge_t, queue_t *, caddr_t, p_mblk_t);
961
962nxge_status_t nxge_set_lb_normal(p_nxge_t);
963boolean_t nxge_set_lb(p_nxge_t, queue_t *, p_mblk_t);
964boolean_t nxge_param_link_update(p_nxge_t);
965int nxge_param_set_ip_opt(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t);
966int nxge_dld_get_ip_opt(p_nxge_t, caddr_t);
967int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *,
968	mblk_t *, char *, caddr_t);
969int nxge_param_rx_intr_time(p_nxge_t, queue_t *,
970	mblk_t *, char *, caddr_t);
971
972
973/* nxge_virtual.c */
974nxge_status_t nxge_cntlops(dev_info_t *, nxge_ctl_enum_t, void *, void *);
975void nxge_common_lock_get(p_nxge_t);
976void nxge_common_lock_free(p_nxge_t);
977
978nxge_status_t nxge_get_config_properties(p_nxge_t);
979void nxge_get_xcvr_properties(p_nxge_t);
980void nxge_init_vlan_config(p_nxge_t);
981void nxge_init_mac_config(p_nxge_t);
982
983
984void nxge_init_logical_devs(p_nxge_t);
985int nxge_init_ldg_intrs(p_nxge_t);
986
987void nxge_set_ldgimgmt(p_nxge_t, uint32_t, boolean_t,
988	uint32_t);
989
990void nxge_init_fzc_txdma_channels(p_nxge_t);
991
992nxge_status_t nxge_init_fzc_txdma_channel(p_nxge_t, uint16_t,
993	p_tx_ring_t, p_tx_mbox_t);
994nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t);
995
996nxge_status_t nxge_init_fzc_rxdma_channel(p_nxge_t, uint16_t);
997
998nxge_status_t nxge_init_fzc_rx_common(p_nxge_t);
999nxge_status_t nxge_init_fzc_rxdma_port(p_nxge_t);
1000
1001nxge_status_t nxge_init_fzc_rxdma_channel_pages(p_nxge_t,
1002	uint16_t, p_rx_rbr_ring_t);
1003nxge_status_t nxge_init_fzc_rxdma_channel_red(p_nxge_t,
1004	uint16_t, p_rx_rcr_ring_t);
1005
1006nxge_status_t nxge_init_fzc_rxdma_channel_clrlog(p_nxge_t,
1007	uint16_t, p_rx_rbr_ring_t);
1008
1009
1010nxge_status_t nxge_init_fzc_txdma_channel_pages(p_nxge_t,
1011	uint16_t, p_tx_ring_t);
1012
1013nxge_status_t nxge_init_fzc_txdma_channel_drr(p_nxge_t, uint16_t,
1014	p_tx_ring_t);
1015
1016nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t);
1017
1018void nxge_init_fzc_ldg_num(p_nxge_t);
1019void nxge_init_fzc_sys_int_data(p_nxge_t);
1020void nxge_init_fzc_ldg_int_timer(p_nxge_t);
1021nxge_status_t nxge_intr_mask_mgmt_set(p_nxge_t, boolean_t on);
1022
1023/* MAC functions */
1024nxge_status_t nxge_mac_init(p_nxge_t);
1025nxge_status_t nxge_link_init(p_nxge_t);
1026nxge_status_t nxge_xif_init(p_nxge_t);
1027nxge_status_t nxge_pcs_init(p_nxge_t);
1028nxge_status_t nxge_mac_ctrl_init(p_nxge_t);
1029nxge_status_t nxge_serdes_init(p_nxge_t);
1030nxge_status_t nxge_serdes_reset(p_nxge_t);
1031nxge_status_t nxge_xcvr_find(p_nxge_t);
1032nxge_status_t nxge_get_xcvr_type(p_nxge_t);
1033nxge_status_t nxge_setup_xcvr_table(p_nxge_t);
1034nxge_status_t nxge_xcvr_init(p_nxge_t);
1035nxge_status_t nxge_tx_mac_init(p_nxge_t);
1036nxge_status_t nxge_rx_mac_init(p_nxge_t);
1037nxge_status_t nxge_tx_mac_enable(p_nxge_t);
1038nxge_status_t nxge_tx_mac_disable(p_nxge_t);
1039nxge_status_t nxge_rx_mac_enable(p_nxge_t);
1040nxge_status_t nxge_rx_mac_disable(p_nxge_t);
1041nxge_status_t nxge_tx_mac_reset(p_nxge_t);
1042nxge_status_t nxge_rx_mac_reset(p_nxge_t);
1043nxge_status_t nxge_link_intr(p_nxge_t, link_intr_enable_t);
1044nxge_status_t nxge_mii_xcvr_init(p_nxge_t);
1045nxge_status_t nxge_mii_xcvr_fiber_init(p_nxge_t);
1046nxge_status_t nxge_mii_read(p_nxge_t, uint8_t,
1047			uint8_t, uint16_t *);
1048nxge_status_t nxge_mii_write(p_nxge_t, uint8_t,
1049			uint8_t, uint16_t);
1050nxge_status_t nxge_mdio_read(p_nxge_t, uint8_t, uint8_t,
1051			uint16_t, uint16_t *);
1052nxge_status_t nxge_mdio_write(p_nxge_t, uint8_t,
1053			uint8_t, uint16_t, uint16_t);
1054nxge_status_t nxge_mii_check(p_nxge_t, mii_bmsr_t,
1055			mii_bmsr_t, nxge_link_state_t *);
1056void nxge_pcs_check(p_nxge_t, uint8_t portn, nxge_link_state_t *);
1057nxge_status_t nxge_add_mcast_addr(p_nxge_t, struct ether_addr *);
1058nxge_status_t nxge_del_mcast_addr(p_nxge_t, struct ether_addr *);
1059nxge_status_t nxge_set_mac_addr(p_nxge_t, struct ether_addr *);
1060nxge_status_t nxge_check_bcm8704_link(p_nxge_t, boolean_t *);
1061nxge_status_t nxge_check_tn1010_link(p_nxge_t);
1062void nxge_link_is_down(p_nxge_t);
1063void nxge_link_is_up(p_nxge_t);
1064nxge_status_t nxge_link_monitor(p_nxge_t, link_mon_enable_t);
1065uint32_t crc32_mchash(p_ether_addr_t);
1066nxge_status_t nxge_set_promisc(p_nxge_t, boolean_t);
1067nxge_status_t nxge_mac_handle_sys_errors(p_nxge_t);
1068nxge_status_t nxge_10g_link_led_on(p_nxge_t);
1069nxge_status_t nxge_10g_link_led_off(p_nxge_t);
1070nxge_status_t nxge_scan_ports_phy(p_nxge_t, p_nxge_hw_list_t);
1071boolean_t nxge_is_valid_local_mac(ether_addr_st);
1072nxge_status_t nxge_mac_set_framesize(p_nxge_t);
1073
1074/* espc (sprom) prototypes */
1075nxge_status_t nxge_espc_mac_addrs_get(p_nxge_t);
1076nxge_status_t nxge_espc_num_macs_get(p_nxge_t, uint8_t *);
1077nxge_status_t nxge_espc_num_ports_get(p_nxge_t);
1078nxge_status_t nxge_espc_phy_type_get(p_nxge_t);
1079nxge_status_t nxge_espc_verify_chksum(p_nxge_t);
1080void nxge_espc_get_next_mac_addr(uint8_t *, uint8_t, struct ether_addr *);
1081void nxge_vpd_info_get(p_nxge_t);
1082
1083
1084void nxge_debug_msg(p_nxge_t, uint64_t, char *, ...);
1085int nxge_get_nports(p_nxge_t);
1086
1087void nxge_free_buf(buf_alloc_type_t, uint64_t, uint32_t);
1088
1089#if defined(sun4v)
1090
1091uint64_t hv_niu_rx_logical_page_conf(uint64_t, uint64_t,
1092	uint64_t, uint64_t);
1093#pragma weak	hv_niu_rx_logical_page_conf
1094
1095uint64_t hv_niu_rx_logical_page_info(uint64_t, uint64_t,
1096	uint64_t *, uint64_t *);
1097#pragma weak	hv_niu_rx_logical_page_info
1098
1099uint64_t hv_niu_tx_logical_page_conf(uint64_t, uint64_t,
1100	uint64_t, uint64_t);
1101#pragma weak	hv_niu_tx_logical_page_conf
1102
1103uint64_t hv_niu_tx_logical_page_info(uint64_t, uint64_t,
1104	uint64_t *, uint64_t *);
1105#pragma weak	hv_niu_tx_logical_page_info
1106
1107uint64_t hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie);
1108#pragma weak	hv_niu_vr_assign
1109
1110uint64_t hv_niu_vr_unassign(uint32_t cookie);
1111#pragma weak	hv_niu_vr_unassign
1112
1113uint64_t hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start,
1114    uint64_t *size);
1115#pragma weak	hv_niu_vr_getinfo
1116
1117uint64_t hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map);
1118#pragma weak	hv_niu_vr_get_rxmap
1119
1120uint64_t hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map);
1121#pragma weak	hv_niu_vr_get_txmap
1122
1123uint64_t hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx,
1124    uint64_t *vchidx);
1125#pragma weak	hv_niu_rx_dma_assign
1126
1127uint64_t hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t chidx);
1128#pragma weak	hv_niu_rx_dma_unassign
1129
1130uint64_t hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx,
1131    uint64_t *vchidx);
1132#pragma weak	hv_niu_tx_dma_assign
1133
1134uint64_t hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx);
1135#pragma weak	hv_niu_tx_dma_unassign
1136
1137uint64_t hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx,
1138    uint64_t pgidx, uint64_t raddr, uint64_t size);
1139#pragma weak	hv_niu_vrrx_logical_page_conf
1140
1141uint64_t hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx,
1142    uint64_t pgidx, uint64_t *raddr, uint64_t *size);
1143#pragma weak	hv_niu_vrrx_logical_page_info
1144
1145uint64_t hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx,
1146    uint64_t pgidx, uint64_t raddr, uint64_t size);
1147#pragma weak	hv_niu_vrtx_logical_page_conf
1148
1149uint64_t hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx,
1150    uint64_t pgidx, uint64_t *raddr, uint64_t *size);
1151#pragma weak	hv_niu_vrtx_logical_page_info
1152
1153uint64_t hv_niu_cfgh_rx_logical_page_conf(uint64_t, uint64_t, uint64_t,
1154	uint64_t, uint64_t);
1155#pragma weak	hv_niu_cfgh_rx_logical_page_conf
1156
1157uint64_t hv_niu_cfgh_rx_logical_page_info(uint64_t, uint64_t, uint64_t,
1158	uint64_t *, uint64_t *);
1159#pragma weak	hv_niu_cfgh_rx_logical_page_info
1160
1161uint64_t hv_niu_cfgh_tx_logical_page_conf(uint64_t, uint64_t, uint64_t,
1162	uint64_t, uint64_t);
1163#pragma weak	hv_niu_cfgh_tx_logical_page_conf
1164
1165uint64_t hv_niu_cfgh_tx_logical_page_info(uint64_t, uint64_t, uint64_t,
1166	uint64_t *, uint64_t *);
1167#pragma weak	hv_niu_cfgh_tx_logical_page_info
1168
1169uint64_t hv_niu_cfgh_vr_assign(uint64_t, uint64_t vridx, uint64_t ldc_id,
1170	uint32_t *cookie);
1171#pragma weak	hv_niu_cfgh_vr_assign
1172
1173//
1174// NIU-specific interrupt API
1175//
1176uint64_t hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t v_chidx,
1177    uint64_t *group, uint64_t *logdev);
1178#pragma weak	hv_niu_vrrx_getinfo
1179
1180uint64_t hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t v_chidx,
1181    uint64_t *group, uint64_t *logdev);
1182#pragma weak	hv_niu_vrtx_getinfo
1183
1184uint64_t hv_niu_vrrx_to_logical_dev(uint32_t cookie, uint64_t v_chidx,
1185    uint64_t *ldn);
1186#pragma weak	hv_niu_vrrx_to_logical_dev
1187
1188uint64_t hv_niu_vrtx_to_logical_dev(uint32_t cookie, uint64_t v_chidx,
1189    uint64_t *ldn);
1190#pragma weak	hv_niu_vrtx_to_logical_dev
1191
1192#endif /* defined(sun4v) */
1193
1194#ifdef NXGE_DEBUG
1195char *nxge_dump_packet(char *, int);
1196#endif
1197
1198#endif	/* !_ASM */
1199
1200#ifdef	__cplusplus
1201}
1202#endif
1203
1204#endif	/* _SYS_NXGE_NXGE_IMPL_H */
1205