xref: /illumos-gate/usr/src/uts/common/sys/nxge/nxge_hw.h (revision 678453a8)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_NXGE_NXGE_HW_H
27 #define	_SYS_NXGE_NXGE_HW_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #if	!defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) && \
36 		!defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN)
37 #error	Host endianness not defined
38 #endif
39 
40 #if	!defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) && \
41 		!defined(__BIT_FIELDS_HTOL) && !defined(__BIT_FIELDS_LTOH)
42 #error	Bit ordering not defined
43 #endif
44 
45 #include <nxge_fflp_hw.h>
46 #include <nxge_ipp_hw.h>
47 #include <nxge_mac_hw.h>
48 #include <nxge_rxdma_hw.h>
49 #include <nxge_txc_hw.h>
50 #include <nxge_txdma_hw.h>
51 #include <nxge_zcp_hw.h>
52 #include <nxge_espc_hw.h>
53 #include <nxge_n2_esr_hw.h>
54 #include <nxge_sr_hw.h>
55 #include <nxge_phy_hw.h>
56 
57 
58 /*
59  * The Neptune chip has 16 Receive DMA channels, but no more than
60  * 24 Transmit DMA channels.
61  */
62 typedef uint32_t dc_map_t;
63 
64 /*
65  * The logical group map is a Crossbow addition.
66  */
67 typedef uint32_t lg_map_t;
68 
69 /* Modes of NXGE core */
70 typedef	enum nxge_mode_e {
71 	NXGE_MODE_NE		= 1,
72 	NXGE_MODE_N2		= 2
73 } nxge_mode_t;
74 
75 /*
76  * Function control Register
77  * (bit 31 is reset to 0. Read back 0 then free to use it.
78  * (once done with it, bit 0:15 can be used to store SW status)
79  */
80 #define	DEV_FUNC_SR_REG			(PIO + 0x10000)
81 #define	DEV_FUNC_SR_SR_SHIFT		0
82 #define	DEV_FUNC_SR_SR_MASK		0x000000000000FFFFULL
83 #define	DEV_FUNC_SR_FUNCID_SHIFT	16
84 #define	DEV_FUNC_SR_FUNCID_MASK		0x0000000000030000ULL
85 #define	DEV_FUNC_SR_TAS_SHIFT		31
86 #define	DEV_FUNC_SR_TAS_MASK		0x0000000080000000ULL
87 
88 typedef union _dev_func_sr_t {
89 	uint64_t value;
90 	struct {
91 #if defined(_BIG_ENDIAN)
92 		uint32_t hdw;
93 #endif
94 		struct {
95 #if defined(_BIT_FIELDS_HTOL)
96 			uint32_t tas:1;
97 			uint32_t res2:13;
98 			uint32_t funcid:2;
99 			uint32_t sr:16;
100 #elif defined(_BIT_FIELDS_LTOH)
101 			uint32_t sr:16;
102 			uint32_t funcid:2;
103 			uint32_t res2:13;
104 			uint32_t tas:1;
105 #endif
106 		} ldw;
107 #if !defined(_BIG_ENDIAN)
108 		uint32_t hdw;
109 #endif
110 	} bits;
111 } dev_func_sr_t, *p_dev_func_sr_t;
112 
113 
114 /*
115  * Multi Parition Control Register (partitiion manager)
116  */
117 #define	MULTI_PART_CTL_REG	(FZC_PIO + 0x00000)
118 #define	MULTI_PART_CTL_MPC	0x0000000000000001ULL
119 
120 typedef union _multi_part_ctl_t {
121 	uint64_t value;
122 	struct {
123 #if defined(_BIG_ENDIAN)
124 		uint32_t hdw;
125 #endif
126 		struct {
127 #if defined(_BIT_FIELDS_HTOL)
128 			uint32_t res1:31;
129 			uint32_t mpc:1;
130 #elif defined(_BIT_FIELDS_LTOH)
131 			uint32_t mpc:1;
132 			uint32_t res1:31;
133 #endif
134 		} ldw;
135 #if !defined(_BIG_ENDIAN)
136 		uint32_t hdw;
137 #endif
138 	} bits;
139 } multi_part_ctl_t, *p_multi_part_ctl_t;
140 
141 /*
142  * Virtual DMA CSR Address (partition manager)
143  */
144 #define	VADDR_REG		(PIO_VADDR + 0x00000)
145 
146 /*
147  * DMA Channel Binding Register (partition manager)
148  */
149 #define	DMA_BIND_REG		(FZC_PIO + 0x10000)
150 #define	DMA_BIND_RX_SHIFT	0
151 #define	DMA_BIND_RX_MASK	0x000000000000001FULL
152 #define	DMA_BIND_RX_BIND_SHIFT	5
153 #define	DMA_BIND_RX_BIND_SET	0x0000000000000020ULL
154 #define	DMA_BIND_RX_BIND_MASK	0x0000000000000020ULL
155 #define	DMA_BIND_TX_SHIFT	8
156 #define	DMA_BIND_TX_MASK	0x0000000000001f00ULL
157 #define	DMA_BIND_TX_BIND_SHIFT	13
158 #define	DMA_BIND_TX_BIND_SET	0x0000000000002000ULL
159 #define	DMA_BIND_TX_BIND_MASK	0x0000000000002000ULL
160 
161 typedef union _dma_bind_t {
162 	uint64_t value;
163 	struct {
164 #if defined(_BIG_ENDIAN)
165 		uint32_t hdw;
166 #endif
167 		struct {
168 #if defined(_BIT_FIELDS_HTOL)
169 			uint32_t res1_1:16;
170 			uint32_t tx_bind:1;
171 			uint32_t tx:5;
172 			uint32_t res2:2;
173 			uint32_t rx_bind:1;
174 			uint32_t rx:5;
175 #elif defined(_BIT_FIELDS_LTOH)
176 			uint32_t rx:5;
177 			uint32_t rx_bind:1;
178 			uint32_t res2:2;
179 			uint32_t tx:5;
180 			uint32_t tx_bind:1;
181 			uint32_t res1_1:16;
182 #endif
183 		} ldw;
184 #if !defined(_BIG_ENDIAN)
185 		uint32_t hdw;
186 #endif
187 	} bits;
188 }  dma_bind_t, *p_dma_bind_t;
189 
190 /*
191  * System interrupts:
192  *	Logical device and group definitions.
193  */
194 #define	NXGE_INT_MAX_LDS		69
195 #define	NXGE_INT_MAX_LDGS		64
196 #define	NXGE_LDGRP_PER_NIU_PORT		(NXGE_INT_MAX_LDGS/2)
197 #define	NXGE_LDGRP_PER_NEP_PORT		(NXGE_INT_MAX_LDGS/4)
198 #define	NXGE_LDGRP_PER_2PORTS		(NXGE_INT_MAX_LDGS/2)
199 #define	NXGE_LDGRP_PER_4PORTS		(NXGE_INT_MAX_LDGS/4)
200 
201 #define	NXGE_RDMA_LD_START		0
202 #define	NXGE_TDMA_LD_START		32
203 #define	NXGE_MIF_LD			63
204 #define	NXGE_MAC_LD_START		64
205 #define	NXGE_MAC_LD_PORT0		64
206 #define	NXGE_MAC_LD_PORT1		65
207 #define	NXGE_MAC_LD_PORT2		66
208 #define	NXGE_MAC_LD_PORT3		67
209 #define	NXGE_SYS_ERROR_LD		68
210 
211 /*
212  * Logical Device Group Number
213  */
214 #define	LDG_NUM_REG		(FZC_PIO + 0x20000)
215 #define	LDG_NUM_NUM_SHIFT	0
216 #define	LDG_NUM_NUM_MASK	0x000000000000001FULL
217 
218 typedef union _ldg_num_t {
219 	uint64_t value;
220 	struct {
221 #if defined(_BIG_ENDIAN)
222 		uint32_t hdw;
223 #endif
224 		struct {
225 #if defined(_BIT_FIELDS_HTOL)
226 			uint32_t res1_1:26;
227 			uint32_t num:6;
228 #elif defined(_BIT_FIELDS_LTOH)
229 			uint32_t num:6;
230 			uint32_t res1_1:26;
231 #endif
232 		} ldw;
233 #if !defined(_BIG_ENDIAN)
234 		uint32_t hdw;
235 #endif
236 	} bits;
237 } ldg_num_t, *p_ldg_num_t;
238 
239 /*
240  * Logical Device State Vector
241  */
242 #define	LDSV0_REG		(PIO_LDSV + 0x00000)
243 #define	LDSV0_LDF_SHIFT		0
244 #define	LDSV0_LDF_MASK		0x00000000000003FFULL
245 #define	LDG_NUM_NUM_MASK	0x000000000000001FULL
246 #define	LDSV_MASK_ALL		0x0000000000000001ULL
247 
248 /*
249  * Logical Device State Vector 1
250  */
251 #define	LDSV1_REG		(PIO_LDSV + 0x00008)
252 
253 /*
254  * Logical Device State Vector 2
255  */
256 #define	LDSV2_REG		(PIO_LDSV + 0x00010)
257 
258 /* For Logical Device State Vector 0 and 1 */
259 typedef union _ldsv_t {
260 	uint64_t value;
261 	struct {
262 #if defined(_BIG_ENDIAN)
263 		uint32_t hdw;
264 #endif
265 		uint32_t ldw;
266 #if !defined(_BIG_ENDIAN)
267 		uint32_t hdw;
268 #endif
269 	} bits;
270 } ldsv_t, *p_ldsv_t;
271 
272 #define	LDSV2_LDF0_SHIFT		0
273 #define	LDSV2_LDF0_MASK			0x000000000000001FULL
274 #define	LDSV2_LDF1_SHIFT		5
275 #define	LDSV2_LDF1_MASK			0x00000000000001E0ULL
276 
277 typedef union _ldsv2_t {
278 	uint64_t value;
279 	struct {
280 #if defined(_BIG_ENDIAN)
281 		uint32_t hdw;
282 #endif
283 		struct {
284 #if defined(_BIT_FIELDS_HTOL)
285 			uint32_t res1_1:22;
286 			uint32_t ldf1:5;
287 			uint32_t ldf0:5;
288 #elif defined(_BIT_FIELDS_LTOH)
289 			uint32_t ldf0:5;
290 			uint32_t ldf1:5;
291 			uint32_t res1_1:22;
292 #endif
293 		} ldw;
294 #if !defined(_BIG_ENDIAN)
295 		uint32_t hdw;
296 #endif
297 	} bits;
298 } ldsv2_t, *p_ldsv2_t;
299 
300 /*
301  * Logical Device Interrupt Mask 0
302  */
303 #define	LD_IM0_REG		(PIO_IMASK0 + 0x00000)
304 #define	LD_IM0_SHIFT		0
305 #define	LD_IM0_MASK		0x0000000000000003ULL
306 #define	LD_IM_MASK		0x0000000000000003ULL
307 
308 /*
309  * Logical Device Interrupt Mask 1
310  */
311 #define	LD_IM1_REG		(PIO_IMASK1 + 0x00000)
312 #define	LD_IM1_SHIFT		0
313 #define	LD_IM1_MASK		0x0000000000000003ULL
314 
315 /* For Lofical Device Interrupt Mask 0 and 1 */
316 typedef union _ld_im_t {
317 	uint64_t value;
318 	struct {
319 #if defined(_BIG_ENDIAN)
320 		uint32_t hdw;
321 #endif
322 		struct {
323 
324 #if defined(_BIT_FIELDS_HTOL)
325 			uint32_t res1_1:30;
326 			uint32_t ldf_mask:2;
327 #elif defined(_BIT_FIELDS_LTOH)
328 			uint32_t ldf_mask:2;
329 			uint32_t res1_1:30;
330 #endif
331 		} ldw;
332 #if !defined(_BIG_ENDIAN)
333 		uint32_t hdw;
334 #endif
335 	} bits;
336 } ld_im_t, *p_ld_im_t;
337 
338 /*
339  * Logical Device Group Interrupt Management
340  */
341 #define	LDGIMGN_REG		(PIO_LDSV + 0x00018)
342 #define	LDGIMGN_TIMER_SHIFT	0
343 #define	LDGIMGM_TIMER_MASK	0x000000000000003FULL
344 #define	LDGIMGN_ARM_SHIFT	31
345 #define	LDGIMGM_ARM		0x0000000080000000ULL
346 #define	LDGIMGM_ARM_MASK	0x0000000080000000ULL
347 
348 typedef union _ldgimgm_t {
349 	uint64_t value;
350 	struct {
351 #if defined(_BIG_ENDIAN)
352 		uint32_t hdw;
353 #endif
354 		struct {
355 #if defined(_BIT_FIELDS_HTOL)
356 		uint32_t arm:1;
357 		uint32_t res2:25;
358 		uint32_t timer:6;
359 #elif defined(_BIT_FIELDS_LTOH)
360 		uint32_t timer:6;
361 		uint32_t res2:25;
362 		uint32_t arm:1;
363 #endif
364 		} ldw;
365 #if !defined(_BIG_ENDIAN)
366 		uint32_t hdw;
367 #endif
368 	} bits;
369 } ldgimgm_t, *p_ldgimgm_t;
370 
371 /*
372  * Logical Device Group Interrupt Timer Resolution
373  */
374 #define	LDGITMRES_REG		(FZC_PIO + 0x00008)
375 #define	LDGTITMRES_RES_SHIFT	0			/* bits 19:0 */
376 #define	LDGTITMRES_RES_MASK	0x00000000000FFFFFULL
377 typedef union _ldgitmres_t {
378 	uint64_t value;
379 	struct {
380 #if defined(_BIG_ENDIAN)
381 		uint32_t hdw;
382 #endif
383 		struct {
384 #if defined(_BIT_FIELDS_HTOL)
385 		uint32_t res1_1:12;
386 		uint32_t res:20;
387 #elif defined(_BIT_FIELDS_LTOH)
388 		uint32_t res:20;
389 		uint32_t res1_1:12;
390 #endif
391 		} ldw;
392 #if !defined(_BIG_ENDIAN)
393 		uint32_t hdw;
394 #endif
395 	} bits;
396 } ldgitmres_t, *p_ldgitmres_t;
397 
398 /*
399  * System Interrupt Data
400  */
401 #define	SID_REG			(FZC_PIO + 0x10200)
402 #define	SID_DATA_SHIFT		0			/* bits 6:0 */
403 #define	SID_DATA_MASK		0x000000000000007FULL
404 #define	SID_DATA_INTNUM_SHIFT	0			/* bits 4:0 */
405 #define	SID_DATA_INTNUM_MASK	0x000000000000001FULL
406 #define	SID_DATA_FUNCNUM_SHIFT	5			/* bits 6:5 */
407 #define	SID_DATA_FUNCNUM_MASK	0x0000000000000060ULL
408 #define	SID_PCI_FUNCTION_SHIFT	(1 << 5)
409 #define	SID_N2_INDEX		(1 << 6)
410 
411 #define	SID_DATA(f, v)		((f << SID_DATA_FUNCNUM_SHIFT) |	\
412 				((v << SID_DATA_SHIFT) & SID_DATA_INTNUM_MASK))
413 
414 #define	SID_DATA_N2(v)		(v | SID_N2_INDEX)
415 
416 typedef union _sid_t {
417 	uint64_t value;
418 	struct {
419 #if defined(_BIG_ENDIAN)
420 		uint32_t hdw;
421 #endif
422 		struct {
423 #if defined(_BIT_FIELDS_HTOL)
424 		uint32_t res1_1:25;
425 		uint32_t data:7;
426 #elif defined(_BIT_FIELDS_LTOH)
427 		uint32_t data:7;
428 		uint32_t res1_1:25;
429 #endif
430 		} ldw;
431 #if !defined(_BIG_ENDIAN)
432 		uint32_t hdw;
433 #endif
434 	} bits;
435 } sid_t, *p_sid_t;
436 
437 /*
438  * Reset Control
439  */
440 #define	RST_CTL_REG		(FZC_PIO + 0x00038)
441 #define	RST_CTL_MAC_RST3	0x0000000000400000ULL
442 #define	RST_CTL_MAC_RST3_SHIFT	22
443 #define	RST_CTL_MAC_RST2	0x0000000000200000ULL
444 #define	RST_CTL_MAC_RST2_SHIFT	21
445 #define	RST_CTL_MAC_RST1	0x0000000000100000ULL
446 #define	RST_CTL_MAC_RST1_SHIFT	20
447 #define	RST_CTL_MAC_RST0	0x0000000000080000ULL
448 #define	RST_CTL_MAC_RST0_SHIFT	19
449 #define	RST_CTL_EN_ACK_TO	0x0000000000000800ULL
450 #define	RST_CTL_EN_ACK_TO_SHIFT	11
451 #define	RST_CTL_ACK_TO_MASK	0x00000000000007FEULL
452 #define	RST_CTL_ACK_TO_SHIFT	1
453 
454 
455 typedef union _rst_ctl_t {
456 	uint64_t value;
457 	struct {
458 #if defined(_BIG_ENDIAN)
459 		uint32_t hdw;
460 #endif
461 		struct {
462 #if defined(_BIT_FIELDS_HTOL)
463 		uint32_t res1:9;
464 		uint32_t mac_rst3:1;
465 		uint32_t mac_rst2:1;
466 		uint32_t mac_rst1:1;
467 		uint32_t mac_rst0:1;
468 		uint32_t res2:7;
469 		uint32_t ack_to_en:1;
470 		uint32_t ack_to_val:10;
471 		uint32_t res3:1;
472 #elif defined(_BIT_FIELDS_LTOH)
473 		uint32_t res3:1;
474 		uint32_t ack_to_val:10;
475 		uint32_t ack_to_en:1;
476 		uint32_t res2:7;
477 		uint32_t mac_rst0:1;
478 		uint32_t mac_rst1:1;
479 		uint32_t mac_rst2:1;
480 		uint32_t mac_rst3:1;
481 		uint32_t res1:9;
482 #endif
483 		} ldw;
484 #if !defined(_BIG_ENDIAN)
485 		uint32_t hdw;
486 #endif
487 	} bits;
488 } rst_ctl_t, *p_rst_ctl_t;
489 
490 /*
491  * System Error Mask
492  */
493 #define	SYS_ERR_MASK_REG	(FZC_PIO + 0x00090)
494 
495 /*
496  * System Error Status
497  */
498 #define	SYS_ERR_STAT_REG	(FZC_PIO + 0x00098)
499 
500 
501 #define	SYS_ERR_META2_MASK	0x0000000000000400ULL
502 #define	SYS_ERR_META2_SHIFT	10
503 #define	SYS_ERR_META1_MASK	0x0000000000000200ULL
504 #define	SYS_ERR_META1_SHIFT	9
505 #define	SYS_ERR_PEU_MASK	0x0000000000000100ULL
506 #define	SYS_ERR_PEU_SHIFT	8
507 #define	SYS_ERR_TXC_MASK	0x0000000000000080ULL
508 #define	SYS_ERR_TXC_SHIFT	7
509 #define	SYS_ERR_RDMC_MASK	0x0000000000000040ULL
510 #define	SYS_ERR_RDMC_SHIFT	6
511 #define	SYS_ERR_TDMC_MASK	0x0000000000000020ULL
512 #define	SYS_ERR_TDMC_SHIFT	5
513 #define	SYS_ERR_ZCP_MASK	0x0000000000000010ULL
514 #define	SYS_ERR_ZCP_SHIFT	4
515 #define	SYS_ERR_FFLP_MASK	0x0000000000000008ULL
516 #define	SYS_ERR_FFLP_SHIFT	3
517 #define	SYS_ERR_IPP_MASK	0x0000000000000004ULL
518 #define	SYS_ERR_IPP_SHIFT	2
519 #define	SYS_ERR_MAC_MASK	0x0000000000000002ULL
520 #define	SYS_ERR_MAC_SHIFT	1
521 #define	SYS_ERR_SMX_MASK	0x0000000000000001ULL
522 #define	SYS_ERR_SMX_SHIFT	0
523 #define	SYS_ERR_MASK_ALL	(SYS_ERR_SMX_MASK | SYS_ERR_MAC_MASK | \
524 				SYS_ERR_IPP_MASK | SYS_ERR_FFLP_MASK | \
525 				SYS_ERR_ZCP_MASK | SYS_ERR_TDMC_MASK | \
526 				SYS_ERR_RDMC_MASK | SYS_ERR_TXC_MASK | \
527 				SYS_ERR_PEU_MASK | SYS_ERR_META1_MASK | \
528 				SYS_ERR_META2_MASK)
529 
530 
531 typedef union _sys_err_mask_t {
532 	uint64_t value;
533 	struct {
534 #if defined(_BIG_ENDIAN)
535 		uint32_t hdw;
536 #endif
537 		struct {
538 #if defined(_BIT_FIELDS_HTOL)
539 		uint32_t res:21;
540 		uint32_t meta2:1;
541 		uint32_t meta1:1;
542 		uint32_t peu:1;
543 		uint32_t txc:1;
544 		uint32_t rdmc:1;
545 		uint32_t tdmc:1;
546 		uint32_t zcp:1;
547 		uint32_t fflp:1;
548 		uint32_t ipp:1;
549 		uint32_t mac:1;
550 		uint32_t smx:1;
551 #elif defined(_BIT_FIELDS_LTOH)
552 		uint32_t smx:1;
553 		uint32_t mac:1;
554 		uint32_t ipp:1;
555 		uint32_t fflp:1;
556 		uint32_t zcp:1;
557 		uint32_t tdmc:1;
558 		uint32_t rdmc:1;
559 		uint32_t txc:1;
560 		uint32_t peu:1;
561 		uint32_t meta1:1;
562 		uint32_t meta2:1;
563 		uint32_t res:21;
564 #endif
565 		} ldw;
566 #if !defined(_BIG_ENDIAN)
567 		uint32_t hdw;
568 #endif
569 	} bits;
570 } sys_err_mask_t, sys_err_stat_t, *p_sys_err_mask_t, *p_sys_err_stat_t;
571 
572 
573 /*
574  * Meta Arbiter Dirty Transaction ID Control
575  */
576 
577 #define	DIRTY_TID_CTL_REG		(FZC_PIO + 0x0010)
578 #define	DIRTY_TID_CTL_WR_THRES_MASK	0x00000000003F0000ULL
579 #define	DIRTY_TID_CTL_WR_THRES_SHIFT    16
580 #define	DIRTY_TID_CTL_RD_THRES_MASK	0x00000000000003F0ULL
581 #define	DIRTY_TID_CTL_RD_THRES_SHIFT	4
582 #define	DIRTY_TID_CTL_DTID_CLR		0x0000000000000002ULL
583 #define	DIRTY_TID_CTL_DTID_CLR_SHIFT	1
584 #define	DIRTY_TID_CTL_DTID_EN		0x0000000000000001ULL
585 #define	DIRTY_TID_CTL_DTID_EN_SHIFT	0
586 
587 typedef union _dty_tid_ctl_t {
588 	uint64_t value;
589 	struct {
590 #if defined(_BIG_ENDIAN)
591 		uint32_t hdw;
592 #endif
593 		struct {
594 #if defined(_BIT_FIELDS_HTOL)
595 		uint32_t res1:10;
596 		uint32_t np_wr_thres_val:6;
597 		uint32_t res2:6;
598 		uint32_t np_rd_thres_val:6;
599 		uint32_t res3:2;
600 		uint32_t dty_tid_clr:1;
601 		uint32_t dty_tid_en:1;
602 #elif defined(_BIT_FIELDS_LTOH)
603 		uint32_t dty_tid_en:1;
604 		uint32_t dty_tid_clr:1;
605 		uint32_t res3:2;
606 		uint32_t np_rd_thres_val:6;
607 		uint32_t res2:6;
608 		uint32_t np_wr_thres_val:6;
609 		uint32_t res1:10;
610 #endif
611 		} ldw;
612 #if !defined(_BIG_ENDIAN)
613 		uint32_t hdw;
614 #endif
615 	} bits;
616 } dty_tid_ctl_t, *p_dty_tid_ctl_t;
617 
618 
619 /*
620  * Meta Arbiter Dirty Transaction ID Status
621  */
622 #define	DIRTY_TID_STAT_REG			(FZC_PIO + 0x0018)
623 #define	DIRTY_TID_STAT_WR_TID_DTY_CNT_MASK	0x0000000000003F00ULL
624 #define	DIRTY_TID_STAT_WR_TID_DTY_CNT_SHIFT	8
625 #define	DIRTY_TID_STAT_RD_TID_DTY_CNT_MASK	0x000000000000003FULL
626 #define	DIRTY_TID_STAT_RD_TID_DTY_CNT_SHIFT	0
627 
628 typedef union _dty_tid_stat_t {
629 	uint64_t value;
630 	struct {
631 #if defined(_BIG_ENDIAN)
632 		uint32_t hdw;
633 #endif
634 		struct {
635 #if defined(_BIT_FIELDS_HTOL)
636 		uint32_t res1:18;
637 		uint32_t wr_tid_dirty_cnt:6;
638 		uint32_t res2:2;
639 		uint32_t rd_tid_dirty_cnt:6;
640 #elif defined(_BIT_FIELDS_LTOH)
641 		uint32_t rd_tid_dirty_cnt:6;
642 		uint32_t res2:2;
643 		uint32_t wr_tid_dirty_cnt:6;
644 		uint32_t res1:18;
645 #endif
646 		} ldw;
647 #if !defined(_BIG_ENDIAN)
648 		uint32_t hdw;
649 #endif
650 	} bits;
651 } dty_tid_stat_t, *p_dty_tid_stat_t;
652 
653 
654 /*
655  * SMX Registers
656  */
657 #define	SMX_CFIG_DAT_REG		(FZC_PIO + 0x00040)
658 #define	SMX_CFIG_DAT_RAS_DET_EN_MASK	0x0000000080000000ULL
659 #define	SMX_CFIG_DAT_RAS_DET_EN_SHIFT	31
660 #define	SMX_CFIG_DAT_RAS_INJ_EN_MASK	0x0000000040000000ULL
661 #define	SMX_CFIG_DAT_RAS_INJ_EN_SHIFT	30
662 #define	SMX_CFIG_DAT_TRANS_TO_MASK	0x000000000FFFFFFFULL
663 #define	SMX_CFIG_DAT_TRANS_TO_SHIFT	0
664 
665 typedef union _smx_cfg_dat_t {
666 	uint64_t value;
667 	struct {
668 #if defined(_BIG_ENDIAN)
669 		uint32_t hdw;
670 #endif
671 		struct {
672 #if defined(_BIT_FIELDS_HTOL)
673 		uint32_t res_err_det:1;
674 		uint32_t ras_err_inj_en:1;
675 		uint32_t res:2;
676 		uint32_t trans_to_val:28;
677 #elif defined(_BIT_FIELDS_LTOH)
678 		uint32_t trans_to_val:28;
679 		uint32_t res:2;
680 		uint32_t ras_err_inj_en:1;
681 		uint32_t res_err_det:1;
682 #endif
683 		} ldw;
684 #if !defined(_BIG_ENDIAN)
685 		uint32_t hdw;
686 #endif
687 	} bits;
688 } smx_cfg_dat_t, *p_smx_cfg_dat_t;
689 
690 
691 #define	SMX_INT_STAT_REG	(FZC_PIO + 0x00048)
692 #define	SMX_INT_STAT_SM_MASK	0x00000000FFFFFFC0ULL
693 #define	SMX_INT_STAT_SM_SHIFT	6
694 
695 typedef union _smx_int_stat_t {
696 	uint64_t value;
697 	struct {
698 #if defined(_BIG_ENDIAN)
699 		uint32_t hdw;
700 #endif
701 		struct {
702 #if defined(_BIT_FIELDS_HTOL)
703 		uint32_t st_mc_stat:26;
704 		uint32_t res:6;
705 #elif defined(_BIT_FIELDS_LTOH)
706 		uint32_t res:6;
707 		uint32_t st_mc_stat:26;
708 #endif
709 		} ldw;
710 #if !defined(_BIG_ENDIAN)
711 		uint32_t hdw;
712 #endif
713 	} bits;
714 } smx_int_stat_t, *p_smx_int_stat_t;
715 
716 
717 #define		SMX_CTL_REG	(FZC_PIO + 0x00050)
718 
719 typedef union _smx_ctl_t {
720 	uint64_t value;
721 	struct {
722 #if defined(_BIG_ENDIAN)
723 		uint32_t hdw;
724 #endif
725 		struct {
726 #if defined(_BIT_FIELDS_HTOL)
727 		uint32_t res1:21;
728 		uint32_t resp_err_inj:3;
729 		uint32_t res2:1;
730 		uint32_t xtb_err_inj:3;
731 		uint32_t res3:1;
732 		uint32_t dbg_sel:3;
733 #elif defined(_BIT_FIELDS_LTOH)
734 		uint32_t dbg_sel:3;
735 		uint32_t res3:1;
736 		uint32_t xtb_err_inj:3;
737 		uint32_t res2:1;
738 		uint32_t resp_err_inj:3;
739 		uint32_t res1:21;
740 #endif
741 		} ldw;
742 #if !defined(_BIG_ENDIAN)
743 		uint32_t hdw;
744 #endif
745 	} bits;
746 } smx_ctl_t, *p_smx_ctl_t;
747 
748 
749 #define	SMX_DBG_VEC_REG	(FZC_PIO + 0x00058)
750 
751 typedef union _smx_dbg_vec_t {
752 	uint64_t value;
753 	struct {
754 #if defined(_BIG_ENDIAN)
755 		uint32_t hdw;
756 #endif
757 		struct {
758 		uint32_t dbg_tng_vec;
759 		} ldw;
760 #if !defined(_BIG_ENDIAN)
761 		uint32_t hdw;
762 #endif
763 	} bits;
764 } smx_dbg_vec_t, *p_smx_dbg_vec_t;
765 
766 
767 /*
768  * Debug registers
769  */
770 
771 #define	PIO_DBG_SEL_REG	(FZC_PIO + 0x00060)
772 
773 typedef union _pio_dbg_sel_t {
774 	uint64_t value;
775 	struct {
776 #if defined(_BIG_ENDIAN)
777 		uint32_t hdw;
778 #endif
779 		struct {
780 		uint32_t sel;
781 		} ldw;
782 #if !defined(_BIG_ENDIAN)
783 		uint32_t hdw;
784 #endif
785 	} bits;
786 } pio_dbg_sel_t, *p_pio_dbg_sel_t;
787 
788 
789 #define	PIO_TRAIN_VEC_REG	(FZC_PIO + 0x00068)
790 
791 typedef union _pio_tng_vec_t {
792 	uint64_t value;
793 	struct {
794 #if defined(_BIG_ENDIAN)
795 		uint32_t hdw;
796 #endif
797 		struct {
798 		uint32_t training_vec;
799 		} ldw;
800 #if !defined(_BIG_ENDIAN)
801 		uint32_t hdw;
802 #endif
803 	} bits;
804 } pio_tng_vec_t, *p_pio_tng_vec_t;
805 
806 #define	PIO_ARB_CTL_REG	(FZC_PIO + 0x00070)
807 
808 typedef union _pio_arb_ctl_t {
809 	uint64_t value;
810 	struct {
811 #if defined(_BIG_ENDIAN)
812 		uint32_t hdw;
813 #endif
814 		struct {
815 		uint32_t ctl;
816 		} ldw;
817 #if !defined(_BIG_ENDIAN)
818 		uint32_t hdw;
819 #endif
820 	} bits;
821 } pio_arb_ctl_t, *p_pio_arb_ctl_t;
822 
823 #define	PIO_ARB_DBG_VEC_REG	(FZC_PIO + 0x00078)
824 
825 typedef union _pio_arb_dbg_vec_t {
826 	uint64_t value;
827 	struct {
828 #if defined(_BIG_ENDIAN)
829 		uint32_t hdw;
830 #endif
831 		struct {
832 		uint32_t dbg_vector;
833 		} ldw;
834 #if !defined(_BIG_ENDIAN)
835 		uint32_t hdw;
836 #endif
837 	} bits;
838 } pio_arb_dbg_vec_t, *p_pio_arb_dbg_vec_t;
839 
840 
841 /*
842  * GPIO Registers
843  */
844 
845 #define	GPIO_EN_REG	(FZC_PIO + 0x00028)
846 #define	GPIO_EN_ENABLE_MASK	 0x000000000000FFFFULL
847 #define	GPIO_EN_ENABLE_SHIFT	 0
848 typedef union _gpio_en_t {
849 	uint64_t value;
850 	struct {
851 #if defined(_BIG_ENDIAN)
852 		uint32_t hdw;
853 #endif
854 		struct {
855 #if defined(_BIT_FIELDS_HTOL)
856 		uint32_t res:16;
857 		uint32_t enable:16;
858 #elif defined(_BIT_FIELDS_LTOH)
859 		uint32_t enable:16;
860 		uint32_t res:16;
861 #endif
862 		} ldw;
863 #if !defined(_BIG_ENDIAN)
864 		uint32_t hdw;
865 #endif
866 	} bits;
867 } gpio_en_t, *p_gpio_en_t;
868 
869 #define	GPIO_DATA_IN_REG	(FZC_PIO + 0x00030)
870 #define	GPIO_DATA_IN_MASK	0x000000000000FFFFULL
871 #define	GPIO_DATA_IN_SHIFT	0
872 typedef union _gpio_data_in_t {
873 	uint64_t value;
874 	struct {
875 #if defined(_BIG_ENDIAN)
876 		uint32_t hdw;
877 #endif
878 		struct {
879 #if defined(_BIT_FIELDS_HTOL)
880 		uint32_t res:16;
881 		uint32_t data_in:16;
882 #elif defined(_BIT_FIELDS_LTOH)
883 		uint32_t data_in:16;
884 		uint32_t res:16;
885 #endif
886 		} ldw;
887 #if !defined(_BIG_ENDIAN)
888 		uint32_t hdw;
889 #endif
890 	} bits;
891 } gpio_data_in_t, *p_gpio_data_in_t;
892 
893 
894 /*
895  * PCI Express Interface Module (PIM) registers
896  */
897 #define	PIM_CONTROL_REG	(FZC_PIM + 0x0)
898 #define	PIM_CONTROL_DBG_SEL_MASK 0x000000000000000FULL
899 #define	PIM_CONTROL_DBG_SEL_SHIFT	0
900 typedef union _pim_ctl_t {
901 	uint64_t value;
902 	struct {
903 #if defined(_BIG_ENDIAN)
904 		uint32_t hdw;
905 #endif
906 		struct {
907 #if defined(_BIT_FIELDS_HTOL)
908 		uint32_t res:28;
909 		uint32_t dbg_sel:4;
910 #elif defined(_BIT_FIELDS_LTOH)
911 		uint32_t dbg_sel:4;
912 		uint32_t res:28;
913 #endif
914 		} ldw;
915 #if !defined(_BIG_ENDIAN)
916 		uint32_t hdw;
917 #endif
918 	} bits;
919 } pim_ctl_t, *p_pim_ctl_t;
920 
921 #define	PIM_DBG_TRAINING_VEC_REG	(FZC_PIM + 0x00008)
922 #define	PIM_DBG_TRAINING_VEC_MASK	0x00000000FFFFFFFFULL
923 
924 #define	PIM_INTR_STATUS_REG		(FZC_PIM + 0x00010)
925 #define	PIM_INTR_STATUS_MASK		0x00000000FFFFFFFFULL
926 
927 #define	PIM_INTERNAL_STATUS_REG		(FZC_PIM + 0x00018)
928 #define	PIM_INTERNAL_STATUS_MASK	0x00000000FFFFFFFFULL
929 
930 #define	PIM_INTR_MASK_REG		(FZC_PIM + 0x00020)
931 #define	PIM_INTR_MASK_MASK		0x00000000FFFFFFFFULL
932 
933 /*
934  * Partitioning Logical pages Definition registers.
935  * (used by both receive and transmit DMA channels)
936  */
937 
938 /* Logical page definitions */
939 typedef union _log_page_vld_t {
940 	uint64_t value;
941 	struct {
942 #if defined(_BIG_ENDIAN)
943 		uint32_t hdw;
944 #endif
945 		struct {
946 #if defined(_BIT_FIELDS_HTOL)
947 			uint32_t res1_1:28;
948 			uint32_t func:2;
949 			uint32_t page1:1;
950 			uint32_t page0:1;
951 #elif defined(_BIT_FIELDS_LTOH)
952 			uint32_t page0:1;
953 			uint32_t page1:1;
954 			uint32_t func:2;
955 			uint32_t res1_1:28;
956 #endif
957 		} ldw;
958 #if !defined(_BIG_ENDIAN)
959 		uint32_t hdw;
960 #endif
961 	} bits;
962 } log_page_vld_t, *p_log_page_vld_t;
963 
964 
965 #define	DMA_LOG_PAGE_MASK_SHIFT		0
966 #define	DMA_LOG_PAGE_MASK_MASK		0x00000000ffffffffULL
967 
968 /* Receive Logical Page Mask */
969 typedef union _log_page_mask_t {
970 	uint64_t value;
971 	struct {
972 #if defined(_BIG_ENDIAN)
973 		uint32_t hdw;
974 #endif
975 		struct {
976 #if defined(_BIT_FIELDS_HTOL)
977 			uint32_t mask:32;
978 #elif defined(_BIT_FIELDS_LTOH)
979 			uint32_t mask:32;
980 #endif
981 		} ldw;
982 #if !defined(_BIG_ENDIAN)
983 		uint32_t hdw;
984 #endif
985 	} bits;
986 } log_page_mask_t, *p_log_page_mask_t;
987 
988 
989 /* Receive Logical Page Value */
990 #define	DMA_LOG_PAGE_VALUE_SHIFT	0
991 #define	DMA_LOG_PAGE_VALUE_MASK		0x00000000ffffffffULL
992 
993 /* Receive Logical Page Value */
994 typedef union _log_page_value_t {
995 	uint64_t value;
996 	struct {
997 #if defined(_BIG_ENDIAN)
998 		uint32_t hdw;
999 #endif
1000 		struct {
1001 #if defined(_BIT_FIELDS_HTOL)
1002 			uint32_t value:32;
1003 #elif defined(_BIT_FIELDS_LTOH)
1004 			uint32_t value:32;
1005 #endif
1006 		} ldw;
1007 #if !defined(_BIG_ENDIAN)
1008 		uint32_t hdw;
1009 #endif
1010 	} bits;
1011 } log_page_value_t, *p_log_page_value_t;
1012 
1013 /* Receive Logical Page Relocation */
1014 #define	DMA_LOG_PAGE_RELO_SHIFT		0			/* bits 31:0 */
1015 #define	DMA_LOG_PAGE_RELO_MASK		0x00000000ffffffffULL
1016 
1017 /* Receive Logical Page Relocation */
1018 typedef union _log_page_relo_t {
1019 	uint64_t value;
1020 	struct {
1021 #if defined(_BIG_ENDIAN)
1022 		uint32_t hdw;
1023 #endif
1024 		struct {
1025 #if defined(_BIT_FIELDS_HTOL)
1026 			uint32_t relo:32;
1027 #elif defined(_BIT_FIELDS_LTOH)
1028 			uint32_t relo:32;
1029 #endif
1030 		} ldw;
1031 #if !defined(_BIG_ENDIAN)
1032 		uint32_t hdw;
1033 #endif
1034 	} bits;
1035 } log_page_relo_t, *p_log_page_relo_t;
1036 
1037 
1038 /* Receive Logical Page Handle */
1039 #define	DMA_LOG_PAGE_HANDLE_SHIFT	0			/* bits 19:0 */
1040 #define	DMA_LOG_PAGE_HANDLE_MASK	0x00000000ffffffffULL
1041 
1042 /* Receive Logical Page Handle */
1043 typedef union _log_page_hdl_t {
1044 	uint64_t value;
1045 	struct {
1046 #if defined(_BIG_ENDIAN)
1047 		uint32_t hdw;
1048 #endif
1049 		struct {
1050 #if defined(_BIT_FIELDS_HTOL)
1051 			uint32_t res1_1:12;
1052 			uint32_t handle:20;
1053 #elif defined(_BIT_FIELDS_LTOH)
1054 			uint32_t handle:20;
1055 			uint32_t res1_1:12;
1056 #endif
1057 		} ldw;
1058 #if !defined(_BIG_ENDIAN)
1059 		uint32_t hdw;
1060 #endif
1061 	} bits;
1062 } log_page_hdl_t, *p_log_page_hdl_t;
1063 
1064 #ifdef	__cplusplus
1065 }
1066 #endif
1067 
1068 #endif	/* _SYS_NXGE_NXGE_HW_H */
1069