144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
21*330cd344SMichael Speer 
2244961713Sgirish /*
23678453a8Sspeer  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
2444961713Sgirish  * Use is subject to license terms.
2544961713Sgirish  */
2644961713Sgirish 
2744961713Sgirish #ifndef	_SYS_NXGE_NXGE_COMMON_IMPL_H
2844961713Sgirish #define	_SYS_NXGE_NXGE_COMMON_IMPL_H
2944961713Sgirish 
3044961713Sgirish #ifdef	__cplusplus
3144961713Sgirish extern "C" {
3244961713Sgirish #endif
3344961713Sgirish 
3444961713Sgirish #define	NPI_REGH(npi_handle)		(npi_handle.regh)
3544961713Sgirish #define	NPI_REGP(npi_handle)		(npi_handle.regp)
3644961713Sgirish 
3744961713Sgirish #if defined(NXGE_DEBUG_DMA) || defined(NXGE_DEBUG_TXC)
3844961713Sgirish #define	__NXGE_STATIC
3944961713Sgirish #define	__NXGE_INLINE
4044961713Sgirish #else
4144961713Sgirish #define	__NXGE_STATIC			static
4244961713Sgirish #define	__NXGE_INLINE			inline
4344961713Sgirish #endif
4444961713Sgirish 
4544961713Sgirish #ifdef	AXIS_DEBUG
4644961713Sgirish #define	AXIS_WAIT			(100000)
4744961713Sgirish #define	AXIS_LONG_WAIT			(100000)
4844961713Sgirish #define	AXIS_WAIT_W			(80000)
4944961713Sgirish #define	AXIS_WAIT_R			(100000)
5044961713Sgirish #define	AXIS_WAIT_LOOP			(4000)
5144961713Sgirish #define	AXIS_WAIT_PER_LOOP		(AXIS_WAIT_R/AXIS_WAIT_LOOP)
5244961713Sgirish #endif
5344961713Sgirish 
5414ea4bb7Ssd #define	NO_DEBUG	0x0000000000000000ULL
5514ea4bb7Ssd #define	MDT_CTL		0x0000000000000001ULL
5614ea4bb7Ssd #define	RX_CTL		0x0000000000000002ULL
5714ea4bb7Ssd #define	TX_CTL		0x0000000000000004ULL
5814ea4bb7Ssd #define	OBP_CTL		0x0000000000000008ULL
5944961713Sgirish 
6014ea4bb7Ssd #define	VPD_CTL		0x0000000000000010ULL
6114ea4bb7Ssd #define	DDI_CTL		0x0000000000000020ULL
6214ea4bb7Ssd #define	MEM_CTL		0x0000000000000040ULL
6314ea4bb7Ssd #define	SAP_CTL		0x0000000000000080ULL
6444961713Sgirish 
6514ea4bb7Ssd #define	IOC_CTL		0x0000000000000100ULL
6614ea4bb7Ssd #define	MOD_CTL		0x0000000000000200ULL
6714ea4bb7Ssd #define	DMA_CTL		0x0000000000000400ULL
6814ea4bb7Ssd #define	STR_CTL		0x0000000000000800ULL
6944961713Sgirish 
7014ea4bb7Ssd #define	INT_CTL		0x0000000000001000ULL
7114ea4bb7Ssd #define	SYSERR_CTL	0x0000000000002000ULL
7214ea4bb7Ssd #define	KST_CTL		0x0000000000004000ULL
7314ea4bb7Ssd #define	PCS_CTL		0x0000000000008000ULL
7444961713Sgirish 
7514ea4bb7Ssd #define	MII_CTL		0x0000000000010000ULL
7614ea4bb7Ssd #define	MIF_CTL		0x0000000000020000ULL
7714ea4bb7Ssd #define	FCRAM_CTL	0x0000000000040000ULL
7814ea4bb7Ssd #define	MAC_CTL		0x0000000000080000ULL
7944961713Sgirish 
8014ea4bb7Ssd #define	IPP_CTL		0x0000000000100000ULL
8114ea4bb7Ssd #define	DMA2_CTL	0x0000000000200000ULL
8214ea4bb7Ssd #define	RX2_CTL		0x0000000000400000ULL
8314ea4bb7Ssd #define	TX2_CTL		0x0000000000800000ULL
8444961713Sgirish 
8514ea4bb7Ssd #define	MEM2_CTL	0x0000000001000000ULL
8614ea4bb7Ssd #define	MEM3_CTL	0x0000000002000000ULL
8714ea4bb7Ssd #define	NXGE_CTL	0x0000000004000000ULL
8814ea4bb7Ssd #define	NDD_CTL		0x0000000008000000ULL
8914ea4bb7Ssd #define	NDD2_CTL	0x0000000010000000ULL
9044961713Sgirish 
9114ea4bb7Ssd #define	TCAM_CTL	0x0000000020000000ULL
9214ea4bb7Ssd #define	CFG_CTL		0x0000000040000000ULL
9314ea4bb7Ssd #define	CFG2_CTL	0x0000000080000000ULL
9444961713Sgirish 
9514ea4bb7Ssd #define	FFLP_CTL	TCAM_CTL | FCRAM_CTL
9644961713Sgirish 
9714ea4bb7Ssd #define	VIR_CTL		0x0000000100000000ULL
9814ea4bb7Ssd #define	VIR2_CTL	0x0000000200000000ULL
9944961713Sgirish 
100678453a8Sspeer #define	HIO_CTL		0x0000000400000000ULL
101678453a8Sspeer 
10214ea4bb7Ssd #define	NXGE_NOTE	0x0000001000000000ULL
10314ea4bb7Ssd #define	NXGE_ERR_CTL	0x0000002000000000ULL
10444961713Sgirish 
10514ea4bb7Ssd #define	DUMP_ALWAYS	0x2000000000000000ULL
10644961713Sgirish 
10744961713Sgirish /* NPI Debug and Error defines */
10814ea4bb7Ssd #define	NPI_RDC_CTL	0x0000000000000001ULL
10914ea4bb7Ssd #define	NPI_TDC_CTL	0x0000000000000002ULL
11014ea4bb7Ssd #define	NPI_TXC_CTL	0x0000000000000004ULL
11114ea4bb7Ssd #define	NPI_IPP_CTL	0x0000000000000008ULL
11244961713Sgirish 
11314ea4bb7Ssd #define	NPI_XPCS_CTL	0x0000000000000010ULL
11414ea4bb7Ssd #define	NPI_PCS_CTL	0x0000000000000020ULL
11514ea4bb7Ssd #define	NPI_ESR_CTL	0x0000000000000040ULL
11614ea4bb7Ssd #define	NPI_BMAC_CTL	0x0000000000000080ULL
11714ea4bb7Ssd #define	NPI_XMAC_CTL	0x0000000000000100ULL
11814ea4bb7Ssd #define	NPI_MAC_CTL	NPI_BMAC_CTL | NPI_XMAC_CTL
11944961713Sgirish 
12014ea4bb7Ssd #define	NPI_ZCP_CTL	0x0000000000000200ULL
12114ea4bb7Ssd #define	NPI_TCAM_CTL	0x0000000000000400ULL
12214ea4bb7Ssd #define	NPI_FCRAM_CTL	0x0000000000000800ULL
12314ea4bb7Ssd #define	NPI_FFLP_CTL	NPI_TCAM_CTL | NPI_FCRAM_CTL
12444961713Sgirish 
12514ea4bb7Ssd #define	NPI_VIR_CTL	0x0000000000001000ULL
12614ea4bb7Ssd #define	NPI_PIO_CTL	0x0000000000002000ULL
12714ea4bb7Ssd #define	NPI_VIO_CTL	0x0000000000004000ULL
12844961713Sgirish 
12914ea4bb7Ssd #define	NPI_REG_CTL	0x0000000040000000ULL
13014ea4bb7Ssd #define	NPI_CTL		0x0000000080000000ULL
13114ea4bb7Ssd #define	NPI_ERR_CTL	0x0000000080000000ULL
13244961713Sgirish 
13344961713Sgirish #include <sys/types.h>
13444961713Sgirish #include <sys/ddi.h>
13544961713Sgirish #include <sys/sunddi.h>
13644961713Sgirish #include <sys/dditypes.h>
13744961713Sgirish #include <sys/ethernet.h>
13844961713Sgirish 
13944961713Sgirish #ifdef NXGE_DEBUG
14044961713Sgirish #define	NXGE_DEBUG_MSG(params) nxge_debug_msg params
14144961713Sgirish #else
14244961713Sgirish #define	NXGE_DEBUG_MSG(params)
14344961713Sgirish #endif
14444961713Sgirish 
14544961713Sgirish #define	NXGE_ERROR_MSG(params)	nxge_debug_msg params
14644961713Sgirish #define	NXGE_WARN_MSG(params)	nxge_debug_msg params
14744961713Sgirish 
14844961713Sgirish typedef kmutex_t			nxge_os_mutex_t;
14944961713Sgirish typedef	krwlock_t			nxge_os_rwlock_t;
15044961713Sgirish 
15144961713Sgirish typedef	dev_info_t			nxge_dev_info_t;
15244961713Sgirish typedef	ddi_iblock_cookie_t 		nxge_intr_cookie_t;
15344961713Sgirish 
15444961713Sgirish typedef ddi_acc_handle_t		nxge_os_acc_handle_t;
15544961713Sgirish typedef	nxge_os_acc_handle_t		npi_reg_handle_t;
156adfcba55Sjoycey #if defined(__i386)
157adfcba55Sjoycey typedef	uint32_t			npi_reg_ptr_t;
158adfcba55Sjoycey #else
159adfcba55Sjoycey typedef uint64_t			npi_reg_ptr_t;
160adfcba55Sjoycey #endif
16144961713Sgirish 
16244961713Sgirish typedef ddi_dma_handle_t		nxge_os_dma_handle_t;
16344961713Sgirish typedef struct _nxge_dma_common_t	nxge_os_dma_common_t;
16444961713Sgirish typedef struct _nxge_block_mv_t		nxge_os_block_mv_t;
16544961713Sgirish typedef frtn_t				nxge_os_frtn_t;
16644961713Sgirish 
16744961713Sgirish #define	NXGE_MUTEX_DRIVER		MUTEX_DRIVER
16814ea4bb7Ssd #define	MUTEX_INIT(lock, name, type, arg) \
16914ea4bb7Ssd 	mutex_init(lock, name, type, arg)
17044961713Sgirish #define	MUTEX_ENTER(lock)		mutex_enter(lock)
17144961713Sgirish #define	MUTEX_TRY_ENTER(lock)		mutex_tryenter(lock)
17244961713Sgirish #define	MUTEX_EXIT(lock)		mutex_exit(lock)
17344961713Sgirish #define	MUTEX_DESTROY(lock)		mutex_destroy(lock)
17444961713Sgirish 
17544961713Sgirish #define	RW_INIT(lock, name, type, arg)	rw_init(lock, name, type, arg)
17644961713Sgirish #define	RW_ENTER_WRITER(lock)		rw_enter(lock, RW_WRITER)
17744961713Sgirish #define	RW_ENTER_READER(lock)		rw_enter(lock, RW_READER)
17844961713Sgirish #define	RW_TRY_ENTER(lock, type)	rw_tryenter(lock, type)
17944961713Sgirish #define	RW_EXIT(lock)			rw_exit(lock)
18044961713Sgirish #define	RW_DESTROY(lock)		rw_destroy(lock)
18144961713Sgirish #define	KMEM_ALLOC(size, flag)		kmem_alloc(size, flag)
18244961713Sgirish #define	KMEM_ZALLOC(size, flag)		kmem_zalloc(size, flag)
18344961713Sgirish #define	KMEM_FREE(buf, size)		kmem_free(buf, size)
18444961713Sgirish 
18544961713Sgirish #define	NXGE_DELAY(microseconds)	 (drv_usecwait(microseconds))
18644961713Sgirish 
18714ea4bb7Ssd #define	NXGE_PIO_READ8(handle, devaddr, offset) \
18844961713Sgirish 	(ddi_get8(handle, (uint8_t *)((caddr_t)devaddr + offset)))
18944961713Sgirish 
19014ea4bb7Ssd #define	NXGE_PIO_READ16(handle, devaddr, offset) \
19144961713Sgirish 	(ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset)))
19244961713Sgirish 
19314ea4bb7Ssd #define	NXGE_PIO_READ32(handle, devaddr, offset) \
19444961713Sgirish 	(ddi_get32(handle, (uint32_t *)((caddr_t)devaddr + offset)))
19544961713Sgirish 
19614ea4bb7Ssd #define	NXGE_PIO_READ64(handle, devaddr, offset) \
19744961713Sgirish 	(ddi_get64(handle, (uint64_t *)((caddr_t)devaddr + offset)))
19844961713Sgirish 
19914ea4bb7Ssd #define	NXGE_PIO_WRITE8(handle, devaddr, offset, data) \
20044961713Sgirish 	(ddi_put8(handle, (uint8_t *)((caddr_t)devaddr + offset), data))
20144961713Sgirish 
20214ea4bb7Ssd #define	NXGE_PIO_WRITE16(handle, devaddr, offset, data) \
20344961713Sgirish 	(ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset), data))
20444961713Sgirish 
20544961713Sgirish #define	NXGE_PIO_WRITE32(handle, devaddr, offset, data)	\
20644961713Sgirish 	(ddi_put32(handle, (uint32_t *)((caddr_t)devaddr + offset), data))
20744961713Sgirish 
20814ea4bb7Ssd #define	NXGE_PIO_WRITE64(handle, devaddr, offset, data) \
20944961713Sgirish 	(ddi_put64(handle, (uint64_t *)((caddr_t)devaddr + offset), data))
21044961713Sgirish 
21114ea4bb7Ssd #define	NXGE_NPI_PIO_READ8(npi_handle, offset) \
21214ea4bb7Ssd 	(ddi_get8(NPI_REGH(npi_handle),	\
21344961713Sgirish 	(uint8_t *)(NPI_REGP(npi_handle) + offset)))
21444961713Sgirish 
21514ea4bb7Ssd #define	NXGE_NPI_PIO_READ16(npi_handle, offset) \
21614ea4bb7Ssd 	(ddi_get16(NPI_REGH(npi_handle), \
21744961713Sgirish 	(uint16_t *)(NPI_REGP(npi_handle) + offset)))
21844961713Sgirish 
21914ea4bb7Ssd #define	NXGE_NPI_PIO_READ32(npi_handle, offset) \
22014ea4bb7Ssd 	(ddi_get32(NPI_REGH(npi_handle), \
22144961713Sgirish 	(uint32_t *)(NPI_REGP(npi_handle) + offset)))
22244961713Sgirish 
223adfcba55Sjoycey #if defined(__i386)
224adfcba55Sjoycey #define	NXGE_NPI_PIO_READ64(npi_handle, offset)		\
225adfcba55Sjoycey 	(ddi_get64(NPI_REGH(npi_handle),		\
226adfcba55Sjoycey 	(uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset)))
227adfcba55Sjoycey #else
22844961713Sgirish #define	NXGE_NPI_PIO_READ64(npi_handle, offset)		\
22944961713Sgirish 	(ddi_get64(NPI_REGH(npi_handle),		\
23044961713Sgirish 	(uint64_t *)(NPI_REGP(npi_handle) + offset)))
231adfcba55Sjoycey #endif
23244961713Sgirish 
23344961713Sgirish #define	NXGE_NPI_PIO_WRITE8(npi_handle, offset, data)	\
23444961713Sgirish 	(ddi_put8(NPI_REGH(npi_handle),			\
23544961713Sgirish 	(uint8_t *)(NPI_REGP(npi_handle) + offset), data))
23644961713Sgirish 
23744961713Sgirish #define	NXGE_NPI_PIO_WRITE16(npi_handle, offset, data)	\
23844961713Sgirish 	(ddi_put16(NPI_REGH(npi_handle),		\
23944961713Sgirish 	(uint16_t *)(NPI_REGP(npi_handle) + offset), data))
24044961713Sgirish 
24144961713Sgirish #define	NXGE_NPI_PIO_WRITE32(npi_handle, offset, data)	\
24244961713Sgirish 	(ddi_put32(NPI_REGH(npi_handle),		\
24344961713Sgirish 	(uint32_t *)(NPI_REGP(npi_handle) + offset), data))
24444961713Sgirish 
245adfcba55Sjoycey #if defined(__i386)
246adfcba55Sjoycey #define	NXGE_NPI_PIO_WRITE64(npi_handle, offset, data)	\
247adfcba55Sjoycey 	(ddi_put64(NPI_REGH(npi_handle),		\
248adfcba55Sjoycey 	(uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset), data))
249adfcba55Sjoycey #else
25044961713Sgirish #define	NXGE_NPI_PIO_WRITE64(npi_handle, offset, data)	\
25144961713Sgirish 	(ddi_put64(NPI_REGH(npi_handle),		\
25244961713Sgirish 	(uint64_t *)(NPI_REGP(npi_handle) + offset), data))
253adfcba55Sjoycey #endif
25444961713Sgirish 
25544961713Sgirish #define	NXGE_MEM_PIO_READ8(npi_handle)		\
25644961713Sgirish 	(ddi_get8(NPI_REGH(npi_handle), (uint8_t *)NPI_REGP(npi_handle)))
25744961713Sgirish 
25844961713Sgirish #define	NXGE_MEM_PIO_READ16(npi_handle)		\
25944961713Sgirish 	(ddi_get16(NPI_REGH(npi_handle), (uint16_t *)NPI_REGP(npi_handle)))
26044961713Sgirish 
26144961713Sgirish #define	NXGE_MEM_PIO_READ32(npi_handle)		\
26244961713Sgirish 	(ddi_get32(NPI_REGH(npi_handle), (uint32_t *)NPI_REGP(npi_handle)))
26344961713Sgirish 
26444961713Sgirish #define	NXGE_MEM_PIO_READ64(npi_handle)		\
26544961713Sgirish 	(ddi_get64(NPI_REGH(npi_handle), (uint64_t *)NPI_REGP(npi_handle)))
26644961713Sgirish 
26744961713Sgirish #define	NXGE_MEM_PIO_WRITE8(npi_handle, data)	\
26844961713Sgirish 	(ddi_put8(NPI_REGH(npi_handle), (uint8_t *)NPI_REGP(npi_handle), data))
26944961713Sgirish 
27044961713Sgirish #define	NXGE_MEM_PIO_WRITE16(npi_handle, data)	\
27144961713Sgirish 		(ddi_put16(NPI_REGH(npi_handle),	\
27244961713Sgirish 		(uint16_t *)NPI_REGP(npi_handle), data))
27344961713Sgirish 
27444961713Sgirish #define	NXGE_MEM_PIO_WRITE32(npi_handle, data)	\
27544961713Sgirish 		(ddi_put32(NPI_REGH(npi_handle),	\
27644961713Sgirish 		(uint32_t *)NPI_REGP(npi_handle), data))
27744961713Sgirish 
27844961713Sgirish #define	NXGE_MEM_PIO_WRITE64(npi_handle, data)	\
27944961713Sgirish 		(ddi_put64(NPI_REGH(npi_handle),	\
28044961713Sgirish 		(uint64_t *)NPI_REGP(npi_handle), data))
28144961713Sgirish 
28244961713Sgirish #define	SERVICE_LOST		DDI_SERVICE_LOST
28344961713Sgirish #define	SERVICE_DEGRADED	DDI_SERVICE_DEGRADED
28444961713Sgirish #define	SERVICE_UNAFFECTED	DDI_SERVICE_UNAFFECTED
28544961713Sgirish #define	SERVICE_RESTORED	DDI_SERVICE_RESTORED
28644961713Sgirish 
28744961713Sgirish #define	DATAPATH_FAULT		DDI_DATAPATH_FAULT
28844961713Sgirish #define	DEVICE_FAULT		DDI_DEVICE_FAULT
28944961713Sgirish #define	EXTERNAL_FAULT		DDI_EXTERNAL_FAULT
29044961713Sgirish 
29144961713Sgirish #define	NOTE_LINK_UP		DL_NOTE_LINK_UP
29244961713Sgirish #define	NOTE_LINK_DOWN		DL_NOTE_LINK_DOWN
29344961713Sgirish #define	NOTE_SPEED		DL_NOTE_SPEED
29444961713Sgirish #define	NOTE_PHYS_ADDR		DL_NOTE_PHYS_ADDR
29544961713Sgirish #define	NOTE_AGGR_AVAIL		DL_NOTE_AGGR_AVAIL
29644961713Sgirish #define	NOTE_AGGR_UNAVAIL	DL_NOTE_AGGR_UNAVAIL
29744961713Sgirish 
29844961713Sgirish #define	FM_REPORT_FAULT(nxgep, impact, location, msg)\
29944961713Sgirish 		ddi_dev_report_fault(nxgep->dip, impact, location, msg)
30044961713Sgirish #define	FM_CHECK_DEV_HANDLE(nxgep)\
30144961713Sgirish 		ddi_check_acc_handle(nxgep->dev_regs->nxge_regh)
30244961713Sgirish #define	FM_GET_DEVSTATE(nxgep)\
30344961713Sgirish 		ddi_get_devstate(nxgep->dip)
30444961713Sgirish #define	FM_SERVICE_RESTORED(nxgep)\
30544961713Sgirish 		ddi_fm_service_impact(nxgep->dip, DDI_SERVICE_RESTORED)
30644961713Sgirish #define	NXGE_FM_REPORT_ERROR(nxgep, portn, chan, ereport_id)\
30744961713Sgirish 		nxge_fm_report_error(nxgep, portn, chan, ereport_id)
30814ea4bb7Ssd #define	FM_CHECK_ACC_HANDLE(nxgep, handle)\
30914ea4bb7Ssd 		fm_check_acc_handle(handle)
31014ea4bb7Ssd #define	FM_CHECK_DMA_HANDLE(nxgep, handle)\
31114ea4bb7Ssd 		fm_check_dma_handle(handle)
31244961713Sgirish 
31344961713Sgirish #if defined(REG_TRACE)
31444961713Sgirish #define	NXGE_REG_RD64(handle, offset, val_p) {\
31544961713Sgirish 	*(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
31644961713Sgirish 	npi_rtrace_update(handle, B_FALSE, &npi_rtracebuf, (uint32_t)offset, \
31744961713Sgirish 			(uint64_t)(*(val_p)));\
31844961713Sgirish }
31944961713Sgirish #elif defined(REG_SHOW)
32044961713Sgirish 	/*
32144961713Sgirish 	 * Send 0xbadbad to tell rs_show_reg that we do not have
32244961713Sgirish 	 * a valid RTBUF index to pass
32344961713Sgirish 	 */
32444961713Sgirish #define	NXGE_REG_RD64(handle, offset, val_p) {\
32544961713Sgirish 	*(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
32644961713Sgirish 	rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, (uint64_t)(*(val_p)));\
32744961713Sgirish }
32844961713Sgirish #else
32944961713Sgirish #define	NXGE_REG_RD64(handle, offset, val_p) {\
33044961713Sgirish 	*(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
33144961713Sgirish }
33244961713Sgirish #endif
33344961713Sgirish 
33444961713Sgirish #if defined(REG_TRACE)
33544961713Sgirish #define	NXGE_REG_WR64(handle, offset, val) {\
33644961713Sgirish 	NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\
33744961713Sgirish 	npi_rtrace_update(handle, B_TRUE, &npi_rtracebuf, (uint32_t)offset,\
33844961713Sgirish 				(uint64_t)(val));\
33944961713Sgirish }
34044961713Sgirish #elif defined(REG_SHOW)
34144961713Sgirish /*
34244961713Sgirish  * Send 0xbadbad to tell rs_show_reg that we do not have
34344961713Sgirish  * a valid RTBUF index to pass
34444961713Sgirish  */
34544961713Sgirish #define	NXGE_REG_WR64(handle, offset, val) {\
34644961713Sgirish 	NXGE_NPI_PIO_WRITE64(handle, offset, (val));\
34744961713Sgirish 	rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\
34844961713Sgirish }
34944961713Sgirish #else
35044961713Sgirish #define	NXGE_REG_WR64(handle, offset, val) {\
35144961713Sgirish 	NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\
35244961713Sgirish }
35344961713Sgirish #endif
35444961713Sgirish 
35544961713Sgirish #ifdef	__cplusplus
35644961713Sgirish }
35744961713Sgirish #endif
35844961713Sgirish 
35944961713Sgirish #endif	/* _SYS_NXGE_NXGE_COMMON_IMPL_H */
360