144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 2289282175SSantwona Behera * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. 2344961713Sgirish */ 2444961713Sgirish 2544961713Sgirish #ifndef _SYS_NXGE_NXGE_H 2644961713Sgirish #define _SYS_NXGE_NXGE_H 2744961713Sgirish 2844961713Sgirish #ifdef __cplusplus 2944961713Sgirish extern "C" { 3044961713Sgirish #endif 3144961713Sgirish 3244961713Sgirish #include <nxge_mac.h> 3344961713Sgirish #include <nxge_ipp.h> 3444961713Sgirish #include <nxge_fflp.h> 3544961713Sgirish 3644961713Sgirish /* 3744961713Sgirish * NXGE diagnostics IOCTLS. 3844961713Sgirish */ 3944961713Sgirish #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 4044961713Sgirish 4144961713Sgirish #define NXGE_GET64 (NXGE_IOC|1) 4244961713Sgirish #define NXGE_PUT64 (NXGE_IOC|2) 4344961713Sgirish #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 4444961713Sgirish #define NXGE_GET_TX_DESC (NXGE_IOC|4) 4544961713Sgirish #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 4644961713Sgirish #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 4744961713Sgirish #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 4844961713Sgirish #define NXGE_RESET_MAC (NXGE_IOC|8) 4944961713Sgirish 5044961713Sgirish #define NXGE_GET_MII (NXGE_IOC|11) 5144961713Sgirish #define NXGE_PUT_MII (NXGE_IOC|12) 5244961713Sgirish #define NXGE_RTRACE (NXGE_IOC|13) 5344961713Sgirish #define NXGE_RTRACE_TEST (NXGE_IOC|20) 5444961713Sgirish #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 5544961713Sgirish #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 5644961713Sgirish #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 5744961713Sgirish #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 5844961713Sgirish #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 5944961713Sgirish #define NXGE_RDUMP (NXGE_IOC|26) 6044961713Sgirish #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 6144961713Sgirish #define NXGE_PIO_TEST (NXGE_IOC|28) 6244961713Sgirish 6344961713Sgirish #define NXGE_GET_TCAM (NXGE_IOC|29) 6444961713Sgirish #define NXGE_PUT_TCAM (NXGE_IOC|30) 6544961713Sgirish #define NXGE_INJECT_ERR (NXGE_IOC|40) 6644961713Sgirish 674df55fdeSJanie Lu #define NXGE_RX_CLASS (NXGE_IOC|41) 684df55fdeSJanie Lu #define NXGE_RX_HASH (NXGE_IOC|42) 694df55fdeSJanie Lu 7044961713Sgirish #define NXGE_OK 0 7144961713Sgirish #define NXGE_ERROR 0x40000000 7244961713Sgirish #define NXGE_DDI_FAILED 0x20000000 7344961713Sgirish #define NXGE_GET_PORT_NUM(n) n 7444961713Sgirish 7544961713Sgirish /* 7644961713Sgirish * Definitions for module_info. 7744961713Sgirish */ 7844961713Sgirish #define NXGE_IDNUM (0) /* module ID number */ 7944961713Sgirish #define NXGE_DRIVER_NAME "nxge" /* module name */ 8044961713Sgirish 8144961713Sgirish #define NXGE_MINPSZ (0) /* min packet size */ 8244961713Sgirish #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 8344961713Sgirish #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 8444961713Sgirish #define NXGE_LOWAT (1) /* lo-water mark */ 8544961713Sgirish #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 8644961713Sgirish #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 8744961713Sgirish #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 8844961713Sgirish #define NXGE_LOWAT_MIN (1) 8944961713Sgirish 9044961713Sgirish #ifndef D_HOTPLUG 9144961713Sgirish #define D_HOTPLUG 0x00 9244961713Sgirish #endif 9344961713Sgirish 9444961713Sgirish #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 9544961713Sgirish 9644961713Sgirish #define NXGE_CHECK_TIMER (5000) 9744961713Sgirish 984df55fdeSJanie Lu /* KT/NIU OBP creates a compatible property for KT */ 994df55fdeSJanie Lu #define KT_NIU_COMPATIBLE "SUNW,niusl-kt" 1004df55fdeSJanie Lu 10144961713Sgirish typedef enum { 10244961713Sgirish param_instance, 10344961713Sgirish param_main_instance, 10444961713Sgirish param_function_number, 10544961713Sgirish param_partition_id, 10644961713Sgirish param_read_write_mode, 10756d930aeSspeer param_fw_version, 1082e59129aSraghus param_port_mode, 10944961713Sgirish param_niu_cfg_type, 11044961713Sgirish param_tx_quick_cfg, 11144961713Sgirish param_rx_quick_cfg, 112a3c5bd6dSspeer param_master_cfg_enable, 113a3c5bd6dSspeer param_master_cfg_value, 11444961713Sgirish 11544961713Sgirish param_autoneg, 11644961713Sgirish param_anar_10gfdx, 11744961713Sgirish param_anar_10ghdx, 11844961713Sgirish param_anar_1000fdx, 11944961713Sgirish param_anar_1000hdx, 12044961713Sgirish param_anar_100T4, 12144961713Sgirish param_anar_100fdx, 12244961713Sgirish param_anar_100hdx, 12344961713Sgirish param_anar_10fdx, 12444961713Sgirish param_anar_10hdx, 12544961713Sgirish 12644961713Sgirish param_anar_asmpause, 12744961713Sgirish param_anar_pause, 12844961713Sgirish param_use_int_xcvr, 12944961713Sgirish param_enable_ipg0, 13044961713Sgirish param_ipg0, 13144961713Sgirish param_ipg1, 13244961713Sgirish param_ipg2, 13344961713Sgirish param_txdma_weight, 13444961713Sgirish param_txdma_channels_begin, 13544961713Sgirish 13644961713Sgirish param_txdma_channels, 13744961713Sgirish param_txdma_info, 13844961713Sgirish param_rxdma_channels_begin, 13944961713Sgirish param_rxdma_channels, 14044961713Sgirish param_rxdma_drr_weight, 14144961713Sgirish param_rxdma_full_header, 14244961713Sgirish param_rxdma_info, 14344961713Sgirish param_rxdma_rbr_size, 14444961713Sgirish param_rxdma_rcr_size, 14544961713Sgirish param_default_port_rdc, 14644961713Sgirish param_rxdma_intr_time, 14744961713Sgirish param_rxdma_intr_pkts, 14844961713Sgirish 14944961713Sgirish param_rdc_grps_start, 15044961713Sgirish param_rx_rdc_grps, 15144961713Sgirish param_default_grp0_rdc, 15244961713Sgirish param_default_grp1_rdc, 15344961713Sgirish param_default_grp2_rdc, 15444961713Sgirish param_default_grp3_rdc, 15544961713Sgirish param_default_grp4_rdc, 15644961713Sgirish param_default_grp5_rdc, 15744961713Sgirish param_default_grp6_rdc, 15844961713Sgirish param_default_grp7_rdc, 15944961713Sgirish 16044961713Sgirish param_info_rdc_groups, 16144961713Sgirish param_start_ldg, 16244961713Sgirish param_max_ldg, 16344961713Sgirish param_mac_2rdc_grp, 16444961713Sgirish param_vlan_2rdc_grp, 16544961713Sgirish param_fcram_part_cfg, 16644961713Sgirish param_fcram_access_ratio, 16744961713Sgirish param_tcam_access_ratio, 16844961713Sgirish param_tcam_enable, 16944961713Sgirish param_hash_lookup_enable, 17044961713Sgirish param_llc_snap_enable, 17144961713Sgirish 17244961713Sgirish param_h1_init_value, 17344961713Sgirish param_h2_init_value, 17444961713Sgirish param_class_cfg_ether_usr1, 17544961713Sgirish param_class_cfg_ether_usr2, 17644961713Sgirish param_class_cfg_ip_usr4, 17744961713Sgirish param_class_cfg_ip_usr5, 17844961713Sgirish param_class_cfg_ip_usr6, 17944961713Sgirish param_class_cfg_ip_usr7, 18044961713Sgirish param_class_opt_ip_usr4, 18144961713Sgirish param_class_opt_ip_usr5, 18244961713Sgirish param_class_opt_ip_usr6, 18344961713Sgirish param_class_opt_ip_usr7, 18444961713Sgirish param_class_opt_ipv4_tcp, 18544961713Sgirish param_class_opt_ipv4_udp, 18644961713Sgirish param_class_opt_ipv4_ah, 18744961713Sgirish param_class_opt_ipv4_sctp, 18844961713Sgirish param_class_opt_ipv6_tcp, 18944961713Sgirish param_class_opt_ipv6_udp, 19044961713Sgirish param_class_opt_ipv6_ah, 19144961713Sgirish param_class_opt_ipv6_sctp, 19244961713Sgirish param_nxge_debug_flag, 19344961713Sgirish param_npi_debug_flag, 19444961713Sgirish param_dump_rdc, 19544961713Sgirish param_dump_tdc, 19644961713Sgirish param_dump_mac_regs, 19744961713Sgirish param_dump_ipp_regs, 19844961713Sgirish param_dump_fflp_regs, 19944961713Sgirish param_dump_vlan_table, 20044961713Sgirish param_dump_rdc_table, 20144961713Sgirish param_dump_ptrs, 20244961713Sgirish param_end 20344961713Sgirish } nxge_param_index_t; 20444961713Sgirish 205678453a8Sspeer typedef enum { 206678453a8Sspeer SOLARIS_DOMAIN, 207678453a8Sspeer SOLARIS_SERVICE_DOMAIN, 208678453a8Sspeer SOLARIS_GUEST_DOMAIN, 209678453a8Sspeer LINUX_SERVICE_DOMAIN, 210678453a8Sspeer LINUX_GUEST_DOMAIN 211678453a8Sspeer } nxge_environs_t; 21244961713Sgirish 21344961713Sgirish /* 21444961713Sgirish * Named Dispatch Parameter Management Structure 21544961713Sgirish */ 21644961713Sgirish typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 21744961713Sgirish typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 218a3c5bd6dSspeer MBLKP, char *, caddr_t, cred_t *); 21944961713Sgirish 22044961713Sgirish #define NXGE_PARAM_READ 0x00000001ULL 22144961713Sgirish #define NXGE_PARAM_WRITE 0x00000002ULL 22244961713Sgirish #define NXGE_PARAM_SHARED 0x00000004ULL 22344961713Sgirish #define NXGE_PARAM_PRIV 0x00000008ULL 22444961713Sgirish #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 22544961713Sgirish #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 22644961713Sgirish #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 22744961713Sgirish 22844961713Sgirish #define NXGE_PARAM_RXDMA 0x00000010ULL 22944961713Sgirish #define NXGE_PARAM_TXDMA 0x00000020ULL 23044961713Sgirish #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 23144961713Sgirish #define NXGE_PARAM_MAC 0x00000080ULL 23244961713Sgirish #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 23344961713Sgirish #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 23444961713Sgirish #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 23544961713Sgirish 23644961713Sgirish #define NXGE_PARAM_CMPLX 0x00010000ULL 23744961713Sgirish #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 23844961713Sgirish #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 23944961713Sgirish #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 24044961713Sgirish 24144961713Sgirish #define NXGE_PARAM_READ_PROP 0x00100000ULL 24244961713Sgirish #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 24344961713Sgirish #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 24444961713Sgirish #define NXGE_PARAM_PROP_STR 0x00800000ULL 24544961713Sgirish 24644961713Sgirish #define NXGE_PARAM_BASE_DEC 0x00000000ULL 24744961713Sgirish #define NXGE_PARAM_BASE_BIN 0x10000000ULL 24844961713Sgirish #define NXGE_PARAM_BASE_HEX 0x20000000ULL 24944961713Sgirish #define NXGE_PARAM_BASE_STR 0x40000000ULL 25044961713Sgirish #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 25144961713Sgirish 25244961713Sgirish #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 25344961713Sgirish #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 25444961713Sgirish #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 25544961713Sgirish #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 25644961713Sgirish 25744961713Sgirish typedef struct _nxge_param_t { 25844961713Sgirish int (*getf)(); 25944961713Sgirish int (*setf)(); /* null for read only */ 26044961713Sgirish uint64_t type; /* R/W/ Common/Port/ .... */ 26144961713Sgirish uint64_t minimum; 26244961713Sgirish uint64_t maximum; 26344961713Sgirish uint64_t value; /* for array params, pointer to value array */ 26444961713Sgirish uint64_t old_value; /* for array params, pointer to old_value array */ 26544961713Sgirish char *fcode_name; 26644961713Sgirish char *name; 26744961713Sgirish } nxge_param_t, *p_nxge_param_t; 26844961713Sgirish 26944961713Sgirish 270321febdeSsbehera /* 271321febdeSsbehera * Do not change the order of the elements of this enum as that will 272321febdeSsbehera * break the driver code. 273321febdeSsbehera */ 27444961713Sgirish typedef enum { 27544961713Sgirish nxge_lb_normal, 27644961713Sgirish nxge_lb_ext10g, 27744961713Sgirish nxge_lb_ext1000, 27844961713Sgirish nxge_lb_ext100, 27944961713Sgirish nxge_lb_ext10, 28044961713Sgirish nxge_lb_phy10g, 28144961713Sgirish nxge_lb_phy1000, 28244961713Sgirish nxge_lb_phy, 28344961713Sgirish nxge_lb_serdes10g, 28444961713Sgirish nxge_lb_serdes1000, 28544961713Sgirish nxge_lb_serdes, 28644961713Sgirish nxge_lb_mac10g, 28744961713Sgirish nxge_lb_mac1000, 28844961713Sgirish nxge_lb_mac 28944961713Sgirish } nxge_lb_t; 29044961713Sgirish 29144961713Sgirish enum nxge_mac_state { 29244961713Sgirish NXGE_MAC_STOPPED = 0, 293678453a8Sspeer NXGE_MAC_STARTED, 294678453a8Sspeer NXGE_MAC_STOPPING 29544961713Sgirish }; 29644961713Sgirish 29744961713Sgirish /* 29844961713Sgirish * Private DLPI full dlsap address format. 29944961713Sgirish */ 30044961713Sgirish typedef struct _nxge_dladdr_t { 30144961713Sgirish ether_addr_st dl_phys; 30244961713Sgirish uint16_t dl_sap; 30344961713Sgirish } nxge_dladdr_t, *p_nxge_dladdr_t; 30444961713Sgirish 30544961713Sgirish typedef struct _mc_addr_t { 30644961713Sgirish ether_addr_st multcast_addr; 30744961713Sgirish uint_t mc_addr_cnt; 30844961713Sgirish } mc_addr_t, *p_mc_addr_t; 30944961713Sgirish 31044961713Sgirish typedef struct _mc_bucket_t { 31144961713Sgirish p_mc_addr_t addr_list; 31244961713Sgirish uint_t list_size; 31344961713Sgirish } mc_bucket_t, *p_mc_bucket_t; 31444961713Sgirish 31544961713Sgirish typedef struct _mc_table_t { 31644961713Sgirish p_mc_bucket_t bucket_list; 31744961713Sgirish uint_t buckets_used; 31844961713Sgirish } mc_table_t, *p_mc_table_t; 31944961713Sgirish 32044961713Sgirish typedef struct _filter_t { 32144961713Sgirish uint32_t all_phys_cnt; 32244961713Sgirish uint32_t all_multicast_cnt; 32344961713Sgirish uint32_t all_sap_cnt; 32444961713Sgirish } filter_t, *p_filter_t; 32544961713Sgirish 326da14cebeSEric Cheng 32744961713Sgirish typedef struct _nxge_port_stats_t { 32844961713Sgirish /* 32944961713Sgirish * Overall structure size 33044961713Sgirish */ 33144961713Sgirish size_t stats_size; 33244961713Sgirish 33344961713Sgirish /* 33444961713Sgirish * Link Input/Output stats 33544961713Sgirish */ 33644961713Sgirish uint64_t ipackets; 33744961713Sgirish uint64_t ierrors; 33844961713Sgirish uint64_t opackets; 33944961713Sgirish uint64_t oerrors; 34044961713Sgirish uint64_t collisions; 34144961713Sgirish 34244961713Sgirish /* 34344961713Sgirish * MIB II variables 34444961713Sgirish */ 34544961713Sgirish uint64_t rbytes; /* # bytes received */ 34644961713Sgirish uint64_t obytes; /* # bytes transmitted */ 34744961713Sgirish uint32_t multircv; /* # multicast packets received */ 34844961713Sgirish uint32_t multixmt; /* # multicast packets for xmit */ 34944961713Sgirish uint32_t brdcstrcv; /* # broadcast packets received */ 35044961713Sgirish uint32_t brdcstxmt; /* # broadcast packets for xmit */ 35144961713Sgirish uint32_t norcvbuf; /* # rcv packets discarded */ 35244961713Sgirish uint32_t noxmtbuf; /* # xmit packets discarded */ 35344961713Sgirish 35444961713Sgirish /* 35544961713Sgirish * Lets the user know the MTU currently in use by 35644961713Sgirish * the physical MAC port. 35744961713Sgirish */ 35844961713Sgirish nxge_lb_t lb_mode; 35944961713Sgirish uint32_t qos_mode; 36044961713Sgirish uint32_t trunk_mode; 36144961713Sgirish uint32_t poll_mode; 36244961713Sgirish 36344961713Sgirish /* 36444961713Sgirish * Tx Statistics. 36544961713Sgirish */ 36644961713Sgirish uint32_t tx_inits; 36744961713Sgirish uint32_t tx_starts; 36844961713Sgirish uint32_t tx_nocanput; 36944961713Sgirish uint32_t tx_msgdup_fail; 37044961713Sgirish uint32_t tx_allocb_fail; 37144961713Sgirish uint32_t tx_no_desc; 37244961713Sgirish uint32_t tx_dma_bind_fail; 37344961713Sgirish uint32_t tx_uflo; 37444961713Sgirish uint32_t tx_hdr_pkts; 37544961713Sgirish uint32_t tx_ddi_pkts; 37644961713Sgirish uint32_t tx_dvma_pkts; 37744961713Sgirish 37844961713Sgirish uint32_t tx_max_pend; 37944961713Sgirish 38044961713Sgirish /* 38144961713Sgirish * Rx Statistics. 38244961713Sgirish */ 38344961713Sgirish uint32_t rx_inits; 38444961713Sgirish uint32_t rx_hdr_pkts; 38544961713Sgirish uint32_t rx_mtu_pkts; 38644961713Sgirish uint32_t rx_split_pkts; 38744961713Sgirish uint32_t rx_no_buf; 38844961713Sgirish uint32_t rx_no_comp_wb; 38944961713Sgirish uint32_t rx_ov_flow; 39044961713Sgirish uint32_t rx_len_mm; 39144961713Sgirish uint32_t rx_tag_err; 39244961713Sgirish uint32_t rx_nocanput; 39344961713Sgirish uint32_t rx_msgdup_fail; 39444961713Sgirish uint32_t rx_allocb_fail; 39544961713Sgirish 39644961713Sgirish /* 39744961713Sgirish * Receive buffer management statistics. 39844961713Sgirish */ 39944961713Sgirish uint32_t rx_new_pages; 40044961713Sgirish uint32_t rx_new_hdr_pgs; 40144961713Sgirish uint32_t rx_new_mtu_pgs; 40244961713Sgirish uint32_t rx_new_nxt_pgs; 40344961713Sgirish uint32_t rx_reused_pgs; 40444961713Sgirish uint32_t rx_hdr_drops; 40544961713Sgirish uint32_t rx_mtu_drops; 40644961713Sgirish uint32_t rx_nxt_drops; 40744961713Sgirish 40844961713Sgirish /* 40944961713Sgirish * Receive flow statistics 41044961713Sgirish */ 41144961713Sgirish uint32_t rx_rel_flow; 41244961713Sgirish uint32_t rx_rel_bit; 41344961713Sgirish 41444961713Sgirish uint32_t rx_pkts_dropped; 41544961713Sgirish 41644961713Sgirish /* 41744961713Sgirish * PCI-E Bus Statistics. 41844961713Sgirish */ 41944961713Sgirish uint32_t pci_bus_speed; 42044961713Sgirish uint32_t pci_err; 42144961713Sgirish uint32_t pci_rta_err; 42244961713Sgirish uint32_t pci_rma_err; 42344961713Sgirish uint32_t pci_parity_err; 42444961713Sgirish uint32_t pci_bad_ack_err; 42544961713Sgirish uint32_t pci_drto_err; 42644961713Sgirish uint32_t pci_dmawz_err; 42744961713Sgirish uint32_t pci_dmarz_err; 42844961713Sgirish 42944961713Sgirish uint32_t rx_taskq_waits; 43044961713Sgirish 43144961713Sgirish uint32_t tx_jumbo_pkts; 43244961713Sgirish 43344961713Sgirish /* 43444961713Sgirish * Some statistics added to support bringup, these 43544961713Sgirish * should be removed. 43644961713Sgirish */ 43744961713Sgirish uint32_t user_defined; 43844961713Sgirish } nxge_port_stats_t, *p_nxge_port_stats_t; 43944961713Sgirish 44044961713Sgirish 44144961713Sgirish typedef struct _nxge_stats_t { 44244961713Sgirish /* 44344961713Sgirish * Overall structure size 44444961713Sgirish */ 44544961713Sgirish size_t stats_size; 44644961713Sgirish 44744961713Sgirish kstat_t *ksp; 44844961713Sgirish kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 44944961713Sgirish kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 45044961713Sgirish kstat_t *rdc_sys_ksp; 45144961713Sgirish kstat_t *fflp_ksp[1]; 45244961713Sgirish kstat_t *ipp_ksp; 45344961713Sgirish kstat_t *txc_ksp; 45444961713Sgirish kstat_t *mac_ksp; 45544961713Sgirish kstat_t *zcp_ksp; 45644961713Sgirish kstat_t *port_ksp; 45744961713Sgirish kstat_t *mmac_ksp; 45844961713Sgirish 45944961713Sgirish nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 46044961713Sgirish nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 46144961713Sgirish nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 46244961713Sgirish 46344961713Sgirish nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 46444961713Sgirish nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 46544961713Sgirish nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 46644961713Sgirish nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 46744961713Sgirish nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 46844961713Sgirish 46944961713Sgirish nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 47044961713Sgirish nxge_txc_stats_t txc_stats; /* per port TX stats */ 47144961713Sgirish nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 47244961713Sgirish nxge_fflp_stats_t fflp_stats; /* fflp stats */ 47344961713Sgirish nxge_port_stats_t port_stats; /* fflp stats */ 47444961713Sgirish nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 47544961713Sgirish 47644961713Sgirish } nxge_stats_t, *p_nxge_stats_t; 47744961713Sgirish 478da14cebeSEric Cheng 479da14cebeSEric Cheng 48044961713Sgirish typedef struct _nxge_intr_t { 48144961713Sgirish boolean_t intr_registered; /* interrupts are registered */ 48244961713Sgirish boolean_t intr_enabled; /* interrupts are enabled */ 48344961713Sgirish boolean_t niu_msi_enable; /* debug or configurable? */ 48444961713Sgirish int intr_types; /* interrupt types supported */ 48544961713Sgirish int intr_type; /* interrupt type to add */ 48644961713Sgirish int max_int_cnt; /* max MSIX/INT HW supports */ 48744961713Sgirish int start_inum; /* start inum (in sequence?) */ 48844961713Sgirish int msi_intx_cnt; /* # msi/intx ints returned */ 48944961713Sgirish int intr_added; /* # ints actually needed */ 49044961713Sgirish int intr_cap; /* interrupt capabilities */ 49144961713Sgirish size_t intr_size; /* size of array to allocate */ 49244961713Sgirish ddi_intr_handle_t *htable; /* For array of interrupts */ 49344961713Sgirish /* Add interrupt number for each interrupt vector */ 49444961713Sgirish int pri; 49544961713Sgirish } nxge_intr_t, *p_nxge_intr_t; 49644961713Sgirish 49744961713Sgirish typedef struct _nxge_ldgv_t { 49844961713Sgirish uint8_t ndma_ldvs; 49944961713Sgirish uint8_t nldvs; 50044961713Sgirish uint8_t maxldgs; 50144961713Sgirish uint8_t maxldvs; 50244961713Sgirish uint8_t ldg_intrs; 50344961713Sgirish uint32_t tmres; 50444961713Sgirish p_nxge_ldg_t ldgp; 50544961713Sgirish p_nxge_ldv_t ldvp; 50644961713Sgirish p_nxge_ldv_t ldvp_syserr; 507da14cebeSEric Cheng boolean_t ldvp_syserr_alloced; 50844961713Sgirish } nxge_ldgv_t, *p_nxge_ldgv_t; 50944961713Sgirish 510678453a8Sspeer typedef enum { 511678453a8Sspeer NXGE_TRANSMIT_GROUP, /* Legacy transmit group */ 512678453a8Sspeer NXGE_RECEIVE_GROUP, /* Legacy receive group */ 513678453a8Sspeer NXGE_VR_GROUP, /* Virtualization Region group */ 514678453a8Sspeer EXT_TRANSMIT_GROUP, /* External (Crossbow) transmit group */ 515678453a8Sspeer EXT_RECEIVE_GROUP /* External (Crossbow) receive group */ 516678453a8Sspeer } nxge_grp_type_t; 517678453a8Sspeer 518678453a8Sspeer #define NXGE_ILLEGAL_CHANNEL (NXGE_MAX_TDCS + 1) 519678453a8Sspeer 520678453a8Sspeer typedef uint8_t nxge_channel_t; 521678453a8Sspeer 522678453a8Sspeer typedef struct nxge_grp { 523678453a8Sspeer nxge_t *nxge; 524678453a8Sspeer nxge_grp_type_t type; /* Tx or Rx */ 525678453a8Sspeer 526678453a8Sspeer int sequence; /* When it was created. */ 527678453a8Sspeer int index; /* nxge_grp_set_t.group[index] */ 528678453a8Sspeer 529678453a8Sspeer struct nx_dc *dc; /* Linked list of DMA channels. */ 530678453a8Sspeer size_t count; /* A count of <dc> above. */ 531678453a8Sspeer 532678453a8Sspeer boolean_t active; /* Is it being used? */ 533678453a8Sspeer 534678453a8Sspeer dc_map_t map; /* A bitmap of the channels in <dc>. */ 535678453a8Sspeer nxge_channel_t legend[NXGE_MAX_TDCS]; 536678453a8Sspeer 537678453a8Sspeer } nxge_grp_t; 538678453a8Sspeer 539678453a8Sspeer typedef struct { 540678453a8Sspeer lg_map_t map; 541678453a8Sspeer size_t count; 542678453a8Sspeer } lg_data_t; 543678453a8Sspeer 544678453a8Sspeer typedef struct { 545678453a8Sspeer dc_map_t map; 546678453a8Sspeer size_t count; 547678453a8Sspeer } dc_data_t; 548678453a8Sspeer 549678453a8Sspeer #define NXGE_DC_SET(map, channel) map |= (1 << channel) 550678453a8Sspeer #define NXGE_DC_RESET(map, channel) map &= (~(1 << channel)) 551678453a8Sspeer 552da14cebeSEric Cheng /* For now, we only support up to 8 RDC/TDC groups */ 553da14cebeSEric Cheng #define NXGE_LOGICAL_GROUP_MAX NXGE_MAX_RDC_GROUPS 554678453a8Sspeer 555678453a8Sspeer typedef struct { 556678453a8Sspeer int sequence; /* To order groups in time. */ 557678453a8Sspeer 558678453a8Sspeer /* These are this instance's logical groups. */ 559678453a8Sspeer nxge_grp_t *group[NXGE_LOGICAL_GROUP_MAX]; 560678453a8Sspeer lg_data_t lg; 561678453a8Sspeer 562678453a8Sspeer dc_data_t shared; /* These DCs are being shared. */ 563678453a8Sspeer dc_data_t owned; /* These DCs belong to me. */ 564678453a8Sspeer dc_data_t dead; /* These DCs are in an error state. */ 565678453a8Sspeer 566678453a8Sspeer } nxge_grp_set_t; 567678453a8Sspeer 568678453a8Sspeer /* 569da14cebeSEric Cheng * Transmit Ring Group 570da14cebeSEric Cheng * TX groups will be used exclusively for the purpose of Hybrid I/O. From 571da14cebeSEric Cheng * the point of view of the nxge driver, the groups will be software 572da14cebeSEric Cheng * constructs which will be used to establish the relationship between TX 573da14cebeSEric Cheng * rings and shares. 574da14cebeSEric Cheng * 575678453a8Sspeer * Receive Ring Group 576678453a8Sspeer * One of the advanced virtualization features is the ability to bundle 577678453a8Sspeer * multiple Receive Rings in a single group. One or more MAC addresses may 578678453a8Sspeer * be assigned to a group. Incoming packets destined to the group's MAC 579678453a8Sspeer * address(es) are delivered to any ring member, according to a programmable 580678453a8Sspeer * or predefined RTS policy. Member rings can be polled individually. 581678453a8Sspeer * RX ring groups can come with a predefined set of member rings, or they 582678453a8Sspeer * are programmable by adding and removing rings to/from them. 583678453a8Sspeer */ 584da14cebeSEric Cheng typedef struct _nxge_ring_group_t { 585678453a8Sspeer mac_group_handle_t ghandle; 586678453a8Sspeer p_nxge_t nxgep; 587da14cebeSEric Cheng boolean_t started; 5882cf06b0dSMichael Speer boolean_t port_default_grp; 589da14cebeSEric Cheng mac_ring_type_t type; 590678453a8Sspeer int gindex; 591678453a8Sspeer int sindex; 592da14cebeSEric Cheng int rdctbl; 593da14cebeSEric Cheng int n_mac_addrs; 594da14cebeSEric Cheng } nxge_ring_group_t; 595678453a8Sspeer 596678453a8Sspeer /* 597678453a8Sspeer * Ring Handle 598678453a8Sspeer */ 599678453a8Sspeer typedef struct _nxge_ring_handle_t { 600678453a8Sspeer p_nxge_t nxgep; 601678453a8Sspeer int index; /* port-wise */ 602678453a8Sspeer mac_ring_handle_t ring_handle; 6030dc2366fSVenugopal Iyer uint64_t ring_gen_num; /* For RX Ring Start */ 6040dc2366fSVenugopal Iyer uint32_t channel; 605da14cebeSEric Cheng } nxge_ring_handle_t, *p_nxge_ring_handle_t; 606678453a8Sspeer 607678453a8Sspeer /* 608678453a8Sspeer * Share Handle 609678453a8Sspeer */ 610678453a8Sspeer typedef struct _nxge_share_handle_t { 611678453a8Sspeer p_nxge_t nxgep; /* Driver Handle */ 612678453a8Sspeer int index; 613678453a8Sspeer void *vrp; 614678453a8Sspeer uint64_t tmap; 615678453a8Sspeer uint64_t rmap; 616678453a8Sspeer int rxgroup; 617678453a8Sspeer boolean_t active; 618678453a8Sspeer } nxge_share_handle_t; 619678453a8Sspeer 62044961713Sgirish /* 62144961713Sgirish * Neptune Device instance state information. 62244961713Sgirish * 62344961713Sgirish * Each instance is dynamically allocated on first attach. 62444961713Sgirish */ 62544961713Sgirish struct _nxge_t { 62644961713Sgirish dev_info_t *dip; /* device instance */ 62744961713Sgirish dev_info_t *p_dip; /* Parent's device instance */ 62844961713Sgirish int instance; /* instance number */ 62944961713Sgirish int function_num; /* device function number */ 63044961713Sgirish int nports; /* # of ports on this device */ 63144961713Sgirish int board_ver; /* Board Version */ 63244961713Sgirish int use_partition; /* partition is enabled */ 63344961713Sgirish uint32_t drv_state; /* driver state bit flags */ 63444961713Sgirish uint64_t nxge_debug_level; /* driver state bit flags */ 63544961713Sgirish kmutex_t genlock[1]; 63644961713Sgirish enum nxge_mac_state nxge_mac_state; 63744961713Sgirish 63844961713Sgirish p_dev_regs_t dev_regs; 63944961713Sgirish npi_handle_t npi_handle; 64044961713Sgirish npi_handle_t npi_pci_handle; 64144961713Sgirish npi_handle_t npi_reg_handle; 64244961713Sgirish npi_handle_t npi_msi_handle; 64344961713Sgirish npi_handle_t npi_vreg_handle; 64444961713Sgirish npi_handle_t npi_v2reg_handle; 64544961713Sgirish 64659ac0c16Sdavemq nxge_xcvr_table_t xcvr; 6472d17280bSsbehera boolean_t hot_swappable_phy; 6482d17280bSsbehera boolean_t phy_absent; 6492d17280bSsbehera uint32_t xcvr_addr; 6502d17280bSsbehera uint16_t chip_id; 65189282175SSantwona Behera nxge_nlp_conn_t nlp_conn; 652*9d587972SSantwona Behera nxge_phy_prop_t phy_prop; 653*9d587972SSantwona Behera nxge_serdes_prop_t srds_prop; 65489282175SSantwona Behera 65544961713Sgirish nxge_mac_t mac; 65644961713Sgirish nxge_ipp_t ipp; 65744961713Sgirish nxge_txc_t txc; 65844961713Sgirish nxge_classify_t classifier; 65944961713Sgirish 66014ea4bb7Ssd mac_handle_t mach; /* mac module handle */ 66144961713Sgirish p_nxge_stats_t statsp; 66244961713Sgirish uint32_t param_count; 66344961713Sgirish p_nxge_param_t param_arr; 6641bd6825cSml 6651bd6825cSml uint32_t param_en_pause:1, 6661bd6825cSml param_en_asym_pause:1, 6671bd6825cSml param_en_1000fdx:1, 6681bd6825cSml param_en_100fdx:1, 6691bd6825cSml param_en_10fdx:1, 6701bd6825cSml param_pad_to_32:27; 6711bd6825cSml 67244961713Sgirish nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 67344961713Sgirish niu_type_t niu_type; 6742e59129aSraghus platform_type_t platform_type; 67544961713Sgirish boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 676678453a8Sspeer 67744961713Sgirish uint8_t def_rdc; 67844961713Sgirish 67944961713Sgirish nxge_intr_t nxge_intr_type; 68044961713Sgirish nxge_dma_pt_cfg_t pt_config; 68144961713Sgirish nxge_class_pt_cfg_t class_config; 68244961713Sgirish 68344961713Sgirish /* Logical device and group data structures. */ 68444961713Sgirish p_nxge_ldgv_t ldgvp; 68544961713Sgirish 68656d930aeSspeer npi_vpd_info_t vpd_info; 68744961713Sgirish 68844961713Sgirish ether_addr_st factaddr; /* factory mac address */ 68944961713Sgirish ether_addr_st ouraddr; /* individual address */ 6902cf06b0dSMichael Speer boolean_t primary; /* primary addr set?. */ 69144961713Sgirish kmutex_t ouraddr_lock; /* lock to protect to uradd */ 69244961713Sgirish 69344961713Sgirish ddi_iblock_cookie_t interrupt_cookie; 69444961713Sgirish 69544961713Sgirish /* 69644961713Sgirish * Blocks of memory may be pre-allocated by the 69744961713Sgirish * partition manager or the driver. They may include 69844961713Sgirish * blocks for configuration and buffers. The idea is 69944961713Sgirish * to preallocate big blocks of contiguous areas in 70044961713Sgirish * system memory (i.e. with IOMMU). These blocks then 70144961713Sgirish * will be broken up to a fixed number of blocks with 70244961713Sgirish * each block having the same block size (4K, 8K, 16K or 70344961713Sgirish * 32K) in the case of buffer blocks. For systems that 70444961713Sgirish * do not support DVMA, more than one big block will be 70544961713Sgirish * allocated. 70644961713Sgirish */ 70744961713Sgirish uint32_t rx_default_block_size; 70844961713Sgirish nxge_rx_block_size_t rx_bksize_code; 70944961713Sgirish 71044961713Sgirish p_nxge_dma_pool_t rx_buf_pool_p; 71144961713Sgirish p_nxge_dma_pool_t rx_cntl_pool_p; 71244961713Sgirish 71344961713Sgirish p_nxge_dma_pool_t tx_buf_pool_p; 71444961713Sgirish p_nxge_dma_pool_t tx_cntl_pool_p; 71544961713Sgirish 71644961713Sgirish /* Receive buffer block ring and completion ring. */ 71744961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 71844961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 71944961713Sgirish p_rx_mbox_areas_t rx_mbox_areas_p; 72044961713Sgirish 72144961713Sgirish uint32_t rdc_mask; 72244961713Sgirish 72344961713Sgirish /* Transmit descriptors rings */ 72444961713Sgirish p_tx_rings_t tx_rings; 72544961713Sgirish p_tx_mbox_areas_t tx_mbox_areas_p; 72644961713Sgirish 72744961713Sgirish ddi_dma_handle_t dmasparehandle; 72844961713Sgirish 72944961713Sgirish ulong_t sys_page_sz; 73044961713Sgirish ulong_t sys_page_mask; 73144961713Sgirish int suspended; 73244961713Sgirish 73344961713Sgirish mii_bmsr_t bmsr; /* xcvr status at last poll. */ 73444961713Sgirish mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 73544961713Sgirish 73644961713Sgirish kmutex_t mif_lock; /* Lock to protect the list. */ 73744961713Sgirish 73844961713Sgirish void (*mii_read)(); 73944961713Sgirish void (*mii_write)(); 74044961713Sgirish void (*mii_poll)(); 74144961713Sgirish filter_t filter; /* Current instance filter */ 74244961713Sgirish p_hash_filter_t hash_filter; /* Multicast hash filter. */ 74344961713Sgirish krwlock_t filter_lock; /* Lock to protect filters. */ 74444961713Sgirish 74544961713Sgirish ulong_t sys_burst_sz; 74644961713Sgirish 74744961713Sgirish uint8_t cache_line; 74844961713Sgirish 74944961713Sgirish timeout_id_t nxge_link_poll_timerid; 75044961713Sgirish timeout_id_t nxge_timerid; 75144961713Sgirish 75244961713Sgirish uint_t need_periodic_reclaim; 75344961713Sgirish timeout_id_t reclaim_timer; 75444961713Sgirish 75544961713Sgirish uint8_t msg_min; 75644961713Sgirish uint8_t crc_size; 75744961713Sgirish 75844961713Sgirish boolean_t hard_props_read; 75944961713Sgirish 76044961713Sgirish uint32_t nxge_ncpus; 76114ea4bb7Ssd uint16_t intr_timeout; 76214ea4bb7Ssd uint16_t intr_threshold; 76344961713Sgirish 76444961713Sgirish int fm_capabilities; /* FMA capabilities */ 76544961713Sgirish 76644961713Sgirish uint32_t nxge_port_rbr_size; 767678453a8Sspeer uint32_t nxge_port_rbr_spare_size; 76844961713Sgirish uint32_t nxge_port_rcr_size; 769678453a8Sspeer uint32_t nxge_port_rx_cntl_alloc_size; 77044961713Sgirish uint32_t nxge_port_tx_ring_size; 77144961713Sgirish nxge_mmac_t nxge_mmac_info; 77244961713Sgirish #if defined(sun4v) 77344961713Sgirish boolean_t niu_hsvc_available; 77444961713Sgirish hsvc_info_t niu_hsvc; 77544961713Sgirish uint64_t niu_min_ver; 77644961713Sgirish #endif 777a3c5bd6dSspeer boolean_t link_notify; 778774da109Stc int link_check_count; 77998ecde52Stm 78098ecde52Stm kmutex_t poll_lock; 78198ecde52Stm kcondvar_t poll_cv; 78298ecde52Stm link_mon_enable_t poll_state; 78398ecde52Stm #define NXGE_MAGIC 0x3ab434e3 78498ecde52Stm uint32_t nxge_magic; 7853d16f8e7Sml 7863d16f8e7Sml int soft_lso_enable; 787678453a8Sspeer /* The following fields are LDOMs-specific additions. */ 788678453a8Sspeer nxge_environs_t environs; 789678453a8Sspeer ether_addr_t hio_mac_addr; 790678453a8Sspeer uint32_t niu_cfg_hdl; 791678453a8Sspeer kmutex_t group_lock; 792678453a8Sspeer 793678453a8Sspeer struct nxge_hio_vr *hio_vr; 794678453a8Sspeer 795678453a8Sspeer nxge_grp_set_t rx_set; 796678453a8Sspeer nxge_grp_set_t tx_set; 797330cd344SMichael Speer boolean_t tdc_is_shared[NXGE_MAX_TDCS]; 798678453a8Sspeer 799da14cebeSEric Cheng /* Ring Handles */ 800da14cebeSEric Cheng nxge_ring_handle_t tx_ring_handles[NXGE_MAX_TDCS]; 801da14cebeSEric Cheng nxge_ring_handle_t rx_ring_handles[NXGE_MAX_RDCS]; 802da14cebeSEric Cheng 803da14cebeSEric Cheng nxge_ring_group_t tx_hio_groups[NXGE_MAX_TDC_GROUPS]; 804da14cebeSEric Cheng nxge_ring_group_t rx_hio_groups[NXGE_MAX_RDC_GROUPS]; 805da14cebeSEric Cheng 806678453a8Sspeer nxge_share_handle_t shares[NXGE_MAX_VRS]; 8074df55fdeSJanie Lu 8084df55fdeSJanie Lu /* 8094df55fdeSJanie Lu * KT-NIU: 8104df55fdeSJanie Lu * KT family will have up to 4 NIUs per system. 8114df55fdeSJanie Lu * Differences between N2/NIU and KT/NIU: 8124df55fdeSJanie Lu * SerDes, Hypervisor interfaces, 8134df55fdeSJanie Lu * additional NIU classification features. 8144df55fdeSJanie Lu */ 8154df55fdeSJanie Lu niu_hw_type_t niu_hw_type; 81644961713Sgirish }; 81744961713Sgirish 81844961713Sgirish /* 81944961713Sgirish * Driver state flags. 82044961713Sgirish */ 82144961713Sgirish #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 82244961713Sgirish #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 82344961713Sgirish #define STATE_NODE_CREATED 0x000000004 /* device node created */ 82444961713Sgirish #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 82544961713Sgirish #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 82644961713Sgirish #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 82744961713Sgirish #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 82844961713Sgirish 82944961713Sgirish #define STOP_POLL_THRESH 9 83044961713Sgirish #define START_POLL_THRESH 2 83144961713Sgirish 83244961713Sgirish typedef struct _nxge_port_kstat_t { 83344961713Sgirish /* 83444961713Sgirish * Transciever state informations. 83544961713Sgirish */ 83644961713Sgirish kstat_named_t xcvr_inits; 83744961713Sgirish kstat_named_t xcvr_inuse; 83844961713Sgirish kstat_named_t xcvr_addr; 83944961713Sgirish kstat_named_t xcvr_id; 84044961713Sgirish kstat_named_t cap_autoneg; 84144961713Sgirish kstat_named_t cap_10gfdx; 84244961713Sgirish kstat_named_t cap_10ghdx; 84344961713Sgirish kstat_named_t cap_1000fdx; 84444961713Sgirish kstat_named_t cap_1000hdx; 84544961713Sgirish kstat_named_t cap_100T4; 84644961713Sgirish kstat_named_t cap_100fdx; 84744961713Sgirish kstat_named_t cap_100hdx; 84844961713Sgirish kstat_named_t cap_10fdx; 84944961713Sgirish kstat_named_t cap_10hdx; 85044961713Sgirish kstat_named_t cap_asmpause; 85144961713Sgirish kstat_named_t cap_pause; 85244961713Sgirish 85344961713Sgirish /* 85444961713Sgirish * Link partner capabilities. 85544961713Sgirish */ 85644961713Sgirish kstat_named_t lp_cap_autoneg; 85744961713Sgirish kstat_named_t lp_cap_10gfdx; 85844961713Sgirish kstat_named_t lp_cap_10ghdx; 85944961713Sgirish kstat_named_t lp_cap_1000fdx; 86044961713Sgirish kstat_named_t lp_cap_1000hdx; 86144961713Sgirish kstat_named_t lp_cap_100T4; 86244961713Sgirish kstat_named_t lp_cap_100fdx; 86344961713Sgirish kstat_named_t lp_cap_100hdx; 86444961713Sgirish kstat_named_t lp_cap_10fdx; 86544961713Sgirish kstat_named_t lp_cap_10hdx; 86644961713Sgirish kstat_named_t lp_cap_asmpause; 86744961713Sgirish kstat_named_t lp_cap_pause; 86844961713Sgirish 86944961713Sgirish /* 87044961713Sgirish * Shared link setup. 87144961713Sgirish */ 87244961713Sgirish kstat_named_t link_T4; 87344961713Sgirish kstat_named_t link_speed; 87444961713Sgirish kstat_named_t link_duplex; 87544961713Sgirish kstat_named_t link_asmpause; 87644961713Sgirish kstat_named_t link_pause; 87744961713Sgirish kstat_named_t link_up; 87844961713Sgirish 87944961713Sgirish /* 88044961713Sgirish * Lets the user know the MTU currently in use by 88144961713Sgirish * the physical MAC port. 88244961713Sgirish */ 88344961713Sgirish kstat_named_t mac_mtu; 88444961713Sgirish kstat_named_t lb_mode; 88544961713Sgirish kstat_named_t qos_mode; 88644961713Sgirish kstat_named_t trunk_mode; 88744961713Sgirish 88844961713Sgirish /* 88944961713Sgirish * Misc MAC statistics. 89044961713Sgirish */ 89144961713Sgirish kstat_named_t ifspeed; 89244961713Sgirish kstat_named_t promisc; 89344961713Sgirish kstat_named_t rev_id; 89444961713Sgirish 89544961713Sgirish /* 89644961713Sgirish * Some statistics added to support bringup, these 89744961713Sgirish * should be removed. 89844961713Sgirish */ 89944961713Sgirish kstat_named_t user_defined; 90044961713Sgirish } nxge_port_kstat_t, *p_nxge_port_kstat_t; 90144961713Sgirish 90244961713Sgirish typedef struct _nxge_rdc_kstat { 90344961713Sgirish /* 90444961713Sgirish * Receive DMA channel statistics. 90544961713Sgirish */ 90644961713Sgirish kstat_named_t ipackets; 90744961713Sgirish kstat_named_t rbytes; 90844961713Sgirish kstat_named_t errors; 90944961713Sgirish kstat_named_t dcf_err; 91044961713Sgirish kstat_named_t rcr_ack_err; 91144961713Sgirish 91244961713Sgirish kstat_named_t dc_fifoflow_err; 91344961713Sgirish kstat_named_t rcr_sha_par_err; 91444961713Sgirish kstat_named_t rbr_pre_par_err; 91544961713Sgirish kstat_named_t wred_drop; 91644961713Sgirish kstat_named_t rbr_pre_emty; 91744961713Sgirish 91844961713Sgirish kstat_named_t rcr_shadow_full; 91944961713Sgirish kstat_named_t rbr_tmout; 92044961713Sgirish kstat_named_t rsp_cnt_err; 92144961713Sgirish kstat_named_t byte_en_bus; 92244961713Sgirish kstat_named_t rsp_dat_err; 92344961713Sgirish 9244202ea4bSsbehera kstat_named_t pkt_too_long_err; 92544961713Sgirish kstat_named_t compl_l2_err; 92644961713Sgirish kstat_named_t compl_l4_cksum_err; 92744961713Sgirish kstat_named_t compl_zcp_soft_err; 92844961713Sgirish kstat_named_t compl_fflp_soft_err; 92944961713Sgirish kstat_named_t config_err; 93044961713Sgirish 93144961713Sgirish kstat_named_t rcrincon; 93244961713Sgirish kstat_named_t rcrfull; 93344961713Sgirish kstat_named_t rbr_empty; 93444961713Sgirish kstat_named_t rbrfull; 93544961713Sgirish kstat_named_t rbrlogpage; 93644961713Sgirish 93744961713Sgirish kstat_named_t cfiglogpage; 93844961713Sgirish kstat_named_t port_drop_pkt; 93944961713Sgirish kstat_named_t rcr_to; 94044961713Sgirish kstat_named_t rcr_thresh; 94144961713Sgirish kstat_named_t rcr_mex; 94244961713Sgirish kstat_named_t id_mismatch; 94344961713Sgirish kstat_named_t zcp_eop_err; 94444961713Sgirish kstat_named_t ipp_eop_err; 94544961713Sgirish } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 94644961713Sgirish 94744961713Sgirish typedef struct _nxge_rdc_sys_kstat { 94844961713Sgirish /* 94944961713Sgirish * Receive DMA system statistics. 95044961713Sgirish */ 95144961713Sgirish kstat_named_t pre_par; 95244961713Sgirish kstat_named_t sha_par; 95344961713Sgirish kstat_named_t id_mismatch; 95444961713Sgirish kstat_named_t ipp_eop_err; 95544961713Sgirish kstat_named_t zcp_eop_err; 95644961713Sgirish } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 95744961713Sgirish 95844961713Sgirish typedef struct _nxge_tdc_kstat { 95944961713Sgirish /* 96044961713Sgirish * Transmit DMA channel statistics. 96144961713Sgirish */ 96244961713Sgirish kstat_named_t opackets; 96344961713Sgirish kstat_named_t obytes; 96444961713Sgirish kstat_named_t oerrors; 96544961713Sgirish kstat_named_t tx_inits; 96644961713Sgirish kstat_named_t tx_no_buf; 96744961713Sgirish 96844961713Sgirish kstat_named_t mbox_err; 96944961713Sgirish kstat_named_t pkt_size_err; 97044961713Sgirish kstat_named_t tx_ring_oflow; 97144961713Sgirish kstat_named_t pref_buf_ecc_err; 97244961713Sgirish kstat_named_t nack_pref; 97344961713Sgirish kstat_named_t nack_pkt_rd; 97444961713Sgirish kstat_named_t conf_part_err; 97544961713Sgirish kstat_named_t pkt_prt_err; 97644961713Sgirish kstat_named_t reset_fail; 97744961713Sgirish /* used to in the common (per port) counter */ 97844961713Sgirish 97944961713Sgirish kstat_named_t tx_starts; 98044961713Sgirish kstat_named_t tx_nocanput; 98144961713Sgirish kstat_named_t tx_msgdup_fail; 98244961713Sgirish kstat_named_t tx_allocb_fail; 98344961713Sgirish kstat_named_t tx_no_desc; 98444961713Sgirish kstat_named_t tx_dma_bind_fail; 98544961713Sgirish kstat_named_t tx_uflo; 98644961713Sgirish kstat_named_t tx_hdr_pkts; 98744961713Sgirish kstat_named_t tx_ddi_pkts; 98844961713Sgirish kstat_named_t tx_dvma_pkts; 98944961713Sgirish kstat_named_t tx_max_pend; 99044961713Sgirish } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 99144961713Sgirish 99244961713Sgirish typedef struct _nxge_txc_kstat { 99344961713Sgirish /* 99444961713Sgirish * Transmit port TXC block statistics. 99544961713Sgirish */ 99644961713Sgirish kstat_named_t pkt_stuffed; 99744961713Sgirish kstat_named_t pkt_xmit; 99844961713Sgirish kstat_named_t ro_correct_err; 99944961713Sgirish kstat_named_t ro_uncorrect_err; 100044961713Sgirish kstat_named_t sf_correct_err; 100144961713Sgirish kstat_named_t sf_uncorrect_err; 100244961713Sgirish kstat_named_t address_failed; 100344961713Sgirish kstat_named_t dma_failed; 100444961713Sgirish kstat_named_t length_failed; 100544961713Sgirish kstat_named_t pkt_assy_dead; 100644961713Sgirish kstat_named_t reorder_err; 100744961713Sgirish } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 100844961713Sgirish 100944961713Sgirish typedef struct _nxge_ipp_kstat { 101044961713Sgirish /* 101144961713Sgirish * Receive port IPP block statistics. 101244961713Sgirish */ 101344961713Sgirish kstat_named_t eop_miss; 101444961713Sgirish kstat_named_t sop_miss; 101544961713Sgirish kstat_named_t dfifo_ue; 101644961713Sgirish kstat_named_t ecc_err_cnt; 1017846a903dSml kstat_named_t pfifo_perr; 101844961713Sgirish kstat_named_t pfifo_over; 101944961713Sgirish kstat_named_t pfifo_und; 102044961713Sgirish kstat_named_t bad_cs_cnt; 102144961713Sgirish kstat_named_t pkt_dis_cnt; 102244961713Sgirish } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 102344961713Sgirish 102444961713Sgirish typedef struct _nxge_zcp_kstat { 102544961713Sgirish /* 102644961713Sgirish * ZCP statistics. 102744961713Sgirish */ 102844961713Sgirish kstat_named_t errors; 102944961713Sgirish kstat_named_t inits; 103044961713Sgirish kstat_named_t rrfifo_underrun; 103144961713Sgirish kstat_named_t rrfifo_overrun; 103244961713Sgirish kstat_named_t rspfifo_uncorr_err; 103344961713Sgirish kstat_named_t buffer_overflow; 103444961713Sgirish kstat_named_t stat_tbl_perr; 103544961713Sgirish kstat_named_t dyn_tbl_perr; 103644961713Sgirish kstat_named_t buf_tbl_perr; 103744961713Sgirish kstat_named_t tt_program_err; 103844961713Sgirish kstat_named_t rsp_tt_index_err; 103944961713Sgirish kstat_named_t slv_tt_index_err; 104044961713Sgirish kstat_named_t zcp_tt_index_err; 104144961713Sgirish kstat_named_t access_fail; 104244961713Sgirish kstat_named_t cfifo_ecc; 104344961713Sgirish } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 104444961713Sgirish 104544961713Sgirish typedef struct _nxge_mac_kstat { 104644961713Sgirish /* 104744961713Sgirish * Transmit MAC statistics. 104844961713Sgirish */ 104944961713Sgirish kstat_named_t tx_frame_cnt; 105044961713Sgirish kstat_named_t tx_underflow_err; 105144961713Sgirish kstat_named_t tx_overflow_err; 105244961713Sgirish kstat_named_t tx_maxpktsize_err; 105344961713Sgirish kstat_named_t tx_fifo_xfr_err; 105444961713Sgirish kstat_named_t tx_byte_cnt; 105544961713Sgirish 105644961713Sgirish /* 105744961713Sgirish * Receive MAC statistics. 105844961713Sgirish */ 105944961713Sgirish kstat_named_t rx_frame_cnt; 106044961713Sgirish kstat_named_t rx_underflow_err; 106144961713Sgirish kstat_named_t rx_overflow_err; 106244961713Sgirish kstat_named_t rx_len_err_cnt; 106344961713Sgirish kstat_named_t rx_crc_err_cnt; 106444961713Sgirish kstat_named_t rx_viol_err_cnt; 106544961713Sgirish kstat_named_t rx_byte_cnt; 106644961713Sgirish kstat_named_t rx_hist1_cnt; 106744961713Sgirish kstat_named_t rx_hist2_cnt; 106844961713Sgirish kstat_named_t rx_hist3_cnt; 106944961713Sgirish kstat_named_t rx_hist4_cnt; 107044961713Sgirish kstat_named_t rx_hist5_cnt; 107144961713Sgirish kstat_named_t rx_hist6_cnt; 1072321febdeSsbehera kstat_named_t rx_hist7_cnt; 107344961713Sgirish kstat_named_t rx_broadcast_cnt; 107444961713Sgirish kstat_named_t rx_mult_cnt; 107544961713Sgirish kstat_named_t rx_frag_cnt; 107644961713Sgirish kstat_named_t rx_frame_align_err_cnt; 107744961713Sgirish kstat_named_t rx_linkfault_err_cnt; 107844961713Sgirish kstat_named_t rx_local_fault_err_cnt; 107944961713Sgirish kstat_named_t rx_remote_fault_err_cnt; 108044961713Sgirish } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 108144961713Sgirish 108244961713Sgirish typedef struct _nxge_xmac_kstat { 108344961713Sgirish /* 108444961713Sgirish * XMAC statistics. 108544961713Sgirish */ 108644961713Sgirish kstat_named_t tx_frame_cnt; 108744961713Sgirish kstat_named_t tx_underflow_err; 108844961713Sgirish kstat_named_t tx_maxpktsize_err; 108944961713Sgirish kstat_named_t tx_overflow_err; 109044961713Sgirish kstat_named_t tx_fifo_xfr_err; 109144961713Sgirish kstat_named_t tx_byte_cnt; 109244961713Sgirish kstat_named_t rx_frame_cnt; 109344961713Sgirish kstat_named_t rx_underflow_err; 109444961713Sgirish kstat_named_t rx_overflow_err; 109544961713Sgirish kstat_named_t rx_crc_err_cnt; 109644961713Sgirish kstat_named_t rx_len_err_cnt; 109744961713Sgirish kstat_named_t rx_viol_err_cnt; 109844961713Sgirish kstat_named_t rx_byte_cnt; 109944961713Sgirish kstat_named_t rx_hist1_cnt; 110044961713Sgirish kstat_named_t rx_hist2_cnt; 110144961713Sgirish kstat_named_t rx_hist3_cnt; 110244961713Sgirish kstat_named_t rx_hist4_cnt; 110344961713Sgirish kstat_named_t rx_hist5_cnt; 110444961713Sgirish kstat_named_t rx_hist6_cnt; 110544961713Sgirish kstat_named_t rx_hist7_cnt; 110644961713Sgirish kstat_named_t rx_broadcast_cnt; 110744961713Sgirish kstat_named_t rx_mult_cnt; 110844961713Sgirish kstat_named_t rx_frag_cnt; 110944961713Sgirish kstat_named_t rx_frame_align_err_cnt; 111044961713Sgirish kstat_named_t rx_linkfault_err_cnt; 111144961713Sgirish kstat_named_t rx_remote_fault_err_cnt; 111244961713Sgirish kstat_named_t rx_local_fault_err_cnt; 111344961713Sgirish kstat_named_t rx_pause_cnt; 111444961713Sgirish kstat_named_t xpcs_deskew_err_cnt; 111544961713Sgirish kstat_named_t xpcs_ln0_symbol_err_cnt; 111644961713Sgirish kstat_named_t xpcs_ln1_symbol_err_cnt; 111744961713Sgirish kstat_named_t xpcs_ln2_symbol_err_cnt; 111844961713Sgirish kstat_named_t xpcs_ln3_symbol_err_cnt; 111944961713Sgirish } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 112044961713Sgirish 112144961713Sgirish typedef struct _nxge_bmac_kstat { 112244961713Sgirish /* 112344961713Sgirish * BMAC statistics. 112444961713Sgirish */ 112544961713Sgirish kstat_named_t tx_frame_cnt; 112644961713Sgirish kstat_named_t tx_underrun_err; 112744961713Sgirish kstat_named_t tx_max_pkt_err; 112844961713Sgirish kstat_named_t tx_byte_cnt; 112944961713Sgirish kstat_named_t rx_frame_cnt; 113044961713Sgirish kstat_named_t rx_byte_cnt; 113144961713Sgirish kstat_named_t rx_overflow_err; 113244961713Sgirish kstat_named_t rx_align_err_cnt; 113344961713Sgirish kstat_named_t rx_crc_err_cnt; 113444961713Sgirish kstat_named_t rx_len_err_cnt; 113544961713Sgirish kstat_named_t rx_viol_err_cnt; 113644961713Sgirish kstat_named_t rx_pause_cnt; 113744961713Sgirish kstat_named_t tx_pause_state; 113844961713Sgirish kstat_named_t tx_nopause_state; 113944961713Sgirish } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 114044961713Sgirish 114144961713Sgirish 114244961713Sgirish typedef struct _nxge_fflp_kstat { 114344961713Sgirish /* 114444961713Sgirish * FFLP statistics. 114544961713Sgirish */ 114644961713Sgirish 114744961713Sgirish kstat_named_t fflp_tcam_perr; 1148979818aeSmisaki kstat_named_t fflp_tcam_ecc_err; 114944961713Sgirish kstat_named_t fflp_vlan_perr; 115044961713Sgirish kstat_named_t fflp_hasht_lookup_err; 115144961713Sgirish kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 115244961713Sgirish } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 115344961713Sgirish 115444961713Sgirish typedef struct _nxge_mmac_kstat { 115544961713Sgirish kstat_named_t mmac_max_addr_cnt; 115644961713Sgirish kstat_named_t mmac_avail_addr_cnt; 115744961713Sgirish kstat_named_t mmac_addr1; 115844961713Sgirish kstat_named_t mmac_addr2; 115944961713Sgirish kstat_named_t mmac_addr3; 116044961713Sgirish kstat_named_t mmac_addr4; 116144961713Sgirish kstat_named_t mmac_addr5; 116244961713Sgirish kstat_named_t mmac_addr6; 116344961713Sgirish kstat_named_t mmac_addr7; 116444961713Sgirish kstat_named_t mmac_addr8; 116544961713Sgirish kstat_named_t mmac_addr9; 116644961713Sgirish kstat_named_t mmac_addr10; 116744961713Sgirish kstat_named_t mmac_addr11; 116844961713Sgirish kstat_named_t mmac_addr12; 116944961713Sgirish kstat_named_t mmac_addr13; 117044961713Sgirish kstat_named_t mmac_addr14; 117144961713Sgirish kstat_named_t mmac_addr15; 117244961713Sgirish kstat_named_t mmac_addr16; 117344961713Sgirish } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 117444961713Sgirish 117544961713Sgirish /* 117644961713Sgirish * Prototype definitions. 117744961713Sgirish */ 117844961713Sgirish nxge_status_t nxge_init(p_nxge_t); 117944961713Sgirish void nxge_uninit(p_nxge_t); 118044961713Sgirish void nxge_get64(p_nxge_t, p_mblk_t); 118144961713Sgirish void nxge_put64(p_nxge_t, p_mblk_t); 118244961713Sgirish void nxge_pio_loop(p_nxge_t, p_mblk_t); 118344961713Sgirish 118444961713Sgirish typedef void (*fptrv_t)(); 1185330cd344SMichael Speer timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 1186330cd344SMichael Speer void nxge_stop_timer(p_nxge_t, timeout_id_t); 118744961713Sgirish 118844961713Sgirish #ifdef __cplusplus 118944961713Sgirish } 119044961713Sgirish #endif 119144961713Sgirish 119244961713Sgirish #endif /* _SYS_NXGE_NXGE_H */ 1193