xref: /illumos-gate/usr/src/uts/common/sys/nxge/nxge.h (revision 1bd6825caba5ece2838569ea639756aee59675a7)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_NXGE_NXGE_H
27 #define	_SYS_NXGE_NXGE_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #if defined(_KERNEL) || defined(COSIM)
36 #include <nxge_mac.h>
37 #include <nxge_ipp.h>
38 #include <nxge_fflp.h>
39 #endif
40 
41 /*
42  * NXGE diagnostics IOCTLS.
43  */
44 #define	NXGE_IOC		((((('N' << 8) + 'X') << 8) + 'G') << 8)
45 
46 #define	NXGE_GET64		(NXGE_IOC|1)
47 #define	NXGE_PUT64		(NXGE_IOC|2)
48 #define	NXGE_GET_TX_RING_SZ	(NXGE_IOC|3)
49 #define	NXGE_GET_TX_DESC	(NXGE_IOC|4)
50 #define	NXGE_GLOBAL_RESET	(NXGE_IOC|5)
51 #define	NXGE_TX_SIDE_RESET	(NXGE_IOC|6)
52 #define	NXGE_RX_SIDE_RESET	(NXGE_IOC|7)
53 #define	NXGE_RESET_MAC		(NXGE_IOC|8)
54 
55 #define	NXGE_GET_MII		(NXGE_IOC|11)
56 #define	NXGE_PUT_MII		(NXGE_IOC|12)
57 #define	NXGE_RTRACE		(NXGE_IOC|13)
58 #define	NXGE_RTRACE_TEST	(NXGE_IOC|20)
59 #define	NXGE_TX_REGS_DUMP	(NXGE_IOC|21)
60 #define	NXGE_RX_REGS_DUMP	(NXGE_IOC|22)
61 #define	NXGE_INT_REGS_DUMP	(NXGE_IOC|23)
62 #define	NXGE_VIR_REGS_DUMP	(NXGE_IOC|24)
63 #define	NXGE_VIR_INT_REGS_DUMP	(NXGE_IOC|25)
64 #define	NXGE_RDUMP		(NXGE_IOC|26)
65 #define	NXGE_RDC_GRPS_DUMP	(NXGE_IOC|27)
66 #define	NXGE_PIO_TEST		(NXGE_IOC|28)
67 
68 #define	NXGE_GET_TCAM		(NXGE_IOC|29)
69 #define	NXGE_PUT_TCAM		(NXGE_IOC|30)
70 #define	NXGE_INJECT_ERR		(NXGE_IOC|40)
71 
72 #if (defined(SOLARIS) && defined(_KERNEL)) || defined(COSIM)
73 #define	NXGE_OK			0
74 #define	NXGE_ERROR		0x40000000
75 #define	NXGE_DDI_FAILED		0x20000000
76 #define	NXGE_GET_PORT_NUM(n)	n
77 
78 /*
79  * Definitions for module_info.
80  */
81 #define	NXGE_IDNUM		(0)			/* module ID number */
82 #define	NXGE_DRIVER_NAME	"nxge"			/* module name */
83 
84 #define	NXGE_MINPSZ		(0)			/* min packet size */
85 #define	NXGE_MAXPSZ		(ETHERMTU)		/* max packet size */
86 #define	NXGE_HIWAT		(2048 * NXGE_MAXPSZ)	/* hi-water mark */
87 #define	NXGE_LOWAT		(1)			/* lo-water mark */
88 #define	NXGE_HIWAT_MAX		(192000 * NXGE_MAXPSZ)
89 #define	NXGE_HIWAT_MIN		(2 * NXGE_MAXPSZ)
90 #define	NXGE_LOWAT_MAX		(192000 * NXGE_MAXPSZ)
91 #define	NXGE_LOWAT_MIN		(1)
92 
93 #ifndef	D_HOTPLUG
94 #define	D_HOTPLUG		0x00
95 #endif
96 
97 #define	INIT_BUCKET_SIZE	16	/* Initial Hash Bucket Size */
98 
99 #define	NXGE_CHECK_TIMER	(5000)
100 
101 typedef enum {
102 	param_instance,
103 	param_main_instance,
104 	param_function_number,
105 	param_partition_id,
106 	param_read_write_mode,
107 	param_fw_version,
108 	param_port_mode,
109 	param_niu_cfg_type,
110 	param_tx_quick_cfg,
111 	param_rx_quick_cfg,
112 	param_master_cfg_enable,
113 	param_master_cfg_value,
114 
115 	param_autoneg,
116 	param_anar_10gfdx,
117 	param_anar_10ghdx,
118 	param_anar_1000fdx,
119 	param_anar_1000hdx,
120 	param_anar_100T4,
121 	param_anar_100fdx,
122 	param_anar_100hdx,
123 	param_anar_10fdx,
124 	param_anar_10hdx,
125 
126 	param_anar_asmpause,
127 	param_anar_pause,
128 	param_use_int_xcvr,
129 	param_enable_ipg0,
130 	param_ipg0,
131 	param_ipg1,
132 	param_ipg2,
133 	param_accept_jumbo,
134 	param_txdma_weight,
135 	param_txdma_channels_begin,
136 
137 	param_txdma_channels,
138 	param_txdma_info,
139 	param_rxdma_channels_begin,
140 	param_rxdma_channels,
141 	param_rxdma_drr_weight,
142 	param_rxdma_full_header,
143 	param_rxdma_info,
144 	param_rxdma_rbr_size,
145 	param_rxdma_rcr_size,
146 	param_default_port_rdc,
147 	param_rxdma_intr_time,
148 	param_rxdma_intr_pkts,
149 
150 	param_rdc_grps_start,
151 	param_rx_rdc_grps,
152 	param_default_grp0_rdc,
153 	param_default_grp1_rdc,
154 	param_default_grp2_rdc,
155 	param_default_grp3_rdc,
156 	param_default_grp4_rdc,
157 	param_default_grp5_rdc,
158 	param_default_grp6_rdc,
159 	param_default_grp7_rdc,
160 
161 	param_info_rdc_groups,
162 	param_start_ldg,
163 	param_max_ldg,
164 	param_mac_2rdc_grp,
165 	param_vlan_2rdc_grp,
166 	param_fcram_part_cfg,
167 	param_fcram_access_ratio,
168 	param_tcam_access_ratio,
169 	param_tcam_enable,
170 	param_hash_lookup_enable,
171 	param_llc_snap_enable,
172 
173 	param_h1_init_value,
174 	param_h2_init_value,
175 	param_class_cfg_ether_usr1,
176 	param_class_cfg_ether_usr2,
177 	param_class_cfg_ip_usr4,
178 	param_class_cfg_ip_usr5,
179 	param_class_cfg_ip_usr6,
180 	param_class_cfg_ip_usr7,
181 	param_class_opt_ip_usr4,
182 	param_class_opt_ip_usr5,
183 	param_class_opt_ip_usr6,
184 	param_class_opt_ip_usr7,
185 	param_class_opt_ipv4_tcp,
186 	param_class_opt_ipv4_udp,
187 	param_class_opt_ipv4_ah,
188 	param_class_opt_ipv4_sctp,
189 	param_class_opt_ipv6_tcp,
190 	param_class_opt_ipv6_udp,
191 	param_class_opt_ipv6_ah,
192 	param_class_opt_ipv6_sctp,
193 	param_nxge_debug_flag,
194 	param_npi_debug_flag,
195 	param_dump_rdc,
196 	param_dump_tdc,
197 	param_dump_mac_regs,
198 	param_dump_ipp_regs,
199 	param_dump_fflp_regs,
200 	param_dump_vlan_table,
201 	param_dump_rdc_table,
202 	param_dump_ptrs,
203 	param_end
204 } nxge_param_index_t;
205 
206 
207 /*
208  * Named Dispatch Parameter Management Structure
209  */
210 typedef	int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *);
211 typedef	int (*nxge_ndsetf_t)(p_nxge_t, queue_t *,
212 	    MBLKP, char *, caddr_t, cred_t *);
213 
214 #define	NXGE_PARAM_READ			0x00000001ULL
215 #define	NXGE_PARAM_WRITE		0x00000002ULL
216 #define	NXGE_PARAM_SHARED		0x00000004ULL
217 #define	NXGE_PARAM_PRIV			0x00000008ULL
218 #define	NXGE_PARAM_RW			NXGE_PARAM_READ | NXGE_PARAM_WRITE
219 #define	NXGE_PARAM_RWS			NXGE_PARAM_RW | NXGE_PARAM_SHARED
220 #define	NXGE_PARAM_RWP			NXGE_PARAM_RW | NXGE_PARAM_PRIV
221 
222 #define	NXGE_PARAM_RXDMA		0x00000010ULL
223 #define	NXGE_PARAM_TXDMA		0x00000020ULL
224 #define	NXGE_PARAM_CLASS_GEN	0x00000040ULL
225 #define	NXGE_PARAM_MAC			0x00000080ULL
226 #define	NXGE_PARAM_CLASS_BIN	NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN
227 #define	NXGE_PARAM_CLASS_HEX	NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX
228 #define	NXGE_PARAM_CLASS		NXGE_PARAM_CLASS_HEX
229 
230 #define	NXGE_PARAM_CMPLX		0x00010000ULL
231 #define	NXGE_PARAM_NDD_WR_OK		0x00020000ULL
232 #define	NXGE_PARAM_INIT_ONLY		0x00040000ULL
233 #define	NXGE_PARAM_INIT_CONFIG		0x00080000ULL
234 
235 #define	NXGE_PARAM_READ_PROP		0x00100000ULL
236 #define	NXGE_PARAM_PROP_ARR32		0x00200000ULL
237 #define	NXGE_PARAM_PROP_ARR64		0x00400000ULL
238 #define	NXGE_PARAM_PROP_STR		0x00800000ULL
239 
240 #define	NXGE_PARAM_BASE_DEC		0x00000000ULL
241 #define	NXGE_PARAM_BASE_BIN		0x10000000ULL
242 #define	NXGE_PARAM_BASE_HEX		0x20000000ULL
243 #define	NXGE_PARAM_BASE_STR		0x40000000ULL
244 #define	NXGE_PARAM_DONT_SHOW		0x80000000ULL
245 
246 #define	NXGE_PARAM_ARRAY_CNT_MASK	0x0000ffff00000000ULL
247 #define	NXGE_PARAM_ARRAY_CNT_SHIFT	32ULL
248 #define	NXGE_PARAM_ARRAY_ALLOC_MASK	0xffff000000000000ULL
249 #define	NXGE_PARAM_ARRAY_ALLOC_SHIFT	48ULL
250 
251 typedef struct _nxge_param_t {
252 	int (*getf)();
253 	int (*setf)();   /* null for read only */
254 	uint64_t type;  /* R/W/ Common/Port/ .... */
255 	uint64_t minimum;
256 	uint64_t maximum;
257 	uint64_t value;	/* for array params, pointer to value array */
258 	uint64_t old_value; /* for array params, pointer to old_value array */
259 	char   *fcode_name;
260 	char   *name;
261 } nxge_param_t, *p_nxge_param_t;
262 
263 
264 /*
265  * Do not change the order of the elements of this enum as that will
266  * break the driver code.
267  */
268 typedef enum {
269 	nxge_lb_normal,
270 	nxge_lb_ext10g,
271 	nxge_lb_ext1000,
272 	nxge_lb_ext100,
273 	nxge_lb_ext10,
274 	nxge_lb_phy10g,
275 	nxge_lb_phy1000,
276 	nxge_lb_phy,
277 	nxge_lb_serdes10g,
278 	nxge_lb_serdes1000,
279 	nxge_lb_serdes,
280 	nxge_lb_mac10g,
281 	nxge_lb_mac1000,
282 	nxge_lb_mac
283 } nxge_lb_t;
284 
285 enum nxge_mac_state {
286 	NXGE_MAC_STOPPED = 0,
287 	NXGE_MAC_STARTED
288 };
289 
290 /*
291  * Private DLPI full dlsap address format.
292  */
293 typedef struct _nxge_dladdr_t {
294 	ether_addr_st dl_phys;
295 	uint16_t dl_sap;
296 } nxge_dladdr_t, *p_nxge_dladdr_t;
297 
298 typedef struct _mc_addr_t {
299 	ether_addr_st multcast_addr;
300 	uint_t mc_addr_cnt;
301 } mc_addr_t, *p_mc_addr_t;
302 
303 typedef struct _mc_bucket_t {
304 	p_mc_addr_t addr_list;
305 	uint_t list_size;
306 } mc_bucket_t, *p_mc_bucket_t;
307 
308 typedef struct _mc_table_t {
309 	p_mc_bucket_t bucket_list;
310 	uint_t buckets_used;
311 } mc_table_t, *p_mc_table_t;
312 
313 typedef struct _filter_t {
314 	uint32_t all_phys_cnt;
315 	uint32_t all_multicast_cnt;
316 	uint32_t all_sap_cnt;
317 } filter_t, *p_filter_t;
318 
319 #if defined(_KERNEL) || defined(COSIM)
320 
321 
322 typedef struct _nxge_port_stats_t {
323 	/*
324 	 *  Overall structure size
325 	 */
326 	size_t			stats_size;
327 
328 	/*
329 	 * Link Input/Output stats
330 	 */
331 	uint64_t		ipackets;
332 	uint64_t		ierrors;
333 	uint64_t		opackets;
334 	uint64_t		oerrors;
335 	uint64_t		collisions;
336 
337 	/*
338 	 * MIB II variables
339 	 */
340 	uint64_t		rbytes;    /* # bytes received */
341 	uint64_t		obytes;    /* # bytes transmitted */
342 	uint32_t		multircv;  /* # multicast packets received */
343 	uint32_t		multixmt;  /* # multicast packets for xmit */
344 	uint32_t		brdcstrcv; /* # broadcast packets received */
345 	uint32_t		brdcstxmt; /* # broadcast packets for xmit */
346 	uint32_t		norcvbuf;  /* # rcv packets discarded */
347 	uint32_t		noxmtbuf;  /* # xmit packets discarded */
348 
349 	/*
350 	 * Lets the user know the MTU currently in use by
351 	 * the physical MAC port.
352 	 */
353 	nxge_lb_t		lb_mode;
354 	uint32_t		qos_mode;
355 	uint32_t		trunk_mode;
356 	uint32_t		poll_mode;
357 
358 	/*
359 	 * Tx Statistics.
360 	 */
361 	uint32_t		tx_inits;
362 	uint32_t		tx_starts;
363 	uint32_t		tx_nocanput;
364 	uint32_t		tx_msgdup_fail;
365 	uint32_t		tx_allocb_fail;
366 	uint32_t		tx_no_desc;
367 	uint32_t		tx_dma_bind_fail;
368 	uint32_t		tx_uflo;
369 	uint32_t		tx_hdr_pkts;
370 	uint32_t		tx_ddi_pkts;
371 	uint32_t		tx_dvma_pkts;
372 
373 	uint32_t		tx_max_pend;
374 
375 	/*
376 	 * Rx Statistics.
377 	 */
378 	uint32_t		rx_inits;
379 	uint32_t		rx_hdr_pkts;
380 	uint32_t		rx_mtu_pkts;
381 	uint32_t		rx_split_pkts;
382 	uint32_t		rx_no_buf;
383 	uint32_t		rx_no_comp_wb;
384 	uint32_t		rx_ov_flow;
385 	uint32_t		rx_len_mm;
386 	uint32_t		rx_tag_err;
387 	uint32_t		rx_nocanput;
388 	uint32_t		rx_msgdup_fail;
389 	uint32_t		rx_allocb_fail;
390 
391 	/*
392 	 * Receive buffer management statistics.
393 	 */
394 	uint32_t		rx_new_pages;
395 	uint32_t		rx_new_hdr_pgs;
396 	uint32_t		rx_new_mtu_pgs;
397 	uint32_t		rx_new_nxt_pgs;
398 	uint32_t		rx_reused_pgs;
399 	uint32_t		rx_hdr_drops;
400 	uint32_t		rx_mtu_drops;
401 	uint32_t		rx_nxt_drops;
402 
403 	/*
404 	 * Receive flow statistics
405 	 */
406 	uint32_t		rx_rel_flow;
407 	uint32_t		rx_rel_bit;
408 
409 	uint32_t		rx_pkts_dropped;
410 
411 	/*
412 	 * PCI-E Bus Statistics.
413 	 */
414 	uint32_t		pci_bus_speed;
415 	uint32_t		pci_err;
416 	uint32_t		pci_rta_err;
417 	uint32_t		pci_rma_err;
418 	uint32_t		pci_parity_err;
419 	uint32_t		pci_bad_ack_err;
420 	uint32_t		pci_drto_err;
421 	uint32_t		pci_dmawz_err;
422 	uint32_t		pci_dmarz_err;
423 
424 	uint32_t		rx_taskq_waits;
425 
426 	uint32_t		tx_jumbo_pkts;
427 
428 	/*
429 	 * Some statistics added to support bringup, these
430 	 * should be removed.
431 	 */
432 	uint32_t		user_defined;
433 } nxge_port_stats_t, *p_nxge_port_stats_t;
434 
435 
436 typedef struct _nxge_stats_t {
437 	/*
438 	 *  Overall structure size
439 	 */
440 	size_t			stats_size;
441 
442 	kstat_t			*ksp;
443 	kstat_t			*rdc_ksp[NXGE_MAX_RDCS];
444 	kstat_t			*tdc_ksp[NXGE_MAX_TDCS];
445 	kstat_t			*rdc_sys_ksp;
446 	kstat_t			*fflp_ksp[1];
447 	kstat_t			*ipp_ksp;
448 	kstat_t			*txc_ksp;
449 	kstat_t			*mac_ksp;
450 	kstat_t			*zcp_ksp;
451 	kstat_t			*port_ksp;
452 	kstat_t			*mmac_ksp;
453 
454 	nxge_mac_stats_t	mac_stats;	/* Common MAC Statistics */
455 	nxge_xmac_stats_t	xmac_stats;	/* XMAC Statistics */
456 	nxge_bmac_stats_t	bmac_stats;	/* BMAC Statistics */
457 
458 	nxge_rx_ring_stats_t	rx_stats;	/* per port RX stats */
459 	nxge_ipp_stats_t	ipp_stats;	/* per port IPP stats */
460 	nxge_zcp_stats_t	zcp_stats;	/* per port IPP stats */
461 	nxge_rx_ring_stats_t	rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */
462 	nxge_rdc_sys_stats_t	rdc_sys_stats;	/* per port RDC stats */
463 
464 	nxge_tx_ring_stats_t	tx_stats;	/* per port TX stats */
465 	nxge_txc_stats_t	txc_stats;	/* per port TX stats */
466 	nxge_tx_ring_stats_t	tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */
467 	nxge_fflp_stats_t	fflp_stats;	/* fflp stats */
468 	nxge_port_stats_t	port_stats;	/* fflp stats */
469 	nxge_mmac_stats_t	mmac_stats;	/* Multi mac. stats */
470 
471 } nxge_stats_t, *p_nxge_stats_t;
472 
473 
474 
475 typedef struct _nxge_intr_t {
476 	boolean_t		intr_registered; /* interrupts are registered */
477 	boolean_t		intr_enabled; 	/* interrupts are enabled */
478 	boolean_t		niu_msi_enable;	/* debug or configurable? */
479 	uint8_t			nldevs;		/* # of logical devices */
480 	int			intr_types;	/* interrupt types supported */
481 	int			intr_type;	/* interrupt type to add */
482 	int			max_int_cnt;	/* max MSIX/INT HW supports */
483 	int			start_inum;	/* start inum (in sequence?) */
484 	int			msi_intx_cnt;	/* # msi/intx ints returned */
485 	int			intr_added;	/* # ints actually needed */
486 	int			intr_cap;	/* interrupt capabilities */
487 	size_t			intr_size;	/* size of array to allocate */
488 	ddi_intr_handle_t 	*htable;	/* For array of interrupts */
489 	/* Add interrupt number for each interrupt vector */
490 	int			pri;
491 } nxge_intr_t, *p_nxge_intr_t;
492 
493 typedef struct _nxge_ldgv_t {
494 	uint8_t			ndma_ldvs;
495 	uint8_t			nldvs;
496 	uint8_t			start_ldg;
497 	uint8_t			start_ldg_tx;
498 	uint8_t			start_ldg_rx;
499 	uint8_t			maxldgs;
500 	uint8_t			maxldvs;
501 	uint8_t			ldg_intrs;
502 	boolean_t		own_sys_err;
503 	boolean_t		own_max_ldv;
504 	uint32_t		tmres;
505 	p_nxge_ldg_t		ldgp;
506 	p_nxge_ldv_t		ldvp;
507 	p_nxge_ldv_t		ldvp_syserr;
508 } nxge_ldgv_t, *p_nxge_ldgv_t;
509 
510 /*
511  * Neptune Device instance state information.
512  *
513  * Each instance is dynamically allocated on first attach.
514  */
515 struct _nxge_t {
516 	dev_info_t		*dip;		/* device instance */
517 	dev_info_t		*p_dip;		/* Parent's device instance */
518 	int			instance;	/* instance number */
519 	int			function_num;	/* device function number */
520 	int			nports;		/* # of ports on this device */
521 	int			board_ver;	/* Board Version */
522 	int			partition_id;	/* partition ID */
523 	int			use_partition;	/* partition is enabled */
524 	uint32_t		drv_state;	/* driver state bit flags */
525 	uint64_t		nxge_debug_level; /* driver state bit flags */
526 	kmutex_t		genlock[1];
527 	enum nxge_mac_state	nxge_mac_state;
528 	ddi_softintr_t		resched_id;	/* reschedule callback	*/
529 	boolean_t		resched_needed;
530 	boolean_t		resched_running;
531 
532 	p_dev_regs_t		dev_regs;
533 	npi_handle_t		npi_handle;
534 	npi_handle_t		npi_pci_handle;
535 	npi_handle_t		npi_reg_handle;
536 	npi_handle_t		npi_msi_handle;
537 	npi_handle_t		npi_vreg_handle;
538 	npi_handle_t		npi_v2reg_handle;
539 
540 	nxge_xcvr_table_t	xcvr;
541 	boolean_t		hot_swappable_phy;
542 	boolean_t		phy_absent;
543 	uint32_t		xcvr_addr;
544 	uint16_t		chip_id;
545 	nxge_mac_t		mac;
546 	nxge_ipp_t		ipp;
547 	nxge_txc_t		txc;
548 	nxge_classify_t		classifier;
549 
550 	mac_handle_t		mach;	/* mac module handle */
551 	p_nxge_stats_t		statsp;
552 	uint32_t		param_count;
553 	p_nxge_param_t		param_arr;
554 
555 	uint32_t		param_en_pause:1,
556 				param_en_asym_pause:1,
557 				param_en_1000fdx:1,
558 				param_en_100fdx:1,
559 				param_en_10fdx:1,
560 				param_pad_to_32:27;
561 
562 	nxge_hw_list_t		*nxge_hw_p; 	/* pointer to per Neptune */
563 	niu_type_t		niu_type;
564 	platform_type_t		platform_type;
565 	boolean_t		os_addr_mode32;	/* set to 1 for 32 bit mode */
566 	uint8_t			nrdc;
567 	uint8_t			def_rdc;
568 	uint8_t			rdc[NXGE_MAX_RDCS];
569 	uint8_t			ntdc;
570 	uint8_t			tdc[NXGE_MAX_TDCS];
571 
572 	nxge_intr_t		nxge_intr_type;
573 	nxge_dma_pt_cfg_t 	pt_config;
574 	nxge_class_pt_cfg_t 	class_config;
575 
576 	/* Logical device and group data structures. */
577 	p_nxge_ldgv_t		ldgvp;
578 
579 	npi_vpd_info_t		vpd_info;
580 	caddr_t			param_list;	/* Parameter list */
581 
582 	ether_addr_st		factaddr;	/* factory mac address	    */
583 	ether_addr_st		ouraddr;	/* individual address	    */
584 	kmutex_t		ouraddr_lock;	/* lock to protect to uradd */
585 
586 	ddi_iblock_cookie_t	interrupt_cookie;
587 
588 	/*
589 	 * Blocks of memory may be pre-allocated by the
590 	 * partition manager or the driver. They may include
591 	 * blocks for configuration and buffers. The idea is
592 	 * to preallocate big blocks of contiguous areas in
593 	 * system memory (i.e. with IOMMU). These blocks then
594 	 * will be broken up to a fixed number of blocks with
595 	 * each block having the same block size (4K, 8K, 16K or
596 	 * 32K) in the case of buffer blocks. For systems that
597 	 * do not support DVMA, more than one big block will be
598 	 * allocated.
599 	 */
600 	uint32_t		rx_default_block_size;
601 	nxge_rx_block_size_t	rx_bksize_code;
602 
603 	p_nxge_dma_pool_t	rx_buf_pool_p;
604 	p_nxge_dma_pool_t	rx_cntl_pool_p;
605 
606 	p_nxge_dma_pool_t	tx_buf_pool_p;
607 	p_nxge_dma_pool_t	tx_cntl_pool_p;
608 
609 	/* Receive buffer block ring and completion ring. */
610 	p_rx_rbr_rings_t 	rx_rbr_rings;
611 	p_rx_rcr_rings_t 	rx_rcr_rings;
612 	p_rx_mbox_areas_t 	rx_mbox_areas_p;
613 
614 	p_rx_tx_params_t	rx_params;
615 	uint32_t		start_rdc;
616 	uint32_t		max_rdcs;
617 	uint32_t		rdc_mask;
618 
619 	/* Transmit descriptors rings */
620 	p_tx_rings_t 		tx_rings;
621 	p_tx_mbox_areas_t	tx_mbox_areas_p;
622 
623 	uint32_t		start_tdc;
624 	uint32_t		max_tdcs;
625 	uint32_t		tdc_mask;
626 
627 	p_rx_tx_params_t	tx_params;
628 
629 	ddi_dma_handle_t 	dmasparehandle;
630 
631 	ulong_t 		sys_page_sz;
632 	ulong_t 		sys_page_mask;
633 	int 			suspended;
634 
635 	mii_bmsr_t 		bmsr;		/* xcvr status at last poll. */
636 	mii_bmsr_t 		soft_bmsr;	/* xcvr status kept by SW. */
637 
638 	kmutex_t 		mif_lock;	/* Lock to protect the list. */
639 
640 	void 			(*mii_read)();
641 	void 			(*mii_write)();
642 	void 			(*mii_poll)();
643 	filter_t 		filter;		/* Current instance filter */
644 	p_hash_filter_t 	hash_filter;	/* Multicast hash filter. */
645 	krwlock_t		filter_lock;	/* Lock to protect filters. */
646 
647 	ulong_t 		sys_burst_sz;
648 
649 	uint8_t 		cache_line;
650 
651 	timeout_id_t 		nxge_link_poll_timerid;
652 	timeout_id_t 		nxge_timerid;
653 
654 	uint_t 			need_periodic_reclaim;
655 	timeout_id_t 		reclaim_timer;
656 
657 	uint8_t 		msg_min;
658 	uint8_t 		crc_size;
659 
660 	boolean_t 		hard_props_read;
661 
662 	boolean_t 		nxge_htraffic;
663 	uint32_t 		nxge_ncpus;
664 	uint32_t 		nxge_cpumask;
665 	uint16_t 		intr_timeout;
666 	uint16_t 		intr_threshold;
667 	uchar_t 		nxge_rxmode;
668 	uint32_t 		active_threads;
669 
670 	rtrace_t		rtrace;
671 	int			fm_capabilities; /* FMA capabilities */
672 
673 	uint32_t 		nxge_port_rbr_size;
674 	uint32_t 		nxge_port_rcr_size;
675 	uint32_t 		nxge_port_tx_ring_size;
676 	nxge_mmac_t		nxge_mmac_info;
677 #if	defined(sun4v)
678 	boolean_t		niu_hsvc_available;
679 	hsvc_info_t		niu_hsvc;
680 	uint64_t		niu_min_ver;
681 #endif
682 	boolean_t		link_notify;
683 
684 	kmutex_t		poll_lock;
685 	kcondvar_t		poll_cv;
686 	link_mon_enable_t	poll_state;
687 #define	NXGE_MAGIC		0x3ab434e3
688 	uint32_t		nxge_magic;
689 
690 	int			soft_lso_enable;
691 };
692 
693 /*
694  * Driver state flags.
695  */
696 #define	STATE_REGS_MAPPED	0x000000001	/* device registers mapped */
697 #define	STATE_KSTATS_SETUP	0x000000002	/* kstats allocated	*/
698 #define	STATE_NODE_CREATED	0x000000004	/* device node created	*/
699 #define	STATE_HW_CONFIG_CREATED	0x000000008	/* hardware properties	*/
700 #define	STATE_HW_INITIALIZED	0x000000010	/* hardware initialized	*/
701 #define	STATE_MDIO_LOCK_INIT	0x000000020	/* mdio lock initialized */
702 #define	STATE_MII_LOCK_INIT	0x000000040	/* mii lock initialized */
703 
704 #define	STOP_POLL_THRESH 	9
705 #define	START_POLL_THRESH	2
706 
707 typedef struct _nxge_port_kstat_t {
708 	/*
709 	 * Transciever state informations.
710 	 */
711 	kstat_named_t	xcvr_inits;
712 	kstat_named_t	xcvr_inuse;
713 	kstat_named_t	xcvr_addr;
714 	kstat_named_t	xcvr_id;
715 	kstat_named_t	cap_autoneg;
716 	kstat_named_t	cap_10gfdx;
717 	kstat_named_t	cap_10ghdx;
718 	kstat_named_t	cap_1000fdx;
719 	kstat_named_t	cap_1000hdx;
720 	kstat_named_t	cap_100T4;
721 	kstat_named_t	cap_100fdx;
722 	kstat_named_t	cap_100hdx;
723 	kstat_named_t	cap_10fdx;
724 	kstat_named_t	cap_10hdx;
725 	kstat_named_t	cap_asmpause;
726 	kstat_named_t	cap_pause;
727 
728 	/*
729 	 * Link partner capabilities.
730 	 */
731 	kstat_named_t	lp_cap_autoneg;
732 	kstat_named_t	lp_cap_10gfdx;
733 	kstat_named_t	lp_cap_10ghdx;
734 	kstat_named_t	lp_cap_1000fdx;
735 	kstat_named_t	lp_cap_1000hdx;
736 	kstat_named_t	lp_cap_100T4;
737 	kstat_named_t	lp_cap_100fdx;
738 	kstat_named_t	lp_cap_100hdx;
739 	kstat_named_t	lp_cap_10fdx;
740 	kstat_named_t	lp_cap_10hdx;
741 	kstat_named_t	lp_cap_asmpause;
742 	kstat_named_t	lp_cap_pause;
743 
744 	/*
745 	 * Shared link setup.
746 	 */
747 	kstat_named_t	link_T4;
748 	kstat_named_t	link_speed;
749 	kstat_named_t	link_duplex;
750 	kstat_named_t	link_asmpause;
751 	kstat_named_t	link_pause;
752 	kstat_named_t	link_up;
753 
754 	/*
755 	 * Lets the user know the MTU currently in use by
756 	 * the physical MAC port.
757 	 */
758 	kstat_named_t	mac_mtu;
759 	kstat_named_t	lb_mode;
760 	kstat_named_t	qos_mode;
761 	kstat_named_t	trunk_mode;
762 
763 	/*
764 	 * Misc MAC statistics.
765 	 */
766 	kstat_named_t	ifspeed;
767 	kstat_named_t	promisc;
768 	kstat_named_t	rev_id;
769 
770 	/*
771 	 * Some statistics added to support bringup, these
772 	 * should be removed.
773 	 */
774 	kstat_named_t	user_defined;
775 } nxge_port_kstat_t, *p_nxge_port_kstat_t;
776 
777 typedef struct _nxge_rdc_kstat {
778 	/*
779 	 * Receive DMA channel statistics.
780 	 */
781 	kstat_named_t	ipackets;
782 	kstat_named_t	rbytes;
783 	kstat_named_t	errors;
784 	kstat_named_t	dcf_err;
785 	kstat_named_t	rcr_ack_err;
786 
787 	kstat_named_t	dc_fifoflow_err;
788 	kstat_named_t	rcr_sha_par_err;
789 	kstat_named_t	rbr_pre_par_err;
790 	kstat_named_t	wred_drop;
791 	kstat_named_t	rbr_pre_emty;
792 
793 	kstat_named_t	rcr_shadow_full;
794 	kstat_named_t	rbr_tmout;
795 	kstat_named_t	rsp_cnt_err;
796 	kstat_named_t	byte_en_bus;
797 	kstat_named_t	rsp_dat_err;
798 
799 	kstat_named_t	pkt_too_long_err;
800 	kstat_named_t	compl_l2_err;
801 	kstat_named_t	compl_l4_cksum_err;
802 	kstat_named_t	compl_zcp_soft_err;
803 	kstat_named_t	compl_fflp_soft_err;
804 	kstat_named_t	config_err;
805 
806 	kstat_named_t	rcrincon;
807 	kstat_named_t	rcrfull;
808 	kstat_named_t	rbr_empty;
809 	kstat_named_t	rbrfull;
810 	kstat_named_t	rbrlogpage;
811 
812 	kstat_named_t	cfiglogpage;
813 	kstat_named_t	port_drop_pkt;
814 	kstat_named_t	rcr_to;
815 	kstat_named_t	rcr_thresh;
816 	kstat_named_t	rcr_mex;
817 	kstat_named_t	id_mismatch;
818 	kstat_named_t	zcp_eop_err;
819 	kstat_named_t	ipp_eop_err;
820 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t;
821 
822 typedef struct _nxge_rdc_sys_kstat {
823 	/*
824 	 * Receive DMA system statistics.
825 	 */
826 	kstat_named_t	pre_par;
827 	kstat_named_t	sha_par;
828 	kstat_named_t	id_mismatch;
829 	kstat_named_t	ipp_eop_err;
830 	kstat_named_t	zcp_eop_err;
831 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t;
832 
833 typedef	struct _nxge_tdc_kstat {
834 	/*
835 	 * Transmit DMA channel statistics.
836 	 */
837 	kstat_named_t	opackets;
838 	kstat_named_t	obytes;
839 	kstat_named_t	oerrors;
840 	kstat_named_t	tx_inits;
841 	kstat_named_t	tx_no_buf;
842 
843 	kstat_named_t	mbox_err;
844 	kstat_named_t	pkt_size_err;
845 	kstat_named_t	tx_ring_oflow;
846 	kstat_named_t	pref_buf_ecc_err;
847 	kstat_named_t	nack_pref;
848 	kstat_named_t	nack_pkt_rd;
849 	kstat_named_t	conf_part_err;
850 	kstat_named_t	pkt_prt_err;
851 	kstat_named_t	reset_fail;
852 /* used to in the common (per port) counter */
853 
854 	kstat_named_t	tx_starts;
855 	kstat_named_t	tx_nocanput;
856 	kstat_named_t	tx_msgdup_fail;
857 	kstat_named_t	tx_allocb_fail;
858 	kstat_named_t	tx_no_desc;
859 	kstat_named_t	tx_dma_bind_fail;
860 	kstat_named_t	tx_uflo;
861 	kstat_named_t	tx_hdr_pkts;
862 	kstat_named_t	tx_ddi_pkts;
863 	kstat_named_t	tx_dvma_pkts;
864 	kstat_named_t	tx_max_pend;
865 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t;
866 
867 typedef	struct _nxge_txc_kstat {
868 	/*
869 	 * Transmit port TXC block statistics.
870 	 */
871 	kstat_named_t	pkt_stuffed;
872 	kstat_named_t	pkt_xmit;
873 	kstat_named_t	ro_correct_err;
874 	kstat_named_t	ro_uncorrect_err;
875 	kstat_named_t	sf_correct_err;
876 	kstat_named_t	sf_uncorrect_err;
877 	kstat_named_t	address_failed;
878 	kstat_named_t	dma_failed;
879 	kstat_named_t	length_failed;
880 	kstat_named_t	pkt_assy_dead;
881 	kstat_named_t	reorder_err;
882 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t;
883 
884 typedef struct _nxge_ipp_kstat {
885 	/*
886 	 * Receive port IPP block statistics.
887 	 */
888 	kstat_named_t	eop_miss;
889 	kstat_named_t	sop_miss;
890 	kstat_named_t	dfifo_ue;
891 	kstat_named_t	ecc_err_cnt;
892 	kstat_named_t	pfifo_perr;
893 	kstat_named_t	pfifo_over;
894 	kstat_named_t	pfifo_und;
895 	kstat_named_t	bad_cs_cnt;
896 	kstat_named_t	pkt_dis_cnt;
897 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t;
898 
899 typedef	struct _nxge_zcp_kstat {
900 	/*
901 	 * ZCP statistics.
902 	 */
903 	kstat_named_t	errors;
904 	kstat_named_t	inits;
905 	kstat_named_t	rrfifo_underrun;
906 	kstat_named_t	rrfifo_overrun;
907 	kstat_named_t	rspfifo_uncorr_err;
908 	kstat_named_t	buffer_overflow;
909 	kstat_named_t	stat_tbl_perr;
910 	kstat_named_t	dyn_tbl_perr;
911 	kstat_named_t	buf_tbl_perr;
912 	kstat_named_t	tt_program_err;
913 	kstat_named_t	rsp_tt_index_err;
914 	kstat_named_t	slv_tt_index_err;
915 	kstat_named_t	zcp_tt_index_err;
916 	kstat_named_t	access_fail;
917 	kstat_named_t	cfifo_ecc;
918 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t;
919 
920 typedef	struct _nxge_mac_kstat {
921 	/*
922 	 * Transmit MAC statistics.
923 	 */
924 	kstat_named_t	tx_frame_cnt;
925 	kstat_named_t	tx_underflow_err;
926 	kstat_named_t	tx_overflow_err;
927 	kstat_named_t	tx_maxpktsize_err;
928 	kstat_named_t	tx_fifo_xfr_err;
929 	kstat_named_t	tx_byte_cnt;
930 
931 	/*
932 	 * Receive MAC statistics.
933 	 */
934 	kstat_named_t	rx_frame_cnt;
935 	kstat_named_t	rx_underflow_err;
936 	kstat_named_t	rx_overflow_err;
937 	kstat_named_t	rx_len_err_cnt;
938 	kstat_named_t	rx_crc_err_cnt;
939 	kstat_named_t	rx_viol_err_cnt;
940 	kstat_named_t	rx_byte_cnt;
941 	kstat_named_t	rx_hist1_cnt;
942 	kstat_named_t	rx_hist2_cnt;
943 	kstat_named_t	rx_hist3_cnt;
944 	kstat_named_t	rx_hist4_cnt;
945 	kstat_named_t	rx_hist5_cnt;
946 	kstat_named_t	rx_hist6_cnt;
947 	kstat_named_t	rx_hist7_cnt;
948 	kstat_named_t	rx_broadcast_cnt;
949 	kstat_named_t	rx_mult_cnt;
950 	kstat_named_t	rx_frag_cnt;
951 	kstat_named_t	rx_frame_align_err_cnt;
952 	kstat_named_t	rx_linkfault_err_cnt;
953 	kstat_named_t	rx_local_fault_err_cnt;
954 	kstat_named_t	rx_remote_fault_err_cnt;
955 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t;
956 
957 typedef	struct _nxge_xmac_kstat {
958 	/*
959 	 * XMAC statistics.
960 	 */
961 	kstat_named_t	tx_frame_cnt;
962 	kstat_named_t	tx_underflow_err;
963 	kstat_named_t	tx_maxpktsize_err;
964 	kstat_named_t	tx_overflow_err;
965 	kstat_named_t	tx_fifo_xfr_err;
966 	kstat_named_t	tx_byte_cnt;
967 	kstat_named_t	rx_frame_cnt;
968 	kstat_named_t	rx_underflow_err;
969 	kstat_named_t	rx_overflow_err;
970 	kstat_named_t	rx_crc_err_cnt;
971 	kstat_named_t	rx_len_err_cnt;
972 	kstat_named_t	rx_viol_err_cnt;
973 	kstat_named_t	rx_byte_cnt;
974 	kstat_named_t	rx_hist1_cnt;
975 	kstat_named_t	rx_hist2_cnt;
976 	kstat_named_t	rx_hist3_cnt;
977 	kstat_named_t	rx_hist4_cnt;
978 	kstat_named_t	rx_hist5_cnt;
979 	kstat_named_t	rx_hist6_cnt;
980 	kstat_named_t	rx_hist7_cnt;
981 	kstat_named_t	rx_broadcast_cnt;
982 	kstat_named_t	rx_mult_cnt;
983 	kstat_named_t	rx_frag_cnt;
984 	kstat_named_t	rx_frame_align_err_cnt;
985 	kstat_named_t	rx_linkfault_err_cnt;
986 	kstat_named_t	rx_remote_fault_err_cnt;
987 	kstat_named_t	rx_local_fault_err_cnt;
988 	kstat_named_t	rx_pause_cnt;
989 	kstat_named_t	xpcs_deskew_err_cnt;
990 	kstat_named_t	xpcs_ln0_symbol_err_cnt;
991 	kstat_named_t	xpcs_ln1_symbol_err_cnt;
992 	kstat_named_t	xpcs_ln2_symbol_err_cnt;
993 	kstat_named_t	xpcs_ln3_symbol_err_cnt;
994 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t;
995 
996 typedef	struct _nxge_bmac_kstat {
997 	/*
998 	 * BMAC statistics.
999 	 */
1000 	kstat_named_t tx_frame_cnt;
1001 	kstat_named_t tx_underrun_err;
1002 	kstat_named_t tx_max_pkt_err;
1003 	kstat_named_t tx_byte_cnt;
1004 	kstat_named_t rx_frame_cnt;
1005 	kstat_named_t rx_byte_cnt;
1006 	kstat_named_t rx_overflow_err;
1007 	kstat_named_t rx_align_err_cnt;
1008 	kstat_named_t rx_crc_err_cnt;
1009 	kstat_named_t rx_len_err_cnt;
1010 	kstat_named_t rx_viol_err_cnt;
1011 	kstat_named_t rx_pause_cnt;
1012 	kstat_named_t tx_pause_state;
1013 	kstat_named_t tx_nopause_state;
1014 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t;
1015 
1016 
1017 typedef struct _nxge_fflp_kstat {
1018 	/*
1019 	 * FFLP statistics.
1020 	 */
1021 
1022 	kstat_named_t	fflp_tcam_perr;
1023 	kstat_named_t	fflp_tcam_ecc_err;
1024 	kstat_named_t	fflp_vlan_perr;
1025 	kstat_named_t	fflp_hasht_lookup_err;
1026 	kstat_named_t	fflp_hasht_data_err[MAX_PARTITION];
1027 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t;
1028 
1029 typedef struct _nxge_mmac_kstat {
1030 	kstat_named_t	mmac_max_addr_cnt;
1031 	kstat_named_t	mmac_avail_addr_cnt;
1032 	kstat_named_t	mmac_addr1;
1033 	kstat_named_t	mmac_addr2;
1034 	kstat_named_t	mmac_addr3;
1035 	kstat_named_t	mmac_addr4;
1036 	kstat_named_t	mmac_addr5;
1037 	kstat_named_t	mmac_addr6;
1038 	kstat_named_t	mmac_addr7;
1039 	kstat_named_t	mmac_addr8;
1040 	kstat_named_t	mmac_addr9;
1041 	kstat_named_t	mmac_addr10;
1042 	kstat_named_t	mmac_addr11;
1043 	kstat_named_t	mmac_addr12;
1044 	kstat_named_t	mmac_addr13;
1045 	kstat_named_t	mmac_addr14;
1046 	kstat_named_t	mmac_addr15;
1047 	kstat_named_t	mmac_addr16;
1048 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t;
1049 
1050 #endif	/* _KERNEL */
1051 
1052 /*
1053  * Prototype definitions.
1054  */
1055 nxge_status_t nxge_init(p_nxge_t);
1056 void nxge_uninit(p_nxge_t);
1057 void nxge_get64(p_nxge_t, p_mblk_t);
1058 void nxge_put64(p_nxge_t, p_mblk_t);
1059 void nxge_pio_loop(p_nxge_t, p_mblk_t);
1060 
1061 #ifndef COSIM
1062 typedef	void	(*fptrv_t)();
1063 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int);
1064 void nxge_stop_timer(p_nxge_t, timeout_id_t);
1065 #endif
1066 #endif
1067 
1068 #ifdef	__cplusplus
1069 }
1070 #endif
1071 
1072 #endif	/* _SYS_NXGE_NXGE_H */
1073