1bafec742SSukumar Swaminathan /*
2bafec742SSukumar Swaminathan  * CDDL HEADER START
3bafec742SSukumar Swaminathan  *
4bafec742SSukumar Swaminathan  * The contents of this file are subject to the terms of the
5bafec742SSukumar Swaminathan  * Common Development and Distribution License (the "License").
6bafec742SSukumar Swaminathan  * You may not use this file except in compliance with the License.
7bafec742SSukumar Swaminathan  *
8bafec742SSukumar Swaminathan  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9bafec742SSukumar Swaminathan  * or http://www.opensolaris.org/os/licensing.
10bafec742SSukumar Swaminathan  * See the License for the specific language governing permissions
11bafec742SSukumar Swaminathan  * and limitations under the License.
12bafec742SSukumar Swaminathan  *
13bafec742SSukumar Swaminathan  * When distributing Covered Code, include this CDDL HEADER in each
14bafec742SSukumar Swaminathan  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15bafec742SSukumar Swaminathan  * If applicable, add the following below this CDDL HEADER, with the
16bafec742SSukumar Swaminathan  * fields enclosed by brackets "[]" replaced with your own identifying
17bafec742SSukumar Swaminathan  * information: Portions Copyright [yyyy] [name of copyright owner]
18bafec742SSukumar Swaminathan  *
19bafec742SSukumar Swaminathan  * CDDL HEADER END
20bafec742SSukumar Swaminathan  */
21bafec742SSukumar Swaminathan 
22bafec742SSukumar Swaminathan /*
23*accf27a5SSukumar Swaminathan  * Copyright 2010 QLogic Corporation. All rights reserved.
24bafec742SSukumar Swaminathan  */
25bafec742SSukumar Swaminathan 
26bafec742SSukumar Swaminathan #ifndef _QLGE_HW_H
27bafec742SSukumar Swaminathan #define	_QLGE_HW_H
28bafec742SSukumar Swaminathan 
29bafec742SSukumar Swaminathan #ifdef __cplusplus
30bafec742SSukumar Swaminathan extern "C" {
31bafec742SSukumar Swaminathan #endif
32bafec742SSukumar Swaminathan 
33bafec742SSukumar Swaminathan #define	ISP_SCHULTZ 0x8000
34bafec742SSukumar Swaminathan 
35bafec742SSukumar Swaminathan #define	MB_REG_COUNT		8
36bafec742SSukumar Swaminathan #define	MB_DATA_REG_COUNT	(MB_REG_COUNT-1)
37bafec742SSukumar Swaminathan 
38bafec742SSukumar Swaminathan 
39bafec742SSukumar Swaminathan #define	QLA_SCHULTZ(qlge) ((qlge)->device_id == ISP_SCHULTZ)
40bafec742SSukumar Swaminathan 
41bafec742SSukumar Swaminathan /*
42bafec742SSukumar Swaminathan  * Data bit definitions.
43bafec742SSukumar Swaminathan  */
44bafec742SSukumar Swaminathan #define	BIT_0	0x1
45bafec742SSukumar Swaminathan #define	BIT_1	0x2
46bafec742SSukumar Swaminathan #define	BIT_2	0x4
47bafec742SSukumar Swaminathan #define	BIT_3	0x8
48bafec742SSukumar Swaminathan #define	BIT_4	0x10
49bafec742SSukumar Swaminathan #define	BIT_5	0x20
50bafec742SSukumar Swaminathan #define	BIT_6	0x40
51bafec742SSukumar Swaminathan #define	BIT_7	0x80
52bafec742SSukumar Swaminathan #define	BIT_8	0x100
53bafec742SSukumar Swaminathan #define	BIT_9	0x200
54bafec742SSukumar Swaminathan #define	BIT_10	0x400
55bafec742SSukumar Swaminathan #define	BIT_11	0x800
56bafec742SSukumar Swaminathan #define	BIT_12	0x1000
57bafec742SSukumar Swaminathan #define	BIT_13	0x2000
58bafec742SSukumar Swaminathan #define	BIT_14	0x4000
59bafec742SSukumar Swaminathan #define	BIT_15	0x8000
60bafec742SSukumar Swaminathan #define	BIT_16	0x10000
61bafec742SSukumar Swaminathan #define	BIT_17	0x20000
62bafec742SSukumar Swaminathan #define	BIT_18	0x40000
63bafec742SSukumar Swaminathan #define	BIT_19	0x80000
64bafec742SSukumar Swaminathan #define	BIT_20	0x100000
65bafec742SSukumar Swaminathan #define	BIT_21	0x200000
66bafec742SSukumar Swaminathan #define	BIT_22	0x400000
67bafec742SSukumar Swaminathan #define	BIT_23	0x800000
68bafec742SSukumar Swaminathan #define	BIT_24	0x1000000
69bafec742SSukumar Swaminathan #define	BIT_25	0x2000000
70bafec742SSukumar Swaminathan #define	BIT_26	0x4000000
71bafec742SSukumar Swaminathan #define	BIT_27	0x8000000
72bafec742SSukumar Swaminathan #define	BIT_28	0x10000000
73bafec742SSukumar Swaminathan #define	BIT_29	0x20000000
74bafec742SSukumar Swaminathan #define	BIT_30	0x40000000
75bafec742SSukumar Swaminathan #define	BIT_31	0x80000000
76bafec742SSukumar Swaminathan 
77bafec742SSukumar Swaminathan typedef struct ql_stats
78bafec742SSukumar Swaminathan {
79bafec742SSukumar Swaminathan 	uint32_t	intr_type;
80bafec742SSukumar Swaminathan 	/* software statics */
81bafec742SSukumar Swaminathan 	uint32_t	intr;
82bafec742SSukumar Swaminathan 	uint64_t	speed;
83bafec742SSukumar Swaminathan 	uint32_t	duplex;
84bafec742SSukumar Swaminathan 	uint32_t	media;
85bafec742SSukumar Swaminathan 	/* TX */
86bafec742SSukumar Swaminathan 	uint64_t	obytes;
87bafec742SSukumar Swaminathan 	uint64_t	opackets;
88bafec742SSukumar Swaminathan 	uint32_t	nocarrier;
89bafec742SSukumar Swaminathan 	uint32_t	defer;
90bafec742SSukumar Swaminathan 	/* RX */
91bafec742SSukumar Swaminathan 	uint64_t	rbytes;
92bafec742SSukumar Swaminathan 	uint64_t	rpackets;
93bafec742SSukumar Swaminathan 	uint32_t	norcvbuf;
94bafec742SSukumar Swaminathan 	uint32_t	frame_too_long;
95bafec742SSukumar Swaminathan 	uint32_t	crc;
96bafec742SSukumar Swaminathan 	ulong_t		multircv;
97bafec742SSukumar Swaminathan 	ulong_t		brdcstrcv;
98bafec742SSukumar Swaminathan 	uint32_t	errrcv;
99bafec742SSukumar Swaminathan 	uint32_t	frame_too_short;
100bafec742SSukumar Swaminathan 	/* statics by hw */
101bafec742SSukumar Swaminathan 	uint32_t	errxmt;
102bafec742SSukumar Swaminathan 	uint32_t	frame_err;
103bafec742SSukumar Swaminathan 	ulong_t		multixmt;
104bafec742SSukumar Swaminathan 	ulong_t		brdcstxmt;
105bafec742SSukumar Swaminathan 	uint32_t	phy_addr;
106bafec742SSukumar Swaminathan 	uint32_t	jabber_err;
107bafec742SSukumar Swaminathan 
108bafec742SSukumar Swaminathan }ql_stats_t;
109bafec742SSukumar Swaminathan 
110bafec742SSukumar Swaminathan 
111bafec742SSukumar Swaminathan #define	ETHERNET_CRC_SIZE	4
112bafec742SSukumar Swaminathan 
113bafec742SSukumar Swaminathan /*
114bafec742SSukumar Swaminathan  * Register Definitions...
115bafec742SSukumar Swaminathan  */
116bafec742SSukumar Swaminathan #define	MAILBOX_COUNT	16
117bafec742SSukumar Swaminathan /* System Register 0x00 */
118bafec742SSukumar Swaminathan #define	PROC_ADDR_RDY	BIT_31
119bafec742SSukumar Swaminathan #define	PROC_ADDR_R	BIT_30
120bafec742SSukumar Swaminathan #define	PROC_ADDR_ERR	BIT_29
121bafec742SSukumar Swaminathan #define	PROC_ADDR_DA	BIT_28
122bafec742SSukumar Swaminathan #define	PROC_ADDR_FUNC0_MBI	0x00001180
123bafec742SSukumar Swaminathan #define	PROC_ADDR_FUNC0_MBO	(PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT)
124bafec742SSukumar Swaminathan #define	PROC_ADDR_FUNC0_CTL	0x000011a1
125bafec742SSukumar Swaminathan #define	PROC_ADDR_FUNC2_MBI	0x00001280
126bafec742SSukumar Swaminathan #define	PROC_ADDR_FUNC2_MBO	(PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT)
127bafec742SSukumar Swaminathan #define	PROC_ADDR_FUNC2_CTL	0x000012a1
128bafec742SSukumar Swaminathan #define	PROC_ADDR_MPI_RISC	0x00000000
129bafec742SSukumar Swaminathan #define	PROC_ADDR_MDE		0x00010000
130bafec742SSukumar Swaminathan #define	PROC_ADDR_REGBLOCK	0x00020000
131bafec742SSukumar Swaminathan #define	PROC_ADDR_RISC_REG	0x00030000
132bafec742SSukumar Swaminathan 
133bafec742SSukumar Swaminathan 
134bafec742SSukumar Swaminathan /* System Register 0x08 */
135bafec742SSukumar Swaminathan #define	SYSTEM_EFE_FAE		0x3u
136bafec742SSukumar Swaminathan #define	SYSTEM_EFE_FAE_MASK	(SYSTEM_EFE_FAE<<16)
137bafec742SSukumar Swaminathan enum {
138bafec742SSukumar Swaminathan 	SYS_EFE = (1 << 0),
139bafec742SSukumar Swaminathan 	SYS_FAE = (1 << 1),
140bafec742SSukumar Swaminathan 	SYS_MDC = (1 << 2),
141bafec742SSukumar Swaminathan 	SYS_DST = (1 << 3),
142bafec742SSukumar Swaminathan 	SYS_DWC = (1 << 4),
143bafec742SSukumar Swaminathan 	SYS_EVW = (1 << 5),
144bafec742SSukumar Swaminathan 	SYS_OMP_DLY_MASK = 0x3f000000,
145bafec742SSukumar Swaminathan 	/*
146bafec742SSukumar Swaminathan 	 * There are no values defined as of edit #15.
147bafec742SSukumar Swaminathan 	 */
148bafec742SSukumar Swaminathan 	SYS_ODI = (1 << 14)
149bafec742SSukumar Swaminathan };
150bafec742SSukumar Swaminathan 
151bafec742SSukumar Swaminathan /*
152bafec742SSukumar Swaminathan  * Reset/Failover Register (RST_FO) bit definitions.
153bafec742SSukumar Swaminathan  */
154bafec742SSukumar Swaminathan 
155bafec742SSukumar Swaminathan #define	RST_FO_TFO		(1 << 0)
156bafec742SSukumar Swaminathan #define	RST_FO_RR_MASK		0x00060000
157bafec742SSukumar Swaminathan #define	RST_FO_RR_CQ_CAM	0x00000000
158bafec742SSukumar Swaminathan #define	RST_FO_RR_DROP		0x00000001
159bafec742SSukumar Swaminathan #define	RST_FO_RR_DQ		0x00000002
160bafec742SSukumar Swaminathan #define	RST_FO_RR_RCV_FUNC_CQ	0x00000003
161bafec742SSukumar Swaminathan #define	RST_FO_FRB		BIT_12
162bafec742SSukumar Swaminathan #define	RST_FO_MOP		BIT_13
163bafec742SSukumar Swaminathan #define	RST_FO_REG		BIT_14
164bafec742SSukumar Swaminathan #define	RST_FO_FR		0x8000u
165bafec742SSukumar Swaminathan 
166bafec742SSukumar Swaminathan /*
167bafec742SSukumar Swaminathan  * Function Specific Control Register (FSC) bit definitions.
168bafec742SSukumar Swaminathan  */
169bafec742SSukumar Swaminathan enum {
170bafec742SSukumar Swaminathan 	FSC_DBRST_MASK = 0x00070000,
171bafec742SSukumar Swaminathan 	FSC_DBRST_256 = 0x00000000,
172bafec742SSukumar Swaminathan 	FSC_DBRST_512 = 0x00000001,
173bafec742SSukumar Swaminathan 	FSC_DBRST_768 = 0x00000002,
174bafec742SSukumar Swaminathan 	FSC_DBRST_1024 = 0x00000003,
175bafec742SSukumar Swaminathan 	FSC_DBL_MASK = 0x00180000,
176bafec742SSukumar Swaminathan 	FSC_DBL_DBRST = 0x00000000,
177bafec742SSukumar Swaminathan 	FSC_DBL_MAX_PLD = 0x00000008,
178bafec742SSukumar Swaminathan 	FSC_DBL_MAX_BRST = 0x00000010,
179bafec742SSukumar Swaminathan 	FSC_DBL_128_BYTES = 0x00000018,
180bafec742SSukumar Swaminathan 	FSC_EC = (1 << 5),
181bafec742SSukumar Swaminathan 	FSC_EPC_MASK = 0x00c00000,
182bafec742SSukumar Swaminathan 	FSC_EPC_INBOUND = (1 << 6),
183bafec742SSukumar Swaminathan 	FSC_EPC_OUTBOUND = (1 << 7),
184bafec742SSukumar Swaminathan 	FSC_VM_PAGESIZE_MASK = 0x07000000,
185bafec742SSukumar Swaminathan 	FSC_VM_PAGE_2K = 0x00000100,
186bafec742SSukumar Swaminathan 	FSC_VM_PAGE_4K = 0x00000200,
187bafec742SSukumar Swaminathan 	FSC_VM_PAGE_8K = 0x00000300,
188bafec742SSukumar Swaminathan 	FSC_VM_PAGE_64K = 0x00000600,
189bafec742SSukumar Swaminathan 	FSC_SH = (1 << 11),
190bafec742SSukumar Swaminathan 	FSC_DSB = (1 << 12),
191bafec742SSukumar Swaminathan 	FSC_STE = (1 << 13),
192bafec742SSukumar Swaminathan 	FSC_FE = (1 << 15)
193bafec742SSukumar Swaminathan };
194bafec742SSukumar Swaminathan 
195bafec742SSukumar Swaminathan /*
196bafec742SSukumar Swaminathan  * Host Command Status Register (CSR) bit definitions.
197bafec742SSukumar Swaminathan  */
198bafec742SSukumar Swaminathan #define	CSR_ERR_STS_MASK	0x0000003f
199bafec742SSukumar Swaminathan /*
200bafec742SSukumar Swaminathan  * There are no valued defined as of edit #15.
201bafec742SSukumar Swaminathan  */
202bafec742SSukumar Swaminathan #define	CSR_RR			BIT_8
203bafec742SSukumar Swaminathan #define	CSR_HRI			BIT_9
204bafec742SSukumar Swaminathan #define	CSR_RP			BIT_10
205bafec742SSukumar Swaminathan #define	CSR_CMD_PARM_SHIFT	22
206bafec742SSukumar Swaminathan #define	CSR_CMD_NOP		0x00000000
207bafec742SSukumar Swaminathan #define	CSR_CMD_SET_RST		0x1000000
208bafec742SSukumar Swaminathan #define	CSR_CMD_CLR_RST		0x20000000
209bafec742SSukumar Swaminathan #define	CSR_CMD_SET_PAUSE	0x30000000
210bafec742SSukumar Swaminathan #define	CSR_CMD_CLR_PAUSE	0x40000000
211bafec742SSukumar Swaminathan #define	CSR_CMD_SET_H2R_INT	0x50000000
212bafec742SSukumar Swaminathan #define	CSR_CMD_CLR_H2R_INT	0x60000000
213bafec742SSukumar Swaminathan #define	CSR_CMD_PAR_EN		0x70000000
214bafec742SSukumar Swaminathan #define	CSR_CMD_SET_BAD_PAR	0x80000000u
215bafec742SSukumar Swaminathan #define	CSR_CMD_CLR_BAD_PAR	0x90000000u
216bafec742SSukumar Swaminathan #define	CSR_CMD_CLR_R2PCI_INT	0xa0000000u
217bafec742SSukumar Swaminathan 
218bafec742SSukumar Swaminathan /*
219bafec742SSukumar Swaminathan  * Configuration Register (CFG) bit definitions.
220bafec742SSukumar Swaminathan  */
221bafec742SSukumar Swaminathan enum {
222bafec742SSukumar Swaminathan 	CFG_LRQ = (1 << 0),
223bafec742SSukumar Swaminathan 	CFG_DRQ = (1 << 1),
224bafec742SSukumar Swaminathan 	CFG_LR = (1 << 2),
225bafec742SSukumar Swaminathan 	CFG_DR = (1 << 3),
226bafec742SSukumar Swaminathan 	CFG_LE = (1 << 5),
227bafec742SSukumar Swaminathan 	CFG_LCQ = (1 << 6),
228bafec742SSukumar Swaminathan 	CFG_DCQ = (1 << 7),
229bafec742SSukumar Swaminathan 	CFG_Q_SHIFT = 8,
230bafec742SSukumar Swaminathan 	CFG_Q_MASK = 0x7f000000
231bafec742SSukumar Swaminathan };
232bafec742SSukumar Swaminathan 
233bafec742SSukumar Swaminathan /*
234bafec742SSukumar Swaminathan  *  Status Register (STS) bit definitions.
235bafec742SSukumar Swaminathan  */
236bafec742SSukumar Swaminathan enum {
237bafec742SSukumar Swaminathan 	STS_FE = (1 << 0),
238bafec742SSukumar Swaminathan 	STS_PI = (1 << 1),
239bafec742SSukumar Swaminathan 	STS_PL0 = (1 << 2),
240bafec742SSukumar Swaminathan 	STS_PL1 = (1 << 3),
241bafec742SSukumar Swaminathan 	STS_PI0 = (1 << 4),
242bafec742SSukumar Swaminathan 	STS_PI1 = (1 << 5),
243bafec742SSukumar Swaminathan 	STS_FUNC_ID_MASK = 0x000000c0,
244bafec742SSukumar Swaminathan 	STS_FUNC_ID_SHIFT = 6,
245bafec742SSukumar Swaminathan 	STS_F0E = (1 << 8),
246bafec742SSukumar Swaminathan 	STS_F1E = (1 << 9),
247bafec742SSukumar Swaminathan 	STS_F2E = (1 << 10),
248bafec742SSukumar Swaminathan 	STS_F3E = (1 << 11),
249bafec742SSukumar Swaminathan 	STS_NFE = (1 << 12)
250bafec742SSukumar Swaminathan };
251bafec742SSukumar Swaminathan 
252bafec742SSukumar Swaminathan /*
253bafec742SSukumar Swaminathan  * Register (REV_ID) bit definitions.
254bafec742SSukumar Swaminathan  */
255bafec742SSukumar Swaminathan enum {
256bafec742SSukumar Swaminathan 	REV_ID_MASK = 0x0000000f,
257bafec742SSukumar Swaminathan 	REV_ID_NICROLL_SHIFT = 0,
258bafec742SSukumar Swaminathan 	REV_ID_NICREV_SHIFT = 4,
259bafec742SSukumar Swaminathan 	REV_ID_XGROLL_SHIFT = 8,
260bafec742SSukumar Swaminathan 	REV_ID_XGREV_SHIFT = 12,
261bafec742SSukumar Swaminathan 	REV_ID_CHIPREV_SHIFT = 28
262bafec742SSukumar Swaminathan };
263bafec742SSukumar Swaminathan 
264bafec742SSukumar Swaminathan /*
265bafec742SSukumar Swaminathan  *  Force ECC Error Register (FRC_ECC_ERR) bit definitions.
266bafec742SSukumar Swaminathan  */
267bafec742SSukumar Swaminathan enum {
268bafec742SSukumar Swaminathan 	FRC_ECC_ERR_VW = (1 << 12),
269bafec742SSukumar Swaminathan 	FRC_ECC_ERR_VB = (1 << 13),
270bafec742SSukumar Swaminathan 	FRC_ECC_ERR_NI = (1 << 14),
271bafec742SSukumar Swaminathan 	FRC_ECC_ERR_NO = (1 << 15),
272bafec742SSukumar Swaminathan 	FRC_ECC_PFE_SHIFT = 16,
273bafec742SSukumar Swaminathan 	FRC_ECC_ERR_DO = (1 << 18),
274bafec742SSukumar Swaminathan 	FRC_ECC_P14 = (1 << 19)
275bafec742SSukumar Swaminathan };
276bafec742SSukumar Swaminathan 
277bafec742SSukumar Swaminathan /*
278bafec742SSukumar Swaminathan  * Error Status Register (ERR_STS) bit definitions.
279bafec742SSukumar Swaminathan  */
280bafec742SSukumar Swaminathan enum {
281bafec742SSukumar Swaminathan 	ERR_STS_NOF = (1 << 0),
282bafec742SSukumar Swaminathan 	ERR_STS_NIF = (1 << 1),
283bafec742SSukumar Swaminathan 	ERR_STS_DRP = (1 << 2),
284bafec742SSukumar Swaminathan 	ERR_STS_XGP = (1 << 3),
285bafec742SSukumar Swaminathan 	ERR_STS_FOU = (1 << 4),
286bafec742SSukumar Swaminathan 	ERR_STS_FOC = (1 << 5),
287bafec742SSukumar Swaminathan 	ERR_STS_FOF = (1 << 6),
288bafec742SSukumar Swaminathan 	ERR_STS_FIU = (1 << 7),
289bafec742SSukumar Swaminathan 	ERR_STS_FIC = (1 << 8),
290bafec742SSukumar Swaminathan 	ERR_STS_FIF = (1 << 9),
291bafec742SSukumar Swaminathan 	ERR_STS_MOF = (1 << 10),
292bafec742SSukumar Swaminathan 	ERR_STS_TA = (1 << 11),
293bafec742SSukumar Swaminathan 	ERR_STS_MA = (1 << 12),
294bafec742SSukumar Swaminathan 	ERR_STS_MPE = (1 << 13),
295bafec742SSukumar Swaminathan 	ERR_STS_SCE = (1 << 14),
296bafec742SSukumar Swaminathan 	ERR_STS_STE = (1 << 15),
297bafec742SSukumar Swaminathan 	ERR_STS_FOW = (1 << 16),
298bafec742SSukumar Swaminathan 	ERR_STS_UE = (1 << 17),
299bafec742SSukumar Swaminathan 	ERR_STS_MCH = (1 << 26),
300bafec742SSukumar Swaminathan 	ERR_STS_LOC_SHIFT = 27
301bafec742SSukumar Swaminathan };
302bafec742SSukumar Swaminathan 
303bafec742SSukumar Swaminathan /*
304bafec742SSukumar Swaminathan  * Semaphore Register (SEM) bit definitions.
305bafec742SSukumar Swaminathan  */
306bafec742SSukumar Swaminathan /*
307bafec742SSukumar Swaminathan  * Example:
308bafec742SSukumar Swaminathan  * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
309bafec742SSukumar Swaminathan  */
310bafec742SSukumar Swaminathan #define	SEM_CLEAR		0
311bafec742SSukumar Swaminathan #define	SEM_SET			1
312bafec742SSukumar Swaminathan #define	SEM_FORCE		3
313bafec742SSukumar Swaminathan #define	SEM_XGMAC0_SHIFT	0
314bafec742SSukumar Swaminathan #define	SEM_XGMAC1_SHIFT	2
315bafec742SSukumar Swaminathan #define	SEM_ICB_SHIFT		4
316bafec742SSukumar Swaminathan #define	SEM_MAC_ADDR_SHIFT	6
317bafec742SSukumar Swaminathan #define	SEM_FLASH_SHIFT		8
318bafec742SSukumar Swaminathan #define	SEM_PROBE_SHIFT		10
319bafec742SSukumar Swaminathan #define	SEM_RT_IDX_SHIFT	12
320bafec742SSukumar Swaminathan #define	SEM_PROC_REG_SHIFT	14
321bafec742SSukumar Swaminathan #define	SEM_XGMAC0_MASK		0x00030000
322bafec742SSukumar Swaminathan #define	SEM_XGMAC1_MASK		0x000c0000
323bafec742SSukumar Swaminathan #define	SEM_ICB_MASK		0x00300000
324bafec742SSukumar Swaminathan #define	SEM_MAC_ADDR_MASK	0x00c00000
325bafec742SSukumar Swaminathan #define	SEM_FLASH_MASK		0x03000000
326bafec742SSukumar Swaminathan #define	SEM_PROBE_MASK		0x0c000000
327bafec742SSukumar Swaminathan #define	SEM_RT_IDX_MASK		0x30000000
328bafec742SSukumar Swaminathan #define	SEM_PROC_REG_MASK	0xc0000000
329bafec742SSukumar Swaminathan 
330bafec742SSukumar Swaminathan /*
331bafec742SSukumar Swaminathan  * Stop CQ Processing Register (CQ_STOP) bit definitions.
332bafec742SSukumar Swaminathan  */
333bafec742SSukumar Swaminathan enum {
334bafec742SSukumar Swaminathan 	CQ_STOP_QUEUE_MASK = (0x007f0000),
335bafec742SSukumar Swaminathan 	CQ_STOP_TYPE_MASK = (0x03000000),
336bafec742SSukumar Swaminathan 	CQ_STOP_TYPE_START = 0x00000100,
337bafec742SSukumar Swaminathan 	CQ_STOP_TYPE_STOP = 0x00000200,
338bafec742SSukumar Swaminathan 	CQ_STOP_TYPE_READ = 0x00000300,
339bafec742SSukumar Swaminathan 	CQ_STOP_EN = (1 << 15)
340bafec742SSukumar Swaminathan };
341bafec742SSukumar Swaminathan 
342bafec742SSukumar Swaminathan /*
343bafec742SSukumar Swaminathan  * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
344bafec742SSukumar Swaminathan  */
345bafec742SSukumar Swaminathan #define	MAC_ADDR_IDX_SHIFT		4
346bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_SHIFT		16
347bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_MASK 		0x000f0000
348bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_CAM_MAC		0x00000000
349bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_MULTI_MAC		0x00010000
350bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_VLAN		0x00020000
351bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_MULTI_FLTR	0x00030000
352bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_FC_MAC		0x00040000
353bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_MGMT_MAC		0x00050000
354bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_MGMT_VLAN		0x00060000
355bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_MGMT_V4		0x00070000
356bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_MGMT_V6		0x00080000
357bafec742SSukumar Swaminathan #define	MAC_ADDR_TYPE_MGMT_TU_DP	0x00090000
358bafec742SSukumar Swaminathan #define	MAC_ADDR_ADR			BIT_25
359bafec742SSukumar Swaminathan #define	MAC_ADDR_RS			BIT_26
360bafec742SSukumar Swaminathan #define	MAC_ADDR_E  			BIT_27
361bafec742SSukumar Swaminathan #define	MAC_ADDR_MR  			BIT_30
362bafec742SSukumar Swaminathan #define	MAC_ADDR_MW  			BIT_31
363bafec742SSukumar Swaminathan #define	MAX_MULTICAST_HW_SIZE		32
364bafec742SSukumar Swaminathan 
365bafec742SSukumar Swaminathan /*
366bafec742SSukumar Swaminathan  *  MAC Protocol Address Index Register (SPLT_HDR, 0xC0) bit definitions.
367bafec742SSukumar Swaminathan  */
368bafec742SSukumar Swaminathan #define	SPLT_HDR_EP	BIT_31
369bafec742SSukumar Swaminathan 
370bafec742SSukumar Swaminathan /*
371bafec742SSukumar Swaminathan  * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
372bafec742SSukumar Swaminathan  */
373bafec742SSukumar Swaminathan enum {
374bafec742SSukumar Swaminathan 	NIC_RCV_CFG_PPE = (1 << 0),
375bafec742SSukumar Swaminathan 	NIC_RCV_CFG_VLAN_MASK = 0x00060000,
376bafec742SSukumar Swaminathan 	NIC_RCV_CFG_VLAN_ALL = 0x00000000,
377bafec742SSukumar Swaminathan 	NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
378bafec742SSukumar Swaminathan 	NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
379bafec742SSukumar Swaminathan 	NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
380bafec742SSukumar Swaminathan 	NIC_RCV_CFG_RV = (1 << 3),
381bafec742SSukumar Swaminathan 	NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
382bafec742SSukumar Swaminathan 	NIC_RCV_CFG_DFQ_SHIFT = 8,
383bafec742SSukumar Swaminathan 	NIC_RCV_CFG_DFQ = 0	/* HARDCODE default queue to 0. */
384bafec742SSukumar Swaminathan };
385bafec742SSukumar Swaminathan 
386bafec742SSukumar Swaminathan /*
387bafec742SSukumar Swaminathan  * Routing Index Register (RT_IDX) bit definitions.
388bafec742SSukumar Swaminathan  */
389bafec742SSukumar Swaminathan #define	RT_IDX_IDX_SHIFT	8
390bafec742SSukumar Swaminathan #define	RT_IDX_TYPE_MASK	0x000f0000
391bafec742SSukumar Swaminathan #define	RT_IDX_TYPE_RT		0x00000000
392bafec742SSukumar Swaminathan #define	RT_IDX_TYPE_RT_INV	0x00010000
393bafec742SSukumar Swaminathan #define	RT_IDX_TYPE_NICQ	0x00020000
394bafec742SSukumar Swaminathan #define	RT_IDX_TYPE_NICQ_INV	0x00030000
395bafec742SSukumar Swaminathan #define	RT_IDX_DST_MASK		0x00700000
396bafec742SSukumar Swaminathan #define	RT_IDX_DST_RSS		0x00000000
397bafec742SSukumar Swaminathan #define	RT_IDX_DST_CAM_Q	0x00100000
398bafec742SSukumar Swaminathan #define	RT_IDX_DST_COS_Q	0x00200000
399bafec742SSukumar Swaminathan #define	RT_IDX_DST_DFLT_Q	0x00300000
400bafec742SSukumar Swaminathan #define	RT_IDX_DST_DEST_Q	0x00400000
401bafec742SSukumar Swaminathan #define	RT_IDX_RS		BIT_26
402bafec742SSukumar Swaminathan #define	RT_IDX_E		BIT_27
403bafec742SSukumar Swaminathan #define	RT_IDX_MR		BIT_30
404bafec742SSukumar Swaminathan #define	RT_IDX_MW		BIT_31
405bafec742SSukumar Swaminathan 
406bafec742SSukumar Swaminathan /* Nic Queue format - type 2 bits */
407bafec742SSukumar Swaminathan #define	RT_IDX_BCAST		1
408bafec742SSukumar Swaminathan #define	RT_IDX_MCAST		BIT_1
409bafec742SSukumar Swaminathan #define	RT_IDX_MCAST_MATCH	BIT_2
410bafec742SSukumar Swaminathan #define	RT_IDX_MCAST_REG_MATCH	BIT_3
411bafec742SSukumar Swaminathan #define	RT_IDX_MCAST_HASH_MATCH	BIT_4
412bafec742SSukumar Swaminathan #define	RT_IDX_FC_MACH		BIT_5
413bafec742SSukumar Swaminathan #define	RT_IDX_ETH_FCOE		BIT_6
414bafec742SSukumar Swaminathan #define	RT_IDX_CAM_HIT		BIT_7
415bafec742SSukumar Swaminathan #define	RT_IDX_CAM_BIT0		BIT_8
416bafec742SSukumar Swaminathan #define	RT_IDX_CAM_BIT1		BIT_9
417bafec742SSukumar Swaminathan #define	RT_IDX_VLAN_TAG		BIT_10
418bafec742SSukumar Swaminathan #define	RT_IDX_VLAN_MATCH	BIT_11
419bafec742SSukumar Swaminathan #define	RT_IDX_VLAN_FILTER	BIT_12
420bafec742SSukumar Swaminathan #define	RT_IDX_ETH_SKIP1	BIT_13
421bafec742SSukumar Swaminathan #define	RT_IDX_ETH_SKIP2	BIT_14
422bafec742SSukumar Swaminathan #define	RT_IDX_BCAST_MCAST_MATCH	BIT_15
423bafec742SSukumar Swaminathan #define	RT_IDX_802_3		BIT_16
424bafec742SSukumar Swaminathan #define	RT_IDX_LLDP		BIT_17
425bafec742SSukumar Swaminathan #define	RT_IDX_UNUSED018	BIT_18
426bafec742SSukumar Swaminathan #define	RT_IDX_UNUSED019	BIT_19
427bafec742SSukumar Swaminathan #define	RT_IDX_UNUSED20		BIT_20
428bafec742SSukumar Swaminathan #define	RT_IDX_UNUSED21		BIT_21
429bafec742SSukumar Swaminathan #define	RT_IDX_ERR		BIT_22
430bafec742SSukumar Swaminathan #define	RT_IDX_VALID		BIT_23
431bafec742SSukumar Swaminathan #define	RT_IDX_TU_CSUM_ERR	BIT_24
432bafec742SSukumar Swaminathan #define	RT_IDX_IP_CSUM_ERR	BIT_25
433bafec742SSukumar Swaminathan #define	RT_IDX_MAC_ERR		BIT_26
434bafec742SSukumar Swaminathan #define	RT_IDX_RSS_TCP6		BIT_27
435bafec742SSukumar Swaminathan #define	RT_IDX_RSS_TCP4		BIT_28
436bafec742SSukumar Swaminathan #define	RT_IDX_RSS_IPV6		BIT_29
437bafec742SSukumar Swaminathan #define	RT_IDX_RSS_IPV4		BIT_30
438bafec742SSukumar Swaminathan #define	RT_IDX_RSS_MATCH	BIT_31
439bafec742SSukumar Swaminathan 
440bafec742SSukumar Swaminathan /* Hierarchy for the NIC Queue Mask */
441bafec742SSukumar Swaminathan enum {
442bafec742SSukumar Swaminathan 	RT_IDX_ALL_ERR_SLOT = 0,
443bafec742SSukumar Swaminathan 	RT_IDX_MAC_ERR_SLOT = 0,
444bafec742SSukumar Swaminathan 	RT_IDX_IP_CSUM_ERR_SLOT = 1,
445bafec742SSukumar Swaminathan 	RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
446bafec742SSukumar Swaminathan 	RT_IDX_BCAST_SLOT = 3,
447bafec742SSukumar Swaminathan 	RT_IDX_MCAST_MATCH_SLOT = 4,
448bafec742SSukumar Swaminathan 	RT_IDX_ALLMULTI_SLOT = 5,
449bafec742SSukumar Swaminathan 	RT_IDX_UNUSED6_SLOT = 6,
450bafec742SSukumar Swaminathan 	RT_IDX_UNUSED7_SLOT = 7,
451bafec742SSukumar Swaminathan 	RT_IDX_RSS_MATCH_SLOT = 8,
452bafec742SSukumar Swaminathan 	RT_IDX_RSS_IPV4_SLOT = 8,
453bafec742SSukumar Swaminathan 	RT_IDX_RSS_IPV6_SLOT = 9,
454bafec742SSukumar Swaminathan 	RT_IDX_RSS_TCP4_SLOT = 10,
455bafec742SSukumar Swaminathan 	RT_IDX_RSS_TCP6_SLOT = 11,
456bafec742SSukumar Swaminathan 	RT_IDX_CAM_HIT_SLOT = 12,
457bafec742SSukumar Swaminathan 	RT_IDX_UNUSED013 = 13,
458bafec742SSukumar Swaminathan 	RT_IDX_UNUSED014 = 14,
459bafec742SSukumar Swaminathan 	RT_IDX_PROMISCUOUS_SLOT = 15,
460bafec742SSukumar Swaminathan 	RT_IDX_MAX_SLOTS = 16
461bafec742SSukumar Swaminathan };
462bafec742SSukumar Swaminathan 
463bafec742SSukumar Swaminathan enum {
464bafec742SSukumar Swaminathan 	CAM_OUT_ROUTE_FC = 0,
465bafec742SSukumar Swaminathan 	CAM_OUT_ROUTE_NIC = 1,
466bafec742SSukumar Swaminathan 	CAM_OUT_FUNC_SHIFT = 2,
467bafec742SSukumar Swaminathan 	CAM_OUT_RV = (1 << 4),
468bafec742SSukumar Swaminathan 	CAM_OUT_SH = (1 << 15),
469bafec742SSukumar Swaminathan 	CAM_OUT_CQ_ID_SHIFT = 5
470bafec742SSukumar Swaminathan };
471bafec742SSukumar Swaminathan 
472bafec742SSukumar Swaminathan /* Reset/Failover Register 0C */
473bafec742SSukumar Swaminathan #define	FUNCTION_RESET		0x8000u
474bafec742SSukumar Swaminathan #define	FUNCTION_RESET_MASK	(FUNCTION_RESET<<16)
475bafec742SSukumar Swaminathan 
476bafec742SSukumar Swaminathan /* Function Specific Control Register 0x10 */
477bafec742SSukumar Swaminathan #define	FSC_MASK	(0x97ffu << 16)
478bafec742SSukumar Swaminathan #define	FSC_FE		0x8000
479bafec742SSukumar Swaminathan 
480bafec742SSukumar Swaminathan /* Configuration Register 0x28 */
481bafec742SSukumar Swaminathan #define	LOAD_LCQ	0x40
482bafec742SSukumar Swaminathan #define	LOAD_LCQ_MASK	(0x7F40u << 16)
483bafec742SSukumar Swaminathan #define	LOAD_ICB_ERR	0x20
484bafec742SSukumar Swaminathan #define	LOAD_LRQ	0x01
485bafec742SSukumar Swaminathan #define	LOAD_LRQ_MASK	(0x7F01u << 16)
486bafec742SSukumar Swaminathan 
487bafec742SSukumar Swaminathan #define	FN0_NET	0
488bafec742SSukumar Swaminathan #define	FN1_NET	1
489bafec742SSukumar Swaminathan #define	FN0_FC	2
490bafec742SSukumar Swaminathan #define	FN1_FC	3
491bafec742SSukumar Swaminathan 
492bafec742SSukumar Swaminathan /*
493bafec742SSukumar Swaminathan  * Semaphore Register (SEM) bit definitions.
494bafec742SSukumar Swaminathan  */
495bafec742SSukumar Swaminathan #define	SEM_CLEAR		0
496bafec742SSukumar Swaminathan #define	SEM_SET			1
497bafec742SSukumar Swaminathan #define	SEM_FORCE		3
498bafec742SSukumar Swaminathan #define	SEM_XGMAC0_SHIFT	0
499bafec742SSukumar Swaminathan #define	SEM_XGMAC1_SHIFT	2
500bafec742SSukumar Swaminathan #define	SEM_ICB_SHIFT		4
501bafec742SSukumar Swaminathan #define	SEM_MAC_ADDR_SHIFT	6
502bafec742SSukumar Swaminathan #define	SEM_FLASH_SHIFT		8
503bafec742SSukumar Swaminathan #define	SEM_PROBE_SHIFT		10
504bafec742SSukumar Swaminathan #define	SEM_RT_IDX_SHIFT	12
505bafec742SSukumar Swaminathan #define	SEM_PROC_REG_SHIFT	14
506bafec742SSukumar Swaminathan #define	SEM_XGMAC0_MASK		0x00030000
507bafec742SSukumar Swaminathan #define	SEM_XGMAC1_MASK		0x000c0000
508bafec742SSukumar Swaminathan #define	SEM_ICB_MASK		0x00300000
509bafec742SSukumar Swaminathan #define	SEM_MAC_ADDR_MASK	0x00c00000
510bafec742SSukumar Swaminathan #define	SEM_FLASH_MASK		0x03000000
511bafec742SSukumar Swaminathan #define	SEM_PROBE_MASK		0x0c000000
512bafec742SSukumar Swaminathan #define	SEM_RT_IDX_MASK		0x30000000
513bafec742SSukumar Swaminathan #define	SEM_PROC_REG_MASK	0xc0000000
514bafec742SSukumar Swaminathan 
515bafec742SSukumar Swaminathan /* System Register 0x08 */
516bafec742SSukumar Swaminathan #define	SYSTEM_EFE_FAE	0x3u
517bafec742SSukumar Swaminathan #define	SYSTEM_EFE_FAE_MASK	(SYSTEM_EFE_FAE<<16)
518bafec742SSukumar Swaminathan 
519bafec742SSukumar Swaminathan /* Interrupt Status Register-1		0x3C */
520bafec742SSukumar Swaminathan #define	CQ_0_NOT_EMPTY			BIT_0
521bafec742SSukumar Swaminathan #define	CQ_1_NOT_EMPTY			BIT_1
522bafec742SSukumar Swaminathan #define	CQ_2_NOT_EMPTY			BIT_2
523bafec742SSukumar Swaminathan #define	CQ_3_NOT_EMPTY			BIT_3
524bafec742SSukumar Swaminathan #define	CQ_4_NOT_EMPTY			BIT_4
525bafec742SSukumar Swaminathan #define	CQ_5_NOT_EMPTY			BIT_5
526bafec742SSukumar Swaminathan #define	CQ_6_NOT_EMPTY			BIT_6
527bafec742SSukumar Swaminathan #define	CQ_7_NOT_EMPTY			BIT_7
528bafec742SSukumar Swaminathan #define	CQ_8_NOT_EMPTY			BIT_8
529bafec742SSukumar Swaminathan #define	CQ_9_NOT_EMPTY			BIT_9
530bafec742SSukumar Swaminathan #define	CQ_10_NOT_EMPTY			BIT_10
531bafec742SSukumar Swaminathan #define	CQ_11_NOT_EMPTY			BIT_11
532bafec742SSukumar Swaminathan #define	CQ_12_NOT_EMPTY			BIT_12
533bafec742SSukumar Swaminathan #define	CQ_13_NOT_EMPTY			BIT_13
534bafec742SSukumar Swaminathan #define	CQ_14_NOT_EMPTY			BIT_14
535bafec742SSukumar Swaminathan #define	CQ_15_NOT_EMPTY			BIT_15
536bafec742SSukumar Swaminathan #define	CQ_16_NOT_EMPTY			BIT_16
537bafec742SSukumar Swaminathan /* Processor Address Register 0x00 */
538bafec742SSukumar Swaminathan #define	PROCESSOR_ADDRESS_RDY	(0x8000u<<16)
539bafec742SSukumar Swaminathan #define	PROCESSOR_ADDRESS_READ	(0x4000u<<16)
540bafec742SSukumar Swaminathan /* Host Command/Status Register 0x14 */
541bafec742SSukumar Swaminathan #define	HOST_CMD_SET_RISC_RESET			0x10000000u
542bafec742SSukumar Swaminathan #define	HOST_CMD_CLEAR_RISC_RESET		0x20000000u
543bafec742SSukumar Swaminathan #define	HOST_CMD_SET_RISC_PAUSE			0x30000000u
544bafec742SSukumar Swaminathan #define	HOST_CMD_RELEASE_RISC_PAUSE		0x40000000u
545bafec742SSukumar Swaminathan #define	HOST_CMD_SET_RISC_INTR			0x50000000u
546bafec742SSukumar Swaminathan #define	HOST_CMD_CLEAR_RISC_INTR		0x60000000u
547bafec742SSukumar Swaminathan #define	HOST_CMD_SET_PARITY_ENABLE		0x70000000u
548bafec742SSukumar Swaminathan #define	HOST_CMD_FORCE_BAD_PARITY		0x80000000u
549bafec742SSukumar Swaminathan #define	HOST_CMD_RELEASE_BAD_PARITY		0x90000000u
550bafec742SSukumar Swaminathan #define	HOST_CMD_CLEAR_RISC_TO_HOST_INTR	0xA0000000u
551bafec742SSukumar Swaminathan #define	HOST_TO_MPI_INTR_NOT_DONE		0x200
552bafec742SSukumar Swaminathan 
553bafec742SSukumar Swaminathan #define	RISC_RESET			BIT_8
554bafec742SSukumar Swaminathan #define	RISC_PAUSED			BIT_10
555bafec742SSukumar Swaminathan /* Semaphor Register 0x64 */
556bafec742SSukumar Swaminathan #define	QL_SEM_BITS_BASE_CODE		0x1u
557bafec742SSukumar Swaminathan #define	QL_PORT0_XGMAC_SEM_BITS		(QL_SEM_BITS_BASE_CODE)
558bafec742SSukumar Swaminathan #define	QL_PORT1_XGMAC_SEM_BITS		(QL_SEM_BITS_BASE_CODE << 2)
559bafec742SSukumar Swaminathan #define	QL_ICB_ACCESS_ADDRESS_SEM_BITS	(QL_SEM_BITS_BASE_CODE << 4)
560bafec742SSukumar Swaminathan #define	QL_MAC_PROTOCOL_SEM_BITS	(QL_SEM_BITS_BASE_CODE << 6)
561bafec742SSukumar Swaminathan #define	QL_FLASH_SEM_BITS		(QL_SEM_BITS_BASE_CODE << 8)
562bafec742SSukumar Swaminathan #define	QL_PROBE_MUX_SEM_BITS		(QL_SEM_BITS_BASE_CODE << 10)
563bafec742SSukumar Swaminathan #define	QL_ROUTING_INDEX_SEM_BITS	(QL_SEM_BITS_BASE_CODE << 12)
564bafec742SSukumar Swaminathan #define	QL_PROCESSOR_SEM_BITS		(QL_SEM_BITS_BASE_CODE << 14)
565bafec742SSukumar Swaminathan #define	QL_NIC_RECV_CONFIG_SEM_BITS	(QL_SEM_BITS_BASE_CODE << 14)
566bafec742SSukumar Swaminathan 
567bafec742SSukumar Swaminathan #define	QL_SEM_MASK_BASE_CODE		0x30000u
568bafec742SSukumar Swaminathan #define	QL_PORT0_XGMAC_SEM_MASK		(QL_SEM_MASK_BASE_CODE)
569bafec742SSukumar Swaminathan #define	QL_PORT1_XGMAC_SEM_MASK		(QL_SEM_MASK_BASE_CODE << 2)
570bafec742SSukumar Swaminathan #define	QL_ICB_ACCESS_ADDRESS_SEM_MASK	(QL_SEM_MASK_BASE_CODE << 4)
571bafec742SSukumar Swaminathan #define	QL_MAC_PROTOCOL_SEM_MASK	(QL_SEM_MASK_BASE_CODE << 6)
572bafec742SSukumar Swaminathan #define	QL_FLASH_SEM_MASK		(QL_SEM_MASK_BASE_CODE << 8)
573bafec742SSukumar Swaminathan #define	QL_PROBE_MUX_SEM_MASK		(QL_SEM_MASK_BASE_CODE << 10)
574bafec742SSukumar Swaminathan #define	QL_ROUTING_INDEX_SEM_MASK	(QL_SEM_MASK_BASE_CODE << 12)
575bafec742SSukumar Swaminathan #define	QL_PROCESSOR_SEM_MASK		(QL_SEM_MASK_BASE_CODE << 14)
576bafec742SSukumar Swaminathan #define	QL_NIC_RECV_CONFIG_SEM_MASK	(QL_SEM_MASK_BASE_CODE << 14)
577bafec742SSukumar Swaminathan 
578bafec742SSukumar Swaminathan /* XGMAC Address Register 0x78 */
579bafec742SSukumar Swaminathan #define	XGMAC_ADDRESS_RDY		(0x8000u<<16)
580bafec742SSukumar Swaminathan #define	XGMAC_ADDRESS_READ_TRANSACT	(0x4000u<<16)
581bafec742SSukumar Swaminathan #define	XGMAC_ADDRESS_ACCESS_ERROR	(0x2000u<<16)
582bafec742SSukumar Swaminathan 
583bafec742SSukumar Swaminathan /* XGMAC Register Set */
584bafec742SSukumar Swaminathan #define	REG_XGMAC_GLOBAL_CONFIGURATION	0x108
585bafec742SSukumar Swaminathan #define	GLOBAL_CONFIG_JUMBO_MODE	0x40
586bafec742SSukumar Swaminathan 
587bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_TX_CONFIGURATION	0x10C
588bafec742SSukumar Swaminathan #define	XGMAC_MAC_TX_ENABLE		0x02
589bafec742SSukumar Swaminathan 
590bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_CONFIGURATION	0x110
591bafec742SSukumar Swaminathan #define	XGMAC_MAC_RX_ENABLE		0x02
592bafec742SSukumar Swaminathan 
593bafec742SSukumar Swaminathan #define	REG_XGMAC_FLOW_CONTROL		0x11C
594bafec742SSukumar Swaminathan 
595bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_TX_PARAM		0x134
596bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_PARAM		0x138
597bafec742SSukumar Swaminathan 
598bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_TX_PKTS		0x200
599bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_TX_OCTETS		0x208
600bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_TX_MULTCAST_PKTS	0x210
601bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_TX_BROADCAST_PKTS	0x218
602bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_TX_PAUSE_PKTS	0x230
603bafec742SSukumar Swaminathan 
604bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_OCTETS		0x300
605bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_OCTETS_OK	0x308
606bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_PKTS		0x310
607bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_PKTS_OK	0x318
608bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_BROADCAST_PKTS	0x320
609bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_MULTCAST_PKTS	0x328
610bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_JABBER_PKTS	0x348
611bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_FCS_ERR		0x360
612bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_ALIGN_ERR		0x368
613bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_SYM_ERR	0x370
614bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_INT_ERR	0x378
615bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_PAUSE_PKTS	0x388
616bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_PHY_ADDR		0x430
617bafec742SSukumar Swaminathan #define	REG_XGMAC_MAC_RX_FIFO_DROPS	0x5B8
618bafec742SSukumar Swaminathan 
619bafec742SSukumar Swaminathan 
620bafec742SSukumar Swaminathan /* MAC Protocol Address Index Register Set 0xA8 */
621bafec742SSukumar Swaminathan #define	MAC_PROTOCOL_ADDRESS_INDEX_MW	(0x8000u<<16)
622bafec742SSukumar Swaminathan #define	MAC_PROTOCOL_ADDRESS_ENABLE	(1 << 27)
623bafec742SSukumar Swaminathan #define	MAC_PROTOCOL_TYPE_CAM_MAC	(0x0)
624bafec742SSukumar Swaminathan #define	MAC_PROTOCOL_TYPE_MULTICAST	(0x10000u)
625bafec742SSukumar Swaminathan 
626bafec742SSukumar Swaminathan /* NIC Receive Configuration Register 0xD4 */
627bafec742SSukumar Swaminathan #define	RECV_CONFIG_DEFAULT_Q_MASK	(0x7F000000u)
628bafec742SSukumar Swaminathan #define	RECV_CONFIG_VTAG_REMOVAL_MASK	(0x80000u)
629bafec742SSukumar Swaminathan #define	RECV_CONFIG_VTAG_RV		0x08
630bafec742SSukumar Swaminathan 
631bafec742SSukumar Swaminathan /*
632bafec742SSukumar Swaminathan  *  10G MAC Address  Register (XGMAC_ADDR) bit definitions.
633bafec742SSukumar Swaminathan  */
634bafec742SSukumar Swaminathan #define	XGMAC_ADDR_RDY	(1 << 31)
635bafec742SSukumar Swaminathan #define	XGMAC_ADDR_R	(1 << 30)
636bafec742SSukumar Swaminathan #define	XGMAC_ADDR_XME	(1 << 29)
637bafec742SSukumar Swaminathan 
638bafec742SSukumar Swaminathan #define	PAUSE_SRC_LO			0x00000100
639bafec742SSukumar Swaminathan #define	PAUSE_SRC_HI			0x00000104
640bafec742SSukumar Swaminathan #define	GLOBAL_CFG			0x00000108
641bafec742SSukumar Swaminathan #define	GLOBAL_CFG_RESET		(1 << 0)
642bafec742SSukumar Swaminathan #define	GLOBAL_CFG_JUMBO		(1 << 6)
643bafec742SSukumar Swaminathan #define	GLOBAL_CFG_TX_STAT_EN		(1 << 10)
644bafec742SSukumar Swaminathan #define	GLOBAL_CFG_RX_STAT_EN		(1 << 11)
645bafec742SSukumar Swaminathan #define	TX_CFG				0x0000010c
646bafec742SSukumar Swaminathan #define	TX_CFG_RESET			(1 << 0)
647bafec742SSukumar Swaminathan #define	TX_CFG_EN			(1 << 1)
648bafec742SSukumar Swaminathan #define	TX_CFG_PREAM			(1 << 2)
649bafec742SSukumar Swaminathan #define	RX_CFG				0x00000110
650bafec742SSukumar Swaminathan #define	RX_CFG_RESET			(1 << 0)
651bafec742SSukumar Swaminathan #define	RX_CFG_EN			(1 << 1)
652bafec742SSukumar Swaminathan #define	RX_CFG_PREAM			(1 << 2)
653bafec742SSukumar Swaminathan #define	FLOW_CTL			0x0000011c
654bafec742SSukumar Swaminathan #define	PAUSE_OPCODE			0x00000120
655bafec742SSukumar Swaminathan #define	PAUSE_TIMER			0x00000124
656bafec742SSukumar Swaminathan #define	PAUSE_FRM_DEST_LO		0x00000128
657bafec742SSukumar Swaminathan #define	PAUSE_FRM_DEST_HI		0x0000012c
658bafec742SSukumar Swaminathan #define	MAC_TX_PARAMS			0x00000134
659bafec742SSukumar Swaminathan #define	MAC_TX_PARAMS_JUMBO		(1 << 31)
660bafec742SSukumar Swaminathan #define	MAC_TX_PARAMS_SIZE_SHIFT	16
661bafec742SSukumar Swaminathan #define	MAC_RX_PARAMS			0x00000138
662bafec742SSukumar Swaminathan #define	MAC_SYS_INT			0x00000144
663bafec742SSukumar Swaminathan #define	MAC_SYS_INT_MASK		0x00000148
664bafec742SSukumar Swaminathan #define	MAC_MGMT_INT			0x0000014c
665bafec742SSukumar Swaminathan #define	MAC_MGMT_IN_MASK		0x00000150
666bafec742SSukumar Swaminathan #define	EXT_ARB_MODE			0x000001fc
667bafec742SSukumar Swaminathan #define	TX_PKTS				0x00000200
668bafec742SSukumar Swaminathan #define	TX_PKTS_LO			0x00000204
669bafec742SSukumar Swaminathan #define	TX_BYTES			0x00000208
670bafec742SSukumar Swaminathan #define	TX_BYTES_LO			0x0000020C
671bafec742SSukumar Swaminathan #define	TX_MCAST_PKTS			0x00000210
672bafec742SSukumar Swaminathan #define	TX_MCAST_PKTS_LO		0x00000214
673bafec742SSukumar Swaminathan #define	TX_BCAST_PKTS			0x00000218
674bafec742SSukumar Swaminathan #define	TX_BCAST_PKTS_LO		0x0000021C
675bafec742SSukumar Swaminathan #define	TX_UCAST_PKTS			0x00000220
676bafec742SSukumar Swaminathan #define	TX_UCAST_PKTS_LO		0x00000224
677bafec742SSukumar Swaminathan #define	TX_CTL_PKTS			0x00000228
678bafec742SSukumar Swaminathan #define	TX_CTL_PKTS_LO			0x0000022c
679bafec742SSukumar Swaminathan #define	TX_PAUSE_PKTS			0x00000230
680bafec742SSukumar Swaminathan #define	TX_PAUSE_PKTS_LO		0x00000234
681bafec742SSukumar Swaminathan #define	TX_64_PKT			0x00000238
682bafec742SSukumar Swaminathan #define	TX_64_PKT_LO			0x0000023c
683bafec742SSukumar Swaminathan #define	TX_65_TO_127_PKT		0x00000240
684bafec742SSukumar Swaminathan #define	TX_65_TO_127_PKT_LO		0x00000244
685bafec742SSukumar Swaminathan #define	TX_128_TO_255_PKT		0x00000248
686bafec742SSukumar Swaminathan #define	TX_128_TO_255_PKT_LO		0x0000024c
687bafec742SSukumar Swaminathan #define	TX_256_511_PKT			0x00000250
688bafec742SSukumar Swaminathan #define	TX_256_511_PKT_LO		0x00000254
689bafec742SSukumar Swaminathan #define	TX_512_TO_1023_PKT		0x00000258
690bafec742SSukumar Swaminathan #define	TX_512_TO_1023_PKT_LO		0x0000025c
691bafec742SSukumar Swaminathan #define	TX_1024_TO_1518_PKT		0x00000260
692bafec742SSukumar Swaminathan #define	TX_1024_TO_1518_PKT_LO		0x00000264
693bafec742SSukumar Swaminathan #define	TX_1519_TO_MAX_PKT		0x00000268
694bafec742SSukumar Swaminathan #define	TX_1519_TO_MAX_PKT_LO		0x0000026c
695bafec742SSukumar Swaminathan #define	TX_UNDERSIZE_PKT		0x00000270
696bafec742SSukumar Swaminathan #define	TX_UNDERSIZE_PKT_LO		0x00000274
697bafec742SSukumar Swaminathan #define	TX_OVERSIZE_PKT			0x00000278
698bafec742SSukumar Swaminathan #define	TX_OVERSIZE_PKT_LO		0x0000027c
699bafec742SSukumar Swaminathan #define	RX_HALF_FULL_DET		0x000002a0
700bafec742SSukumar Swaminathan #define	TX_HALF_FULL_DET_LO		0x000002a4
701bafec742SSukumar Swaminathan #define	RX_OVERFLOW_DET			0x000002a8
702bafec742SSukumar Swaminathan #define	TX_OVERFLOW_DET_LO		0x000002ac
703bafec742SSukumar Swaminathan #define	RX_HALF_FULL_MASK		0x000002b0
704bafec742SSukumar Swaminathan #define	TX_HALF_FULL_MASK_LO		0x000002b4
705bafec742SSukumar Swaminathan #define	RX_OVERFLOW_MASK		0x000002b8
706bafec742SSukumar Swaminathan #define	TX_OVERFLOW_MASK_LO		0x000002bc
707bafec742SSukumar Swaminathan #define	STAT_CNT_CTL			0x000002c0
708bafec742SSukumar Swaminathan #define	STAT_CNT_CTL_CLEAR_TX		(1 << 0)	/* Control */
709bafec742SSukumar Swaminathan #define	STAT_CNT_CTL_CLEAR_RX		(1 << 1)	/* Control */
710bafec742SSukumar Swaminathan #define	AUX_RX_HALF_FULL_DET		0x000002d0
711bafec742SSukumar Swaminathan #define	AUX_TX_HALF_FULL_DET		0x000002d4
712bafec742SSukumar Swaminathan #define	AUX_RX_OVERFLOW_DET		0x000002d8
713bafec742SSukumar Swaminathan #define	AUX_TX_OVERFLOW_DET		0x000002dc
714bafec742SSukumar Swaminathan #define	AUX_RX_HALF_FULL_MASK		0x000002f0
715bafec742SSukumar Swaminathan #define	AUX_TX_HALF_FULL_MASK		0x000002f4
716bafec742SSukumar Swaminathan #define	AUX_RX_OVERFLOW_MASK		0x000002f8
717bafec742SSukumar Swaminathan #define	AUX_TX_OVERFLOW_MASK		0x000002fc
718bafec742SSukumar Swaminathan #define	RX_BYTES			0x00000300
719bafec742SSukumar Swaminathan #define	RX_BYTES_LO			0x00000304
720bafec742SSukumar Swaminathan #define	RX_BYTES_OK			0x00000308
721bafec742SSukumar Swaminathan #define	RX_BYTES_OK_LO			0x0000030c
722bafec742SSukumar Swaminathan #define	RX_PKTS				0x00000310
723bafec742SSukumar Swaminathan #define	RX_PKTS_LO			0x00000314
724bafec742SSukumar Swaminathan #define	RX_PKTS_OK			0x00000318
725bafec742SSukumar Swaminathan #define	RX_PKTS_OK_LO			0x0000031c
726bafec742SSukumar Swaminathan #define	RX_BCAST_PKTS			0x00000320
727bafec742SSukumar Swaminathan #define	RX_BCAST_PKTS_LO		0x00000324
728bafec742SSukumar Swaminathan #define	RX_MCAST_PKTS			0x00000328
729bafec742SSukumar Swaminathan #define	RX_MCAST_PKTS_LO		0x0000032c
730bafec742SSukumar Swaminathan #define	RX_UCAST_PKTS			0x00000330
731bafec742SSukumar Swaminathan #define	RX_UCAST_PKTS_LO		0x00000334
732bafec742SSukumar Swaminathan #define	RX_UNDERSIZE_PKTS		0x00000338
733bafec742SSukumar Swaminathan #define	RX_UNDERSIZE_PKTS_LO		0x0000033c
734bafec742SSukumar Swaminathan #define	RX_OVERSIZE_PKTS		0x00000340
735bafec742SSukumar Swaminathan #define	RX_OVERSIZE_PKTS_LO		0x00000344
736bafec742SSukumar Swaminathan #define	RX_JABBER_PKTS			0x00000348
737bafec742SSukumar Swaminathan #define	RX_JABBER_PKTS_LO		0x0000034c
738bafec742SSukumar Swaminathan #define	RX_UNDERSIZE_FCERR_PKTS		0x00000350
739bafec742SSukumar Swaminathan #define	RX_UNDERSIZE_FCERR_PKTS_LO	0x00000354
740bafec742SSukumar Swaminathan #define	RX_DROP_EVENTS			0x00000358
741bafec742SSukumar Swaminathan #define	RX_DROP_EVENTS_LO		0x0000035c
742bafec742SSukumar Swaminathan #define	RX_FCERR_PKTS			0x00000360
743bafec742SSukumar Swaminathan #define	RX_FCERR_PKTS_LO		0x00000364
744bafec742SSukumar Swaminathan #define	RX_ALIGN_ERR			0x00000368
745bafec742SSukumar Swaminathan #define	RX_ALIGN_ERR_LO			0x0000036c
746bafec742SSukumar Swaminathan #define	RX_SYMBOL_ERR			0x00000370
747bafec742SSukumar Swaminathan #define	RX_SYMBOL_ERR_LO		0x00000374
748bafec742SSukumar Swaminathan #define	RX_MAC_ERR			0x00000378
749bafec742SSukumar Swaminathan #define	RX_MAC_ERR_LO			0x0000037c
750bafec742SSukumar Swaminathan #define	RX_CTL_PKTS			0x00000380
751bafec742SSukumar Swaminathan #define	RX_CTL_PKTS_LO			0x00000384
752bafec742SSukumar Swaminathan #define	RX_PAUSE_PKTS			0x00000388
753bafec742SSukumar Swaminathan #define	RX_PAUSE_PKTS_LO		0x0000038c
754bafec742SSukumar Swaminathan #define	RX_64_PKTS			0x00000390
755bafec742SSukumar Swaminathan #define	RX_64_PKTS_LO			0x00000394
756bafec742SSukumar Swaminathan #define	RX_65_TO_127_PKTS		0x00000398
757bafec742SSukumar Swaminathan #define	RX_65_TO_127_PKTS_LO		0x0000039c
758bafec742SSukumar Swaminathan #define	RX_128_255_PKTS			0x000003a0
759bafec742SSukumar Swaminathan #define	RX_128_255_PKTS_LO		0x000003a4
760bafec742SSukumar Swaminathan #define	RX_256_511_PKTS			0x000003a8
761bafec742SSukumar Swaminathan #define	RX_256_511_PKTS_LO		0x000003ac
762bafec742SSukumar Swaminathan #define	RX_512_TO_1023_PKTS		0x000003b0
763bafec742SSukumar Swaminathan #define	RX_512_TO_1023_PKTS_LO		0x000003b4
764bafec742SSukumar Swaminathan #define	RX_1024_TO_1518_PKTS		0x000003b8
765bafec742SSukumar Swaminathan #define	RX_1024_TO_1518_PKTS_LO		0x000003bc
766bafec742SSukumar Swaminathan #define	RX_1519_TO_MAX_PKTS		0x000003c0
767bafec742SSukumar Swaminathan #define	RX_1519_TO_MAX_PKTS_LO		0x000003c4
768bafec742SSukumar Swaminathan #define	RX_LEN_ERR_PKTS			0x000003c8
769bafec742SSukumar Swaminathan #define	RX_LEN_ERR_PKTS_LO		0x000003cc
770bafec742SSukumar Swaminathan #define	MDIO_TX_DATA			0x00000400
771bafec742SSukumar Swaminathan #define	MDIO_RX_DATA			0x00000410
772bafec742SSukumar Swaminathan #define	MDIO_CMD			0x00000420
773bafec742SSukumar Swaminathan #define	MDIO_PHY_ADDR			0x00000430
774bafec742SSukumar Swaminathan #define	MDIO_PORT			0x00000440
775bafec742SSukumar Swaminathan #define	MDIO_STATUS			0x00000450
776bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES0		0x00000500
777bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES0_LO	0x00000504
778bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES1		0x00000508
779bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES1_LO	0x0000050C
780bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES2		0x00000510
781bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES2_LO	0x00000514
782bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES3		0x00000518
783bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES3_LO	0x0000051C
784bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES4		0x00000520
785bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES4_LO	0x00000524
786bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES5		0x00000528
787bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES5_LO	0x0000052C
788bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES6		0x00000530
789bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES6_LO	0x00000534
790bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES7		0x00000538
791bafec742SSukumar Swaminathan #define	TX_CBFC_PAUSE_FRAMES7_LO	0x0000053C
792bafec742SSukumar Swaminathan #define	TX_FCOE_PKTS			0x00000540
793bafec742SSukumar Swaminathan #define	TX_FCOE_PKTS_LO			0x00000544
794bafec742SSukumar Swaminathan #define	TX_MGMT_PKTS			0x00000548
795bafec742SSukumar Swaminathan #define	TX_MGMT_PKTS_LO			0x0000054C
796bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES0		0x00000568
797bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES0_LO	0x0000056C
798bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES1		0x00000570
799bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES1_LO	0x00000574
800bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES2		0x00000578
801bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES2_LO	0x0000057C
802bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES3		0x00000580
803bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES3_LO	0x00000584
804bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES4		0x00000588
805bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES4_LO	0x0000058C
806bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES5		0x00000590
807bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES5_LO	0x00000594
808bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES6		0x00000598
809bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES6_LO	0x0000059C
810bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES7		0x000005A0
811bafec742SSukumar Swaminathan #define	RX_CBFC_PAUSE_FRAMES7_LO	0x000005A4
812bafec742SSukumar Swaminathan #define	RX_FCOE_PKTS			0x000005A8
813bafec742SSukumar Swaminathan #define	RX_FCOE_PKTS_LO			0x000005AC
814bafec742SSukumar Swaminathan #define	RX_MGMT_PKTS			0x000005B0
815bafec742SSukumar Swaminathan #define	RX_MGMT_PKTS_LO			0x000005B4
816bafec742SSukumar Swaminathan #define	RX_NIC_FIFO_DROP		0x000005B8
817bafec742SSukumar Swaminathan #define	RX_NIC_FIFO_DROP_LO		0x000005BC
818bafec742SSukumar Swaminathan #define	RX_FCOE_FIFO_DROP		0x000005C0
819bafec742SSukumar Swaminathan #define	RX_FCOE_FIFO_DROP_LO		0x000005C4
820bafec742SSukumar Swaminathan #define	RX_MGMT_FIFO_DROP		0x000005C8
821bafec742SSukumar Swaminathan #define	RX_MGMT_FIFO_DROP_LO		0x000005CC
822bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY0		0x00000600
823bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY0_LO		0x00000604
824bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY1		0x00000608
825bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY1_LO		0x0000060C
826bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY2		0x00000610
827bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY2_LO		0x00000614
828bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY3		0x00000618
829bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY3_LO		0x0000061C
830bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY4		0x00000620
831bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY4_LO		0x00000624
832bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY5		0x00000628
833bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY5_LO		0x0000062C
834bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY6		0x00000630
835bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY6_LO		0x00000634
836bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY7		0x00000638
837bafec742SSukumar Swaminathan #define	RX_PKTS_PRIORITY7_LO		0x0000063C
838bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY0		0x00000640
839bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY0_LO		0x00000644
840bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY1		0x00000648
841bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY1_LO		0x0000064C
842bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY2		0x00000650
843bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY2_LO		0x00000654
844bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY3		0x00000658
845bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY3_LO		0x0000065C
846bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY4		0x00000660
847bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY4_LO		0x00000664
848bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY5		0x00000668
849bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY5_LO		0x0000066C
850bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY6		0x00000670
851bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY6_LO		0x00000674
852bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY7		0x00000678
853bafec742SSukumar Swaminathan #define	RX_OCTETS_PRIORITY7_LO		0x0000067C
854bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY0		0x00000680
855bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY0_LO		0x00000684
856bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY1		0x00000688
857bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY1_LO		0x0000068C
858bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY2		0x00000690
859bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY2_LO		0x00000694
860bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY3		0x00000698
861bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY3_LO		0x0000069C
862bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY4		0x000006A0
863bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY4_LO		0x000006A4
864bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY5		0x000006A8
865bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY5_LO		0x000006AC
866bafec742SSukumar Swaminathan #define	TX_PKTS_PRIORITY6		0x000006B0
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