1*bafec742SSukumar Swaminathan /* 2*bafec742SSukumar Swaminathan * CDDL HEADER START 3*bafec742SSukumar Swaminathan * 4*bafec742SSukumar Swaminathan * The contents of this file are subject to the terms of the 5*bafec742SSukumar Swaminathan * Common Development and Distribution License (the "License"). 6*bafec742SSukumar Swaminathan * You may not use this file except in compliance with the License. 7*bafec742SSukumar Swaminathan * 8*bafec742SSukumar Swaminathan * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*bafec742SSukumar Swaminathan * or http://www.opensolaris.org/os/licensing. 10*bafec742SSukumar Swaminathan * See the License for the specific language governing permissions 11*bafec742SSukumar Swaminathan * and limitations under the License. 12*bafec742SSukumar Swaminathan * 13*bafec742SSukumar Swaminathan * When distributing Covered Code, include this CDDL HEADER in each 14*bafec742SSukumar Swaminathan * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*bafec742SSukumar Swaminathan * If applicable, add the following below this CDDL HEADER, with the 16*bafec742SSukumar Swaminathan * fields enclosed by brackets "[]" replaced with your own identifying 17*bafec742SSukumar Swaminathan * information: Portions Copyright [yyyy] [name of copyright owner] 18*bafec742SSukumar Swaminathan * 19*bafec742SSukumar Swaminathan * CDDL HEADER END 20*bafec742SSukumar Swaminathan */ 21*bafec742SSukumar Swaminathan 22*bafec742SSukumar Swaminathan /* 23*bafec742SSukumar Swaminathan * Copyright 2009 QLogic Corporation. All rights reserved. 24*bafec742SSukumar Swaminathan */ 25*bafec742SSukumar Swaminathan 26*bafec742SSukumar Swaminathan #ifndef _QLGE_HW_H 27*bafec742SSukumar Swaminathan #define _QLGE_HW_H 28*bafec742SSukumar Swaminathan 29*bafec742SSukumar Swaminathan #ifdef __cplusplus 30*bafec742SSukumar Swaminathan extern "C" { 31*bafec742SSukumar Swaminathan #endif 32*bafec742SSukumar Swaminathan 33*bafec742SSukumar Swaminathan #define ISP_SCHULTZ 0x8000 34*bafec742SSukumar Swaminathan 35*bafec742SSukumar Swaminathan #define MB_REG_COUNT 8 36*bafec742SSukumar Swaminathan #define MB_DATA_REG_COUNT (MB_REG_COUNT-1) 37*bafec742SSukumar Swaminathan 38*bafec742SSukumar Swaminathan 39*bafec742SSukumar Swaminathan #define QLA_SCHULTZ(qlge) ((qlge)->device_id == ISP_SCHULTZ) 40*bafec742SSukumar Swaminathan 41*bafec742SSukumar Swaminathan /* 42*bafec742SSukumar Swaminathan * Data bit definitions. 43*bafec742SSukumar Swaminathan */ 44*bafec742SSukumar Swaminathan #define BIT_0 0x1 45*bafec742SSukumar Swaminathan #define BIT_1 0x2 46*bafec742SSukumar Swaminathan #define BIT_2 0x4 47*bafec742SSukumar Swaminathan #define BIT_3 0x8 48*bafec742SSukumar Swaminathan #define BIT_4 0x10 49*bafec742SSukumar Swaminathan #define BIT_5 0x20 50*bafec742SSukumar Swaminathan #define BIT_6 0x40 51*bafec742SSukumar Swaminathan #define BIT_7 0x80 52*bafec742SSukumar Swaminathan #define BIT_8 0x100 53*bafec742SSukumar Swaminathan #define BIT_9 0x200 54*bafec742SSukumar Swaminathan #define BIT_10 0x400 55*bafec742SSukumar Swaminathan #define BIT_11 0x800 56*bafec742SSukumar Swaminathan #define BIT_12 0x1000 57*bafec742SSukumar Swaminathan #define BIT_13 0x2000 58*bafec742SSukumar Swaminathan #define BIT_14 0x4000 59*bafec742SSukumar Swaminathan #define BIT_15 0x8000 60*bafec742SSukumar Swaminathan #define BIT_16 0x10000 61*bafec742SSukumar Swaminathan #define BIT_17 0x20000 62*bafec742SSukumar Swaminathan #define BIT_18 0x40000 63*bafec742SSukumar Swaminathan #define BIT_19 0x80000 64*bafec742SSukumar Swaminathan #define BIT_20 0x100000 65*bafec742SSukumar Swaminathan #define BIT_21 0x200000 66*bafec742SSukumar Swaminathan #define BIT_22 0x400000 67*bafec742SSukumar Swaminathan #define BIT_23 0x800000 68*bafec742SSukumar Swaminathan #define BIT_24 0x1000000 69*bafec742SSukumar Swaminathan #define BIT_25 0x2000000 70*bafec742SSukumar Swaminathan #define BIT_26 0x4000000 71*bafec742SSukumar Swaminathan #define BIT_27 0x8000000 72*bafec742SSukumar Swaminathan #define BIT_28 0x10000000 73*bafec742SSukumar Swaminathan #define BIT_29 0x20000000 74*bafec742SSukumar Swaminathan #define BIT_30 0x40000000 75*bafec742SSukumar Swaminathan #define BIT_31 0x80000000 76*bafec742SSukumar Swaminathan 77*bafec742SSukumar Swaminathan typedef struct ql_stats 78*bafec742SSukumar Swaminathan { 79*bafec742SSukumar Swaminathan uint32_t intr_type; 80*bafec742SSukumar Swaminathan /* software statics */ 81*bafec742SSukumar Swaminathan uint32_t intr; 82*bafec742SSukumar Swaminathan uint64_t speed; 83*bafec742SSukumar Swaminathan uint32_t duplex; 84*bafec742SSukumar Swaminathan uint32_t media; 85*bafec742SSukumar Swaminathan /* TX */ 86*bafec742SSukumar Swaminathan uint64_t obytes; 87*bafec742SSukumar Swaminathan uint64_t opackets; 88*bafec742SSukumar Swaminathan uint32_t nocarrier; 89*bafec742SSukumar Swaminathan uint32_t defer; 90*bafec742SSukumar Swaminathan /* RX */ 91*bafec742SSukumar Swaminathan uint64_t rbytes; 92*bafec742SSukumar Swaminathan uint64_t rpackets; 93*bafec742SSukumar Swaminathan uint32_t norcvbuf; 94*bafec742SSukumar Swaminathan uint32_t frame_too_long; 95*bafec742SSukumar Swaminathan uint32_t crc; 96*bafec742SSukumar Swaminathan ulong_t multircv; 97*bafec742SSukumar Swaminathan ulong_t brdcstrcv; 98*bafec742SSukumar Swaminathan uint32_t errrcv; 99*bafec742SSukumar Swaminathan uint32_t frame_too_short; 100*bafec742SSukumar Swaminathan /* statics by hw */ 101*bafec742SSukumar Swaminathan uint32_t errxmt; 102*bafec742SSukumar Swaminathan uint32_t frame_err; 103*bafec742SSukumar Swaminathan ulong_t multixmt; 104*bafec742SSukumar Swaminathan ulong_t brdcstxmt; 105*bafec742SSukumar Swaminathan uint32_t phy_addr; 106*bafec742SSukumar Swaminathan uint32_t jabber_err; 107*bafec742SSukumar Swaminathan 108*bafec742SSukumar Swaminathan }ql_stats_t; 109*bafec742SSukumar Swaminathan 110*bafec742SSukumar Swaminathan 111*bafec742SSukumar Swaminathan #define ETHERNET_CRC_SIZE 4 112*bafec742SSukumar Swaminathan 113*bafec742SSukumar Swaminathan /* 114*bafec742SSukumar Swaminathan * Register Definitions... 115*bafec742SSukumar Swaminathan */ 116*bafec742SSukumar Swaminathan #define MAILBOX_COUNT 16 117*bafec742SSukumar Swaminathan /* System Register 0x00 */ 118*bafec742SSukumar Swaminathan #define PROC_ADDR_RDY BIT_31 119*bafec742SSukumar Swaminathan #define PROC_ADDR_R BIT_30 120*bafec742SSukumar Swaminathan #define PROC_ADDR_ERR BIT_29 121*bafec742SSukumar Swaminathan #define PROC_ADDR_DA BIT_28 122*bafec742SSukumar Swaminathan #define PROC_ADDR_FUNC0_MBI 0x00001180 123*bafec742SSukumar Swaminathan #define PROC_ADDR_FUNC0_MBO (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT) 124*bafec742SSukumar Swaminathan #define PROC_ADDR_FUNC0_CTL 0x000011a1 125*bafec742SSukumar Swaminathan #define PROC_ADDR_FUNC2_MBI 0x00001280 126*bafec742SSukumar Swaminathan #define PROC_ADDR_FUNC2_MBO (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT) 127*bafec742SSukumar Swaminathan #define PROC_ADDR_FUNC2_CTL 0x000012a1 128*bafec742SSukumar Swaminathan #define PROC_ADDR_MPI_RISC 0x00000000 129*bafec742SSukumar Swaminathan #define PROC_ADDR_MDE 0x00010000 130*bafec742SSukumar Swaminathan #define PROC_ADDR_REGBLOCK 0x00020000 131*bafec742SSukumar Swaminathan #define PROC_ADDR_RISC_REG 0x00030000 132*bafec742SSukumar Swaminathan 133*bafec742SSukumar Swaminathan 134*bafec742SSukumar Swaminathan /* System Register 0x08 */ 135*bafec742SSukumar Swaminathan #define SYSTEM_EFE_FAE 0x3u 136*bafec742SSukumar Swaminathan #define SYSTEM_EFE_FAE_MASK (SYSTEM_EFE_FAE<<16) 137*bafec742SSukumar Swaminathan enum { 138*bafec742SSukumar Swaminathan SYS_EFE = (1 << 0), 139*bafec742SSukumar Swaminathan SYS_FAE = (1 << 1), 140*bafec742SSukumar Swaminathan SYS_MDC = (1 << 2), 141*bafec742SSukumar Swaminathan SYS_DST = (1 << 3), 142*bafec742SSukumar Swaminathan SYS_DWC = (1 << 4), 143*bafec742SSukumar Swaminathan SYS_EVW = (1 << 5), 144*bafec742SSukumar Swaminathan SYS_OMP_DLY_MASK = 0x3f000000, 145*bafec742SSukumar Swaminathan /* 146*bafec742SSukumar Swaminathan * There are no values defined as of edit #15. 147*bafec742SSukumar Swaminathan */ 148*bafec742SSukumar Swaminathan SYS_ODI = (1 << 14) 149*bafec742SSukumar Swaminathan }; 150*bafec742SSukumar Swaminathan 151*bafec742SSukumar Swaminathan /* 152*bafec742SSukumar Swaminathan * Reset/Failover Register (RST_FO) bit definitions. 153*bafec742SSukumar Swaminathan */ 154*bafec742SSukumar Swaminathan 155*bafec742SSukumar Swaminathan #define RST_FO_TFO (1 << 0) 156*bafec742SSukumar Swaminathan #define RST_FO_RR_MASK 0x00060000 157*bafec742SSukumar Swaminathan #define RST_FO_RR_CQ_CAM 0x00000000 158*bafec742SSukumar Swaminathan #define RST_FO_RR_DROP 0x00000001 159*bafec742SSukumar Swaminathan #define RST_FO_RR_DQ 0x00000002 160*bafec742SSukumar Swaminathan #define RST_FO_RR_RCV_FUNC_CQ 0x00000003 161*bafec742SSukumar Swaminathan #define RST_FO_FRB BIT_12 162*bafec742SSukumar Swaminathan #define RST_FO_MOP BIT_13 163*bafec742SSukumar Swaminathan #define RST_FO_REG BIT_14 164*bafec742SSukumar Swaminathan #define RST_FO_FR 0x8000u 165*bafec742SSukumar Swaminathan 166*bafec742SSukumar Swaminathan /* 167*bafec742SSukumar Swaminathan * Function Specific Control Register (FSC) bit definitions. 168*bafec742SSukumar Swaminathan */ 169*bafec742SSukumar Swaminathan enum { 170*bafec742SSukumar Swaminathan FSC_DBRST_MASK = 0x00070000, 171*bafec742SSukumar Swaminathan FSC_DBRST_256 = 0x00000000, 172*bafec742SSukumar Swaminathan FSC_DBRST_512 = 0x00000001, 173*bafec742SSukumar Swaminathan FSC_DBRST_768 = 0x00000002, 174*bafec742SSukumar Swaminathan FSC_DBRST_1024 = 0x00000003, 175*bafec742SSukumar Swaminathan FSC_DBL_MASK = 0x00180000, 176*bafec742SSukumar Swaminathan FSC_DBL_DBRST = 0x00000000, 177*bafec742SSukumar Swaminathan FSC_DBL_MAX_PLD = 0x00000008, 178*bafec742SSukumar Swaminathan FSC_DBL_MAX_BRST = 0x00000010, 179*bafec742SSukumar Swaminathan FSC_DBL_128_BYTES = 0x00000018, 180*bafec742SSukumar Swaminathan FSC_EC = (1 << 5), 181*bafec742SSukumar Swaminathan FSC_EPC_MASK = 0x00c00000, 182*bafec742SSukumar Swaminathan FSC_EPC_INBOUND = (1 << 6), 183*bafec742SSukumar Swaminathan FSC_EPC_OUTBOUND = (1 << 7), 184*bafec742SSukumar Swaminathan FSC_VM_PAGESIZE_MASK = 0x07000000, 185*bafec742SSukumar Swaminathan FSC_VM_PAGE_2K = 0x00000100, 186*bafec742SSukumar Swaminathan FSC_VM_PAGE_4K = 0x00000200, 187*bafec742SSukumar Swaminathan FSC_VM_PAGE_8K = 0x00000300, 188*bafec742SSukumar Swaminathan FSC_VM_PAGE_64K = 0x00000600, 189*bafec742SSukumar Swaminathan FSC_SH = (1 << 11), 190*bafec742SSukumar Swaminathan FSC_DSB = (1 << 12), 191*bafec742SSukumar Swaminathan FSC_STE = (1 << 13), 192*bafec742SSukumar Swaminathan FSC_FE = (1 << 15) 193*bafec742SSukumar Swaminathan }; 194*bafec742SSukumar Swaminathan 195*bafec742SSukumar Swaminathan /* 196*bafec742SSukumar Swaminathan * Host Command Status Register (CSR) bit definitions. 197*bafec742SSukumar Swaminathan */ 198*bafec742SSukumar Swaminathan #define CSR_ERR_STS_MASK 0x0000003f 199*bafec742SSukumar Swaminathan /* 200*bafec742SSukumar Swaminathan * There are no valued defined as of edit #15. 201*bafec742SSukumar Swaminathan */ 202*bafec742SSukumar Swaminathan #define CSR_RR BIT_8 203*bafec742SSukumar Swaminathan #define CSR_HRI BIT_9 204*bafec742SSukumar Swaminathan #define CSR_RP BIT_10 205*bafec742SSukumar Swaminathan #define CSR_CMD_PARM_SHIFT 22 206*bafec742SSukumar Swaminathan #define CSR_CMD_NOP 0x00000000 207*bafec742SSukumar Swaminathan #define CSR_CMD_SET_RST 0x1000000 208*bafec742SSukumar Swaminathan #define CSR_CMD_CLR_RST 0x20000000 209*bafec742SSukumar Swaminathan #define CSR_CMD_SET_PAUSE 0x30000000 210*bafec742SSukumar Swaminathan #define CSR_CMD_CLR_PAUSE 0x40000000 211*bafec742SSukumar Swaminathan #define CSR_CMD_SET_H2R_INT 0x50000000 212*bafec742SSukumar Swaminathan #define CSR_CMD_CLR_H2R_INT 0x60000000 213*bafec742SSukumar Swaminathan #define CSR_CMD_PAR_EN 0x70000000 214*bafec742SSukumar Swaminathan #define CSR_CMD_SET_BAD_PAR 0x80000000u 215*bafec742SSukumar Swaminathan #define CSR_CMD_CLR_BAD_PAR 0x90000000u 216*bafec742SSukumar Swaminathan #define CSR_CMD_CLR_R2PCI_INT 0xa0000000u 217*bafec742SSukumar Swaminathan 218*bafec742SSukumar Swaminathan /* 219*bafec742SSukumar Swaminathan * Configuration Register (CFG) bit definitions. 220*bafec742SSukumar Swaminathan */ 221*bafec742SSukumar Swaminathan enum { 222*bafec742SSukumar Swaminathan CFG_LRQ = (1 << 0), 223*bafec742SSukumar Swaminathan CFG_DRQ = (1 << 1), 224*bafec742SSukumar Swaminathan CFG_LR = (1 << 2), 225*bafec742SSukumar Swaminathan CFG_DR = (1 << 3), 226*bafec742SSukumar Swaminathan CFG_LE = (1 << 5), 227*bafec742SSukumar Swaminathan CFG_LCQ = (1 << 6), 228*bafec742SSukumar Swaminathan CFG_DCQ = (1 << 7), 229*bafec742SSukumar Swaminathan CFG_Q_SHIFT = 8, 230*bafec742SSukumar Swaminathan CFG_Q_MASK = 0x7f000000 231*bafec742SSukumar Swaminathan }; 232*bafec742SSukumar Swaminathan 233*bafec742SSukumar Swaminathan /* 234*bafec742SSukumar Swaminathan * Status Register (STS) bit definitions. 235*bafec742SSukumar Swaminathan */ 236*bafec742SSukumar Swaminathan enum { 237*bafec742SSukumar Swaminathan STS_FE = (1 << 0), 238*bafec742SSukumar Swaminathan STS_PI = (1 << 1), 239*bafec742SSukumar Swaminathan STS_PL0 = (1 << 2), 240*bafec742SSukumar Swaminathan STS_PL1 = (1 << 3), 241*bafec742SSukumar Swaminathan STS_PI0 = (1 << 4), 242*bafec742SSukumar Swaminathan STS_PI1 = (1 << 5), 243*bafec742SSukumar Swaminathan STS_FUNC_ID_MASK = 0x000000c0, 244*bafec742SSukumar Swaminathan STS_FUNC_ID_SHIFT = 6, 245*bafec742SSukumar Swaminathan STS_F0E = (1 << 8), 246*bafec742SSukumar Swaminathan STS_F1E = (1 << 9), 247*bafec742SSukumar Swaminathan STS_F2E = (1 << 10), 248*bafec742SSukumar Swaminathan STS_F3E = (1 << 11), 249*bafec742SSukumar Swaminathan STS_NFE = (1 << 12) 250*bafec742SSukumar Swaminathan }; 251*bafec742SSukumar Swaminathan 252*bafec742SSukumar Swaminathan /* 253*bafec742SSukumar Swaminathan * Register (REV_ID) bit definitions. 254*bafec742SSukumar Swaminathan */ 255*bafec742SSukumar Swaminathan enum { 256*bafec742SSukumar Swaminathan REV_ID_MASK = 0x0000000f, 257*bafec742SSukumar Swaminathan REV_ID_NICROLL_SHIFT = 0, 258*bafec742SSukumar Swaminathan REV_ID_NICREV_SHIFT = 4, 259*bafec742SSukumar Swaminathan REV_ID_XGROLL_SHIFT = 8, 260*bafec742SSukumar Swaminathan REV_ID_XGREV_SHIFT = 12, 261*bafec742SSukumar Swaminathan REV_ID_CHIPREV_SHIFT = 28 262*bafec742SSukumar Swaminathan }; 263*bafec742SSukumar Swaminathan 264*bafec742SSukumar Swaminathan /* 265*bafec742SSukumar Swaminathan * Force ECC Error Register (FRC_ECC_ERR) bit definitions. 266*bafec742SSukumar Swaminathan */ 267*bafec742SSukumar Swaminathan enum { 268*bafec742SSukumar Swaminathan FRC_ECC_ERR_VW = (1 << 12), 269*bafec742SSukumar Swaminathan FRC_ECC_ERR_VB = (1 << 13), 270*bafec742SSukumar Swaminathan FRC_ECC_ERR_NI = (1 << 14), 271*bafec742SSukumar Swaminathan FRC_ECC_ERR_NO = (1 << 15), 272*bafec742SSukumar Swaminathan FRC_ECC_PFE_SHIFT = 16, 273*bafec742SSukumar Swaminathan FRC_ECC_ERR_DO = (1 << 18), 274*bafec742SSukumar Swaminathan FRC_ECC_P14 = (1 << 19) 275*bafec742SSukumar Swaminathan }; 276*bafec742SSukumar Swaminathan 277*bafec742SSukumar Swaminathan /* 278*bafec742SSukumar Swaminathan * Error Status Register (ERR_STS) bit definitions. 279*bafec742SSukumar Swaminathan */ 280*bafec742SSukumar Swaminathan enum { 281*bafec742SSukumar Swaminathan ERR_STS_NOF = (1 << 0), 282*bafec742SSukumar Swaminathan ERR_STS_NIF = (1 << 1), 283*bafec742SSukumar Swaminathan ERR_STS_DRP = (1 << 2), 284*bafec742SSukumar Swaminathan ERR_STS_XGP = (1 << 3), 285*bafec742SSukumar Swaminathan ERR_STS_FOU = (1 << 4), 286*bafec742SSukumar Swaminathan ERR_STS_FOC = (1 << 5), 287*bafec742SSukumar Swaminathan ERR_STS_FOF = (1 << 6), 288*bafec742SSukumar Swaminathan ERR_STS_FIU = (1 << 7), 289*bafec742SSukumar Swaminathan ERR_STS_FIC = (1 << 8), 290*bafec742SSukumar Swaminathan ERR_STS_FIF = (1 << 9), 291*bafec742SSukumar Swaminathan ERR_STS_MOF = (1 << 10), 292*bafec742SSukumar Swaminathan ERR_STS_TA = (1 << 11), 293*bafec742SSukumar Swaminathan ERR_STS_MA = (1 << 12), 294*bafec742SSukumar Swaminathan ERR_STS_MPE = (1 << 13), 295*bafec742SSukumar Swaminathan ERR_STS_SCE = (1 << 14), 296*bafec742SSukumar Swaminathan ERR_STS_STE = (1 << 15), 297*bafec742SSukumar Swaminathan ERR_STS_FOW = (1 << 16), 298*bafec742SSukumar Swaminathan ERR_STS_UE = (1 << 17), 299*bafec742SSukumar Swaminathan ERR_STS_MCH = (1 << 26), 300*bafec742SSukumar Swaminathan ERR_STS_LOC_SHIFT = 27 301*bafec742SSukumar Swaminathan }; 302*bafec742SSukumar Swaminathan 303*bafec742SSukumar Swaminathan /* 304*bafec742SSukumar Swaminathan * Semaphore Register (SEM) bit definitions. 305*bafec742SSukumar Swaminathan */ 306*bafec742SSukumar Swaminathan /* 307*bafec742SSukumar Swaminathan * Example: 308*bafec742SSukumar Swaminathan * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT) 309*bafec742SSukumar Swaminathan */ 310*bafec742SSukumar Swaminathan #define SEM_CLEAR 0 311*bafec742SSukumar Swaminathan #define SEM_SET 1 312*bafec742SSukumar Swaminathan #define SEM_FORCE 3 313*bafec742SSukumar Swaminathan #define SEM_XGMAC0_SHIFT 0 314*bafec742SSukumar Swaminathan #define SEM_XGMAC1_SHIFT 2 315*bafec742SSukumar Swaminathan #define SEM_ICB_SHIFT 4 316*bafec742SSukumar Swaminathan #define SEM_MAC_ADDR_SHIFT 6 317*bafec742SSukumar Swaminathan #define SEM_FLASH_SHIFT 8 318*bafec742SSukumar Swaminathan #define SEM_PROBE_SHIFT 10 319*bafec742SSukumar Swaminathan #define SEM_RT_IDX_SHIFT 12 320*bafec742SSukumar Swaminathan #define SEM_PROC_REG_SHIFT 14 321*bafec742SSukumar Swaminathan #define SEM_XGMAC0_MASK 0x00030000 322*bafec742SSukumar Swaminathan #define SEM_XGMAC1_MASK 0x000c0000 323*bafec742SSukumar Swaminathan #define SEM_ICB_MASK 0x00300000 324*bafec742SSukumar Swaminathan #define SEM_MAC_ADDR_MASK 0x00c00000 325*bafec742SSukumar Swaminathan #define SEM_FLASH_MASK 0x03000000 326*bafec742SSukumar Swaminathan #define SEM_PROBE_MASK 0x0c000000 327*bafec742SSukumar Swaminathan #define SEM_RT_IDX_MASK 0x30000000 328*bafec742SSukumar Swaminathan #define SEM_PROC_REG_MASK 0xc0000000 329*bafec742SSukumar Swaminathan 330*bafec742SSukumar Swaminathan /* 331*bafec742SSukumar Swaminathan * Stop CQ Processing Register (CQ_STOP) bit definitions. 332*bafec742SSukumar Swaminathan */ 333*bafec742SSukumar Swaminathan enum { 334*bafec742SSukumar Swaminathan CQ_STOP_QUEUE_MASK = (0x007f0000), 335*bafec742SSukumar Swaminathan CQ_STOP_TYPE_MASK = (0x03000000), 336*bafec742SSukumar Swaminathan CQ_STOP_TYPE_START = 0x00000100, 337*bafec742SSukumar Swaminathan CQ_STOP_TYPE_STOP = 0x00000200, 338*bafec742SSukumar Swaminathan CQ_STOP_TYPE_READ = 0x00000300, 339*bafec742SSukumar Swaminathan CQ_STOP_EN = (1 << 15) 340*bafec742SSukumar Swaminathan }; 341*bafec742SSukumar Swaminathan 342*bafec742SSukumar Swaminathan /* 343*bafec742SSukumar Swaminathan * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions. 344*bafec742SSukumar Swaminathan */ 345*bafec742SSukumar Swaminathan #define MAC_ADDR_IDX_SHIFT 4 346*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_SHIFT 16 347*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_MASK 0x000f0000 348*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_CAM_MAC 0x00000000 349*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_MULTI_MAC 0x00010000 350*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_VLAN 0x00020000 351*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_MULTI_FLTR 0x00030000 352*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_FC_MAC 0x00040000 353*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_MGMT_MAC 0x00050000 354*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_MGMT_VLAN 0x00060000 355*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_MGMT_V4 0x00070000 356*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_MGMT_V6 0x00080000 357*bafec742SSukumar Swaminathan #define MAC_ADDR_TYPE_MGMT_TU_DP 0x00090000 358*bafec742SSukumar Swaminathan #define MAC_ADDR_ADR BIT_25 359*bafec742SSukumar Swaminathan #define MAC_ADDR_RS BIT_26 360*bafec742SSukumar Swaminathan #define MAC_ADDR_E BIT_27 361*bafec742SSukumar Swaminathan #define MAC_ADDR_MR BIT_30 362*bafec742SSukumar Swaminathan #define MAC_ADDR_MW BIT_31 363*bafec742SSukumar Swaminathan #define MAX_MULTICAST_HW_SIZE 32 364*bafec742SSukumar Swaminathan 365*bafec742SSukumar Swaminathan /* 366*bafec742SSukumar Swaminathan * MAC Protocol Address Index Register (SPLT_HDR, 0xC0) bit definitions. 367*bafec742SSukumar Swaminathan */ 368*bafec742SSukumar Swaminathan #define SPLT_HDR_EP BIT_31 369*bafec742SSukumar Swaminathan 370*bafec742SSukumar Swaminathan /* 371*bafec742SSukumar Swaminathan * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions. 372*bafec742SSukumar Swaminathan */ 373*bafec742SSukumar Swaminathan enum { 374*bafec742SSukumar Swaminathan NIC_RCV_CFG_PPE = (1 << 0), 375*bafec742SSukumar Swaminathan NIC_RCV_CFG_VLAN_MASK = 0x00060000, 376*bafec742SSukumar Swaminathan NIC_RCV_CFG_VLAN_ALL = 0x00000000, 377*bafec742SSukumar Swaminathan NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002, 378*bafec742SSukumar Swaminathan NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004, 379*bafec742SSukumar Swaminathan NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006, 380*bafec742SSukumar Swaminathan NIC_RCV_CFG_RV = (1 << 3), 381*bafec742SSukumar Swaminathan NIC_RCV_CFG_DFQ_MASK = (0x7f000000), 382*bafec742SSukumar Swaminathan NIC_RCV_CFG_DFQ_SHIFT = 8, 383*bafec742SSukumar Swaminathan NIC_RCV_CFG_DFQ = 0 /* HARDCODE default queue to 0. */ 384*bafec742SSukumar Swaminathan }; 385*bafec742SSukumar Swaminathan 386*bafec742SSukumar Swaminathan /* 387*bafec742SSukumar Swaminathan * Routing Index Register (RT_IDX) bit definitions. 388*bafec742SSukumar Swaminathan */ 389*bafec742SSukumar Swaminathan #define RT_IDX_IDX_SHIFT 8 390*bafec742SSukumar Swaminathan #define RT_IDX_TYPE_MASK 0x000f0000 391*bafec742SSukumar Swaminathan #define RT_IDX_TYPE_RT 0x00000000 392*bafec742SSukumar Swaminathan #define RT_IDX_TYPE_RT_INV 0x00010000 393*bafec742SSukumar Swaminathan #define RT_IDX_TYPE_NICQ 0x00020000 394*bafec742SSukumar Swaminathan #define RT_IDX_TYPE_NICQ_INV 0x00030000 395*bafec742SSukumar Swaminathan #define RT_IDX_DST_MASK 0x00700000 396*bafec742SSukumar Swaminathan #define RT_IDX_DST_RSS 0x00000000 397*bafec742SSukumar Swaminathan #define RT_IDX_DST_CAM_Q 0x00100000 398*bafec742SSukumar Swaminathan #define RT_IDX_DST_COS_Q 0x00200000 399*bafec742SSukumar Swaminathan #define RT_IDX_DST_DFLT_Q 0x00300000 400*bafec742SSukumar Swaminathan #define RT_IDX_DST_DEST_Q 0x00400000 401*bafec742SSukumar Swaminathan #define RT_IDX_RS BIT_26 402*bafec742SSukumar Swaminathan #define RT_IDX_E BIT_27 403*bafec742SSukumar Swaminathan #define RT_IDX_MR BIT_30 404*bafec742SSukumar Swaminathan #define RT_IDX_MW BIT_31 405*bafec742SSukumar Swaminathan 406*bafec742SSukumar Swaminathan /* Nic Queue format - type 2 bits */ 407*bafec742SSukumar Swaminathan #define RT_IDX_BCAST 1 408*bafec742SSukumar Swaminathan #define RT_IDX_MCAST BIT_1 409*bafec742SSukumar Swaminathan #define RT_IDX_MCAST_MATCH BIT_2 410*bafec742SSukumar Swaminathan #define RT_IDX_MCAST_REG_MATCH BIT_3 411*bafec742SSukumar Swaminathan #define RT_IDX_MCAST_HASH_MATCH BIT_4 412*bafec742SSukumar Swaminathan #define RT_IDX_FC_MACH BIT_5 413*bafec742SSukumar Swaminathan #define RT_IDX_ETH_FCOE BIT_6 414*bafec742SSukumar Swaminathan #define RT_IDX_CAM_HIT BIT_7 415*bafec742SSukumar Swaminathan #define RT_IDX_CAM_BIT0 BIT_8 416*bafec742SSukumar Swaminathan #define RT_IDX_CAM_BIT1 BIT_9 417*bafec742SSukumar Swaminathan #define RT_IDX_VLAN_TAG BIT_10 418*bafec742SSukumar Swaminathan #define RT_IDX_VLAN_MATCH BIT_11 419*bafec742SSukumar Swaminathan #define RT_IDX_VLAN_FILTER BIT_12 420*bafec742SSukumar Swaminathan #define RT_IDX_ETH_SKIP1 BIT_13 421*bafec742SSukumar Swaminathan #define RT_IDX_ETH_SKIP2 BIT_14 422*bafec742SSukumar Swaminathan #define RT_IDX_BCAST_MCAST_MATCH BIT_15 423*bafec742SSukumar Swaminathan #define RT_IDX_802_3 BIT_16 424*bafec742SSukumar Swaminathan #define RT_IDX_LLDP BIT_17 425*bafec742SSukumar Swaminathan #define RT_IDX_UNUSED018 BIT_18 426*bafec742SSukumar Swaminathan #define RT_IDX_UNUSED019 BIT_19 427*bafec742SSukumar Swaminathan #define RT_IDX_UNUSED20 BIT_20 428*bafec742SSukumar Swaminathan #define RT_IDX_UNUSED21 BIT_21 429*bafec742SSukumar Swaminathan #define RT_IDX_ERR BIT_22 430*bafec742SSukumar Swaminathan #define RT_IDX_VALID BIT_23 431*bafec742SSukumar Swaminathan #define RT_IDX_TU_CSUM_ERR BIT_24 432*bafec742SSukumar Swaminathan #define RT_IDX_IP_CSUM_ERR BIT_25 433*bafec742SSukumar Swaminathan #define RT_IDX_MAC_ERR BIT_26 434*bafec742SSukumar Swaminathan #define RT_IDX_RSS_TCP6 BIT_27 435*bafec742SSukumar Swaminathan #define RT_IDX_RSS_TCP4 BIT_28 436*bafec742SSukumar Swaminathan #define RT_IDX_RSS_IPV6 BIT_29 437*bafec742SSukumar Swaminathan #define RT_IDX_RSS_IPV4 BIT_30 438*bafec742SSukumar Swaminathan #define RT_IDX_RSS_MATCH BIT_31 439*bafec742SSukumar Swaminathan 440*bafec742SSukumar Swaminathan /* Hierarchy for the NIC Queue Mask */ 441*bafec742SSukumar Swaminathan enum { 442*bafec742SSukumar Swaminathan RT_IDX_ALL_ERR_SLOT = 0, 443*bafec742SSukumar Swaminathan RT_IDX_MAC_ERR_SLOT = 0, 444*bafec742SSukumar Swaminathan RT_IDX_IP_CSUM_ERR_SLOT = 1, 445*bafec742SSukumar Swaminathan RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2, 446*bafec742SSukumar Swaminathan RT_IDX_BCAST_SLOT = 3, 447*bafec742SSukumar Swaminathan RT_IDX_MCAST_MATCH_SLOT = 4, 448*bafec742SSukumar Swaminathan RT_IDX_ALLMULTI_SLOT = 5, 449*bafec742SSukumar Swaminathan RT_IDX_UNUSED6_SLOT = 6, 450*bafec742SSukumar Swaminathan RT_IDX_UNUSED7_SLOT = 7, 451*bafec742SSukumar Swaminathan RT_IDX_RSS_MATCH_SLOT = 8, 452*bafec742SSukumar Swaminathan RT_IDX_RSS_IPV4_SLOT = 8, 453*bafec742SSukumar Swaminathan RT_IDX_RSS_IPV6_SLOT = 9, 454*bafec742SSukumar Swaminathan RT_IDX_RSS_TCP4_SLOT = 10, 455*bafec742SSukumar Swaminathan RT_IDX_RSS_TCP6_SLOT = 11, 456*bafec742SSukumar Swaminathan RT_IDX_CAM_HIT_SLOT = 12, 457*bafec742SSukumar Swaminathan RT_IDX_UNUSED013 = 13, 458*bafec742SSukumar Swaminathan RT_IDX_UNUSED014 = 14, 459*bafec742SSukumar Swaminathan RT_IDX_PROMISCUOUS_SLOT = 15, 460*bafec742SSukumar Swaminathan RT_IDX_MAX_SLOTS = 16 461*bafec742SSukumar Swaminathan }; 462*bafec742SSukumar Swaminathan 463*bafec742SSukumar Swaminathan enum { 464*bafec742SSukumar Swaminathan CAM_OUT_ROUTE_FC = 0, 465*bafec742SSukumar Swaminathan CAM_OUT_ROUTE_NIC = 1, 466*bafec742SSukumar Swaminathan CAM_OUT_FUNC_SHIFT = 2, 467*bafec742SSukumar Swaminathan CAM_OUT_RV = (1 << 4), 468*bafec742SSukumar Swaminathan CAM_OUT_SH = (1 << 15), 469*bafec742SSukumar Swaminathan CAM_OUT_CQ_ID_SHIFT = 5 470*bafec742SSukumar Swaminathan }; 471*bafec742SSukumar Swaminathan 472*bafec742SSukumar Swaminathan /* Reset/Failover Register 0C */ 473*bafec742SSukumar Swaminathan #define FUNCTION_RESET 0x8000u 474*bafec742SSukumar Swaminathan #define FUNCTION_RESET_MASK (FUNCTION_RESET<<16) 475*bafec742SSukumar Swaminathan 476*bafec742SSukumar Swaminathan /* Function Specific Control Register 0x10 */ 477*bafec742SSukumar Swaminathan #define FSC_MASK (0x97ffu << 16) 478*bafec742SSukumar Swaminathan #define FSC_FE 0x8000 479*bafec742SSukumar Swaminathan 480*bafec742SSukumar Swaminathan /* Configuration Register 0x28 */ 481*bafec742SSukumar Swaminathan #define LOAD_LCQ 0x40 482*bafec742SSukumar Swaminathan #define LOAD_LCQ_MASK (0x7F40u << 16) 483*bafec742SSukumar Swaminathan #define LOAD_ICB_ERR 0x20 484*bafec742SSukumar Swaminathan #define LOAD_LRQ 0x01 485*bafec742SSukumar Swaminathan #define LOAD_LRQ_MASK (0x7F01u << 16) 486*bafec742SSukumar Swaminathan 487*bafec742SSukumar Swaminathan #define FN0_NET 0 488*bafec742SSukumar Swaminathan #define FN1_NET 1 489*bafec742SSukumar Swaminathan #define FN0_FC 2 490*bafec742SSukumar Swaminathan #define FN1_FC 3 491*bafec742SSukumar Swaminathan 492*bafec742SSukumar Swaminathan /* 493*bafec742SSukumar Swaminathan * Semaphore Register (SEM) bit definitions. 494*bafec742SSukumar Swaminathan */ 495*bafec742SSukumar Swaminathan #define SEM_CLEAR 0 496*bafec742SSukumar Swaminathan #define SEM_SET 1 497*bafec742SSukumar Swaminathan #define SEM_FORCE 3 498*bafec742SSukumar Swaminathan #define SEM_XGMAC0_SHIFT 0 499*bafec742SSukumar Swaminathan #define SEM_XGMAC1_SHIFT 2 500*bafec742SSukumar Swaminathan #define SEM_ICB_SHIFT 4 501*bafec742SSukumar Swaminathan #define SEM_MAC_ADDR_SHIFT 6 502*bafec742SSukumar Swaminathan #define SEM_FLASH_SHIFT 8 503*bafec742SSukumar Swaminathan #define SEM_PROBE_SHIFT 10 504*bafec742SSukumar Swaminathan #define SEM_RT_IDX_SHIFT 12 505*bafec742SSukumar Swaminathan #define SEM_PROC_REG_SHIFT 14 506*bafec742SSukumar Swaminathan #define SEM_XGMAC0_MASK 0x00030000 507*bafec742SSukumar Swaminathan #define SEM_XGMAC1_MASK 0x000c0000 508*bafec742SSukumar Swaminathan #define SEM_ICB_MASK 0x00300000 509*bafec742SSukumar Swaminathan #define SEM_MAC_ADDR_MASK 0x00c00000 510*bafec742SSukumar Swaminathan #define SEM_FLASH_MASK 0x03000000 511*bafec742SSukumar Swaminathan #define SEM_PROBE_MASK 0x0c000000 512*bafec742SSukumar Swaminathan #define SEM_RT_IDX_MASK 0x30000000 513*bafec742SSukumar Swaminathan #define SEM_PROC_REG_MASK 0xc0000000 514*bafec742SSukumar Swaminathan 515*bafec742SSukumar Swaminathan /* System Register 0x08 */ 516*bafec742SSukumar Swaminathan #define SYSTEM_EFE_FAE 0x3u 517*bafec742SSukumar Swaminathan #define SYSTEM_EFE_FAE_MASK (SYSTEM_EFE_FAE<<16) 518*bafec742SSukumar Swaminathan 519*bafec742SSukumar Swaminathan /* Interrupt Status Register-1 0x3C */ 520*bafec742SSukumar Swaminathan #define CQ_0_NOT_EMPTY BIT_0 521*bafec742SSukumar Swaminathan #define CQ_1_NOT_EMPTY BIT_1 522*bafec742SSukumar Swaminathan #define CQ_2_NOT_EMPTY BIT_2 523*bafec742SSukumar Swaminathan #define CQ_3_NOT_EMPTY BIT_3 524*bafec742SSukumar Swaminathan #define CQ_4_NOT_EMPTY BIT_4 525*bafec742SSukumar Swaminathan #define CQ_5_NOT_EMPTY BIT_5 526*bafec742SSukumar Swaminathan #define CQ_6_NOT_EMPTY BIT_6 527*bafec742SSukumar Swaminathan #define CQ_7_NOT_EMPTY BIT_7 528*bafec742SSukumar Swaminathan #define CQ_8_NOT_EMPTY BIT_8 529*bafec742SSukumar Swaminathan #define CQ_9_NOT_EMPTY BIT_9 530*bafec742SSukumar Swaminathan #define CQ_10_NOT_EMPTY BIT_10 531*bafec742SSukumar Swaminathan #define CQ_11_NOT_EMPTY BIT_11 532*bafec742SSukumar Swaminathan #define CQ_12_NOT_EMPTY BIT_12 533*bafec742SSukumar Swaminathan #define CQ_13_NOT_EMPTY BIT_13 534*bafec742SSukumar Swaminathan #define CQ_14_NOT_EMPTY BIT_14 535*bafec742SSukumar Swaminathan #define CQ_15_NOT_EMPTY BIT_15 536*bafec742SSukumar Swaminathan #define CQ_16_NOT_EMPTY BIT_16 537*bafec742SSukumar Swaminathan /* Processor Address Register 0x00 */ 538*bafec742SSukumar Swaminathan #define PROCESSOR_ADDRESS_RDY (0x8000u<<16) 539*bafec742SSukumar Swaminathan #define PROCESSOR_ADDRESS_READ (0x4000u<<16) 540*bafec742SSukumar Swaminathan /* Host Command/Status Register 0x14 */ 541*bafec742SSukumar Swaminathan #define HOST_CMD_SET_RISC_RESET 0x10000000u 542*bafec742SSukumar Swaminathan #define HOST_CMD_CLEAR_RISC_RESET 0x20000000u 543*bafec742SSukumar Swaminathan #define HOST_CMD_SET_RISC_PAUSE 0x30000000u 544*bafec742SSukumar Swaminathan #define HOST_CMD_RELEASE_RISC_PAUSE 0x40000000u 545*bafec742SSukumar Swaminathan #define HOST_CMD_SET_RISC_INTR 0x50000000u 546*bafec742SSukumar Swaminathan #define HOST_CMD_CLEAR_RISC_INTR 0x60000000u 547*bafec742SSukumar Swaminathan #define HOST_CMD_SET_PARITY_ENABLE 0x70000000u 548*bafec742SSukumar Swaminathan #define HOST_CMD_FORCE_BAD_PARITY 0x80000000u 549*bafec742SSukumar Swaminathan #define HOST_CMD_RELEASE_BAD_PARITY 0x90000000u 550*bafec742SSukumar Swaminathan #define HOST_CMD_CLEAR_RISC_TO_HOST_INTR 0xA0000000u 551*bafec742SSukumar Swaminathan #define HOST_TO_MPI_INTR_NOT_DONE 0x200 552*bafec742SSukumar Swaminathan 553*bafec742SSukumar Swaminathan #define RISC_RESET BIT_8 554*bafec742SSukumar Swaminathan #define RISC_PAUSED BIT_10 555*bafec742SSukumar Swaminathan /* Semaphor Register 0x64 */ 556*bafec742SSukumar Swaminathan #define QL_SEM_BITS_BASE_CODE 0x1u 557*bafec742SSukumar Swaminathan #define QL_PORT0_XGMAC_SEM_BITS (QL_SEM_BITS_BASE_CODE) 558*bafec742SSukumar Swaminathan #define QL_PORT1_XGMAC_SEM_BITS (QL_SEM_BITS_BASE_CODE << 2) 559*bafec742SSukumar Swaminathan #define QL_ICB_ACCESS_ADDRESS_SEM_BITS (QL_SEM_BITS_BASE_CODE << 4) 560*bafec742SSukumar Swaminathan #define QL_MAC_PROTOCOL_SEM_BITS (QL_SEM_BITS_BASE_CODE << 6) 561*bafec742SSukumar Swaminathan #define QL_FLASH_SEM_BITS (QL_SEM_BITS_BASE_CODE << 8) 562*bafec742SSukumar Swaminathan #define QL_PROBE_MUX_SEM_BITS (QL_SEM_BITS_BASE_CODE << 10) 563*bafec742SSukumar Swaminathan #define QL_ROUTING_INDEX_SEM_BITS (QL_SEM_BITS_BASE_CODE << 12) 564*bafec742SSukumar Swaminathan #define QL_PROCESSOR_SEM_BITS (QL_SEM_BITS_BASE_CODE << 14) 565*bafec742SSukumar Swaminathan #define QL_NIC_RECV_CONFIG_SEM_BITS (QL_SEM_BITS_BASE_CODE << 14) 566*bafec742SSukumar Swaminathan 567*bafec742SSukumar Swaminathan #define QL_SEM_MASK_BASE_CODE 0x30000u 568*bafec742SSukumar Swaminathan #define QL_PORT0_XGMAC_SEM_MASK (QL_SEM_MASK_BASE_CODE) 569*bafec742SSukumar Swaminathan #define QL_PORT1_XGMAC_SEM_MASK (QL_SEM_MASK_BASE_CODE << 2) 570*bafec742SSukumar Swaminathan #define QL_ICB_ACCESS_ADDRESS_SEM_MASK (QL_SEM_MASK_BASE_CODE << 4) 571*bafec742SSukumar Swaminathan #define QL_MAC_PROTOCOL_SEM_MASK (QL_SEM_MASK_BASE_CODE << 6) 572*bafec742SSukumar Swaminathan #define QL_FLASH_SEM_MASK (QL_SEM_MASK_BASE_CODE << 8) 573*bafec742SSukumar Swaminathan #define QL_PROBE_MUX_SEM_MASK (QL_SEM_MASK_BASE_CODE << 10) 574*bafec742SSukumar Swaminathan #define QL_ROUTING_INDEX_SEM_MASK (QL_SEM_MASK_BASE_CODE << 12) 575*bafec742SSukumar Swaminathan #define QL_PROCESSOR_SEM_MASK (QL_SEM_MASK_BASE_CODE << 14) 576*bafec742SSukumar Swaminathan #define QL_NIC_RECV_CONFIG_SEM_MASK (QL_SEM_MASK_BASE_CODE << 14) 577*bafec742SSukumar Swaminathan 578*bafec742SSukumar Swaminathan /* XGMAC Address Register 0x78 */ 579*bafec742SSukumar Swaminathan #define XGMAC_ADDRESS_RDY (0x8000u<<16) 580*bafec742SSukumar Swaminathan #define XGMAC_ADDRESS_READ_TRANSACT (0x4000u<<16) 581*bafec742SSukumar Swaminathan #define XGMAC_ADDRESS_ACCESS_ERROR (0x2000u<<16) 582*bafec742SSukumar Swaminathan 583*bafec742SSukumar Swaminathan /* XGMAC Register Set */ 584*bafec742SSukumar Swaminathan #define REG_XGMAC_GLOBAL_CONFIGURATION 0x108 585*bafec742SSukumar Swaminathan #define GLOBAL_CONFIG_JUMBO_MODE 0x40 586*bafec742SSukumar Swaminathan 587*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_TX_CONFIGURATION 0x10C 588*bafec742SSukumar Swaminathan #define XGMAC_MAC_TX_ENABLE 0x02 589*bafec742SSukumar Swaminathan 590*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_CONFIGURATION 0x110 591*bafec742SSukumar Swaminathan #define XGMAC_MAC_RX_ENABLE 0x02 592*bafec742SSukumar Swaminathan 593*bafec742SSukumar Swaminathan #define REG_XGMAC_FLOW_CONTROL 0x11C 594*bafec742SSukumar Swaminathan 595*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_TX_PARAM 0x134 596*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_PARAM 0x138 597*bafec742SSukumar Swaminathan 598*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_TX_PKTS 0x200 599*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_TX_OCTETS 0x208 600*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_TX_MULTCAST_PKTS 0x210 601*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_TX_BROADCAST_PKTS 0x218 602*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_TX_PAUSE_PKTS 0x230 603*bafec742SSukumar Swaminathan 604*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_OCTETS 0x300 605*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_OCTETS_OK 0x308 606*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_PKTS 0x310 607*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_PKTS_OK 0x318 608*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_BROADCAST_PKTS 0x320 609*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_MULTCAST_PKTS 0x328 610*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_JABBER_PKTS 0x348 611*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_FCS_ERR 0x360 612*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_ALIGN_ERR 0x368 613*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_SYM_ERR 0x370 614*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_INT_ERR 0x378 615*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_PAUSE_PKTS 0x388 616*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_PHY_ADDR 0x430 617*bafec742SSukumar Swaminathan #define REG_XGMAC_MAC_RX_FIFO_DROPS 0x5B8 618*bafec742SSukumar Swaminathan 619*bafec742SSukumar Swaminathan 620*bafec742SSukumar Swaminathan /* MAC Protocol Address Index Register Set 0xA8 */ 621*bafec742SSukumar Swaminathan #define MAC_PROTOCOL_ADDRESS_INDEX_MW (0x8000u<<16) 622*bafec742SSukumar Swaminathan #define MAC_PROTOCOL_ADDRESS_ENABLE (1 << 27) 623*bafec742SSukumar Swaminathan #define MAC_PROTOCOL_TYPE_CAM_MAC (0x0) 624*bafec742SSukumar Swaminathan #define MAC_PROTOCOL_TYPE_MULTICAST (0x10000u) 625*bafec742SSukumar Swaminathan 626*bafec742SSukumar Swaminathan /* NIC Receive Configuration Register 0xD4 */ 627*bafec742SSukumar Swaminathan #define RECV_CONFIG_DEFAULT_Q_MASK (0x7F000000u) 628*bafec742SSukumar Swaminathan #define RECV_CONFIG_VTAG_REMOVAL_MASK (0x80000u) 629*bafec742SSukumar Swaminathan #define RECV_CONFIG_VTAG_RV 0x08 630*bafec742SSukumar Swaminathan 631*bafec742SSukumar Swaminathan /* 632*bafec742SSukumar Swaminathan * 10G MAC Address Register (XGMAC_ADDR) bit definitions. 633*bafec742SSukumar Swaminathan */ 634*bafec742SSukumar Swaminathan #define XGMAC_ADDR_RDY (1 << 31) 635*bafec742SSukumar Swaminathan #define XGMAC_ADDR_R (1 << 30) 636*bafec742SSukumar Swaminathan #define XGMAC_ADDR_XME (1 << 29) 637*bafec742SSukumar Swaminathan 638*bafec742SSukumar Swaminathan #define PAUSE_SRC_LO 0x00000100 639*bafec742SSukumar Swaminathan #define PAUSE_SRC_HI 0x00000104 640*bafec742SSukumar Swaminathan #define GLOBAL_CFG 0x00000108 641*bafec742SSukumar Swaminathan #define GLOBAL_CFG_RESET (1 << 0) 642*bafec742SSukumar Swaminathan #define GLOBAL_CFG_JUMBO (1 << 6) 643*bafec742SSukumar Swaminathan #define GLOBAL_CFG_TX_STAT_EN (1 << 10) 644*bafec742SSukumar Swaminathan #define GLOBAL_CFG_RX_STAT_EN (1 << 11) 645*bafec742SSukumar Swaminathan #define TX_CFG 0x0000010c 646*bafec742SSukumar Swaminathan #define TX_CFG_RESET (1 << 0) 647*bafec742SSukumar Swaminathan #define TX_CFG_EN (1 << 1) 648*bafec742SSukumar Swaminathan #define TX_CFG_PREAM (1 << 2) 649*bafec742SSukumar Swaminathan #define RX_CFG 0x00000110 650*bafec742SSukumar Swaminathan #define RX_CFG_RESET (1 << 0) 651*bafec742SSukumar Swaminathan #define RX_CFG_EN (1 << 1) 652*bafec742SSukumar Swaminathan #define RX_CFG_PREAM (1 << 2) 653*bafec742SSukumar Swaminathan #define FLOW_CTL 0x0000011c 654*bafec742SSukumar Swaminathan #define PAUSE_OPCODE 0x00000120 655*bafec742SSukumar Swaminathan #define PAUSE_TIMER 0x00000124 656*bafec742SSukumar Swaminathan #define PAUSE_FRM_DEST_LO 0x00000128 657*bafec742SSukumar Swaminathan #define PAUSE_FRM_DEST_HI 0x0000012c 658*bafec742SSukumar Swaminathan #define MAC_TX_PARAMS 0x00000134 659*bafec742SSukumar Swaminathan #define MAC_TX_PARAMS_JUMBO (1 << 31) 660*bafec742SSukumar Swaminathan #define MAC_TX_PARAMS_SIZE_SHIFT 16 661*bafec742SSukumar Swaminathan #define MAC_RX_PARAMS 0x00000138 662*bafec742SSukumar Swaminathan #define MAC_SYS_INT 0x00000144 663*bafec742SSukumar Swaminathan #define MAC_SYS_INT_MASK 0x00000148 664*bafec742SSukumar Swaminathan #define MAC_MGMT_INT 0x0000014c 665*bafec742SSukumar Swaminathan #define MAC_MGMT_IN_MASK 0x00000150 666*bafec742SSukumar Swaminathan #define EXT_ARB_MODE 0x000001fc 667*bafec742SSukumar Swaminathan #define TX_PKTS 0x00000200 668*bafec742SSukumar Swaminathan #define TX_PKTS_LO 0x00000204 669*bafec742SSukumar Swaminathan #define TX_BYTES 0x00000208 670*bafec742SSukumar Swaminathan #define TX_BYTES_LO 0x0000020C 671*bafec742SSukumar Swaminathan #define TX_MCAST_PKTS 0x00000210 672*bafec742SSukumar Swaminathan #define TX_MCAST_PKTS_LO 0x00000214 673*bafec742SSukumar Swaminathan #define TX_BCAST_PKTS 0x00000218 674*bafec742SSukumar Swaminathan #define TX_BCAST_PKTS_LO 0x0000021C 675*bafec742SSukumar Swaminathan #define TX_UCAST_PKTS 0x00000220 676*bafec742SSukumar Swaminathan #define TX_UCAST_PKTS_LO 0x00000224 677*bafec742SSukumar Swaminathan #define TX_CTL_PKTS 0x00000228 678*bafec742SSukumar Swaminathan #define TX_CTL_PKTS_LO 0x0000022c 679*bafec742SSukumar Swaminathan #define TX_PAUSE_PKTS 0x00000230 680*bafec742SSukumar Swaminathan #define TX_PAUSE_PKTS_LO 0x00000234 681*bafec742SSukumar Swaminathan #define TX_64_PKT 0x00000238 682*bafec742SSukumar Swaminathan #define TX_64_PKT_LO 0x0000023c 683*bafec742SSukumar Swaminathan #define TX_65_TO_127_PKT 0x00000240 684*bafec742SSukumar Swaminathan #define TX_65_TO_127_PKT_LO 0x00000244 685*bafec742SSukumar Swaminathan #define TX_128_TO_255_PKT 0x00000248 686*bafec742SSukumar Swaminathan #define TX_128_TO_255_PKT_LO 0x0000024c 687*bafec742SSukumar Swaminathan #define TX_256_511_PKT 0x00000250 688*bafec742SSukumar Swaminathan #define TX_256_511_PKT_LO 0x00000254 689*bafec742SSukumar Swaminathan #define TX_512_TO_1023_PKT 0x00000258 690*bafec742SSukumar Swaminathan #define TX_512_TO_1023_PKT_LO 0x0000025c 691*bafec742SSukumar Swaminathan #define TX_1024_TO_1518_PKT 0x00000260 692*bafec742SSukumar Swaminathan #define TX_1024_TO_1518_PKT_LO 0x00000264 693*bafec742SSukumar Swaminathan #define TX_1519_TO_MAX_PKT 0x00000268 694*bafec742SSukumar Swaminathan #define TX_1519_TO_MAX_PKT_LO 0x0000026c 695*bafec742SSukumar Swaminathan #define TX_UNDERSIZE_PKT 0x00000270 696*bafec742SSukumar Swaminathan #define TX_UNDERSIZE_PKT_LO 0x00000274 697*bafec742SSukumar Swaminathan #define TX_OVERSIZE_PKT 0x00000278 698*bafec742SSukumar Swaminathan #define TX_OVERSIZE_PKT_LO 0x0000027c 699*bafec742SSukumar Swaminathan #define RX_HALF_FULL_DET 0x000002a0 700*bafec742SSukumar Swaminathan #define TX_HALF_FULL_DET_LO 0x000002a4 701*bafec742SSukumar Swaminathan #define RX_OVERFLOW_DET 0x000002a8 702*bafec742SSukumar Swaminathan #define TX_OVERFLOW_DET_LO 0x000002ac 703*bafec742SSukumar Swaminathan #define RX_HALF_FULL_MASK 0x000002b0 704*bafec742SSukumar Swaminathan #define TX_HALF_FULL_MASK_LO 0x000002b4 705*bafec742SSukumar Swaminathan #define RX_OVERFLOW_MASK 0x000002b8 706*bafec742SSukumar Swaminathan #define TX_OVERFLOW_MASK_LO 0x000002bc 707*bafec742SSukumar Swaminathan #define STAT_CNT_CTL 0x000002c0 708*bafec742SSukumar Swaminathan #define STAT_CNT_CTL_CLEAR_TX (1 << 0) /* Control */ 709*bafec742SSukumar Swaminathan #define STAT_CNT_CTL_CLEAR_RX (1 << 1) /* Control */ 710*bafec742SSukumar Swaminathan #define AUX_RX_HALF_FULL_DET 0x000002d0 711*bafec742SSukumar Swaminathan #define AUX_TX_HALF_FULL_DET 0x000002d4 712*bafec742SSukumar Swaminathan #define AUX_RX_OVERFLOW_DET 0x000002d8 713*bafec742SSukumar Swaminathan #define AUX_TX_OVERFLOW_DET 0x000002dc 714*bafec742SSukumar Swaminathan #define AUX_RX_HALF_FULL_MASK 0x000002f0 715*bafec742SSukumar Swaminathan #define AUX_TX_HALF_FULL_MASK 0x000002f4 716*bafec742SSukumar Swaminathan #define AUX_RX_OVERFLOW_MASK 0x000002f8 717*bafec742SSukumar Swaminathan #define AUX_TX_OVERFLOW_MASK 0x000002fc 718*bafec742SSukumar Swaminathan #define RX_BYTES 0x00000300 719*bafec742SSukumar Swaminathan #define RX_BYTES_LO 0x00000304 720*bafec742SSukumar Swaminathan #define RX_BYTES_OK 0x00000308 721*bafec742SSukumar Swaminathan #define RX_BYTES_OK_LO 0x0000030c 722*bafec742SSukumar Swaminathan #define RX_PKTS 0x00000310 723*bafec742SSukumar Swaminathan #define RX_PKTS_LO 0x00000314 724*bafec742SSukumar Swaminathan #define RX_PKTS_OK 0x00000318 725*bafec742SSukumar Swaminathan #define RX_PKTS_OK_LO 0x0000031c 726*bafec742SSukumar Swaminathan #define RX_BCAST_PKTS 0x00000320 727*bafec742SSukumar Swaminathan #define RX_BCAST_PKTS_LO 0x00000324 728*bafec742SSukumar Swaminathan #define RX_MCAST_PKTS 0x00000328 729*bafec742SSukumar Swaminathan #define RX_MCAST_PKTS_LO 0x0000032c 730*bafec742SSukumar Swaminathan #define RX_UCAST_PKTS 0x00000330 731*bafec742SSukumar Swaminathan #define RX_UCAST_PKTS_LO 0x00000334 732*bafec742SSukumar Swaminathan #define RX_UNDERSIZE_PKTS 0x00000338 733*bafec742SSukumar Swaminathan #define RX_UNDERSIZE_PKTS_LO 0x0000033c 734*bafec742SSukumar Swaminathan #define RX_OVERSIZE_PKTS 0x00000340 735*bafec742SSukumar Swaminathan #define RX_OVERSIZE_PKTS_LO 0x00000344 736*bafec742SSukumar Swaminathan #define RX_JABBER_PKTS 0x00000348 737*bafec742SSukumar Swaminathan #define RX_JABBER_PKTS_LO 0x0000034c 738*bafec742SSukumar Swaminathan #define RX_UNDERSIZE_FCERR_PKTS 0x00000350 739*bafec742SSukumar Swaminathan #define RX_UNDERSIZE_FCERR_PKTS_LO 0x00000354 740*bafec742SSukumar Swaminathan #define RX_DROP_EVENTS 0x00000358 741*bafec742SSukumar Swaminathan #define RX_DROP_EVENTS_LO 0x0000035c 742*bafec742SSukumar Swaminathan #define RX_FCERR_PKTS 0x00000360 743*bafec742SSukumar Swaminathan #define RX_FCERR_PKTS_LO 0x00000364 744*bafec742SSukumar Swaminathan #define RX_ALIGN_ERR 0x00000368 745*bafec742SSukumar Swaminathan #define RX_ALIGN_ERR_LO 0x0000036c 746*bafec742SSukumar Swaminathan #define RX_SYMBOL_ERR 0x00000370 747*bafec742SSukumar Swaminathan #define RX_SYMBOL_ERR_LO 0x00000374 748*bafec742SSukumar Swaminathan #define RX_MAC_ERR 0x00000378 749*bafec742SSukumar Swaminathan #define RX_MAC_ERR_LO 0x0000037c 750*bafec742SSukumar Swaminathan #define RX_CTL_PKTS 0x00000380 751*bafec742SSukumar Swaminathan #define RX_CTL_PKTS_LO 0x00000384 752*bafec742SSukumar Swaminathan #define RX_PAUSE_PKTS 0x00000388 753*bafec742SSukumar Swaminathan #define RX_PAUSE_PKTS_LO 0x0000038c 754*bafec742SSukumar Swaminathan #define RX_64_PKTS 0x00000390 755*bafec742SSukumar Swaminathan #define RX_64_PKTS_LO 0x00000394 756*bafec742SSukumar Swaminathan #define RX_65_TO_127_PKTS 0x00000398 757*bafec742SSukumar Swaminathan #define RX_65_TO_127_PKTS_LO 0x0000039c 758*bafec742SSukumar Swaminathan #define RX_128_255_PKTS 0x000003a0 759*bafec742SSukumar Swaminathan #define RX_128_255_PKTS_LO 0x000003a4 760*bafec742SSukumar Swaminathan #define RX_256_511_PKTS 0x000003a8 761*bafec742SSukumar Swaminathan #define RX_256_511_PKTS_LO 0x000003ac 762*bafec742SSukumar Swaminathan #define RX_512_TO_1023_PKTS 0x000003b0 763*bafec742SSukumar Swaminathan #define RX_512_TO_1023_PKTS_LO 0x000003b4 764*bafec742SSukumar Swaminathan #define RX_1024_TO_1518_PKTS 0x000003b8 765*bafec742SSukumar Swaminathan #define RX_1024_TO_1518_PKTS_LO 0x000003bc 766*bafec742SSukumar Swaminathan #define RX_1519_TO_MAX_PKTS 0x000003c0 767*bafec742SSukumar Swaminathan #define RX_1519_TO_MAX_PKTS_LO 0x000003c4 768*bafec742SSukumar Swaminathan #define RX_LEN_ERR_PKTS 0x000003c8 769*bafec742SSukumar Swaminathan #define RX_LEN_ERR_PKTS_LO 0x000003cc 770*bafec742SSukumar Swaminathan #define MDIO_TX_DATA 0x00000400 771*bafec742SSukumar Swaminathan #define MDIO_RX_DATA 0x00000410 772*bafec742SSukumar Swaminathan #define MDIO_CMD 0x00000420 773*bafec742SSukumar Swaminathan #define MDIO_PHY_ADDR 0x00000430 774*bafec742SSukumar Swaminathan #define MDIO_PORT 0x00000440 775*bafec742SSukumar Swaminathan #define MDIO_STATUS 0x00000450 776*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES0 0x00000500 777*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES0_LO 0x00000504 778*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES1 0x00000508 779*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES1_LO 0x0000050C 780*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES2 0x00000510 781*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES2_LO 0x00000514 782*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES3 0x00000518 783*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES3_LO 0x0000051C 784*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES4 0x00000520 785*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES4_LO 0x00000524 786*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES5 0x00000528 787*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES5_LO 0x0000052C 788*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES6 0x00000530 789*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES6_LO 0x00000534 790*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES7 0x00000538 791*bafec742SSukumar Swaminathan #define TX_CBFC_PAUSE_FRAMES7_LO 0x0000053C 792*bafec742SSukumar Swaminathan #define TX_FCOE_PKTS 0x00000540 793*bafec742SSukumar Swaminathan #define TX_FCOE_PKTS_LO 0x00000544 794*bafec742SSukumar Swaminathan #define TX_MGMT_PKTS 0x00000548 795*bafec742SSukumar Swaminathan #define TX_MGMT_PKTS_LO 0x0000054C 796*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES0 0x00000568 797*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES0_LO 0x0000056C 798*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES1 0x00000570 799*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES1_LO 0x00000574 800*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES2 0x00000578 801*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES2_LO 0x0000057C 802*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES3 0x00000580 803*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES3_LO 0x00000584 804*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES4 0x00000588 805*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES4_LO 0x0000058C 806*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES5 0x00000590 807*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES5_LO 0x00000594 808*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES6 0x00000598 809*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES6_LO 0x0000059C 810*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES7 0x000005A0 811*bafec742SSukumar Swaminathan #define RX_CBFC_PAUSE_FRAMES7_LO 0x000005A4 812*bafec742SSukumar Swaminathan #define RX_FCOE_PKTS 0x000005A8 813*bafec742SSukumar Swaminathan #define RX_FCOE_PKTS_LO 0x000005AC 814*bafec742SSukumar Swaminathan #define RX_MGMT_PKTS 0x000005B0 815*bafec742SSukumar Swaminathan #define RX_MGMT_PKTS_LO 0x000005B4 816*bafec742SSukumar Swaminathan #define RX_NIC_FIFO_DROP 0x000005B8 817*bafec742SSukumar Swaminathan #define RX_NIC_FIFO_DROP_LO 0x000005BC 818*bafec742SSukumar Swaminathan #define RX_FCOE_FIFO_DROP 0x000005C0 819*bafec742SSukumar Swaminathan #define RX_FCOE_FIFO_DROP_LO 0x000005C4 820*bafec742SSukumar Swaminathan #define RX_MGMT_FIFO_DROP 0x000005C8 821*bafec742SSukumar Swaminathan #define RX_MGMT_FIFO_DROP_LO 0x000005CC 822*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY0 0x00000600 823*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY0_LO 0x00000604 824*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY1 0x00000608 825*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY1_LO 0x0000060C 826*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY2 0x00000610 827*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY2_LO 0x00000614 828*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY3 0x00000618 829*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY3_LO 0x0000061C 830*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY4 0x00000620 831*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY4_LO 0x00000624 832*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY5 0x00000628 833*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY5_LO 0x0000062C 834*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY6 0x00000630 835*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY6_LO 0x00000634 836*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY7 0x00000638 837*bafec742SSukumar Swaminathan #define RX_PKTS_PRIORITY7_LO 0x0000063C 838*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY0 0x00000640 839*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY0_LO 0x00000644 840*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY1 0x00000648 841*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY1_LO 0x0000064C 842*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY2 0x00000650 843*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY2_LO 0x00000654 844*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY3 0x00000658 845*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY3_LO 0x0000065C 846*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY4 0x00000660 847*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY4_LO 0x00000664 848*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY5 0x00000668 849*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY5_LO 0x0000066C 850*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY6 0x00000670 851*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY6_LO 0x00000674 852*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY7 0x00000678 853*bafec742SSukumar Swaminathan #define RX_OCTETS_PRIORITY7_LO 0x0000067C 854*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY0 0x00000680 855*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY0_LO 0x00000684 856*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY1 0x00000688 857*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY1_LO 0x0000068C 858*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY2 0x00000690 859*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY2_LO 0x00000694 860*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY3 0x00000698 861*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY3_LO 0x0000069C 862*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY4 0x000006A0 863*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY4_LO 0x000006A4 864*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY5 0x000006A8 865*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY5_LO 0x000006AC 866*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY6 0x000006B0 867*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY6_LO 0x000006B4 868*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY7 0x000006B8 869*bafec742SSukumar Swaminathan #define TX_PKTS_PRIORITY7_LO 0x000006BC 870*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY0 0x000006C0 871*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY0_LO 0x000006C4 872*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY1 0x000006C8 873*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY1_LO 0x000006CC 874*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY2 0x000006D0 875*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY2_LO 0x000006D4 876*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY3 0x000006D8 877*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY3_LO 0x000006DC 878*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY4 0x000006E0 879*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY4_LO 0x000006E4 880*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY5 0x000006E8 881*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY5_LO 0x000006EC 882*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY6 0x000006F0 883*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY6_LO 0x000006F4 884*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY7 0x000006F8 885*bafec742SSukumar Swaminathan #define TX_OCTETS_PRIORITY7_LO 0x000006FC 886*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY0 0x00000700 887*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY0_LO 0x00000704 888*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY1 0x00000708 889*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY1_LO 0x0000070C 890*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY2 0x00000710 891*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY2_LO 0x00000714 892*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY3 0x00000718 893*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY3_LO 0x0000071C 894*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY4 0x00000720 895*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY4_LO 0x00000724 896*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY5 0x00000728 897*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY5_LO 0x0000072C 898*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY6 0x00000730 899*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY6_LO 0x00000734 900*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY7 0x00000738 901*bafec742SSukumar Swaminathan #define RX_DISCARD_PRIORITY7_LO 0x0000073C 902*bafec742SSukumar Swaminathan 903*bafec742SSukumar Swaminathan 904*bafec742SSukumar Swaminathan #define CQ0_ID 0x0 905*bafec742SSukumar Swaminathan #define NIC_CORE 0x1 906*bafec742SSukumar Swaminathan /* Routing Index Register 0xE4 */ 907*bafec742SSukumar Swaminathan #define ROUTING_INDEX_MW BIT_31 908*bafec742SSukumar Swaminathan #define ROUTING_INDEX_DEFAULT_ENABLE_MASK (0x8320000u) 909*bafec742SSukumar Swaminathan #define ROUTING_INDEX_DEFAULT_DISABLE_MASK (0x0320000u) 910*bafec742SSukumar Swaminathan 911*bafec742SSukumar Swaminathan /* Routing Data Register 0xE8 */ 912*bafec742SSukumar Swaminathan #define ROUTE_AS_CAM_HIT 0x80 913*bafec742SSukumar Swaminathan #define ROUTE_AS_BCAST_MCAST_MATCH 0x8000u 914*bafec742SSukumar Swaminathan #define ROUTE_AS_VALID_PKT 0x800000u /* promiscuous mode? */ 915*bafec742SSukumar Swaminathan 916*bafec742SSukumar Swaminathan enum { 917*bafec742SSukumar Swaminathan ROUTING_MASK_INDEX_CAM_HIT, 918*bafec742SSukumar Swaminathan ROUTING_MASK_INDEX_BCAST_MCAST_MATCH, 919*bafec742SSukumar Swaminathan ROUTING_MASK_INDEX_VALID_PKT, 920*bafec742SSukumar Swaminathan ROUTING_MASK_INDEX_TOTAL 921*bafec742SSukumar Swaminathan }; 922*bafec742SSukumar Swaminathan 923*bafec742SSukumar Swaminathan #define ROUTING_MASK_INDEX_MAX 16 924*bafec742SSukumar Swaminathan /* 925*bafec742SSukumar Swaminathan * General definitions... 926*bafec742SSukumar Swaminathan */ 927*bafec742SSukumar Swaminathan 928*bafec742SSukumar Swaminathan /* 929*bafec742SSukumar Swaminathan * Below are a number compiler switches for controlling driver behavior. 930*bafec742SSukumar Swaminathan * Some are not supported under certain conditions and are notated as such. 931*bafec742SSukumar Swaminathan */ 932*bafec742SSukumar Swaminathan 933*bafec742SSukumar Swaminathan /* MTU & Frame Size stuff */ 934*bafec742SSukumar Swaminathan #define JUMBO_MTU 9000 935*bafec742SSukumar Swaminathan #define NORMAL_FRAME_SIZE 2500 /* ETHERMTU,1500 */ 936*bafec742SSukumar Swaminathan #define JUMBO_FRAME_SIZE 9600 937*bafec742SSukumar Swaminathan #define VLAN_ID_LEN 2 938*bafec742SSukumar Swaminathan #define VLAN_HEADER_LEN sizeof (struct ether_vlan_header) /* 18 */ 939*bafec742SSukumar Swaminathan #define ETHER_HEADER_LEN sizeof (struct ether_header) /* 14 */ 940*bafec742SSukumar Swaminathan 941*bafec742SSukumar Swaminathan #define NUM_TX_RING_ENTRIES (2048*2) 942*bafec742SSukumar Swaminathan #define NUM_RX_RING_ENTRIES (2048) 943*bafec742SSukumar Swaminathan 944*bafec742SSukumar Swaminathan #define NUM_SMALL_BUFFERS (2048) 945*bafec742SSukumar Swaminathan #define NUM_LARGE_BUFFERS (2048) 946*bafec742SSukumar Swaminathan 947*bafec742SSukumar Swaminathan #define RX_TX_RING_SHADOW_SPACE 2 /* 1st one is wqicb and 2nd for cqicb */ 948*bafec742SSukumar Swaminathan #define BUF_Q_PTR_SPACE ((((NUM_SMALL_BUFFERS * sizeof (uint64_t)) \ 949*bafec742SSukumar Swaminathan / VM_PAGE_SIZE) + 1) + \ 950*bafec742SSukumar Swaminathan (((NUM_LARGE_BUFFERS * sizeof (uint64_t)) \ 951*bafec742SSukumar Swaminathan / VM_PAGE_SIZE) + 1)) 952*bafec742SSukumar Swaminathan 953*bafec742SSukumar Swaminathan #define MAX_CQ 128 954*bafec742SSukumar Swaminathan #define DFLT_RX_COALESCE_WAIT 500 /* usec wait for coalescing */ 955*bafec742SSukumar Swaminathan #define DFLT_RX_INTER_FRAME_WAIT 25 /* max interframe-wait for */ 956*bafec742SSukumar Swaminathan /* coalescing */ 957*bafec742SSukumar Swaminathan #define DFLT_TX_COALESCE_WAIT 800 /* usec wait for coalescing */ 958*bafec742SSukumar Swaminathan #define DFLT_TX_INTER_FRAME_WAIT 5 /* max interframe-wait for */ 959*bafec742SSukumar Swaminathan /* coalescing */ 960*bafec742SSukumar Swaminathan #define DFLT_PAYLOAD_COPY_THRESH 6 /* must be at least 6 usec */ 961*bafec742SSukumar Swaminathan 962*bafec742SSukumar Swaminathan #define UDELAY_COUNT 3 963*bafec742SSukumar Swaminathan #define UDELAY_DELAY 10 964*bafec742SSukumar Swaminathan 965*bafec742SSukumar Swaminathan #define MAX_RX_RINGS 128 966*bafec742SSukumar Swaminathan #define MAX_TX_RINGS 16 967*bafec742SSukumar Swaminathan 968*bafec742SSukumar Swaminathan /* 969*bafec742SSukumar Swaminathan * Large & Small Buffers for Receives 970*bafec742SSukumar Swaminathan */ 971*bafec742SSukumar Swaminathan struct lrg_buf_q_entry { 972*bafec742SSukumar Swaminathan uint32_t addr0_lower; 973*bafec742SSukumar Swaminathan #define IAL_LAST_ENTRY 0x00000001 974*bafec742SSukumar Swaminathan #define IAL_CONT_ENTRY 0x00000002 975*bafec742SSukumar Swaminathan #define IAL_FLAG_MASK 0x00000003 976*bafec742SSukumar Swaminathan uint32_t addr0_upper; 977*bafec742SSukumar Swaminathan }; 978*bafec742SSukumar Swaminathan 979*bafec742SSukumar Swaminathan struct bufq_addr_element { 980*bafec742SSukumar Swaminathan uint32_t addr_low; 981*bafec742SSukumar Swaminathan uint32_t addr_high; 982*bafec742SSukumar Swaminathan }; 983*bafec742SSukumar Swaminathan 984*bafec742SSukumar Swaminathan #define QL_NO_RESET 0 985*bafec742SSukumar Swaminathan #define QL_DO_RESET 1 986*bafec742SSukumar Swaminathan 987*bafec742SSukumar Swaminathan /* Link must be in one of these states */ 988*bafec742SSukumar Swaminathan enum link_state_t { 989*bafec742SSukumar Swaminathan LS_DOWN, 990*bafec742SSukumar Swaminathan LS_UP 991*bafec742SSukumar Swaminathan }; 992*bafec742SSukumar Swaminathan 993*bafec742SSukumar Swaminathan /* qlge->flags definitions. */ 994*bafec742SSukumar Swaminathan #define QL_RESET_DONE BIT_0 /* Reset finished. */ 995*bafec742SSukumar Swaminathan #define QL_RESET_ACTIVE BIT_1 /* Waiting for reset to finish. */ 996*bafec742SSukumar Swaminathan #define QL_RESET_START BIT_2 /* Please reset the chip. */ 997*bafec742SSukumar Swaminathan #define QL_LINK_MASTER BIT_5 /* This driver controls the link */ 998*bafec742SSukumar Swaminathan #define QL_ADAPTER_UP BIT_6 /* Adapter has been brought up. */ 999*bafec742SSukumar Swaminathan #define QL_LINK_OPTICAL BIT_12 1000*bafec742SSukumar Swaminathan #define QL_MSI_ENABLED BIT_13 1001*bafec742SSukumar Swaminathan #define INTERRUPTS_ENABLED BIT_14 1002*bafec742SSukumar Swaminathan #define ADAPTER_SUSPENDED BIT_15 1003*bafec742SSukumar Swaminathan #define QLA_PM_CAPABLE BIT_16 1004*bafec742SSukumar Swaminathan 1005*bafec742SSukumar Swaminathan /* 1006*bafec742SSukumar Swaminathan * ISP PCI Configuration Register Set structure definitions. 1007*bafec742SSukumar Swaminathan */ 1008*bafec742SSukumar Swaminathan typedef volatile struct 1009*bafec742SSukumar Swaminathan { 1010*bafec742SSukumar Swaminathan volatile uint16_t vendor_id; 1011*bafec742SSukumar Swaminathan volatile uint16_t device_id; 1012*bafec742SSukumar Swaminathan volatile uint16_t command; 1013*bafec742SSukumar Swaminathan volatile uint16_t status; 1014*bafec742SSukumar Swaminathan volatile uint8_t revision; 1015*bafec742SSukumar Swaminathan volatile uint8_t prog_class; 1016*bafec742SSukumar Swaminathan volatile uint8_t sub_class; 1017*bafec742SSukumar Swaminathan volatile uint8_t base_class; 1018*bafec742SSukumar Swaminathan volatile uint8_t cache_line_size; 1019*bafec742SSukumar Swaminathan volatile uint8_t latency_timer; 1020*bafec742SSukumar Swaminathan volatile uint8_t header_type; 1021*bafec742SSukumar Swaminathan volatile uint32_t io_base_address; 1022*bafec742SSukumar Swaminathan volatile uint32_t pci_cntl_reg_set_mem_base_address_lower; 1023*bafec742SSukumar Swaminathan volatile uint32_t pci_cntl_reg_set_mem_base_address_upper; 1024*bafec742SSukumar Swaminathan volatile uint32_t pci_doorbell_mem_base_address_lower; 1025*bafec742SSukumar Swaminathan volatile uint32_t pci_doorbell_mem_base_address_upper; 1026*bafec742SSukumar Swaminathan 1027*bafec742SSukumar Swaminathan volatile uint16_t sub_vendor_id; 1028*bafec742SSukumar Swaminathan volatile uint16_t sub_device_id; 1029*bafec742SSukumar Swaminathan volatile uint32_t expansion_rom; 1030*bafec742SSukumar Swaminathan volatile uint8_t intr_line; 1031*bafec742SSukumar Swaminathan volatile uint8_t intr_pin; 1032*bafec742SSukumar Swaminathan volatile uint8_t min_grant; 1033*bafec742SSukumar Swaminathan volatile uint8_t max_latency; 1034*bafec742SSukumar Swaminathan volatile uint16_t pcie_device_control; 1035*bafec742SSukumar Swaminathan volatile uint16_t link_status; 1036*bafec742SSukumar Swaminathan volatile uint16_t msi_msg_control; 1037*bafec742SSukumar Swaminathan volatile uint16_t msi_x_msg_control; 1038*bafec742SSukumar Swaminathan 1039*bafec742SSukumar Swaminathan } pci_cfg_t; 1040*bafec742SSukumar Swaminathan 1041*bafec742SSukumar Swaminathan 1042*bafec742SSukumar Swaminathan /* 1043*bafec742SSukumar Swaminathan * 1044*bafec742SSukumar Swaminathan * Schultz Control Registers Index 1045*bafec742SSukumar Swaminathan * 1046*bafec742SSukumar Swaminathan */ 1047*bafec742SSukumar Swaminathan #define REG_PROCESSOR_ADDR 0x00 1048*bafec742SSukumar Swaminathan #define REG_PROCESSOR_DATA 0x04 1049*bafec742SSukumar Swaminathan #define REG_SYSTEM 0x08 1050*bafec742SSukumar Swaminathan #define REG_RESET_FAILOVER 0x0C 1051*bafec742SSukumar Swaminathan #define REG_FUNCTION_SPECIFIC_CONTROL 0x10 1052*bafec742SSukumar Swaminathan #define REG_HOST_CMD_STATUS 0x14 1053*bafec742SSukumar Swaminathan #define REG_ICB_RID 0x1C 1054*bafec742SSukumar Swaminathan #define REG_ICB_ACCESS_ADDRESS_LOWER 0x20 1055*bafec742SSukumar Swaminathan #define REG_ICB_ACCESS_ADDRESS_UPPER 0x24 1056*bafec742SSukumar Swaminathan #define REG_CONFIGURATION 0x28 1057*bafec742SSukumar Swaminathan 1058*bafec742SSukumar Swaminathan #define INTR_EN_INTR_MASK 0x007f0000 1059*bafec742SSukumar Swaminathan #define INTR_EN_TYPE_MASK 0x03000000 1060*bafec742SSukumar Swaminathan #define INTR_EN_TYPE_ENABLE 0x00000100 1061*bafec742SSukumar Swaminathan #define INTR_EN_TYPE_DISABLE 0x00000200 1062*bafec742SSukumar Swaminathan #define INTR_EN_TYPE_READ 0x00000300 1063*bafec742SSukumar Swaminathan #define INTR_EN_IHD 0x00002000 1064*bafec742SSukumar Swaminathan #define INTR_EN_IHD_MASK (INTR_EN_IHD << 16) 1065*bafec742SSukumar Swaminathan #define INTR_EN_EI 0x00004000 1066*bafec742SSukumar Swaminathan #define INTR_EN_EN 0x00008000 1067*bafec742SSukumar Swaminathan 1068*bafec742SSukumar Swaminathan #define REG_STATUS 0x30 1069*bafec742SSukumar Swaminathan #define REG_INTERRUPT_ENABLE 0x34 1070*bafec742SSukumar Swaminathan #define REG_INTERRUPT_MASK 0x38 1071*bafec742SSukumar Swaminathan #define REG_INTERRUPT_STATUS_1 0x3C 1072*bafec742SSukumar Swaminathan 1073*bafec742SSukumar Swaminathan #define REG_ERROR_STATUS 0x54 1074*bafec742SSukumar Swaminathan 1075*bafec742SSukumar Swaminathan #define REG_SEMAPHORE 0x64 1076*bafec742SSukumar Swaminathan 1077*bafec742SSukumar Swaminathan #define REG_XGMAC_ADDRESS 0x78 1078*bafec742SSukumar Swaminathan #define REG_XGMAC_DATA 0x7C 1079*bafec742SSukumar Swaminathan #define REG_NIC_ENHANCED_TX_SCHEDULE 0x80 1080*bafec742SSukumar Swaminathan #define REG_CNA_ENHANCED_TX_SCHEDULE 0x84 1081*bafec742SSukumar Swaminathan #define REG_FLASH_ADDRESS 0x88 1082*bafec742SSukumar Swaminathan #define REG_FLASH_DATA 0x8C 1083*bafec742SSukumar Swaminathan 1084*bafec742SSukumar Swaminathan #define REG_STOP_CQ_PROCESSING 0x90 1085*bafec742SSukumar Swaminathan #define REG_PAGE_TABLE_RID 0x94 1086*bafec742SSukumar Swaminathan #define REG_WQ_PAGE_TABLE_BASE_ADDR_LOWER 0x98 1087*bafec742SSukumar Swaminathan #define REG_WQ_PAGE_TABLE_BASE_ADDR_UPPER 0x9C 1088*bafec742SSukumar Swaminathan #define REG_CQ_PAGE_TABLE_BASE_ADDR_LOWER 0xA0 1089*bafec742SSukumar Swaminathan #define REG_CQ_PAGE_TABLE_BASE_ADDR_UPPER 0xA4 1090*bafec742SSukumar Swaminathan #define REG_MAC_PROTOCOL_ADDRESS_INDEX 0xA8 1091*bafec742SSukumar Swaminathan #define REG_MAC_PROTOCOL_DATA 0xAC 1092*bafec742SSukumar Swaminathan #define REG_SPLIT_HEADER 0xC0 1093*bafec742SSukumar Swaminathan #define REG_NIC_RECEIVE_CONFIGURATION 0xD4 1094*bafec742SSukumar Swaminathan 1095*bafec742SSukumar Swaminathan #define REG_MGMT_RCV_CFG 0xE0 1096*bafec742SSukumar Swaminathan #define REG_ROUTING_INDEX 0xE4 1097*bafec742SSukumar Swaminathan #define REG_ROUTING_DATA 0xE8 1098*bafec742SSukumar Swaminathan #define REG_RSVD7 0xEC 1099*bafec742SSukumar Swaminathan #define REG_XG_SERDES_ADDR 0xF0 1100*bafec742SSukumar Swaminathan #define REG_XG_SERDES_DATA 0xF4 1101*bafec742SSukumar Swaminathan #define REG_PRB_MX_ADDR 0xF8 1102*bafec742SSukumar Swaminathan #define REG_PRB_MX_DATA 0xFC 1103*bafec742SSukumar Swaminathan 1104*bafec742SSukumar Swaminathan #define INTR_MASK_PI 0x00000001 1105*bafec742SSukumar Swaminathan #define INTR_MASK_HL0 0x00000002 1106*bafec742SSukumar Swaminathan #define INTR_MASK_LH0 0x00000004 1107*bafec742SSukumar Swaminathan #define INTR_MASK_HL1 0x00000008 1108*bafec742SSukumar Swaminathan #define INTR_MASK_LH1 0x00000010 1109*bafec742SSukumar Swaminathan #define INTR_MASK_SE 0x00000020 1110*bafec742SSukumar Swaminathan #define INTR_MASK_LSC 0x00000040 1111*bafec742SSukumar Swaminathan #define INTR_MASK_MC 0x00000080 1112*bafec742SSukumar Swaminathan #define INTR_MASK_LINK_IRQS = (INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC) 1113*bafec742SSukumar Swaminathan 1114*bafec742SSukumar Swaminathan /* Interrupt Enable Register 0x34 */ 1115*bafec742SSukumar Swaminathan #define INTR_ENABLED 0x8000 1116*bafec742SSukumar Swaminathan #define GLOBAL_ENABLE_INTR 0x4000 1117*bafec742SSukumar Swaminathan #define ENABLE_MSI_MULTI_INTR 0x2000 1118*bafec742SSukumar Swaminathan #define ONE_INTR_MASK 0x3FF0000u 1119*bafec742SSukumar Swaminathan #define ENABLE_INTR 0x0100 1120*bafec742SSukumar Swaminathan #define DISABLE_INTR 0x0200 1121*bafec742SSukumar Swaminathan #define VERIFY_INTR_ENABLED 0x0300 1122*bafec742SSukumar Swaminathan #define ISP_ENABLE_INTR(qlge) ql_put32(qlge, \ 1123*bafec742SSukumar Swaminathan REG_INTERRUPT_ENABLE,\ 1124*bafec742SSukumar Swaminathan (ONE_INTR_MASK | ENABLE_INTR)) 1125*bafec742SSukumar Swaminathan #define ISP_DISABLE_INTR(qlge) ql_put32(qlge, \ 1126*bafec742SSukumar Swaminathan REG_INTERRUPT_ENABLE, \ 1127*bafec742SSukumar Swaminathan (ONE_INTR_MASK | DISABLE_INTR)) 1128*bafec742SSukumar Swaminathan #define ISP_ENABLE_PI_INTR(qlge) ql_put32(qlge, \ 1129*bafec742SSukumar Swaminathan REG_INTERRUPT_MASK, (BIT_16|1)) 1130*bafec742SSukumar Swaminathan #define ISP_DISABLE_PI_INTR(qlge) ql_put32(qlge, \ 1131*bafec742SSukumar Swaminathan REG_INTERRUPT_MASK, BIT_16) 1132*bafec742SSukumar Swaminathan 1133*bafec742SSukumar Swaminathan #define ISP_ENABLE_GLOBAL_INTRS(qlge) { \ 1134*bafec742SSukumar Swaminathan ql_put32(qlge, REG_INTERRUPT_ENABLE, \ 1135*bafec742SSukumar Swaminathan (0x40000000u | GLOBAL_ENABLE_INTR)); \ 1136*bafec742SSukumar Swaminathan qlge->flags |= INTERRUPTS_ENABLED; \ 1137*bafec742SSukumar Swaminathan } 1138*bafec742SSukumar Swaminathan #define ISP_DISABLE_GLOBAL_INTRS(qlge) { \ 1139*bafec742SSukumar Swaminathan ql_put32(qlge, \ 1140*bafec742SSukumar Swaminathan REG_INTERRUPT_ENABLE, (0x40000000u)); \ 1141*bafec742SSukumar Swaminathan qlge->flags &= ~INTERRUPTS_ENABLED; \ 1142*bafec742SSukumar Swaminathan } 1143*bafec742SSukumar Swaminathan #define REQ_Q_VALID 0x10 1144*bafec742SSukumar Swaminathan #define RSP_Q_VALID 0x10 1145*bafec742SSukumar Swaminathan 1146*bafec742SSukumar Swaminathan /* 1147*bafec742SSukumar Swaminathan * Mailbox Registers 1148*bafec742SSukumar Swaminathan */ 1149*bafec742SSukumar Swaminathan #define MPI_REG 0x1002 1150*bafec742SSukumar Swaminathan #define NUM_MAILBOX_REGS 16 1151*bafec742SSukumar Swaminathan #define FUNC_0_IN_MAILBOX_0_REG_OFFSET 0x1180 1152*bafec742SSukumar Swaminathan #define FUNC_0_OUT_MAILBOX_0_REG_OFFSET 0x1190 1153*bafec742SSukumar Swaminathan #define FUNC_1_IN_MAILBOX_0_REG_OFFSET 0x1280 1154*bafec742SSukumar Swaminathan #define FUNC_1_OUT_MAILBOX_0_REG_OFFSET 0x1290 1155*bafec742SSukumar Swaminathan 1156*bafec742SSukumar Swaminathan /* 1157*bafec742SSukumar Swaminathan * Control Register Set definitions. 1158*bafec742SSukumar Swaminathan */ 1159*bafec742SSukumar Swaminathan typedef volatile struct 1160*bafec742SSukumar Swaminathan { 1161*bafec742SSukumar Swaminathan volatile uint32_t processor_address; /* 0x00 */ 1162*bafec742SSukumar Swaminathan volatile uint32_t processor_data; /* 0x04 */ 1163*bafec742SSukumar Swaminathan volatile uint32_t system_data; /* 0x08 */ 1164*bafec742SSukumar Swaminathan volatile uint32_t reset_failover; /* 0x0C */ 1165*bafec742SSukumar Swaminathan 1166*bafec742SSukumar Swaminathan volatile uint32_t function_specific_control; /* 0x10 */ 1167*bafec742SSukumar Swaminathan volatile uint32_t host_command_status; /* 0x14 */ 1168*bafec742SSukumar Swaminathan volatile uint32_t led; /* 0x18 */ 1169*bafec742SSukumar Swaminathan volatile uint32_t icb_rid; /* 0x1c */ 1170*bafec742SSukumar Swaminathan 1171*bafec742SSukumar Swaminathan volatile uint32_t idb_access_address_low; /* 0x20 */ 1172*bafec742SSukumar Swaminathan volatile uint32_t idb_access_address_high; /* 0x24 */ 1173*bafec742SSukumar Swaminathan volatile uint32_t configuration; /* 0x28 */ 1174*bafec742SSukumar Swaminathan volatile uint32_t bios_base; /* 0x2C */ 1175*bafec742SSukumar Swaminathan 1176*bafec742SSukumar Swaminathan volatile uint32_t status; /* 0x30 */ 1177*bafec742SSukumar Swaminathan volatile uint32_t interrupt_enable; /* 0x34 */ 1178*bafec742SSukumar Swaminathan volatile uint32_t interrupt_mask; /* 0x38 */ 1179*bafec742SSukumar Swaminathan volatile uint32_t interrupt_status_1; /* 0x3c */ 1180*bafec742SSukumar Swaminathan 1181*bafec742SSukumar Swaminathan volatile uint32_t interrupt_status_2; /* 0x40 */ 1182*bafec742SSukumar Swaminathan volatile uint32_t interrupt_status_3; /* 0x44 */ 1183*bafec742SSukumar Swaminathan volatile uint32_t interrupt_status_4; /* 0x48 */ 1184*bafec742SSukumar Swaminathan volatile uint32_t rev_id; /* 0x4c */ 1185*bafec742SSukumar Swaminathan 1186*bafec742SSukumar Swaminathan volatile uint32_t force_ecc_error; /* 0x50 */ 1187*bafec742SSukumar Swaminathan volatile uint32_t error_status; /* 0x54 */ 1188*bafec742SSukumar Swaminathan volatile uint32_t internal_ram_debug_address; /* 0x58 */ 1189*bafec742SSukumar Swaminathan volatile uint32_t internal_ram_data; /* 0x5c */ 1190*bafec742SSukumar Swaminathan 1191*bafec742SSukumar Swaminathan volatile uint32_t correctable_ecc_error; /* 0x60 */ 1192*bafec742SSukumar Swaminathan volatile uint32_t semaphore; /* 0x64 */ 1193*bafec742SSukumar Swaminathan 1194*bafec742SSukumar Swaminathan volatile uint32_t gpio1; /* 0x68 */ 1195*bafec742SSukumar Swaminathan volatile uint32_t gpio2; /* 0x6c */ 1196*bafec742SSukumar Swaminathan 1197*bafec742SSukumar Swaminathan volatile uint32_t gpio3; /* 0x70 */ 1198*bafec742SSukumar Swaminathan volatile uint32_t reserved1; /* 0x74 */ 1199*bafec742SSukumar Swaminathan volatile uint32_t xgmac_address; /* 0x78 */ 1200*bafec742SSukumar Swaminathan volatile uint32_t xgmac_data; /* 0x7c */ 1201*bafec742SSukumar Swaminathan 1202*bafec742SSukumar Swaminathan volatile uint32_t nic_enhanced_tx_schedule; /* 0x80 */ 1203*bafec742SSukumar Swaminathan volatile uint32_t cna_enhanced_tx_schedule; /* 0x84 */ 1204*bafec742SSukumar Swaminathan volatile uint32_t flash_address; /* 0x88 */ 1205*bafec742SSukumar Swaminathan volatile uint32_t flash_data; /* 0x8c */ 1206*bafec742SSukumar Swaminathan 1207*bafec742SSukumar Swaminathan volatile uint32_t stop_cq; /* 0x90 */ 1208*bafec742SSukumar Swaminathan volatile uint32_t page_table_rid; /* 0x94 */ 1209*bafec742SSukumar Swaminathan volatile uint32_t wq_page_table_base_address_lower; /* 0x98 */ 1210*bafec742SSukumar Swaminathan volatile uint32_t wq_page_table_base_address_upper; /* 0x9c */ 1211*bafec742SSukumar Swaminathan 1212*bafec742SSukumar Swaminathan volatile uint32_t cq_page_table_base_address_lower; /* 0xA0 */ 1213*bafec742SSukumar Swaminathan volatile uint32_t cq_page_table_base_address_upper; /* 0xA4 */ 1214*bafec742SSukumar Swaminathan volatile uint32_t mac_protocol_address_index; /* 0xA8 */ 1215*bafec742SSukumar Swaminathan volatile uint32_t mac_protocol_data; /* 0xAc */ 1216*bafec742SSukumar Swaminathan 1217*bafec742SSukumar Swaminathan volatile uint32_t cos_default_cq_reg1; /* 0xB0 */ 1218*bafec742SSukumar Swaminathan volatile uint32_t cos_default_cq_reg2; /* 0xB4 */ 1219*bafec742SSukumar Swaminathan volatile uint32_t ethertype_skip_reg1; /* 0xB8 */ 1220*bafec742SSukumar Swaminathan volatile uint32_t ethertype_skip_reg2; /* 0xBC */ 1221*bafec742SSukumar Swaminathan 1222*bafec742SSukumar Swaminathan volatile uint32_t split_header; /* 0xC0 */ 1223*bafec742SSukumar Swaminathan volatile uint32_t fcoe_pause_threshold; /* 0xC4 */ 1224*bafec742SSukumar Swaminathan volatile uint32_t nic_pause_threshold; /* 0xC8 */ 1225*bafec742SSukumar Swaminathan volatile uint32_t fc_ethertype; /* 0xCC */ 1226*bafec742SSukumar Swaminathan 1227*bafec742SSukumar Swaminathan volatile uint32_t fcoe_recv_configuration; /* 0xD0 */ 1228*bafec742SSukumar Swaminathan volatile uint32_t nic_recv_configuration; /* 0xD4 */ 1229*bafec742SSukumar Swaminathan volatile uint32_t cos_tags_in_fcoe_fifo; /* 0xD8 */ 1230*bafec742SSukumar Swaminathan volatile uint32_t cos_tags_in_nic_fifo; /* 0xDc */ 1231*bafec742SSukumar Swaminathan 1232*bafec742SSukumar Swaminathan volatile uint32_t mgmt_recv_configuration; /* 0xE0 */ 1233*bafec742SSukumar Swaminathan volatile uint32_t routing_index; /* 0xE4 */ 1234*bafec742SSukumar Swaminathan volatile uint32_t routing_data; /* 0xE8 */ 1235*bafec742SSukumar Swaminathan volatile uint32_t reserved2; /* 0xEc */ 1236*bafec742SSukumar Swaminathan 1237*bafec742SSukumar Swaminathan volatile uint32_t xg_serdes_address; /* 0xF0 */ 1238*bafec742SSukumar Swaminathan volatile uint32_t xg_serdes_data; /* 0xF4 */ 1239*bafec742SSukumar Swaminathan volatile uint32_t probe_mux_address; /* 0xF8 */ 1240*bafec742SSukumar Swaminathan volatile uint32_t probe_mux_read_data; /* 0xFc */ 1241*bafec742SSukumar Swaminathan 1242*bafec742SSukumar Swaminathan #define INTR_PENDING (uint32_t)(CSR_COMPLETION_INTR) 1243*bafec742SSukumar Swaminathan 1244*bafec742SSukumar Swaminathan } dev_reg_t; 1245*bafec742SSukumar Swaminathan 1246*bafec742SSukumar Swaminathan typedef volatile struct 1247*bafec742SSukumar Swaminathan { 1248*bafec742SSukumar Swaminathan volatile uint32_t doorbell_reg_address[256]; /* 0x00 */ 1249*bafec742SSukumar Swaminathan } dev_doorbell_reg_t; 1250*bafec742SSukumar Swaminathan 1251*bafec742SSukumar Swaminathan #define SET_RMASK(val) ((val & 0xffff) | (val << 16)) 1252*bafec742SSukumar Swaminathan #define CLR_RMASK(val) (0 | (val << 16)) 1253*bafec742SSukumar Swaminathan 1254*bafec742SSukumar Swaminathan /* 1255*bafec742SSukumar Swaminathan * DMA registers read only 1256*bafec742SSukumar Swaminathan */ 1257*bafec742SSukumar Swaminathan typedef volatile struct 1258*bafec742SSukumar Swaminathan { 1259*bafec742SSukumar Swaminathan volatile uint32_t req_q_out; 1260*bafec742SSukumar Swaminathan volatile uint32_t rsp_q_in; 1261*bafec742SSukumar Swaminathan 1262*bafec742SSukumar Swaminathan } iop_dmaregs_t; 1263*bafec742SSukumar Swaminathan 1264*bafec742SSukumar Swaminathan #define DMAREGS_SIZE (sizeof (iop_dmaregs_t)) 1265*bafec742SSukumar Swaminathan #define DUMMY_SIZE (32*1024) 1266*bafec742SSukumar Swaminathan 1267*bafec742SSukumar Swaminathan #ifdef QL_DEBUG 1268*bafec742SSukumar Swaminathan typedef struct crash_record { 1269*bafec742SSukumar Swaminathan uint16_t fw_major_version; /* 00 - 01 */ 1270*bafec742SSukumar Swaminathan uint16_t fw_minor_version; /* 02 - 03 */ 1271*bafec742SSukumar Swaminathan uint16_t fw_patch_version; /* 04 - 05 */ 1272*bafec742SSukumar Swaminathan uint16_t fw_build_version; /* 06 - 07 */ 1273*bafec742SSukumar Swaminathan 1274*bafec742SSukumar Swaminathan uint8_t build_date[16]; /* 08 - 17 */ 1275*bafec742SSukumar Swaminathan uint8_t build_time[16]; /* 18 - 27 */ 1276*bafec742SSukumar Swaminathan uint8_t build_user[16]; /* 28 - 37 */ 1277*bafec742SSukumar Swaminathan uint8_t card_serial_num[16]; /* 38 - 47 */ 1278*bafec742SSukumar Swaminathan 1279*bafec742SSukumar Swaminathan uint32_t time_of_crash_in_secs; /* 48 - 4B */ 1280*bafec742SSukumar Swaminathan uint32_t time_of_crash_in_ms; /* 4C - 4F */ 1281*bafec742SSukumar Swaminathan 1282*bafec742SSukumar Swaminathan uint16_t outb_risc_sd_num_frames; /* 50 - 51 */ 1283*bafec742SSukumar Swaminathan uint16_t oap_sd_length; /* 52 - 53 */ 1284*bafec742SSukumar Swaminathan uint16_t iap_sd_num_frames; /* 54 - 55 */ 1285*bafec742SSukumar Swaminathan uint16_t inb_risc_sd_length; /* 56 - 57 */ 1286*bafec742SSukumar Swaminathan 1287*bafec742SSukumar Swaminathan uint8_t reserved[28]; /* 58 - 7F */ 1288*bafec742SSukumar Swaminathan 1289*bafec742SSukumar Swaminathan uint8_t outb_risc_reg_dump[256]; /* 80 -17F */ 1290*bafec742SSukumar Swaminathan uint8_t inb_risc_reg_dump[256]; /* 180 -27F */ 1291*bafec742SSukumar Swaminathan uint8_t inb_outb_risc_stack_dump[1]; /* 280 - ??? */ 1292*bafec742SSukumar Swaminathan } crash_record_t; 1293*bafec742SSukumar Swaminathan #endif 1294*bafec742SSukumar Swaminathan 1295*bafec742SSukumar Swaminathan /* 1296*bafec742SSukumar Swaminathan * I/O register access macros 1297*bafec742SSukumar Swaminathan * #if QL_DEBUG & 1 1298*bafec742SSukumar Swaminathan */ 1299*bafec742SSukumar Swaminathan 1300*bafec742SSukumar Swaminathan #define RD_REG_BYTE(qlge, addr) \ 1301*bafec742SSukumar Swaminathan ddi_get8(qlge->dev_handle, (uint8_t *)addr) 1302*bafec742SSukumar Swaminathan #define RD_REG_DWORD(qlge, addr) \ 1303*bafec742SSukumar Swaminathan ddi_get32(qlge->dev_handle, (uint32_t *)addr) 1304*bafec742SSukumar Swaminathan #define WRT_REG_BYTE(qlge, addr, data) \ 1305*bafec742SSukumar Swaminathan ddi_put8(qlge->dev_handle, (uint8_t *)addr, data) 1306*bafec742SSukumar Swaminathan #define WRT_REG_WORD(qlge, addr, data) \ 1307*bafec742SSukumar Swaminathan ddi_put16(qlge->dev_handle, (uint16_t *)addr, data) 1308*bafec742SSukumar Swaminathan #define WRT_REG_DWORD(qlge, addr, data) \ 1309*bafec742SSukumar Swaminathan ddi_put32(qlge->dev_handle, (uint32_t *)addr, data) 1310*bafec742SSukumar Swaminathan 1311*bafec742SSukumar Swaminathan /* 1312*bafec742SSukumar Swaminathan * QLGE-specific ioctls ... 1313*bafec742SSukumar Swaminathan */ 1314*bafec742SSukumar Swaminathan #define QLA_IOC ((((('Q' << 8) + 'L') << 8) + 'A') << 8) 1315*bafec742SSukumar Swaminathan 1316*bafec742SSukumar Swaminathan /* 1317*bafec742SSukumar Swaminathan * Definition of ioctls commands 1318*bafec742SSukumar Swaminathan */ 1319*bafec742SSukumar Swaminathan #define QLA_PCI_STATUS (QLA_IOC|1) /* Read all PCI registers */ 1320*bafec742SSukumar Swaminathan 1321*bafec742SSukumar Swaminathan #define QLA_WRITE_REG (QLA_IOC|3) 1322*bafec742SSukumar Swaminathan #define QLA_READ_PCI_REG (QLA_IOC|4) 1323*bafec742SSukumar Swaminathan #define QLA_WRITE_PCI_REG (QLA_IOC|5) 1324*bafec742SSukumar Swaminathan #define QLA_GET_DBGLEAVEL (QLA_IOC|6) 1325*bafec742SSukumar Swaminathan #define QLA_SET_DBGLEAVEL (QLA_IOC|7) 1326*bafec742SSukumar Swaminathan #define QLA_READ_CONTRL_REGISTERS (QLA_IOC|8) 1327*bafec742SSukumar Swaminathan 1328*bafec742SSukumar Swaminathan #define QLA_MANUAL_READ_FLASH (QLA_IOC|9) 1329*bafec742SSukumar Swaminathan #define QLA_MANUAL_WRITE_FLASH (QLA_IOC|10) 1330*bafec742SSukumar Swaminathan #define QLA_SUPPORTED_DUMP_TYPES (QLA_IOC|11) 1331*bafec742SSukumar Swaminathan #define QLA_GET_BINARY_CORE_DUMP (QLA_IOC|12) 1332*bafec742SSukumar Swaminathan #define QLA_TRIGGER_SYS_ERROR_EVENT (QLA_IOC|13) 1333*bafec742SSukumar Swaminathan 1334*bafec742SSukumar Swaminathan #define QLA_READ_FLASH (QLA_IOC|15) 1335*bafec742SSukumar Swaminathan #define QLA_WRITE_FLASH (QLA_IOC|16) 1336*bafec742SSukumar Swaminathan #define QLA_READ_VPD (QLA_IOC|17) 1337*bafec742SSukumar Swaminathan #define QLA_GET_PROP (QLA_IOC|18) 1338*bafec742SSukumar Swaminathan #define QLA_SHOW_REGION (QLA_IOC|19) 1339*bafec742SSukumar Swaminathan #define QLA_LIST_ADAPTER_INFO (QLA_IOC|20) 1340*bafec742SSukumar Swaminathan #define QLA_READ_FW_IMAGE (QLA_IOC|21) 1341*bafec742SSukumar Swaminathan #define QLA_WRITE_FW_IMAGE_HEADERS (QLA_IOC|22) 1342*bafec742SSukumar Swaminathan 1343*bafec742SSukumar Swaminathan #define QLA_CONTINUE_COPY_IN (QLA_IOC|29) 1344*bafec742SSukumar Swaminathan #define QLA_CONTINUE_COPY_OUT (QLA_IOC|30) 1345*bafec742SSukumar Swaminathan #define QLA_SOFT_RESET (QLA_IOC|31) 1346*bafec742SSukumar Swaminathan 1347*bafec742SSukumar Swaminathan #define QLA_IOCTL_CMD_FIRST QLA_PCI_STATUS 1348*bafec742SSukumar Swaminathan #define QLA_IOCTL_CMD_LAST QLA_SOFT_RESET 1349*bafec742SSukumar Swaminathan 1350*bafec742SSukumar Swaminathan /* Solaris IOCTL can copy in&out up to 1024 bytes each time */ 1351*bafec742SSukumar Swaminathan #define IOCTL_BUFFER_SIZE 1024 1352*bafec742SSukumar Swaminathan #define IOCTL_MAX_BUF_SIZE (IOCTL_BUFFER_SIZE*512) /* 512k */ 1353*bafec742SSukumar Swaminathan 1354*bafec742SSukumar Swaminathan typedef struct ioctl_header_info { 1355*bafec742SSukumar Swaminathan uint8_t version; 1356*bafec742SSukumar Swaminathan uint8_t reserved; 1357*bafec742SSukumar Swaminathan uint8_t option[2]; 1358*bafec742SSukumar Swaminathan uint16_t expected_trans_times; 1359*bafec742SSukumar Swaminathan uint16_t payload_length; 1360*bafec742SSukumar Swaminathan uint32_t total_length; 1361*bafec742SSukumar Swaminathan } ioctl_header_info_t; 1362*bafec742SSukumar Swaminathan 1363*bafec742SSukumar Swaminathan #define IOCTL_HEADER_LEN sizeof (ioctl_header_info_t) 1364*bafec742SSukumar Swaminathan #define IOCTL_MAX_DATA_LEN (IOCTL_BUFFER_SIZE - IOCTL_HEADER_LEN) 1365*bafec742SSukumar Swaminathan 1366*bafec742SSukumar Swaminathan struct ql_pci_reg { 1367*bafec742SSukumar Swaminathan uint16_t addr; /* register number [0..ff] */ 1368*bafec742SSukumar Swaminathan uint16_t value; /* data to write/data read */ 1369*bafec742SSukumar Swaminathan }; 1370*bafec742SSukumar Swaminathan 1371*bafec742SSukumar Swaminathan struct ql_device_reg { 1372*bafec742SSukumar Swaminathan uint32_t addr; /* address to write/data read */ 1373*bafec742SSukumar Swaminathan uint32_t value; /* data to write/data read */ 1374*bafec742SSukumar Swaminathan }; 1375*bafec742SSukumar Swaminathan 1376*bafec742SSukumar Swaminathan struct ql_flash_io_info { 1377*bafec742SSukumar Swaminathan uint32_t addr; /* register number [0..ff] */ 1378*bafec742SSukumar Swaminathan uint32_t size; /* number of data to write/data read */ 1379*bafec742SSukumar Swaminathan }; 1380*bafec742SSukumar Swaminathan 1381*bafec742SSukumar Swaminathan struct qlnic_mpi_version_info { 1382*bafec742SSukumar Swaminathan uint32_t fw_version; 1383*bafec742SSukumar Swaminathan uint32_t phy_version; 1384*bafec742SSukumar Swaminathan }; 1385*bafec742SSukumar Swaminathan 1386*bafec742SSukumar Swaminathan struct qlnic_link_status_info { 1387*bafec742SSukumar Swaminathan uint32_t link_status_info; 1388*bafec742SSukumar Swaminathan uint32_t additional_info; 1389*bafec742SSukumar Swaminathan uint32_t network_hw_info; 1390*bafec742SSukumar Swaminathan uint32_t dcbx_frame_counters_info; 1391*bafec742SSukumar Swaminathan uint32_t change_counters_info; 1392*bafec742SSukumar Swaminathan }; 1393*bafec742SSukumar Swaminathan 1394*bafec742SSukumar Swaminathan struct qlnic_prop_info { 1395*bafec742SSukumar Swaminathan struct qlnic_mpi_version_info mpi_version; /* MPI Version */ 1396*bafec742SSukumar Swaminathan uint32_t fw_state; /* MPI state */ 1397*bafec742SSukumar Swaminathan struct qlnic_link_status_info link_status; /* Link Status */ 1398*bafec742SSukumar Swaminathan }; 1399*bafec742SSukumar Swaminathan 1400*bafec742SSukumar Swaminathan typedef struct ql_adapter_info { 1401*bafec742SSukumar Swaminathan uint32_t pci_binding; /* /bus/dev/func number per IEEE 1277 format */ 1402*bafec742SSukumar Swaminathan uint16_t vendor_id; 1403*bafec742SSukumar Swaminathan uint16_t device_id; 1404*bafec742SSukumar Swaminathan uint16_t sub_vendor_id; 1405*bafec742SSukumar Swaminathan uint16_t sub_device_id; 1406*bafec742SSukumar Swaminathan struct ether_addr cur_addr; 1407*bafec742SSukumar Swaminathan } ql_adapter_info_t; 1408*bafec742SSukumar Swaminathan 1409*bafec742SSukumar Swaminathan #define DUMP_DESCRIPTION_HEADER_SIGNATURE 0x42535451 /* "QTSB" */ 1410*bafec742SSukumar Swaminathan typedef struct ql_dump_header { 1411*bafec742SSukumar Swaminathan uint32_t signature; /* QTSB */ 1412*bafec742SSukumar Swaminathan uint8_t version; 1413*bafec742SSukumar Swaminathan uint8_t length; 1414*bafec742SSukumar Swaminathan uint8_t num_dumps; 1415*bafec742SSukumar Swaminathan uint8_t reserved; 1416*bafec742SSukumar Swaminathan uint32_t time_stamp_lo; 1417*bafec742SSukumar Swaminathan uint32_t time_stamp_hi; 1418*bafec742SSukumar Swaminathan } ql_dump_header_t; 1419*bafec742SSukumar Swaminathan 1420*bafec742SSukumar Swaminathan #define DUMP_IMAGE_HEADER_SIGNATURE 0x504D4451 /* "QDMP" */ 1421*bafec742SSukumar Swaminathan 1422*bafec742SSukumar Swaminathan typedef struct ql_dump_image_header { 1423*bafec742SSukumar Swaminathan uint32_t signature; /* QDMP */ 1424*bafec742SSukumar Swaminathan uint8_t version; 1425*bafec742SSukumar Swaminathan uint8_t header_length; 1426*bafec742SSukumar Swaminathan uint16_t checksum; 1427*bafec742SSukumar Swaminathan uint32_t data_type; 1428*bafec742SSukumar Swaminathan #define DUMP_TYPE_CORE_DUMP 1 1429*bafec742SSukumar Swaminathan #define DUMP_TYPE_REGISTER_DUMP 2 1430*bafec742SSukumar Swaminathan #define DUMP_TYPE_DRIVER_DUMP 3 1431*bafec742SSukumar Swaminathan uint32_t data_length; 1432*bafec742SSukumar Swaminathan } ql_dump_image_header_t; 1433*bafec742SSukumar Swaminathan 1434*bafec742SSukumar Swaminathan /* utility request */ 1435*bafec742SSukumar Swaminathan #define DUMP_REQUEST_CORE BIT_1 1436*bafec742SSukumar Swaminathan #define DUMP_REQUEST_REGISTER BIT_2 1437*bafec742SSukumar Swaminathan #define DUMP_REQUEST_DRIVER BIT_3 1438*bafec742SSukumar Swaminathan 1439*bafec742SSukumar Swaminathan #define DUMP_REQUEST_ALL BIT_7 1440*bafec742SSukumar Swaminathan 1441*bafec742SSukumar Swaminathan #define DUMP_DESCRIPTION_FOOTER_SIGNATURE 0x45535451 /* "QTSE" */ 1442*bafec742SSukumar Swaminathan typedef struct ql_dump_footer { 1443*bafec742SSukumar Swaminathan uint32_t signature; /* QTSE */ 1444*bafec742SSukumar Swaminathan uint8_t version; 1445*bafec742SSukumar Swaminathan uint8_t length; 1446*bafec742SSukumar Swaminathan uint16_t reserved; 1447*bafec742SSukumar Swaminathan uint32_t time_stamp_lo; 1448*bafec742SSukumar Swaminathan uint32_t time_stamp_hi; 1449*bafec742SSukumar Swaminathan } ql_dump_footer_t; 1450*bafec742SSukumar Swaminathan 1451*bafec742SSukumar Swaminathan 1452*bafec742SSukumar Swaminathan /* 1453*bafec742SSukumar Swaminathan * Solaris qlnic exit status. 1454*bafec742SSukumar Swaminathan */ 1455*bafec742SSukumar Swaminathan #define QN_ERR_BASE 0x30000000 1456*bafec742SSukumar Swaminathan #define QN_ERR_OK QN_ERR_BASE | 0 /* Success */ 1457*bafec742SSukumar Swaminathan #define QN_ERR_NOT_SUPPORTED QN_ERR_BASE | 1 /* Command not supported */ 1458*bafec742SSukumar Swaminathan #define QN_ERR_INVALID_PARAM QN_ERR_BASE | 2 /* Invalid parameter */ 1459*bafec742SSukumar Swaminathan #define QN_ERR_WRONG_NO_PARAM QN_ERR_BASE | 3 /* Wrong number of parameters */ 1460*bafec742SSukumar Swaminathan #define QN_ERR_FILE_NOT_FOUND QN_ERR_BASE | 4 /* File not found */ 1461*bafec742SSukumar Swaminathan #define QN_ERR_FILE_READ_ERR QN_ERR_BASE | 5 /* File read err */ 1462*bafec742SSukumar Swaminathan #define QN_ERR_FILE_WRITE_ERR QN_ERR_BASE | 6 /* File write err */ 1463*bafec742SSukumar Swaminathan #define QN_ERR_NO_MEMORY QN_ERR_BASE | 7 /* No Memory */ 1464*bafec742SSukumar Swaminathan 1465*bafec742SSukumar Swaminathan #define FLT_REGION_FDT 0x1A 1466*bafec742SSukumar Swaminathan #define ISP_8100_FDT_ADDR 0x360000 1467*bafec742SSukumar Swaminathan #define ISP_8100_FDT_SIZE 0x80 1468*bafec742SSukumar Swaminathan 1469*bafec742SSukumar Swaminathan #define FLT_REGION_FLT 0x1C 1470*bafec742SSukumar Swaminathan #define ISP_8100_FLT_ADDR 0x361000 1471*bafec742SSukumar Swaminathan #define ISP_8100_FLT_SIZE 0x1000 1472*bafec742SSukumar Swaminathan 1473*bafec742SSukumar Swaminathan #define FLT_REGION_NIC_BOOT_CODE 0x2E 1474*bafec742SSukumar Swaminathan #define ISP_8100_NIC_BOOT_CODE_ADDR 0x0 1475*bafec742SSukumar Swaminathan #define ISP_8100_NIC_BOOT_CODE_SIZE 0x80000 1476*bafec742SSukumar Swaminathan 1477*bafec742SSukumar Swaminathan #define FLT_REGION_MPI_FW_USE 0x42 1478*bafec742SSukumar Swaminathan #define ISP_8100_MPI_FW_USE_ADDR 0xF0000 1479*bafec742SSukumar Swaminathan #define ISP_8100_MPI_FW_USE_SIZE 0x10000 1480*bafec742SSukumar Swaminathan 1481*bafec742SSukumar Swaminathan #define FLT_REGION_MPI_RISC_FW 0x40 1482*bafec742SSukumar Swaminathan #define ISP_8100_MPI_RISC_FW_ADDR 0x100000 1483*bafec742SSukumar Swaminathan #define ISP_8100_MPI_RISC_FW_SIZE 0x10000 1484*bafec742SSukumar Swaminathan 1485*bafec742SSukumar Swaminathan #define FLT_REGION_VPD0 0x2C 1486*bafec742SSukumar Swaminathan #define ISP_8100_VPD0_ADDR 0x140000 1487*bafec742SSukumar Swaminathan #define ISP_8100_VPD0_SIZE 0x200 1488*bafec742SSukumar Swaminathan 1489*bafec742SSukumar Swaminathan #define FLT_REGION_NIC_PARAM0 0x46 1490*bafec742SSukumar Swaminathan #define ISP_8100_NIC_PARAM0_ADDR 0x140200 1491*bafec742SSukumar Swaminathan #define ISP_8100_NIC_PARAM0_SIZE 0x200 1492*bafec742SSukumar Swaminathan 1493*bafec742SSukumar Swaminathan #define FLT_REGION_VPD1 0x2D 1494*bafec742SSukumar Swaminathan #define ISP_8100_VPD1_ADDR 0x140400 1495*bafec742SSukumar Swaminathan #define ISP_8100_VPD1_SIZE 0x200 1496*bafec742SSukumar Swaminathan 1497*bafec742SSukumar Swaminathan #define FLT_REGION_NIC_PARAM1 0x47 1498*bafec742SSukumar Swaminathan #define ISP_8100_NIC_PARAM1_ADDR 0x140600 1499*bafec742SSukumar Swaminathan #define ISP_8100_NIC_PARAM1_SIZE 0x200 1500*bafec742SSukumar Swaminathan 1501*bafec742SSukumar Swaminathan #define FLT_REGION_MPI_CFG 0x41 1502*bafec742SSukumar Swaminathan #define ISP_8100_MPI_CFG_ADDR 0x150000 1503*bafec742SSukumar Swaminathan #define ISP_8100_MPI_CFG_SIZE 0x10000 1504*bafec742SSukumar Swaminathan 1505*bafec742SSukumar Swaminathan #define FLT_REGION_EDC_PHY_FW 0x45 1506*bafec742SSukumar Swaminathan #define ISP_8100_EDC_PHY_FW_ADDR 0x170000 1507*bafec742SSukumar Swaminathan #define ISP_8100_EDC_PHY_FW_SIZE 0x20000 1508*bafec742SSukumar Swaminathan 1509*bafec742SSukumar Swaminathan #define FLT_REGION_FC_BOOT_CODE 0x07 1510*bafec742SSukumar Swaminathan #define ISP_8100_FC_BOOT_CODE_ADDR 0x200000 1511*bafec742SSukumar Swaminathan #define ISP_8100_FC_BOOT_CODE_SIZE 0x80000 1512*bafec742SSukumar Swaminathan 1513*bafec742SSukumar Swaminathan #define FLT_REGION_FC_FW 0x01 1514*bafec742SSukumar Swaminathan #define ISP_8100_FC_FW_ADDR 0x280000 1515*bafec742SSukumar Swaminathan #define ISP_8100_FC_FW_SIZE 0x80000 1516*bafec742SSukumar Swaminathan 1517*bafec742SSukumar Swaminathan #define FLT_REGION_FC_VPD0 0x14 1518*bafec742SSukumar Swaminathan #define ISP_8100_FC_VPD0_ADDR 0x340000 1519*bafec742SSukumar Swaminathan #define ISP_8100_FC_VPD0_SIZE 0x200 1520*bafec742SSukumar Swaminathan 1521*bafec742SSukumar Swaminathan #define FLT_REGION_FC_NVRAM0 0x15 1522*bafec742SSukumar Swaminathan #define ISP_8100_FC_NVRAM0_ADDR 0x340200 1523*bafec742SSukumar Swaminathan #define ISP_8100_FC_NVRAM0_SIZE 0x200 1524*bafec742SSukumar Swaminathan 1525*bafec742SSukumar Swaminathan #define FLT_REGION_FC_VPD1 0x16 1526*bafec742SSukumar Swaminathan #define ISP_8100_FC_VPD1_ADDR 0x340400 1527*bafec742SSukumar Swaminathan #define ISP_8100_FC_VPD1_SIZE 0x200 1528*bafec742SSukumar Swaminathan 1529*bafec742SSukumar Swaminathan #define FLT_REGION_FC_NVRAM1 0x17 1530*bafec742SSukumar Swaminathan #define ISP_8100_FC_NVRAM1_ADDR 0x340600 1531*bafec742SSukumar Swaminathan #define ISP_8100_FC_NVRAM1_SIZE 0x200 1532*bafec742SSukumar Swaminathan 1533*bafec742SSukumar Swaminathan #define FLT_REGION_FC_BOOT_CODE 0x07 1534*bafec742SSukumar Swaminathan #define ISP_8100_FC_BOOT_CODE_ADDR 0x200000 1535*bafec742SSukumar Swaminathan #define ISP_8100_FC_BOOT_CODE_SIZE 0x80000 1536*bafec742SSukumar Swaminathan 1537*bafec742SSukumar Swaminathan #define FLT_REGION_FC_FW 0x01 1538*bafec742SSukumar Swaminathan #define ISP_8100_FC_FW_ADDR 0x280000 1539*bafec742SSukumar Swaminathan #define ISP_8100_FC_FW_SIZE 0x80000 1540*bafec742SSukumar Swaminathan 1541*bafec742SSukumar Swaminathan #define FLT_REGION_TIME_STAMP 0x60 1542*bafec742SSukumar Swaminathan 1543*bafec742SSukumar Swaminathan /* flash region for testing */ 1544*bafec742SSukumar Swaminathan #define FLT_REGION_WIN_FW_DUMP0 0x48 1545*bafec742SSukumar Swaminathan #define ISP_8100_WIN_FW_DUMP0_ADDR 0x190000 1546*bafec742SSukumar Swaminathan #define ISP_8100_WIN_FW_DUMP0_SIZE 0x30000 1547*bafec742SSukumar Swaminathan 1548*bafec742SSukumar Swaminathan #define ISP_8100_FLASH_TEST_REGION_ADDR ISP_8100_WIN_FW_DUMP0_ADDR 1549*bafec742SSukumar Swaminathan #define ISP_8100_FLASH_TEST_REGION_SIZE 0x10000 1550*bafec742SSukumar Swaminathan 1551*bafec742SSukumar Swaminathan /* mailbox */ 1552*bafec742SSukumar Swaminathan #define QL_8XXX_SFP_SIZE 256 1553*bafec742SSukumar Swaminathan 1554*bafec742SSukumar Swaminathan #define MAILBOX_TOV 30 /* Default Timeout value. */ 1555*bafec742SSukumar Swaminathan /* 1556*bafec742SSukumar Swaminathan * ISP mailbox commands from Host 1557*bafec742SSukumar Swaminathan */ 1558*bafec742SSukumar Swaminathan #define MBC_NO_OPERATION 0 /* No Operation. */ 1559*bafec742SSukumar Swaminathan #define MBC_LOAD_RAM 1 /* Load RAM. */ 1560*bafec742SSukumar Swaminathan #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1561*bafec742SSukumar Swaminathan #define MBC_MAILBOX_REGISTER_TEST 6 /* Mailbox echo test */ 1562*bafec742SSukumar Swaminathan #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1563*bafec742SSukumar Swaminathan #define MBC_ABOUT_FIRMWARE 8 /* About Firmware. */ 1564*bafec742SSukumar Swaminathan #define MBC_RISC_MEMORY_COPY 0xA /* Copy RISC memory. */ 1565*bafec742SSukumar Swaminathan #define MBC_LOAD_RISC_RAM 0xB /* Load RISC RAM command. */ 1566*bafec742SSukumar Swaminathan #define MBC_DUMP_RISC_RAM 0xC /* Dump RISC RAM command. */ 1567*bafec742SSukumar Swaminathan #define MBC_INIT_RISC_RAM 0xE 1568*bafec742SSukumar Swaminathan #define MBC_READ_RAM_WORD 0xF /* Read RAM */ 1569*bafec742SSukumar Swaminathan #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware */ 1570*bafec742SSukumar Swaminathan #define MBC_GENERATE_SYS_ERROR 0x2A /* Generate System Error */ 1571*bafec742SSukumar Swaminathan #define MBC_WRITE_SFP 0x30 /* Write SFP. */ 1572*bafec742SSukumar Swaminathan #define MBC_READ_SFP 0x31 /* Read SFP. */ 1573*bafec742SSukumar Swaminathan #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1574*bafec742SSukumar Swaminathan #define MBC_GET_INIT_CTRL_BLOCK 0x61 /* Get Initialization CBLK */ 1575*bafec742SSukumar Swaminathan #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1576*bafec742SSukumar Swaminathan #define MBC_IDC_REQUEST 0x100 /* IDC Request. */ 1577*bafec742SSukumar Swaminathan #define IDC_REQ_ALL_DEST_FUNC_MASK BIT_4 /* Mailbox 1 */ 1578*bafec742SSukumar Swaminathan 1579*bafec742SSukumar Swaminathan #define IDC_REQ_DEST_FUNC_0_MASK BIT_0 /* Mailbox 2 */ 1580*bafec742SSukumar Swaminathan #define IDC_REQ_DEST_FUNC_1_MASK BIT_1 1581*bafec742SSukumar Swaminathan #define IDC_REQ_DEST_FUNC_2_MASK BIT_2 1582*bafec742SSukumar Swaminathan #define IDC_REQ_DEST_FUNC_3_MASK BIT_3 1583*bafec742SSukumar Swaminathan 1584*bafec742SSukumar Swaminathan enum IDC_REQ_DEST_FUNC { 1585*bafec742SSukumar Swaminathan IDC_REQ_DEST_FUNC_0, 1586*bafec742SSukumar Swaminathan IDC_REQ_DEST_FUNC_1, 1587*bafec742SSukumar Swaminathan IDC_REQ_DEST_FUNC_2, 1588*bafec742SSukumar Swaminathan IDC_REQ_DEST_FUNC_3, 1589*bafec742SSukumar Swaminathan IDC_REQ_DEST_FUNC_ALL = 0x0F 1590*bafec742SSukumar Swaminathan }; 1591*bafec742SSukumar Swaminathan 1592*bafec742SSukumar Swaminathan #define IDC_REQ_TIMEOUT_MASK 0x01 1593*bafec742SSukumar Swaminathan 1594*bafec742SSukumar Swaminathan #define MBC_IDC_ACK 0x101 /* IDC Acknowledge. */ 1595*bafec742SSukumar Swaminathan #define MBC_IDC_TIME_EXTENDED 0x102 /* IDC Time Extended. */ 1596*bafec742SSukumar Swaminathan 1597*bafec742SSukumar Swaminathan #define MBC_SET_WAKE_ON_LANE_MODE 0x110 1598*bafec742SSukumar Swaminathan #define MBC_SET_WAKE_ON_LANE_FILTER 0x111 1599*bafec742SSukumar Swaminathan #define MBC_CLEAR_WAKE_ON_LANE_FILTER 0x112 1600*bafec742SSukumar Swaminathan #define MBC_SET_WAKE_ON_LANE_MAGIC_PKT 0x113 1601*bafec742SSukumar Swaminathan #define MBC_CLEAR_WAKE_ON_LANE_MAGIC_PKT 0x114 1602*bafec742SSukumar Swaminathan 1603*bafec742SSukumar Swaminathan #define MBC_PORT_RESET 0x120 1604*bafec742SSukumar Swaminathan #define MBC_SET_PORT_CONFIG 0x122 1605*bafec742SSukumar Swaminathan #define MBC_GET_PORT_CONFIG 0x123 1606*bafec742SSukumar Swaminathan #define ENABLE_JUMBO_FRAME_SIZE_MASK BIT_16 1607*bafec742SSukumar Swaminathan #define MBC_GET_LINK_STATUS 0x124 1608*bafec742SSukumar Swaminathan 1609*bafec742SSukumar Swaminathan #define MBC_SET_LED_CONFIG 0x125 1610*bafec742SSukumar Swaminathan #define MBC_GET_LED_CONFIG 0x126 1611*bafec742SSukumar Swaminathan 1612*bafec742SSukumar Swaminathan /* 1613*bafec742SSukumar Swaminathan * ISP mailbox command complete status codes 1614*bafec742SSukumar Swaminathan */ 1615*bafec742SSukumar Swaminathan #define MBS_COMMAND_COMPLETE 0x4000 1616*bafec742SSukumar Swaminathan #define MBS_INVALID_COMMAND 0x4001 1617*bafec742SSukumar Swaminathan #define MBS_HOST_INTERFACE_ERROR 0x4002 1618*bafec742SSukumar Swaminathan #define MBS_TEST_FAILED 0x4003 1619*bafec742SSukumar Swaminathan #define MBS_POST_ERROR 0x4004 1620*bafec742SSukumar Swaminathan #define MBS_COMMAND_ERROR 0x4005 1621*bafec742SSukumar Swaminathan #define MBS_COMMAND_PARAMETER_ERROR 0x4006 1622*bafec742SSukumar Swaminathan #define MBS_PORT_ID_USED 0x4007 1623*bafec742SSukumar Swaminathan #define MBS_LOOP_ID_USED 0x4008 1624*bafec742SSukumar Swaminathan #define MBS_ALL_IDS_IN_USE 0x4009 1625*bafec742SSukumar Swaminathan #define MBS_NOT_LOGGED_IN 0x400A 1626*bafec742SSukumar Swaminathan #define MBS_LOOP_DOWN 0x400B 1627*bafec742SSukumar Swaminathan #define MBS_LOOP_BACK_ERROR 0x400C 1628*bafec742SSukumar Swaminathan #define MBS_CHECKSUM_ERROR 0x4010 1629*bafec742SSukumar Swaminathan 1630*bafec742SSukumar Swaminathan /* Async Event Status */ 1631*bafec742SSukumar Swaminathan #define MBA_IDC_INTERMEDIATE_COMPLETE 0x1000 1632*bafec742SSukumar Swaminathan #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1633*bafec742SSukumar Swaminathan #define MBA_SYSTEM_ERR 0x8002 1634*bafec742SSukumar Swaminathan #define MBA_LINK_UP 0x8011 1635*bafec742SSukumar Swaminathan enum { 1636*bafec742SSukumar Swaminathan XFI_NETWORK_INTERFACE = 1, 1637*bafec742SSukumar Swaminathan XAUI_NETWORK_INTERFACE, 1638*bafec742SSukumar Swaminathan XFI_BACKPLANE_INTERFACE, 1639*bafec742SSukumar Swaminathan XAUI_BACKPLANE_INTERFACE, 1640*bafec742SSukumar Swaminathan EXT_10GBASE_T_PHY, 1641*bafec742SSukumar Swaminathan EXT_EXT_EDC_PHY 1642*bafec742SSukumar Swaminathan }; 1643*bafec742SSukumar Swaminathan #define MBA_LINK_DOWN 0x8012 1644*bafec742SSukumar Swaminathan #define MBA_IDC_COMPLETE 0x8100 1645*bafec742SSukumar Swaminathan #define MBA_IDC_REQUEST_NOTIFICATION 0x8101 1646*bafec742SSukumar Swaminathan #define MBA_IDC_TIME_EXTENDED 0x8102 1647*bafec742SSukumar Swaminathan #define MBA_DCBX_CONFIG_CHANGE 0x8110 1648*bafec742SSukumar Swaminathan #define MBA_NOTIFICATION_LOST 0x8120 1649*bafec742SSukumar Swaminathan #define MBA_SFT_TRANSCEIVER_INSERTION 0x8130 1650*bafec742SSukumar Swaminathan #define MBA_SFT_TRANSCEIVER_REMOVAL 0x8131 1651*bafec742SSukumar Swaminathan #define MBA_FIRMWARE_INIT_COMPLETE 0x8400 1652*bafec742SSukumar Swaminathan #define MBA_FIRMWARE_INIT_FAILED 0x8401 1653*bafec742SSukumar Swaminathan 1654*bafec742SSukumar Swaminathan typedef struct firmware_version_info { 1655*bafec742SSukumar Swaminathan uint8_t reserved; 1656*bafec742SSukumar Swaminathan uint8_t major_version; 1657*bafec742SSukumar Swaminathan uint8_t minor_version; 1658*bafec742SSukumar Swaminathan uint8_t sub_minor_version; 1659*bafec742SSukumar Swaminathan } firmware_version_info_t; 1660*bafec742SSukumar Swaminathan 1661*bafec742SSukumar Swaminathan typedef struct phy_firmware_version_info { 1662*bafec742SSukumar Swaminathan uint8_t reserved; 1663*bafec742SSukumar Swaminathan uint8_t major_version; 1664*bafec742SSukumar Swaminathan uint8_t minor_version; 1665*bafec742SSukumar Swaminathan uint8_t sub_minor_version; 1666*bafec742SSukumar Swaminathan } phy_firmware_version_info_t; 1667*bafec742SSukumar Swaminathan 1668*bafec742SSukumar Swaminathan #define ENABLE_JUMBO BIT_16 1669*bafec742SSukumar Swaminathan #define STD_PAUSE 0x20 1670*bafec742SSukumar Swaminathan #define PP_PAUSE 0x40 1671*bafec742SSukumar Swaminathan #define LOOP_INTERNAL_PARALLEL 0x02 1672*bafec742SSukumar Swaminathan #define LOOP_INTERNAL_SERIAL 0x04 1673*bafec742SSukumar Swaminathan #define LOOP_EXTERNAL_PHY 0x06 1674*bafec742SSukumar Swaminathan 1675*bafec742SSukumar Swaminathan typedef struct port_cfg_info { 1676*bafec742SSukumar Swaminathan uint32_t link_cfg; 1677*bafec742SSukumar Swaminathan uint32_t max_frame_size; 1678*bafec742SSukumar Swaminathan } port_cfg_info_t; 1679*bafec742SSukumar Swaminathan 1680*bafec742SSukumar Swaminathan enum { 1681*bafec742SSukumar Swaminathan PAUSE_MODE_DISABLED, 1682*bafec742SSukumar Swaminathan PAUSE_MODE_STANDARD, /* Standard Ethernet Pause */ 1683*bafec742SSukumar Swaminathan PAUSE_MODE_PER_PRIORITY /* Class Based Pause */ 1684*bafec742SSukumar Swaminathan }; 1685*bafec742SSukumar Swaminathan 1686*bafec742SSukumar Swaminathan /* Mailbox command parameter structure definition. */ 1687*bafec742SSukumar Swaminathan typedef struct mbx_cmd { 1688*bafec742SSukumar Swaminathan uint32_t from_mpi; /* number of Incomming from MPI to driver */ 1689*bafec742SSukumar Swaminathan uint32_t mb[NUM_MAILBOX_REGS]; 1690*bafec742SSukumar Swaminathan clock_t timeout; /* Timeout in seconds. */ 1691*bafec742SSukumar Swaminathan } mbx_cmd_t; 1692*bafec742SSukumar Swaminathan 1693*bafec742SSukumar Swaminathan /* Returned Mailbox registers. */ 1694*bafec742SSukumar Swaminathan typedef struct mbx_data { 1695*bafec742SSukumar Swaminathan uint32_t from_mpi; /* number of Incomming from MPI to driver */ 1696*bafec742SSukumar Swaminathan uint32_t mb[NUM_MAILBOX_REGS]; 1697*bafec742SSukumar Swaminathan } mbx_data_t; 1698*bafec742SSukumar Swaminathan 1699*bafec742SSukumar Swaminathan /* Address/Length pairs for the coredump. */ 1700*bafec742SSukumar Swaminathan 1701*bafec742SSukumar Swaminathan #define MPI_CORE_REGS_ADDR 0x00030000 1702*bafec742SSukumar Swaminathan #define MPI_CORE_REGS_CNT 127 1703*bafec742SSukumar Swaminathan #define MPI_CORE_SH_REGS_CNT 16 1704*bafec742SSukumar Swaminathan #define TEST_REGS_ADDR 0x00001000 1705*bafec742SSukumar Swaminathan #define TEST_REGS_CNT 23 1706*bafec742SSukumar Swaminathan #define RMII_REGS_ADDR 0x00001040 1707*bafec742SSukumar Swaminathan #define RMII_REGS_CNT 64 1708*bafec742SSukumar Swaminathan #define FCMAC1_REGS_ADDR 0x00001080 1709*bafec742SSukumar Swaminathan #define FCMAC2_REGS_ADDR 0x000010c0 1710*bafec742SSukumar Swaminathan #define FCMAC_REGS_CNT 64 1711*bafec742SSukumar Swaminathan #define FC1_MBX_REGS_ADDR 0x00001100 1712*bafec742SSukumar Swaminathan #define FC2_MBX_REGS_ADDR 0x00001240 1713*bafec742SSukumar Swaminathan #define FC_MBX_REGS_CNT 64 1714*bafec742SSukumar Swaminathan #define IDE_REGS_ADDR 0x00001140 1715*bafec742SSukumar Swaminathan #define IDE_REGS_CNT 64 1716*bafec742SSukumar Swaminathan #define NIC1_MBX_REGS_ADDR 0x00001180 1717*bafec742SSukumar Swaminathan #define NIC2_MBX_REGS_ADDR 0x00001280 1718*bafec742SSukumar Swaminathan #define NIC_MBX_REGS_CNT 64 1719*bafec742SSukumar Swaminathan #define SMBUS_REGS_ADDR 0x00001200 1720*bafec742SSukumar Swaminathan #define SMBUS_REGS_CNT 64 1721*bafec742SSukumar Swaminathan #define I2C_REGS_ADDR 0x00001fc0 1722*bafec742SSukumar Swaminathan #define I2C_REGS_CNT 64 1723*bafec742SSukumar Swaminathan #define MEMC_REGS_ADDR 0x00003000 1724*bafec742SSukumar Swaminathan #define MEMC_REGS_CNT 256 1725*bafec742SSukumar Swaminathan #define PBUS_REGS_ADDR 0x00007c00 1726*bafec742SSukumar Swaminathan #define PBUS_REGS_CNT 256 1727*bafec742SSukumar Swaminathan #define MDE_REGS_ADDR 0x00010000 1728*bafec742SSukumar Swaminathan #define MDE_REGS_CNT 6 1729*bafec742SSukumar Swaminathan #define CODE_RAM_ADDR 0x00020000 1730*bafec742SSukumar Swaminathan #define CODE_RAM_CNT 0x2000 1731*bafec742SSukumar Swaminathan #define MEMC_RAM_ADDR 0x00100000 1732*bafec742SSukumar Swaminathan #define MEMC_RAM_CNT 0x2000 1733*bafec742SSukumar Swaminathan 1734*bafec742SSukumar Swaminathan /* 64 probes, 8 bytes per probe + 4 bytes to list the probe ID */ 1735*bafec742SSukumar Swaminathan #define PROBE_DATA_LENGTH_WORDS ((64 * 2) + 1) 1736*bafec742SSukumar Swaminathan #define NUMBER_OF_PROBES 34 1737*bafec742SSukumar Swaminathan #define NUMBER_ROUTING_REG_ENTRIES 48 1738*bafec742SSukumar Swaminathan #define WORDS_PER_ROUTING_REG_ENTRY 4 1739*bafec742SSukumar Swaminathan #define MAC_PROTOCOL_REGISTER_WORDS ((512 * 3) + (32 * 2) + (4096 * 1) + \ 1740*bafec742SSukumar Swaminathan (4096 * 1) + (4 * 2) + (8 * 2) + \ 1741*bafec742SSukumar Swaminathan (16 * 1) + (4 * 1) + (4 * 4) + \ 1742*bafec742SSukumar Swaminathan (4 * 1)) 1743*bafec742SSukumar Swaminathan /* Save both the address and data register */ 1744*bafec742SSukumar Swaminathan #define WORDS_PER_MAC_PROT_ENTRY 2 1745*bafec742SSukumar Swaminathan 1746*bafec742SSukumar Swaminathan #define MPI_COREDUMP_COOKIE 0x5555aaaa 1747*bafec742SSukumar Swaminathan typedef struct mpi_coredump_global_header { 1748*bafec742SSukumar Swaminathan uint32_t cookie; 1749*bafec742SSukumar Swaminathan char id_string[16]; 1750*bafec742SSukumar Swaminathan uint32_t time_lo; 1751*bafec742SSukumar Swaminathan uint32_t time_hi; 1752*bafec742SSukumar Swaminathan uint32_t total_image_size; 1753*bafec742SSukumar Swaminathan uint32_t global_header_size; 1754*bafec742SSukumar Swaminathan char driver_info[0xE0]; 1755*bafec742SSukumar Swaminathan }mpi_coredump_global_header_t; 1756*bafec742SSukumar Swaminathan 1757*bafec742SSukumar Swaminathan typedef struct mpi_coredump_segment_header { 1758*bafec742SSukumar Swaminathan uint32_t cookie; 1759*bafec742SSukumar Swaminathan uint32_t seg_number; 1760*bafec742SSukumar Swaminathan uint32_t seg_size; 1761*bafec742SSukumar Swaminathan uint32_t extra; 1762*bafec742SSukumar Swaminathan char description[16]; 1763*bafec742SSukumar Swaminathan }mpi_coredump_segment_header_t; 1764*bafec742SSukumar Swaminathan 1765*bafec742SSukumar Swaminathan typedef struct ql_mpi_coredump { 1766*bafec742SSukumar Swaminathan mpi_coredump_global_header_t mpi_global_header; 1767*bafec742SSukumar Swaminathan 1768*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t core_regs_seg_hdr; 1769*bafec742SSukumar Swaminathan uint32_t mpi_core_regs[MPI_CORE_REGS_CNT]; 1770*bafec742SSukumar Swaminathan uint32_t mpi_core_sh_regs[MPI_CORE_SH_REGS_CNT]; 1771*bafec742SSukumar Swaminathan 1772*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t test_logic_regs_seg_hdr; 1773*bafec742SSukumar Swaminathan uint32_t test_logic_regs[TEST_REGS_CNT]; 1774*bafec742SSukumar Swaminathan 1775*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t rmii_regs_seg_hdr; 1776*bafec742SSukumar Swaminathan uint32_t rmii_regs[RMII_REGS_CNT]; 1777*bafec742SSukumar Swaminathan 1778*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t fcmac1_regs_seg_hdr; 1779*bafec742SSukumar Swaminathan uint32_t fcmac1_regs[FCMAC_REGS_CNT]; 1780*bafec742SSukumar Swaminathan 1781*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t fcmac2_regs_seg_hdr; 1782*bafec742SSukumar Swaminathan uint32_t fcmac2_regs[FCMAC_REGS_CNT]; 1783*bafec742SSukumar Swaminathan 1784*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t fc1_mbx_regs_seg_hdr; 1785*bafec742SSukumar Swaminathan uint32_t fc1_mbx_regs[FC_MBX_REGS_CNT]; 1786*bafec742SSukumar Swaminathan 1787*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t ide_regs_seg_hdr; 1788*bafec742SSukumar Swaminathan uint32_t ide_regs[IDE_REGS_CNT]; 1789*bafec742SSukumar Swaminathan 1790*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t nic1_mbx_regs_seg_hdr; 1791*bafec742SSukumar Swaminathan uint32_t nic1_mbx_regs[NIC_MBX_REGS_CNT]; 1792*bafec742SSukumar Swaminathan 1793*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t smbus_regs_seg_hdr; 1794*bafec742SSukumar Swaminathan uint32_t smbus_regs[SMBUS_REGS_CNT]; 1795*bafec742SSukumar Swaminathan 1796*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t fc2_mbx_regs_seg_hdr; 1797*bafec742SSukumar Swaminathan uint32_t fc2_mbx_regs[FC_MBX_REGS_CNT]; 1798*bafec742SSukumar Swaminathan 1799*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t nic2_mbx_regs_seg_hdr; 1800*bafec742SSukumar Swaminathan uint32_t nic2_mbx_regs[NIC_MBX_REGS_CNT]; 1801*bafec742SSukumar Swaminathan 1802*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t i2c_regs_seg_hdr; 1803*bafec742SSukumar Swaminathan uint32_t i2c_regs[I2C_REGS_CNT]; 1804*bafec742SSukumar Swaminathan 1805*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t memc_regs_seg_hdr; 1806*bafec742SSukumar Swaminathan uint32_t memc_regs[MEMC_REGS_CNT]; 1807*bafec742SSukumar Swaminathan 1808*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t pbus_regs_seg_hdr; 1809*bafec742SSukumar Swaminathan uint32_t pbus_regs[PBUS_REGS_CNT]; 1810*bafec742SSukumar Swaminathan 1811*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t mde_regs_seg_hdr; 1812*bafec742SSukumar Swaminathan uint32_t mde_regs[MDE_REGS_CNT]; 1813*bafec742SSukumar Swaminathan 1814*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t xaui_an_hdr; 1815*bafec742SSukumar Swaminathan uint32_t serdes_xaui_an[14]; 1816*bafec742SSukumar Swaminathan 1817*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t xaui_hss_pcs_hdr; 1818*bafec742SSukumar Swaminathan uint32_t serdes_xaui_hss_pcs[33]; 1819*bafec742SSukumar Swaminathan 1820*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t xfi_an_hdr; 1821*bafec742SSukumar Swaminathan uint32_t serdes_xfi_an[14]; 1822*bafec742SSukumar Swaminathan 1823*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t xfi_train_hdr; 1824*bafec742SSukumar Swaminathan uint32_t serdes_xfi_train[12]; 1825*bafec742SSukumar Swaminathan 1826*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t xfi_hss_pcs_hdr; 1827*bafec742SSukumar Swaminathan uint32_t serdes_xfi_hss_pcs[15]; 1828*bafec742SSukumar Swaminathan 1829*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t xfi_hss_tx_hdr; 1830*bafec742SSukumar Swaminathan uint32_t serdes_xfi_hss_tx[32]; 1831*bafec742SSukumar Swaminathan 1832*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t xfi_hss_rx_hdr; 1833*bafec742SSukumar Swaminathan uint32_t serdes_xfi_hss_rx[32]; 1834*bafec742SSukumar Swaminathan 1835*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t xfi_hss_pll_hdr; 1836*bafec742SSukumar Swaminathan uint32_t serdes_xfi_hss_pll[32]; 1837*bafec742SSukumar Swaminathan 1838*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t nic_regs_seg_hdr; 1839*bafec742SSukumar Swaminathan uint32_t nic_regs[64]; 1840*bafec742SSukumar Swaminathan 1841*bafec742SSukumar Swaminathan /* one interrupt state for each CQ */ 1842*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t intr_states_seg_hdr; 1843*bafec742SSukumar Swaminathan uint32_t intr_states[MAX_RX_RINGS]; 1844*bafec742SSukumar Swaminathan 1845*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t xgmac_seg_hdr; 1846*bafec742SSukumar Swaminathan #define XGMAC_REGISTER_END 0x740 1847*bafec742SSukumar Swaminathan uint32_t xgmac[XGMAC_REGISTER_END]; 1848*bafec742SSukumar Swaminathan 1849*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t probe_dump_seg_hdr; 1850*bafec742SSukumar Swaminathan uint32_t probe_dump[PROBE_DATA_LENGTH_WORDS * NUMBER_OF_PROBES]; 1851*bafec742SSukumar Swaminathan 1852*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t routing_reg_seg_hdr; 1853*bafec742SSukumar Swaminathan uint32_t routing_regs[NUMBER_ROUTING_REG_ENTRIES * WORDS_PER_ROUTING_REG_ENTRY]; 1854*bafec742SSukumar Swaminathan 1855*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t mac_prot_reg_seg_hdr; 1856*bafec742SSukumar Swaminathan uint32_t mac_prot_regs[MAC_PROTOCOL_REGISTER_WORDS * WORDS_PER_MAC_PROT_ENTRY]; 1857*bafec742SSukumar Swaminathan 1858*bafec742SSukumar Swaminathan 1859*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t ets_seg_hdr; 1860*bafec742SSukumar Swaminathan uint32_t ets[8+2]; 1861*bafec742SSukumar Swaminathan 1862*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t code_ram_seg_hdr; 1863*bafec742SSukumar Swaminathan uint32_t code_ram[CODE_RAM_CNT]; 1864*bafec742SSukumar Swaminathan 1865*bafec742SSukumar Swaminathan mpi_coredump_segment_header_t memc_ram_seg_hdr; 1866*bafec742SSukumar Swaminathan uint32_t memc_ram[MEMC_RAM_CNT]; 1867*bafec742SSukumar Swaminathan 1868*bafec742SSukumar Swaminathan } ql_mpi_coredump_t; 1869*bafec742SSukumar Swaminathan 1870*bafec742SSukumar Swaminathan #define WCS_MPI_CODE_RAM_LENGTH (0x2000*4) 1871*bafec742SSukumar Swaminathan #define MEMC_MPI_RAM_LENGTH (0x2000*4) 1872*bafec742SSukumar Swaminathan 1873*bafec742SSukumar Swaminathan #define XG_SERDES_ADDR_RDY BIT_31 1874*bafec742SSukumar Swaminathan #define XG_SERDES_ADDR_R BIT_30 1875*bafec742SSukumar Swaminathan 1876*bafec742SSukumar Swaminathan #define CORE_SEG_NUM 1 1877*bafec742SSukumar Swaminathan #define TEST_LOGIC_SEG_NUM 2 1878*bafec742SSukumar Swaminathan #define RMII_SEG_NUM 3 1879*bafec742SSukumar Swaminathan #define FCMAC1_SEG_NUM 4 1880*bafec742SSukumar Swaminathan #define FCMAC2_SEG_NUM 5 1881*bafec742SSukumar Swaminathan #define FC1_MBOX_SEG_NUM 6 1882*bafec742SSukumar Swaminathan #define IDE_SEG_NUM 7 1883*bafec742SSukumar Swaminathan #define NIC1_MBOX_SEG_NUM 8 1884*bafec742SSukumar Swaminathan #define SMBUS_SEG_NUM 9 1885*bafec742SSukumar Swaminathan #define FC2_MBOX_SEG_NUM 10 1886*bafec742SSukumar Swaminathan #define NIC2_MBOX_SEG_NUM 11 1887*bafec742SSukumar Swaminathan #define I2C_SEG_NUM 12 1888*bafec742SSukumar Swaminathan #define MEMC_SEG_NUM 13 1889*bafec742SSukumar Swaminathan #define PBUS_SEG_NUM 14 1890*bafec742SSukumar Swaminathan #define MDE_SEG_NUM 15 1891*bafec742SSukumar Swaminathan #define NIC1_CONTROL_SEG_NUM 16 1892*bafec742SSukumar Swaminathan #define NIC2_CONTROL_SEG_NUM 17 1893*bafec742SSukumar Swaminathan #define NIC1_XGMAC_SEG_NUM 18 1894*bafec742SSukumar Swaminathan #define NIC2_XGMAC_SEG_NUM 19 1895*bafec742SSukumar Swaminathan #define WCS_RAM_SEG_NUM 20 1896*bafec742SSukumar Swaminathan #define MEMC_RAM_SEG_NUM 21 1897*bafec742SSukumar Swaminathan #define XAUI_AN_SEG_NUM 22 1898*bafec742SSukumar Swaminathan #define XAUI_HSS_PCS_SEG_NUM 23 1899*bafec742SSukumar Swaminathan #define XFI_AN_SEG_NUM 24 1900*bafec742SSukumar Swaminathan #define XFI_TRAIN_SEG_NUM 25 1901*bafec742SSukumar Swaminathan #define XFI_HSS_PCS_SEG_NUM 26 1902*bafec742SSukumar Swaminathan #define XFI_HSS_TX_SEG_NUM 27 1903*bafec742SSukumar Swaminathan #define XFI_HSS_RX_SEG_NUM 28 1904*bafec742SSukumar Swaminathan #define XFI_HSS_PLL_SEG_NUM 29 1905*bafec742SSukumar Swaminathan #define INTR_STATES_SEG_NUM 31 1906*bafec742SSukumar Swaminathan #define ETS_SEG_NUM 34 1907*bafec742SSukumar Swaminathan #define PROBE_DUMP_SEG_NUM 35 1908*bafec742SSukumar Swaminathan #define ROUTING_INDEX_SEG_NUM 36 1909*bafec742SSukumar Swaminathan #define MAC_PROTOCOL_SEG_NUM 37 1910*bafec742SSukumar Swaminathan 1911*bafec742SSukumar Swaminathan /* Force byte packing for the following structures */ 1912*bafec742SSukumar Swaminathan #pragma pack(1) 1913*bafec742SSukumar Swaminathan 1914*bafec742SSukumar Swaminathan /* 1915*bafec742SSukumar Swaminathan * Work Queue (Request Queue) Initialization Control Block (WQICB) 1916*bafec742SSukumar Swaminathan */ 1917*bafec742SSukumar Swaminathan 1918*bafec742SSukumar Swaminathan struct wqicb_t { 1919*bafec742SSukumar Swaminathan uint16_t len; 1920*bafec742SSukumar Swaminathan #define Q_LEN_V (1 << 4) 1921*bafec742SSukumar Swaminathan #define Q_LEN_CPP_CONT 0x0000 1922*bafec742SSukumar Swaminathan #define Q_LEN_CPP_16 0x0001 1923*bafec742SSukumar Swaminathan #define Q_LEN_CPP_32 0x0002 1924*bafec742SSukumar Swaminathan #define Q_LEN_CPP_64 0x0003 1925*bafec742SSukumar Swaminathan #define Q_LEN_CPP_512 0x0006 1926*bafec742SSukumar Swaminathan uint16_t flags; 1927*bafec742SSukumar Swaminathan #define Q_PRI_SHIFT 1 1928*bafec742SSukumar Swaminathan #define Q_FLAGS_LC 0x1000 1929*bafec742SSukumar Swaminathan #define Q_FLAGS_LB 0x2000 1930*bafec742SSukumar Swaminathan #define Q_FLAGS_LI 0x4000 1931*bafec742SSukumar Swaminathan #define Q_FLAGS_LO 0x8000 1932*bafec742SSukumar Swaminathan uint16_t cq_id_rss; 1933*bafec742SSukumar Swaminathan #define Q_CQ_ID_RSS_RV 0x8000 1934*bafec742SSukumar Swaminathan uint16_t rid; 1935*bafec742SSukumar Swaminathan uint32_t wq_addr_lo; 1936*bafec742SSukumar Swaminathan uint32_t wq_addr_hi; 1937*bafec742SSukumar Swaminathan uint32_t cnsmr_idx_addr_lo; 1938*bafec742SSukumar Swaminathan uint32_t cnsmr_idx_addr_hi; 1939*bafec742SSukumar Swaminathan }; 1940*bafec742SSukumar Swaminathan 1941*bafec742SSukumar Swaminathan /* 1942*bafec742SSukumar Swaminathan * Completion Queue (Response Queue) Initialization Control Block (CQICB) 1943*bafec742SSukumar Swaminathan */ 1944*bafec742SSukumar Swaminathan 1945*bafec742SSukumar Swaminathan struct cqicb_t { 1946*bafec742SSukumar Swaminathan uint8_t msix_vect; 1947*bafec742SSukumar Swaminathan uint8_t reserved1; 1948*bafec742SSukumar Swaminathan uint8_t reserved2; 1949*bafec742SSukumar Swaminathan uint8_t flags; 1950*bafec742SSukumar Swaminathan #define FLAGS_LV 0x08 1951*bafec742SSukumar Swaminathan #define FLAGS_LS 0x10 1952*bafec742SSukumar Swaminathan #define FLAGS_LL 0x20 1953*bafec742SSukumar Swaminathan #define FLAGS_LI 0x40 1954*bafec742SSukumar Swaminathan #define FLAGS_LC 0x80 1955*bafec742SSukumar Swaminathan uint16_t len; 1956*bafec742SSukumar Swaminathan #define LEN_V (1 << 4) 1957*bafec742SSukumar Swaminathan #define LEN_CPP_CONT 0x0000 1958*bafec742SSukumar Swaminathan #define LEN_CPP_32 0x0001 1959*bafec742SSukumar Swaminathan #define LEN_CPP_64 0x0002 1960*bafec742SSukumar Swaminathan #define LEN_CPP_128 0x0003 1961*bafec742SSukumar Swaminathan uint16_t rid; 1962*bafec742SSukumar Swaminathan uint32_t cq_base_addr_lo; /* completion queue base address */ 1963*bafec742SSukumar Swaminathan uint32_t cq_base_addr_hi; 1964*bafec742SSukumar Swaminathan uint32_t prod_idx_addr_lo; /* completion queue host copy */ 1965*bafec742SSukumar Swaminathan /* producer index host shadow */ 1966*bafec742SSukumar Swaminathan uint32_t prod_idx_addr_hi; 1967*bafec742SSukumar Swaminathan uint16_t pkt_delay; 1968*bafec742SSukumar Swaminathan uint16_t irq_delay; 1969*bafec742SSukumar Swaminathan uint32_t lbq_addr_lo; 1970*bafec742SSukumar Swaminathan uint32_t lbq_addr_hi; 1971*bafec742SSukumar Swaminathan uint16_t lbq_buf_size; 1972*bafec742SSukumar Swaminathan uint16_t lbq_len; /* entry count */ 1973*bafec742SSukumar Swaminathan uint32_t sbq_addr_lo; 1974*bafec742SSukumar Swaminathan uint32_t sbq_addr_hi; 1975*bafec742SSukumar Swaminathan uint16_t sbq_buf_size; 1976*bafec742SSukumar Swaminathan uint16_t sbq_len; /* entry count */ 1977*bafec742SSukumar Swaminathan }; 1978*bafec742SSukumar Swaminathan 1979*bafec742SSukumar Swaminathan struct ricb { 1980*bafec742SSukumar Swaminathan uint8_t base_cq; 1981*bafec742SSukumar Swaminathan #define RSS_L4K 0x80 1982*bafec742SSukumar Swaminathan uint8_t flags; 1983*bafec742SSukumar Swaminathan #define RSS_L6K 0x01 1984*bafec742SSukumar Swaminathan #define RSS_LI 0x02 1985*bafec742SSukumar Swaminathan #define RSS_LB 0x04 1986*bafec742SSukumar Swaminathan #define RSS_LM 0x08 1987*bafec742SSukumar Swaminathan #define RSS_RI4 0x10 1988*bafec742SSukumar Swaminathan #define RSS_RT4 0x20 1989*bafec742SSukumar Swaminathan #define RSS_RI6 0x40 1990*bafec742SSukumar Swaminathan #define RSS_RT6 0x80 1991*bafec742SSukumar Swaminathan uint16_t mask; 1992*bafec742SSukumar Swaminathan #define RSS_HASH_CQ_ID_MAX 1024 1993*bafec742SSukumar Swaminathan uint8_t hash_cq_id[RSS_HASH_CQ_ID_MAX]; 1994*bafec742SSukumar Swaminathan uint32_t ipv6_hash_key[10]; 1995*bafec742SSukumar Swaminathan uint32_t ipv4_hash_key[4]; 1996*bafec742SSukumar Swaminathan }; 1997*bafec742SSukumar Swaminathan 1998*bafec742SSukumar Swaminathan /* 1999*bafec742SSukumar Swaminathan * Host Command IOCB Formats 2000*bafec742SSukumar Swaminathan */ 2001*bafec742SSukumar Swaminathan 2002*bafec742SSukumar Swaminathan #define OPCODE_OB_MAC_IOCB 0x01 2003*bafec742SSukumar Swaminathan #define OPCODE_OB_MAC_OFFLOAD_IOCB 0x02 2004*bafec742SSukumar Swaminathan 2005*bafec742SSukumar Swaminathan #define OPCODE_IB_MAC_IOCB 0x20 2006*bafec742SSukumar Swaminathan #define OPCODE_IB_SYS_EVENT_IOCB 0x3f 2007*bafec742SSukumar Swaminathan 2008*bafec742SSukumar Swaminathan /* 2009*bafec742SSukumar Swaminathan * The following constants define control bits for buffer 2010*bafec742SSukumar Swaminathan * length fields for all IOCB's. 2011*bafec742SSukumar Swaminathan */ 2012*bafec742SSukumar Swaminathan #define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */ 2013*bafec742SSukumar Swaminathan #define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */ 2014*bafec742SSukumar Swaminathan 2015*bafec742SSukumar Swaminathan struct oal_entry { 2016*bafec742SSukumar Swaminathan uint32_t buf_addr_low; 2017*bafec742SSukumar Swaminathan uint32_t buf_addr_high; 2018*bafec742SSukumar Swaminathan uint32_t buf_len; 2019*bafec742SSukumar Swaminathan }; 2020*bafec742SSukumar Swaminathan 2021*bafec742SSukumar Swaminathan /* 32 words, 128 bytes */ 2022*bafec742SSukumar Swaminathan #define TX_DESC_PER_IOCB 8 /* Number of descs in one TX IOCB */ 2023*bafec742SSukumar Swaminathan 2024*bafec742SSukumar Swaminathan struct ob_mac_iocb_req { 2025*bafec742SSukumar Swaminathan uint8_t opcode; 2026*bafec742SSukumar Swaminathan uint8_t flag0; 2027*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_IPv6 0x80 2028*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_IPv4 0x40 2029*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_D 0x08 /* disable generation of comp. msg */ 2030*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_I 0x02 /* disable generation of intr at comp */ 2031*bafec742SSukumar Swaminathan uint8_t flag1; 2032*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_TC 0x80 /* enable TCP checksum offload */ 2033*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_UC 0x40 /* enable UDP checksum offload */ 2034*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_LSO 0x20 /* enable LSO offload */ 2035*bafec742SSukumar Swaminathan uint8_t flag2; 2036*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_VLAN_OFFSET_MASK 0xF8 /* VLAN TCI insert */ 2037*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_V 0x04 /* insert VLAN TCI */ 2038*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_DFP 0x02 /* Drop for Failover port */ 2039*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_REQ_IC 0x01 /* enable IP checksum offload */ 2040*bafec742SSukumar Swaminathan uint32_t unused; 2041*bafec742SSukumar Swaminathan uint32_t reserved_cq_tag; 2042*bafec742SSukumar Swaminathan uint32_t frame_len; /* max 9000,for none LSO, 16M for LSO */ 2043*bafec742SSukumar Swaminathan uint32_t tid; 2044*bafec742SSukumar Swaminathan uint32_t txq_idx; 2045*bafec742SSukumar Swaminathan uint16_t protocol_hdr_len; 2046*bafec742SSukumar Swaminathan uint16_t hdr_off; /* tcp/udp hdr offset */ 2047*bafec742SSukumar Swaminathan uint16_t vlan_tci; 2048*bafec742SSukumar Swaminathan uint16_t mss; 2049*bafec742SSukumar Swaminathan 2050*bafec742SSukumar Swaminathan struct oal_entry oal_entry[TX_DESC_PER_IOCB]; /* max FFFFF 1M bytes */ 2051*bafec742SSukumar Swaminathan 2052*bafec742SSukumar Swaminathan }; 2053*bafec742SSukumar Swaminathan /* 16 words, 64 bytes */ 2054*bafec742SSukumar Swaminathan struct ob_mac_iocb_rsp { 2055*bafec742SSukumar Swaminathan uint8_t opcode; 2056*bafec742SSukumar Swaminathan uint8_t flags1; 2057*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_RSP_OI 0x01 /* */ 2058*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_RSP_I 0x02 /* */ 2059*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_RSP_E 0x08 /* */ 2060*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */ 2061*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */ 2062*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */ 2063*bafec742SSukumar Swaminathan 2064*bafec742SSukumar Swaminathan uint8_t flags2; 2065*bafec742SSukumar Swaminathan uint8_t flags3; 2066*bafec742SSukumar Swaminathan 2067*bafec742SSukumar Swaminathan #define OB_MAC_IOCB_RSP_B 0x80 2068*bafec742SSukumar Swaminathan 2069*bafec742SSukumar Swaminathan uint32_t tid; 2070*bafec742SSukumar Swaminathan uint32_t txq_idx; 2071*bafec742SSukumar Swaminathan 2072*bafec742SSukumar Swaminathan uint32_t reserved[13]; 2073*bafec742SSukumar Swaminathan }; 2074*bafec742SSukumar Swaminathan 2075*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff 2076*bafec742SSukumar Swaminathan 2077*bafec742SSukumar Swaminathan struct ib_mac_iocb_rsp { 2078*bafec742SSukumar Swaminathan uint8_t opcode; /* 0x20 */ 2079*bafec742SSukumar Swaminathan uint8_t flags1; 2080*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */ 2081*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */ 2082*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */ 2083*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */ 2084*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */ 2085*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */ 2086*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */ 2087*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */ 2088*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */ 2089*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */ 2090*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */ 2091*bafec742SSukumar Swaminathan uint8_t flags2; 2092*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */ 2093*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */ 2094*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */ 2095*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04 2096*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08 2097*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10 2098*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14 2099*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18 2100*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c 2101*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */ 2102*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */ 2103*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */ 2104*bafec742SSukumar Swaminathan uint8_t flags3; 2105*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */ 2106*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */ 2107*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */ 2108*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */ 2109*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */ 2110*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */ 2111*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */ 2112*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */ 2113*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */ 2114*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */ 2115*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */ 2116*bafec742SSukumar Swaminathan uint32_t data_len; 2117*bafec742SSukumar Swaminathan uint64_t data_addr; 2118*bafec742SSukumar Swaminathan uint32_t rss; 2119*bafec742SSukumar Swaminathan uint16_t vlan_id; /* 12 bits */ 2120*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_VLAN_ID_MASK 0xFFF 2121*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */ 2122*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */ 2123*bafec742SSukumar Swaminathan 2124*bafec742SSukumar Swaminathan uint16_t reserved1; 2125*bafec742SSukumar Swaminathan uint32_t reserved2[6]; 2126*bafec742SSukumar Swaminathan uint8_t reserved3[3]; 2127*bafec742SSukumar Swaminathan uint8_t flags4; 2128*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_HV 0x20 2129*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_HS 0x40 2130*bafec742SSukumar Swaminathan #define IB_MAC_IOCB_RSP_HL 0x80 2131*bafec742SSukumar Swaminathan uint32_t hdr_len; 2132*bafec742SSukumar Swaminathan uint64_t hdr_addr; 2133*bafec742SSukumar Swaminathan }; 2134*bafec742SSukumar Swaminathan 2135*bafec742SSukumar Swaminathan /* 16 words, 64 bytes */ 2136*bafec742SSukumar Swaminathan struct ib_sys_event_iocb_rsp { 2137*bafec742SSukumar Swaminathan uint8_t opcode; 2138*bafec742SSukumar Swaminathan uint8_t flag0; 2139*bafec742SSukumar Swaminathan uint8_t event_type; 2140*bafec742SSukumar Swaminathan uint8_t q_id; 2141*bafec742SSukumar Swaminathan uint32_t reserved[15]; 2142*bafec742SSukumar Swaminathan }; 2143*bafec742SSukumar Swaminathan #define SYS_EVENT_PORT_LINK_UP 0x0 2144*bafec742SSukumar Swaminathan #define SYS_EVENT_PORT_LINK_DOWN 0x1 2145*bafec742SSukumar Swaminathan #define SYS_EVENT_MULTIPLE_CAM_HITS 0x6 2146*bafec742SSukumar Swaminathan #define SYS_EVENT_SOFT_ECC_ERR 0x7 2147*bafec742SSukumar Swaminathan #define SYS_EVENT_MGMT_FATAL_ERR 0x8 /* MPI_PROCESSOR */ 2148*bafec742SSukumar Swaminathan #define SYS_EVENT_MAC_INTERRUPT 0x9 2149*bafec742SSukumar Swaminathan #define SYS_EVENT_PCI_ERR_READING_SML_LRG_BUF 0x40 2150*bafec742SSukumar Swaminathan 2151*bafec742SSukumar Swaminathan /* 2152*bafec742SSukumar Swaminathan * Status Register (#define STATUS) bit definitions. 2153*bafec742SSukumar Swaminathan */ 2154*bafec742SSukumar Swaminathan #define STATUS_FE (1 << 0) 2155*bafec742SSukumar Swaminathan #define STATUS_PI (1 << 1) 2156*bafec742SSukumar Swaminathan #define STATUS_PL0 (1 << 2), 2157*bafec742SSukumar Swaminathan #define STATUS_PL1 (1 << 3) 2158*bafec742SSukumar Swaminathan #define STATUS_PI0 (1 << 4) 2159*bafec742SSukumar Swaminathan #define STATUS_PI1 (1 << 5) 2160*bafec742SSukumar Swaminathan #define STATUS_FUNC_ID_MASK 0x000000c0 2161*bafec742SSukumar Swaminathan #define STATUS_FUNC_ID_SHIFT 6 2162*bafec742SSukumar Swaminathan #define STATUS_F0E (1 << 8) 2163*bafec742SSukumar Swaminathan #define STATUS_F1E (1 << 9) 2164*bafec742SSukumar Swaminathan #define STATUS_F2E (1 << 10) 2165*bafec742SSukumar Swaminathan #define STATUS_F3E (1 << 11) 2166*bafec742SSukumar Swaminathan #define STATUS_NFE (1 << 12) 2167*bafec742SSukumar Swaminathan 2168*bafec742SSukumar Swaminathan /* 2169*bafec742SSukumar Swaminathan * Generic Response Queue IOCB Format which abstracts the difference between 2170*bafec742SSukumar Swaminathan * IB_MAC, OB_MAC IOCBs 2171*bafec742SSukumar Swaminathan */ 2172*bafec742SSukumar Swaminathan struct net_rsp_iocb { 2173*bafec742SSukumar Swaminathan uint8_t opcode; 2174*bafec742SSukumar Swaminathan uint8_t flag0; 2175*bafec742SSukumar Swaminathan uint8_t flag1; 2176*bafec742SSukumar Swaminathan uint8_t flag2; 2177*bafec742SSukumar Swaminathan uint32_t reserved[15]; 2178*bafec742SSukumar Swaminathan }; 2179*bafec742SSukumar Swaminathan 2180*bafec742SSukumar Swaminathan /* Restore original packing rules */ 2181*bafec742SSukumar Swaminathan #pragma pack() 2182*bafec742SSukumar Swaminathan 2183*bafec742SSukumar Swaminathan #define RESPONSE_ENTRY_SIZE (sizeof (struct net_rsp_iocb)) 2184*bafec742SSukumar Swaminathan #define REQUEST_ENTRY_SIZE (sizeof (struct ob_mac_iocb_req)) 2185*bafec742SSukumar Swaminathan 2186*bafec742SSukumar Swaminathan /* flash */ 2187*bafec742SSukumar Swaminathan /* Little endian machine correction defines. */ 2188*bafec742SSukumar Swaminathan #ifdef _LITTLE_ENDIAN 2189*bafec742SSukumar Swaminathan #define LITTLE_ENDIAN_16(x) 2190*bafec742SSukumar Swaminathan #define LITTLE_ENDIAN_24(x) 2191*bafec742SSukumar Swaminathan #define LITTLE_ENDIAN_32(x) 2192*bafec742SSukumar Swaminathan #define LITTLE_ENDIAN_64(x) 2193*bafec742SSukumar Swaminathan #define LITTLE_ENDIAN(bp, bytes) 2194*bafec742SSukumar Swaminathan #define BIG_ENDIAN_16(x) ql_change_endian((uint8_t *)x, 2) 2195*bafec742SSukumar Swaminathan #define BIG_ENDIAN_24(x) ql_change_endian((uint8_t *)x, 3) 2196*bafec742SSukumar Swaminathan #define BIG_ENDIAN_32(x) ql_change_endian((uint8_t *)x, 4) 2197*bafec742SSukumar Swaminathan #define BIG_ENDIAN_64(x) ql_change_endian((uint8_t *)x, 8) 2198*bafec742SSukumar Swaminathan #define BIG_ENDIAN(bp, bytes) ql_change_endian((uint8_t *)bp, bytes) 2199*bafec742SSukumar Swaminathan #endif /* _LITTLE_ENDIAN */ 2200*bafec742SSukumar Swaminathan 2201*bafec742SSukumar Swaminathan /* Big endian machine correction defines. */ 2202*bafec742SSukumar Swaminathan #ifdef _BIG_ENDIAN 2203*bafec742SSukumar Swaminathan #define LITTLE_ENDIAN_16(x) ql_change_endian((uint8_t *)x, 2) 2204*bafec742SSukumar Swaminathan #define LITTLE_ENDIAN_24(x) ql_change_endian((uint8_t *)x, 3) 2205*bafec742SSukumar Swaminathan #define LITTLE_ENDIAN_32(x) ql_change_endian((uint8_t *)x, 4) 2206*bafec742SSukumar Swaminathan #define LITTLE_ENDIAN_64(x) ql_change_endian((uint8_t *)x, 8) 2207*bafec742SSukumar Swaminathan #define LITTLE_ENDIAN(bp, bytes) ql_change_endian((uint8_t *)bp, bytes) 2208*bafec742SSukumar Swaminathan #define BIG_ENDIAN_16(x) 2209*bafec742SSukumar Swaminathan #define BIG_ENDIAN_24(x) 2210*bafec742SSukumar Swaminathan #define BIG_ENDIAN_32(x) 2211*bafec742SSukumar Swaminathan #define BIG_ENDIAN_64(x) 2212*bafec742SSukumar Swaminathan #define BIG_ENDIAN(bp, bytes) 2213*bafec742SSukumar Swaminathan #endif /* _BIG_ENDIAN */ 2214*bafec742SSukumar Swaminathan 2215*bafec742SSukumar Swaminathan void ql_change_endian(uint8_t *, size_t); 2216*bafec742SSukumar Swaminathan 2217*bafec742SSukumar Swaminathan /* Flash Address Register 0x88 */ 2218*bafec742SSukumar Swaminathan #define FLASH_RDY_FLAG BIT_31 2219*bafec742SSukumar Swaminathan #define FLASH_R_FLAG BIT_30 2220*bafec742SSukumar Swaminathan #define FLASH_ERR_FLAG BIT_29 2221*bafec742SSukumar Swaminathan #define FLASH_CONF_ADDR 0x7D0000u 2222*bafec742SSukumar Swaminathan #define FLASH_ADDR_MASK 0x7F0000 2223*bafec742SSukumar Swaminathan 2224*bafec742SSukumar Swaminathan #define FLASH_WRSR_CMD 0x01 2225*bafec742SSukumar Swaminathan #define FLASH_PP_CMD 0x02 2226*bafec742SSukumar Swaminathan #define FLASH_READ_CMD 0x03 2227*bafec742SSukumar Swaminathan #define FLASH_WRDI_CMD 0x04 2228*bafec742SSukumar Swaminathan #define FLASH_RDSR_CMD 0x05 2229*bafec742SSukumar Swaminathan #define FLASH_WREN_CMD 0x06 2230*bafec742SSukumar Swaminathan #define FLASH_RDID_CMD 0x9F 2231*bafec742SSukumar Swaminathan #define FLASH_RES_CMD 0xAB 2232*bafec742SSukumar Swaminathan 2233*bafec742SSukumar Swaminathan /* 2234*bafec742SSukumar Swaminathan * Flash definitions. 2235*bafec742SSukumar Swaminathan */ 2236*bafec742SSukumar Swaminathan typedef struct ql_flash_info { 2237*bafec742SSukumar Swaminathan uint32_t type; /* flash type */ 2238*bafec742SSukumar Swaminathan uint32_t flash_size; /* length in bytes of flash */ 2239*bafec742SSukumar Swaminathan uint32_t sec_mask; /* sector number mask */ 2240*bafec742SSukumar Swaminathan uint8_t flash_manuf; /* flash chip manufacturer id */ 2241*bafec742SSukumar Swaminathan uint8_t flash_id; /* flash chip id */ 2242*bafec742SSukumar Swaminathan uint8_t flash_cap; /* flash chip capacity */ 2243*bafec742SSukumar Swaminathan } ql_flash_info_t; 2244*bafec742SSukumar Swaminathan 2245*bafec742SSukumar Swaminathan /* 2246*bafec742SSukumar Swaminathan * Flash Description Table 2247*bafec742SSukumar Swaminathan */ 2248*bafec742SSukumar Swaminathan #define FLASH_DESC_VERSION 1 2249*bafec742SSukumar Swaminathan #define FLASH_DESC_VAILD 0x44494C51 /* "QLID" */ 2250*bafec742SSukumar Swaminathan typedef struct flash_desc { 2251*bafec742SSukumar Swaminathan uint32_t flash_valid; 2252*bafec742SSukumar Swaminathan uint16_t flash_version; 2253*bafec742SSukumar Swaminathan uint16_t flash_len; /* flash description table length */ 2254*bafec742SSukumar Swaminathan uint16_t flash_checksum; 2255*bafec742SSukumar Swaminathan uint16_t flash_unused; 2256*bafec742SSukumar Swaminathan uint8_t flash_model[16]; 2257*bafec742SSukumar Swaminathan uint16_t flash_manuf; 2258*bafec742SSukumar Swaminathan uint16_t flash_id; 2259*bafec742SSukumar Swaminathan uint8_t flash_flag; 2260*bafec742SSukumar Swaminathan uint8_t erase_cmd; 2261*bafec742SSukumar Swaminathan uint8_t alt_erase_cmd; 2262*bafec742SSukumar Swaminathan uint8_t write_enable_cmd; 2263*bafec742SSukumar Swaminathan uint8_t write_enable_bits; 2264*bafec742SSukumar Swaminathan uint8_t write_statusreg_cmd; 2265*bafec742SSukumar Swaminathan uint8_t unprotect_sector_cmd; 2266*bafec742SSukumar Swaminathan uint8_t read_manuf_cmd; 2267*bafec742SSukumar Swaminathan uint32_t block_size; 2268*bafec742SSukumar Swaminathan uint32_t alt_block_size; 2269*bafec742SSukumar Swaminathan uint32_t flash_size; 2270*bafec742SSukumar Swaminathan uint32_t write_enable_data; 2271*bafec742SSukumar Swaminathan uint8_t readid_address_len; 2272*bafec742SSukumar Swaminathan uint8_t write_disable_bits; 2273*bafec742SSukumar Swaminathan uint8_t read_device_id_len; 2274*bafec742SSukumar Swaminathan uint8_t chip_erase_cmd; 2275*bafec742SSukumar Swaminathan uint16_t read_timeout; 2276*bafec742SSukumar Swaminathan uint8_t protect_sector_cmd; 2277*bafec742SSukumar Swaminathan uint8_t exp_reserved[65]; 2278*bafec742SSukumar Swaminathan } flash_desc_t; 2279*bafec742SSukumar Swaminathan 2280*bafec742SSukumar Swaminathan /* flash manufacturer id's */ 2281*bafec742SSukumar Swaminathan #define AMD_FLASH 0x01 /* AMD / Spansion */ 2282*bafec742SSukumar Swaminathan #define ST_FLASH 0x20 /* ST Electronics */ 2283*bafec742SSukumar Swaminathan #define SST_FLASH 0xbf /* SST Electronics */ 2284*bafec742SSukumar Swaminathan #define MXIC_FLASH 0xc2 /* Macronix (MXIC) */ 2285*bafec742SSukumar Swaminathan #define ATMEL_FLASH 0x1f /* Atmel (AT26DF081A) */ 2286*bafec742SSukumar Swaminathan #define WINBOND_FLASH 0xef /* Winbond (W25X16,W25X32) */ 2287*bafec742SSukumar Swaminathan #define INTEL_FLASH 0x89 /* Intel (QB25F016S33B8) */ 2288*bafec742SSukumar Swaminathan 2289*bafec742SSukumar Swaminathan /* flash id defines */ 2290*bafec742SSukumar Swaminathan #define AMD_FLASHID_128K 0x6e /* 128k AMD flash chip */ 2291*bafec742SSukumar Swaminathan #define AMD_FLASHID_512K 0x4f /* 512k AMD flash chip */ 2292*bafec742SSukumar Swaminathan #define AMD_FLASHID_512Kt 0xb9 /* 512k AMD flash chip - top boot blk */ 2293*bafec742SSukumar Swaminathan #define AMD_FLASHID_512Kb 0xba /* 512k AMD flash chip - btm boot blk */ 2294*bafec742SSukumar Swaminathan #define AMD_FLASHID_1024K 0x38 /* 1 MB AMD flash chip */ 2295*bafec742SSukumar Swaminathan #define ST_FLASHID_128K 0x23 /* 128k ST flash chip */ 2296*bafec742SSukumar Swaminathan #define ST_FLASHID_512K 0xe3 /* 512k ST flash chip */ 2297*bafec742SSukumar Swaminathan #define ST_FLASHID_M25PXX 0x20 /* M25Pxx ST flash chip */ 2298*bafec742SSukumar Swaminathan #define SST_FLASHID_128K 0xd5 /* 128k SST flash chip */ 2299*bafec742SSukumar Swaminathan #define SST_FLASHID_1024K 0xd8 /* 1 MB SST flash chip */ 2300*bafec742SSukumar Swaminathan #define SST_FLASHID_1024K_A 0x80 /* 1 MB SST 25LF080A flash chip */ 2301*bafec742SSukumar Swaminathan #define SST_FLASHID_1024K_B 0x8e /* 1 MB SST 25VF080B flash chip */ 2302*bafec742SSukumar Swaminathan #define SST_FLASHID_2048K 0x25 /* 2 MB SST 25VF016B flash chip */ 2303*bafec742SSukumar Swaminathan #define MXIC_FLASHID_512K 0x4f /* 512k MXIC flash chip */ 2304*bafec742SSukumar Swaminathan #define MXIC_FLASHID_1024K 0x38 /* 1 MB MXIC flash chip */ 2305*bafec742SSukumar Swaminathan #define MXIC_FLASHID_25LXX 0x20 /* 25Lxx MXIC flash chip */ 2306*bafec742SSukumar Swaminathan #define ATMEL_FLASHID_1024K 0x45 /* 1 MB ATMEL flash chip */ 2307*bafec742SSukumar Swaminathan #define SPAN_FLASHID_2048K 0x02 /* 2 MB Spansion flash chip */ 2308*bafec742SSukumar Swaminathan #define WINBOND_FLASHID 0x30 /* Winbond W25Xxx flash chip */ 2309*bafec742SSukumar Swaminathan #define INTEL_FLASHID 0x89 /* Intel QB25F016S33B8 flash chip */ 2310*bafec742SSukumar Swaminathan 2311*bafec742SSukumar Swaminathan /* flash type defines */ 2312*bafec742SSukumar Swaminathan #define FLASH128 BIT_0 2313*bafec742SSukumar Swaminathan #define FLASH512 BIT_1 2314*bafec742SSukumar Swaminathan #define FLASH512S BIT_2 2315*bafec742SSukumar Swaminathan #define FLASH1024 BIT_3 2316*bafec742SSukumar Swaminathan #define FLASH2048 BIT_4 2317*bafec742SSukumar Swaminathan #define FLASH4096 BIT_5 2318*bafec742SSukumar Swaminathan #define FLASH8192 BIT_6 2319*bafec742SSukumar Swaminathan #define FLASH_PAGE BIT_31 2320*bafec742SSukumar Swaminathan #define FLASH_LEGACY (FLASH128 | FLASH512S) 2321*bafec742SSukumar Swaminathan 2322*bafec742SSukumar Swaminathan #define FLASH_FIRMWARE_IMAGE_ADDR 0x100000 /* 1M */ 2323*bafec742SSukumar Swaminathan typedef struct { 2324*bafec742SSukumar Swaminathan uint8_t signature[2]; 2325*bafec742SSukumar Swaminathan uint8_t reserved[0x16]; 2326*bafec742SSukumar Swaminathan uint8_t dataoffset[2]; 2327*bafec742SSukumar Swaminathan uint8_t pad[6]; 2328*bafec742SSukumar Swaminathan } pci_header_t; 2329*bafec742SSukumar Swaminathan 2330*bafec742SSukumar Swaminathan typedef struct { 2331*bafec742SSukumar Swaminathan uint8_t signature[4]; 2332*bafec742SSukumar Swaminathan uint8_t vid[2]; 2333*bafec742SSukumar Swaminathan uint8_t did[2]; 2334*bafec742SSukumar Swaminathan uint8_t reserved0[2]; 2335*bafec742SSukumar Swaminathan uint8_t pcidatalen[2]; 2336*bafec742SSukumar Swaminathan uint8_t pcidatarev; 2337*bafec742SSukumar Swaminathan uint8_t classcode[3]; 2338*bafec742SSukumar Swaminathan uint8_t imagelength[2]; /* In sectors */ 2339*bafec742SSukumar Swaminathan uint8_t revisionlevel[2]; 2340*bafec742SSukumar Swaminathan uint8_t codetype; 2341*bafec742SSukumar Swaminathan uint8_t indicator; 2342*bafec742SSukumar Swaminathan uint8_t reserved1[2]; 2343*bafec742SSukumar Swaminathan uint8_t pad[8]; 2344*bafec742SSukumar Swaminathan } pci_data_t; 2345*bafec742SSukumar Swaminathan 2346*bafec742SSukumar Swaminathan #define PCI_HEADER0 0x55 2347*bafec742SSukumar Swaminathan #define PCI_HEADER1 0xAA 2348*bafec742SSukumar Swaminathan #define PCI_DATASIG "PCIR" 2349*bafec742SSukumar Swaminathan #define PCI_SECTOR_SIZE 0x200 2350*bafec742SSukumar Swaminathan #define PCI_CODE_X86PC 0 2351*bafec742SSukumar Swaminathan #define PCI_CODE_FCODE 1 2352*bafec742SSukumar Swaminathan #define PCI_CODE_HPPA 2 2353*bafec742SSukumar Swaminathan #define PCI_CODE_EFI 3 2354*bafec742SSukumar Swaminathan #define PCI_CODE_FW 0xfe 2355*bafec742SSukumar Swaminathan #define PCI_IND_LAST_IMAGE 0x80 2356*bafec742SSukumar Swaminathan #define SBUS_CODE_FCODE 0xf1 2357*bafec742SSukumar Swaminathan 2358*bafec742SSukumar Swaminathan #define FBUFSIZE 100 2359*bafec742SSukumar Swaminathan /* Flash Layout Table Data Structure(FLTDS) */ 2360*bafec742SSukumar Swaminathan #define FLASH_FLTDS_SIGNATURE 0x544C4651 /* "QFLT" */ 2361*bafec742SSukumar Swaminathan 2362*bafec742SSukumar Swaminathan typedef struct ql_fltds { 2363*bafec742SSukumar Swaminathan uint32_t signature; 2364*bafec742SSukumar Swaminathan uint16_t flt_addr_lo; 2365*bafec742SSukumar Swaminathan uint16_t flt_addr_hi; 2366*bafec742SSukumar Swaminathan uint8_t version; 2367*bafec742SSukumar Swaminathan uint8_t reserved; 2368*bafec742SSukumar Swaminathan uint16_t checksum; 2369*bafec742SSukumar Swaminathan } ql_fltds_t; 2370*bafec742SSukumar Swaminathan /* Image Layout Table Data Structure(ILTDS) */ 2371*bafec742SSukumar Swaminathan #define FLASH_ILTDS_SIGNATURE 0x4D494651 /* "QFIM" */ 2372*bafec742SSukumar Swaminathan typedef struct ql_iltds_header { 2373*bafec742SSukumar Swaminathan uint32_t signature; 2374*bafec742SSukumar Swaminathan uint16_t table_version; /* version of this structure */ 2375*bafec742SSukumar Swaminathan uint16_t length; /* length of the table */ 2376*bafec742SSukumar Swaminathan uint16_t checksum; 2377*bafec742SSukumar Swaminathan uint16_t number_entries; /* Number of type/len/size entries */ 2378*bafec742SSukumar Swaminathan uint16_t reserved; 2379*bafec742SSukumar Swaminathan uint16_t version; /* version of the image */ 2380*bafec742SSukumar Swaminathan } ql_iltds_header_t; 2381*bafec742SSukumar Swaminathan 2382*bafec742SSukumar Swaminathan #define IMAGE_TABLE_HEADER_LEN sizeof (ql_iltds_header_t) 2383*bafec742SSukumar Swaminathan 2384*bafec742SSukumar Swaminathan #define ILTDS_REGION_VERSION_LEN_NA 0 /* version not applicable */ 2385*bafec742SSukumar Swaminathan typedef struct ql_iltds_img_entry { 2386*bafec742SSukumar Swaminathan uint16_t region_type; 2387*bafec742SSukumar Swaminathan uint8_t region_version_len; 2388*bafec742SSukumar Swaminathan uint8_t region_version[3]; 2389*bafec742SSukumar Swaminathan uint16_t offset_lo; 2390*bafec742SSukumar Swaminathan uint16_t offset_hi; 2391*bafec742SSukumar Swaminathan uint16_t size_lo; 2392*bafec742SSukumar Swaminathan uint16_t size_hi; 2393*bafec742SSukumar Swaminathan uint8_t swap_mode; 2394*bafec742SSukumar Swaminathan #define ILTDS_IMG_SWAP_NONE 0 /* no swap needed */ 2395*bafec742SSukumar Swaminathan #define ILTDS_IMG_SWAP_WORD 1 2396*bafec742SSukumar Swaminathan 2397*bafec742SSukumar Swaminathan uint8_t card_type; 2398*bafec742SSukumar Swaminathan #define ILTDS_IMG_CARD_TYPE_ALL 0 /* apply to all types */ 2399*bafec742SSukumar Swaminathan #define ILTDS_IMG_CARD_TYPE_SR 1 /* apply to SR/fc cards */ 2400*bafec742SSukumar Swaminathan #define ILTDS_IMG_CARD_TYPE_COPPER 2 /* apply to Copper cards */ 2401*bafec742SSukumar Swaminathan #define ILTDS_IMG_CARD_TYPE_MEZZ 4 /* apply to Mezz cards */ 2402*bafec742SSukumar Swaminathan } ql_iltds_img_entry_t; 2403*bafec742SSukumar Swaminathan 2404*bafec742SSukumar Swaminathan #define IMAGE_TABLE_ENTRY_LEN sizeof (ql_iltds_img_entry_t) 2405*bafec742SSukumar Swaminathan 2406*bafec742SSukumar Swaminathan typedef struct ql_iltds_time_stamp { 2407*bafec742SSukumar Swaminathan uint16_t region_type; 2408*bafec742SSukumar Swaminathan uint8_t region_version_len; 2409*bafec742SSukumar Swaminathan uint8_t region_version[3]; 2410*bafec742SSukumar Swaminathan uint8_t year; 2411*bafec742SSukumar Swaminathan uint8_t month; 2412*bafec742SSukumar Swaminathan uint8_t day; 2413*bafec742SSukumar Swaminathan uint8_t hour; 2414*bafec742SSukumar Swaminathan uint8_t min; 2415*bafec742SSukumar Swaminathan uint8_t sec; 2416*bafec742SSukumar Swaminathan uint32_t reserved; 2417*bafec742SSukumar Swaminathan } ql_iltds_time_stamp_t; 2418*bafec742SSukumar Swaminathan 2419*bafec742SSukumar Swaminathan #define IMAGE_TABLE_TIME_STAMP_LEN sizeof (ql_iltds_time_stamp_t) 2420*bafec742SSukumar Swaminathan 2421*bafec742SSukumar Swaminathan #define IMAGE_TABLE_IMAGE_DEFAULT_ENTRIES 5 2422*bafec742SSukumar Swaminathan 2423*bafec742SSukumar Swaminathan typedef struct ql_iltds_description_header { 2424*bafec742SSukumar Swaminathan ql_iltds_header_t iltds_table_header; 2425*bafec742SSukumar Swaminathan ql_iltds_img_entry_t img_entry[IMAGE_TABLE_IMAGE_DEFAULT_ENTRIES]; 2426*bafec742SSukumar Swaminathan ql_iltds_time_stamp_t time_stamp; 2427*bafec742SSukumar Swaminathan }ql_iltds_description_header_t; 2428*bafec742SSukumar Swaminathan 2429*bafec742SSukumar Swaminathan #define ILTDS_DESCRIPTION_HEADERS_LEN sizeof (ql_iltds_description_header_t) 2430*bafec742SSukumar Swaminathan 2431*bafec742SSukumar Swaminathan /* flash layout table definition */ 2432*bafec742SSukumar Swaminathan /* header */ 2433*bafec742SSukumar Swaminathan typedef struct ql_flt_header { 2434*bafec742SSukumar Swaminathan uint16_t version; 2435*bafec742SSukumar Swaminathan uint16_t length; /* length of the flt table,no table header */ 2436*bafec742SSukumar Swaminathan uint16_t checksum; 2437*bafec742SSukumar Swaminathan uint16_t reserved; 2438*bafec742SSukumar Swaminathan } ql_flt_header_t; 2439*bafec742SSukumar Swaminathan 2440*bafec742SSukumar Swaminathan /* table entry */ 2441*bafec742SSukumar Swaminathan typedef struct ql_flt_entry { 2442*bafec742SSukumar Swaminathan uint8_t region; 2443*bafec742SSukumar Swaminathan uint8_t reserved0; 2444*bafec742SSukumar Swaminathan uint8_t attr; 2445*bafec742SSukumar Swaminathan #define FLT_ATTR_READ_ONLY BIT_0 2446*bafec742SSukumar Swaminathan #define FLT_ATTR_NEED_FW_RESTART BIT_1 2447*bafec742SSukumar Swaminathan #define FLT_ATTR_NEED_DATA_REALOAD BIT_2 2448*bafec742SSukumar Swaminathan uint8_t reserved1; 2449*bafec742SSukumar Swaminathan uint32_t size; 2450*bafec742SSukumar Swaminathan uint32_t begin_addr; 2451*bafec742SSukumar Swaminathan uint32_t end_addr; 2452*bafec742SSukumar Swaminathan } ql_flt_entry_t; 2453*bafec742SSukumar Swaminathan 2454*bafec742SSukumar Swaminathan /* flt table */ 2455*bafec742SSukumar Swaminathan typedef struct ql_flt { 2456*bafec742SSukumar Swaminathan ql_flt_header_t header; 2457*bafec742SSukumar Swaminathan uint16_t num_entries; 2458*bafec742SSukumar Swaminathan ql_flt_entry_t *ql_flt_entry_ptr; 2459*bafec742SSukumar Swaminathan } ql_flt_t; 2460*bafec742SSukumar Swaminathan 2461*bafec742SSukumar Swaminathan /* Nic Configuration Table */ 2462*bafec742SSukumar Swaminathan #define FLASH_NIC_CONFIG_SIGNATURE 0x30303038 /* "8000" */ 2463*bafec742SSukumar Swaminathan 2464*bafec742SSukumar Swaminathan enum { 2465*bafec742SSukumar Swaminathan DATA_TYPE_NONE, 2466*bafec742SSukumar Swaminathan DATA_TYPE_FACTORY_MAC_ADDR, 2467*bafec742SSukumar Swaminathan DATA_TYPE_CLP_MAC_ADDR, 2468*bafec742SSukumar Swaminathan DATA_TYPE_CLP_VLAN_MAC_ADDR, 2469*bafec742SSukumar Swaminathan DATA_TYPE_RESERVED, 2470*bafec742SSukumar Swaminathan DATA_TYPE_LAST_ENTRY 2471*bafec742SSukumar Swaminathan }; 2472*bafec742SSukumar Swaminathan 2473*bafec742SSukumar Swaminathan typedef struct ql_nic_config { 2474*bafec742SSukumar Swaminathan uint32_t signature; 2475*bafec742SSukumar Swaminathan uint16_t version; 2476*bafec742SSukumar Swaminathan uint16_t size; 2477*bafec742SSukumar Swaminathan uint16_t checksum; 2478*bafec742SSukumar Swaminathan uint16_t reserved0; 2479*bafec742SSukumar Swaminathan uint16_t total_data_size; 2480*bafec742SSukumar Swaminathan uint16_t num_of_entries; 2481*bafec742SSukumar Swaminathan uint8_t factory_data_type; 2482*bafec742SSukumar Swaminathan uint8_t factory_data_type_size; 2483*bafec742SSukumar Swaminathan uint8_t factory_MAC[6]; 2484*bafec742SSukumar Swaminathan uint8_t clp_data_type; 2485*bafec742SSukumar Swaminathan uint8_t clp_data_type_size; 2486*bafec742SSukumar Swaminathan uint8_t clp_MAC[6]; 2487*bafec742SSukumar Swaminathan uint8_t clp_vlan_data_type; 2488*bafec742SSukumar Swaminathan uint8_t clp_vlan_data_type_size; 2489*bafec742SSukumar Swaminathan uint16_t vlan_id; 2490*bafec742SSukumar Swaminathan uint8_t last_data_type; 2491*bafec742SSukumar Swaminathan uint8_t last_data_type_size; 2492*bafec742SSukumar Swaminathan uint16_t last_entry; 2493*bafec742SSukumar Swaminathan uint8_t reserved1[464]; 2494*bafec742SSukumar Swaminathan uint16_t subsys_vendor_id; 2495*bafec742SSukumar Swaminathan uint16_t subsys_device_id; 2496*bafec742SSukumar Swaminathan uint8_t reserved2[4]; 2497*bafec742SSukumar Swaminathan } ql_nic_config_t; 2498*bafec742SSukumar Swaminathan 2499*bafec742SSukumar Swaminathan #ifdef __cplusplus 2500*bafec742SSukumar Swaminathan } 2501*bafec742SSukumar Swaminathan #endif 2502*bafec742SSukumar Swaminathan 2503*bafec742SSukumar Swaminathan #endif /* _QLGE_HW_H */ 2504