1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2010 QLogic Corporation. All rights reserved.
24  */
25 
26 #ifndef _QLGE_H
27 #define	_QLGE_H
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 #include <sys/ddi.h>
34 #include <sys/sunddi.h>
35 #include <sys/sunmdi.h>
36 #include <sys/modctl.h>
37 #include <sys/pci.h>
38 #include <sys/dlpi.h>
39 #include <sys/sdt.h>
40 #include <sys/mac_provider.h>
41 #include <sys/mac.h>
42 #include <sys/mac_flow.h>
43 #include <sys/mac_ether.h>
44 #include <sys/vlan.h>
45 #include <sys/netlb.h>
46 #include <sys/kmem.h>
47 #include <sys/file.h>
48 #include <sys/proc.h>
49 #include <sys/callb.h>
50 #include <sys/disp.h>
51 #include <sys/strsun.h>
52 #include <sys/ethernet.h>
53 #include <sys/miiregs.h>
54 #include <sys/kstat.h>
55 #include <sys/byteorder.h>
56 #include <sys/ddifm.h>
57 #include <sys/fm/protocol.h>
58 #include <sys/fm/util.h>
59 #include <sys/fm/io/ddi.h>
60 
61 #include <qlge_hw.h>
62 #include <qlge_dbg.h>
63 #include <qlge_open.h>
64 
65 #define	ADAPTER_NAME		"qlge"
66 
67 /*
68  * Local Macro Definitions.
69  */
70 #ifdef  TRUE
71 #undef  TRUE
72 #endif
73 #define	TRUE	1
74 
75 #ifdef  FALSE
76 #undef  FALSE
77 #endif
78 #define	FALSE	0
79 
80 /* #define QLGE_TRACK_BUFFER_USAGE */
81 /*
82  * byte order, sparc is big endian, x86 is little endian,
83  * but PCI is little endian only
84  */
85 #ifdef sparc
86 #define	cpu_to_le64(x)	BSWAP_64(x)
87 #define	cpu_to_le32(x)	BSWAP_32(x)
88 #define	cpu_to_le16(x)	BSWAP_16(x)
89 #define	le64_to_cpu(x)	cpu_to_le64(x)
90 #define	le32_to_cpu(x)	cpu_to_le32(x)
91 #define	le16_to_cpu(x)	cpu_to_le16(x)
92 #else
93 #define	cpu_to_le64(x)	(x)
94 #define	cpu_to_le32(x)	(x)
95 #define	cpu_to_le16(x)	(x)
96 #define	le64_to_cpu(x)	(x)
97 #define	le32_to_cpu(x)	(x)
98 #define	le16_to_cpu(x)	(x)
99 #endif
100 
101 /*
102  * Macros to help code, maintain, etc.
103  */
104 
105 #define	LSB(x)			(uint8_t)(x)
106 #define	MSB(x)			(uint8_t)((uint16_t)(x) >> 8)
107 
108 #define	MSW(x)			(uint16_t)((uint32_t)(x) >> 16)
109 #define	LSW(x)			(uint16_t)(x)
110 
111 #define	MS32(x)			(uint32_t)((uint32_t)(x) >> 32)
112 #define	LS32(x)			(uint32_t)(x)
113 
114 #define	MSW_LSB(x)		(uint8_t)(LSB(MSW(x)))
115 #define	MSW_MSB(x)		(uint8_t)(MSB(MSW(x)))
116 
117 #define	LSD(x)			(uint32_t)(x)
118 #define	MSD(x)			(uint32_t)((uint64_t)(x) >> 32)
119 
120 #define	SHORT_TO_LONG(a, b)	(uint32_t)((uint16_t)b << 16 | (uint16_t)a)
121 #define	CHAR_TO_SHORT(a, b)	(uint16_t)((uint8_t)b << 8 | (uint8_t)a)
122 
123 #define	SWAP_ENDIAN_16(x)	((LSB(x) << 8) | MSB(x))
124 
125 #define	SWAP_ENDIAN_32(x)	((SWAP_ENDIAN_16(LSW(x)) << 16) | \
126 				    SWAP_ENDIAN_16(MSW(x)))
127 
128 #define	SWAP_ENDIAN_64(x)	((SWAP_ENDIAN_32(LS32(x)) << 32) | \
129 				    SWAP_ENDIAN_32(MS32(x)))
130 
131 #define	QL_MIN(x, y)		((x < y) ? x : y)
132 
133 #define	CARRIER_ON(qlge)	mac_link_update((qlge)->mh, LINK_STATE_UP)
134 #define	CARRIER_OFF(qlge)	mac_link_update((qlge)->mh, LINK_STATE_DOWN)
135 
136 /*
137  * qlge local function return status codes
138  */
139 #define	QL_ERROR		1
140 #define	QL_SUCCESS		0
141 /*
142  * Solaris version compatibility definitions.
143  */
144 #define	QL_GET_LBOLT(timer)	timer = ddi_get_lbolt()
145 #define	QL_DMA_XFER_COUNTER	(uint64_t)0xffffffff
146 #define	QL_DRIVER_NAME(dip)	ddi_driver_name(ddi_get_parent(dip))
147 
148 #define	MINOR_NODE_FLAG		8
149 
150 /*
151  * Host adapter default definitions.
152  */
153 
154 /* Timeout timer counts in seconds (must greater than 1 second). */
155 #define	USEC_PER_TICK		drv_hztousec(1)
156 #define	TICKS_PER_SEC		drv_usectohz(1000000)
157 #define	QL_ONE_SEC_DELAY	1000000
158 #define	QL_ONE_MSEC_DELAY	1000
159 #define	TX_TIMEOUT		3*TICKS_PER_SEC
160 /*
161  * DMA attributes definitions.
162  */
163 #define	QL_DMA_LOW_ADDRESS		(uint64_t)0
164 #define	QL_DMA_HIGH_64BIT_ADDRESS	(uint64_t)0xffffffffffffffffull
165 #define	QL_DMA_HIGH_32BIT_ADDRESS	(uint64_t)0xffffffff
166 #define	QL_DMA_ADDRESS_ALIGNMENT	(uint64_t)8
167 #define	QL_DMA_ALIGN_8_BYTE_BOUNDARY	(uint64_t)BIT_3
168 #define	QL_DMA_RING_ADDRESS_ALIGNMENT	(uint64_t)64
169 #define	QL_DMA_ALIGN_64_BYTE_BOUNDARY	(uint64_t)BIT_6
170 #define	QL_DMA_BURSTSIZES		0xfff
171 #define	QL_DMA_MIN_XFER_SIZE		1
172 #define	QL_DMA_MAX_XFER_SIZE		(uint64_t)0xffffffff
173 #define	QL_DMA_SEGMENT_BOUNDARY		(uint64_t)0xffffffff
174 #define	QL_DMA_GRANULARITY		1
175 #define	QL_DMA_XFER_FLAGS		0
176 #define	QL_MAX_COOKIES			16
177 
178 /*
179  * ISP PCI Configuration.
180  */
181 #define	QL_INTR_INTERVAL	128	/* default interrupt interval 128us */
182 #define	QL_INTR_PKTS		8	/* default packet count threshold 8us */
183 
184 /* GLD */
185 #define	QL_STREAM_OPS(dev_ops, attach, detach)	\
186 	DDI_DEFINE_STREAM_OPS(dev_ops, nulldev, nulldev, attach, detach, \
187 	    nodev, NULL, D_MP, NULL, ql_quiesce)
188 
189 #define	QL_GET_DEV(dip)		((qlge_t *)(ddi_get_driver_private(dip)))
190 #define	RESUME_TX(tx_ring)		mac_tx_update(tx_ring->qlge->mh);
191 #define	RX_UPSTREAM(rx_ring, mp)	mac_rx(rx_ring->qlge->mh, \
192 					    rx_ring->qlge->handle, mp);
193 
194 /* GLD DMA */
195 extern ddi_device_acc_attr_t ql_dev_acc_attr;
196 extern ddi_device_acc_attr_t ql_desc_acc_attr;
197 extern ddi_device_acc_attr_t ql_buf_acc_attr;
198 
199 struct dma_info {
200 	void		 *vaddr;
201 	ddi_dma_handle_t dma_handle;
202 	ddi_acc_handle_t acc_handle;
203 	uint64_t	 dma_addr;
204 	size_t		 mem_len; /* allocated size */
205 	offset_t	 offset;  /* relative to handle	*/
206 };
207 
208 /*
209  * Sync a DMA area described by a dma_info
210  */
211 #define	DMA_SYNC(area, flag)	((void) ddi_dma_sync((area).dma_handle,	\
212 				    (area).offset, (area).mem_len, (flag)))
213 
214 /*
215  * Find the (kernel virtual) address of block of memory
216  * described by a dma_info
217  */
218 #define	DMA_VPTR(area)		((area).vaddr)
219 
220 /*
221  * Zero a block of memory described by a dma_info
222  */
223 #define	DMA_ZERO(area)		bzero(DMA_VPTR(area), (area).mem_len)
224 
225 #define	MAX_SG_ELEMENTS		16
226 #define	QL_MAX_TX_DMA_HANDLES	MAX_SG_ELEMENTS
227 #define	TOTAL_SG_ELEMENTS	(MAX_SG_ELEMENTS + TX_DESC_PER_IOCB)
228 
229 /*
230  * ISP PCI Configuration.
231  */
232 
233 /* Initialize steps */
234 #define	INIT_SOFTSTATE_ALLOC 		BIT_0
235 #define	INIT_REGS_SETUP			BIT_1
236 #define	INIT_DOORBELL_REGS_SETUP	BIT_2
237 #define	INIT_MAC_ALLOC			BIT_3
238 #define	INIT_PCI_CONFIG_SETUP   	BIT_4
239 #define	INIT_SETUP_RINGS		BIT_5
240 #define	INIT_MEMORY_ALLOC		BIT_6
241 #define	INIT_INTR_ALLOC			BIT_7
242 #define	INIT_ADD_INTERRUPT		BIT_8
243 #define	INIT_LOCKS_CREATED		BIT_9
244 #define	INIT_ADD_SOFT_INTERRUPT		BIT_10
245 #define	INIT_MUTEX			BIT_11
246 #define	ADAPTER_INIT			BIT_12
247 #define	INIT_MAC_REGISTERED		BIT_13
248 #define	INIT_KSTATS			BIT_14
249 #define	INIT_FM				BIT_15
250 #define	INIT_ADAPTER_UP			BIT_16
251 #define	INIT_ALLOC_RX_BUF		BIT_17
252 #define	INIT_INTR_ENABLED		BIT_18
253 
254 
255 #define	LS_64BITS(x)	(uint32_t)(0xffffffff & ((uint64_t)x))
256 #define	MS_64BITS(x)	(uint32_t)(0xffffffff & (((uint64_t)x)>>16>>16))
257 
258 typedef uint64_t dma_addr_t;
259 extern int ql_quiesce(dev_info_t *dip);
260 
261 /*
262  * LSO can support up to 65535 bytes of data, but can not be sent in one IOCB
263  * which only has 8 TX OALs, additional OALs must be applied separately.
264  */
265 #define	QL_LSO_MAX		65535 /* Maximum supported LSO data Length */
266 
267 enum tx_mode_t {
268 	USE_DMA,
269 	USE_COPY
270 };
271 
272 #define	QL_MAX_COPY_LENGTH	256
273 
274 #define	MAX_FRAGMENTS_IN_IOCB	7
275 
276 #ifndef VLAN_ID_MASK
277 #define	VLAN_ID_MASK		0x0fffu
278 #endif
279 #ifndef VLAN_TAGSZ
280 #define	VLAN_TAGSZ		4
281 #endif
282 
283 #ifndef	ETHERTYPE_VLAN
284 #define	ETHERTYPE_VLAN		0x8100
285 #endif
286 
287 #ifndef	MBLKL
288 #define	MBLKL(mp)	((uintptr_t)(mp)->b_wptr - (uintptr_t)(mp)->b_rptr)
289 #endif
290 /*
291  * Checksum Offload
292  */
293 #define	TCP_CKSUM_OFFSET	16
294 #define	UDP_CKSUM_OFFSET	6
295 #define	IPPROTO_IPv6OVERv4	41
296 
297 /*
298  * Driver must be in one of these states
299  */
300 enum mac_state {
301 	QL_MAC_INIT,		/* in the initialization stage */
302 	QL_MAC_ATTACHED,	/* driver attached */
303 	QL_MAC_STARTED,		/* interrupt enabled, driver is ready */
304 	QL_MAC_BRINGDOWN,	/* in the bring down process */
305 	QL_MAC_STOPPED,		/* stoped, no more interrupts */
306 	QL_MAC_DETACH,		/* to be detached */
307 	QL_MAC_SUSPENDED
308 };
309 
310 /*
311  * Soft Request Flag
312  */
313 #define	NEED_HW_RESET	BIT_0	/* need hardware reset */
314 #define	NEED_MPI_RESET	BIT_1	/* need MPI RISC reset */
315 
316 /*
317  * (Internal) return values from ioctl subroutines
318  */
319 enum ioc_reply {
320 	IOC_INVAL = -1,			/* bad, NAK with EINVAL	*/
321 	IOC_DONE,			/* OK, reply sent	*/
322 	IOC_ACK,			/* OK, just send ACK	*/
323 	IOC_REPLY,			/* OK, just send reply	*/
324 	IOC_RESTART_ACK,		/* OK, restart & ACK	*/
325 	IOC_RESTART_REPLY		/* OK, restart & reply	*/
326 };
327 
328 /*
329  * Link Speed,in Mbps
330  */
331 #define	SPEED_10		10
332 #define	SPEED_100		100
333 #define	SPEED_1000		1000
334 #define	SPEED_10G		10000
335 
336 /*
337  * Multicast List
338  */
339 typedef struct {
340 	struct ether_addr	addr;
341 	unsigned char		reserved[2];
342 } ql_multicast_addr;
343 
344 #define	MAX_MULTICAST_LIST_SIZE	128
345 
346 typedef struct {
347 	struct ether_addr	addr;		/* in canonical form	*/
348 	boolean_t		set;		/* B_TRUE => valid	*/
349 } qlge_mac_addr_t;
350 
351 #define	MAX_UNICAST_LIST_SIZE	128
352 
353 /*
354  * Device kstate structure.
355  */
356 enum {
357 	QL_KSTAT_CHIP = 0,
358 	QL_KSTAT_LINK,
359 	QL_KSTAT_REG,
360 	QL_KSTAT_COUNT
361 };
362 
363 /*
364  * Register Bit Set/Reset
365  */
366 enum {
367 	BIT_SET = 0,
368 	BIT_RESET
369 };
370 
371 /*
372  * Flash Image Search State
373  */
374 enum {	STOP_SEARCH,		/* Image address bad, no more search */
375 	CONTINUE_SEARCH,	/* Image address ok, continue search */
376 	LAST_IMAGE_FOUND	/* Found last image and FLTDS address */
377 };
378 
379 /*
380  * Loop Back Modes
381  */
382 enum {	QLGE_LOOP_NONE,
383 	QLGE_LOOP_INTERNAL_PARALLEL,
384 	QLGE_LOOP_INTERNAL_SERIAL,
385 	QLGE_LOOP_EXTERNAL_PHY
386 };
387 
388 /* for soft state routine */
389 typedef struct {
390 	offset_t	index;
391 	char		*name;
392 } ql_ksindex_t;
393 
394 struct bq_desc {
395 	struct		dma_info bd_dma;
396 	struct		bq_desc *next;
397 	struct		rx_ring *rx_ring;
398 	mblk_t		*mp;
399 	frtn_t		rx_recycle;	/* recycle function - called after mp */
400 					/* is to be freed by OS */
401 	uint16_t	index;
402 	uint16_t	free_buf;	/* Set to indicate the buffer is */
403 					/* being freed, new one should not */
404 					/* be allocated */
405 	uint32_t	upl_inuse;	/* buffer in use by upper layers */
406 };
407 
408 #define	VM_PAGE_SIZE		4096
409 
410 #define	QLGE_POLL_ALL		-1
411 
412 #define	SMALL_BUFFER_SIZE	512
413 #define	LARGE_BUFFER_SIZE	4096
414 
415 #define	MAX_TX_WAIT_COUNT	1000
416 #define	MAX_RX_WAIT_COUNT	25	/* 25 second */
417 
418 #define	MIN_BUFFERS_ARM_COUNT	16
419 #define	MIN_BUFFERS_FREE_COUNT	32	/* If free buffer count go over this */
420 					/* value, arm the chip */
421 /* if less than 16 free lrg buf nodes in the free list, then */
422 /* rx has to use copy method to send packets upstream */
423 #define	RX_COPY_MODE_THRESHOLD	(MIN_BUFFERS_ARM_COUNT/4)
424 /* if there are more than TX_STOP_THRESHOLD free tx buffers, try to send it */
425 #define	TX_STOP_THRESHOLD	16
426 #define	TX_RESUME_THRESHOLD	8
427 
428 struct tx_ring_desc {
429 	struct ob_mac_iocb_req *queue_entry;	/* tx descriptor of this */
430 	struct dma_info		dma_mem_area;	/* tx buffer */
431 	ddi_dma_handle_t	tx_dma_handle[QL_MAX_TX_DMA_HANDLES];
432 	int			tx_dma_handle_used;
433 	enum tx_mode_t		tx_type;	/* map mode or copy mode */
434 	mblk_t			*mp;		/* requested sending packet */
435 	uint32_t		index;
436 	caddr_t			copy_buffer;
437 	uint64_t		copy_buffer_dma_addr;
438 	struct dma_info		oal_dma;	/* oal is premapped */
439 	uint64_t		oal_dma_addr;	/* oal dma address premapped */
440 	uint32_t		tx_bytes;
441 	void			*oal;
442 };
443 
444 struct tx_ring {
445 	struct qlge		*qlge;
446 	struct dma_info		wqicb_dma;
447 	uint16_t		cq_id;		/* completion (rx) queue for */
448 						/* tx completions */
449 	uint8_t			wq_id;
450 	uint32_t		wq_size;
451 	uint32_t		wq_len;
452 	kmutex_t		tx_lock;
453 	struct dma_info		wq_dma;
454 	volatile uint32_t	tx_free_count;
455 	uint32_t		tx_mode;
456 	boolean_t		queue_stopped;	/* Tx no resource */
457 	uint32_t		*prod_idx_db_reg;
458 	uint16_t		prod_idx;
459 	uint32_t		*valid_db_reg;	/* PCI doorbell mem area + 4 */
460 	struct tx_ring_desc	*wq_desc;
461 				/* shadow copy of consumer idx */
462 	uint32_t		*cnsmr_idx_sh_reg;
463 				/* dma-shadow copy consumer */
464 	uint64_t		cnsmr_idx_sh_reg_dma;
465 	uint32_t		defer;	/* tx no resource */
466 	uint64_t		obytes;
467 	uint64_t		opackets;
468 	uint32_t		errxmt;
469 	uint64_t		brdcstxmt;
470 	uint64_t		multixmt;
471 	uint64_t		tx_fail_dma_bind;
472 	uint64_t		tx_no_dma_handle;
473 	uint64_t		tx_no_dma_cookie;
474 
475 	enum mac_state		mac_flags;
476 };
477 
478 struct bq_element {
479 uint32_t addr_lo;
480 uint32_t addr_hi;
481 };
482 
483 /*
484  * Type of inbound queue.
485  */
486 enum {
487 	DEFAULT_Q = 2,		/* Handles slow queue and chip/MPI events. */
488 	TX_Q = 3,		/* Handles outbound completions. */
489 	RX_Q = 4,		/* Handles inbound completions. */
490 };
491 
492 struct rx_ring {
493 	struct dma_info		cqicb_dma;
494 
495 	/* GLD required flags */
496 	uint64_t		ring_gen_num;
497 	/* statistics */
498 	uint64_t		rx_packets;
499 	uint64_t		rx_bytes;
500 	uint32_t		frame_too_long;
501 	uint32_t		frame_too_short;
502 	uint32_t		fcs_err;
503 	uint32_t		rx_packets_dropped_no_buffer;
504 	uint32_t		rx_pkt_dropped_mac_unenabled;
505 	volatile uint32_t	rx_indicate;
506 
507 	/* miscellaneous */
508 	int			type; /* DEFAULT_Q, TX_Q, RX_Q */
509 	kmutex_t		rx_lock;
510 	uint32_t		irq;
511 	struct qlge		*qlge;
512 	uint32_t		cpu;	/* Which CPU this should run on. */
513 	enum mac_state		mac_flags;
514 	/* completion queue */
515 	struct dma_info		cq_dma;	/* virtual addr and phy addr */
516 	uint32_t		cq_size;
517 	uint32_t		cq_len;
518 	uint16_t		cq_id;
519 	off_t			prod_idx_sh_reg_offset;
520 	volatile uint32_t	*prod_idx_sh_reg;	/* Shadowed prod reg */
521 	uint64_t		prod_idx_sh_reg_dma;	/* Physical address */
522 	uint32_t		*cnsmr_idx_db_reg;	/* PCI db mem area 0 */
523 	uint32_t		cnsmr_idx;		/* current sw idx */
524 	struct net_rsp_iocb	*curr_entry;	/* next entry on queue */
525 	uint32_t		*valid_db_reg;	/* PCI doorbell mem area + 4 */
526 
527 	/* large buffer queue */
528 	uint32_t 		lbq_len;		/* entry count */
529 	uint32_t		lbq_size;		/* size in bytes */
530 	uint32_t		lbq_buf_size;
531 	struct dma_info		lbq_dma;		/* lbq dma info */
532 	uint64_t		*lbq_base_indirect;
533 	uint64_t		lbq_base_indirect_dma;
534 	kmutex_t 		lbq_lock;
535 	struct bq_desc		**lbuf_in_use;
536 	volatile uint32_t	lbuf_in_use_count;
537 	struct bq_desc		**lbuf_free;
538 	volatile uint32_t	lbuf_free_count;	/* free lbuf desc cnt */
539 	uint32_t		*lbq_prod_idx_db_reg; /* PCI db mem area+0x18 */
540 	uint32_t		lbq_prod_idx;	/* current sw prod idx */
541 	uint32_t		lbq_curr_idx;	/* next entry we expect */
542 	uint32_t		lbq_free_tail;	/* free tail */
543 	uint32_t		lbq_free_head;	/* free head */
544 	uint32_t		lbq_use_tail;	/* inuse tail */
545 	uint32_t		lbq_use_head;	/* inuse head */
546 
547 	struct bq_desc		*lbq_desc;
548 
549 	/* small buffer queue */
550 	uint32_t		sbq_len;		/* entry count */
551 	uint32_t		sbq_size;	/* size in bytes of queue */
552 	uint32_t		sbq_buf_size;
553 	struct dma_info		sbq_dma; 		/* sbq dma info */
554 	uint64_t		*sbq_base_indirect;
555 	uint64_t		sbq_base_indirect_dma;
556 	kmutex_t		sbq_lock;
557 	struct bq_desc		**sbuf_in_use;
558 	volatile uint32_t	sbuf_in_use_count;
559 	struct bq_desc		**sbuf_free;
560 	volatile uint32_t	sbuf_free_count; /* free buffer desc cnt */
561 	uint32_t		*sbq_prod_idx_db_reg; /* PCI db mem area+0x1c */
562 	uint32_t		sbq_prod_idx;	/* current sw prod idx */
563 	uint32_t		sbq_curr_idx;	/* next entry we expect */
564 	uint32_t		sbq_free_tail;	/* free tail */
565 	uint32_t		sbq_free_head;	/* free head */
566 	uint32_t		sbq_use_tail;	/* inuse tail */
567 	uint32_t		sbq_use_head;	/* inuse head */
568 	struct bq_desc		*sbq_desc;
569 	/* for test purpose */
570 	uint32_t		rx_failed_sbq_allocs;
571 	uint32_t		rx_failed_lbq_allocs;
572 	uint32_t		sbuf_copy_count;
573 	uint32_t		lbuf_copy_count;
574 
575 #ifdef QLGE_PERFORMANCE
576 	uint32_t		hist[8];
577 #endif
578 };
579 
580 struct intr_ctx {
581 	struct	qlge		*qlge;
582 	uint32_t		intr;
583 	uint32_t		hooked;
584 	uint32_t		intr_en_mask;
585 	uint32_t		intr_dis_mask;
586 	uint32_t		intr_read_mask;
587 				/*
588 				 * It's incremented for
589 				 * each irq handler that is scheduled.
590 				 * When each handler finishes it
591 				 * decrements irq_cnt and enables
592 				 * interrupts if it's zero.
593 				 */
594 	uint32_t		irq_cnt;
595 	uint_t			(*handler)(caddr_t, caddr_t);
596 };
597 
598 struct tx_buf_desc {
599 	uint64_t		addr;
600 	uint32_t		len;
601 #define	TX_DESC_LEN_MASK	0x000fffff
602 #define	TX_DESC_C		0x40000000
603 #define	TX_DESC_E		0x80000000
604 };
605 
606 typedef struct qlge {
607 	/*
608 	 * Solaris adapter configuration data
609 	 */
610 	dev_info_t		*dip;
611 	int			instance;
612 	ddi_acc_handle_t	dev_handle;
613 	caddr_t			iobase;
614 	ddi_acc_handle_t	dev_doorbell_reg_handle;
615 	caddr_t			doorbell_reg_iobase;
616 	pci_cfg_t		pci_cfg;
617 	ddi_acc_handle_t	pci_handle;
618 	uint32_t		page_size;
619 	uint32_t		sequence;
620 	struct intr_ctx		intr_ctx[MAX_RX_RINGS];
621 	struct dma_info		ricb_dma;
622 	/* fault management capabilities */
623 	int			fm_capabilities;
624 	boolean_t		fm_enable;
625 	enum mac_state		mac_flags;
626 
627 	volatile uint32_t	cfg_flags;
628 
629 #define	CFG_JUMBLE_PACKET		BIT_1
630 #define	CFG_RX_COPY_MODE		BIT_2
631 #define	CFG_SUPPORT_MULTICAST		BIT_3
632 #define	CFG_HW_UNABLE_PSEUDO_HDR_CKSUM	BIT_4
633 #define	CFG_CKSUM_HEADER_IPv4		BIT_5
634 #define	CFG_CKSUM_PARTIAL		BIT_6
635 #define	CFG_CKSUM_FULL_IPv4		BIT_7
636 #define	CFG_CKSUM_FULL_IPv6		BIT_8
637 #define	CFG_LSO				BIT_9
638 #define	CFG_SUPPORT_SCATTER_GATHER	BIT_10
639 #define	CFG_ENABLE_SPLIT_HEADER		BIT_11
640 #define	CFG_ENABLE_EXTENDED_LOGGING	BIT_15
641 	uint32_t			chksum_cap;
642 	volatile uint32_t		flags;
643 #define	CFG_CHIP_8100			BIT_16
644 
645 #define	CFG_IST(qlge, cfgflags)		(qlge->cfg_flags & cfgflags)
646 
647 	/* For Shadow Registers, used by adapter to write to host memory */
648 	struct dma_info		host_copy_shadow_dma_attr;
649 	/*
650 	 * Extra 2x8 bytes memory saving large/small buf queue base address
651 	 * for each CQICB and read by chip, new request since 8100
652 	 */
653 	struct dma_info		buf_q_ptr_base_addr_dma_attr;
654 	/*
655 	 * Debugging
656 	 */
657 	uint32_t		ql_dbgprnt;
658 	/*
659 	 * GLD
660 	 */
661 	mac_handle_t		mh;
662 	mac_resource_handle_t	handle;
663 	ql_stats_t		stats;
664 	kstat_t			*ql_kstats[QL_KSTAT_COUNT];
665 	/*
666 	 * mutex
667 	 */
668 	kmutex_t		gen_mutex;	/* general adapter mutex */
669 	kmutex_t		hw_mutex;	/* common hw(nvram)access */
670 
671 	/*
672 	 * Generic timer
673 	 */
674 	timeout_id_t		ql_timer_timeout_id;
675 	clock_t			ql_timer_ticks;
676 
677 	/*
678 	 * Interrupt
679 	 */
680 	int			intr_type;
681 	/* for legacy interrupt */
682 	ddi_iblock_cookie_t	iblock_cookie;
683 	/* for MSI and Fixed interrupts */
684 	ddi_intr_handle_t	*htable;	/* For array of interrupts */
685 	int			intr_cnt; /* # of intrs actually allocated */
686 	uint_t			intr_pri;	/* Interrupt priority */
687 	int			intr_cap;	/* Interrupt capabilities */
688 	size_t			intr_size;	/* size of the allocated  */
689 						/* interrupt handlers */
690 	/* Power management context. */
691 	uint8_t			power_level;
692 #define	LOW_POWER_LEVEL		(BIT_1 | BIT_0)
693 #define	MAX_POWER_LEVEL		0
694 
695 	/*
696 	 * General NIC
697 	 */
698 	uint32_t		xgmac_sem_mask;
699 	uint32_t		xgmac_sem_bits;
700 	uint32_t		func_number;
701 	uint32_t		fn0_net;	/* network function 0 port */
702 	uint32_t		fn1_net;	/* network function 1 port */
703 
704 	uint32_t		mtu;
705 	uint32_t		max_frame_size;
706 	uint32_t		port_link_state;
707 	uint32_t		speed;
708 	uint16_t		link_type;
709 	uint32_t		duplex;
710 	uint32_t		pause;	/* flow-control mode */
711 	uint32_t		loop_back_mode;
712 	uint32_t		lso_enable;
713 	uint32_t		dcbx_enable;	/* dcbx mode */
714 	/*
715 	 * PCI status
716 	 */
717 	uint16_t		vendor_id;
718 	uint16_t		device_id;
719 
720 	/*
721 	 * Multicast list
722 	 */
723 	uint32_t		multicast_list_count;
724 	ql_multicast_addr	multicast_list[MAX_MULTICAST_LIST_SIZE];
725 	boolean_t		multicast_promisc;
726 	/*
727 	 * MAC address information
728 	 */
729 	struct ether_addr	dev_addr; /* ethernet address read from nvram */
730 	qlge_mac_addr_t		unicst_addr[MAX_UNICAST_LIST_SIZE];
731 	uint32_t		unicst_total; /* total unicst addresses */
732 	uint32_t		unicst_avail;
733 	/*
734 	 * Soft Interrupt handlers
735 	 */
736 	/* soft interrupt handle for MPI interrupt */
737 	ddi_softint_handle_t	mpi_event_intr_hdl;
738 	/* soft interrupt handle for asic reset */
739 	ddi_softint_handle_t	asic_reset_intr_hdl;
740 	/* soft interrupt handle for mpi reset */
741 	ddi_softint_handle_t	mpi_reset_intr_hdl;
742 	/*
743 	 * IOCTL
744 	 */
745 	/* new ioctl admin flags to work around the 1024 max data copy in&out */
746 	caddr_t			ioctl_buf_ptr;
747 	uint32_t		ioctl_buf_lenth;
748 	uint16_t		expected_trans_times;
749 	uint32_t		ioctl_total_length;
750 	uint32_t		ioctl_transferred_bytes;
751 	ql_mpi_coredump_t	ql_mpi_coredump;
752 	/*
753 	 * Mailbox lock and flags
754 	 */
755 	boolean_t		fw_init_complete;
756 	kmutex_t		mbx_mutex;
757 	boolean_t		mbx_wait_completion;
758 	kcondvar_t		cv_mbx_intr;
759 	mbx_data_t 		received_mbx_cmds;
760 	uint_t			max_read_mbx;
761 	firmware_version_info_t		fw_version_info;
762 	phy_firmware_version_info_t	phy_version_info;
763 	port_cfg_info_t			port_cfg_info;
764 	struct dma_info			ioctl_buf_dma_attr;
765 
766 	/*
767 	 * Flash
768 	 */
769 	uint32_t		flash_fltds_addr;
770 	uint32_t		flash_flt_fdt_index;
771 	uint32_t		flash_fdt_addr;
772 	uint32_t		flash_fdt_size;
773 	uint32_t		flash_flt_nic_config_table_index;
774 	uint32_t		flash_nic_config_table_addr;
775 	uint32_t		flash_nic_config_table_size;
776 	uint32_t		flash_vpd_addr;
777 	ql_flash_info_t		flash_info;
778 	ql_fltds_t		fltds;
779 	ql_flt_t		flt;
780 	uint16_t		flash_len;	/* size of Flash memory */
781 	ql_nic_config_t		nic_config;
782 	flash_desc_t		fdesc;
783 	/*
784 	 * TX / RX
785 	 */
786 	clock_t			last_tx_time;
787 	boolean_t		rx_copy;
788 	uint16_t		rx_coalesce_usecs;
789 	uint16_t		rx_max_coalesced_frames;
790 	uint16_t		tx_coalesce_usecs;
791 	uint16_t		tx_max_coalesced_frames;
792 	uint32_t		payload_copy_thresh;
793 
794 	uint32_t		xg_sem_mask;
795 
796 	uint32_t		ip_hdr_offset;
797 	uint32_t		selected_tx_ring;
798 
799 	struct rx_ring		rx_ring[MAX_RX_RINGS];
800 	struct tx_ring		tx_ring[MAX_TX_RINGS];
801 	uint32_t		rx_polls[MAX_RX_RINGS];
802 	uint32_t		rx_interrupts[MAX_RX_RINGS];
803 
804 	int 			tx_ring_size;
805 	int 			rx_ring_size;
806 	uint32_t		rx_copy_threshold;
807 	uint32_t		rx_ring_count;
808 	uint32_t		rss_ring_count;
809 	uint32_t		tx_ring_first_cq_id;
810 	uint32_t		tx_ring_count;
811 	uint32_t		isr_stride;
812 #ifdef QLGE_TRACK_BUFFER_USAGE
813 	/* Count no of times the buffers fell below 32 */
814 	uint32_t		rx_sb_low_count[MAX_RX_RINGS];
815 	uint32_t		rx_lb_low_count[MAX_RX_RINGS];
816 	uint32_t		cq_low_count[MAX_RX_RINGS];
817 #endif
818 } qlge_t;
819 
820 
821 /*
822  * Reconfiguring the network devices requires the net_config privilege
823  * in Solaris 10+.
824  */
825 extern int secpolicy_net_config(const cred_t *, boolean_t);
826 
827 /*
828  * Global Function Prototypes in qlge_dbg.c source file.
829  */
830 extern int ql_fw_dump(qlge_t *);
831 extern uint8_t ql_get8(qlge_t *, uint32_t);
832 extern uint16_t ql_get16(qlge_t *, uint32_t);
833 extern uint32_t ql_get32(qlge_t *, uint32_t);
834 extern void ql_put8(qlge_t *, uint32_t, uint8_t);
835 extern void ql_put16(qlge_t *, uint32_t, uint16_t);
836 extern void ql_put32(qlge_t *, uint32_t, uint32_t);
837 extern uint32_t ql_read_reg(qlge_t *, uint32_t);
838 extern void ql_write_reg(qlge_t *, uint32_t, uint32_t);
839 extern void ql_dump_all_contrl_regs(qlge_t *);
840 extern int ql_wait_reg_bit(qlge_t *, uint32_t, uint32_t, int, uint32_t);
841 extern void ql_dump_pci_config(qlge_t *);
842 extern void ql_dump_host_pci_regs(qlge_t *);
843 extern void ql_dump_req_pkt(qlge_t *, struct ob_mac_iocb_req *, void *, int);
844 extern void ql_dump_cqicb(qlge_t *, struct cqicb_t *);
845 extern void ql_dump_wqicb(qlge_t *, struct wqicb_t *);
846 extern void ql_gld3_init(qlge_t *, mac_register_t *);
847 enum ioc_reply ql_chip_ioctl(qlge_t *, queue_t *, mblk_t *);
848 enum ioc_reply ql_loop_ioctl(qlge_t *, queue_t *, mblk_t *, struct iocblk *);
849 extern int ql_8xxx_binary_core_dump(qlge_t *, ql_mpi_coredump_t *);
850 /*
851  * Global Data in qlge.c source file.
852  */
853 extern void qlge_delay(clock_t usecs);
854 extern int ql_sem_spinlock(qlge_t *, uint32_t);
855 extern void ql_sem_unlock(qlge_t *, uint32_t);
856 extern int ql_sem_lock(qlge_t *, uint32_t, uint32_t);
857 extern int ql_init_misc_registers(qlge_t *);
858 extern int ql_init_mem_resources(qlge_t *);
859 extern int ql_do_start(qlge_t *);
860 extern int ql_do_stop(qlge_t *);
861 extern int ql_add_to_multicast_list(qlge_t *, uint8_t *ep);
862 extern int ql_remove_from_multicast_list(qlge_t *, uint8_t *);
863 extern void ql_set_promiscuous(qlge_t *, int);
864 extern void ql_get_hw_stats(qlge_t *);
865 extern int ql_send_common(struct tx_ring *, mblk_t *);
866 extern void ql_wake_asic_reset_soft_intr(qlge_t *);
867 extern void ql_write_doorbell_reg(qlge_t *, uint32_t *, uint32_t);
868 extern uint32_t ql_read_doorbell_reg(qlge_t *, uint32_t *);
869 extern int ql_set_mac_addr_reg(qlge_t *, uint8_t *, uint32_t, uint16_t);
870 extern int ql_read_xgmac_reg(qlge_t *, uint32_t, uint32_t *);
871 extern void ql_enable_completion_interrupt(qlge_t *, uint32_t);
872 extern mblk_t *ql_ring_rx_poll(void *, int);
873 extern void ql_disable_completion_interrupt(qlge_t *qlge, uint32_t intr);
874 extern mblk_t *ql_ring_tx(void *arg, mblk_t *mp);
875 extern uint8_t ql_tx_hashing(qlge_t *qlge, caddr_t bp);
876 extern void ql_atomic_set_32(volatile uint32_t *target, uint32_t newval);
877 extern uint32_t ql_atomic_read_32(volatile uint32_t *target);
878 extern void ql_restart_timer(qlge_t *qlge);
879 /*
880  * Global Function Prototypes in qlge_flash.c source file.
881  */
882 extern int ql_sem_flash_lock(qlge_t *);
883 extern void ql_sem_flash_unlock(qlge_t *);
884 extern int qlge_load_flash(qlge_t *, uint8_t *, uint32_t, uint32_t);
885 extern int qlge_dump_fcode(qlge_t *, uint8_t *, uint32_t, uint32_t);
886 extern int ql_flash_vpd(qlge_t *qlge, uint8_t *buf);
887 extern int ql_get_flash_params(qlge_t *qlge);
888 /*
889  * Global Function Prototypes in qlge_mpi.c source file.
890  */
891 extern void ql_do_mpi_intr(qlge_t *qlge);
892 extern int ql_reset_mpi_risc(qlge_t *);
893 extern int ql_get_fw_state(qlge_t *, uint32_t *);
894 extern int qlge_get_link_status(qlge_t *, struct qlnic_link_status_info *);
895 extern int ql_mbx_test(qlge_t *qlge);
896 extern int ql_mbx_test2(qlge_t *qlge);
897 extern int ql_get_port_cfg(qlge_t *qlge);
898 extern int ql_set_mpi_port_config(qlge_t *qlge, port_cfg_info_t new_cfg);
899 extern int ql_set_loop_back_mode(qlge_t *qlge);
900 extern int ql_set_pause_mode(qlge_t *qlge);
901 extern int ql_get_LED_config(qlge_t *);
902 extern int ql_dump_sfp(qlge_t *, void *bp, int mode);
903 extern int ql_set_IDC_Req(qlge_t *, uint8_t dest_functions, uint8_t timeout);
904 extern void ql_write_flash_test(qlge_t *qlge, uint32_t testAddr);
905 extern void ql_write_flash_test2(qlge_t *qlge, uint32_t testAddr);
906 extern int ql_get_firmware_version(qlge_t *,
907     struct qlnic_mpi_version_info *);
908 extern int ql_read_processor_data(qlge_t *, uint32_t, uint32_t *);
909 extern int ql_write_processor_data(qlge_t *, uint32_t, uint32_t);
910 extern int ql_read_risc_ram(qlge_t *, uint32_t, uint64_t, uint32_t);
911 extern int ql_trigger_system_error_event(qlge_t *qlge);
912 
913 extern void ql_core_dump(qlge_t *);
914 extern void ql_dump_crash_record(qlge_t *);
915 extern void ql_dump_buf(char *, uint8_t *, uint8_t, uint32_t);
916 extern void ql_printf(const char *, ...);
917 
918 /*
919  * Global Function Prototypes in qlge_gld.c source file.
920  */
921 extern int ql_unicst_set(qlge_t *qlge, const uint8_t *macaddr, int slot);
922 
923 /*
924  * Global Function Prototypes in qlge_fm.c source file.
925  */
926 extern void ql_fm_ereport(qlge_t *qlge, char *detail);
927 extern int ql_fm_check_acc_handle(ddi_acc_handle_t handle);
928 extern int ql_fm_check_dma_handle(ddi_dma_handle_t handle);
929 
930 
931 #ifdef __cplusplus
932 }
933 #endif
934 
935 #endif /* _QLGE_H */
936