1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/* Copyright 2010 QLogic Corporation */
23
24/*
25 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
26 */
27
28#ifndef	_QL_MBX_H
29#define	_QL_MBX_H
30
31/*
32 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
33 *
34 * ***********************************************************************
35 * *									**
36 * *				NOTICE					**
37 * *		COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION		**
38 * *			ALL RIGHTS RESERVED				**
39 * *									**
40 * ***********************************************************************
41 *
42 */
43
44#ifdef	__cplusplus
45extern "C" {
46#endif
47
48/*
49 * ISP mailbox Self-Test status codes
50 */
51#define	MBS_FRM_ALIVE	0	/* Firmware Alive. */
52#define	MBS_CHKSUM_ERR	1	/* Checksum Error. */
53#define	MBS_BUSY	4	/* Busy. */
54
55/*
56 * ISP mailbox command complete status codes
57 */
58#define	MBS_COMMAND_COMPLETE		0x4000
59#define	MBS_INVALID_COMMAND		0x4001
60#define	MBS_HOST_INTERFACE_ERROR	0x4002
61#define	MBS_TEST_FAILED			0x4003
62#define	MBS_POST_ERROR			0x4004
63#define	MBS_COMMAND_ERROR		0x4005
64#define	MBS_COMMAND_PARAMETER_ERROR	0x4006
65#define	MBS_PORT_ID_USED		0x4007
66#define	MBS_LOOP_ID_USED		0x4008
67#define	MBS_ALL_IDS_IN_USE		0x4009
68#define	MBS_NOT_LOGGED_IN		0x400A
69#define	MBS_LOOP_DOWN			0x400B
70#define	MBS_LOOP_BACK_ERROR		0x400C
71#define	MBS_CHECKSUM_ERROR		0x4010
72
73/*
74 * Sub-error Codes for Mailbox Command Completion Status Code 4005h
75 */
76#define	MBSS_NO_LINK			0x0001
77#define	MBSS_IOCB_ALLOC_ERR		0x0002
78#define	MBSS_ECB_ALLOC_ERR		0x0003
79#define	MBSS_CMD_FAILURE		0x0004
80#define	MBSS_NO_FABRIC			0x0005
81#define	MBSS_FIRMWARE_NOT_RDY		0x0007
82#define	MBSS_INITIATOR_DISABLED		0x0008
83#define	MBSS_NOT_LOGGED_IN		0x0009
84#define	MBSS_PARTIAL_DATA_XFER		0x000A
85#define	MBSS_TOPOLOGY_ERR		0x0016
86#define	MBSS_CHIP_RESET_NEEDED		0x0017
87#define	MBSS_MULTIPLE_OPEN_EXCH		0x0018
88#define	MBSS_IOCB_COUNT_ERR		0x0019
89#define	MBSS_CMD_AFTER_FW_INIT_ERR	0x001A
90#define	MBSS_NO_VIRTUAL_PORT_ID		0x001B
91#define	MBSS_INVALID_FCF_INDEX		0x0022
92#define	MBSS_MPI_PROCESSOR_ERR		0x0023
93#define	MBSS_SEMAPHORE_ERR		0x0024
94#define	MBSS_RANGE_ERR			0x0025
95#define	MBSS_TRANSFER_SIZE_TO_LARGE	0x0026
96#define	MBSS_CHECKSUM_ERR		0x0027
97#define	MBSS_CONFIGURATION_ERR		0x0028
98
99/*
100 * ISP mailbox asynchronous event status codes
101 */
102#define	MBA_ASYNC_EVENT		0x8000  /* Asynchronous event. */
103#define	MBA_RESET		0x8001  /* Reset Detected. */
104#define	MBA_SYSTEM_ERR		0x8002  /* System Error. */
105#define	MBA_REQ_TRANSFER_ERR	0x8003  /* Request Transfer Error. */
106#define	MBA_RSP_TRANSFER_ERR	0x8004  /* Response Transfer Error. */
107#define	MBA_WAKEUP_THRES	0x8005  /* Request Queue Wake-up. */
108#define	MBA_MENLO_ALERT		0x800f  /* Menlo Alert Notification. */
109#define	MBA_LIP_OCCURRED	0x8010  /* Loop Initialization Procedure */
110					/* occurred. */
111#define	MBA_LOOP_UP		0x8011  /* FC Loop UP. */
112#define	MBA_LOOP_DOWN		0x8012  /* FC Loop Down. */
113#define	MBA_LIP_RESET		0x8013	/* LIP reset occurred. */
114#define	MBA_PORT_UPDATE		0x8014  /* Port Database update. */
115#define	MBA_RSCN_UPDATE		0x8015  /* State Change Registration. */
116#define	MBA_LIP_F8		0x8016	/* Received a LIP F8. */
117#define	MBA_LIP_ERROR		0x8017	/* Loop initialization errors. */
118#define	MBA_SECURITY_UPDATE	0x801B	/* FC-SP security update. */
119#define	MBA_SCSI_COMPLETION	0x8020  /* SCSI Command Complete. */
120#define	MBA_CTIO_COMPLETION	0x8021  /* CTIO Complete. */
121#define	MBA_IP_COMPLETION	0x8022  /* IP Transmit Command Complete. */
122#define	MBA_IP_RECEIVE		0x8023  /* IP Received. */
123#define	MBA_IP_BROADCAST	0x8024  /* IP Broadcast Received. */
124#define	MBA_IP_LOW_WATER_MARK   0x8025  /* IP Low Water Mark reached. */
125#define	MBA_IP_RCV_BUFFER_EMPTY 0x8026  /* IP receive buffer queue empty. */
126#define	MBA_IP_HDR_DATA_SPLIT   0x8027  /* IP header/data splitting feature */
127					/* used. */
128#define	MBA_ERROR_LOGGING_DISABLED	0x8029  /* Error Logging Disabled. */
129#define	MBA_POINT_TO_POINT	0x8030  /* Point to point mode. */
130#define	MBA_DCBX_COMPLETED	0x8030  /* DCBX completed. */
131#define	MBA_CMPLT_1_16BIT	0x8031	/* Completion 1 16bit IOSB. */
132#define	MBA_FCF_CONFIG_ERROR	0x8031	/* FCF configuration error. */
133#define	MBA_CMPLT_2_16BIT	0x8032	/* Completion 2 16bit IOSB. */
134#define	MBA_DCBX_PARAM_CHANGED	0x8032	/* DCBX parameters changed. */
135#define	MBA_CMPLT_3_16BIT	0x8033	/* Completion 3 16bit IOSB. */
136#define	MBA_CMPLT_4_16BIT	0x8034	/* Completion 4 16bit IOSB. */
137#define	MBA_CMPLT_5_16BIT	0x8035	/* Completion 5 16bit IOSB. */
138#define	MBA_CHG_IN_CONNECTION   0x8036  /* Change in connection mode. */
139#define	MBA_ZIO_UPDATE		0x8040  /* ZIO response queue update. */
140#define	MBA_CMPLT_2_32BIT	0x8042	/* Completion 2 32bit IOSB. */
141#define	MBA_PORT_BYPASS_CHANGED	0x8043	/* Crystal+ port#0 bypass transition */
142#define	MBA_RECEIVE_ERROR	0x8048	/* Receive Error */
143#define	MBA_LS_RJT_SENT		0x8049	/* LS_RJT response sent */
144#define	MBA_FW_RESTART_COMP	0x8060	/* Firmware Restart Complete. */
145#define	MBA_IDC_COMPLETE	0x8100	/* Inter-driver communication */
146					/* complete. */
147#define	MBA_IDC_NOTIFICATION	0x8101	/* Inter-driver communication */
148					/* notification. */
149#define	MBA_IDC_TIME_EXTENDED	0x8102	/* Inter-driver communication */
150					/* time extended. */
151
152/* Driver defined. */
153#define	MBA_CMPLT_1_32BIT	0x9000	/* Completion 1 32bit IOSB. */
154/*
155 * Mailbox 23 event codes
156 */
157#define	MBX23_MBX_OR_ASYNC_EVENT	0x0
158#define	MBX23_RESPONSE_QUEUE_UPDATE	0x1
159#define	MBX23_SCSI_COMPLETION		0x2
160
161/*
162 * System Error event (0x8002) defines
163 */
164#define	SE_MPI_RISC	BIT_2
165#define	SE_NIC_1	BIT_1
166#define	SE_NIC_2	BIT_0
167
168/*
169 * Menlo alert event defines
170 */
171#define	MLA_PANIC_RECOVERY		0x1
172#define	MLA_LOGIN_OPERATIONAL_FW	0x2
173#define	MLA_LOGIN_DIAGNOSTIC_FW		0x3
174#define	MLA_LOGIN_GOLDEN_FW		0x4
175#define	MLA_REJECT_RESPONSE		0x5
176
177/*
178 * ISP mailbox commands
179 */
180#define	MBC_LOAD_RAM			1	/* Load RAM. */
181#define	MBC_EXECUTE_FIRMWARE		2	/* Execute firmware. */
182#define	MBC_DUMP_RAM			3	/* Dump RAM. */
183#define	MBC_WRITE_RAM_WORD		4	/* Write RAM word. */
184#define	MBC_READ_RAM_WORD		5	/* Read RAM word. */
185#define	MBC_MAILBOX_REGISTER_TEST	6	/* Wrap incoming mailboxes */
186#define	MBC_VERIFY_CHECKSUM		7	/* Verify checksum. */
187#define	MBC_ABOUT_FIRMWARE		8	/* About Firmware. */
188#define	MBC_DUMP_RISC_RAM		0xa	/* Dump RISC RAM command. */
189#define	MBC_LOAD_RAM_EXTENDED		0xb	/* Load RAM extended. */
190#define	MBC_DUMP_RAM_EXTENDED		0xc	/* Dump RAM extended. */
191#define	MBC_WRITE_RAM_EXTENDED		0xd	/* Write RAM word. */
192#define	MBC_READ_RAM_EXTENDED		0xf	/* Read RAM extended. */
193#define	MBC_SERDES_TRANSMIT_PARAMETERS	0x10	/* Serdes Xmit Parameters */
194#define	MBC_TOGGLE_INTERRUPT		0x10	/* 82XX enable/disable intr */
195#define	MBC_2300_EXECUTE_IOCB		0x12	/* ISP2300 Execute IOCB cmd */
196#define	MBC_GET_IO_STATUS		0x12	/* ISP2422 Get I/O Status */
197#define	MBC_STOP_FIRMWARE		0x14	/* Stop firmware */
198#define	MBC_ABORT_COMMAND_IOCB		0x15	/* Abort IOCB command. */
199#define	MBC_ABORT_DEVICE		0x16	/* Abort device (ID/LUN). */
200#define	MBC_ABORT_TARGET		0x17	/* Abort target (ID). */
201#define	MBC_RESET			0x18	/* Target reset. */
202#define	MBC_XMIT_PARM			0x19	/* Change default xmit parms */
203#define	MBC_PORT_PARAM			0x1a	/* Get/set port speed parms */
204#define	MBC_GET_ID			0x20	/* Get loop id of ISP2200. */
205#define	MBC_GET_TIMEOUT_PARAMETERS	0x22	/* Get Timeout Parameters. */
206#define	MBC_TRACE_CONTROL		0x27	/* Trace control. */
207#define	MBC_GET_FIRMWARE_OPTIONS	0x28	/* Get firmware options */
208#define	MBC_READ_SFP			0x31	/* Read SFP. */
209#define	MBC_SET_FIRMWARE_OPTIONS	0x38	/* set firmware options */
210#define	MBC_RESET_MENLO			0x3a	/* Reset Menlo. */
211#define	MBC_RESTART_MPI			0x3d	/* Restart MPI. */
212#define	MBC_FLASH_ACCESS		0x3e	/* Flash Access Control */
213#define	MBC_LOOP_PORT_BYPASS		0x40	/* Loop Port Bypass. */
214#define	MBC_LOOP_PORT_ENABLE		0x41	/* Loop Port Enable. */
215#define	MBC_GET_RESOURCE_COUNTS		0x42	/* Get Resource Counts. */
216#define	MBC_NON_PARTICIPATE		0x43	/* Non-Participating Mode. */
217#define	MBC_ECHO			0x44	/* ELS ECHO */
218#define	MBC_DIAGNOSTIC_LOOP_BACK	0x45	/* Diagnostic loop back. */
219#define	MBC_ONLINE_SELF_TEST		0x46	/* Online self-test. */
220#define	MBC_ENHANCED_GET_PORT_DATABASE	0x47	/* Get Port Database + login */
221#define	MBC_INITIALIZE_MULTI_ID_FW	0x48	/* Initialize multi-id fw */
222#define	MBC_GET_FCF_LIST		0x50	/* Get FCF List */
223#define	MBC_GET_DCBX_PARAMS		0x51	/* Get DCBX parameters */
224#define	MBC_RESET_LINK_STATUS		0x52	/* Reset Link Error Status */
225#define	MBC_EXECUTE_IOCB		0x54	/* 64 Bit Execute IOCB cmd. */
226#define	MBC_SEND_RNID_ELS		0x57	/* Send RNID ELS request */
227#define	MBC_SET_PARAMETERS		0x59	/* Set RNID parameters */
228#define	MBC_GET_PARAMETERS		0x5a	/* Get RNID parameters */
229#define	MBC_DATA_RATE			0x5d	/* Data Rate */
230#define	MBC_INITIALIZE_FIRMWARE		0x60	/* Initialize firmware */
231#define	MBC_INITIATE_LIP		0x62	/* Initiate LIP */
232#define	MBC_GET_FC_AL_POSITION_MAP	0x63	/* Get FC_AL Position Map. */
233#define	MBC_GET_PORT_DATABASE		0x64	/* Get Port Database. */
234#define	MBC_CLEAR_ACA			0x65	/* Clear ACA. */
235#define	MBC_TARGET_RESET		0x66	/* Target Reset. */
236#define	MBC_CLEAR_TASK_SET		0x67	/* Clear Task Set. */
237#define	MBC_ABORT_TASK_SET		0x68	/* Abort Task Set. */
238#define	MBC_GET_FIRMWARE_STATE		0x69	/* Get firmware state. */
239#define	MBC_GET_PORT_NAME		0x6a	/* Get port name. */
240#define	MBC_GET_LINK_STATUS		0x6b	/* Get Link Status. */
241#define	MBC_LIP_RESET			0x6c	/* LIP reset. */
242#define	MBC_GET_STATUS_COUNTS		0x6d	/* Get Link Statistics and */
243						/* Private Data Counts */
244#define	MBC_SEND_SNS_COMMAND		0x6e	/* Send Simple Name Server */
245#define	MBC_LOGIN_FABRIC_PORT		0x6f	/* Login fabric port. */
246#define	MBC_SEND_CHANGE_REQUEST		0x70	/* Send Change Request. */
247#define	MBC_LOGOUT_FABRIC_PORT		0x71	/* Logout fabric port. */
248#define	MBC_LIP_FULL_LOGIN		0x72	/* Full login LIP. */
249#define	MBC_LOGIN_LOOP_PORT		0x74	/* Login Loop Port. */
250#define	MBC_PORT_NODE_NAME_LIST		0x75	/* Get port/node name list */
251#define	MBC_INITIALIZE_IP		0x77	/* Initialize IP */
252#define	MBC_SEND_FARP_REQ_COMMAND	0x78	/* FARP request. */
253#define	MBC_UNLOAD_IP			0x79	/* Unload IP */
254#define	MBC_GET_XGMAC_STATS		0x7a	/* Get XGMAC Statistics. */
255#define	MBC_GET_ID_LIST			0x7c	/* Get port ID list. */
256#define	MBC_SEND_LFA_COMMAND		0x7d	/* Send Loop Fabric Address */
257#define	MBC_LUN_RESET			0x7e	/* Send Task mgmt LUN reset */
258#define	MBC_IDC_REQUEST			0x100	/* IDC request */
259#define	MBC_IDC_ACK			0x101	/* IDC acknowledge */
260#define	MBC_IDC_TIME_EXTEND		0x102	/* IDC extend time */
261#define	MBC_PORT_RESET			0x120	/* Port Reset */
262#define	MBC_SET_PORT_CONFIG		0x122	/* Set port configuration */
263#define	MBC_GET_PORT_CONFIG		0x123	/* Get port configuration */
264
265/*
266 * Mbc 0x100 (IDC request)
267 */
268/* Timeout Value */
269#define	IDC_TIMEOUT_POS		8
270#define	IDC_TIMEOUT_MASK	(BIT_11 | BIT_10 | BIT_9 | BIT_8)
271
272/* Function Destination Selector */
273#define	IDC_FUNC_DST_MASK	(BIT_5 | BIT_4)
274#define	IDC_FUNC_DST_MBX3	0
275#define	IDC_FUNC_DST_SP		0x10
276
277/* Function Source */
278#define	IDC_FUNC_SRC_MASK	(BIT_3 | BIT_2 | BIT_1 | BIT_0)
279
280/* Information opcode */
281#define	IDC_OPC_DRV_START		0x100
282#define	IDC_OPC_FLASH_ACC		0x101
283#define	IDC_OPC_RESTART_MPI		0x102
284#define	IDC_OPC_PORT_RESET_MBC		0x120
285#define	IDC_OPC_SET_PORT_CONFIG_MBC	0x122
286
287/* Function Destination Mask */
288#define	IDC_FUNC_3		BIT_3
289#define	IDC_FUNC_2		BIT_2
290#define	IDC_FUNC_1		BIT_1
291#define	IDC_FUNC_0		BIT_0
292#define	IDC_FC_FUNC		(BIT_3 | BIT_2)
293#define	IDC_NIC_FUNC		(BIT_1 | BIT_0)
294#define	IDC_ALL_FUNC		(IDC_FC_FUNC | IDC_NIC_FUNC)
295
296/* Requestor Id Function Type */
297#define	IDC_RIT_MASK		(BIT_6 | BIT_5 | BIT_4)
298#define	IDC_RIT_NIC		0
299#define	IDC_RIT_FC		0x10
300
301/* Requestor Id Originator */
302#define	IDC_RIO_MASK		(BIT_3 | BIT_2 | BIT_1 | BIT_0)
303#define	IDC_RIO_DRV		0
304#define	IDC_RIO_FW		1
305#define	IDC_RIO_MPI		2
306#define	IDC_RIO_DRV_APP		3
307#define	IDC_RIO_QL_APP		4
308#define	IDC_RIO_QL_MFG		5
309#define	IDC_RIO_OTH_APP		6
310
311/* Region Code */
312#define	IDC_RC_POS		8
313#define	IDC_RC_MASK		0xFF00
314
315/* Region Size in 64k blocks */
316#define	IDC_RS_POS		0
317#define	IDC_RS_MASK		0xFF
318
319/* Message Source */
320#define	IDC_MSG_QLGC		BIT_15
321
322/* Message Subcode */
323#define	IDC_MS_MASK		(BIT_7 | BIT_6 | BIT_5 | BIT_4)
324#define	IDC_MS_NONE		0x00
325#define	IDC_MS_READ		0x10
326#define	IDC_MS_WRITE		0x20
327#define	IDC_MS_ERASE		0x30
328
329/* Marker */
330#define	IDC_MM_MASK		(BIT_3 | BIT_2 | BIT_1 | BIT_0)
331#define	IDC_MM_NONE		0x0
332#define	IDC_MM_BEG		0x1
333#define	IDC_MM_END		0x2
334#define	IDC_MM_WIP		0x3
335#define	IDC_MM_ABORT		0x4
336
337/*
338 * Mbc 0x3e (Flash Access Control)
339 */
340#define	FAC_FORCE_SEMA_LOCK	BIT_15
341#define	FAC_APPL_ID		BIT_14
342#define	FAC_WRT_PROTECT		0
343#define	FAC_WRT_ENABLE		1
344#define	FAC_ERASE_SECTOR	2
345#define	FAC_SEMA_LOCK		3
346#define	FAC_SEMA_UNLOCK		4
347#define	FAC_GET_SECTOR_SIZE	5
348#define	FAC_ADDR_MASK		0x3fff
349
350/*
351 * MBC_DIAGNOSTIC_LOOP_BACK
352 */
353#define	MBC_LOOPBACK_POINT_MASK		0x07
354#define	MBC_LOOPBACK_POINT_10BIT	0x00	/* 2425xx	*/
355#define	MBC_LOOPBACK_POINT_1BIT		0x01	/* 2425xx	*/
356#define	MBC_LOOPBACK_POINT_INTERNAL	0x01	/* 81xx		*/
357#define	MBC_LOOPBACK_POINT_EXTERNAL	0x02	/* 242581xx	*/
358
359/*
360 * MBC_ECHO
361 */
362#define	MBC_ECHO_ELS		BIT_15	/* echo ELS */
363#define	MBC_ECHO_64BIT		BIT_6	/* 64bit DMA address used */
364
365/*
366 * 81xx
367 * MBC_SET_PORT_CONFIG
368 * MBC_GET_PORT_CONFIG
369 */
370#define	LOOPBACK_MODE_FIELD_SIZE	0x03
371#define	LOOPBACK_MODE_FIELD_SHIFT	0x01
372#define	LOOPBACK_MODE_FIELD_MASK	((1 << LOOPBACK_MODE_FIELD_SIZE) -1)
373
374#define	LOOPBACK_MODE(mode)		((mode & LOOPBACK_MODE_FIELD_MASK) << \
375					    LOOPBACK_MODE_FIELD_SHIFT)
376#define	LOOPBACK_MODE_NONE		0x00
377#define	LOOPBACK_MODE_INTERNAL		0x02
378
379/*
380 * Mbc 20h (Get ID) returns the switch capabilities in mailbox7.
381 * The extra bits were added with 4.00.28 MID firmware.
382 */
383#define	GID_TOP_NL_PORT			0
384#define	GID_TOP_FL_PORT			1
385#define	GID_TOP_N_PORT			2
386#define	GID_TOP_F_PORT			3
387#define	GID_TOP_N_PORT_NO_TGT		4
388
389#define	GID_FP_IN_ORDER			BIT_8
390#define	GID_FP_MAC_ADDR			BIT_9
391#define	GID_FP_NPIV_SUPPORT		BIT_10	/* implies FDISC support */
392#define	GID_FP_VF_SUPPORT		BIT_12
393#define	GID_FP_SP_SUPPORT		BIT_13
394
395/*
396 * Driver Mailbox command definitions.
397 */
398#define	MAILBOX_TOV		30	/* Default Timeout value. */
399
400/* Mailbox command parameter structure definition. */
401typedef struct mbx_cmd {
402	uint32_t out_mb;		/* Outgoing from driver */
403	uint32_t in_mb;			/* Incomming from RISC */
404	uint16_t mb[MAX_MBOX_COUNT];
405	clock_t  timeout;		/* Timeout in seconds. */
406} mbx_cmd_t;
407
408/* Returned Mailbox registers. */
409typedef struct ql_mbx_data {
410	uint16_t	mb[MAX_MBOX_COUNT];
411} ql_mbx_data_t;
412
413/* Mailbox bit definitions for out_mb and in_mb */
414#define	MBX_29		BIT_29
415#define	MBX_28		BIT_28
416#define	MBX_27		BIT_27
417#define	MBX_26		BIT_26
418#define	MBX_25		BIT_25
419#define	MBX_24		BIT_24
420#define	MBX_23		BIT_23
421#define	MBX_22		BIT_22
422#define	MBX_21		BIT_21
423#define	MBX_20		BIT_20
424#define	MBX_19		BIT_19
425#define	MBX_18		BIT_18
426#define	MBX_17		BIT_17
427#define	MBX_16		BIT_16
428#define	MBX_15		BIT_15
429#define	MBX_14		BIT_14
430#define	MBX_13		BIT_13
431#define	MBX_12		BIT_12
432#define	MBX_11		BIT_11
433#define	MBX_10		BIT_10
434#define	MBX_9		BIT_9
435#define	MBX_8		BIT_8
436#define	MBX_7		BIT_7
437#define	MBX_6		BIT_6
438#define	MBX_5		BIT_5
439#define	MBX_4		BIT_4
440#define	MBX_3		BIT_3
441#define	MBX_2		BIT_2
442#define	MBX_1		BIT_1
443#define	MBX_0		BIT_0
444
445#define	MBX_0_THRU_1	MBX_0|MBX_1
446#define	MBX_0_THRU_2	MBX_0_THRU_1|MBX_2
447#define	MBX_0_THRU_3	MBX_0_THRU_2|MBX_3
448#define	MBX_0_THRU_4	MBX_0_THRU_3|MBX_4
449#define	MBX_0_THRU_5	MBX_0_THRU_4|MBX_5
450#define	MBX_0_THRU_6	MBX_0_THRU_5|MBX_6
451#define	MBX_0_THRU_7	MBX_0_THRU_6|MBX_7
452#define	MBX_0_THRU_8	MBX_0_THRU_7|MBX_8
453#define	MBX_0_THRU_9	MBX_0_THRU_8|MBX_9
454#define	MBX_0_THRU_10	MBX_0_THRU_9|MBX_10
455
456/*
457 * Firmware state codes from get firmware state mailbox command
458 */
459#define	FSTATE_CONFIG_WAIT	0
460#define	FSTATE_WAIT_AL_PA	1
461#define	FSTATE_WAIT_LOGIN	2
462#define	FSTATE_READY		3
463#define	FSTATE_LOSS_SYNC	4
464#define	FSTATE_ERROR		5
465#define	FSTATE_NON_PART		7
466
467/*
468 * Firmware options 1, 2, 3.
469 */
470#define	FO1_AE_ON_LIPF8			BIT_0
471#define	FO1_AE_ALL_LIP_RESET		BIT_1
472#define	FO1_CTIO_RETRY			BIT_3
473#define	FO1_DISABLE_LIP_F7_SW		BIT_4
474#define	FO1_DISABLE_100MS_LOS_WAIT	BIT_5
475#define	FO1_DISABLE_GPIO		BIT_6
476#define	FO1_AE_AUTO_BYPASS		BIT_9
477#define	FO1_ENABLE_PURE_IOCB		BIT_10
478#define	FO1_AE_PLOGI_RJT		BIT_11
479#define	FO1_AE_IMMEDIATE_NOTIFY_IOCB	BIT_11
480#define	FO1_ENABLE_ABORT_SEQUENCE	BIT_12
481#define	FO1_AE_QUEUE_FULL		BIT_13
482#define	FO1_POST_NOTIFY_ACK_IOCB_2_ATIO	BIT_13
483#define	FO1_POST_NOTIFY_ACK_IOCB	BIT_14
484
485#define	FO2_FCOE_512_MAX_MEM_WR_BURST	BIT_9
486#define	FO2_ENABLE_SELECTIVE_CLASS_2	BIT_5
487#define	FO2_REV_LOOPBACK		BIT_1
488#define	FO2_ENABLE_ATIO_TYPE_3		BIT_0
489
490#define	FO3_NO_ABORT_IO_ON_LINK_DOWN	BIT_14
491#define	FO3_HOLD_STS_FOR_ABTS_RSP	BIT_12
492#define	FO3_STARTUP_OPTS_VALID		BIT_5
493#define	FO3_SEND_N2N_PRLI		BIT_4
494#define	FO3_AE_RND_ERROR		BIT_1
495#define	FO3_ENABLE_EMERG_IOCB		BIT_0
496
497#define	FO13_LESB_NO_RESET		BIT_0
498
499/*
500 * f/w trace opcodes - mailbox 1(bits 7-0)
501 */
502#define	FTO_INSERT_TIME_STAMP	1
503#define	FTO_RESERVED_2		2
504#define	FTO_RESERVED_3		3
505#define	FTO_EXT_TRACE_ENABLE	4
506#define	FTO_EXT_TRACE_DISABLE	5
507#define	FTO_FCE_TRACE_ENABLE	8
508#define	FTO_FCE_TRACE_DISABLE	9
509#define	FTO_FCEMAXTRACEBUF	0x840	/* max frame size */
510
511/*
512 * fw version 1 attributes defines from firmware version mailbox command
513 */
514#define	FWATTRIB_EF		0x7
515#define	FWATTRIB_TP		0x17
516#define	FWATTRIB_IP		0x37
517#define	FWATTRIB_TPX		0x117
518#define	FWATTRIB_IPX		0x137
519#define	FWATTRIB_FL		0x217
520#define	FWATTRIB_FPX		0x317
521
522/*
523 * fw version 2 attributes defines
524 */
525#define	FWATTRIB2_CLASS2	BIT_0
526#define	FWATTRIB2_IP		BIT_1
527#define	FWATTRIB2_MID		BIT_2
528#define	FWATTRIB2_SB2		BIT_3
529#define	FWATTRIB2_T10_CRC	BIT_4
530#define	FWATTRIB2_VI		BIT_5
531#define	FWATTRIB2_MQUE		BIT_6
532#define	FWATTRIB2_FCOE		BIT_11
533#define	FWATTRIB2_EX_REL	BIT_13
534
535/*
536 * Diagnostic ELS ECHO parameter structure definition.
537 */
538typedef struct echo {
539	uint16_t		options;
540	uint32_t		transfer_count;
541	ddi_dma_cookie_t	transfer_data_address;
542	ddi_dma_cookie_t	receive_data_address;
543} echo_t;
544
545/*
546 * LFA command structure.
547 */
548#define	LFA_PAYLOAD_SIZE	38
549typedef struct lfa_cmd {
550	uint8_t	 resp_buffer_length[2];		/* length in 16bit words. */
551	uint8_t	 reserved[2];
552	uint8_t	 resp_buffer_address[8];
553	uint8_t	 subcommand_length[2];		/* length in 16bit words. */
554	uint8_t	 reserved_1[2];
555	uint8_t	 addr[4];
556	uint8_t  subcommand[2];
557	uint8_t	 payload[LFA_PAYLOAD_SIZE];
558} lfa_cmd_t;
559
560/* Define size of Loop Position Map. */
561#define	LOOP_POSITION_MAP_SIZE  128	/* bytes */
562
563/*
564 * Port Database structure definition
565 * Little endian except where noted.
566 */
567#define	PORT_DATABASE_SIZE	128	/* bytes */
568typedef struct port_database_23 {
569	uint8_t  options;
570	uint8_t  control;
571	uint8_t  master_state;
572	uint8_t  slave_state;
573	uint8_t  hard_address[3];
574	uint8_t  rsvd;
575	uint32_t port_id;
576	uint8_t  node_name[8];		/* Big endian. */
577	uint8_t  port_name[8];		/* Big endian. */
578	uint16_t execution_throttle;
579	uint16_t execution_count;
580	uint8_t  reset_count;
581	uint8_t  reserved_2;
582	uint16_t resource_allocation;
583	uint16_t current_allocation;
584	uint16_t queue_head;
585	uint16_t queue_tail;
586	uint16_t transmit_execution_list_next;
587	uint16_t transmit_execution_list_previous;
588	uint16_t common_features;
589	uint16_t total_concurrent_sequences;
590	uint16_t RO_by_information_category;
591	uint8_t  recipient;
592	uint8_t  initiator;
593	uint16_t receive_data_size;
594	uint16_t concurrent_sequences;
595	uint16_t open_sequences_per_exchange;
596	uint16_t lun_abort_flags;
597	uint16_t lun_stop_flags;
598	uint16_t stop_queue_head;
599	uint16_t stop_queue_tail;
600	uint16_t port_retry_timer;
601	uint16_t next_sequence_id;
602	uint16_t frame_count;
603	uint16_t PRLI_payload_length;
604	uint16_t PRLI_service_parameter_word_0; /* Big endian */
605						/* Bits 15-0 of word 0 */
606	uint16_t PRLI_service_parameter_word_3; /* Big endian */
607						/* Bits 15-0 of word 3 */
608	uint16_t loop_id;
609	uint16_t extended_lun_info_list_pointer;
610	uint16_t extended_lun_stop_list_pointer;
611} port_database_23_t;
612
613typedef struct port_database_24 {
614	uint16_t flags;
615	uint8_t  current_login_state;
616	uint8_t  last_stable_login_state;
617	uint8_t  hard_address[3];
618	uint8_t  rsvd;
619	uint8_t  port_id[3];
620	uint8_t  sequence_id;
621	uint16_t port_retry_timer;
622	uint16_t n_port_handle;
623	uint16_t receive_data_size;
624	uint8_t	 reserved_1[2];
625	uint16_t PRLI_service_parameter_word_0; /* Big endian */
626						/* Bits 15-0 of word 0 */
627	uint16_t PRLI_service_parameter_word_3; /* Big endian */
628						/* Bits 15-0 of word 3 */
629	uint8_t  port_name[8];		/* Big endian. */
630	uint8_t  node_name[8];		/* Big endian. */
631	uint8_t	 reserved_2[24];
632} port_database_24_t;
633
634/*
635 * Port database slave/master/current_login/ast_stable_login states
636 */
637#define	PD_STATE_DISCOVERY			0
638#define	PD_STATE_WAIT_DISCOVERY_ACK		1
639#define	PD_STATE_PORT_LOGIN			2
640#define	PD_STATE_WAIT_PORT_LOGIN_ACK		3
641#define	PD_STATE_PLOGI_PENDING			3
642#define	PD_STATE_PROCESS_LOGIN			4
643#define	PD_STATE_PLOGI_COMPLETED		4
644#define	PD_STATE_WAIT_PROCESS_LOGIN_ACK		5
645#define	PD_STATE_PRLI_PENDING			5
646#define	PD_STATE_PORT_LOGGED_IN			6
647#define	PD_STATE_PLOGI_PRLI_COMPLETED		6
648#define	PD_STATE_PORT_UNAVAILABLE		7
649#define	PD_STATE_PROCESS_LOGOUT			8
650#define	PD_STATE_WAIT_PROCESS_LOGOUT_ACK	9
651#define	PD_STATE_PORT_LOGOUT			10
652#define	PD_STATE_WAIT_PORT_LOGOUT_ACK		11
653
654#define	PD_PORT_LOGIN(tq) \
655	(tq->master_state == PD_STATE_PROCESS_LOGIN || \
656	tq->master_state == PD_STATE_PORT_LOGGED_IN || \
657	tq->slave_state == PD_STATE_PROCESS_LOGIN || \
658	tq->slave_state == PD_STATE_PORT_LOGGED_IN)
659
660/*
661 * ql_login_lport() options
662 */
663#define	LLF_NONE	0
664#define	LLF_PLOGI	BIT_0		/* unconditional PLOGI */
665
666/*
667 * ql_login_fport() options
668 */
669#define	LFF_NONE	0
670#define	LFF_NO_PLOGI	BIT_0
671#define	LFF_NO_PRLI	BIT_1
672
673/*
674 * ql_get_port_database() options
675 */
676#define	PDF_NONE	0
677#define	PDF_PLOGI	BIT_0
678#define	PDF_ADISC	BIT_1
679
680/*
681 * ql_get_adapter_id() returned connection types
682 */
683#define	CNX_LOOP_NO_FABRIC		0
684#define	CNX_FLPORT_IN_LOOP		1
685#define	CNX_NPORT_2_NPORT_P2P		2
686#define	CNX_FLPORT_P2P			3
687#define	CNX_NPORT_2_NPORT_NO_TGT_RSP	4
688
689/*
690 * Set/Get Port Configuration MBC
691 */
692#define	LINK_CONFIG_PAUSE_MASK		(BIT_6 | BIT_5)
693#define	LINK_CONFIG_PAUSE_DISABLE	0x00
694#define	LINK_CONFIG_PAUSE_STD_ETH	0x01
695#define	LINK_CONFIG_PAUSE_PER_PRIO	0x02
696
697#define	LINK_CONFIG_DCBX_ENA		BIT_4
698
699#define	LINK_CONFIG_LB_MODE_MASK	(BIT_3 | BIT_2 | BIT_1)
700#define	LINK_CONFIG_LB_NONE		0x00
701#define	LINK_CONFIG_LB_INTERNAL		0x02
702
703#define	LINK_CONFIG2_BP_TRAIN_ENA	BIT_15
704#define	LINK_CONFIG2_BP_AUTO_NEGO_ENA	BIT_14
705#define	LINK_CONFIG2_JUMBO_FRM_ENA	BIT_0
706
707/*
708 *
709 */
710#define	FCF_LIST_RETURN_ALL	BIT_0
711#define	FCF_LIST_RETURN_ONE	BIT_1
712
713typedef struct fcf_desc {
714	uint16_t	options;
715	uint16_t	fcf_index;
716	uint32_t	buffer_size;
717} ql_fcf_list_desc_t;
718
719/*
720 * Global Data in ql_mbx.c source file.
721 */
722
723/*
724 * Global Function Prototypes in ql_mbx.c source file.
725 */
726int ql_initialize_ip(ql_adapter_state_t *);
727int ql_shutdown_ip(ql_adapter_state_t *);
728int ql_online_selftest(ql_adapter_state_t *);
729int ql_loop_back(ql_adapter_state_t *, uint16_t, lbp_t *, uint32_t, uint32_t);
730int ql_echo(ql_adapter_state_t *, uint16_t, echo_t *);
731int ql_send_change_request(ql_adapter_state_t *, uint16_t);
732int ql_send_lfa(ql_adapter_state_t *, lfa_cmd_t *);
733int ql_clear_aca(ql_adapter_state_t *, ql_tgt_t *, uint16_t);
734int ql_target_reset(ql_adapter_state_t *, ql_tgt_t *, uint16_t);
735int ql_abort_target(ql_adapter_state_t *, ql_tgt_t *, uint16_t);
736int ql_lun_reset(ql_adapter_state_t *, ql_tgt_t *, uint16_t);
737int ql_clear_task_set(ql_adapter_state_t *, ql_tgt_t *, uint16_t);
738int ql_abort_task_set(ql_adapter_state_t *, ql_tgt_t *, uint16_t);
739int ql_loop_port_bypass(ql_adapter_state_t *, ql_tgt_t *);
740int ql_loop_port_enable(ql_adapter_state_t *, ql_tgt_t *);
741int ql_login_lport(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t);
742int ql_login_fport(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t,
743    ql_mbx_data_t *);
744int ql_logout_fabric_port(ql_adapter_state_t *, ql_tgt_t *);
745int ql_log_iocb(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t,
746    ql_mbx_data_t *);
747int ql_get_port_database(ql_adapter_state_t *, ql_tgt_t *, uint8_t);
748int ql_get_loop_position_map(ql_adapter_state_t *, size_t, caddr_t);
749int ql_set_rnid_params(ql_adapter_state_t *, size_t, caddr_t);
750int ql_send_rnid_els(ql_adapter_state_t *, uint16_t, uint8_t, size_t, caddr_t);
751int ql_get_rnid_params(ql_adapter_state_t *, size_t, caddr_t);
752int ql_get_link_status(ql_adapter_state_t *, uint16_t, size_t, caddr_t,
753    uint8_t);
754int ql_get_status_counts(ql_adapter_state_t *, uint16_t, size_t, caddr_t,
755    uint8_t);
756int ql_reset_link_status(ql_adapter_state_t *);
757int ql_loop_reset(ql_adapter_state_t *);
758int ql_initiate_lip(ql_adapter_state_t *);
759int ql_full_login_lip(ql_adapter_state_t *);
760int ql_lip_reset(ql_adapter_state_t *, uint16_t);
761int ql_abort_command(ql_adapter_state_t *, ql_srb_t *);
762int ql_verify_checksum(ql_adapter_state_t *);
763int ql_get_id_list(ql_adapter_state_t *, caddr_t, uint32_t, ql_mbx_data_t *);
764int ql_wrt_risc_ram(ql_adapter_state_t *, uint32_t, uint64_t, uint32_t);
765int ql_rd_risc_ram(ql_adapter_state_t *, uint32_t, uint64_t, uint32_t);
766int ql_wrt_risc_ram_word(ql_adapter_state_t *, uint32_t, uint32_t);
767int ql_rd_risc_ram_word(ql_adapter_state_t *, uint32_t, uint32_t *);
768int ql_issue_mbx_iocb(ql_adapter_state_t *, caddr_t, uint32_t);
769int ql_mbx_wrap_test(ql_adapter_state_t *, ql_mbx_data_t *);
770int ql_execute_fw(ql_adapter_state_t *);
771int ql_get_firmware_option(ql_adapter_state_t *, ql_mbx_data_t *);
772int ql_set_firmware_option(ql_adapter_state_t *, ql_mbx_data_t *);
773int ql_init_firmware(ql_adapter_state_t *);
774int ql_get_firmware_state(ql_adapter_state_t *, ql_mbx_data_t *);
775int ql_get_adapter_id(ql_adapter_state_t *, ql_mbx_data_t *);
776int ql_get_fw_version(ql_adapter_state_t *, ql_mbx_data_t *, uint16_t);
777int ql_data_rate(ql_adapter_state_t *, ql_mbx_data_t *);
778int ql_diag_loopback(ql_adapter_state_t *, uint16_t, caddr_t, uint32_t,
779    uint16_t, uint32_t, ql_mbx_data_t *);
780int ql_diag_echo(ql_adapter_state_t *, uint16_t, caddr_t, uint32_t, uint16_t,
781    ql_mbx_data_t *);
782int ql_serdes_param(ql_adapter_state_t *, ql_mbx_data_t *);
783int ql_get_timeout_parameters(ql_adapter_state_t *, uint16_t *);
784int ql_stop_firmware(ql_adapter_state_t *);
785int ql_read_sfp(ql_adapter_state_t *, dma_mem_t *, uint16_t, uint16_t);
786int ql_iidma_rate(ql_adapter_state_t *, uint16_t, uint32_t *, uint32_t);
787int ql_fw_etrace(ql_adapter_state_t *, dma_mem_t *, uint16_t);
788int ql_reset_menlo(ql_adapter_state_t *, ql_mbx_data_t *, uint16_t);
789int ql_restart_mpi(ql_adapter_state_t *);
790int ql_idc_request(ql_adapter_state_t *, ql_mbx_data_t *);
791int ql_idc_ack(ql_adapter_state_t *);
792int ql_idc_time_extend(ql_adapter_state_t *, ql_mbx_data_t *);
793int ql_port_reset(ql_adapter_state_t *);
794int ql_set_port_config(ql_adapter_state_t *, ql_mbx_data_t *);
795int ql_get_port_config(ql_adapter_state_t *, ql_mbx_data_t *);
796int ql_flash_access(ql_adapter_state_t *, uint16_t, uint32_t, uint32_t,
797    uint32_t *);
798int ql_get_xgmac_stats(ql_adapter_state_t *, size_t, caddr_t);
799int ql_get_dcbx_params(ql_adapter_state_t *, uint32_t, caddr_t);
800int ql_get_fcf_list_mbx(ql_adapter_state_t *, ql_fcf_list_desc_t *, caddr_t);
801int ql_get_resource_cnts(ql_adapter_state_t *, ql_mbx_data_t *);
802int ql_toggle_interrupt(ql_adapter_state_t *, uint16_t);
803/*
804 * Mailbox command table initializer
805 */
806#define	MBOX_CMD_TABLE()						\
807{									\
808	{MBC_LOAD_RAM, "MBC_LOAD_RAM"},					\
809	{MBC_EXECUTE_FIRMWARE, "MBC_EXECUTE_FIRMWARE"},			\
810	{MBC_DUMP_RAM, "MBC_DUMP_RAM"},					\
811	{MBC_WRITE_RAM_WORD, "MBC_WRITE_RAM_WORD"},			\
812	{MBC_READ_RAM_WORD, "MBC_READ_RAM_WORD"},			\
813	{MBC_MAILBOX_REGISTER_TEST, "MBC_MAILBOX_REGISTER_TEST"},	\
814	{MBC_VERIFY_CHECKSUM, "MBC_VERIFY_CHECKSUM"},			\
815	{MBC_ABOUT_FIRMWARE, "MBC_ABOUT_FIRMWARE"},			\
816	{MBC_DUMP_RISC_RAM, "MBC_DUMP_RISC_RAM"},			\
817	{MBC_LOAD_RAM_EXTENDED, "MBC_LOAD_RAM_EXTENDED"},		\
818	{MBC_DUMP_RAM_EXTENDED, "MBC_DUMP_RAM_EXTENDED"},		\
819	{MBC_WRITE_RAM_EXTENDED, "MBC_WRITE_RAM_EXTENDED"},		\
820	{MBC_READ_RAM_EXTENDED, "MBC_READ_RAM_EXTENDED"},		\
821	{MBC_SERDES_TRANSMIT_PARAMETERS, \
822	"MBC_SERDES_TRANSMIT_PARAMETERS or MBC_TOGGLE_INTERRUPT"},\
823	{MBC_2300_EXECUTE_IOCB, "MBC_2300_EXECUTE_IOCB"},		\
824	{MBC_GET_IO_STATUS, "MBC_GET_IO_STATUS"},			\
825	{MBC_STOP_FIRMWARE, "MBC_STOP_FIRMWARE"},			\
826	{MBC_ABORT_COMMAND_IOCB, "MBC_ABORT_COMMAND_IOCB"},		\
827	{MBC_ABORT_DEVICE, "MBC_ABORT_DEVICE"},				\
828	{MBC_ABORT_TARGET, "MBC_ABORT_TARGET"},				\
829	{MBC_RESET, "MBC_RESET"},					\
830	{MBC_XMIT_PARM, "MBC_XMIT_PARM"},				\
831	{MBC_PORT_PARAM, "MBC_PORT_PARAM"},				\
832	{MBC_GET_ID, "MBC_GET_ID"},					\
833	{MBC_GET_TIMEOUT_PARAMETERS, "MBC_GET_TIMEOUT_PARAMETERS"},	\
834	{MBC_TRACE_CONTROL, "MBC_TRACE_CONTROL"},			\
835	{MBC_GET_FIRMWARE_OPTIONS, "MBC_GET_FIRMWARE_OPTIONS"},		\
836	{MBC_READ_SFP, "MBC_READ_SFP"},					\
837	{MBC_SET_FIRMWARE_OPTIONS, "MBC_SET_FIRMWARE_OPTIONS"},		\
838	{MBC_RESET_MENLO, "MBC_RESET_MENLO"},				\
839	{MBC_RESTART_MPI, "MBC_RESTART_MPI"},				\
840	{MBC_FLASH_ACCESS, "MBC_FLASH_ACCESS"},				\
841	{MBC_LOOP_PORT_BYPASS, "MBC_LOOP_PORT_BYPASS"},			\
842	{MBC_LOOP_PORT_ENABLE, "MBC_LOOP_PORT_ENABLE"},			\
843	{MBC_GET_RESOURCE_COUNTS, "MBC_GET_RESOURCE_COUNTS"},		\
844	{MBC_NON_PARTICIPATE, "MBC_NON_PARTICIPATE"},			\
845	{MBC_ECHO, "MBC_ECHO"},						\
846	{MBC_DIAGNOSTIC_LOOP_BACK, "MBC_DIAGNOSTIC_LOOP_BACK"},		\
847	{MBC_ONLINE_SELF_TEST, "MBC_ONLINE_SELF_TEST"},			\
848	{MBC_ENHANCED_GET_PORT_DATABASE, "MBC_ENHANCED_GET_PORT_DATABASE"},\
849	{MBC_INITIALIZE_MULTI_ID_FW, "MBC_INITIALIZE_MULTI_ID_FW"},	\
850	{MBC_GET_FCF_LIST, "MBC_GET_FCF_LIST"},				\
851	{MBC_GET_DCBX_PARAMS, "MBC_GET_DCBX_PARAMS"},			\
852	{MBC_RESET_LINK_STATUS, "MBC_RESET_LINK_STATUS"},		\
853	{MBC_EXECUTE_IOCB, "MBC_EXECUTE_IOCB"},				\
854	{MBC_SEND_RNID_ELS, "MBC_SEND_RNID_ELS"},			\
855	{MBC_SET_PARAMETERS, "MBC_SET_PARAMETERS"},			\
856	{MBC_GET_PARAMETERS, "MBC_GET_PARAMETERS"},			\
857	{MBC_DATA_RATE, "MBC_DATA_RATE"},				\
858	{MBC_INITIALIZE_FIRMWARE, "MBC_INITIALIZE_FIRMWARE"},		\
859	{MBC_INITIATE_LIP, "MBC_INITIATE_LIP"},				\
860	{MBC_GET_FC_AL_POSITION_MAP, "MBC_GET_FC_AL_POSITION_MAP"},	\
861	{MBC_GET_PORT_DATABASE, "MBC_GET_PORT_DATABASE"},		\
862	{MBC_CLEAR_ACA, "MBC_CLEAR_ACA"},				\
863	{MBC_TARGET_RESET, "MBC_TARGET_RESET"},				\
864	{MBC_CLEAR_TASK_SET, "MBC_CLEAR_TASK_SET"},			\
865	{MBC_ABORT_TASK_SET, "MBC_ABORT_TASK_SET"},			\
866	{MBC_GET_FIRMWARE_STATE, "MBC_GET_FIRMWARE_STATE"},		\
867	{MBC_GET_PORT_NAME, "MBC_GET_PORT_NAME"},			\
868	{MBC_GET_LINK_STATUS, "MBC_GET_LINK_STATUS"},			\
869	{MBC_LIP_RESET, "MBC_LIP_RESET"},				\
870	{MBC_GET_STATUS_COUNTS, "MBC_GET_STATUS_COUNTS"},		\
871	{MBC_SEND_SNS_COMMAND, "MBC_SEND_SNS_COMMAND"},			\
872	{MBC_LOGIN_FABRIC_PORT, "MBC_LOGIN_FABRIC_PORT"},		\
873	{MBC_SEND_CHANGE_REQUEST, "MBC_SEND_CHANGE_REQUEST"},		\
874	{MBC_LOGOUT_FABRIC_PORT, "MBC_LOGOUT_FABRIC_PORT"},		\
875	{MBC_LIP_FULL_LOGIN, "MBC_LIP_FULL_LOGIN"},			\
876	{MBC_LOGIN_LOOP_PORT, "MBC_LOGIN_LOOP_PORT"},			\
877	{MBC_PORT_NODE_NAME_LIST, "MBC_PORT_NODE_NAME_LIST"},		\
878	{MBC_INITIALIZE_IP, "MBC_INITIALIZE_IP"},			\
879	{MBC_SEND_FARP_REQ_COMMAND, "MBC_SEND_FARP_REQ_COMMAND"},	\
880	{MBC_UNLOAD_IP, "MBC_UNLOAD_IP"},				\
881	{MBC_GET_XGMAC_STATS, "MBC_GET_XGMAC_STATS"},			\
882	{MBC_GET_ID_LIST, "MBC_GET_ID_LIST"},				\
883	{MBC_SEND_LFA_COMMAND, "MBC_SEND_LFA_COMMAND"},			\
884	{MBC_LUN_RESET, "MBC_LUN_RESET"},				\
885	{MBC_IDC_REQUEST, "MBC_IDC_REQUEST"},				\
886	{MBC_IDC_ACK, "MBC_IDC_ACK"},					\
887	{MBC_IDC_TIME_EXTEND, "MBC_IDC_TIME_EXTEND"},			\
888	{MBC_PORT_RESET, "MBC_PORT_RESET"},				\
889	{MBC_SET_PORT_CONFIG, "MBC_SET_PORT_CONFIG"},			\
890	{MBC_GET_PORT_CONFIG, "MBC_GET_PORT_CONFIG"},			\
891	{0, "Unsupported"}						\
892}
893
894#ifdef	__cplusplus
895}
896#endif
897
898#endif /* _QL_MBX_H */
899