1fcf3ce44SJohn Forte /* 2fcf3ce44SJohn Forte * CDDL HEADER START 3fcf3ce44SJohn Forte * 4fcf3ce44SJohn Forte * The contents of this file are subject to the terms of the 5fcf3ce44SJohn Forte * Common Development and Distribution License (the "License"). 6fcf3ce44SJohn Forte * You may not use this file except in compliance with the License. 7fcf3ce44SJohn Forte * 8fcf3ce44SJohn Forte * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9fcf3ce44SJohn Forte * or http://www.opensolaris.org/os/licensing. 10fcf3ce44SJohn Forte * See the License for the specific language governing permissions 11fcf3ce44SJohn Forte * and limitations under the License. 12fcf3ce44SJohn Forte * 13fcf3ce44SJohn Forte * When distributing Covered Code, include this CDDL HEADER in each 14fcf3ce44SJohn Forte * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15fcf3ce44SJohn Forte * If applicable, add the following below this CDDL HEADER, with the 16fcf3ce44SJohn Forte * fields enclosed by brackets "[]" replaced with your own identifying 17fcf3ce44SJohn Forte * information: Portions Copyright [yyyy] [name of copyright owner] 18fcf3ce44SJohn Forte * 19fcf3ce44SJohn Forte * CDDL HEADER END 20fcf3ce44SJohn Forte */ 21fcf3ce44SJohn Forte 22*4c3888b8SHans Rosenfeld /* Copyright 2015 QLogic Corporation */ 23fcf3ce44SJohn Forte 24fcf3ce44SJohn Forte /* 25*4c3888b8SHans Rosenfeld * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 26fcf3ce44SJohn Forte */ 27fcf3ce44SJohn Forte 28fcf3ce44SJohn Forte #ifndef _QL_INIT_H 29fcf3ce44SJohn Forte #define _QL_INIT_H 30fcf3ce44SJohn Forte 31fcf3ce44SJohn Forte /* 32fcf3ce44SJohn Forte * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 33fcf3ce44SJohn Forte * 34fcf3ce44SJohn Forte * *********************************************************************** 35fcf3ce44SJohn Forte * * ** 36fcf3ce44SJohn Forte * * NOTICE ** 37*4c3888b8SHans Rosenfeld * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION ** 38fcf3ce44SJohn Forte * * ALL RIGHTS RESERVED ** 39fcf3ce44SJohn Forte * * ** 40fcf3ce44SJohn Forte * *********************************************************************** 41fcf3ce44SJohn Forte * 42fcf3ce44SJohn Forte */ 43fcf3ce44SJohn Forte 44fcf3ce44SJohn Forte #ifdef __cplusplus 45fcf3ce44SJohn Forte extern "C" { 46fcf3ce44SJohn Forte #endif 47fcf3ce44SJohn Forte 48*4c3888b8SHans Rosenfeld extern uint32_t ql_task_cb_dly; 49*4c3888b8SHans Rosenfeld 50fcf3ce44SJohn Forte /* 51fcf3ce44SJohn Forte * ISP2200 NVRAM structure definition. 52fcf3ce44SJohn Forte * Little endian except where noted. 53fcf3ce44SJohn Forte */ 54fcf3ce44SJohn Forte typedef struct nvram { 55fcf3ce44SJohn Forte /* 56fcf3ce44SJohn Forte * NVRAM header 57fcf3ce44SJohn Forte */ 58fcf3ce44SJohn Forte uint8_t id[4]; 59fcf3ce44SJohn Forte uint8_t nvram_version; 60fcf3ce44SJohn Forte uint8_t reserved_0; 61fcf3ce44SJohn Forte 62fcf3ce44SJohn Forte /* 63fcf3ce44SJohn Forte * NVRAM RISC parameter block 64fcf3ce44SJohn Forte */ 65fcf3ce44SJohn Forte uint8_t parameter_block_version; 66fcf3ce44SJohn Forte uint8_t reserved_1; 67fcf3ce44SJohn Forte 68fcf3ce44SJohn Forte /* 69fcf3ce44SJohn Forte * LSB BIT 0 = enable_hard_loop_id 70fcf3ce44SJohn Forte * LSB BIT 1 = enable_fairness 71fcf3ce44SJohn Forte * LSB BIT 2 = enable_full_duplex 72fcf3ce44SJohn Forte * LSB BIT 3 = enable_fast_posting 73fcf3ce44SJohn Forte * LSB BIT 4 = enable_target_mode 74fcf3ce44SJohn Forte * LSB BIT 5 = disable_initiator_mode 75fcf3ce44SJohn Forte * LSB BIT 6 = enable_adisc 76fcf3ce44SJohn Forte * LSB BIT 7 = enable_target_inquiry_data 77fcf3ce44SJohn Forte * 78fcf3ce44SJohn Forte * MSB BIT 0 = enable_port_update_ae 79fcf3ce44SJohn Forte * MSB BIT 1 = disable_initial_lip 80fcf3ce44SJohn Forte * MSB BIT 2 = enable_decending_soft_assign 81fcf3ce44SJohn Forte * MSB BIT 3 = previous_assigned_addressing 82fcf3ce44SJohn Forte * MSB BIT 4 = enable_stop_q_on_full 83fcf3ce44SJohn Forte * MSB BIT 5 = enable_full_login_on_lip 84fcf3ce44SJohn Forte * MSB BIT 6 = enable_node_name 85fcf3ce44SJohn Forte * MSB BIT 7 = extended_control_block 86fcf3ce44SJohn Forte */ 87fcf3ce44SJohn Forte uint8_t firmware_options[2]; 88fcf3ce44SJohn Forte 89fcf3ce44SJohn Forte uint8_t max_frame_length[2]; 90fcf3ce44SJohn Forte uint8_t max_iocb_allocation[2]; 91fcf3ce44SJohn Forte uint8_t execution_throttle[2]; 92fcf3ce44SJohn Forte uint8_t login_retry_count; 93fcf3ce44SJohn Forte uint8_t retry_delay; /* unused */ 94fcf3ce44SJohn Forte uint8_t port_name[8]; /* Big endian. */ 95fcf3ce44SJohn Forte uint8_t hard_address[2]; 96fcf3ce44SJohn Forte uint8_t inquiry; 97fcf3ce44SJohn Forte uint8_t login_timeout; 98fcf3ce44SJohn Forte uint8_t node_name[8]; /* Big endian. */ 99fcf3ce44SJohn Forte 100fcf3ce44SJohn Forte /* 101fcf3ce44SJohn Forte * LSB BIT 0 = Timer operation mode bit 0 102fcf3ce44SJohn Forte * LSB BIT 1 = Timer operation mode bit 1 103fcf3ce44SJohn Forte * LSB BIT 2 = Timer operation mode bit 2 104fcf3ce44SJohn Forte * LSB BIT 3 = Timer operation mode bit 3 105fcf3ce44SJohn Forte * LSB BIT 4 = P2P Connection option bit 0 106fcf3ce44SJohn Forte * LSB BIT 5 = P2P Connection option bit 1 107fcf3ce44SJohn Forte * LSB BIT 6 = P2P Connection option bit 2 108fcf3ce44SJohn Forte * LSB BIT 7 = Enable Non part on LIHA failure 109fcf3ce44SJohn Forte * 110fcf3ce44SJohn Forte * MSB BIT 0 = Enable class 2 111fcf3ce44SJohn Forte * MSB BIT 1 = Enable ACK0 112fcf3ce44SJohn Forte * MSB BIT 2 = 113fcf3ce44SJohn Forte * MSB BIT 3 = 114fcf3ce44SJohn Forte * MSB BIT 4 = FC Tape Enable 115fcf3ce44SJohn Forte * MSB BIT 5 = Enable FC Confirm 116fcf3ce44SJohn Forte * MSB BIT 6 = Enable command queuing in target mode 117fcf3ce44SJohn Forte * MSB BIT 7 = No Logo On Link Down 118fcf3ce44SJohn Forte */ 119fcf3ce44SJohn Forte uint8_t add_fw_opt[2]; 120fcf3ce44SJohn Forte uint8_t response_accumulation_timer; 121fcf3ce44SJohn Forte uint8_t interrupt_delay_timer; 122fcf3ce44SJohn Forte 123fcf3ce44SJohn Forte /* 124fcf3ce44SJohn Forte * LSB BIT 0 = Enable Read xfr_rdy 125fcf3ce44SJohn Forte * LSB BIT 1 = Soft ID only 126fcf3ce44SJohn Forte * LSB BIT 2 = 127fcf3ce44SJohn Forte * LSB BIT 3 = 128fcf3ce44SJohn Forte * LSB BIT 4 = FCP RSP Payload [0] 129fcf3ce44SJohn Forte * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 130fcf3ce44SJohn Forte * LSB BIT 6 = 131fcf3ce44SJohn Forte * LSB BIT 7 = 132fcf3ce44SJohn Forte * 133fcf3ce44SJohn Forte * MSB BIT 0 = Sbus enable - 2300 134fcf3ce44SJohn Forte * MSB BIT 1 = 135fcf3ce44SJohn Forte * MSB BIT 2 = 136fcf3ce44SJohn Forte * MSB BIT 3 = 137fcf3ce44SJohn Forte * MSB BIT 4 = 138fcf3ce44SJohn Forte * MSB BIT 5 = Enable 50 ohm termination 139fcf3ce44SJohn Forte * MSB BIT 6 = Data Rate (2300 only) 140fcf3ce44SJohn Forte * MSB BIT 7 = Data Rate (2300 only) 141fcf3ce44SJohn Forte */ 142fcf3ce44SJohn Forte uint8_t special_options[2]; 143fcf3ce44SJohn Forte 144fcf3ce44SJohn Forte /* Reserved for expanded RISC parameter block */ 145fcf3ce44SJohn Forte uint8_t reserved_4[26]; 146fcf3ce44SJohn Forte 147fcf3ce44SJohn Forte /* 148fcf3ce44SJohn Forte * NVRAM host parameter block 149fcf3ce44SJohn Forte * 150fcf3ce44SJohn Forte * LSB BIT 0 = unused 151fcf3ce44SJohn Forte * LSB BIT 1 = disable_bios 152fcf3ce44SJohn Forte * LSB BIT 2 = disable_luns 153fcf3ce44SJohn Forte * LSB BIT 3 = enable_selectable_boot 154fcf3ce44SJohn Forte * LSB BIT 4 = disable_risc_code_load 155fcf3ce44SJohn Forte * LSB BIT 5 = set_cache_line_size_1 156fcf3ce44SJohn Forte * LSB BIT 6 = pci_parity_disable 157fcf3ce44SJohn Forte * LSB BIT 7 = enable_extended_logging 158fcf3ce44SJohn Forte * 159fcf3ce44SJohn Forte * MSB BIT 0 = enable_64bit_addressing 160fcf3ce44SJohn Forte * MSB BIT 1 = enable_lip_reset 161fcf3ce44SJohn Forte * MSB BIT 2 = enable_lip_full_login 162fcf3ce44SJohn Forte * MSB BIT 3 = enable_target_reset 163fcf3ce44SJohn Forte * MSB BIT 4 = enable_database_storage 164fcf3ce44SJohn Forte * MSB BIT 5 = unused 165fcf3ce44SJohn Forte * MSB BIT 6 = unused 166fcf3ce44SJohn Forte * MSB BIT 7 = unused 167fcf3ce44SJohn Forte */ 168*4c3888b8SHans Rosenfeld uint8_t host_p[2]; 169fcf3ce44SJohn Forte 170*4c3888b8SHans Rosenfeld uint8_t boot_node_name[8]; 171*4c3888b8SHans Rosenfeld uint8_t boot_lun_number; 172*4c3888b8SHans Rosenfeld uint8_t reset_delay; 173*4c3888b8SHans Rosenfeld uint8_t port_down_retry_count; 174*4c3888b8SHans Rosenfeld uint8_t reserved_5; 175fcf3ce44SJohn Forte 176*4c3888b8SHans Rosenfeld uint8_t maximum_luns_per_target[2]; 177fcf3ce44SJohn Forte 178fcf3ce44SJohn Forte uint8_t reserved_6[14]; 179fcf3ce44SJohn Forte 180fcf3ce44SJohn Forte /* Offset 100 */ 181fcf3ce44SJohn Forte uint8_t reverved_7[12]; 182fcf3ce44SJohn Forte 183fcf3ce44SJohn Forte /* offset 112 */ 184fcf3ce44SJohn Forte uint8_t adapInfo[16]; /* Sun OEM HBA's 23xx only */ 185fcf3ce44SJohn Forte 186fcf3ce44SJohn Forte uint8_t reserved_8[22]; 187fcf3ce44SJohn Forte 188fcf3ce44SJohn Forte /* Offset 150 */ 189fcf3ce44SJohn Forte uint8_t reserved_9[50]; 190fcf3ce44SJohn Forte 191fcf3ce44SJohn Forte /* Offset 200 */ 192fcf3ce44SJohn Forte uint8_t reserved_10[32]; 193fcf3ce44SJohn Forte 194fcf3ce44SJohn Forte /* 195fcf3ce44SJohn Forte * NVRAM Adapter Features offset 232-239 196fcf3ce44SJohn Forte * 197fcf3ce44SJohn Forte * LSB BIT 0 = External GBIC 198fcf3ce44SJohn Forte * LSB BIT 1 = Risc RAM parity 199fcf3ce44SJohn Forte * LSB BIT 2 = Buffer Plus Module 200fcf3ce44SJohn Forte * LSB BIT 3 = Multi Chip Adapter 201fcf3ce44SJohn Forte * LSB BIT 4 = 202fcf3ce44SJohn Forte * LSB BIT 5 = 203fcf3ce44SJohn Forte * LSB BIT 6 = 204fcf3ce44SJohn Forte * LSB BIT 7 = 205fcf3ce44SJohn Forte * 206fcf3ce44SJohn Forte * MSB BIT 0 = 207fcf3ce44SJohn Forte * MSB BIT 1 = 208fcf3ce44SJohn Forte * MSB BIT 2 = 209fcf3ce44SJohn Forte * MSB BIT 3 = 210fcf3ce44SJohn Forte * MSB BIT 4 = 211fcf3ce44SJohn Forte * MSB BIT 5 = 212fcf3ce44SJohn Forte * MSB BIT 6 = 213fcf3ce44SJohn Forte * MSB BIT 7 = 214fcf3ce44SJohn Forte */ 215fcf3ce44SJohn Forte uint8_t adapter_features[2]; 216fcf3ce44SJohn Forte uint8_t reserved_11[6]; 217fcf3ce44SJohn Forte 218fcf3ce44SJohn Forte /* 219fcf3ce44SJohn Forte * Resrved for use with ISP2300 - offset 240 220fcf3ce44SJohn Forte */ 221fcf3ce44SJohn Forte uint8_t reserved_12[4]; 222fcf3ce44SJohn Forte 223fcf3ce44SJohn Forte /* Subsystem ID must be at offset 244 */ 224fcf3ce44SJohn Forte uint8_t subsystem_vendor_id[2]; 225fcf3ce44SJohn Forte 226fcf3ce44SJohn Forte uint8_t reserved_13[2]; 227fcf3ce44SJohn Forte 228fcf3ce44SJohn Forte /* Subsystem device ID must be at offset 248 */ 229fcf3ce44SJohn Forte uint8_t subsystem_device_id[2]; 230fcf3ce44SJohn Forte 231fcf3ce44SJohn Forte /* Subsystem vendor ID for ISP2200 */ 232fcf3ce44SJohn Forte uint8_t subsystem_vendor_id_2200[2]; 233fcf3ce44SJohn Forte 234fcf3ce44SJohn Forte /* Subsystem device ID for ISP2200 */ 235fcf3ce44SJohn Forte uint8_t subsystem_device_id_2200[2]; 236fcf3ce44SJohn Forte 237fcf3ce44SJohn Forte uint8_t reserved_14; 238fcf3ce44SJohn Forte uint8_t checksum; 239fcf3ce44SJohn Forte } nvram_t; 240fcf3ce44SJohn Forte 241fcf3ce44SJohn Forte /* 242fcf3ce44SJohn Forte * NVRAM structure definition. 243fcf3ce44SJohn Forte */ 244fcf3ce44SJohn Forte typedef struct nvram_24xx { 245fcf3ce44SJohn Forte /* NVRAM header. */ 246fcf3ce44SJohn Forte uint8_t id[4]; 247fcf3ce44SJohn Forte uint8_t nvram_version[2]; 248fcf3ce44SJohn Forte uint8_t reserved_0[2]; 249fcf3ce44SJohn Forte 250fcf3ce44SJohn Forte /* Firmware Initialization Control Block. */ 251fcf3ce44SJohn Forte uint8_t version[2]; 252fcf3ce44SJohn Forte uint8_t reserved_1[2]; 253fcf3ce44SJohn Forte uint8_t max_frame_length[2]; 254fcf3ce44SJohn Forte uint8_t execution_throttle[2]; 255fcf3ce44SJohn Forte uint8_t exchange_count[2]; 256fcf3ce44SJohn Forte uint8_t hard_address[2]; 257fcf3ce44SJohn Forte uint8_t port_name[8]; 258fcf3ce44SJohn Forte uint8_t node_name[8]; 259fcf3ce44SJohn Forte uint8_t login_retry_count[2]; 260fcf3ce44SJohn Forte uint8_t link_down_on_nos[2]; 261fcf3ce44SJohn Forte uint8_t interrupt_delay_timer[2]; 262fcf3ce44SJohn Forte uint8_t login_timeout[2]; 263fcf3ce44SJohn Forte 264fcf3ce44SJohn Forte /* 265fcf3ce44SJohn Forte * BIT 0 = Hard Assigned Loop ID 266fcf3ce44SJohn Forte * BIT 1 = Enable Fairness 267fcf3ce44SJohn Forte * BIT 2 = Enable Full-Duplex 268fcf3ce44SJohn Forte * BIT 3 = Reserved 269fcf3ce44SJohn Forte * BIT 4 = Target Mode Enable 270fcf3ce44SJohn Forte * BIT 5 = Initiator Mode Disable 271fcf3ce44SJohn Forte * BIT 6 = Reserved 272fcf3ce44SJohn Forte * BIT 7 = Reserved 273fcf3ce44SJohn Forte * 274fcf3ce44SJohn Forte * BIT 8 = Reserved 275fcf3ce44SJohn Forte * BIT 9 = Disable Initial LIP 276fcf3ce44SJohn Forte * BIT 10 = Descending Loop ID Search 277fcf3ce44SJohn Forte * BIT 11 = Previous Assigned Loop ID 278fcf3ce44SJohn Forte * BIT 12 = Reserved 279fcf3ce44SJohn Forte * BIT 13 = Full Login after LIP 280fcf3ce44SJohn Forte * BIT 14 = Node Name Option 2815dfd244aSDaniel Beauregard * BIT 15 = Reserved 2825dfd244aSDaniel Beauregard * 2835dfd244aSDaniel Beauregard * BIT 16-31 = Reserved 284fcf3ce44SJohn Forte */ 285fcf3ce44SJohn Forte uint8_t firmware_options_1[4]; 286fcf3ce44SJohn Forte 287fcf3ce44SJohn Forte /* 288fcf3ce44SJohn Forte * BIT 0 = Operation Mode bit 0 289fcf3ce44SJohn Forte * BIT 1 = Operation Mode bit 1 290fcf3ce44SJohn Forte * BIT 2 = Operation Mode bit 2 291fcf3ce44SJohn Forte * BIT 3 = Operation Mode bit 3 292fcf3ce44SJohn Forte * BIT 4 = Connection Options bit 0 293fcf3ce44SJohn Forte * BIT 5 = Connection Options bit 1 294fcf3ce44SJohn Forte * BIT 6 = Connection Options bit 2 295fcf3ce44SJohn Forte * BIT 7 = Enable Non part on LIHA failure 296fcf3ce44SJohn Forte * 297fcf3ce44SJohn Forte * BIT 8 = Enable Class 2 298fcf3ce44SJohn Forte * BIT 9 = Enable ACK0 2995dfd244aSDaniel Beauregard * BIT 10 = Enable Virtual Fabric 300fcf3ce44SJohn Forte * BIT 11 = Enable FC-SP Security 301fcf3ce44SJohn Forte * BIT 12 = FC Tape Enable 3025dfd244aSDaniel Beauregard * BIT 13 = Reserved 3035dfd244aSDaniel Beauregard * BIT 14 = Target PRLI Control 3045dfd244aSDaniel Beauregard * BIT 15 = Reserved 3055dfd244aSDaniel Beauregard * 3065dfd244aSDaniel Beauregard * BIT 16 = Enable Emulated MSIX 3075dfd244aSDaniel Beauregard * BIT 17 = Reserved 3085dfd244aSDaniel Beauregard * BIT 18 = Enable Alternate Device Number 3095dfd244aSDaniel Beauregard * BIT 19 = Enable Alternate Bus Number 3105dfd244aSDaniel Beauregard * BIT 20 = Enable Translated Address 3115dfd244aSDaniel Beauregard * BIT 21 = Enable VM Security 3125dfd244aSDaniel Beauregard * BIT 22 = Enable Interrupt Handshake 3135dfd244aSDaniel Beauregard * BIT 23 = Enable Multiple Queue 3145dfd244aSDaniel Beauregard * 3155dfd244aSDaniel Beauregard * BIT 24 = IOCB Security 3165dfd244aSDaniel Beauregard * BIT 25 = qos 3175dfd244aSDaniel Beauregard * BIT 26-31 = Reserved 318fcf3ce44SJohn Forte */ 319fcf3ce44SJohn Forte uint8_t firmware_options_2[4]; 320fcf3ce44SJohn Forte 321fcf3ce44SJohn Forte /* 322fcf3ce44SJohn Forte * BIT 0 = Reserved 323fcf3ce44SJohn Forte * BIT 1 = Soft ID only 324fcf3ce44SJohn Forte * BIT 2 = Reserved 3255dfd244aSDaniel Beauregard * BIT 3 = disable split completion timeout 326fcf3ce44SJohn Forte * BIT 4 = FCP RSP Payload bit 0 327fcf3ce44SJohn Forte * BIT 5 = FCP RSP Payload bit 1 328fcf3ce44SJohn Forte * BIT 6 = Enable Rec Out-of-Order data frame handling 329fcf3ce44SJohn Forte * BIT 7 = Disable Automatic PLOGI on Local Loop 330fcf3ce44SJohn Forte * 331fcf3ce44SJohn Forte * BIT 8 = Reserved 332fcf3ce44SJohn Forte * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 333fcf3ce44SJohn Forte * offset handling 334fcf3ce44SJohn Forte * BIT 10 = Reserved 335fcf3ce44SJohn Forte * BIT 11 = Reserved 336fcf3ce44SJohn Forte * BIT 12 = Reserved 337fcf3ce44SJohn Forte * BIT 13 = Data Rate bit 0 338fcf3ce44SJohn Forte * BIT 14 = Data Rate bit 1 339fcf3ce44SJohn Forte * BIT 15 = Data Rate bit 2 3405dfd244aSDaniel Beauregard * 341fcf3ce44SJohn Forte * BIT 16 = 75-ohm Termination Select 3425dfd244aSDaniel Beauregard * BIT 17 = Enable Multiple FCFs 3435dfd244aSDaniel Beauregard * BIT 18 = MAC Addressing Mode 3445dfd244aSDaniel Beauregard * BIT 19 = MAC Addressing Mode 3455dfd244aSDaniel Beauregard * BIT 20 = MAC Addressing Mode 3465dfd244aSDaniel Beauregard * BIT 21 = Ethernet Data Rate 3475dfd244aSDaniel Beauregard * BIT 22 = Ethernet Data Rate 3485dfd244aSDaniel Beauregard * BIT 23 = Ethernet Data Rate 3495dfd244aSDaniel Beauregard * 3505dfd244aSDaniel Beauregard * BIT 24 = Ethernet Data Rate 3515dfd244aSDaniel Beauregard * BIT 25 = Ethernet Data Rate 3525dfd244aSDaniel Beauregard * BIT 26 = Enable Ethernet Header ATIO Queue 3535dfd244aSDaniel Beauregard * BIT 27 = Enable Ethernet Header Response Queue 3545dfd244aSDaniel Beauregard * BIT 28 = SPMA Selection 3555dfd244aSDaniel Beauregard * BIT 29 = SPMA Selection 3565dfd244aSDaniel Beauregard * BIT 30 = Reserved 3575dfd244aSDaniel Beauregard * BIT 31 = Reserved 358fcf3ce44SJohn Forte */ 359fcf3ce44SJohn Forte uint8_t firmware_options_3[4]; 360fcf3ce44SJohn Forte 3615dfd244aSDaniel Beauregard union { 3625dfd244aSDaniel Beauregard struct { 3635dfd244aSDaniel Beauregard /* 3645dfd244aSDaniel Beauregard * Offset 56 (38h) 3655dfd244aSDaniel Beauregard * Serial Link Control 3665dfd244aSDaniel Beauregard * BIT 0 = control enable 3675dfd244aSDaniel Beauregard * BIT 1-15 = Reserved 3685dfd244aSDaniel Beauregard */ 3695dfd244aSDaniel Beauregard uint8_t swing_opt[2]; 3705dfd244aSDaniel Beauregard /* 3715dfd244aSDaniel Beauregard * Offset 58 (3Ah) 3725dfd244aSDaniel Beauregard * Serial Link Control 1G 3735dfd244aSDaniel Beauregard * BIT 0-7 = Reserved 3745dfd244aSDaniel Beauregard * 3755dfd244aSDaniel Beauregard * BIT 8-10 = output swing 3765dfd244aSDaniel Beauregard * BIT 11-13 = output emphasis 3775dfd244aSDaniel Beauregard * BIT 14-15 = Reserved 3785dfd244aSDaniel Beauregard */ 3795dfd244aSDaniel Beauregard uint8_t swing_1g[2]; 3805dfd244aSDaniel Beauregard /* 3815dfd244aSDaniel Beauregard * Offset 60 (3Ch) 3825dfd244aSDaniel Beauregard * Serial Link Control 2G 3835dfd244aSDaniel Beauregard * BIT 0-7 = Reserved 3845dfd244aSDaniel Beauregard * 3855dfd244aSDaniel Beauregard * BIT 8-10 = output swing 3865dfd244aSDaniel Beauregard * BIT 11-13 = output emphasis 3875dfd244aSDaniel Beauregard * BIT 14-15 = Reserved 3885dfd244aSDaniel Beauregard */ 3895dfd244aSDaniel Beauregard uint8_t swing_2g[2]; 3905dfd244aSDaniel Beauregard /* 3915dfd244aSDaniel Beauregard * Offset 62 (3Eh) 3925dfd244aSDaniel Beauregard * Serial Link Control 4G 3935dfd244aSDaniel Beauregard * BIT 0-7 = Reserved 3945dfd244aSDaniel Beauregard * 3955dfd244aSDaniel Beauregard * BIT 8-10 = output swing 3965dfd244aSDaniel Beauregard * BIT 11-13 = output emphasis 3975dfd244aSDaniel Beauregard * BIT 14-15 = Reserved 3985dfd244aSDaniel Beauregard */ 3995dfd244aSDaniel Beauregard uint8_t swing_4g[2]; 4005dfd244aSDaniel Beauregard 4015dfd244aSDaniel Beauregard /* Offset 64 (40h). */ 4025dfd244aSDaniel Beauregard uint8_t reserved[32]; 4035dfd244aSDaniel Beauregard } isp2400; 4045dfd244aSDaniel Beauregard struct { 4055dfd244aSDaniel Beauregard /* 4065dfd244aSDaniel Beauregard * Offset 56 (38h) 4075dfd244aSDaniel Beauregard * Serial Link Control 4085dfd244aSDaniel Beauregard * BIT 0 = Reserved 4095dfd244aSDaniel Beauregard * BIT 1 = 25xx TX control enable 4105dfd244aSDaniel Beauregard * BIT 2 = 25xx RX control enable (lmtg) 4115dfd244aSDaniel Beauregard * BIT 3 = 25xx RX control enable (linear) 4125dfd244aSDaniel Beauregard * BIT 4 = embedded HBA 4135dfd244aSDaniel Beauregard * BIT 5 = unused 4145dfd244aSDaniel Beauregard * BIT 6 = 25xx E7 Addr27 Preset 4155dfd244aSDaniel Beauregard * BIT 7 = 25xx E6 Addr0 Ch0 enable 4165dfd244aSDaniel Beauregard * 4175dfd244aSDaniel Beauregard * BIT 8-15 = 25xx E6 Addr0 Ch0 4185dfd244aSDaniel Beauregard * 4195dfd244aSDaniel Beauregard * BIT 16-31 = Reserved 4205dfd244aSDaniel Beauregard */ 4215dfd244aSDaniel Beauregard uint8_t swing_opt[4]; 4225dfd244aSDaniel Beauregard 4235dfd244aSDaniel Beauregard /* 4245dfd244aSDaniel Beauregard * Offset 60 (3Ch) 4255dfd244aSDaniel Beauregard * Serial Link TX Parameters 4265dfd244aSDaniel Beauregard * BIT 0 = TX Amplitude 4275dfd244aSDaniel Beauregard * BIT 1 = TX Amplitude 4285dfd244aSDaniel Beauregard * BIT 2 = TX Amplitude 4295dfd244aSDaniel Beauregard * BIT 3 = TX Amplitude 4305dfd244aSDaniel Beauregard * BIT 4 = TX Amplitude 4315dfd244aSDaniel Beauregard * BIT 5 = TX iPost 4325dfd244aSDaniel Beauregard * BIT 6 = TX iPost 4335dfd244aSDaniel Beauregard * BIT 7 = TX iPost 4345dfd244aSDaniel Beauregard * 4355dfd244aSDaniel Beauregard * BIT 8 = TX iPost 4365dfd244aSDaniel Beauregard * BIT 9 = TX iPre 4375dfd244aSDaniel Beauregard * BIT 10 = TX iPre 4385dfd244aSDaniel Beauregard * BIT 11 = TX iPre 4395dfd244aSDaniel Beauregard * BIT 12 = TX iPre 4405dfd244aSDaniel Beauregard * BIT 13 = TX iMain 4415dfd244aSDaniel Beauregard * BIT 14 = TX iMain 4425dfd244aSDaniel Beauregard * BIT 15 = TX iMain 4435dfd244aSDaniel Beauregard * 4445dfd244aSDaniel Beauregard * BIT 16 = TX iMain 4455dfd244aSDaniel Beauregard * BIT 17 = TX iMain 4465dfd244aSDaniel Beauregard * BIT 18-23 = Reserved 4475dfd244aSDaniel Beauregard * 4485dfd244aSDaniel Beauregard * BIT 24-31 = Reserved 4495dfd244aSDaniel Beauregard */ 4505dfd244aSDaniel Beauregard uint8_t tx_8g[4]; 4515dfd244aSDaniel Beauregard /* Offset 64 (40h) */ 4525dfd244aSDaniel Beauregard uint8_t tx_4g[4]; 4535dfd244aSDaniel Beauregard /* Offset 68 (44h) */ 4545dfd244aSDaniel Beauregard uint8_t tx_2g[4]; 4555dfd244aSDaniel Beauregard 4565dfd244aSDaniel Beauregard /* 4575dfd244aSDaniel Beauregard * Offset 72 (48h) 4585dfd244aSDaniel Beauregard * Serial Link RX Parameters 4595dfd244aSDaniel Beauregard * BIT 0 = RX Z1Cnt 4605dfd244aSDaniel Beauregard * BIT 1 = RX Z1Cnt 4615dfd244aSDaniel Beauregard * BIT 2 = RX Z1Cnt 4625dfd244aSDaniel Beauregard * BIT 3 = RX Z1Cnt 4635dfd244aSDaniel Beauregard * BIT 4 = RX G1Cnt 4645dfd244aSDaniel Beauregard * BIT 5 = RX ZCnt 4655dfd244aSDaniel Beauregard * BIT 6 = RX ZCnt 4665dfd244aSDaniel Beauregard * BIT 7 = RX ZCnt 4675dfd244aSDaniel Beauregard * 4685dfd244aSDaniel Beauregard * BIT 8 = RX ZCnt 4695dfd244aSDaniel Beauregard * BIT 9 = RX ZCnt 4705dfd244aSDaniel Beauregard * BIT 10 = RX TLTH 4715dfd244aSDaniel Beauregard * BIT 11 = RX TLTH 4725dfd244aSDaniel Beauregard * BIT 12 = RX TLTH 4735dfd244aSDaniel Beauregard * BIT 13 = RX TLTH 4745dfd244aSDaniel Beauregard * BIT 14 = RX TLTH 4755dfd244aSDaniel Beauregard * BIT 15 = RX TLTH 4765dfd244aSDaniel Beauregard * 4775dfd244aSDaniel Beauregard * BIT 16 = RX DFELTH 4785dfd244aSDaniel Beauregard * BIT 17 = RX DFELTH 4795dfd244aSDaniel Beauregard * BIT 18 = RX DFELTH 4805dfd244aSDaniel Beauregard * BIT 19 = RX DFELTH 4815dfd244aSDaniel Beauregard * BIT 20 = RX DFELTH 4825dfd244aSDaniel Beauregard * BIT 21 = RX DFELTH 4835dfd244aSDaniel Beauregard * BIT 22-23 = Reserved 4845dfd244aSDaniel Beauregard * 4855dfd244aSDaniel Beauregard * BIT 24-31 = Reserved 4865dfd244aSDaniel Beauregard */ 4875dfd244aSDaniel Beauregard uint8_t rx_limit_8g[4]; 4885dfd244aSDaniel Beauregard /* Offset 76 (4Ch) */ 4895dfd244aSDaniel Beauregard uint8_t rx_limit_4g[4]; 4905dfd244aSDaniel Beauregard /* Offset 80 (50h) */ 4915dfd244aSDaniel Beauregard uint8_t rx_limit_2g[4]; 4925dfd244aSDaniel Beauregard /* Offset 84 (54h) */ 4935dfd244aSDaniel Beauregard uint8_t rx_linear_8g[4]; 4945dfd244aSDaniel Beauregard /* Offset 88 (58h) */ 4955dfd244aSDaniel Beauregard uint8_t rx_linear_4g[4]; 4965dfd244aSDaniel Beauregard /* Offset 92 (5Ch) */ 4975dfd244aSDaniel Beauregard uint8_t rx_linear_2g[4]; 4985dfd244aSDaniel Beauregard } isp2500; 4995dfd244aSDaniel Beauregard struct { 5005dfd244aSDaniel Beauregard /* Offset 56 (38h) */ 5015dfd244aSDaniel Beauregard uint8_t reserved[8]; 5025dfd244aSDaniel Beauregard 5035dfd244aSDaniel Beauregard /* Offset 64 (40h). */ 5045dfd244aSDaniel Beauregard uint8_t e_node_mac_addr[6]; 5055dfd244aSDaniel Beauregard 5065dfd244aSDaniel Beauregard /* Offset 70 (46h). */ 5075dfd244aSDaniel Beauregard uint8_t reserved2[26]; 5085dfd244aSDaniel Beauregard } isp8001; 5095dfd244aSDaniel Beauregard } fw; 510fcf3ce44SJohn Forte 511fcf3ce44SJohn Forte /* 5125dfd244aSDaniel Beauregard * Offset 96 (60h) 5135dfd244aSDaniel Beauregard * BIT 0 = initiator op 5145dfd244aSDaniel Beauregard * BIT 1 = target op 5155dfd244aSDaniel Beauregard * BIT 2 = VI op 5165dfd244aSDaniel Beauregard * BIT 3-7 = Reserved 517fcf3ce44SJohn Forte */ 5185dfd244aSDaniel Beauregard uint8_t oem_specific; 5195dfd244aSDaniel Beauregard uint8_t reserved_4[15]; 520fcf3ce44SJohn Forte 521*4c3888b8SHans Rosenfeld /* 522*4c3888b8SHans Rosenfeld * Offset 112 (70h). 523*4c3888b8SHans Rosenfeld * BIT 0 = additional receive credits 524*4c3888b8SHans Rosenfeld * BIT 1 = additional receive credits 525*4c3888b8SHans Rosenfeld * BIT 2-15 = Reserved 526*4c3888b8SHans Rosenfeld */ 527*4c3888b8SHans Rosenfeld uint8_t execute_fw_options[2]; 528*4c3888b8SHans Rosenfeld uint8_t reserved_5[14]; 529fcf3ce44SJohn Forte 530fcf3ce44SJohn Forte /* 5315dfd244aSDaniel Beauregard * Offset 128 (80h). 5325dfd244aSDaniel Beauregard * PCIe table entries. 5335dfd244aSDaniel Beauregard * Firmware Extended Initialization Control Block. 534fcf3ce44SJohn Forte */ 5355dfd244aSDaniel Beauregard ql_ext_icb_8100_t ext_blk; 536fcf3ce44SJohn Forte 537fcf3ce44SJohn Forte /* Offset 192. */ 538fcf3ce44SJohn Forte uint8_t reserved_6[32]; 539fcf3ce44SJohn Forte 540fcf3ce44SJohn Forte /* Offset 224. */ 541fcf3ce44SJohn Forte uint8_t reserved_7[32]; 542fcf3ce44SJohn Forte 543fcf3ce44SJohn Forte /* 544fcf3ce44SJohn Forte * BIT 0 = Enable spinup delay 545fcf3ce44SJohn Forte * BIT 1 = Disable BIOS 546fcf3ce44SJohn Forte * BIT 2 = Enable Memory Map BIOS 547fcf3ce44SJohn Forte * BIT 3 = Enable Selectable Boot 548fcf3ce44SJohn Forte * BIT 4 = Disable RISC code load 549fcf3ce44SJohn Forte * BIT 5 = Disable serdes 550fcf3ce44SJohn Forte * BIT 6 = Enable opt boot mode 551fcf3ce44SJohn Forte * BIT 7 = Enable int mode BIOS 552fcf3ce44SJohn Forte * 5535dfd244aSDaniel Beauregard * BIT 8 = EV control enable 5545dfd244aSDaniel Beauregard * BIT 9 = Enable lip reset 555fcf3ce44SJohn Forte * BIT 10 = Enable lip full login 556fcf3ce44SJohn Forte * BIT 11 = Enable target reset 5575dfd244aSDaniel Beauregard * BIT 12 = Stop firmware 558fcf3ce44SJohn Forte * BIT 13 = Default Node Name Option 5595dfd244aSDaniel Beauregard * BIT 14 = Default WWPN valid 560fcf3ce44SJohn Forte * BIT 15 = Enable alternate WWN 561fcf3ce44SJohn Forte * 5625dfd244aSDaniel Beauregard * CLP BIOS flags 5635dfd244aSDaniel Beauregard * 5645dfd244aSDaniel Beauregard * BIT 16 = clp lun string 5655dfd244aSDaniel Beauregard * BIT 17 = clp target string 5665dfd244aSDaniel Beauregard * BIT 18 = clp bios enable string 5675dfd244aSDaniel Beauregard * BIT 19 = clp serdes_string 5685dfd244aSDaniel Beauregard * BIT 20 = clp wwpn string 5695dfd244aSDaniel Beauregard * BIT 21 = clp wwnn string 5705dfd244aSDaniel Beauregard * BIT 22 = win reserverd 0 5715dfd244aSDaniel Beauregard * BIT 23 = win reserverd 1 5725dfd244aSDaniel Beauregard * 5735dfd244aSDaniel Beauregard * BIT 24 = keep wwpn 5745dfd244aSDaniel Beauregard * BIT 25 = temp wwpn 5755dfd244aSDaniel Beauregard * BIT 26 = win reserverd 2 5765dfd244aSDaniel Beauregard * BIT 27 = win reserverd 3 5775dfd244aSDaniel Beauregard * BIT 28 = clear WBT in flash (win driver) 5785dfd244aSDaniel Beauregard * BIT 29 = write WBT in flash (win driver) 5795dfd244aSDaniel Beauregard * BIT 30 = load fw from flash (win driver) 5805dfd244aSDaniel Beauregard * BIT 31 = enable alternate WWN (win driver) 581fcf3ce44SJohn Forte */ 582fcf3ce44SJohn Forte uint8_t host_p[4]; 583fcf3ce44SJohn Forte 584fcf3ce44SJohn Forte uint8_t alternate_port_name[8]; 585fcf3ce44SJohn Forte uint8_t alternate_node_name[8]; 586fcf3ce44SJohn Forte 587fcf3ce44SJohn Forte uint8_t boot_port_name[8]; 588fcf3ce44SJohn Forte uint8_t boot_lun_number[2]; 589fcf3ce44SJohn Forte uint8_t reserved_8[2]; 590fcf3ce44SJohn Forte 591fcf3ce44SJohn Forte uint8_t alt1_boot_port_name[8]; 592fcf3ce44SJohn Forte uint8_t alt1_boot_lun_number[2]; 593fcf3ce44SJohn Forte uint8_t reserved_9[2]; 594fcf3ce44SJohn Forte 595fcf3ce44SJohn Forte uint8_t alt2_boot_port_name[8]; 596fcf3ce44SJohn Forte uint8_t alt2_boot_lun_number[2]; 597fcf3ce44SJohn Forte uint8_t reserved_10[2]; 598fcf3ce44SJohn Forte 599fcf3ce44SJohn Forte uint8_t alt3_boot_port_name[8]; 600fcf3ce44SJohn Forte uint8_t alt3_boot_lun_number[2]; 601fcf3ce44SJohn Forte uint8_t reserved_11[2]; 602fcf3ce44SJohn Forte 603fcf3ce44SJohn Forte /* 604fcf3ce44SJohn Forte * BIT 0 = Selective Login 605fcf3ce44SJohn Forte * BIT 1 = Alt-Boot Enable 606fcf3ce44SJohn Forte * BIT 2 = Reserved 607fcf3ce44SJohn Forte * BIT 3 = Enable Boot Order List 608fcf3ce44SJohn Forte * BIT 4 = Reserved 609fcf3ce44SJohn Forte * BIT 5 = Enable Selective LUN 610fcf3ce44SJohn Forte * BIT 6 = Reserved 611fcf3ce44SJohn Forte * BIT 7-31 = 612fcf3ce44SJohn Forte */ 613fcf3ce44SJohn Forte uint8_t efi_parameters[4]; 614fcf3ce44SJohn Forte 615fcf3ce44SJohn Forte uint8_t reset_delay; 616fcf3ce44SJohn Forte uint8_t reserved_12; 617fcf3ce44SJohn Forte uint8_t reserved_13[2]; 618fcf3ce44SJohn Forte 619fcf3ce44SJohn Forte uint8_t boot_id_number[2]; 620fcf3ce44SJohn Forte uint8_t reserved_14[2]; 621fcf3ce44SJohn Forte 622fcf3ce44SJohn Forte uint8_t max_luns_per_target[2]; 623fcf3ce44SJohn Forte uint8_t reserved_15[2]; 624fcf3ce44SJohn Forte 625fcf3ce44SJohn Forte uint8_t port_down_retry_count[2]; 626fcf3ce44SJohn Forte uint8_t link_down_timeout[2]; 627fcf3ce44SJohn Forte 628fcf3ce44SJohn Forte /* 629fcf3ce44SJohn Forte * FCode parameters word (offset 344) 630fcf3ce44SJohn Forte * 631fcf3ce44SJohn Forte * BIT 0 = Enable BIOS pathname 632fcf3ce44SJohn Forte * BIT 1 = fcode qlc 633fcf3ce44SJohn Forte * BIT 2 = fcode host 6345dfd244aSDaniel Beauregard * BIT 3 = fcode sunid 6355dfd244aSDaniel Beauregard * BIT 4-7 = 636fcf3ce44SJohn Forte */ 637fcf3ce44SJohn Forte uint8_t fcode_p0; 638fcf3ce44SJohn Forte uint8_t reserved_16[7]; 639fcf3ce44SJohn Forte 6405dfd244aSDaniel Beauregard /* 6415dfd244aSDaniel Beauregard * Offset 352 (160h). 6425dfd244aSDaniel Beauregard * uint8_t prev_drv_ver_major; 6435dfd244aSDaniel Beauregard * uint8_t prev_drv_ver_submajob; 6445dfd244aSDaniel Beauregard * uint8_t prev_drv_ver_minor; 6455dfd244aSDaniel Beauregard * uint8_t prev_drv_ver_subminor; 6465dfd244aSDaniel Beauregard * uint8_t prev_bios_ver_major[2]; 6475dfd244aSDaniel Beauregard * uint8_t prev_bios_ver_minor[2]; 6485dfd244aSDaniel Beauregard * uint8_t prev_efi_ver_major[2]; 6495dfd244aSDaniel Beauregard * uint8_t prev_efi_ver_minor[2]; 6505dfd244aSDaniel Beauregard * uint8_t prev_fw_ver_major[2]; 6515dfd244aSDaniel Beauregard * uint8_t prev_fw_ver_minor; 6525dfd244aSDaniel Beauregard * uint8_t prev_fw_ver_subminor; 6535dfd244aSDaniel Beauregard * uint8_t reserved[16]; 6545dfd244aSDaniel Beauregard */ 6555dfd244aSDaniel Beauregard uint8_t mac_address[6]; 6565dfd244aSDaniel Beauregard uint8_t clp_flag[2]; 6575dfd244aSDaniel Beauregard uint8_t reserved_18[24]; 658fcf3ce44SJohn Forte 6595dfd244aSDaniel Beauregard /* Offset 384 (180h). */ 6605dfd244aSDaniel Beauregard uint8_t def_port_name[8]; 6615dfd244aSDaniel Beauregard uint8_t def_node_name[8]; 6625dfd244aSDaniel Beauregard uint8_t clp_flag1[2]; 6635dfd244aSDaniel Beauregard uint8_t clp_flag2[2]; 664fcf3ce44SJohn Forte 6655dfd244aSDaniel Beauregard /* Offset 404 (194h). */ 6665dfd244aSDaniel Beauregard uint8_t default_firmware_options[2]; 667fcf3ce44SJohn Forte 6685dfd244aSDaniel Beauregard /* Offset 406 (196h). */ 6695dfd244aSDaniel Beauregard uint8_t enhanced_features[2]; 6705dfd244aSDaniel Beauregard uint8_t serdes_index[2]; 6715dfd244aSDaniel Beauregard uint8_t reserved_19[6]; 672fcf3ce44SJohn Forte 6735dfd244aSDaniel Beauregard /* Offset 416 (1A0h). */ 6745dfd244aSDaniel Beauregard uint8_t alt4_boot_port_name[8]; 6755dfd244aSDaniel Beauregard uint8_t alt4_boot_lun_number[2]; 6765dfd244aSDaniel Beauregard uint8_t reserved_20[2]; 677fcf3ce44SJohn Forte 6785dfd244aSDaniel Beauregard /* Offset 428 (1ACh). */ 6795dfd244aSDaniel Beauregard uint8_t alt5_boot_port_name[8]; 6805dfd244aSDaniel Beauregard uint8_t alt5_boot_lun_number[2]; 6815dfd244aSDaniel Beauregard uint8_t reserved_21[2]; 682fcf3ce44SJohn Forte 6835dfd244aSDaniel Beauregard /* Offset 440 (1B8h). */ 6845dfd244aSDaniel Beauregard uint8_t alt6_boot_port_name[8]; 6855dfd244aSDaniel Beauregard uint8_t alt6_boot_lun_number[2]; 6865dfd244aSDaniel Beauregard uint8_t reserved_22[2]; 687fcf3ce44SJohn Forte 6885dfd244aSDaniel Beauregard /* Offset 452 (1C4h). */ 6895dfd244aSDaniel Beauregard uint8_t alt7_boot_port_name[8]; 6905dfd244aSDaniel Beauregard uint8_t alt7_boot_lun_number[2]; 6915dfd244aSDaniel Beauregard uint8_t reserved_23[2]; 692fcf3ce44SJohn Forte 6935dfd244aSDaniel Beauregard /* Offset 464 (1D0h). */ 6945dfd244aSDaniel Beauregard uint8_t reserved_24[12]; 695fcf3ce44SJohn Forte 6965dfd244aSDaniel Beauregard /* Offset 476 (1DCh). */ 697fcf3ce44SJohn Forte uint8_t fw_table_offset[2]; 698fcf3ce44SJohn Forte uint8_t fw_table_sig[2]; 699fcf3ce44SJohn Forte 7005dfd244aSDaniel Beauregard /* Offset 480 (1E0h). */ 701*4c3888b8SHans Rosenfeld int8_t model_name[4]; 702*4c3888b8SHans Rosenfeld int8_t model_name1[12]; /* 24xx power_table[8]. */ 703fcf3ce44SJohn Forte 7045dfd244aSDaniel Beauregard /* Offset 496 (1F0h). */ 7055dfd244aSDaniel Beauregard uint8_t feature_mask_l[2]; 7065dfd244aSDaniel Beauregard uint8_t feature_mask_h[2]; 7075dfd244aSDaniel Beauregard uint8_t reserved_25[4]; 708fcf3ce44SJohn Forte 7095dfd244aSDaniel Beauregard /* Offset 504 (1F8h). */ 710fcf3ce44SJohn Forte uint8_t subsystem_vendor_id[2]; 711fcf3ce44SJohn Forte uint8_t subsystem_device_id[2]; 712fcf3ce44SJohn Forte 713fcf3ce44SJohn Forte uint8_t checksum[4]; 714fcf3ce44SJohn Forte } nvram_24xx_t; 715fcf3ce44SJohn Forte 716fcf3ce44SJohn Forte /* 717fcf3ce44SJohn Forte * Firmware Dump structure definition 718fcf3ce44SJohn Forte */ 719*4c3888b8SHans Rosenfeld #define QL_2200_FW_DUMP_SIZE 0x100000 /* 86e15 bytes */ 720*4c3888b8SHans Rosenfeld #define QL_2300_FW_DUMP_SIZE 0x100000 /* fc6d3 bytes */ 721*4c3888b8SHans Rosenfeld #define QL_6322_FW_DUMP_SIZE 0x100000 /* fc6d8 bytes */ 722*4c3888b8SHans Rosenfeld #define QL_24XX_FW_DUMP_SIZE 0x300000 /* 2cef71 bytes */ 723*4c3888b8SHans Rosenfeld #define QL_25XX_FW_DUMP_SIZE 0x400000 /* 356c97 bytes */ 724*4c3888b8SHans Rosenfeld #define QL_81XX_FW_DUMP_SIZE 0x400000 /* 356c97 bytes */ 725*4c3888b8SHans Rosenfeld #define QL_27XX_FW_DUMP_SIZE 0x600000 /* 5c3e69 bytes */ 726*4c3888b8SHans Rosenfeld #define QL_83XX_FW_DUMP_SIZE 0x400000 /* 372792 bytes */ 727fcf3ce44SJohn Forte 728fcf3ce44SJohn Forte #define QL_24XX_VPD_SIZE 0x200 /* bytes */ 729fcf3ce44SJohn Forte #define QL_24XX_SFP_SIZE 0x200 /* bytes */ 730fcf3ce44SJohn Forte 731fcf3ce44SJohn Forte /* 732fcf3ce44SJohn Forte * firmware dump struct for 2300 is a superset of firmware dump struct 733fcf3ce44SJohn Forte * for 2200. Fields which are 2300 only or are enhanced for 2300 are 734fcf3ce44SJohn Forte * marked below. 735fcf3ce44SJohn Forte */ 736fcf3ce44SJohn Forte typedef struct ql_fw_dump { 737fcf3ce44SJohn Forte uint16_t pbiu_reg[8]; 738fcf3ce44SJohn Forte uint16_t risc_host_reg[8]; /* 2300 only. */ 739fcf3ce44SJohn Forte uint16_t mailbox_reg[16]; /* 2200 only needs 8 */ 740fcf3ce44SJohn Forte uint16_t resp_dma_reg[32]; /* 2300 only. */ 741fcf3ce44SJohn Forte uint16_t dma_reg[48]; 742fcf3ce44SJohn Forte uint16_t risc_hdw_reg[16]; 743fcf3ce44SJohn Forte uint16_t risc_gp0_reg[16]; 744fcf3ce44SJohn Forte uint16_t risc_gp1_reg[16]; 745fcf3ce44SJohn Forte uint16_t risc_gp2_reg[16]; 746fcf3ce44SJohn Forte uint16_t risc_gp3_reg[16]; 747fcf3ce44SJohn Forte uint16_t risc_gp4_reg[16]; 748fcf3ce44SJohn Forte uint16_t risc_gp5_reg[16]; 749fcf3ce44SJohn Forte uint16_t risc_gp6_reg[16]; 750fcf3ce44SJohn Forte uint16_t risc_gp7_reg[16]; 751fcf3ce44SJohn Forte uint16_t frame_buf_hdw_reg[64]; /* 2200 has only 16 */ 752fcf3ce44SJohn Forte uint16_t fpm_b0_reg[64]; 753fcf3ce44SJohn Forte uint16_t fpm_b1_reg[64]; 754fcf3ce44SJohn Forte uint16_t risc_ram[0xf800]; /* 2200 needs only 0xf000 */ 755fcf3ce44SJohn Forte uint16_t stack_ram[0x800]; /* 2300 only */ 756fcf3ce44SJohn Forte uint16_t data_ram[0xf800]; /* 2300 only */ 75716dd44c2SDaniel Beauregard uint32_t req_q[REQUEST_QUEUE_SIZE / 4]; 75816dd44c2SDaniel Beauregard uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4]; 759fcf3ce44SJohn Forte } ql_fw_dump_t; 760fcf3ce44SJohn Forte 761fcf3ce44SJohn Forte typedef struct ql_24xx_fw_dump { 762fcf3ce44SJohn Forte uint32_t hccr; 763fcf3ce44SJohn Forte uint32_t host_reg[32]; 764fcf3ce44SJohn Forte uint16_t mailbox_reg[32]; 765fcf3ce44SJohn Forte uint32_t xseq_gp_reg[128]; 766fcf3ce44SJohn Forte uint32_t xseq_0_reg[16]; 767fcf3ce44SJohn Forte uint32_t xseq_1_reg[16]; 768fcf3ce44SJohn Forte uint32_t rseq_gp_reg[128]; 769fcf3ce44SJohn Forte uint32_t rseq_0_reg[16]; 770fcf3ce44SJohn Forte uint32_t rseq_1_reg[16]; 771fcf3ce44SJohn Forte uint32_t rseq_2_reg[16]; 772fcf3ce44SJohn Forte uint32_t cmd_dma_reg[16]; 773fcf3ce44SJohn Forte uint32_t req0_dma_reg[15]; 774fcf3ce44SJohn Forte uint32_t resp0_dma_reg[15]; 775fcf3ce44SJohn Forte uint32_t req1_dma_reg[15]; 776fcf3ce44SJohn Forte uint32_t xmt0_dma_reg[32]; 777fcf3ce44SJohn Forte uint32_t xmt1_dma_reg[32]; 778fcf3ce44SJohn Forte uint32_t xmt2_dma_reg[32]; 779fcf3ce44SJohn Forte uint32_t xmt3_dma_reg[32]; 780fcf3ce44SJohn Forte uint32_t xmt4_dma_reg[32]; 781fcf3ce44SJohn Forte uint32_t xmt_data_dma_reg[16]; 782fcf3ce44SJohn Forte uint32_t rcvt0_data_dma_reg[32]; 783fcf3ce44SJohn Forte uint32_t rcvt1_data_dma_reg[32]; 784fcf3ce44SJohn Forte uint32_t risc_gp_reg[128]; 785fcf3ce44SJohn Forte uint32_t shadow_reg[7]; 786fcf3ce44SJohn Forte uint32_t lmc_reg[112]; 787fcf3ce44SJohn Forte uint32_t fpm_hdw_reg[192]; 788fcf3ce44SJohn Forte uint32_t fb_hdw_reg[176]; 789fcf3ce44SJohn Forte uint32_t code_ram[0x2000]; 79016dd44c2SDaniel Beauregard uint32_t req_q[REQUEST_QUEUE_SIZE / 4]; 79116dd44c2SDaniel Beauregard uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4]; 79216dd44c2SDaniel Beauregard uint32_t ext_trace_buf[FWEXTSIZE / 4]; 79316dd44c2SDaniel Beauregard uint32_t fce_trace_buf[FWFCESIZE / 4]; 794fcf3ce44SJohn Forte uint32_t ext_mem[1]; 795fcf3ce44SJohn Forte } ql_24xx_fw_dump_t; 796fcf3ce44SJohn Forte 797fcf3ce44SJohn Forte typedef struct ql_25xx_fw_dump { 798*4c3888b8SHans Rosenfeld uint32_t hccr; 799fcf3ce44SJohn Forte uint32_t r2h_status; 800*4c3888b8SHans Rosenfeld uint32_t aer_ues; 801fcf3ce44SJohn Forte uint32_t hostrisc_reg[32]; 802fcf3ce44SJohn Forte uint32_t pcie_reg[4]; 803fcf3ce44SJohn Forte uint32_t host_reg[32]; 804fcf3ce44SJohn Forte uint16_t mailbox_reg[32]; 805fcf3ce44SJohn Forte uint32_t xseq_gp_reg[128]; 806fcf3ce44SJohn Forte uint32_t xseq_0_reg[48]; 807fcf3ce44SJohn Forte uint32_t xseq_1_reg[16]; 808fcf3ce44SJohn Forte uint32_t rseq_gp_reg[128]; 809fcf3ce44SJohn Forte uint32_t rseq_0_reg[32]; 810fcf3ce44SJohn Forte uint32_t rseq_1_reg[16]; 811fcf3ce44SJohn Forte uint32_t rseq_2_reg[16]; 812fcf3ce44SJohn Forte uint32_t aseq_gp_reg[128]; 813fcf3ce44SJohn Forte uint32_t aseq_0_reg[32]; 814fcf3ce44SJohn Forte uint32_t aseq_1_reg[16]; 815fcf3ce44SJohn Forte uint32_t aseq_2_reg[16]; 816fcf3ce44SJohn Forte uint32_t cmd_dma_reg[16]; 817fcf3ce44SJohn Forte uint32_t req0_dma_reg[15]; 818fcf3ce44SJohn Forte uint32_t resp0_dma_reg[15]; 819fcf3ce44SJohn Forte uint32_t req1_dma_reg[15]; 820fcf3ce44SJohn Forte uint32_t xmt0_dma_reg[32]; 821fcf3ce44SJohn Forte uint32_t xmt1_dma_reg[32]; 822fcf3ce44SJohn Forte uint32_t xmt2_dma_reg[32]; 823fcf3ce44SJohn Forte uint32_t xmt3_dma_reg[32]; 824fcf3ce44SJohn Forte uint32_t xmt4_dma_reg[32]; 825fcf3ce44SJohn Forte uint32_t xmt_data_dma_reg[16]; 826fcf3ce44SJohn Forte uint32_t rcvt0_data_dma_reg[32]; 827fcf3ce44SJohn Forte uint32_t rcvt1_data_dma_reg[32]; 828fcf3ce44SJohn Forte uint32_t risc_gp_reg[128]; 829fcf3ce44SJohn Forte uint32_t shadow_reg[11]; 830fcf3ce44SJohn Forte uint32_t risc_io; 831fcf3ce44SJohn Forte uint32_t lmc_reg[128]; 832fcf3ce44SJohn Forte uint32_t fpm_hdw_reg[192]; 833fcf3ce44SJohn Forte uint32_t fb_hdw_reg[192]; 834fcf3ce44SJohn Forte uint32_t code_ram[0x2000]; 83516dd44c2SDaniel Beauregard uint32_t ext_trace_buf[FWEXTSIZE / 4]; 83616dd44c2SDaniel Beauregard uint32_t fce_trace_buf[FWFCESIZE / 4]; 837*4c3888b8SHans Rosenfeld uint32_t req_q_size[2]; 838*4c3888b8SHans Rosenfeld uint32_t rsp_q_size; 839*4c3888b8SHans Rosenfeld uint32_t req_rsp_ext_mem[1]; 840fcf3ce44SJohn Forte } ql_25xx_fw_dump_t; 841fcf3ce44SJohn Forte 842f33c1cdbSDaniel Beauregard typedef struct ql_81xx_fw_dump { 843*4c3888b8SHans Rosenfeld uint32_t hccr; 844f33c1cdbSDaniel Beauregard uint32_t r2h_status; 845*4c3888b8SHans Rosenfeld uint32_t aer_ues; 846f33c1cdbSDaniel Beauregard uint32_t hostrisc_reg[32]; 847f33c1cdbSDaniel Beauregard uint32_t pcie_reg[4]; 848f33c1cdbSDaniel Beauregard uint32_t host_reg[32]; 849f33c1cdbSDaniel Beauregard uint16_t mailbox_reg[32]; 850f33c1cdbSDaniel Beauregard uint32_t xseq_gp_reg[128]; 851f33c1cdbSDaniel Beauregard uint32_t xseq_0_reg[48]; 852f33c1cdbSDaniel Beauregard uint32_t xseq_1_reg[16]; 853f33c1cdbSDaniel Beauregard uint32_t rseq_gp_reg[128]; 854f33c1cdbSDaniel Beauregard uint32_t rseq_0_reg[32]; 855f33c1cdbSDaniel Beauregard uint32_t rseq_1_reg[16]; 856f33c1cdbSDaniel Beauregard uint32_t rseq_2_reg[16]; 857f33c1cdbSDaniel Beauregard uint32_t aseq_gp_reg[128]; 858f33c1cdbSDaniel Beauregard uint32_t aseq_0_reg[32]; 859f33c1cdbSDaniel Beauregard uint32_t aseq_1_reg[16]; 860f33c1cdbSDaniel Beauregard uint32_t aseq_2_reg[16]; 861f33c1cdbSDaniel Beauregard uint32_t cmd_dma_reg[16]; 862f33c1cdbSDaniel Beauregard uint32_t req0_dma_reg[15]; 863f33c1cdbSDaniel Beauregard uint32_t resp0_dma_reg[15]; 864f33c1cdbSDaniel Beauregard uint32_t req1_dma_reg[15]; 865f33c1cdbSDaniel Beauregard uint32_t xmt0_dma_reg[32]; 866f33c1cdbSDaniel Beauregard uint32_t xmt1_dma_reg[32]; 867f33c1cdbSDaniel Beauregard uint32_t xmt2_dma_reg[32]; 868f33c1cdbSDaniel Beauregard uint32_t xmt3_dma_reg[32]; 869f33c1cdbSDaniel Beauregard uint32_t xmt4_dma_reg[32]; 870f33c1cdbSDaniel Beauregard uint32_t xmt_data_dma_reg[16]; 871f33c1cdbSDaniel Beauregard uint32_t rcvt0_data_dma_reg[32]; 872f33c1cdbSDaniel Beauregard uint32_t rcvt1_data_dma_reg[32]; 873f33c1cdbSDaniel Beauregard uint32_t risc_gp_reg[128]; 874f33c1cdbSDaniel Beauregard uint32_t shadow_reg[11]; 875f33c1cdbSDaniel Beauregard uint32_t risc_io; 876f33c1cdbSDaniel Beauregard uint32_t lmc_reg[128]; 877f33c1cdbSDaniel Beauregard uint32_t fpm_hdw_reg[224]; 878f33c1cdbSDaniel Beauregard uint32_t fb_hdw_reg[208]; 879f33c1cdbSDaniel Beauregard uint32_t code_ram[0x2000]; 880f33c1cdbSDaniel Beauregard uint32_t ext_trace_buf[FWEXTSIZE / 4]; 881f33c1cdbSDaniel Beauregard uint32_t fce_trace_buf[FWFCESIZE / 4]; 882*4c3888b8SHans Rosenfeld uint32_t req_q_size[2]; 883*4c3888b8SHans Rosenfeld uint32_t rsp_q_size; 884*4c3888b8SHans Rosenfeld uint32_t req_rsp_ext_mem[1]; 885f33c1cdbSDaniel Beauregard } ql_81xx_fw_dump_t; 886f33c1cdbSDaniel Beauregard 887*4c3888b8SHans Rosenfeld typedef struct ql_83xx_fw_dump { 888*4c3888b8SHans Rosenfeld uint32_t hccr; 889*4c3888b8SHans Rosenfeld uint32_t r2h_status; 890*4c3888b8SHans Rosenfeld uint32_t aer_ues; 891*4c3888b8SHans Rosenfeld uint32_t hostrisc_reg[48]; 892*4c3888b8SHans Rosenfeld uint32_t pcie_reg[4]; 893*4c3888b8SHans Rosenfeld uint32_t host_reg[32]; 894*4c3888b8SHans Rosenfeld uint16_t mailbox_reg[32]; 895*4c3888b8SHans Rosenfeld uint32_t xseq_gp_reg[256]; 896*4c3888b8SHans Rosenfeld uint32_t xseq_0_reg[48]; 897*4c3888b8SHans Rosenfeld uint32_t xseq_1_reg[16]; 898*4c3888b8SHans Rosenfeld uint32_t xseq_2_reg[16]; 899*4c3888b8SHans Rosenfeld uint32_t rseq_gp_reg[256]; 900*4c3888b8SHans Rosenfeld uint32_t rseq_0_reg[32]; 901*4c3888b8SHans Rosenfeld uint32_t rseq_1_reg[16]; 902*4c3888b8SHans Rosenfeld uint32_t rseq_2_reg[16]; 903*4c3888b8SHans Rosenfeld uint32_t rseq_3_reg[16]; 904*4c3888b8SHans Rosenfeld uint32_t aseq_gp_reg[256]; 905*4c3888b8SHans Rosenfeld uint32_t aseq_0_reg[32]; 906*4c3888b8SHans Rosenfeld uint32_t aseq_1_reg[16]; 907*4c3888b8SHans Rosenfeld uint32_t aseq_2_reg[16]; 908*4c3888b8SHans Rosenfeld uint32_t aseq_3_reg[16]; 909*4c3888b8SHans Rosenfeld uint32_t cmd_dma_reg[64]; 910*4c3888b8SHans Rosenfeld uint32_t req0_dma_reg[15]; 911*4c3888b8SHans Rosenfeld uint32_t resp0_dma_reg[15]; 912*4c3888b8SHans Rosenfeld uint32_t req1_dma_reg[15]; 913*4c3888b8SHans Rosenfeld uint32_t xmt0_dma_reg[32]; 914*4c3888b8SHans Rosenfeld uint32_t xmt1_dma_reg[32]; 915*4c3888b8SHans Rosenfeld uint32_t xmt2_dma_reg[32]; 916*4c3888b8SHans Rosenfeld uint32_t xmt3_dma_reg[32]; 917*4c3888b8SHans Rosenfeld uint32_t xmt4_dma_reg[32]; 918*4c3888b8SHans Rosenfeld uint32_t xmt_data_dma_reg[16]; 919*4c3888b8SHans Rosenfeld uint32_t rcvt0_data_dma_reg[32]; 920*4c3888b8SHans Rosenfeld uint32_t rcvt1_data_dma_reg[32]; 921*4c3888b8SHans Rosenfeld uint32_t risc_gp_reg[128]; 922*4c3888b8SHans Rosenfeld uint32_t shadow_reg[11]; 923*4c3888b8SHans Rosenfeld uint32_t risc_io; 924*4c3888b8SHans Rosenfeld uint32_t lmc_reg[128]; 925*4c3888b8SHans Rosenfeld uint32_t fpm_hdw_reg[256]; 926*4c3888b8SHans Rosenfeld uint32_t rq0_array_reg[256]; 927*4c3888b8SHans Rosenfeld uint32_t rq1_array_reg[256]; 928*4c3888b8SHans Rosenfeld uint32_t rp0_array_reg[256]; 929*4c3888b8SHans Rosenfeld uint32_t rp1_array_reg[256]; 930*4c3888b8SHans Rosenfeld uint32_t ato_array_reg[128]; 931*4c3888b8SHans Rosenfeld uint32_t queue_control_reg[16]; 932*4c3888b8SHans Rosenfeld uint32_t fb_hdw_reg[432]; 933*4c3888b8SHans Rosenfeld uint32_t code_ram[0x2400]; 934*4c3888b8SHans Rosenfeld uint32_t ext_trace_buf[FWEXTSIZE / 4]; 935*4c3888b8SHans Rosenfeld uint32_t fce_trace_buf[FWFCESIZE / 4]; 936*4c3888b8SHans Rosenfeld uint32_t req_q_size[2]; 937*4c3888b8SHans Rosenfeld uint32_t rsp_q_size; 938*4c3888b8SHans Rosenfeld uint32_t req_rsp_ext_mem[1]; 939*4c3888b8SHans Rosenfeld } ql_83xx_fw_dump_t; 940*4c3888b8SHans Rosenfeld 941fcf3ce44SJohn Forte #ifdef _KERNEL 942fcf3ce44SJohn Forte 943*4c3888b8SHans Rosenfeld /* 944*4c3888b8SHans Rosenfeld * firmware dump Entry Types 945*4c3888b8SHans Rosenfeld */ 946*4c3888b8SHans Rosenfeld #define DT_NOP 0 947*4c3888b8SHans Rosenfeld #define DT_THDR 99 948*4c3888b8SHans Rosenfeld #define DT_TEND 255 949*4c3888b8SHans Rosenfeld #define DT_RIOB1 256 950*4c3888b8SHans Rosenfeld #define DT_WIOB1 257 951*4c3888b8SHans Rosenfeld #define DT_RIOB2 258 952*4c3888b8SHans Rosenfeld #define DT_WIOB2 259 953*4c3888b8SHans Rosenfeld #define DT_RPCI 260 954*4c3888b8SHans Rosenfeld #define DT_WPCI 261 955*4c3888b8SHans Rosenfeld #define DT_RRAM 262 956*4c3888b8SHans Rosenfeld #define DT_GQUE 263 957*4c3888b8SHans Rosenfeld #define DT_GFCE 264 958*4c3888b8SHans Rosenfeld #define DT_PRISC 265 959*4c3888b8SHans Rosenfeld #define DT_RRISC 266 960*4c3888b8SHans Rosenfeld #define DT_DINT 267 961*4c3888b8SHans Rosenfeld #define DT_GHBD 268 962*4c3888b8SHans Rosenfeld #define DT_SCRA 269 963*4c3888b8SHans Rosenfeld #define DT_RRREG 270 964*4c3888b8SHans Rosenfeld #define DT_WRREG 271 965*4c3888b8SHans Rosenfeld #define DT_RRRAM 272 966*4c3888b8SHans Rosenfeld #define DT_RPCIC 273 967*4c3888b8SHans Rosenfeld #define DT_GQUES 274 968*4c3888b8SHans Rosenfeld #define DT_WDMP 275 969*4c3888b8SHans Rosenfeld 970*4c3888b8SHans Rosenfeld /* 971*4c3888b8SHans Rosenfeld * firmware dump Template Header (Entry Type 99) 972*4c3888b8SHans Rosenfeld */ 973*4c3888b8SHans Rosenfeld typedef struct ql_dt_hdr { 974*4c3888b8SHans Rosenfeld uint32_t type; 975*4c3888b8SHans Rosenfeld uint32_t first_entry_offset; 976*4c3888b8SHans Rosenfeld uint32_t size_of_template; 977*4c3888b8SHans Rosenfeld uint32_t rsv; 978*4c3888b8SHans Rosenfeld uint32_t num_of_entries; 979*4c3888b8SHans Rosenfeld uint32_t version; 980*4c3888b8SHans Rosenfeld uint32_t driver_timestamp; 981*4c3888b8SHans Rosenfeld uint32_t checksum; 982*4c3888b8SHans Rosenfeld uint32_t rsv_1; 983*4c3888b8SHans Rosenfeld uint32_t driver_info[3]; 984*4c3888b8SHans Rosenfeld uint32_t saved_state_area[16]; 985*4c3888b8SHans Rosenfeld uint32_t rsv_2[8]; 986*4c3888b8SHans Rosenfeld uint32_t ver_attr[5]; 987*4c3888b8SHans Rosenfeld } ql_dt_hdr_t; 988*4c3888b8SHans Rosenfeld 989*4c3888b8SHans Rosenfeld /* 990*4c3888b8SHans Rosenfeld * firmware dump Common Entry Header 991*4c3888b8SHans Rosenfeld */ 992*4c3888b8SHans Rosenfeld typedef struct ql_dt_entry_hdr { 993*4c3888b8SHans Rosenfeld uint32_t type; 994*4c3888b8SHans Rosenfeld uint32_t size; 995*4c3888b8SHans Rosenfeld uint32_t rsv; 996*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 997*4c3888b8SHans Rosenfeld uint8_t driver_flags; 998*4c3888b8SHans Rosenfeld uint8_t rsv_2; 999*4c3888b8SHans Rosenfeld uint8_t rsv_1; 1000*4c3888b8SHans Rosenfeld uint8_t capture_flags; 1001*4c3888b8SHans Rosenfeld #else 1002*4c3888b8SHans Rosenfeld uint8_t capture_flags; 1003*4c3888b8SHans Rosenfeld uint8_t rsv_1; 1004*4c3888b8SHans Rosenfeld uint8_t rsv_2; 1005*4c3888b8SHans Rosenfeld uint8_t driver_flags; 1006*4c3888b8SHans Rosenfeld #endif 1007*4c3888b8SHans Rosenfeld } ql_dt_entry_hdr_t; 1008*4c3888b8SHans Rosenfeld 1009*4c3888b8SHans Rosenfeld /* 1010*4c3888b8SHans Rosenfeld * Capture Flags 1011*4c3888b8SHans Rosenfeld */ 1012*4c3888b8SHans Rosenfeld #define PF_ONLY_FLAG BIT_0 /* Physical Function Only */ 1013*4c3888b8SHans Rosenfeld #define PF_VF_FLAG BIT_1 /* Physical and Virtual Functions */ 1014*4c3888b8SHans Rosenfeld 1015*4c3888b8SHans Rosenfeld /* 1016*4c3888b8SHans Rosenfeld * Driver Flags 1017*4c3888b8SHans Rosenfeld */ 1018*4c3888b8SHans Rosenfeld #define SKIPPED_FLAG BIT_7 /* driver skipped this entry */ 1019*4c3888b8SHans Rosenfeld 1020*4c3888b8SHans Rosenfeld /* 1021*4c3888b8SHans Rosenfeld * firmware dump Entry Including Header 1022*4c3888b8SHans Rosenfeld */ 1023*4c3888b8SHans Rosenfeld typedef struct ql_dt_entry { 1024*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1025*4c3888b8SHans Rosenfeld uint32_t data[1]; 1026*4c3888b8SHans Rosenfeld } ql_dt_entry_t; 1027*4c3888b8SHans Rosenfeld 1028*4c3888b8SHans Rosenfeld /* 1029*4c3888b8SHans Rosenfeld * firmware dump Template image 1030*4c3888b8SHans Rosenfeld */ 1031*4c3888b8SHans Rosenfeld typedef struct ql_dmp_template { 1032*4c3888b8SHans Rosenfeld uint32_t rsv[2]; 1033*4c3888b8SHans Rosenfeld uint32_t len; 1034*4c3888b8SHans Rosenfeld uint32_t major_ver; 1035*4c3888b8SHans Rosenfeld uint32_t minor_ver; 1036*4c3888b8SHans Rosenfeld uint32_t subminor_ver; 1037*4c3888b8SHans Rosenfeld uint32_t attribute; 1038*4c3888b8SHans Rosenfeld ql_dt_hdr_t hdr; 1039*4c3888b8SHans Rosenfeld ql_dt_entry_t entries[1]; 1040*4c3888b8SHans Rosenfeld } ql_dmp_template_t; 1041*4c3888b8SHans Rosenfeld 1042*4c3888b8SHans Rosenfeld typedef struct ql_dt_riob1 { 1043*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1044*4c3888b8SHans Rosenfeld uint32_t addr; 1045*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1046*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1047*4c3888b8SHans Rosenfeld uint8_t reg_count_h; 1048*4c3888b8SHans Rosenfeld uint8_t reg_count_l; 1049*4c3888b8SHans Rosenfeld uint8_t reg_size; 1050*4c3888b8SHans Rosenfeld #else 1051*4c3888b8SHans Rosenfeld uint8_t reg_size; 1052*4c3888b8SHans Rosenfeld uint8_t reg_count_l; 1053*4c3888b8SHans Rosenfeld uint8_t reg_count_h; 1054*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1055*4c3888b8SHans Rosenfeld #endif 1056*4c3888b8SHans Rosenfeld } ql_dt_riob1_t; 1057*4c3888b8SHans Rosenfeld 1058*4c3888b8SHans Rosenfeld typedef struct ql_dt_wiob1 { 1059*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1060*4c3888b8SHans Rosenfeld uint32_t addr; 1061*4c3888b8SHans Rosenfeld uint32_t data; 1062*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1063*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1064*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1065*4c3888b8SHans Rosenfeld #else 1066*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1067*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1068*4c3888b8SHans Rosenfeld #endif 1069*4c3888b8SHans Rosenfeld } ql_dt_wiob1_t; 1070*4c3888b8SHans Rosenfeld 1071*4c3888b8SHans Rosenfeld typedef struct ql_dt_riob2 { 1072*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1073*4c3888b8SHans Rosenfeld uint32_t addr; 1074*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1075*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1076*4c3888b8SHans Rosenfeld uint8_t reg_count_h; 1077*4c3888b8SHans Rosenfeld uint8_t reg_count_l; 1078*4c3888b8SHans Rosenfeld uint8_t reg_size; 1079*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1080*4c3888b8SHans Rosenfeld uint8_t bank_sel_offset; 1081*4c3888b8SHans Rosenfeld #else 1082*4c3888b8SHans Rosenfeld uint8_t reg_size; 1083*4c3888b8SHans Rosenfeld uint8_t reg_count_l; 1084*4c3888b8SHans Rosenfeld uint8_t reg_count_h; 1085*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1086*4c3888b8SHans Rosenfeld uint8_t bank_sel_offset; 1087*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1088*4c3888b8SHans Rosenfeld #endif 1089*4c3888b8SHans Rosenfeld uint32_t reg_bank; 1090*4c3888b8SHans Rosenfeld } ql_dt_riob2_t; 1091*4c3888b8SHans Rosenfeld 1092*4c3888b8SHans Rosenfeld typedef struct ql_dt_wiob2 { 1093*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1094*4c3888b8SHans Rosenfeld uint32_t addr; 1095*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1096*4c3888b8SHans Rosenfeld uint8_t rsv[2]; 1097*4c3888b8SHans Rosenfeld uint8_t data_h; 1098*4c3888b8SHans Rosenfeld uint8_t data_l; 1099*4c3888b8SHans Rosenfeld uint8_t bank_sel_offset; 1100*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1101*4c3888b8SHans Rosenfeld uint8_t rsv1[2]; 1102*4c3888b8SHans Rosenfeld #else 1103*4c3888b8SHans Rosenfeld uint8_t data_l; 1104*4c3888b8SHans Rosenfeld uint8_t data_h; 1105*4c3888b8SHans Rosenfeld uint8_t rsv[2]; 1106*4c3888b8SHans Rosenfeld uint8_t rsv1[2]; 1107*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1108*4c3888b8SHans Rosenfeld uint8_t bank_sel_offset; 1109*4c3888b8SHans Rosenfeld #endif 1110*4c3888b8SHans Rosenfeld uint32_t reg_bank; 1111*4c3888b8SHans Rosenfeld } ql_dt_wiob2_t; 1112*4c3888b8SHans Rosenfeld 1113*4c3888b8SHans Rosenfeld typedef struct ql_dt_rpci { 1114*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1115*4c3888b8SHans Rosenfeld uint32_t addr; 1116*4c3888b8SHans Rosenfeld } ql_dt_rpci_t; 1117*4c3888b8SHans Rosenfeld 1118*4c3888b8SHans Rosenfeld typedef struct ql_dt_wpci { 1119*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1120*4c3888b8SHans Rosenfeld uint32_t addr; 1121*4c3888b8SHans Rosenfeld uint32_t data; 1122*4c3888b8SHans Rosenfeld } ql_dt_wpci_t, ql_dt_wrreg_t; 1123*4c3888b8SHans Rosenfeld 1124*4c3888b8SHans Rosenfeld typedef struct ql_dt_rram { 1125*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1126*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1127*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1128*4c3888b8SHans Rosenfeld uint8_t ram_area; 1129*4c3888b8SHans Rosenfeld #else 1130*4c3888b8SHans Rosenfeld uint8_t ram_area; 1131*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1132*4c3888b8SHans Rosenfeld #endif 1133*4c3888b8SHans Rosenfeld uint32_t start_addr; 1134*4c3888b8SHans Rosenfeld uint32_t end_addr; 1135*4c3888b8SHans Rosenfeld } ql_dt_rram_t; 1136*4c3888b8SHans Rosenfeld 1137*4c3888b8SHans Rosenfeld typedef struct ql_dt_gque { 1138*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1139*4c3888b8SHans Rosenfeld uint32_t num_queues; 1140*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1141*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1142*4c3888b8SHans Rosenfeld uint8_t queue_type; 1143*4c3888b8SHans Rosenfeld #else 1144*4c3888b8SHans Rosenfeld uint8_t queue_type; 1145*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1146*4c3888b8SHans Rosenfeld #endif 1147*4c3888b8SHans Rosenfeld } ql_dt_gque_t, ql_dt_gques_t; 1148*4c3888b8SHans Rosenfeld 1149*4c3888b8SHans Rosenfeld typedef struct ql_dt_gfce { 1150*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1151*4c3888b8SHans Rosenfeld uint32_t fce_trace_size; 1152*4c3888b8SHans Rosenfeld uint32_t write_pointer[2]; 1153*4c3888b8SHans Rosenfeld uint32_t base_pointer[2]; 1154*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb0; 1155*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb2; 1156*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb3; 1157*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb4; 1158*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb5; 1159*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb6; 1160*4c3888b8SHans Rosenfeld } ql_dt_gfce_t; 1161*4c3888b8SHans Rosenfeld 1162*4c3888b8SHans Rosenfeld typedef struct ql_dt_prisc { 1163*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1164*4c3888b8SHans Rosenfeld } ql_dt_prisc_t, ql_dt_rrisc_t; 1165*4c3888b8SHans Rosenfeld 1166*4c3888b8SHans Rosenfeld typedef struct ql_dt_dint { 1167*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1168*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1169*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1170*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1171*4c3888b8SHans Rosenfeld #else 1172*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1173*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1174*4c3888b8SHans Rosenfeld #endif 1175*4c3888b8SHans Rosenfeld uint32_t data; 1176*4c3888b8SHans Rosenfeld } ql_dt_dint_t; 1177*4c3888b8SHans Rosenfeld 1178*4c3888b8SHans Rosenfeld typedef struct ql_dt_ghbd { 1179*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1180*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1181*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1182*4c3888b8SHans Rosenfeld uint8_t host_buf_type; 1183*4c3888b8SHans Rosenfeld #else 1184*4c3888b8SHans Rosenfeld uint8_t host_buf_type; 1185*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1186*4c3888b8SHans Rosenfeld #endif 1187*4c3888b8SHans Rosenfeld uint32_t buf_size; 1188*4c3888b8SHans Rosenfeld uint32_t start_addr; 1189*4c3888b8SHans Rosenfeld } ql_dt_ghbd_t; 1190*4c3888b8SHans Rosenfeld 1191*4c3888b8SHans Rosenfeld typedef struct ql_dt_scra { 1192*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1193*4c3888b8SHans Rosenfeld uint32_t scratch_size; 1194*4c3888b8SHans Rosenfeld } ql_dt_scra_t; 1195*4c3888b8SHans Rosenfeld 1196*4c3888b8SHans Rosenfeld typedef struct ql_dt_rrreg { 1197*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1198*4c3888b8SHans Rosenfeld uint32_t addr; 1199*4c3888b8SHans Rosenfeld uint32_t count; 1200*4c3888b8SHans Rosenfeld } ql_dt_rrreg_t, ql_dt_rrram_t, ql_dt_rpcic_t; 1201*4c3888b8SHans Rosenfeld 1202*4c3888b8SHans Rosenfeld typedef struct ql_dt_wdmp { 1203*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1204*4c3888b8SHans Rosenfeld uint32_t length; 1205*4c3888b8SHans Rosenfeld uint32_t data[1]; 1206*4c3888b8SHans Rosenfeld } ql_dt_wdmp_t; 1207*4c3888b8SHans Rosenfeld 1208fcf3ce44SJohn Forte /* 1209fcf3ce44SJohn Forte * ql_lock_nvram() flags 1210fcf3ce44SJohn Forte */ 1211fcf3ce44SJohn Forte #define LNF_NVRAM_DATA BIT_0 /* get nvram */ 1212fcf3ce44SJohn Forte #define LNF_VPD_DATA BIT_1 /* get vpd data (24xx only) */ 1213fcf3ce44SJohn Forte 1214fcf3ce44SJohn Forte /* 1215fcf3ce44SJohn Forte * ISP product identification definitions in mailboxes after reset. 1216fcf3ce44SJohn Forte */ 1217fcf3ce44SJohn Forte #define PROD_ID_1 0x4953 1218fcf3ce44SJohn Forte #define PROD_ID_2 0x0000 1219fcf3ce44SJohn Forte #define PROD_ID_2a 0x5020 1220fcf3ce44SJohn Forte #define PROD_ID_3 0x2020 1221fcf3ce44SJohn Forte 1222fcf3ce44SJohn Forte /* 1223fcf3ce44SJohn Forte * NVRAM Command values. 1224fcf3ce44SJohn Forte */ 1225fcf3ce44SJohn Forte #define NV_START_BIT BIT_2 1226*4c3888b8SHans Rosenfeld #define NV_WRITE_OP (BIT_26 + BIT_24) 1227*4c3888b8SHans Rosenfeld #define NV_READ_OP (BIT_26 + BIT_25) 1228*4c3888b8SHans Rosenfeld #define NV_ERASE_OP (BIT_26 + BIT_25 + BIT_24) 1229*4c3888b8SHans Rosenfeld #define NV_MASK_OP (BIT_26 + BIT_25 + BIT_24) 1230fcf3ce44SJohn Forte #define NV_DELAY_COUNT 10 1231fcf3ce44SJohn Forte 12325dfd244aSDaniel Beauregard /* 12335dfd244aSDaniel Beauregard * Deivce ID list definitions. 12345dfd244aSDaniel Beauregard */ 12355dfd244aSDaniel Beauregard struct ql_dev_id { 12365dfd244aSDaniel Beauregard uint8_t al_pa; 12375dfd244aSDaniel Beauregard uint8_t area; 12385dfd244aSDaniel Beauregard uint8_t domain; 12395dfd244aSDaniel Beauregard uint8_t loop_id; 12405dfd244aSDaniel Beauregard }; 12415dfd244aSDaniel Beauregard 12425dfd244aSDaniel Beauregard struct ql_ex_dev_id { 12435dfd244aSDaniel Beauregard uint8_t al_pa; 12445dfd244aSDaniel Beauregard uint8_t area; 12455dfd244aSDaniel Beauregard uint8_t domain; 12465dfd244aSDaniel Beauregard uint8_t reserved; 12475dfd244aSDaniel Beauregard uint8_t loop_id_l; 12485dfd244aSDaniel Beauregard uint8_t loop_id_h; 12495dfd244aSDaniel Beauregard }; 12505dfd244aSDaniel Beauregard 12515dfd244aSDaniel Beauregard struct ql_24_dev_id { 12525dfd244aSDaniel Beauregard uint8_t al_pa; 12535dfd244aSDaniel Beauregard uint8_t area; 12545dfd244aSDaniel Beauregard uint8_t domain; 12555dfd244aSDaniel Beauregard uint8_t reserved; 12565dfd244aSDaniel Beauregard uint8_t n_port_hdl_l; 12575dfd244aSDaniel Beauregard uint8_t n_port_hdl_h; 12585dfd244aSDaniel Beauregard uint8_t reserved_1[2]; 12595dfd244aSDaniel Beauregard }; 12605dfd244aSDaniel Beauregard 12615dfd244aSDaniel Beauregard typedef union ql_dev_id_list { 12625dfd244aSDaniel Beauregard struct ql_dev_id d; 12635dfd244aSDaniel Beauregard struct ql_ex_dev_id d_ex; 12645dfd244aSDaniel Beauregard struct ql_24_dev_id d_24; 12655dfd244aSDaniel Beauregard } ql_dev_id_list_t; 12665dfd244aSDaniel Beauregard 12675dfd244aSDaniel Beauregard /* Define maximum number of device list entries.. */ 12685dfd244aSDaniel Beauregard #define DEVICE_LIST_ENTRIES MAX_24_FIBRE_DEVICES 1269fcf3ce44SJohn Forte 1270fcf3ce44SJohn Forte /* 1271fcf3ce44SJohn Forte * Global Data in ql_init.c source file. 1272fcf3ce44SJohn Forte */ 1273fcf3ce44SJohn Forte 1274fcf3ce44SJohn Forte /* 1275fcf3ce44SJohn Forte * Global Function Prototypes in ql_init.c source file. 1276fcf3ce44SJohn Forte */ 1277fcf3ce44SJohn Forte int ql_initialize_adapter(ql_adapter_state_t *); 1278fcf3ce44SJohn Forte int ql_pci_sbus_config(ql_adapter_state_t *); 1279fcf3ce44SJohn Forte int ql_nvram_config(ql_adapter_state_t *); 1280fcf3ce44SJohn Forte uint16_t ql_get_nvram_word(ql_adapter_state_t *, uint32_t); 1281fcf3ce44SJohn Forte void ql_nv_write(ql_adapter_state_t *, uint16_t); 1282fcf3ce44SJohn Forte void ql_nv_delay(void); 1283fcf3ce44SJohn Forte int ql_lock_nvram(ql_adapter_state_t *, uint32_t *, uint32_t); 1284fcf3ce44SJohn Forte void ql_release_nvram(ql_adapter_state_t *); 1285fcf3ce44SJohn Forte void ql_common_properties(ql_adapter_state_t *); 1286fcf3ce44SJohn Forte uint32_t ql_get_prop(ql_adapter_state_t *, char *); 1287fcf3ce44SJohn Forte int ql_load_isp_firmware(ql_adapter_state_t *); 1288fcf3ce44SJohn Forte int ql_start_firmware(ql_adapter_state_t *); 1289fcf3ce44SJohn Forte int ql_set_cache_line(ql_adapter_state_t *); 1290fcf3ce44SJohn Forte int ql_init_rings(ql_adapter_state_t *); 1291fcf3ce44SJohn Forte int ql_fw_ready(ql_adapter_state_t *, uint8_t); 12925dfd244aSDaniel Beauregard void ql_dev_list(ql_adapter_state_t *, ql_dev_id_list_t *, uint32_t, 1293fcf3ce44SJohn Forte port_id_t *, uint16_t *); 1294fcf3ce44SJohn Forte void ql_reset_chip(ql_adapter_state_t *); 1295fcf3ce44SJohn Forte int ql_abort_isp(ql_adapter_state_t *); 1296*4c3888b8SHans Rosenfeld void ql_requeue_all_cmds(ql_adapter_state_t *); 1297fcf3ce44SJohn Forte int ql_vport_control(ql_adapter_state_t *, uint8_t); 1298fcf3ce44SJohn Forte int ql_vport_modify(ql_adapter_state_t *, uint8_t, uint8_t); 1299fcf3ce44SJohn Forte int ql_vport_enable(ql_adapter_state_t *); 1300fcf3ce44SJohn Forte ql_adapter_state_t *ql_vport_create(ql_adapter_state_t *, uint8_t); 1301fcf3ce44SJohn Forte void ql_vport_destroy(ql_adapter_state_t *); 1302fcf3ce44SJohn Forte #endif /* _KERNEL */ 1303fcf3ce44SJohn Forte 1304fcf3ce44SJohn Forte #ifdef __cplusplus 1305fcf3ce44SJohn Forte } 1306fcf3ce44SJohn Forte #endif 1307fcf3ce44SJohn Forte 1308fcf3ce44SJohn Forte #endif /* _QL_INIT_H */ 1309