1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2010 QLogic Corporation */ 23 24 /* 25 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _QL_API_H 30 #define _QL_API_H 31 32 /* 33 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 34 * 35 * *********************************************************************** 36 * * ** 37 * * NOTICE ** 38 * * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION ** 39 * * ALL RIGHTS RESERVED ** 40 * * ** 41 * *********************************************************************** 42 * 43 */ 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /* OS include files. */ 50 #include <sys/scsi/scsi_types.h> 51 #include <sys/byteorder.h> 52 #include <sys/pci.h> 53 #include <sys/utsname.h> 54 #include <sys/file.h> 55 #include <sys/param.h> 56 #include <ql_open.h> 57 58 #include <sys/fibre-channel/fc.h> 59 #include <sys/fibre-channel/impl/fc_fcaif.h> 60 61 #ifndef DDI_INTR_TYPE_FIXED 62 #define DDI_INTR_TYPE_FIXED 0x1 63 #endif 64 #ifndef DDI_INTR_TYPE_MSI 65 #define DDI_INTR_TYPE_MSI 0x2 66 #endif 67 #ifndef DDI_INTR_TYPE_MSIX 68 #define DDI_INTR_TYPE_MSIX 0x4 69 #endif 70 #ifndef DDI_INTR_FLAG_BLOCK 71 #define DDI_INTR_FLAG_BLOCK 0x100 72 #endif 73 #ifndef DDI_INTR_ALLOC_NORMAL 74 #define DDI_INTR_ALLOC_NORMAL 0 75 #endif 76 #ifndef DDI_INTR_ALLOC_STRICT 77 #define DDI_INTR_ALLOC_STRICT 1 78 #endif 79 80 /* 81 * NPIV defines 82 */ 83 #ifndef FC_NPIV_FDISC_FAILED 84 #define FC_NPIV_FDISC_FAILED 0x45 85 #endif 86 #ifndef FC_NPIV_FDISC_WWN_INUSE 87 #define FC_NPIV_FDISC_WWN_INUSE 0x46 88 #endif 89 #ifndef FC_NPIV_NOT_SUPPORTED 90 #define FC_NPIV_NOT_SUPPORTED 0x47 91 #endif 92 #ifndef FC_NPIV_WRONG_TOPOLOGY 93 #define FC_NPIV_WRONG_TOPOLOGY 0x48 94 #endif 95 #ifndef FC_NPIV_NPIV_BOUND 96 #define FC_NPIV_NPIV_BOUND 0x49 97 #endif 98 99 #pragma weak ddi_intr_get_supported_types 100 #pragma weak ddi_intr_get_nintrs 101 #pragma weak ddi_intr_alloc 102 #pragma weak ddi_intr_free 103 #pragma weak ddi_intr_get_pri 104 #pragma weak ddi_intr_add_handler 105 #pragma weak ddi_intr_dup_handler 106 #pragma weak ddi_intr_get_navail 107 #pragma weak ddi_intr_block_disable 108 #pragma weak ddi_intr_block_enable 109 #pragma weak ddi_intr_disable 110 #pragma weak ddi_intr_enable 111 #pragma weak ddi_intr_get_cap 112 #pragma weak ddi_intr_remove_handler 113 extern int ddi_intr_get_supported_types(); 114 extern int ddi_intr_get_nintrs(); 115 extern int ddi_intr_alloc(); 116 extern int ddi_intr_free(); 117 extern int ddi_intr_get_pri(); 118 extern int ddi_intr_add_handler(); 119 extern int ddi_intr_dup_handler(); 120 extern int ddi_intr_get_navail(); 121 extern int ddi_intr_block_disable(); 122 extern int ddi_intr_block_enable(); 123 extern int ddi_intr_disable(); 124 extern int ddi_intr_enable(); 125 extern int ddi_intr_get_cap(); 126 extern int ddi_intr_remove_handler(); 127 128 #ifndef QL_DRV_HARDENING 129 #define ddi_devstate_t int 130 #define DDI_DEVSTATE_UP 0 131 #define ddi_get_devstate(a) DDI_DEVSTATE_UP 132 #define ddi_dev_report_fault(a, b, c, d) 133 #define ddi_check_dma_handle(a) DDI_SUCCESS 134 #define ddi_check_acc_handle(a) DDI_SUCCESS 135 #define QL_CLEAR_DMA_HANDLE(x) 136 #else 137 #define QL_CLEAR_DMA_HANDLE(x) ((ddi_dma_impl_t *)x)->dmai_fault_notify = 0; \ 138 ((ddi_dma_impl_t *)x)->dmai_fault_check = 0; \ 139 ((ddi_dma_impl_t *)x)->dmai_fault = 0 140 #endif 141 142 #ifndef FC_STATE_1GBIT_SPEED 143 #define FC_STATE_1GBIT_SPEED 0x0100 /* 1 Gbit/sec */ 144 #endif 145 #ifndef FC_STATE_2GBIT_SPEED 146 #define FC_STATE_2GBIT_SPEED 0x0400 /* 2 Gbit/sec */ 147 #endif 148 #ifndef FC_STATE_4GBIT_SPEED 149 #define FC_STATE_4GBIT_SPEED 0x0500 /* 4 Gbit/sec */ 150 #endif 151 #ifndef FC_STATE_8GBIT_SPEED 152 #define FC_STATE_8GBIT_SPEED 0x0700 /* 8 Gbit/sec */ 153 #endif 154 #ifndef FC_STATE_10GBIT_SPEED 155 #define FC_STATE_10GBIT_SPEED 0x0600 /* 10 Gbit/sec */ 156 #endif 157 158 /* 159 * Data bit definitions. 160 */ 161 #define BIT_0 0x1 162 #define BIT_1 0x2 163 #define BIT_2 0x4 164 #define BIT_3 0x8 165 #define BIT_4 0x10 166 #define BIT_5 0x20 167 #define BIT_6 0x40 168 #define BIT_7 0x80 169 #define BIT_8 0x100 170 #define BIT_9 0x200 171 #define BIT_10 0x400 172 #define BIT_11 0x800 173 #define BIT_12 0x1000 174 #define BIT_13 0x2000 175 #define BIT_14 0x4000 176 #define BIT_15 0x8000 177 #define BIT_16 0x10000 178 #define BIT_17 0x20000 179 #define BIT_18 0x40000 180 #define BIT_19 0x80000 181 #define BIT_20 0x100000 182 #define BIT_21 0x200000 183 #define BIT_22 0x400000 184 #define BIT_23 0x800000 185 #define BIT_24 0x1000000 186 #define BIT_25 0x2000000 187 #define BIT_26 0x4000000 188 #define BIT_27 0x8000000 189 #define BIT_28 0x10000000 190 #define BIT_29 0x20000000 191 #define BIT_30 0x40000000 192 #define BIT_31 0x80000000 193 194 /* 195 * Local Macro Definitions. 196 */ 197 #ifndef TRUE 198 #define TRUE B_TRUE 199 #endif 200 201 #ifndef FALSE 202 #define FALSE B_FALSE 203 #endif 204 205 /* 206 * I/O register 207 */ 208 #define RD_REG_BYTE(ha, addr) \ 209 (uint8_t)ddi_get8(ha->dev_handle, (uint8_t *)(addr)) 210 #define RD_REG_WORD(ha, addr) \ 211 (uint16_t)ddi_get16(ha->dev_handle, (uint16_t *)(addr)) 212 #define RD_REG_DWORD(ha, addr) \ 213 (uint32_t)ddi_get32(ha->dev_handle, (uint32_t *)(addr)) 214 #define RD_REG_DDWORD(ha, addr) \ 215 (uint64_t)ddi_get64(ha->dev_handle, (uint64_t *)(addr)) 216 217 #define WRT_REG_BYTE(ha, addr, data) \ 218 ddi_put8(ha->dev_handle, (uint8_t *)(addr), (uint8_t)(data)) 219 #define WRT_REG_WORD(ha, addr, data) \ 220 ddi_put16(ha->dev_handle, (uint16_t *)(addr), (uint16_t)(data)) 221 #define WRT_REG_DWORD(ha, addr, data) \ 222 ddi_put32(ha->dev_handle, (uint32_t *)(addr), (uint32_t)(data)) 223 #define WRT_REG_DDWORD(ha, addr, data) \ 224 ddi_put64(ha->dev_handle, (uint64_t *)(addr), (uint64_t)(data)) 225 226 #define RD8_IO_REG(ha, regname) \ 227 RD_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname)) 228 #define RD16_IO_REG(ha, regname) \ 229 RD_REG_WORD(ha, (ha->iobase + ha->reg_off->regname)) 230 #define RD32_IO_REG(ha, regname) \ 231 RD_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname)) 232 233 #define WRT8_IO_REG(ha, regname, data) \ 234 WRT_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname), (data)) 235 #define WRT16_IO_REG(ha, regname, data) \ 236 WRT_REG_WORD(ha, (ha->iobase + ha->reg_off->regname), (data)) 237 #define WRT32_IO_REG(ha, regname, data) \ 238 WRT_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname), (data)) 239 240 #define RD_IOREG_BYTE(ha, addr) \ 241 (uint8_t)ddi_get8(ha->iomap_dev_handle, (uint8_t *)(addr)) 242 #define RD_IOREG_WORD(ha, addr) \ 243 (uint16_t)ddi_get16(ha->iomap_dev_handle, (uint16_t *)(addr)) 244 #define RD_IOREG_DWORD(ha, addr) \ 245 (uint32_t)ddi_get32(ha->iomap_dev_handle, (uint32_t *)(addr)) 246 247 #define WRT_IOREG_BYTE(ha, addr, data) \ 248 ddi_put8(ha->iomap_dev_handle, (uint8_t *)addr, (uint8_t)(data)) 249 #define WRT_IOREG_WORD(ha, addr, data) \ 250 ddi_put16(ha->iomap_dev_handle, (uint16_t *)addr, (uint16_t)(data)) 251 #define WRT_IOREG_DWORD(ha, addr, data) \ 252 ddi_put32(ha->iomap_dev_handle, (uint32_t *)addr, (uint32_t)(data)) 253 254 #define RD8_IOMAP_REG(ha, regname) \ 255 RD_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname)) 256 #define RD16_IOMAP_REG(ha, regname) \ 257 RD_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname)) 258 #define RD32_IOMAP_REG(ha, regname) \ 259 RD_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname)) 260 261 #define WRT8_IOMAP_REG(ha, regname, data) \ 262 WRT_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname), (data)) 263 #define WRT16_IOMAP_REG(ha, regname, data) \ 264 WRT_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname), (data)) 265 #define WRT32_IOMAP_REG(ha, regname, data) \ 266 WRT_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname), (data)) 267 268 /* 269 * FCA definitions 270 */ 271 #define MAX_LUNS 16384 272 #define QL_FCA_BRAND 0x0fca2200 273 274 /* Following to be removed when defined by OS. */ 275 /* ************************************************************************ */ 276 #define LA_ELS_FARP_REQ 0x54 277 #define LA_ELS_FARP_REPLY 0x55 278 #define LA_ELS_LPC 0x71 279 #define LA_ELS_LSTS 0x72 280 281 typedef struct { 282 ls_code_t ls_code; 283 uint8_t rsvd[3]; 284 uint8_t port_control; 285 uint8_t lpb[16]; 286 uint8_t lpe[16]; 287 } ql_lpc_t; 288 289 typedef struct { 290 ls_code_t ls_code; 291 } ql_acc_rjt_t; 292 293 typedef fc_linit_resp_t ql_lpc_resp_t; 294 typedef fc_scr_resp_t ql_rscn_resp_t; 295 296 typedef struct { 297 uint16_t class_valid_svc_opt; 298 uint16_t initiator_ctl; 299 uint16_t recipient_ctl; 300 uint16_t rcv_data_size; 301 uint16_t conc_sequences; 302 uint16_t n_port_end_to_end_credit; 303 uint16_t open_sequences_per_exch; 304 uint16_t unused; 305 } class_svc_param_t; 306 307 typedef struct { 308 uint8_t type; 309 uint8_t rsvd; 310 uint16_t process_assoc_flags; 311 uint32_t originator_process; 312 uint32_t responder_process; 313 uint32_t process_flags; 314 } prli_svc_param_t; 315 /* *********************************************************************** */ 316 317 /* 318 * Fibre Channel device definitions. 319 */ 320 #define MAX_22_FIBRE_DEVICES 256 321 #define MAX_24_FIBRE_DEVICES 2048 322 #define MAX_24_VIRTUAL_PORTS 127 323 #define MAX_25_VIRTUAL_PORTS 254 324 325 #define LAST_LOCAL_LOOP_ID 0x7d 326 #define FL_PORT_LOOP_ID 0x7e /* FFFFFE Fabric F_Port */ 327 #define SWITCH_FABRIC_CONTROLLER_LOOP_ID 0x7f /* FFFFFD Fabric Controller */ 328 #define SIMPLE_NAME_SERVER_LOOP_ID 0x80 /* FFFFFC Directory Server */ 329 #define SNS_FIRST_LOOP_ID 0x81 330 #define SNS_LAST_LOOP_ID 0xfe 331 #define IP_BROADCAST_LOOP_ID 0xff /* FFFFFF Broadcast */ 332 #define BROADCAST_ADDR 0xffffff /* FFFFFF Broadcast */ 333 334 /* 335 * Fibre Channel 24xx device definitions. 336 */ 337 #define LAST_N_PORT_HDL 0x7ef 338 #define SNS_24XX_HDL 0x7FC /* SNS FFFFFCh */ 339 #define SFC_24XX_HDL 0x7FD /* fabric controller FFFFFDh */ 340 #define FL_PORT_24XX_HDL 0x7FE /* F_Port FFFFFEh */ 341 #define BROADCAST_24XX_HDL 0x7FF /* IP broadcast FFFFFFh */ 342 343 /* Loop ID's used as flags, must be higher than any valid Loop ID */ 344 #define PORT_NO_LOOP_ID 0x8000 /* Device does not have loop ID. */ 345 #define PORT_LOST_ID 0x4000 /* Device has been lost. */ 346 347 /* Fibre Channel Topoploy. */ 348 #define QL_N_PORT BIT_0 349 #define QL_NL_PORT BIT_1 350 #define QL_F_PORT BIT_2 351 #define QL_FL_PORT BIT_3 352 #define QL_SNS_CONNECTION BIT_4 353 #define QL_LOOP_CONNECTION (QL_NL_PORT | QL_FL_PORT) 354 #define QL_P2P_CONNECTION (QL_F_PORT | QL_N_PORT) 355 356 /* Timeout timer counts in seconds (must greater than 1 second). */ 357 #define WATCHDOG_TIME 5 /* 0 - 255 */ 358 #define PORT_RETRY_TIME 2 /* 0 - 255 */ 359 #define LOOP_DOWN_TIMER_OFF 0 360 #define LOOP_DOWN_TIMER_START 240 /* 0 - 255 */ 361 #define LOOP_DOWN_TIMER_END 1 362 #define LOOP_DOWN_RESET (LOOP_DOWN_TIMER_START - 45) /* 0 - 255 */ 363 #define R_A_TOV_DEFAULT 20 /* 0 - 65535 */ 364 #define IDLE_CHECK_TIMER 300 /* 0 - 65535 */ 365 #define MAX_DEVICE_LOST_RETRY 16 /* 0 - 255 */ 366 367 /* Maximum outstanding commands in ISP queues (1-4095) */ 368 #define MAX_OUTSTANDING_COMMANDS 0x400 369 #define OSC_INDEX_MASK 0xfff 370 #define OSC_INDEX_SHIFT 12 371 372 /* Maximum unsolicited buffers (1-65535) */ 373 #define QL_UB_LIMIT 256 374 375 /* ISP request, response and receive buffer entry counts */ 376 #define REQUEST_ENTRY_CNT 512 /* Request entries (205-65535) */ 377 #define RESPONSE_ENTRY_CNT 256 /* Response entries (1-65535) */ 378 #define RCVBUF_CONTAINER_CNT 64 /* Rcv buffer containers (8-1024) */ 379 380 /* 381 * ISP request, response, mailbox and receive buffer queue sizes 382 */ 383 #define REQUEST_ENTRY_SIZE 64 384 #define REQUEST_QUEUE_SIZE (REQUEST_ENTRY_SIZE * REQUEST_ENTRY_CNT) 385 386 #define RESPONSE_ENTRY_SIZE 64 387 #define RESPONSE_QUEUE_SIZE (RESPONSE_ENTRY_SIZE * RESPONSE_ENTRY_CNT) 388 389 #define MAILBOX_BUFFER_SIZE 0x4000 390 391 #define RCVBUF_CONTAINER_SIZE 12 392 #define RCVBUF_QUEUE_SIZE (RCVBUF_CONTAINER_SIZE * RCVBUF_CONTAINER_CNT) 393 394 /* 395 * ISP DMA buffer definitions 396 */ 397 #define REQUEST_Q_BUFFER_OFFSET 0 398 #define RESPONSE_Q_BUFFER_OFFSET (REQUEST_Q_BUFFER_OFFSET + REQUEST_QUEUE_SIZE) 399 #define RCVBUF_Q_BUFFER_OFFSET (RESPONSE_Q_BUFFER_OFFSET + RESPONSE_QUEUE_SIZE) 400 401 /* 402 * DMA attributes definitions. 403 */ 404 #define QL_DMA_LOW_ADDRESS (uint64_t)0 405 #define QL_DMA_HIGH_64BIT_ADDRESS (uint64_t)0xffffffffffffffff 406 #define QL_DMA_HIGH_32BIT_ADDRESS (uint64_t)0xffffffff 407 #define QL_DMA_XFER_COUNTER (uint64_t)0xffffffff 408 #define QL_DMA_ADDRESS_ALIGNMENT (uint64_t)8 409 #define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3 410 #define QL_DMA_RING_ADDRESS_ALIGNMENT (uint64_t)64 411 #define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6 412 #define QL_DMA_BURSTSIZES 0xff 413 #define QL_DMA_MIN_XFER_SIZE 1 414 #define QL_DMA_MAX_XFER_SIZE (uint64_t)0xffffffff 415 #define QL_DMA_SEGMENT_BOUNDARY (uint64_t)0xffffffff 416 417 #ifdef __sparc 418 #define QL_DMA_SG_LIST_LENGTH 1 419 #define QL_FCSM_CMD_SGLLEN 1 420 #define QL_FCSM_RSP_SGLLEN 1 421 #define QL_FCIP_CMD_SGLLEN 1 422 #define QL_FCIP_RSP_SGLLEN 1 423 #define QL_FCP_CMD_SGLLEN 1 424 #define QL_FCP_RSP_SGLLEN 1 425 #else 426 #define QL_DMA_SG_LIST_LENGTH 1024 427 #define QL_FCSM_CMD_SGLLEN 1 428 #define QL_FCSM_RSP_SGLLEN 6 429 /* 430 * QL_FCIP_CMD_SGLLEN needs to be increased as we changed the max fcip packet 431 * size to about 64K. With this, we need to increase the maximum number of 432 * scatter-gather elements allowable from the existing 7. We want it to be more 433 * like 17 (max fragments for an fcip packet that is unaligned). (64K / 4K) + 1 434 * or whatever. Otherwise the DMA breakup routines will give bad results. 435 */ 436 #define QL_FCIP_CMD_SGLLEN 17 437 #define QL_FCIP_RSP_SGLLEN 1 438 #define QL_FCP_CMD_SGLLEN 1 439 #define QL_FCP_RSP_SGLLEN 1 440 #endif 441 442 #ifndef DDI_DMA_RELAXED_ORDERING 443 #define DDI_DMA_RELAXED_ORDERING 0x400 444 #endif 445 446 #define QL_DMA_GRANULARITY 1 447 #define QL_DMA_XFER_FLAGS 0 448 449 typedef union { 450 uint64_t size64; /* 1 X 64 bit number */ 451 uint32_t size32[2]; /* 2 x 32 bit number */ 452 uint16_t size16[4]; /* 4 x 16 bit number */ 453 uint8_t size8[8]; /* 8 x 8 bit number */ 454 } conv_num_t; 455 456 /* 457 * Device register offsets. 458 */ 459 #define MAX_MBOX_COUNT 32 460 typedef struct { 461 uint16_t flash_address; /* Flash BIOS address */ 462 uint16_t flash_data; /* Flash BIOS data */ 463 uint16_t ctrl_status; /* Control/Status */ 464 uint16_t ictrl; /* Interrupt control */ 465 uint16_t istatus; /* Interrupt status */ 466 uint16_t semaphore; /* Semaphore */ 467 uint16_t nvram; /* NVRAM register. */ 468 uint16_t req_in; /* for 2200 MBX 4 Write */ 469 uint16_t req_out; /* for 2200 MBX 4 read */ 470 uint16_t resp_in; /* for 2200 MBX 5 Read */ 471 uint16_t resp_out; /* for 2200 MBX 5 Write */ 472 uint16_t risc2host; 473 uint16_t mbox_cnt; /* Number of mailboxes */ 474 uint16_t mailbox_in[MAX_MBOX_COUNT]; /* Mailbox registers */ 475 uint16_t mailbox_out[MAX_MBOX_COUNT]; /* Mailbox registers */ 476 uint16_t fpm_diag_config; 477 uint16_t pcr; /* Processor Control Register. */ 478 uint16_t mctr; /* Memory Configuration and Timing. */ 479 uint16_t fb_cmd; 480 uint16_t hccr; /* Host command & control register. */ 481 uint16_t gpiod; /* GPIO Data register. */ 482 uint16_t gpioe; /* GPIO Enable register. */ 483 uint16_t host_to_host_sema; /* 2312 resource lock register */ 484 uint16_t pri_req_in; /* 2400 */ 485 uint16_t pri_req_out; /* 2400 */ 486 uint16_t atio_req_in; /* 2400 */ 487 uint16_t atio_req_out; /* 2400 */ 488 uint16_t io_base_addr; /* 2400 */ 489 uint16_t nx_host_int; /* NetXen */ 490 uint16_t nx_risc_int; /* NetXen */ 491 } reg_off_t; 492 493 /* 494 * Mbox-8 read maximum debounce count. 495 * Reading Mbox-8 could be debouncing, before getting stable value. 496 * This is the recommended driver fix from Qlogic along with firmware fix. 497 * During testing, maximum count did not cross 3. 498 */ 499 #define QL_MAX_DEBOUNCE 10 500 501 /* 502 * Control Status register definitions 503 */ 504 #define ISP_FUNC_NUM_MASK (BIT_15 | BIT_14) 505 #define ISP_FLASH_64K_BANK BIT_3 /* Flash BIOS 64K Bank Select */ 506 #define ISP_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 507 #define ISP_RESET BIT_0 /* ISP soft reset */ 508 509 /* 510 * Control Status 24xx register definitions 511 */ 512 #define FLASH_NVRAM_ACCESS_ERROR BIT_18 513 #define DMA_ACTIVE BIT_17 514 #define DMA_SHUTDOWN BIT_16 515 #define FUNCTION_NUMBER BIT_15 516 517 #define MWB_4096_BYTES (BIT_5 | BIT_4) 518 #define MWB_2048_BYTES BIT_5 519 #define MWB_1024_BYTES BIT_4 520 #define MWB_512_BYTES 0 521 522 /* 523 * Interrupt Control register definitions 524 */ 525 #define ISP_EN_INT BIT_15 /* ISP enable interrupts. */ 526 #define ISP_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 527 528 /* 529 * Interrupt Status register definitions 530 */ 531 #define RISC_INT BIT_3 /* RISC interrupt */ 532 533 /* 534 * NetXen Host/Risc Interrupt register definitions 535 */ 536 #define NX_MBX_CMD BIT_0 /* Mailbox command present */ 537 #define NX_RISC_INT BIT_0 /* RISC interrupt present */ 538 539 /* 540 * NVRAM register definitions. 541 */ 542 #define NV_DESELECT 0 543 #define NV_CLOCK BIT_0 544 #define NV_SELECT BIT_1 545 #define NV_DATA_OUT BIT_2 546 #define NV_DATA_IN BIT_3 547 #define NV_PR_ENABLE BIT_13 /* protection register enable */ 548 #define NV_WR_ENABLE BIT_14 /* write enable */ 549 #define NV_BUSY BIT_15 550 551 /* 552 * Flash/NVRAM 24xx definitions 553 */ 554 #define FLASH_DATA_FLAG BIT_31 555 #define FLASH_CONF_ADDR 0x7FFD0000 556 #define FLASH_24_25_DATA_ADDR 0x7FF00000 557 #define FLASH_8100_DATA_ADDR 0x7F800000 558 #define FLASH_ADDR_MASK 0x7FFF0000 559 560 #define NVRAM_CONF_ADDR 0x7FFF0000 561 #define NVRAM_DATA_ADDR 0x7FFE0000 562 563 #define NVRAM_2200_FUNC0_ADDR 0x0 564 #define NVRAM_2300_FUNC0_ADDR 0x0 565 #define NVRAM_2300_FUNC1_ADDR 0x80 566 #define NVRAM_2400_FUNC0_ADDR 0x80 567 #define NVRAM_2400_FUNC1_ADDR 0x180 568 #define NVRAM_2500_FUNC0_ADDR 0x48080 569 #define NVRAM_2500_FUNC1_ADDR 0x48180 570 #define NVRAM_8100_FUNC0_ADDR 0xD0080 571 #define NVRAM_8100_FUNC1_ADDR 0xD0180 572 #define NVRAM_8021_FUNC0_ADDR 0xF0080 573 #define NVRAM_8021_FUNC1_ADDR 0xF0180 574 575 #define VPD_2400_FUNC0_ADDR 0 576 #define VPD_2400_FUNC1_ADDR 0x100 577 #define VPD_2500_FUNC0_ADDR 0x48000 578 #define VPD_2500_FUNC1_ADDR 0x48100 579 #define VPD_8100_FUNC0_ADDR 0xD0000 580 #define VPD_8100_FUNC1_ADDR 0xD0400 581 #define VPD_8021_FUNC0_ADDR 0xFA300 582 #define VPD_8021_FUNC1_ADDR 0xFA300 583 #define VPD_SIZE 0x80 584 585 #define FLASH_2200_FIRMWARE_ADDR 0x20000 586 #define FLASH_2300_FIRMWARE_ADDR 0x20000 587 #define FLASH_2400_FIRMWARE_ADDR 0x20000 588 #define FLASH_2500_FIRMWARE_ADDR 0x20000 589 #define FLASH_8100_FIRMWARE_ADDR 0xA0000 590 #define FLASH_8021_FIRMWARE_ADDR 0x40000 591 #define FLASH_8021_FIRMWARE_SIZE 0x80000 592 #define FLASH_8021_BOOTLOADER_ADDR 0x4000 593 #define FLASH_8021_BOOTLOADER_SIZE 0x8000 594 595 #define FLASH_2400_ERRLOG_START_ADDR_0 0 596 #define FLASH_2400_ERRLOG_START_ADDR_1 0 597 #define FLASH_2500_ERRLOG_START_ADDR_0 0x54000 598 #define FLASH_2500_ERRLOG_START_ADDR_1 0x54400 599 #define FLASH_8100_ERRLOG_START_ADDR_0 0xDC000 600 #define FLASH_8100_ERRLOG_START_ADDR_1 0xDC400 601 #define FLASH_ERRLOG_SIZE 0x200 602 #define FLASH_ERRLOG_ENTRY_SIZE 4 603 604 #define FLASH_2400_DESCRIPTOR_TABLE 0 605 #define FLASH_2500_DESCRIPTOR_TABLE 0x50000 606 #define FLASH_8100_DESCRIPTOR_TABLE 0xD8000 607 #define FLASH_8021_DESCRIPTOR_TABLE 0 608 609 #define FLASH_2400_LAYOUT_TABLE 0x11400 610 #define FLASH_2500_LAYOUT_TABLE 0x50400 611 #define FLASH_8100_LAYOUT_TABLE 0xD8400 612 #define FLASH_8021_LAYOUT_TABLE 0xFC400 613 614 /* 615 * Flash Error Log Event Codes. 616 */ 617 #define FLASH_ERRLOG_AEN_8002 0x8002 618 #define FLASH_ERRLOG_AEN_8003 0x8003 619 #define FLASH_ERRLOG_AEN_8004 0x8004 620 #define FLASH_ERRLOG_RESET_ERR 0xF00B 621 #define FLASH_ERRLOG_ISP_ERR 0xF020 622 #define FLASH_ERRLOG_PARITY_ERR 0xF022 623 #define FLASH_ERRLOG_NVRAM_CHKSUM_ERR 0xF023 624 #define FLASH_ERRLOG_FLASH_FW_ERR 0xF024 625 626 #define VPD_TAG_END 0x78 627 #define VPD_TAG_CHKSUM "RV" 628 #define VPD_TAG_SN "SN" 629 #define VPD_TAG_PN "PN" 630 #define VPD_TAG_PRODID "\x82" 631 #define VPD_TAG_LRT 0x90 632 #define VPD_TAG_LRTC 0x91 633 634 /* 635 * RISC to Host Status register definitions. 636 */ 637 #define RH_RISC_INT BIT_15 /* RISC to Host Intrpt Req */ 638 #define RH_RISC_PAUSED BIT_8 /* RISC Paused bit. */ 639 640 /* 641 * RISC to Host Status register status field definitions. 642 */ 643 #define ROM_MBX_SUCCESS 0x01 644 #define ROM_MBX_ERR 0x02 645 #define MBX_SUCCESS 0x10 646 #define MBX_ERR 0x11 647 #define ASYNC_EVENT 0x12 648 #define RESP_UPDATE 0x13 649 #define REQ_UPDATE 0x14 650 #define SCSI_FAST_POST_16 0x15 651 #define SCSI_FAST_POST_32 0x16 652 #define CTIO_FAST_POST 0x17 653 #define IP_FAST_POST_XMT 0x18 654 #define IP_FAST_POST_RCV 0x19 655 #define IP_FAST_POST_BRD 0x1a 656 #define IP_FAST_POST_RCV_ALN 0x1b 657 #define ATIO_UPDATE 0x1c 658 #define ATIO_RESP_UPDATE 0x1d 659 660 /* 661 * HCCR commands. 662 */ 663 #define HC_RESET_RISC 0x1000 /* Reset RISC */ 664 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */ 665 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 666 #define HC_DISABLE_PARITY_PAUSE 0x4001 /* qla2200/2300 - disable parity err */ 667 /* RISC pause. */ 668 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */ 669 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 670 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 671 #define HC_HOST_INT BIT_7 /* Host interrupt bit */ 672 #define HC_RISC_PAUSE BIT_5 /* Pause mode bit */ 673 674 /* 675 * HCCR commands for 24xx and 25xx. 676 */ 677 #define HC24_RESET_RISC 0x10000000 /* Reset RISC */ 678 #define HC24_CLEAR_RISC_RESET 0x20000000 /* Release RISC from reset. */ 679 #define HC24_PAUSE_RISC 0x30000000 /* Pause RISC */ 680 #define HC24_RELEASE_PAUSE 0x40000000 /* Release RISC from pause */ 681 #define HC24_SET_HOST_INT 0x50000000 /* Set host interrupt */ 682 #define HC24_CLR_HOST_INT 0x60000000 /* Clear HOST interrupt */ 683 #define HC24_CLR_RISC_INT 0xA0000000 /* Clear RISC interrupt */ 684 #define HC24_HOST_INT BIT_6 /* Host to RISC intrpt bit */ 685 #define HC24_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 686 687 /* 688 * ISP Initialization Control Blocks. 689 * Little endian except where noted. 690 */ 691 #define ICB_VERSION 1 692 typedef struct ql_init_cb { 693 uint8_t version; 694 uint8_t reserved; 695 696 /* 697 * LSB BIT 0 = enable_hard_loop_id 698 * LSB BIT 1 = enable_fairness 699 * LSB BIT 2 = enable_full_duplex 700 * LSB BIT 3 = enable_fast_posting 701 * LSB BIT 4 = enable_target_mode 702 * LSB BIT 5 = disable_initiator_mode 703 * LSB BIT 6 = enable_adisc 704 * LSB BIT 7 = enable_target_inquiry_data 705 * 706 * MSB BIT 0 = enable_port_update_ae 707 * MSB BIT 1 = disable_initial_lip 708 * MSB BIT 2 = enable_decending_soft_assign 709 * MSB BIT 3 = previous_assigned_addressing 710 * MSB BIT 4 = enable_stop_q_on_full 711 * MSB BIT 5 = enable_full_login_on_lip 712 * MSB BIT 6 = enable_node_name 713 * MSB BIT 7 = extended_control_block 714 */ 715 uint8_t firmware_options[2]; 716 717 uint8_t max_frame_length[2]; 718 uint8_t max_iocb_allocation[2]; 719 uint8_t execution_throttle[2]; 720 uint8_t login_retry_count; 721 uint8_t retry_delay; /* unused */ 722 uint8_t port_name[8]; /* Big endian. */ 723 uint8_t hard_address[2]; /* option bit 0 */ 724 uint8_t inquiry; /* option bit 7 */ 725 uint8_t login_timeout; 726 uint8_t node_name[8]; /* Big endian */ 727 uint8_t request_q_outpointer[2]; 728 uint8_t response_q_inpointer[2]; 729 uint8_t request_q_length[2]; 730 uint8_t response_q_length[2]; 731 uint8_t request_q_address[8]; 732 uint8_t response_q_address[8]; 733 uint8_t lun_enables[2]; 734 uint8_t command_resouce_count; 735 uint8_t immediate_notify_resouce_count; 736 uint8_t timeout[2]; 737 uint8_t reserved_2[2]; 738 739 /* 740 * LSB BIT 0 = Timer operation mode bit 0 741 * LSB BIT 1 = Timer operation mode bit 1 742 * LSB BIT 2 = Timer operation mode bit 2 743 * LSB BIT 3 = Timer operation mode bit 3 744 * LSB BIT 4 = P2P Connection option bit 0 745 * LSB BIT 5 = P2P Connection option bit 1 746 * LSB BIT 6 = P2P Connection option bit 2 747 * LSB BIT 7 = Enable Non part on LIHA failure 748 * 749 * MSB BIT 0 = Enable class 2 750 * MSB BIT 1 = Enable ACK0 751 * MSB BIT 2 = 752 * MSB BIT 3 = 753 * MSB BIT 4 = FC Tape Enable 754 * MSB BIT 5 = Enable FC Confirm 755 * MSB BIT 6 = Enable CRN 756 * MSB BIT 7 = 757 */ 758 uint8_t add_fw_opt[2]; 759 760 uint8_t response_accumulation_timer; 761 uint8_t interrupt_delay_timer; 762 763 /* 764 * LSB BIT 0 = Enable Read xfr_rdy 765 * LSB BIT 1 = Soft ID only 766 * LSB BIT 2 = 767 * LSB BIT 3 = 768 * LSB BIT 4 = FCP RSP Payload [0] 769 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 770 * LSB BIT 6 = 771 * LSB BIT 7 = 772 * 773 * MSB BIT 0 = Sbus enable - 2300 774 * MSB BIT 1 = 775 * MSB BIT 2 = 776 * MSB BIT 3 = 777 * MSB BIT 4 = 778 * MSB BIT 5 = enable 50 ohm termination 779 * MSB BIT 6 = Data Rate (2300 only) 780 * MSB BIT 7 = Data Rate (2300 only) 781 */ 782 uint8_t special_options[2]; 783 784 uint8_t reserved_3[26]; 785 } ql_init_cb_t; 786 787 /* 788 * Virtual port definition. 789 */ 790 typedef struct ql_vp_cfg { 791 uint8_t reserved[2]; 792 uint8_t options; 793 uint8_t hard_prev_addr; 794 uint8_t port_name[8]; 795 uint8_t node_name[8]; 796 } ql_vp_cfg_t; 797 798 /* 799 * VP options. 800 */ 801 #define VPO_ENABLE_SNS_LOGIN_SCR BIT_6 802 #define VPO_TARGET_MODE_DISABLED BIT_5 803 #define VPO_INITIATOR_MODE_ENABLED BIT_4 804 #define VPO_ENABLED BIT_3 805 #define VPO_ID_NOT_ACQUIRED BIT_2 806 #define VPO_PREVIOUSLY_ASSIGNED_ID BIT_1 807 #define VPO_HARD_ASSIGNED_ID BIT_0 808 809 #define ICB_24XX_VERSION 1 810 typedef struct ql_init_24xx_cb { 811 uint8_t version[2]; 812 uint8_t reserved_1[2]; 813 uint8_t max_frame_length[2]; 814 uint8_t execution_throttle[2]; 815 uint8_t exchange_count[2]; 816 uint8_t hard_address[2]; 817 uint8_t port_name[8]; /* Big endian. */ 818 uint8_t node_name[8]; /* Big endian. */ 819 820 uint8_t response_q_inpointer[2]; 821 uint8_t request_q_outpointer[2]; 822 823 uint8_t login_retry_count[2]; 824 825 uint8_t prio_request_q_outpointer[2]; 826 827 uint8_t response_q_length[2]; 828 uint8_t request_q_length[2]; 829 830 uint8_t link_down_on_nos[2]; 831 832 uint8_t prio_request_q_length[2]; 833 uint8_t request_q_address[8]; 834 uint8_t response_q_address[8]; 835 uint8_t prio_request_q_address[8]; 836 uint8_t msi_x_vector[2]; 837 uint8_t reserved_2[6]; 838 uint8_t atio_q_inpointer[2]; 839 uint8_t atio_q_length[2]; 840 uint8_t atio_q_address[8]; 841 842 uint8_t interrupt_delay_timer[2]; /* 100us per */ 843 uint8_t login_timeout[2]; 844 /* 845 * BIT 0 = Hard Assigned Loop ID 846 * BIT 1 = Enable Fairness 847 * BIT 2 = Enable Full-Duplex 848 * BIT 3 = Reserved 849 * BIT 4 = Target Mode Enable 850 * BIT 5 = Initiator Mode Disable 851 * BIT 6 = Reserved 852 * BIT 7 = Reserved 853 * 854 * BIT 8 = Reserved 855 * BIT 9 = Disable Initial LIP 856 * BIT 10 = Descending Loop ID Search 857 * BIT 11 = Previous Assigned Loop ID 858 * BIT 12 = Reserved 859 * BIT 13 = Full Login after LIP 860 * BIT 14 = Node Name Option 861 * BIT 15-31 = Reserved 862 */ 863 uint8_t firmware_options_1[4]; 864 865 /* 866 * BIT 0 = Operation Mode bit 0 867 * BIT 1 = Operation Mode bit 1 868 * BIT 2 = Operation Mode bit 2 869 * BIT 3 = Operation Mode bit 3 870 * BIT 4 = Connection Options bit 0 871 * BIT 5 = Connection Options bit 1 872 * BIT 6 = Connection Options bit 2 873 * BIT 7 = Enable Non part on LIHA failure 874 * 875 * BIT 8 = Enable Class 2 876 * BIT 9 = Enable ACK0 877 * BIT 10 = Reserved 878 * BIT 11 = Enable FC-SP Security 879 * BIT 12 = FC Tape Enable 880 * BIT 13 = Reserved 881 * BIT 14 = Target PRLI Control 882 * BIT 15 = Reserved 883 * 884 * BIT 16 = Enable Emulated MSIX 885 * BIT 17 = Reserved 886 * BIT 18 = Enable Alternate Device Number 887 * BIT 19 = Enable Alternate Bus Number 888 * BIT 20 = Enable Translated Address 889 * BIT 21 = Enable VM Security 890 * BIT 22 = Enable Interrupt Handshake 891 * BIT 23 = Enable Multiple Queue 892 * 893 * BIT 24 = IOCB Security 894 * BIT 25 = qos 895 * BIT 26-31 = Reserved 896 */ 897 uint8_t firmware_options_2[4]; 898 899 /* 900 * BIT 0 = Reserved 901 * BIT 1 = Soft ID only 902 * BIT 2 = Reserved 903 * BIT 3 = Reserved 904 * BIT 4 = FCP RSP Payload bit 0 905 * BIT 5 = FCP RSP Payload bit 1 906 * BIT 6 = Enable Rec Out-of-Order data frame handling 907 * BIT 7 = Disable Automatic PLOGI on Local Loop 908 * 909 * BIT 8 = Reserved 910 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 911 * offset handling 912 * BIT 10 = Reserved 913 * BIT 11 = Reserved 914 * BIT 12 = Reserved 915 * BIT 13 = Data Rate bit 0 916 * BIT 14 = Data Rate bit 1 917 * BIT 15 = Data Rate bit 2 918 * 919 * BIT 16 = 75-ohm Termination Select 920 * BIT 17 = Enable Multiple FCFs 921 * BIT 18 = MAC Addressing Mode 922 * BIT 19 = MAC Addressing Mode 923 * BIT 20 = MAC Addressing Mode 924 * BIT 21 = Ethernet Data Rate 925 * BIT 22 = Ethernet Data Rate 926 * BIT 23 = Ethernet Data Rate 927 * 928 * BIT 24 = Ethernet Data Rate 929 * BIT 25 = Ethernet Data Rate 930 * BIT 26 = Enable Ethernet Header ATIO Queue 931 * BIT 27 = Enable Ethernet Header Response Queue 932 * BIT 28 = SPMA Selection 933 * BIT 29 = SPMA Selection 934 * BIT 30 = Reserved 935 * BIT 31 = Reserved 936 */ 937 uint8_t firmware_options_3[4]; 938 939 uint8_t qos[2]; 940 uint8_t rid[2]; 941 942 uint8_t reserved_3[4]; 943 944 uint8_t enode_mac_addr[6]; 945 946 uint8_t reserved_4[10]; 947 948 /* 949 * Multi-ID firmware. 950 */ 951 uint8_t vp_count[2]; 952 953 /* 954 * BIT 1 = Allows mode 2 connection option 955 */ 956 uint8_t global_vp_option[2]; 957 958 ql_vp_cfg_t vpc[MAX_25_VIRTUAL_PORTS + 1]; 959 960 /* 961 * Extended Initialization Control Block 962 */ 963 ql_ext_icb_8100_t ext_blk; 964 } ql_init_24xx_cb_t; 965 966 typedef union ql_comb_init_cb { 967 ql_init_cb_t cb; 968 ql_init_24xx_cb_t cb24; 969 } ql_comb_init_cb_t; 970 971 /* 972 * ISP IP Initialization Control Block. 973 * Little endian except where noted. 974 */ 975 #define IP_ICB_VERSION 1 976 typedef struct ql_ip_init_cb { 977 uint8_t version; 978 uint8_t reserved; 979 980 /* 981 * LSB BIT 0 = receive_buffer_address_length 982 * LSB BIT 1 = fast post broadcast received 983 * LSB BIT 2 = allow out of receive buffers AE 984 */ 985 uint8_t ip_firmware_options[2]; 986 uint8_t ip_header_size[2]; 987 uint8_t mtu_size[2]; /* max value is 65280 */ 988 uint8_t buf_size[2]; 989 uint8_t reserved_1[8]; 990 uint8_t queue_size[2]; /* 8-1024 */ 991 uint8_t low_water_mark[2]; 992 uint8_t queue_address[8]; 993 uint8_t queue_inpointer[2]; 994 uint8_t fast_post_reg_count[2]; /* 0-14 */ 995 uint8_t cc[2]; 996 uint8_t reserved_2[28]; 997 } ql_ip_init_cb_t; 998 999 #define IP_ICB_24XX_VERSION 1 1000 typedef struct ql_ip_init_24xx_cb { 1001 uint8_t version; 1002 uint8_t reserved; 1003 /* 1004 * LSB BIT 2 = allow out of receive buffers AE 1005 */ 1006 uint8_t ip_firmware_options[2]; 1007 uint8_t ip_header_size[2]; 1008 uint8_t mtu_size[2]; 1009 uint8_t buf_size[2]; 1010 uint8_t reserved_1[10]; 1011 uint8_t low_water_mark[2]; 1012 uint8_t reserved_3[12]; 1013 uint8_t cc[2]; 1014 uint8_t reserved_2[28]; 1015 } ql_ip_init_24xx_cb_t; 1016 1017 typedef union ql_comb_ip_init_cb { 1018 ql_ip_init_cb_t cb; 1019 ql_ip_init_24xx_cb_t cb24; 1020 } ql_comb_ip_init_cb_t; 1021 1022 /* 1023 * f/w module table 1024 */ 1025 struct fw_table { 1026 uint16_t fw_class; 1027 int8_t *fw_version; 1028 }; 1029 1030 /* 1031 * aif function table 1032 */ 1033 typedef struct ql_ifunc { 1034 uint_t (*ifunc)(); 1035 } ql_ifunc_t; 1036 1037 #define QL_MSIX_AIF 0x0 1038 #define QL_MSIX_RSPQ 0x1 1039 #define QL_MSIX_MAXAIF QL_MSIX_RSPQ + 1 1040 1041 /* 1042 * DMA memory type. 1043 */ 1044 typedef enum mem_alloc_type { 1045 UNKNOWN_MEMORY, 1046 TASK_MEMORY, 1047 LITTLE_ENDIAN_DMA, 1048 BIG_ENDIAN_DMA, 1049 KERNEL_MEM, 1050 NO_SWAP_DMA, 1051 STRUCT_BUF_MEMORY 1052 } mem_alloc_type_t; 1053 1054 /* 1055 * DMA memory alignment type. 1056 */ 1057 typedef enum men_align_type { 1058 QL_DMA_DATA_ALIGN, 1059 QL_DMA_RING_ALIGN, 1060 } mem_alignment_t; 1061 1062 /* 1063 * DMA memory object. 1064 */ 1065 typedef struct dma_mem { 1066 uint64_t alignment; 1067 void *bp; 1068 ddi_dma_cookie_t *cookies; 1069 ddi_acc_handle_t acc_handle; 1070 ddi_dma_handle_t dma_handle; 1071 ddi_dma_cookie_t cookie; 1072 uint32_t cookie_count; 1073 uint32_t size; 1074 uint32_t memflags; 1075 mem_alloc_type_t type; 1076 uint32_t flags; /* Solaris DMA flags. */ 1077 } dma_mem_t; 1078 1079 /* 1080 * dma_mem_t memflags defines 1081 */ 1082 #define MFLG_32BIT_ONLY BIT_0 1083 1084 /* 1085 * 24 bit port ID type definition. 1086 */ 1087 typedef union { 1088 struct { 1089 uint8_t d_id[3]; 1090 uint8_t rsvd_1; 1091 }r; 1092 1093 uint32_t b24 : 24; 1094 1095 #if defined(_BIT_FIELDS_LTOH) 1096 struct { 1097 uint8_t al_pa; 1098 uint8_t area; 1099 uint8_t domain; 1100 uint8_t rsvd_1; 1101 }b; 1102 #elif defined(_BIT_FIELDS_HTOL) 1103 struct { 1104 uint8_t domain; 1105 uint8_t area; 1106 uint8_t al_pa; 1107 uint8_t rsvd_1; 1108 }b; 1109 #else 1110 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined 1111 #endif 1112 } port_id_t; 1113 1114 /* 1115 * Link list definitions. 1116 */ 1117 typedef struct ql_link { 1118 struct ql_link *prev; 1119 struct ql_link *next; 1120 void *base_address; 1121 struct ql_head *head; /* the queue this link is on */ 1122 } ql_link_t; 1123 1124 typedef struct ql_head { 1125 ql_link_t *first; 1126 ql_link_t *last; 1127 } ql_head_t; 1128 1129 /* 1130 * This is the per-command structure 1131 */ 1132 typedef struct ql_srb { 1133 /* Command link. */ 1134 ql_link_t cmd; 1135 1136 /* Watchdog link and timer. */ 1137 ql_link_t wdg; 1138 time_t wdg_q_time; 1139 time_t init_wdg_q_time; 1140 uint16_t isp_timeout; 1141 1142 /* FCA and FC Transport data. */ 1143 fc_packet_t *pkt; 1144 struct ql_adapter_state *ha; 1145 uint32_t magic_number; 1146 1147 /* unsolicited buffer context. */ 1148 dma_mem_t ub_buffer; 1149 uint32_t ub_type; 1150 uint32_t ub_size; 1151 1152 /* FCP command. */ 1153 fcp_cmd_t *fcp; 1154 1155 /* Request sense. */ 1156 uint32_t request_sense_length; 1157 caddr_t request_sense_ptr; 1158 1159 /* Device queue pointer. */ 1160 struct ql_lun *lun_queue; 1161 1162 /* Command state/status flags. */ 1163 volatile uint32_t flags; 1164 1165 /* Command IOCB context. */ 1166 void (*iocb)(struct ql_adapter_state *, 1167 struct ql_srb *, void *); 1168 uint32_t handle; 1169 uint16_t req_cnt; 1170 uint8_t retry_count; 1171 } ql_srb_t; 1172 1173 #define SRB_ISP_STARTED BIT_0 /* Command sent to ISP. */ 1174 #define SRB_ISP_COMPLETED BIT_1 /* ISP finished with command. */ 1175 #define SRB_RETRY BIT_2 /* Driver retrying command. */ 1176 #define SRB_POLL BIT_3 /* Poll for completion. */ 1177 #define SRB_WATCHDOG_ENABLED BIT_4 /* Command on watchdog list. */ 1178 #define SRB_ABORT BIT_5 /* SRB to be aborted. */ 1179 #define SRB_UB_IN_FCA BIT_6 /* FCA holds unsolicited buffer */ 1180 #define SRB_UB_IN_ISP BIT_7 /* ISP holds unsolicited buffer */ 1181 #define SRB_UB_CALLBACK BIT_8 /* Unsolicited callback needed. */ 1182 #define SRB_UB_RSCN BIT_9 /* Unsolicited RSCN callback. */ 1183 #define SRB_UB_FCP BIT_10 /* Unsolicited RSCN callback. */ 1184 #define SRB_FCP_CMD_PKT BIT_11 /* FCP command type packet. */ 1185 #define SRB_FCP_DATA_PKT BIT_12 /* FCP data type packet. */ 1186 #define SRB_FCP_RSP_PKT BIT_13 /* FCP response type packet. */ 1187 #define SRB_IP_PKT BIT_14 /* IP type packet. */ 1188 #define SRB_GENERIC_SERVICES_PKT BIT_15 /* Generic services type packet */ 1189 #define SRB_COMMAND_TIMEOUT BIT_16 /* Command timed out. */ 1190 #define SRB_ABORTING BIT_17 /* SRB aborting. */ 1191 #define SRB_IN_DEVICE_QUEUE BIT_18 /* In Device Queue */ 1192 #define SRB_IN_TOKEN_ARRAY BIT_19 /* In Token Array */ 1193 #define SRB_UB_FREE_REQUESTED BIT_20 /* UB Free requested */ 1194 #define SRB_UB_ACQUIRED BIT_21 /* UB selected for upcall */ 1195 #define SRB_MS_PKT BIT_22 /* Management Service pkt */ 1196 #define SRB_ELS_PKT BIT_23 /* Extended Link Services pkt */ 1197 1198 /* 1199 * This byte will be used to define flags for the LUN on the target. 1200 * Presently, we have untagged-command as one flag. Others can be 1201 * added later, if needed. 1202 */ 1203 typedef struct tgt_lun_flags { 1204 uint8_t 1205 untagged_pending:1, 1206 unused_bits:7; 1207 } tgt_lun_flags_t; 1208 1209 #define QL_IS_UNTAGGED_PENDING(q, lun_num) \ 1210 ((q->lun_flags[lun_num].untagged_pending == TRUE) ? 1 : 0) 1211 #define QL_SET_UNTAGGED_PENDING(q, lun_num) \ 1212 (q->lun_flags[lun_num].untagged_pending = TRUE) 1213 #define QL_CLEAR_UNTAGGED_PENDING(q, lun_num) \ 1214 (q->lun_flags[lun_num].untagged_pending = FALSE) 1215 1216 /* 1217 * Fibre Channel LUN Queue structure 1218 */ 1219 typedef struct ql_lun { 1220 /* Head command link. */ 1221 ql_head_t cmd; 1222 1223 struct ql_target *target_queue; 1224 1225 uint32_t flags; 1226 1227 /* LUN execution throttle. */ 1228 uint16_t lun_outcnt; 1229 1230 uint16_t lun_no; 1231 1232 ql_link_t link; 1233 } ql_lun_t; 1234 1235 /* 1236 * LUN Queue flags 1237 */ 1238 #define LQF_UNTAGGED_PENDING BIT_0 1239 1240 /* 1241 * Fibre Channel Device Queue structure 1242 */ 1243 typedef struct ql_target { 1244 /* Device queue lock. */ 1245 kmutex_t mutex; 1246 1247 /* Head target command link. */ 1248 ql_head_t tgt_cmd; 1249 1250 volatile uint32_t flags; 1251 port_id_t d_id; 1252 uint16_t loop_id; 1253 volatile uint16_t outcnt; /* # of cmds running in ISP */ 1254 uint32_t iidma_rate; 1255 1256 /* Device link. */ 1257 ql_link_t device; 1258 1259 /* Head watchdog link. */ 1260 ql_head_t wdg; 1261 1262 /* Unsolicited buffer IP data. */ 1263 uint32_t ub_frame_ro; 1264 uint16_t ub_sequence_length; 1265 uint16_t ub_loop_id; 1266 uint8_t ub_total_seg_cnt; 1267 uint8_t ub_seq_cnt; 1268 uint8_t ub_seq_id; 1269 1270 /* Port down retry counter. */ 1271 uint16_t port_down_retry_count; 1272 uint16_t qfull_retry_count; 1273 1274 /* logout sent state */ 1275 uint8_t logout_sent; 1276 1277 /* Data from Port database matches machine type. */ 1278 uint8_t master_state; 1279 uint8_t slave_state; 1280 port_id_t hard_addr; 1281 uint8_t port_name[8]; 1282 uint8_t node_name[8]; 1283 uint16_t cmn_features; 1284 uint16_t conc_sequences; 1285 uint16_t relative_offset; 1286 uint16_t class3_recipient_ctl; 1287 uint16_t class3_rcv_data_size; 1288 uint16_t class3_conc_sequences; 1289 uint16_t class3_open_sequences_per_exch; 1290 uint16_t prli_payload_length; 1291 uint16_t prli_svc_param_word_0; 1292 uint16_t prli_svc_param_word_3; 1293 1294 /* LUN context. */ 1295 ql_head_t lun_queues; 1296 ql_lun_t *last_lun_queue; 1297 } ql_tgt_t; 1298 1299 /* 1300 * Target Queue flags 1301 */ 1302 #define TQF_TAPE_DEVICE BIT_0 1303 #define TQF_QUEUE_SUSPENDED BIT_1 /* Queue suspended. */ 1304 #define TQF_FABRIC_DEVICE BIT_2 1305 #define TQF_INITIATOR_DEVICE BIT_3 1306 #define TQF_RSCN_RCVD BIT_4 1307 #define TQF_NEED_AUTHENTICATION BIT_5 1308 #define TQF_PLOGI_PROGRS BIT_6 1309 #define TQF_IIDMA_NEEDED BIT_7 1310 /* 1311 * Tempoary N_Port information 1312 */ 1313 typedef struct ql_n_port_info { 1314 uint16_t n_port_handle; 1315 uint8_t port_name[8]; /* Big endian. */ 1316 uint8_t node_name[8]; /* Big endian. */ 1317 } ql_n_port_info_t; 1318 1319 /* 1320 * iiDMA 1321 */ 1322 #define IIDMA_RATE_INIT 0xffffffff /* init state */ 1323 #define IIDMA_RATE_NDEF 0xfffffffe /* not defined in conf file */ 1324 #define IIDMA_RATE_1GB 0x0 1325 #define IIDMA_RATE_2GB 0x1 1326 #define IIDMA_RATE_4GB 0x3 1327 #define IIDMA_RATE_8GB 0x4 1328 #define IIDMA_RATE_10GB 0x13 1329 #define IIDMA_RATE_MAX IIDMA_RATE_10GB 1330 1331 /* 1332 * Kernel statistic structure definitions. 1333 */ 1334 typedef struct ql_device_stat { 1335 int logouts_recvd; 1336 int task_mgmt_failures; 1337 int data_ro_mismatches; 1338 int dl_len_mismatches; 1339 } ql_device_stat_t; 1340 1341 typedef struct ql_adapter_24xx_stat { 1342 int version; /* version of this struct */ 1343 int lip_count; /* lips forced */ 1344 int ncmds; /* outstanding commands */ 1345 ql_adapter_revlvl_t revlvl; /* adapter revision levels */ 1346 ql_device_stat_t d_stats[MAX_24_FIBRE_DEVICES]; /* per device stats */ 1347 } ql_adapter_stat_t; 1348 1349 /* 1350 * Firmware code segment. 1351 */ 1352 #define MAX_RISC_CODE_SEGMENTS 3 1353 typedef struct fw_code { 1354 caddr_t code; 1355 uint32_t addr; 1356 uint32_t length; 1357 } ql_fw_code_t; 1358 1359 /* diagnostic els ECHO defines */ 1360 #define QL_ECHO_CMD 0x10000000 /* echo opcode */ 1361 #define QL_ECHO_CMD_LENGTH 220 /* command length */ 1362 1363 /* DUMP state flags. */ 1364 #define QL_DUMPING BIT_0 1365 #define QL_DUMP_VALID BIT_1 1366 #define QL_DUMP_UPLOADED BIT_2 1367 1368 typedef struct el_trace_desc { 1369 kmutex_t mutex; 1370 uint16_t next; 1371 uint32_t trace_buffer_size; 1372 char *trace_buffer; 1373 } el_trace_desc_t; 1374 1375 /* 1376 * NVRAM cache descriptor. 1377 */ 1378 typedef struct nvram_cache_desc { 1379 kmutex_t mutex; 1380 uint32_t valid; 1381 uint32_t size; 1382 void *cache; 1383 } nvram_cache_desc_t; 1384 1385 /* 1386 * ql attach progress indication 1387 */ 1388 #define QL_SOFT_STATE_ALLOCED BIT_0 1389 #define QL_REGS_MAPPED BIT_1 1390 #define QL_HBA_BUFFER_SETUP BIT_2 1391 #define QL_MUTEX_CV_INITED BIT_3 1392 #define QL_INTR_ADDED BIT_4 1393 #define QL_CONFIG_SPACE_SETUP BIT_5 1394 #define QL_TASK_DAEMON_STARTED BIT_6 1395 #define QL_KSTAT_CREATED BIT_7 1396 #define QL_MINOR_NODE_CREATED BIT_8 1397 #define QL_FCA_TRAN_ALLOCED BIT_9 1398 #define QL_FCA_ATTACH_DONE BIT_10 1399 #define QL_IOMAP_IOBASE_MAPPED BIT_11 1400 #define QL_N_PORT_INFO_CREATED BIT_12 1401 #define QL_DB_IOBASE_MAPPED BIT_13 1402 /* Device queue head list size (based on AL_PA address). */ 1403 #define DEVICE_HEAD_LIST_SIZE 0x81 1404 1405 struct legacy_intr_set { 1406 uint32_t int_vec_bit; 1407 uint32_t tgt_status_reg; 1408 uint32_t tgt_mask_reg; 1409 uint32_t pci_int_reg; 1410 }; 1411 1412 /* 1413 * Adapter state structure. 1414 */ 1415 typedef struct ql_adapter_state { 1416 ql_link_t hba; 1417 1418 kmutex_t mutex; 1419 volatile uint32_t flags; /* State flags. */ 1420 uint32_t state; 1421 port_id_t d_id; 1422 uint16_t loop_id; 1423 uint8_t topology; 1424 uint16_t sfp_stat; 1425 1426 uint16_t idle_timer; 1427 uint8_t loop_down_abort_time; 1428 uint8_t port_retry_timer; 1429 uint8_t loop_down_timer; 1430 uint8_t watchdog_timer; 1431 uint16_t r_a_tov; /* 2 * R_A_TOV + 5 */ 1432 1433 /* Task Daemon context. */ 1434 callb_cpr_t cprinfo; 1435 kmutex_t task_daemon_mutex; 1436 kcondvar_t cv_dr_suspended; 1437 kcondvar_t cv_task_daemon; 1438 volatile uint32_t task_daemon_flags; 1439 ql_head_t callback_queue; 1440 1441 /* Interrupt context. */ 1442 kmutex_t intr_mutex; 1443 caddr_t iobase; 1444 uint8_t rev_id; 1445 uint16_t device_id; 1446 uint16_t subsys_id; 1447 uint16_t subven_id; 1448 uint16_t ven_id; 1449 uint16_t fw_class; 1450 ql_srb_t *status_srb; 1451 volatile uint8_t intr_claimed; 1452 1453 /* 1454 * ISP request queue, response queue, mailbox buffer and 1455 * IP receive queue buffer. 1456 */ 1457 dma_mem_t hba_buf; 1458 1459 /* ISP request queue context. */ 1460 kmutex_t req_ring_mutex; 1461 struct cmd_entry *request_ring_bp; 1462 struct cmd_entry *request_ring_ptr; 1463 uint64_t request_dvma; 1464 uint16_t req_ring_index; 1465 uint16_t req_q_cnt; /* # of available entries. */ 1466 ql_head_t pending_cmds; 1467 ql_srb_t **outstanding_cmds; 1468 uint16_t osc_index; 1469 1470 /* ISP response queue context. */ 1471 struct sts_entry *response_ring_bp; 1472 struct sts_entry *response_ring_ptr; 1473 uint64_t response_dvma; 1474 uint16_t rsp_ring_index; 1475 uint16_t isp_rsp_index; 1476 1477 /* Mailbox context. */ 1478 kmutex_t mbx_mutex; 1479 caddr_t mbx_bp; 1480 struct mbx_cmd *mcp; 1481 kcondvar_t cv_mbx_wait; 1482 kcondvar_t cv_mbx_intr; 1483 volatile uint8_t mailbox_flags; 1484 1485 /* ISP receive buffer queue context. */ 1486 ql_tgt_t *rcv_dev_q; 1487 struct rcvbuf *rcvbuf_ring_bp; 1488 struct rcvbuf *rcvbuf_ring_ptr; 1489 uint64_t rcvbuf_dvma; 1490 uint16_t rcvbuf_ring_index; 1491 1492 /* Unsolicited buffer data. */ 1493 uint16_t ub_outcnt; 1494 uint8_t ub_seq_id; 1495 uint8_t ub_command_count; 1496 uint8_t ub_notify_count; 1497 uint32_t ub_allocated; 1498 kmutex_t ub_mutex; 1499 kcondvar_t cv_ub; 1500 fc_unsol_buf_t **ub_array; 1501 1502 /* Head of device queue list. */ 1503 ql_head_t *dev; 1504 1505 /* Kernel statistics. */ 1506 kstat_t *k_stats; 1507 ql_adapter_stat_t *adapter_stats; 1508 1509 /* Solaris adapter configuration data */ 1510 ddi_acc_handle_t dev_handle; 1511 ddi_acc_handle_t pci_handle; /* config space */ 1512 ddi_acc_handle_t iomap_dev_handle; 1513 caddr_t iomap_iobase; 1514 dev_info_t *dip; 1515 ddi_iblock_cookie_t iblock_cookie; 1516 fc_fca_tran_t *tran; 1517 uint32_t instance; 1518 int8_t *devpath; 1519 uint32_t fru_hba_index; 1520 uint32_t fru_port_index; 1521 uint8_t adapInfo[18]; 1522 1523 /* Adapter context */ 1524 la_els_logi_t loginparams; 1525 fc_fca_bind_info_t bind_info; 1526 ddi_modhandle_t fw_module; 1527 uint32_t fw_major_version; 1528 uint32_t fw_minor_version; 1529 uint32_t fw_subminor_version; 1530 uint16_t fw_attributes; 1531 uint32_t fw_ext_memory_size; 1532 uint32_t parity_pause_errors; 1533 boolean_t log_parity_pause; 1534 uint16_t parity_hccr_err; 1535 uint32_t parity_stat_err; 1536 reg_off_t *reg_off; 1537 caddr_t risc_code; 1538 uint32_t risc_code_size; 1539 ql_fw_code_t risc_fw[MAX_RISC_CODE_SEGMENTS]; 1540 uint32_t risc_dump_size; 1541 void (*fcp_cmd)(struct ql_adapter_state *, 1542 ql_srb_t *, void *); 1543 void (*ip_cmd)(struct ql_adapter_state *, 1544 ql_srb_t *, void *); 1545 void (*ms_cmd)(struct ql_adapter_state *, 1546 ql_srb_t *, void *); 1547 uint8_t cmd_segs; 1548 uint8_t cmd_cont_segs; 1549 1550 /* NVRAM configuration data */ 1551 uint32_t cfg_flags; 1552 ql_comb_init_cb_t init_ctrl_blk; 1553 ql_comb_ip_init_cb_t ip_init_ctrl_blk; 1554 uint16_t nvram_version; 1555 uint16_t adapter_features; 1556 uint32_t fw_transfer_size; 1557 uint16_t execution_throttle; 1558 uint16_t port_down_retry_count; 1559 uint8_t port_down_retry_delay; 1560 uint8_t qfull_retry_count; 1561 uint8_t qfull_retry_delay; 1562 uint16_t serdes_param[4]; 1563 uint8_t loop_reset_delay; 1564 1565 /* Power management context. */ 1566 kmutex_t pm_mutex; 1567 uint32_t busy; 1568 uint8_t power_level; 1569 uint8_t pm_capable; 1570 uint8_t config_saved; 1571 uint8_t lip_on_panic; 1572 port_id_t port_hard_address; 1573 1574 /* sbus card data */ 1575 caddr_t sbus_fpga_iobase; 1576 ddi_acc_handle_t sbus_fpga_dev_handle; 1577 ddi_acc_handle_t sbus_config_handle; 1578 caddr_t sbus_config_base; 1579 1580 /* XIOCTL context pointer. */ 1581 struct ql_xioctl *xioctl; 1582 1583 kmutex_t cache_mutex; 1584 struct ql_fcache *fcache; 1585 int8_t *vcache; 1586 1587 /* AIF (Advanced Interrupt Framework) support */ 1588 ddi_intr_handle_t *htable; 1589 uint32_t hsize; 1590 int32_t intr_cnt; 1591 uint32_t intr_pri; 1592 int32_t intr_cap; 1593 uint32_t iflags; 1594 1595 /* PCI maximum read request override */ 1596 uint16_t pci_max_read_req; 1597 1598 /* port manage mutex */ 1599 kmutex_t portmutex; 1600 uint16_t maximum_luns_per_target; 1601 1602 /* f/w dump mutex */ 1603 uint32_t ql_dump_size; 1604 uint32_t ql_dump_state; 1605 void *ql_dump_ptr; 1606 kmutex_t dump_mutex; 1607 1608 uint8_t fwwait; 1609 1610 dma_mem_t fwexttracebuf; /* extended trace */ 1611 dma_mem_t fwfcetracebuf; /* event trace */ 1612 uint32_t fwfcetraceopt; 1613 uint32_t flash_errlog_start; /* 32bit word addr */ 1614 uint32_t flash_errlog_ptr; /* 32bit word addr */ 1615 uint8_t send_plogi_timer; 1616 1617 /* Virtual port context. */ 1618 fca_port_attrs_t *pi_attrs; 1619 struct ql_adapter_state *pha; 1620 struct ql_adapter_state *vp_next; 1621 uint8_t vp_index; 1622 1623 uint16_t free_loop_id; 1624 1625 /* Tempoary N_Port information */ 1626 struct ql_n_port_info *n_port; 1627 1628 void (*els_cmd)(struct ql_adapter_state *, 1629 ql_srb_t *, void *); 1630 el_trace_desc_t *el_trace_desc; 1631 1632 uint32_t flash_data_addr; 1633 uint32_t flash_fw_addr; 1634 uint32_t flash_golden_fw_addr; 1635 uint32_t flash_vpd_addr; 1636 uint32_t flash_nvram_addr; 1637 uint32_t flash_desc_addr; 1638 uint32_t mpi_capability_list; 1639 uint8_t phy_fw_major_version; 1640 uint8_t phy_fw_minor_version; 1641 uint8_t phy_fw_subminor_version; 1642 uint8_t mpi_fw_major_version; 1643 uint8_t mpi_fw_minor_version; 1644 uint8_t mpi_fw_subminor_version; 1645 1646 uint8_t idc_flash_acc; 1647 uint8_t idc_restart_mpi; 1648 uint16_t idc_mb[8]; 1649 uint8_t restart_mpi_timer; 1650 uint8_t flash_acc_timer; 1651 1652 /* VLAN ID and MAC address */ 1653 uint8_t fcoe_vnport_mac[6]; 1654 uint16_t fabric_params; 1655 uint16_t fcoe_vlan_id; 1656 uint16_t fcoe_fcf_idx; 1657 nvram_cache_desc_t *nvram_cache; 1658 uint32_t async_event_wait; 1659 1660 /* NetXen context */ 1661 ddi_acc_handle_t db_dev_handle; 1662 caddr_t db_iobase; 1663 uint64_t first_page_group_start; 1664 uint64_t first_page_group_end; 1665 uint64_t mn_win_crb; 1666 caddr_t nx_pcibase; /* BAR0 base I/O address */ 1667 uint32_t crb_win; 1668 uint32_t ddr_mn_window; 1669 uint32_t qdr_sn_window; 1670 uint32_t *nx_req_in; 1671 caddr_t db_read; 1672 uint32_t pci_bus_addr; 1673 struct legacy_intr_set nx_legacy_intr; 1674 uint32_t bootloader_size; 1675 uint32_t bootloader_addr; 1676 uint32_t flash_fw_size; 1677 uint8_t function_number; 1678 } ql_adapter_state_t; 1679 1680 /* 1681 * adapter state flags 1682 */ 1683 #define FCA_BOUND BIT_0 1684 #define QL_OPENED BIT_1 1685 #define ONLINE BIT_2 1686 #define INTERRUPTS_ENABLED BIT_3 1687 #define ABORT_CMDS_LOOP_DOWN_TMO BIT_4 1688 #define POINT_TO_POINT BIT_5 1689 #define IP_ENABLED BIT_6 1690 #define IP_INITIALIZED BIT_7 1691 #define MENLO_LOGIN_OPERATIONAL BIT_8 1692 #define ADAPTER_SUSPENDED BIT_9 1693 #define ADAPTER_TIMER_BUSY BIT_10 1694 #define PARITY_ERROR BIT_11 1695 #define FLASH_ERRLOG_MARKER BIT_12 1696 #define VP_ENABLED BIT_13 1697 #define FDISC_ENABLED BIT_14 1698 #define FUNCTION_1 BIT_15 1699 #define MPI_RESET_NEEDED BIT_16 1700 1701 /* 1702 * task daemon flags 1703 */ 1704 #define TASK_DAEMON_STOP_FLG BIT_0 1705 #define TASK_DAEMON_SLEEPING_FLG BIT_1 1706 #define TASK_DAEMON_ALIVE_FLG BIT_2 1707 #define TASK_DAEMON_IDLE_CHK_FLG BIT_3 1708 #define SUSPENDED_WAKEUP_FLG BIT_4 1709 #define FC_STATE_CHANGE BIT_5 1710 #define NEED_UNSOLICITED_BUFFERS BIT_6 1711 #define RESET_MARKER_NEEDED BIT_7 1712 #define RESET_ACTIVE BIT_8 1713 #define ISP_ABORT_NEEDED BIT_9 1714 #define ABORT_ISP_ACTIVE BIT_10 1715 #define LOOP_RESYNC_NEEDED BIT_11 1716 #define LOOP_RESYNC_ACTIVE BIT_12 1717 #define LOOP_DOWN BIT_13 1718 #define DRIVER_STALL BIT_14 1719 #define COMMAND_WAIT_NEEDED BIT_15 1720 #define COMMAND_WAIT_ACTIVE BIT_16 1721 #define STATE_ONLINE BIT_17 1722 #define ABORT_QUEUES_NEEDED BIT_18 1723 #define TASK_DAEMON_STALLED_FLG BIT_19 1724 #define TASK_THREAD_CALLED BIT_20 1725 #define FIRMWARE_UP BIT_21 1726 #define LIP_RESET_PENDING BIT_22 1727 #define FIRMWARE_LOADED BIT_23 1728 #define RSCN_UPDATE_NEEDED BIT_24 1729 #define HANDLE_PORT_BYPASS_CHANGE BIT_25 1730 #define PORT_RETRY_NEEDED BIT_26 1731 #define TASK_DAEMON_POWERING_DOWN BIT_27 1732 #define TD_IIDMA_NEEDED BIT_28 1733 #define SEND_PLOGI BIT_29 1734 #define IDC_ACK_NEEDED BIT_30 1735 1736 /* 1737 * Mailbox flags 1738 */ 1739 #define MBX_WANT_FLG BIT_0 1740 #define MBX_BUSY_FLG BIT_1 1741 #define MBX_INTERRUPT BIT_2 1742 #define MBX_ABORT BIT_3 1743 1744 /* 1745 * Configuration flags 1746 */ 1747 #define CFG_ENABLE_HARD_ADDRESS BIT_0 1748 #define CFG_ENABLE_64BIT_ADDRESSING BIT_1 1749 #define CFG_ENABLE_LIP_RESET BIT_2 1750 #define CFG_ENABLE_FULL_LIP_LOGIN BIT_3 1751 #define CFG_ENABLE_TARGET_RESET BIT_4 1752 #define CFG_ENABLE_LINK_DOWN_REPORTING BIT_5 1753 #define CFG_DISABLE_EXTENDED_LOGGING_TRACE BIT_6 1754 #define CFG_ENABLE_FCP_2_SUPPORT BIT_7 1755 #define CFG_MULTI_CHIP_ADAPTER BIT_8 1756 #define CFG_SBUS_CARD BIT_9 1757 #define CFG_CTRL_2300 BIT_10 1758 #define CFG_CTRL_6322 BIT_11 1759 #define CFG_CTRL_2200 BIT_12 1760 #define CFG_CTRL_2422 BIT_13 1761 #define CFG_CTRL_25XX BIT_14 1762 #define CFG_ENABLE_EXTENDED_LOGGING BIT_15 1763 #define CFG_DISABLE_RISC_CODE_LOAD BIT_16 1764 #define CFG_SET_CACHE_LINE_SIZE_1 BIT_17 1765 #define CFG_CTRL_MENLO BIT_18 1766 #define CFG_EXT_FW_INTERFACE BIT_19 1767 #define CFG_LOAD_FLASH_FW BIT_20 1768 #define CFG_DUMP_MAILBOX_TIMEOUT BIT_21 1769 #define CFG_DUMP_ISP_SYSTEM_ERROR BIT_22 1770 #define CFG_DUMP_DRIVER_COMMAND_TIMEOUT BIT_23 1771 #define CFG_DUMP_LOOP_OFFLINE_TIMEOUT BIT_24 1772 #define CFG_ENABLE_FWEXTTRACE BIT_25 1773 #define CFG_ENABLE_FWFCETRACE BIT_26 1774 #define CFG_FW_MISMATCH BIT_27 1775 #define CFG_CTRL_81XX BIT_28 1776 #define CFG_CTRL_8021 BIT_29 1777 #define CFG_FAST_TIMEOUT BIT_30 1778 #define CFG_LR_SUPPORT BIT_31 1779 1780 #define CFG_CTRL_2425 (CFG_CTRL_2422 | CFG_CTRL_25XX) 1781 #define CFG_CTRL_8081 (CFG_CTRL_8021 | CFG_CTRL_81XX) 1782 #define CFG_CTRL_2581 (CFG_CTRL_25XX | CFG_CTRL_81XX) 1783 #define CFG_CTRL_242581 (CFG_CTRL_2422 | CFG_CTRL_25XX | CFG_CTRL_81XX) 1784 #define CFG_CTRL_24258081 (CFG_CTRL_2425 | CFG_CTRL_8081) 1785 #define CFG_CTRL_258081 (CFG_CTRL_25XX | CFG_CTRL_8081) 1786 #define CFG_CTRL_2480 (CFG_CTRL_2422 | CFG_CTRL_8021) 1787 1788 #define CFG_IST(ha, cfgflags) (ha->cfg_flags & cfgflags) 1789 1790 /* 1791 * Interrupt configuration flags 1792 */ 1793 #define IFLG_INTR_LEGACY BIT_0 1794 #define IFLG_INTR_FIXED BIT_1 1795 #define IFLG_INTR_MSI BIT_2 1796 #define IFLG_INTR_MSIX BIT_3 1797 1798 #define IFLG_INTR_AIF (IFLG_INTR_MSI | IFLG_INTR_FIXED | IFLG_INTR_MSIX) 1799 1800 /* 1801 * Macros to help code, maintain, etc. 1802 */ 1803 #define LSB(x) (uint8_t)(x) 1804 #define MSB(x) (uint8_t)((uint16_t)(x) >> 8) 1805 #define MSW(x) (uint16_t)((uint32_t)(x) >> 16) 1806 #define LSW(x) (uint16_t)(x) 1807 #define LSD(x) (uint32_t)(x) 1808 #define MSD(x) (uint32_t)((uint64_t)(x) >> 32) 1809 1810 #define SHORT_TO_LONG(lsw, msw) (uint32_t)((uint16_t)msw << 16 | (uint16_t)lsw) 1811 #define CHAR_TO_SHORT(lsb, msb) (uint16_t)((uint8_t)msb << 8 | (uint8_t)lsb) 1812 #define CHAR_TO_LONG(lsb, b1, b2, msb) \ 1813 (uint32_t)(SHORT_TO_LONG(CHAR_TO_SHORT(lsb, b1), \ 1814 CHAR_TO_SHORT(b2, msb))) 1815 1816 /* Little endian machine correction defines. */ 1817 #ifdef _LITTLE_ENDIAN 1818 #define LITTLE_ENDIAN_16(x) 1819 #define LITTLE_ENDIAN_24(x) 1820 #define LITTLE_ENDIAN_32(x) 1821 #define LITTLE_ENDIAN_64(x) 1822 #define LITTLE_ENDIAN(bp, bytes) 1823 #define BIG_ENDIAN_16(x) ql_chg_endian((uint8_t *)x, 2) 1824 #define BIG_ENDIAN_24(x) ql_chg_endian((uint8_t *)x, 3) 1825 #define BIG_ENDIAN_32(x) ql_chg_endian((uint8_t *)x, 4) 1826 #define BIG_ENDIAN_64(x) ql_chg_endian((uint8_t *)x, 8) 1827 #define BIG_ENDIAN(bp, bytes) ql_chg_endian((uint8_t *)bp, bytes) 1828 #endif /* _LITTLE_ENDIAN */ 1829 1830 /* Big endian machine correction defines. */ 1831 #ifdef _BIG_ENDIAN 1832 #define LITTLE_ENDIAN_16(x) ql_chg_endian((uint8_t *)x, 2) 1833 #define LITTLE_ENDIAN_24(x) ql_chg_endian((uint8_t *)x, 3) 1834 #define LITTLE_ENDIAN_32(x) ql_chg_endian((uint8_t *)x, 4) 1835 #define LITTLE_ENDIAN_64(x) ql_chg_endian((uint8_t *)x, 8) 1836 #define LITTLE_ENDIAN(bp, bytes) ql_chg_endian((uint8_t *)bp, bytes) 1837 #define BIG_ENDIAN_16(x) 1838 #define BIG_ENDIAN_24(x) 1839 #define BIG_ENDIAN_32(x) 1840 #define BIG_ENDIAN_64(x) 1841 #define BIG_ENDIAN(bp, bytes) 1842 #endif /* _BIG_ENDIAN */ 1843 1844 #define LOCAL_LOOP_ID(x) (x <= LAST_LOCAL_LOOP_ID) 1845 1846 #define FABRIC_LOOP_ID(x) (x == FL_PORT_LOOP_ID || \ 1847 x == SIMPLE_NAME_SERVER_LOOP_ID) 1848 1849 #define SNS_LOOP_ID(x) (x >= SNS_FIRST_LOOP_ID && \ 1850 x <= SNS_LAST_LOOP_ID) 1851 1852 #define BROADCAST_LOOP_ID(x) (x == IP_BROADCAST_LOOP_ID) 1853 1854 #define VALID_LOOP_ID(x) (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x) || \ 1855 FABRIC_LOOP_ID(x) || BROADCAST_LOOP_ID(x)) 1856 1857 #define VALID_N_PORT_HDL(x) (x <= LAST_N_PORT_HDL || \ 1858 (x >= SNS_24XX_HDL && x <= BROADCAST_24XX_HDL)) 1859 1860 #define VALID_DEVICE_ID(ha, x) (CFG_IST(ha, CFG_CTRL_24258081) ? \ 1861 VALID_N_PORT_HDL(x) : VALID_LOOP_ID(x)) 1862 1863 #define VALID_TARGET_ID(ha, x) (CFG_IST(ha, CFG_CTRL_24258081) ? \ 1864 (x <= LAST_N_PORT_HDL) : (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x))) 1865 1866 #define RESERVED_LOOP_ID(ha, x) (CFG_IST(ha, CFG_CTRL_24258081) ? \ 1867 (x > LAST_N_PORT_HDL && x <= FL_PORT_24XX_HDL) : \ 1868 (x >= FL_PORT_LOOP_ID && x <= SIMPLE_NAME_SERVER_LOOP_ID)) 1869 1870 #define QL_LOOP_TRANSITION (RESET_MARKER_NEEDED | RESET_ACTIVE | \ 1871 ISP_ABORT_NEEDED | ABORT_ISP_ACTIVE | \ 1872 LOOP_RESYNC_NEEDED | LOOP_RESYNC_ACTIVE | \ 1873 COMMAND_WAIT_NEEDED | COMMAND_WAIT_ACTIVE) 1874 1875 #define QL_SUSPENDED (QL_LOOP_TRANSITION | LOOP_DOWN | DRIVER_STALL) 1876 1877 #define LOOP_RECONFIGURE(ha) (ha->task_daemon_flags & (QL_LOOP_TRANSITION | \ 1878 DRIVER_STALL)) 1879 1880 #define DRIVER_SUSPENDED(ha) (ha->task_daemon_flags & QL_SUSPENDED) 1881 1882 #define LOOP_NOT_READY(ha) (ha->task_daemon_flags & (QL_LOOP_TRANSITION | \ 1883 LOOP_DOWN)) 1884 1885 #define LOOP_READY(ha) (LOOP_NOT_READY(ha) == 0) 1886 1887 #define QL_TASK_PENDING(ha) ( \ 1888 ha->task_daemon_flags & (QL_LOOP_TRANSITION | ABORT_QUEUES_NEEDED | \ 1889 PORT_RETRY_NEEDED) || ha->callback_queue.first != NULL) 1890 1891 #define QL_DAEMON_NOT_ACTIVE(ha) ( \ 1892 !(ha->task_daemon_flags & TASK_DAEMON_ALIVE_FLG) || \ 1893 ha->task_daemon_flags & (TASK_DAEMON_SLEEPING_FLG | \ 1894 TASK_DAEMON_STOP_FLG)) 1895 1896 #define QL_DAEMON_SUSPENDED(ha) (\ 1897 (((ha)->cprinfo.cc_events & CALLB_CPR_START) ||\ 1898 ((ha)->flags & ADAPTER_SUSPENDED))) 1899 1900 #define INTERRUPT_PENDING(ha) (CFG_IST(ha, CFG_CTRL_8021) ? \ 1901 RD32_IO_REG(ha, nx_risc_int) & NX_RISC_INT : \ 1902 RD16_IO_REG(ha, istatus) & RISC_INT) 1903 1904 #define QL_MAX_FRAME_SIZE(ha) \ 1905 (uint16_t)(CFG_IST(ha, CFG_CTRL_24258081) ? CHAR_TO_SHORT( \ 1906 ha->init_ctrl_blk.cb24.max_frame_length[0], \ 1907 ha->init_ctrl_blk.cb24.max_frame_length[1]) : CHAR_TO_SHORT( \ 1908 ha->init_ctrl_blk.cb.max_frame_length[0], \ 1909 ha->init_ctrl_blk.cb.max_frame_length[1])) 1910 1911 /* 1912 * Locking Macro Definitions 1913 */ 1914 #define GLOBAL_STATE_LOCK() mutex_enter(&ql_global_mutex) 1915 #define GLOBAL_STATE_UNLOCK() mutex_exit(&ql_global_mutex) 1916 1917 #define TRY_DEVICE_QUEUE_LOCK(q) mutex_tryenter(&q->mutex) 1918 #define DEVICE_QUEUE_LOCK(q) mutex_enter(&q->mutex) 1919 #define DEVICE_QUEUE_UNLOCK(q) mutex_exit(&q->mutex) 1920 1921 #define TRY_MBX_REGISTER_LOCK(ha) mutex_tryenter(&ha->pha->mbx_mutex) 1922 #define MBX_REGISTER_LOCK_OWNER(ha) mutex_owner(&ha->pha->mbx_mutex) 1923 #define MBX_REGISTER_LOCK(ha) mutex_enter(&ha->pha->mbx_mutex) 1924 #define MBX_REGISTER_UNLOCK(ha) mutex_exit(&ha->pha->mbx_mutex) 1925 1926 #define INTR_LOCK(ha) mutex_enter(&ha->pha->intr_mutex) 1927 #define INTR_UNLOCK(ha) mutex_exit(&ha->pha->intr_mutex) 1928 1929 #define TASK_DAEMON_LOCK(ha) mutex_enter(&ha->pha->task_daemon_mutex) 1930 #define TASK_DAEMON_UNLOCK(ha) mutex_exit(&ha->pha->task_daemon_mutex) 1931 1932 #define REQUEST_RING_LOCK(ha) mutex_enter(&ha->pha->req_ring_mutex) 1933 #define REQUEST_RING_UNLOCK(ha) mutex_exit(&ha->pha->req_ring_mutex) 1934 1935 #define CACHE_LOCK(ha) mutex_enter(&ha->pha->cache_mutex); 1936 #define CACHE_UNLOCK(ha) mutex_exit(&ha->pha->cache_mutex); 1937 1938 #define PORTMANAGE_LOCK(ha) mutex_enter(&ha->pha->portmutex); 1939 #define PORTMANAGE_UNLOCK(ha) mutex_exit(&ha->pha->portmutex); 1940 1941 #define ADAPTER_STATE_LOCK(ha) mutex_enter(&ha->pha->mutex) 1942 #define ADAPTER_STATE_UNLOCK(ha) mutex_exit(&ha->pha->mutex) 1943 1944 #define QL_DUMP_LOCK(ha) mutex_enter(&ha->pha->dump_mutex) 1945 #define QL_DUMP_UNLOCK(ha) mutex_exit(&ha->pha->dump_mutex) 1946 1947 #define QL_PM_LOCK(ha) mutex_enter(&ha->pha->pm_mutex) 1948 #define QL_PM_UNLOCK(ha) mutex_exit(&ha->pha->pm_mutex) 1949 1950 #define QL_UB_LOCK(ha) mutex_enter(&ha->pha->ub_mutex) 1951 #define QL_UB_UNLOCK(ha) mutex_exit(&ha->pha->ub_mutex) 1952 1953 #define GLOBAL_HW_LOCK() mutex_enter(&ql_global_hw_mutex) 1954 #define GLOBAL_HW_UNLOCK() mutex_exit(&ql_global_hw_mutex) 1955 1956 #define NVRAM_CACHE_LOCK(ha) mutex_enter(&ha->nvram_cache->mutex); 1957 #define NVRAM_CACHE_UNLOCK(ha) mutex_exit(&ha->nvram_cache->mutex); 1958 1959 /* 1960 * PCI power management control/status register location 1961 */ 1962 #define QL_PM_CS_REG 0x48 1963 1964 /* 1965 * ql component 1966 */ 1967 #define QL_POWER_COMPONENT 0 1968 1969 typedef struct ql_config_space { 1970 uint16_t chs_command; 1971 uint8_t chs_cache_line_size; 1972 uint8_t chs_latency_timer; 1973 uint8_t chs_header_type; 1974 uint8_t chs_sec_latency_timer; 1975 uint8_t chs_bridge_control; 1976 uint32_t chs_base0; 1977 uint32_t chs_base1; 1978 uint32_t chs_base2; 1979 uint32_t chs_base3; 1980 uint32_t chs_base4; 1981 uint32_t chs_base5; 1982 } ql_config_space_t; 1983 1984 #ifdef USE_DDI_INTERFACES 1985 1986 #define QL_SAVE_CONFIG_REGS(dip) pci_save_config_regs(dip) 1987 #define QL_RESTORE_CONFIG_REGS(dip) pci_restore_config_regs(dip) 1988 1989 #else /* USE_DDI_INTERFACES */ 1990 1991 #define QL_SAVE_CONFIG_REGS(dip) ql_save_config_regs(dip) 1992 #define QL_RESTORE_CONFIG_REGS(dip) ql_restore_config_regs(dip) 1993 1994 #endif /* USE_DDI_INTERFACES */ 1995 1996 #define QL_IS_SET(x, y) (((x) & (y)) == (y)) 1997 1998 /* 1999 * QL local function return status codes 2000 */ 2001 #define QL_SUCCESS 0x4000 2002 #define QL_INVALID_COMMAND 0x4001 2003 #define QL_INTERFACE_ERROR 0x4002 2004 #define QL_TEST_FAILED 0x4003 2005 #define QL_COMMAND_ERROR 0x4005 2006 #define QL_PARAMETER_ERROR 0x4006 2007 #define QL_PORT_ID_USED 0x4007 2008 #define QL_LOOP_ID_USED 0x4008 2009 #define QL_ALL_IDS_IN_USE 0x4009 2010 #define QL_NOT_LOGGED_IN 0x400A 2011 #define QL_LOOP_DOWN 0x400B 2012 #define QL_LOOP_BACK_ERROR 0x400C 2013 #define QL_CHECKSUM_ERROR 0x4010 2014 #define QL_CONSUMED 0x4011 2015 2016 #define QL_FUNCTION_TIMEOUT 0x100 2017 #define QL_FUNCTION_PARAMETER_ERROR 0x101 2018 #define QL_FUNCTION_FAILED 0x102 2019 #define QL_MEMORY_ALLOC_FAILED 0x103 2020 #define QL_FABRIC_NOT_INITIALIZED 0x104 2021 #define QL_LOCK_TIMEOUT 0x105 2022 #define QL_ABORTED 0x106 2023 #define QL_FUNCTION_SUSPENDED 0x107 2024 #define QL_END_OF_DATA 0x108 2025 #define QL_IP_UNSUPPORTED 0x109 2026 #define QL_PM_ERROR 0x10a 2027 #define QL_DATA_EXISTS 0x10b 2028 #define QL_NOT_SUPPORTED 0x10c 2029 #define QL_MEMORY_FULL 0x10d 2030 #define QL_FW_NOT_SUPPORTED 0x10e 2031 #define QL_FWMODLOAD_FAILED 0x10f 2032 #define QL_FWSYM_NOT_FOUND 0x110 2033 #define QL_LOGIN_NOT_SUPPORTED 0x111 2034 2035 /* 2036 * SBus card FPGA register offsets. 2037 */ 2038 #define FPGA_CONF 0x100 2039 #define FPGA_EEPROM_LOADDR 0x102 2040 #define FPGA_EEPROM_HIADDR 0x104 2041 #define FPGA_EEPROM_DATA 0x106 2042 #define FPGA_REVISION 0x108 2043 2044 #define SBUS_FLASH_WRITE_ENABLE 0x0080 2045 #define QL_SBUS_FCODE_SIZE 0x30000 2046 #define QL_FCODE_OFFSET 0 2047 #define QL_FPGA_SIZE 0x40000 2048 #define QL_FPGA_OFFSET 0x40000 2049 2050 #define READ_PORT_ID(addr) ((uint32_t)((((uint32_t)((addr)[0])) << 16) | \ 2051 (((uint32_t)((addr)[1])) << 8) | \ 2052 (((uint32_t)((addr)[2]))))) 2053 #define READ_PORT_NAME(addr) ((u_longlong_t)((((uint64_t)((addr)[0])) << 56) | \ 2054 (((uint64_t)((addr)[1])) << 48) | \ 2055 (((uint64_t)((addr)[2])) << 40) | \ 2056 (((uint64_t)((addr)[3])) << 32) | \ 2057 (((uint64_t)((addr)[4])) << 24) | \ 2058 (((uint64_t)((addr)[5])) << 16) | \ 2059 (((uint64_t)((addr)[6])) << 8) | \ 2060 (((uint64_t)((addr)[7]))))) 2061 /* 2062 * Structure used to associate cmds with strings which describe them. 2063 */ 2064 typedef struct cmd_table_entry { 2065 uint16_t cmd; 2066 char *string; 2067 } cmd_table_t; 2068 2069 /* 2070 * ELS command table initializer 2071 */ 2072 #define ELS_CMD_TABLE() \ 2073 { \ 2074 {LA_ELS_RJT, "LA_ELS_RJT"}, \ 2075 {LA_ELS_ACC, "LA_ELS_ACC"}, \ 2076 {LA_ELS_PLOGI, "LA_ELS_PLOGI"}, \ 2077 {LA_ELS_PDISC, "LA_ELS_PDISC"}, \ 2078 {LA_ELS_FLOGI, "LA_ELS_FLOGI"}, \ 2079 {LA_ELS_FDISC, "LA_ELS_FDISC"}, \ 2080 {LA_ELS_LOGO, "LA_ELS_LOGO"}, \ 2081 {LA_ELS_PRLI, "LA_ELS_PRLI"}, \ 2082 {LA_ELS_PRLO, "LA_ELS_PRLO"}, \ 2083 {LA_ELS_ADISC, "LA_ELS_ADISC"}, \ 2084 {LA_ELS_LINIT, "LA_ELS_LINIT"}, \ 2085 {LA_ELS_LPC, "LA_ELS_LPC"}, \ 2086 {LA_ELS_LSTS, "LA_ELS_LSTS"}, \ 2087 {LA_ELS_SCR, "LA_ELS_SCR"}, \ 2088 {LA_ELS_RSCN, "LA_ELS_RSCN"}, \ 2089 {LA_ELS_FARP_REQ, "LA_ELS_FARP_REQ"}, \ 2090 {LA_ELS_FARP_REPLY, "LA_ELS_FARP_REPLY"}, \ 2091 {LA_ELS_RLS, "LA_ELS_RLS"}, \ 2092 {LA_ELS_RNID, "LA_ELS_RNID"}, \ 2093 {NULL, NULL} \ 2094 } 2095 2096 /* 2097 * ELS Passthru IOCB data segment descriptor. 2098 */ 2099 typedef struct data_seg_desc { 2100 uint32_t addr[2]; 2101 uint32_t length; 2102 } data_seg_desc_t; 2103 2104 /* 2105 * ELS descriptor used to abstract the hosts fibre channel packet 2106 * from the ISP ELS code. 2107 */ 2108 typedef struct els_desc { 2109 uint8_t els; /* the ELS command code */ 2110 ddi_acc_handle_t els_handle; 2111 uint16_t n_port_handle; 2112 port_id_t d_id; 2113 port_id_t s_id; 2114 uint16_t control_flags; 2115 uint32_t cmd_byte_count; 2116 uint32_t rsp_byte_count; 2117 data_seg_desc_t tx_dsd; /* FC frame payload */ 2118 data_seg_desc_t rx_dsd; /* ELS resp payload buffer */ 2119 } els_descriptor_t; 2120 2121 typedef struct prli_svc_pram_resp_page { 2122 uint8_t type_code; 2123 uint8_t type_code_ext; 2124 uint16_t prli_resp_flags; 2125 uint32_t orig_process_associator; 2126 uint32_t resp_process_associator; 2127 uint32_t common_parameters; 2128 } prli_svc_pram_resp_page_t; 2129 2130 /* 2131 * PRLI accept Service Parameter Page Word 3 2132 */ 2133 #define PRLI_W3_WRITE_FCP_XFR_RDY_DISABLED BIT_0 2134 #define PRLI_W3_READ_FCP_XFR_RDY_DISABLED BIT_1 2135 #define PRLI_W3_OBSOLETE_BIT_2 BIT_2 2136 #define PRLI_W3_OBSOLETE_BIT_3 BIT_3 2137 #define PRLI_W3_TARGET_FUNCTION BIT_4 2138 #define PRLI_W3_INITIATOR_FUNCTION BIT_5 2139 #define PRLI_W3_DATA_OVERLAY_ALLOWED BIT_6 2140 #define PRLI_W3_CONFIRMED_COMP_ALLOWED BIT_7 2141 #define PRLI_W3_RETRY BIT_8 2142 #define PRLI_W3_TASK_RETRY_ID_REQUESTED BIT_9 2143 2144 typedef struct prli_acc_resp { 2145 uint8_t ls_code; 2146 uint8_t page_length; 2147 uint16_t payload_length; 2148 struct prli_svc_pram_resp_page svc_params; 2149 } prli_acc_resp_t; 2150 2151 #define EL_TRACE_BUF_SIZE 8192 2152 2153 /* 2154 * Global Data in ql_api.c source file. 2155 */ 2156 extern void *ql_state; /* for soft state routine */ 2157 extern uint32_t ql_os_release_level; 2158 extern ql_head_t ql_hba; 2159 extern kmutex_t ql_global_mutex; 2160 extern kmutex_t ql_global_hw_mutex; 2161 extern kmutex_t ql_global_el_mutex; 2162 extern uint8_t ql_ip_fast_post_count; 2163 extern uint32_t ql_ip_buffer_count; 2164 extern uint32_t ql_ip_low_water; 2165 extern uint8_t ql_alpa_to_index[]; 2166 extern uint32_t ql_gfru_hba_index; 2167 2168 /* 2169 * Global Function Prototypes in ql_api.c source file. 2170 */ 2171 void ql_chg_endian(uint8_t *, size_t); 2172 void ql_populate_hba_fru_details(ql_adapter_state_t *, fc_fca_port_info_t *); 2173 void ql_setup_fruinfo(ql_adapter_state_t *); 2174 uint16_t ql_pci_config_get16(ql_adapter_state_t *, off_t); 2175 uint32_t ql_pci_config_get32(ql_adapter_state_t *, off_t); 2176 void ql_pci_config_put8(ql_adapter_state_t *, off_t, uint8_t); 2177 void ql_pci_config_put16(ql_adapter_state_t *, off_t, uint16_t); 2178 void ql_delay(ql_adapter_state_t *, clock_t); 2179 void ql_awaken_task_daemon(ql_adapter_state_t *, ql_srb_t *, uint32_t, 2180 uint32_t); 2181 int ql_abort_device(ql_adapter_state_t *, ql_tgt_t *, int); 2182 int ql_binary_fw_dump(ql_adapter_state_t *, int); 2183 void ql_done(ql_link_t *); 2184 int ql_24xx_flash_id(ql_adapter_state_t *); 2185 int ql_24xx_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t); 2186 int ql_poll_flash(ql_adapter_state_t *, uint32_t, uint8_t); 2187 void ql_flash_disable(ql_adapter_state_t *); 2188 void ql_flash_enable(ql_adapter_state_t *); 2189 int ql_erase_flash(ql_adapter_state_t *, int); 2190 void ql_write_flash_byte(ql_adapter_state_t *, uint32_t, uint8_t); 2191 uint8_t ql_read_flash_byte(ql_adapter_state_t *, uint32_t); 2192 int ql_24xx_read_flash(ql_adapter_state_t *, uint32_t, uint32_t *); 2193 int ql_24xx_write_flash(ql_adapter_state_t *, uint32_t, uint32_t); 2194 fc_unsol_buf_t *ql_get_unsolicited_buffer(ql_adapter_state_t *, uint32_t); 2195 size_t ql_ascii_fw_dump(ql_adapter_state_t *, caddr_t); 2196 void ql_add_link_b(ql_head_t *, ql_link_t *); 2197 void ql_add_link_t(ql_head_t *, ql_link_t *); 2198 void ql_remove_link(ql_head_t *, ql_link_t *); 2199 void ql_next(ql_adapter_state_t *, ql_lun_t *); 2200 void ql_send_logo(ql_adapter_state_t *, ql_tgt_t *, ql_head_t *); 2201 void ql_cthdr_endian(ddi_acc_handle_t, caddr_t, boolean_t); 2202 ql_tgt_t *ql_d_id_to_queue(ql_adapter_state_t *, port_id_t); 2203 ql_tgt_t *ql_loop_id_to_queue(ql_adapter_state_t *, uint16_t); 2204 void ql_cmd_wait(ql_adapter_state_t *); 2205 void ql_loop_online(ql_adapter_state_t *); 2206 ql_tgt_t *ql_dev_init(ql_adapter_state_t *, port_id_t, uint16_t); 2207 int ql_ub_frame_hdr(ql_adapter_state_t *, ql_tgt_t *, uint16_t, ql_head_t *); 2208 void ql_rcv_rscn_els(ql_adapter_state_t *, uint16_t *, ql_head_t *); 2209 int ql_stall_driver(ql_adapter_state_t *, uint32_t); 2210 void ql_restart_driver(ql_adapter_state_t *); 2211 int ql_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t); 2212 int ql_get_dma_mem(ql_adapter_state_t *, dma_mem_t *, uint32_t, 2213 mem_alloc_type_t, mem_alignment_t); 2214 int ql_alloc_phys(ql_adapter_state_t *, dma_mem_t *, int); 2215 void ql_free_phys(ql_adapter_state_t *, dma_mem_t *); 2216 void ql_24xx_protect_flash(ql_adapter_state_t *); 2217 void ql_free_dma_resource(ql_adapter_state_t *, dma_mem_t *); 2218 uint8_t ql_pci_config_get8(ql_adapter_state_t *, off_t); 2219 void ql_pci_config_put32(ql_adapter_state_t *, off_t, uint32_t); 2220 int ql_24xx_unprotect_flash(ql_adapter_state_t *); 2221 char *els_cmd_text(int); 2222 char *mbx_cmd_text(int); 2223 char *cmd_text(cmd_table_t *, int); 2224 uint32_t ql_fwmodule_resolve(ql_adapter_state_t *); 2225 void ql_port_state(ql_adapter_state_t *, uint32_t, uint32_t); 2226 void ql_isp_els_handle_cmd_endian(ql_adapter_state_t *ha, ql_srb_t *srb); 2227 void ql_isp_els_handle_rsp_endian(ql_adapter_state_t *ha, ql_srb_t *srb); 2228 void ql_isp_els_handle_endian(ql_adapter_state_t *ha, uint8_t *ptr, 2229 uint8_t ls_code); 2230 int ql_el_trace_desc_ctor(ql_adapter_state_t *); 2231 int ql_el_trace_desc_dtor(ql_adapter_state_t *); 2232 int ql_nvram_cache_desc_ctor(ql_adapter_state_t *); 2233 int ql_nvram_cache_desc_dtor(ql_adapter_state_t *); 2234 int ql_wwn_cmp(ql_adapter_state_t *, la_wwn_t *, la_wwn_t *); 2235 void ql_dev_free(ql_adapter_state_t *, ql_tgt_t *); 2236 2237 #ifdef __cplusplus 2238 } 2239 #endif 2240 2241 #endif /* _QL_API_H */ 2242