1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2009 QLogic Corporation */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _QL_API_H 30 #define _QL_API_H 31 32 /* 33 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 34 * 35 * *********************************************************************** 36 * * ** 37 * * NOTICE ** 38 * * COPYRIGHT (C) 1996-2009 QLOGIC CORPORATION ** 39 * * ALL RIGHTS RESERVED ** 40 * * ** 41 * *********************************************************************** 42 * 43 */ 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /* OS include files. */ 50 #include <sys/scsi/scsi_types.h> 51 #include <sys/byteorder.h> 52 #include <sys/pci.h> 53 #include <sys/utsname.h> 54 #include <sys/file.h> 55 #include <sys/param.h> 56 #include <ql_open.h> 57 58 #include <sys/fibre-channel/fc.h> 59 #include <sys/fibre-channel/impl/fc_fcaif.h> 60 61 #ifndef DDI_INTR_TYPE_FIXED 62 #define DDI_INTR_TYPE_FIXED 0x1 63 #endif 64 #ifndef DDI_INTR_TYPE_MSI 65 #define DDI_INTR_TYPE_MSI 0x2 66 #endif 67 #ifndef DDI_INTR_TYPE_MSIX 68 #define DDI_INTR_TYPE_MSIX 0x4 69 #endif 70 #ifndef DDI_INTR_FLAG_BLOCK 71 #define DDI_INTR_FLAG_BLOCK 0x100 72 #endif 73 #ifndef DDI_INTR_ALLOC_NORMAL 74 #define DDI_INTR_ALLOC_NORMAL 0 75 #endif 76 #ifndef DDI_INTR_ALLOC_STRICT 77 #define DDI_INTR_ALLOC_STRICT 1 78 #endif 79 80 /* 81 * NPIV defines 82 */ 83 #ifndef FC_NPIV_FDISC_FAILED 84 #define FC_NPIV_FDISC_FAILED 0x45 85 #endif 86 #ifndef FC_NPIV_FDISC_WWN_INUSE 87 #define FC_NPIV_FDISC_WWN_INUSE 0x46 88 #endif 89 #ifndef FC_NPIV_NOT_SUPPORTED 90 #define FC_NPIV_NOT_SUPPORTED 0x47 91 #endif 92 #ifndef FC_NPIV_WRONG_TOPOLOGY 93 #define FC_NPIV_WRONG_TOPOLOGY 0x48 94 #endif 95 #ifndef FC_NPIV_NPIV_BOUND 96 #define FC_NPIV_NPIV_BOUND 0x49 97 #endif 98 99 #pragma weak ddi_intr_get_supported_types 100 #pragma weak ddi_intr_get_nintrs 101 #pragma weak ddi_intr_alloc 102 #pragma weak ddi_intr_free 103 #pragma weak ddi_intr_get_pri 104 #pragma weak ddi_intr_add_handler 105 #pragma weak ddi_intr_dup_handler 106 #pragma weak ddi_intr_get_navail 107 #pragma weak ddi_intr_block_disable 108 #pragma weak ddi_intr_block_enable 109 #pragma weak ddi_intr_disable 110 #pragma weak ddi_intr_enable 111 #pragma weak ddi_intr_get_cap 112 #pragma weak ddi_intr_remove_handler 113 extern int ddi_intr_get_supported_types(); 114 extern int ddi_intr_get_nintrs(); 115 extern int ddi_intr_alloc(); 116 extern int ddi_intr_free(); 117 extern int ddi_intr_get_pri(); 118 extern int ddi_intr_add_handler(); 119 extern int ddi_intr_dup_handler(); 120 extern int ddi_intr_get_navail(); 121 extern int ddi_intr_block_disable(); 122 extern int ddi_intr_block_enable(); 123 extern int ddi_intr_disable(); 124 extern int ddi_intr_enable(); 125 extern int ddi_intr_get_cap(); 126 extern int ddi_intr_remove_handler(); 127 128 #ifndef QL_DRV_HARDENING 129 #define ddi_devstate_t int 130 #define DDI_DEVSTATE_UP 0 131 #define ddi_get_devstate(a) DDI_DEVSTATE_UP 132 #define ddi_dev_report_fault(a, b, c, d) 133 #define ddi_check_dma_handle(a) DDI_SUCCESS 134 #define ddi_check_acc_handle(a) DDI_SUCCESS 135 #define QL_CLEAR_DMA_HANDLE(x) 136 #else 137 #define QL_CLEAR_DMA_HANDLE(x) ((ddi_dma_impl_t *)x)->dmai_fault_notify = 0; \ 138 ((ddi_dma_impl_t *)x)->dmai_fault_check = 0; \ 139 ((ddi_dma_impl_t *)x)->dmai_fault = 0 140 #endif 141 142 #ifndef FC_STATE_1GBIT_SPEED 143 #define FC_STATE_1GBIT_SPEED 0x0100 /* 1 Gbit/sec */ 144 #endif 145 #ifndef FC_STATE_2GBIT_SPEED 146 #define FC_STATE_2GBIT_SPEED 0x0400 /* 2 Gbit/sec */ 147 #endif 148 #ifndef FC_STATE_4GBIT_SPEED 149 #define FC_STATE_4GBIT_SPEED 0x0500 /* 4 Gbit/sec */ 150 #endif 151 #ifndef FC_STATE_8GBIT_SPEED 152 #define FC_STATE_8GBIT_SPEED 0x0700 /* 8 Gbit/sec */ 153 #endif 154 #ifndef FC_STATE_10GBIT_SPEED 155 #define FC_STATE_10GBIT_SPEED 0x0600 /* 10 Gbit/sec */ 156 #endif 157 158 /* 159 * Data bit definitions. 160 */ 161 #define BIT_0 0x1 162 #define BIT_1 0x2 163 #define BIT_2 0x4 164 #define BIT_3 0x8 165 #define BIT_4 0x10 166 #define BIT_5 0x20 167 #define BIT_6 0x40 168 #define BIT_7 0x80 169 #define BIT_8 0x100 170 #define BIT_9 0x200 171 #define BIT_10 0x400 172 #define BIT_11 0x800 173 #define BIT_12 0x1000 174 #define BIT_13 0x2000 175 #define BIT_14 0x4000 176 #define BIT_15 0x8000 177 #define BIT_16 0x10000 178 #define BIT_17 0x20000 179 #define BIT_18 0x40000 180 #define BIT_19 0x80000 181 #define BIT_20 0x100000 182 #define BIT_21 0x200000 183 #define BIT_22 0x400000 184 #define BIT_23 0x800000 185 #define BIT_24 0x1000000 186 #define BIT_25 0x2000000 187 #define BIT_26 0x4000000 188 #define BIT_27 0x8000000 189 #define BIT_28 0x10000000 190 #define BIT_29 0x20000000 191 #define BIT_30 0x40000000 192 #define BIT_31 0x80000000 193 194 /* 195 * Local Macro Definitions. 196 */ 197 #ifndef TRUE 198 #define TRUE B_TRUE 199 #endif 200 201 #ifndef FALSE 202 #define FALSE B_FALSE 203 #endif 204 205 /* 206 * I/O register 207 */ 208 #define RD_REG_BYTE(ha, addr) \ 209 (uint8_t)ddi_get8(ha->dev_handle, (uint8_t *)addr) 210 #define RD_REG_WORD(ha, addr) \ 211 (uint16_t)ddi_get16(ha->dev_handle, (uint16_t *)addr) 212 #define RD_REG_DWORD(ha, addr) \ 213 (uint32_t)ddi_get32(ha->dev_handle, (uint32_t *)addr) 214 215 #define WRT_REG_BYTE(ha, addr, data) \ 216 ddi_put8(ha->dev_handle, (uint8_t *)addr, (uint8_t)data) 217 #define WRT_REG_WORD(ha, addr, data) \ 218 ddi_put16(ha->dev_handle, (uint16_t *)addr, (uint16_t)data) 219 #define WRT_REG_DWORD(ha, addr, data) \ 220 ddi_put32(ha->dev_handle, (uint32_t *)addr, (uint32_t)data) 221 222 #define RD8_IO_REG(ha, regname) \ 223 RD_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname)) 224 #define RD16_IO_REG(ha, regname) \ 225 RD_REG_WORD(ha, (ha->iobase + ha->reg_off->regname)) 226 #define RD32_IO_REG(ha, regname) \ 227 RD_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname)) 228 229 #define WRT8_IO_REG(ha, regname, data) \ 230 WRT_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname), data) 231 #define WRT16_IO_REG(ha, regname, data) \ 232 WRT_REG_WORD(ha, (ha->iobase + ha->reg_off->regname), data) 233 #define WRT32_IO_REG(ha, regname, data) \ 234 WRT_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname), data) 235 236 #define RD_IOREG_BYTE(ha, addr) \ 237 (uint8_t)ddi_get8(ha->iomap_dev_handle, (uint8_t *)addr) 238 #define RD_IOREG_WORD(ha, addr) \ 239 (uint16_t)ddi_get16(ha->iomap_dev_handle, (uint16_t *)addr) 240 #define RD_IOREG_DWORD(ha, addr) \ 241 (uint32_t)ddi_get32(ha->iomap_dev_handle, (uint32_t *)addr) 242 243 #define WRT_IOREG_BYTE(ha, addr, data) \ 244 ddi_put8(ha->iomap_dev_handle, (uint8_t *)addr, (uint8_t)data) 245 #define WRT_IOREG_WORD(ha, addr, data) \ 246 ddi_put16(ha->iomap_dev_handle, (uint16_t *)addr, (uint16_t)data) 247 #define WRT_IOREG_DWORD(ha, addr, data) \ 248 ddi_put32(ha->iomap_dev_handle, (uint32_t *)addr, (uint32_t)data) 249 250 #define RD8_IOMAP_REG(ha, regname) \ 251 RD_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname)) 252 #define RD16_IOMAP_REG(ha, regname) \ 253 RD_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname)) 254 #define RD32_IOMAP_REG(ha, regname) \ 255 RD_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname)) 256 257 #define WRT8_IOMAP_REG(ha, regname, data) \ 258 WRT_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname), data) 259 #define WRT16_IOMAP_REG(ha, regname, data) \ 260 WRT_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname), data) 261 #define WRT32_IOMAP_REG(ha, regname, data) \ 262 WRT_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname), data) 263 264 /* 265 * FCA definitions 266 */ 267 #define MAX_LUNS 16384 268 #define QL_FCA_BRAND 0x0fca2200 269 270 /* Following to be removed when defined by OS. */ 271 /* ************************************************************************ */ 272 #define LA_ELS_FARP_REQ 0x54 273 #define LA_ELS_FARP_REPLY 0x55 274 #define LA_ELS_LPC 0x71 275 #define LA_ELS_LSTS 0x72 276 277 typedef struct { 278 ls_code_t ls_code; 279 uint8_t rsvd[3]; 280 uint8_t port_control; 281 uint8_t lpb[16]; 282 uint8_t lpe[16]; 283 } ql_lpc_t; 284 285 typedef struct { 286 ls_code_t ls_code; 287 } ql_acc_rjt_t; 288 289 typedef fc_linit_resp_t ql_lpc_resp_t; 290 typedef fc_scr_resp_t ql_rscn_resp_t; 291 292 typedef struct { 293 uint16_t class_valid_svc_opt; 294 uint16_t initiator_ctl; 295 uint16_t recipient_ctl; 296 uint16_t rcv_data_size; 297 uint16_t conc_sequences; 298 uint16_t n_port_end_to_end_credit; 299 uint16_t open_sequences_per_exch; 300 uint16_t unused; 301 } class_svc_param_t; 302 303 typedef struct { 304 uint8_t type; 305 uint8_t rsvd; 306 uint16_t process_assoc_flags; 307 uint32_t originator_process; 308 uint32_t responder_process; 309 uint32_t process_flags; 310 } prli_svc_param_t; 311 /* *********************************************************************** */ 312 313 /* 314 * Fibre Channel device definitions. 315 */ 316 #define MAX_22_FIBRE_DEVICES 256 317 #define MAX_24_FIBRE_DEVICES 2048 318 #define MAX_24_VIRTUAL_PORTS 127 319 #define MAX_25_VIRTUAL_PORTS 254 320 321 #define LAST_LOCAL_LOOP_ID 0x7d 322 #define FL_PORT_LOOP_ID 0x7e /* FFFFFE Fabric F_Port */ 323 #define SWITCH_FABRIC_CONTROLLER_LOOP_ID 0x7f /* FFFFFD Fabric Controller */ 324 #define SIMPLE_NAME_SERVER_LOOP_ID 0x80 /* FFFFFC Directory Server */ 325 #define SNS_FIRST_LOOP_ID 0x81 326 #define SNS_LAST_LOOP_ID 0xfe 327 #define IP_BROADCAST_LOOP_ID 0xff /* FFFFFF Broadcast */ 328 #define BROADCAST_ADDR 0xffffff /* FFFFFF Broadcast */ 329 330 /* 331 * Fibre Channel 24xx device definitions. 332 */ 333 #define LAST_N_PORT_HDL 0x7ef 334 #define SNS_24XX_HDL 0x7FC /* SNS FFFFFCh */ 335 #define SFC_24XX_HDL 0x7FD /* fabric controller FFFFFDh */ 336 #define FL_PORT_24XX_HDL 0x7FE /* F_Port FFFFFEh */ 337 #define BROADCAST_24XX_HDL 0x7FF /* IP broadcast FFFFFFh */ 338 339 /* Loop ID's used as flags, must be higher than any valid Loop ID */ 340 #define PORT_NO_LOOP_ID 0x8000 /* Device does not have loop ID. */ 341 #define PORT_LOST_ID 0x4000 /* Device has been lost. */ 342 343 /* Fibre Channel Topoploy. */ 344 #define QL_N_PORT BIT_0 345 #define QL_NL_PORT BIT_1 346 #define QL_F_PORT BIT_2 347 #define QL_FL_PORT BIT_3 348 #define QL_SNS_CONNECTION BIT_4 349 #define QL_LOOP_CONNECTION (QL_NL_PORT | QL_FL_PORT) 350 #define QL_P2P_CONNECTION (QL_F_PORT | QL_N_PORT) 351 352 /* Timeout timer counts in seconds (must greater than 1 second). */ 353 #define WATCHDOG_TIME 5 /* 0 - 255 */ 354 #define PORT_RETRY_TIME 2 /* 0 - 255 */ 355 #define LOOP_DOWN_TIMER_OFF 0 356 #define LOOP_DOWN_TIMER_START 240 /* 0 - 255 */ 357 #define LOOP_DOWN_TIMER_END 1 358 #define LOOP_DOWN_RESET (LOOP_DOWN_TIMER_START - 45) /* 0 - 255 */ 359 #define R_A_TOV_DEFAULT 20 /* 0 - 65535 */ 360 #define IDLE_CHECK_TIMER 300 /* 0 - 65535 */ 361 #define MAX_DEVICE_LOST_RETRY 16 /* 0 - 255 */ 362 363 /* Maximum outstanding commands in ISP queues (1-4095) */ 364 #define MAX_OUTSTANDING_COMMANDS 0x400 365 #define OSC_INDEX_MASK 0xfff 366 #define OSC_INDEX_SHIFT 12 367 368 /* Maximum unsolicited buffers (1-65535) */ 369 #define QL_UB_LIMIT 256 370 371 /* ISP request, response and receive buffer entry counts */ 372 #define REQUEST_ENTRY_CNT 512 /* Request entries (205-65535) */ 373 #define RESPONSE_ENTRY_CNT 256 /* Response entries (1-65535) */ 374 #define RCVBUF_CONTAINER_CNT 64 /* Rcv buffer containers (8-1024) */ 375 376 /* 377 * ISP request, response, mailbox and receive buffer queue sizes 378 */ 379 #define REQUEST_ENTRY_SIZE 64 380 #define REQUEST_QUEUE_SIZE (REQUEST_ENTRY_SIZE * REQUEST_ENTRY_CNT) 381 382 #define RESPONSE_ENTRY_SIZE 64 383 #define RESPONSE_QUEUE_SIZE (RESPONSE_ENTRY_SIZE * RESPONSE_ENTRY_CNT) 384 385 #define MAILBOX_BUFFER_SIZE 0x4000 386 387 #define RCVBUF_CONTAINER_SIZE 12 388 #define RCVBUF_QUEUE_SIZE (RCVBUF_CONTAINER_SIZE * RCVBUF_CONTAINER_CNT) 389 390 /* 391 * ISP DMA buffer definitions 392 */ 393 #define REQUEST_Q_BUFFER_OFFSET 0 394 #define RESPONSE_Q_BUFFER_OFFSET (REQUEST_Q_BUFFER_OFFSET + REQUEST_QUEUE_SIZE) 395 #define RCVBUF_Q_BUFFER_OFFSET (RESPONSE_Q_BUFFER_OFFSET + RESPONSE_QUEUE_SIZE) 396 397 /* 398 * DMA attributes definitions. 399 */ 400 #define QL_DMA_LOW_ADDRESS (uint64_t)0 401 #define QL_DMA_HIGH_64BIT_ADDRESS (uint64_t)0xffffffffffffffff 402 #define QL_DMA_HIGH_32BIT_ADDRESS (uint64_t)0xffffffff 403 #define QL_DMA_XFER_COUNTER (uint64_t)0xffffffff 404 #define QL_DMA_ADDRESS_ALIGNMENT (uint64_t)8 405 #define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3 406 #define QL_DMA_RING_ADDRESS_ALIGNMENT (uint64_t)64 407 #define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6 408 #define QL_DMA_BURSTSIZES 0xff 409 #define QL_DMA_MIN_XFER_SIZE 1 410 #define QL_DMA_MAX_XFER_SIZE (uint64_t)0xffffffff 411 #define QL_DMA_SEGMENT_BOUNDARY (uint64_t)0xffffffff 412 413 #ifdef __sparc 414 #define QL_DMA_SG_LIST_LENGTH 1 415 #define QL_FCSM_CMD_SGLLEN 1 416 #define QL_FCSM_RSP_SGLLEN 1 417 #define QL_FCIP_CMD_SGLLEN 1 418 #define QL_FCIP_RSP_SGLLEN 1 419 #define QL_FCP_CMD_SGLLEN 1 420 #define QL_FCP_RSP_SGLLEN 1 421 #else 422 #define QL_DMA_SG_LIST_LENGTH 1024 423 #define QL_FCSM_CMD_SGLLEN 1 424 #define QL_FCSM_RSP_SGLLEN 6 425 /* 426 * QL_FCIP_CMD_SGLLEN needs to be increased as we changed the max fcip packet 427 * size to about 64K. With this, we need to increase the maximum number of 428 * scatter-gather elements allowable from the existing 7. We want it to be more 429 * like 17 (max fragments for an fcip packet that is unaligned). (64K / 4K) + 1 430 * or whatever. Otherwise the DMA breakup routines will give bad results. 431 */ 432 #define QL_FCIP_CMD_SGLLEN 17 433 #define QL_FCIP_RSP_SGLLEN 1 434 #define QL_FCP_CMD_SGLLEN 1 435 #define QL_FCP_RSP_SGLLEN 1 436 #endif 437 438 #ifndef DDI_DMA_RELAXED_ORDERING 439 #define DDI_DMA_RELAXED_ORDERING 0x400 440 #endif 441 442 #define QL_DMA_GRANULARITY 1 443 #define QL_DMA_XFER_FLAGS 0 444 445 typedef union { 446 uint64_t size64; /* 1 X 64 bit number */ 447 uint32_t size32[2]; /* 2 x 32 bit number */ 448 uint16_t size16[4]; /* 4 x 16 bit number */ 449 uint8_t size8[8]; /* 8 x 8 bit number */ 450 } conv_num_t; 451 452 /* 453 * Device register offsets. 454 */ 455 #define MAX_MBOX_COUNT 32 456 typedef struct { 457 uint8_t flash_address; /* Flash BIOS address */ 458 uint8_t flash_data; /* Flash BIOS data */ 459 uint8_t ctrl_status; /* Control/Status */ 460 uint8_t ictrl; /* Interrupt control */ 461 uint8_t istatus; /* Interrupt status */ 462 uint8_t semaphore; /* Semaphore */ 463 uint8_t nvram; /* NVRAM register. */ 464 uint8_t req_in; /* for 2200 MBX 4 Write */ 465 uint8_t req_out; /* for 2200 MBX 4 read */ 466 uint8_t resp_in; /* for 2200 MBX 5 Read */ 467 uint8_t resp_out; /* for 2200 MBX 5 Write */ 468 uint8_t intr_info_lo; 469 uint8_t intr_info_hi; 470 uint8_t mbox_cnt; /* Number of mailboxes */ 471 uint8_t mailbox[MAX_MBOX_COUNT]; /* Mailbox registers */ 472 uint8_t fpm_diag_config; 473 uint8_t pcr; /* Processor Control Register. */ 474 uint8_t mctr; /* Memory Configuration and Timing. */ 475 uint8_t fb_cmd; 476 uint8_t hccr; /* Host command & control register. */ 477 uint8_t gpiod; /* GPIO Data register. */ 478 uint8_t gpioe; /* GPIO Enable register. */ 479 uint8_t host_to_host_sema; /* 2312 resource lock register */ 480 uint8_t pri_req_in; /* 2400 */ 481 uint8_t pri_req_out; /* 2400 */ 482 uint8_t atio_req_in; /* 2400 */ 483 uint8_t atio_req_out; /* 2400 */ 484 uint8_t io_base_addr; /* 2400 */ 485 } reg_off_t; 486 487 /* 488 * Mbox-8 read maximum debounce count. 489 * Reading Mbox-8 could be debouncing, before getting stable value. 490 * This is the recommended driver fix from Qlogic along with firmware fix. 491 * During testing, maximum count did not cross 3. 492 */ 493 #define QL_MAX_DEBOUNCE 10 494 495 /* 496 * Control Status register definitions 497 */ 498 #define ISP_FUNC_NUM_MASK (BIT_15 | BIT_14) 499 #define ISP_FLASH_64K_BANK BIT_3 /* Flash BIOS 64K Bank Select */ 500 #define ISP_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 501 #define ISP_RESET BIT_0 /* ISP soft reset */ 502 503 /* 504 * Control Status 24xx register definitions 505 */ 506 #define FLASH_NVRAM_ACCESS_ERROR BIT_18 507 #define DMA_ACTIVE BIT_17 508 #define DMA_SHUTDOWN BIT_16 509 #define FUNCTION_NUMBER BIT_15 510 511 #define MWB_4096_BYTES (BIT_5 | BIT_4) 512 #define MWB_2048_BYTES BIT_5 513 #define MWB_1024_BYTES BIT_4 514 #define MWB_512_BYTES 0 515 516 /* 517 * Interrupt Control register definitions 518 */ 519 #define ISP_EN_INT BIT_15 /* ISP enable interrupts. */ 520 #define ISP_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 521 522 /* 523 * Interrupt Status register definitions 524 */ 525 #define RISC_INT BIT_3 /* RISC interrupt */ 526 527 /* 528 * NVRAM register definitions. 529 */ 530 #define NV_DESELECT 0 531 #define NV_CLOCK BIT_0 532 #define NV_SELECT BIT_1 533 #define NV_DATA_OUT BIT_2 534 #define NV_DATA_IN BIT_3 535 #define NV_PR_ENABLE BIT_13 /* protection register enable */ 536 #define NV_WR_ENABLE BIT_14 /* write enable */ 537 #define NV_BUSY BIT_15 538 539 /* 540 * Flash/NVRAM 24xx definitions 541 */ 542 #define FLASH_DATA_FLAG BIT_31 543 #define FLASH_CONF_ADDR 0x7FFD0000 544 #define FLASH_24_25_DATA_ADDR 0x7FF00000 545 #define FLASH_8100_DATA_ADDR 0x7F800000 546 #define FLASH_ADDR_MASK 0x7FFF0000 547 548 #define NVRAM_CONF_ADDR 0x7FFF0000 549 #define NVRAM_DATA_ADDR 0x7FFE0000 550 551 #define NVRAM_2200_FUNC0_ADDR 0x0 552 #define NVRAM_2300_FUNC0_ADDR 0x0 553 #define NVRAM_2300_FUNC1_ADDR 0x80 554 #define NVRAM_2400_FUNC0_ADDR 0x80 555 #define NVRAM_2400_FUNC1_ADDR 0x180 556 #define NVRAM_2500_FUNC0_ADDR 0x48080 557 #define NVRAM_2500_FUNC1_ADDR 0x48180 558 #define NVRAM_8100_FUNC0_ADDR 0xD0080 559 #define NVRAM_8100_FUNC1_ADDR 0xD0180 560 561 #define VPD_2400_FUNC0_ADDR 0 562 #define VPD_2400_FUNC1_ADDR 0x100 563 #define VPD_2500_FUNC0_ADDR 0x48000 564 #define VPD_2500_FUNC1_ADDR 0x48100 565 #define VPD_8100_FUNC0_ADDR 0xD0000 566 #define VPD_8100_FUNC1_ADDR 0xD0400 567 #define VPD_SIZE 0x80 568 569 #define FLASH_2200_FIRMWARE_ADDR 0x20000 570 #define FLASH_2300_FIRMWARE_ADDR 0x20000 571 #define FLASH_2400_FIRMWARE_ADDR 0x20000 572 #define FLASH_2500_FIRMWARE_ADDR 0x20000 573 #define FLASH_8100_FIRMWARE_ADDR 0xA0000 574 575 #define FLASH_2400_ERRLOG_START_ADDR_0 0 576 #define FLASH_2400_ERRLOG_START_ADDR_1 0 577 #define FLASH_2500_ERRLOG_START_ADDR_0 0x54000 578 #define FLASH_2500_ERRLOG_START_ADDR_1 0x54400 579 #define FLASH_8100_ERRLOG_START_ADDR_0 0xDC000 580 #define FLASH_8100_ERRLOG_START_ADDR_1 0xDC400 581 #define FLASH_ERRLOG_SIZE 0x200 582 #define FLASH_ERRLOG_ENTRY_SIZE 4 583 584 #define FLASH_2400_DESCRIPTOR_TABLE 0 585 #define FLASH_2500_DESCRIPTOR_TABLE 0x50000 586 #define FLASH_8100_DESCRIPTOR_TABLE 0xD8000 587 588 #define FLASH_2400_LAYOUT_TABLE 0x11400 589 #define FLASH_2500_LAYOUT_TABLE 0x50400 590 #define FLASH_8100_LAYOUT_TABLE 0xD8400 591 592 /* 593 * Flash Error Log Event Codes. 594 */ 595 #define FLASH_ERRLOG_AEN_8002 0x8002 596 #define FLASH_ERRLOG_AEN_8003 0x8003 597 #define FLASH_ERRLOG_AEN_8004 0x8004 598 #define FLASH_ERRLOG_RESET_ERR 0xF00B 599 #define FLASH_ERRLOG_ISP_ERR 0xF020 600 #define FLASH_ERRLOG_PARITY_ERR 0xF022 601 #define FLASH_ERRLOG_NVRAM_CHKSUM_ERR 0xF023 602 #define FLASH_ERRLOG_FLASH_FW_ERR 0xF024 603 604 #define VPD_TAG_END 0x78 605 #define VPD_TAG_CHKSUM "RV" 606 #define VPD_TAG_SN "SN" 607 #define VPD_TAG_PN "PN" 608 #define VPD_TAG_PRODID "\x82" 609 #define VPD_TAG_LRT 0x90 610 #define VPD_TAG_LRTC 0x91 611 612 /* 613 * RISC to Host Status register definitions. 614 */ 615 #define RH_RISC_INT BIT_15 /* RISC to Host Intrpt Req */ 616 #define RH_RISC_PAUSED BIT_8 /* RISC Paused bit. */ 617 618 /* 619 * RISC to Host Status register status field definitions. 620 */ 621 #define ROM_MBX_SUCCESS 0x01 622 #define ROM_MBX_ERR 0x02 623 #define MBX_SUCCESS 0x10 624 #define MBX_ERR 0x11 625 #define ASYNC_EVENT 0x12 626 #define RESP_UPDATE 0x13 627 #define REQ_UPDATE 0x14 628 #define SCSI_FAST_POST_16 0x15 629 #define SCSI_FAST_POST_32 0x16 630 #define CTIO_FAST_POST 0x17 631 #define IP_FAST_POST_XMT 0x18 632 #define IP_FAST_POST_RCV 0x19 633 #define IP_FAST_POST_BRD 0x1a 634 #define IP_FAST_POST_RCV_ALN 0x1b 635 #define ATIO_UPDATE 0x1c 636 #define ATIO_RESP_UPDATE 0x1d 637 638 /* 639 * HCCR commands. 640 */ 641 #define HC_RESET_RISC 0x1000 /* Reset RISC */ 642 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */ 643 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 644 #define HC_DISABLE_PARITY_PAUSE 0x4001 /* qla2200/2300 - disable parity err */ 645 /* RISC pause. */ 646 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */ 647 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 648 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 649 #define HC_HOST_INT BIT_7 /* Host interrupt bit */ 650 #define HC_RISC_PAUSE BIT_5 /* Pause mode bit */ 651 652 /* 653 * HCCR commands for 24xx and 25xx. 654 */ 655 #define HC24_RESET_RISC 0x10000000 /* Reset RISC */ 656 #define HC24_CLEAR_RISC_RESET 0x20000000 /* Release RISC from reset. */ 657 #define HC24_PAUSE_RISC 0x30000000 /* Pause RISC */ 658 #define HC24_RELEASE_PAUSE 0x40000000 /* Release RISC from pause */ 659 #define HC24_SET_HOST_INT 0x50000000 /* Set host interrupt */ 660 #define HC24_CLR_HOST_INT 0x60000000 /* Clear HOST interrupt */ 661 #define HC24_CLR_RISC_INT 0xA0000000 /* Clear RISC interrupt */ 662 #define HC24_HOST_INT BIT_6 /* Host to RISC intrpt bit */ 663 #define HC24_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 664 665 /* 666 * ISP Initialization Control Blocks. 667 * Little endian except where noted. 668 */ 669 #define ICB_VERSION 1 670 typedef struct ql_init_cb { 671 uint8_t version; 672 uint8_t reserved; 673 674 /* 675 * LSB BIT 0 = enable_hard_loop_id 676 * LSB BIT 1 = enable_fairness 677 * LSB BIT 2 = enable_full_duplex 678 * LSB BIT 3 = enable_fast_posting 679 * LSB BIT 4 = enable_target_mode 680 * LSB BIT 5 = disable_initiator_mode 681 * LSB BIT 6 = enable_adisc 682 * LSB BIT 7 = enable_target_inquiry_data 683 * 684 * MSB BIT 0 = enable_port_update_ae 685 * MSB BIT 1 = disable_initial_lip 686 * MSB BIT 2 = enable_decending_soft_assign 687 * MSB BIT 3 = previous_assigned_addressing 688 * MSB BIT 4 = enable_stop_q_on_full 689 * MSB BIT 5 = enable_full_login_on_lip 690 * MSB BIT 6 = enable_node_name 691 * MSB BIT 7 = extended_control_block 692 */ 693 uint8_t firmware_options[2]; 694 695 uint8_t max_frame_length[2]; 696 uint8_t max_iocb_allocation[2]; 697 uint8_t execution_throttle[2]; 698 uint8_t login_retry_count; 699 uint8_t retry_delay; /* unused */ 700 uint8_t port_name[8]; /* Big endian. */ 701 uint8_t hard_address[2]; /* option bit 0 */ 702 uint8_t inquiry; /* option bit 7 */ 703 uint8_t login_timeout; 704 uint8_t node_name[8]; /* Big endian */ 705 uint8_t request_q_outpointer[2]; 706 uint8_t response_q_inpointer[2]; 707 uint8_t request_q_length[2]; 708 uint8_t response_q_length[2]; 709 uint8_t request_q_address[8]; 710 uint8_t response_q_address[8]; 711 uint8_t lun_enables[2]; 712 uint8_t command_resouce_count; 713 uint8_t immediate_notify_resouce_count; 714 uint8_t timeout[2]; 715 uint8_t reserved_2[2]; 716 717 /* 718 * LSB BIT 0 = Timer operation mode bit 0 719 * LSB BIT 1 = Timer operation mode bit 1 720 * LSB BIT 2 = Timer operation mode bit 2 721 * LSB BIT 3 = Timer operation mode bit 3 722 * LSB BIT 4 = P2P Connection option bit 0 723 * LSB BIT 5 = P2P Connection option bit 1 724 * LSB BIT 6 = P2P Connection option bit 2 725 * LSB BIT 7 = Enable Non part on LIHA failure 726 * 727 * MSB BIT 0 = Enable class 2 728 * MSB BIT 1 = Enable ACK0 729 * MSB BIT 2 = 730 * MSB BIT 3 = 731 * MSB BIT 4 = FC Tape Enable 732 * MSB BIT 5 = Enable FC Confirm 733 * MSB BIT 6 = Enable CRN 734 * MSB BIT 7 = 735 */ 736 uint8_t add_fw_opt[2]; 737 738 uint8_t response_accumulation_timer; 739 uint8_t interrupt_delay_timer; 740 741 /* 742 * LSB BIT 0 = Enable Read xfr_rdy 743 * LSB BIT 1 = Soft ID only 744 * LSB BIT 2 = 745 * LSB BIT 3 = 746 * LSB BIT 4 = FCP RSP Payload [0] 747 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 748 * LSB BIT 6 = 749 * LSB BIT 7 = 750 * 751 * MSB BIT 0 = Sbus enable - 2300 752 * MSB BIT 1 = 753 * MSB BIT 2 = 754 * MSB BIT 3 = 755 * MSB BIT 4 = 756 * MSB BIT 5 = enable 50 ohm termination 757 * MSB BIT 6 = Data Rate (2300 only) 758 * MSB BIT 7 = Data Rate (2300 only) 759 */ 760 uint8_t special_options[2]; 761 762 uint8_t reserved_3[26]; 763 } ql_init_cb_t; 764 765 /* 766 * Virtual port definition. 767 */ 768 typedef struct ql_vp_cfg { 769 uint8_t reserved[2]; 770 uint8_t options; 771 uint8_t hard_prev_addr; 772 uint8_t port_name[8]; 773 uint8_t node_name[8]; 774 } ql_vp_cfg_t; 775 776 /* 777 * VP options. 778 */ 779 #define VPO_ENABLE_SNS_LOGIN_SCR BIT_6 780 #define VPO_TARGET_MODE_DISABLED BIT_5 781 #define VPO_INITIATOR_MODE_ENABLED BIT_4 782 #define VPO_ENABLED BIT_3 783 #define VPO_ID_NOT_ACQUIRED BIT_2 784 #define VPO_PREVIOUSLY_ASSIGNED_ID BIT_1 785 #define VPO_HARD_ASSIGNED_ID BIT_0 786 787 #define ICB_24XX_VERSION 1 788 typedef struct ql_init_24xx_cb { 789 uint8_t version[2]; 790 uint8_t reserved_1[2]; 791 uint8_t max_frame_length[2]; 792 uint8_t execution_throttle[2]; 793 uint8_t exchange_count[2]; 794 uint8_t hard_address[2]; 795 uint8_t port_name[8]; /* Big endian. */ 796 uint8_t node_name[8]; /* Big endian. */ 797 798 uint8_t response_q_inpointer[2]; 799 uint8_t request_q_outpointer[2]; 800 801 uint8_t login_retry_count[2]; 802 803 uint8_t prio_request_q_outpointer[2]; 804 805 uint8_t response_q_length[2]; 806 uint8_t request_q_length[2]; 807 808 uint8_t link_down_on_nos[2]; 809 810 uint8_t prio_request_q_length[2]; 811 uint8_t request_q_address[8]; 812 uint8_t response_q_address[8]; 813 uint8_t prio_request_q_address[8]; 814 uint8_t msi_x_vector[2]; 815 uint8_t reserved_2[6]; 816 uint8_t atio_q_inpointer[2]; 817 uint8_t atio_q_length[2]; 818 uint8_t atio_q_address[8]; 819 820 uint8_t interrupt_delay_timer[2]; /* 100us per */ 821 uint8_t login_timeout[2]; 822 /* 823 * BIT 0 = Hard Assigned Loop ID 824 * BIT 1 = Enable Fairness 825 * BIT 2 = Enable Full-Duplex 826 * BIT 3 = Reserved 827 * BIT 4 = Target Mode Enable 828 * BIT 5 = Initiator Mode Disable 829 * BIT 6 = Reserved 830 * BIT 7 = Reserved 831 * 832 * BIT 8 = Reserved 833 * BIT 9 = Disable Initial LIP 834 * BIT 10 = Descending Loop ID Search 835 * BIT 11 = Previous Assigned Loop ID 836 * BIT 12 = Reserved 837 * BIT 13 = Full Login after LIP 838 * BIT 14 = Node Name Option 839 * BIT 15-31 = Reserved 840 */ 841 uint8_t firmware_options_1[4]; 842 843 /* 844 * BIT 0 = Operation Mode bit 0 845 * BIT 1 = Operation Mode bit 1 846 * BIT 2 = Operation Mode bit 2 847 * BIT 3 = Operation Mode bit 3 848 * BIT 4 = Connection Options bit 0 849 * BIT 5 = Connection Options bit 1 850 * BIT 6 = Connection Options bit 2 851 * BIT 7 = Enable Non part on LIHA failure 852 * 853 * BIT 8 = Enable Class 2 854 * BIT 9 = Enable ACK0 855 * BIT 10 = Reserved 856 * BIT 11 = Enable FC-SP Security 857 * BIT 12 = FC Tape Enable 858 * BIT 13 = Reserved 859 * BIT 14 = Target PRLI Control 860 * BIT 15 = Reserved 861 * 862 * BIT 16 = Enable Emulated MSIX 863 * BIT 17 = Reserved 864 * BIT 18 = Enable Alternate Device Number 865 * BIT 19 = Enable Alternate Bus Number 866 * BIT 20 = Enable Translated Address 867 * BIT 21 = Enable VM Security 868 * BIT 22 = Enable Interrupt Handshake 869 * BIT 23 = Enable Multiple Queue 870 * 871 * BIT 24 = IOCB Security 872 * BIT 25 = qos 873 * BIT 26-31 = Reserved 874 */ 875 uint8_t firmware_options_2[4]; 876 877 /* 878 * BIT 0 = Reserved 879 * BIT 1 = Soft ID only 880 * BIT 2 = Reserved 881 * BIT 3 = Reserved 882 * BIT 4 = FCP RSP Payload bit 0 883 * BIT 5 = FCP RSP Payload bit 1 884 * BIT 6 = Enable Rec Out-of-Order data frame handling 885 * BIT 7 = Disable Automatic PLOGI on Local Loop 886 * 887 * BIT 8 = Reserved 888 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 889 * offset handling 890 * BIT 10 = Reserved 891 * BIT 11 = Reserved 892 * BIT 12 = Reserved 893 * BIT 13 = Data Rate bit 0 894 * BIT 14 = Data Rate bit 1 895 * BIT 15 = Data Rate bit 2 896 * 897 * BIT 16 = 75-ohm Termination Select 898 * BIT 17 = Enable Multiple FCFs 899 * BIT 18 = MAC Addressing Mode 900 * BIT 19 = MAC Addressing Mode 901 * BIT 20 = MAC Addressing Mode 902 * BIT 21 = Ethernet Data Rate 903 * BIT 22 = Ethernet Data Rate 904 * BIT 23 = Ethernet Data Rate 905 * 906 * BIT 24 = Ethernet Data Rate 907 * BIT 25 = Ethernet Data Rate 908 * BIT 26 = Enable Ethernet Header ATIO Queue 909 * BIT 27 = Enable Ethernet Header Response Queue 910 * BIT 28 = SPMA Selection 911 * BIT 29 = SPMA Selection 912 * BIT 30 = Reserved 913 * BIT 31 = Reserved 914 */ 915 uint8_t firmware_options_3[4]; 916 917 uint8_t qos[2]; 918 uint8_t rid[2]; 919 920 uint8_t reserved_3[4]; 921 922 uint8_t enode_mac_addr[6]; 923 924 uint8_t reserved_4[10]; 925 926 /* 927 * Multi-ID firmware. 928 */ 929 uint8_t vp_count[2]; 930 931 /* 932 * BIT 1 = Allows mode 2 connection option 933 */ 934 uint8_t global_vp_option[2]; 935 936 ql_vp_cfg_t vpc[MAX_25_VIRTUAL_PORTS + 1]; 937 938 /* 939 * Extended Initialization Control Block 940 */ 941 ql_ext_icb_8100_t ext_blk; 942 } ql_init_24xx_cb_t; 943 944 typedef union ql_comb_init_cb { 945 ql_init_cb_t cb; 946 ql_init_24xx_cb_t cb24; 947 } ql_comb_init_cb_t; 948 949 /* 950 * ISP IP Initialization Control Block. 951 * Little endian except where noted. 952 */ 953 #define IP_ICB_VERSION 1 954 typedef struct ql_ip_init_cb { 955 uint8_t version; 956 uint8_t reserved; 957 958 /* 959 * LSB BIT 0 = receive_buffer_address_length 960 * LSB BIT 1 = fast post broadcast received 961 * LSB BIT 2 = allow out of receive buffers AE 962 */ 963 uint8_t ip_firmware_options[2]; 964 uint8_t ip_header_size[2]; 965 uint8_t mtu_size[2]; /* max value is 65280 */ 966 uint8_t buf_size[2]; 967 uint8_t reserved_1[8]; 968 uint8_t queue_size[2]; /* 8-1024 */ 969 uint8_t low_water_mark[2]; 970 uint8_t queue_address[8]; 971 uint8_t queue_inpointer[2]; 972 uint8_t fast_post_reg_count[2]; /* 0-14 */ 973 uint8_t cc[2]; 974 uint8_t reserved_2[28]; 975 } ql_ip_init_cb_t; 976 977 #define IP_ICB_24XX_VERSION 1 978 typedef struct ql_ip_init_24xx_cb { 979 uint8_t version; 980 uint8_t reserved; 981 /* 982 * LSB BIT 2 = allow out of receive buffers AE 983 */ 984 uint8_t ip_firmware_options[2]; 985 uint8_t ip_header_size[2]; 986 uint8_t mtu_size[2]; 987 uint8_t buf_size[2]; 988 uint8_t reserved_1[10]; 989 uint8_t low_water_mark[2]; 990 uint8_t reserved_3[12]; 991 uint8_t cc[2]; 992 uint8_t reserved_2[28]; 993 } ql_ip_init_24xx_cb_t; 994 995 typedef union ql_comb_ip_init_cb { 996 ql_ip_init_cb_t cb; 997 ql_ip_init_24xx_cb_t cb24; 998 } ql_comb_ip_init_cb_t; 999 1000 /* 1001 * f/w module table 1002 */ 1003 struct fw_table { 1004 uint16_t fw_class; 1005 int8_t *fw_version; 1006 }; 1007 1008 /* 1009 * aif function table 1010 */ 1011 typedef struct ql_ifunc { 1012 uint_t (*ifunc)(); 1013 } ql_ifunc_t; 1014 1015 #define QL_MSIX_AIF 0x0 1016 #define QL_MSIX_RSPQ 0x1 1017 #define QL_MSIX_MAXAIF QL_MSIX_RSPQ + 1 1018 1019 /* 1020 * DMA memory type. 1021 */ 1022 typedef enum mem_alloc_type { 1023 UNKNOWN_MEMORY, 1024 TASK_MEMORY, 1025 LITTLE_ENDIAN_DMA, 1026 BIG_ENDIAN_DMA, 1027 KERNEL_MEM, 1028 NO_SWAP_DMA, 1029 STRUCT_BUF_MEMORY 1030 } mem_alloc_type_t; 1031 1032 /* 1033 * DMA memory alignment type. 1034 */ 1035 typedef enum men_align_type { 1036 QL_DMA_DATA_ALIGN, 1037 QL_DMA_RING_ALIGN, 1038 } mem_alignment_t; 1039 1040 /* 1041 * DMA memory object. 1042 */ 1043 typedef struct dma_mem { 1044 uint64_t alignment; 1045 void *bp; 1046 ddi_dma_cookie_t *cookies; 1047 ddi_acc_handle_t acc_handle; 1048 ddi_dma_handle_t dma_handle; 1049 ddi_dma_cookie_t cookie; 1050 uint32_t cookie_count; 1051 uint32_t size; 1052 uint32_t memflags; 1053 mem_alloc_type_t type; 1054 uint32_t flags; /* Solaris DMA flags. */ 1055 } dma_mem_t; 1056 1057 /* 1058 * dma_mem_t memflags defines 1059 */ 1060 #define MFLG_32BIT_ONLY BIT_0 1061 1062 /* 1063 * 24 bit port ID type definition. 1064 */ 1065 typedef union { 1066 struct { 1067 uint8_t d_id[3]; 1068 uint8_t rsvd_1; 1069 }r; 1070 1071 uint32_t b24 : 24; 1072 1073 #if defined(_BIT_FIELDS_LTOH) 1074 struct { 1075 uint8_t al_pa; 1076 uint8_t area; 1077 uint8_t domain; 1078 uint8_t rsvd_1; 1079 }b; 1080 #elif defined(_BIT_FIELDS_HTOL) 1081 struct { 1082 uint8_t domain; 1083 uint8_t area; 1084 uint8_t al_pa; 1085 uint8_t rsvd_1; 1086 }b; 1087 #else 1088 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined 1089 #endif 1090 } port_id_t; 1091 1092 /* 1093 * Link list definitions. 1094 */ 1095 typedef struct ql_link { 1096 struct ql_link *prev; 1097 struct ql_link *next; 1098 void *base_address; 1099 struct ql_head *head; /* the queue this link is on */ 1100 } ql_link_t; 1101 1102 typedef struct ql_head { 1103 ql_link_t *first; 1104 ql_link_t *last; 1105 } ql_head_t; 1106 1107 /* 1108 * This is the per-command structure 1109 */ 1110 typedef struct ql_srb { 1111 /* Command link. */ 1112 ql_link_t cmd; 1113 1114 /* Watchdog link and timer. */ 1115 ql_link_t wdg; 1116 time_t wdg_q_time; 1117 time_t init_wdg_q_time; 1118 uint16_t isp_timeout; 1119 1120 /* FCA and FC Transport data. */ 1121 fc_packet_t *pkt; 1122 struct ql_adapter_state *ha; 1123 uint32_t magic_number; 1124 1125 /* unsolicited buffer context. */ 1126 dma_mem_t ub_buffer; 1127 uint32_t ub_type; 1128 uint32_t ub_size; 1129 1130 /* FCP command. */ 1131 fcp_cmd_t *fcp; 1132 1133 /* Request sense. */ 1134 uint32_t request_sense_length; 1135 caddr_t request_sense_ptr; 1136 1137 /* Device queue pointer. */ 1138 struct ql_lun *lun_queue; 1139 1140 /* Command state/status flags. */ 1141 volatile uint32_t flags; 1142 1143 /* Command IOCB context. */ 1144 void (*iocb)(struct ql_adapter_state *, 1145 struct ql_srb *, void *); 1146 uint32_t handle; 1147 uint16_t req_cnt; 1148 uint8_t retry_count; 1149 } ql_srb_t; 1150 1151 #define SRB_ISP_STARTED BIT_0 /* Command sent to ISP. */ 1152 #define SRB_ISP_COMPLETED BIT_1 /* ISP finished with command. */ 1153 #define SRB_RETRY BIT_2 /* Driver retrying command. */ 1154 #define SRB_POLL BIT_3 /* Poll for completion. */ 1155 #define SRB_WATCHDOG_ENABLED BIT_4 /* Command on watchdog list. */ 1156 #define SRB_ABORT BIT_5 /* SRB to be aborted. */ 1157 #define SRB_UB_IN_FCA BIT_6 /* FCA holds unsolicited buffer */ 1158 #define SRB_UB_IN_ISP BIT_7 /* ISP holds unsolicited buffer */ 1159 #define SRB_UB_CALLBACK BIT_8 /* Unsolicited callback needed. */ 1160 #define SRB_UB_RSCN BIT_9 /* Unsolicited RSCN callback. */ 1161 #define SRB_UB_FCP BIT_10 /* Unsolicited RSCN callback. */ 1162 #define SRB_FCP_CMD_PKT BIT_11 /* FCP command type packet. */ 1163 #define SRB_FCP_DATA_PKT BIT_12 /* FCP data type packet. */ 1164 #define SRB_FCP_RSP_PKT BIT_13 /* FCP response type packet. */ 1165 #define SRB_IP_PKT BIT_14 /* IP type packet. */ 1166 #define SRB_GENERIC_SERVICES_PKT BIT_15 /* Generic services type packet */ 1167 #define SRB_COMMAND_TIMEOUT BIT_16 /* Command timed out. */ 1168 #define SRB_ABORTING BIT_17 /* SRB aborting. */ 1169 #define SRB_IN_DEVICE_QUEUE BIT_18 /* In Device Queue */ 1170 #define SRB_IN_TOKEN_ARRAY BIT_19 /* In Token Array */ 1171 #define SRB_UB_FREE_REQUESTED BIT_20 /* UB Free requested */ 1172 #define SRB_UB_ACQUIRED BIT_21 /* UB selected for upcall */ 1173 #define SRB_MS_PKT BIT_22 /* Management Service pkt */ 1174 #define SRB_ELS_PKT BIT_23 /* Extended Link Services pkt */ 1175 1176 /* 1177 * This byte will be used to define flags for the LUN on the target. 1178 * Presently, we have untagged-command as one flag. Others can be 1179 * added later, if needed. 1180 */ 1181 typedef struct tgt_lun_flags { 1182 uint8_t 1183 untagged_pending:1, 1184 unused_bits:7; 1185 } tgt_lun_flags_t; 1186 1187 #define QL_IS_UNTAGGED_PENDING(q, lun_num) \ 1188 ((q->lun_flags[lun_num].untagged_pending == TRUE) ? 1 : 0) 1189 #define QL_SET_UNTAGGED_PENDING(q, lun_num) \ 1190 (q->lun_flags[lun_num].untagged_pending = TRUE) 1191 #define QL_CLEAR_UNTAGGED_PENDING(q, lun_num) \ 1192 (q->lun_flags[lun_num].untagged_pending = FALSE) 1193 1194 /* 1195 * Fibre Channel LUN Queue structure 1196 */ 1197 typedef struct ql_lun { 1198 /* Head command link. */ 1199 ql_head_t cmd; 1200 1201 struct ql_target *target_queue; 1202 1203 uint32_t flags; 1204 1205 /* LUN execution throttle. */ 1206 uint16_t lun_outcnt; 1207 1208 uint16_t lun_no; 1209 1210 ql_link_t link; 1211 } ql_lun_t; 1212 1213 /* 1214 * LUN Queue flags 1215 */ 1216 #define LQF_UNTAGGED_PENDING BIT_0 1217 1218 /* 1219 * Fibre Channel Device Queue structure 1220 */ 1221 typedef struct ql_target { 1222 /* Device queue lock. */ 1223 kmutex_t mutex; 1224 1225 /* Head target command link. */ 1226 ql_head_t tgt_cmd; 1227 1228 volatile uint32_t flags; 1229 port_id_t d_id; 1230 uint16_t loop_id; 1231 volatile uint16_t outcnt; /* # of cmds running in ISP */ 1232 uint32_t iidma_rate; 1233 1234 /* Device link. */ 1235 ql_link_t device; 1236 1237 /* Head watchdog link. */ 1238 ql_head_t wdg; 1239 1240 /* Unsolicited buffer IP data. */ 1241 uint32_t ub_frame_ro; 1242 uint16_t ub_sequence_length; 1243 uint16_t ub_loop_id; 1244 uint8_t ub_total_seg_cnt; 1245 uint8_t ub_seq_cnt; 1246 uint8_t ub_seq_id; 1247 1248 /* Port down retry counter. */ 1249 uint16_t port_down_retry_count; 1250 uint16_t qfull_retry_count; 1251 1252 /* logout sent state */ 1253 uint8_t logout_sent; 1254 1255 /* Data from Port database matches machine type. */ 1256 uint8_t master_state; 1257 uint8_t slave_state; 1258 port_id_t hard_addr; 1259 uint8_t port_name[8]; 1260 uint8_t node_name[8]; 1261 uint16_t cmn_features; 1262 uint16_t conc_sequences; 1263 uint16_t relative_offset; 1264 uint16_t class3_recipient_ctl; 1265 uint16_t class3_rcv_data_size; 1266 uint16_t class3_conc_sequences; 1267 uint16_t class3_open_sequences_per_exch; 1268 uint16_t prli_payload_length; 1269 uint16_t prli_svc_param_word_0; 1270 uint16_t prli_svc_param_word_3; 1271 1272 /* LUN context. */ 1273 ql_head_t lun_queues; 1274 ql_lun_t *last_lun_queue; 1275 } ql_tgt_t; 1276 1277 /* 1278 * Target Queue flags 1279 */ 1280 #define TQF_TAPE_DEVICE BIT_0 1281 #define TQF_QUEUE_SUSPENDED BIT_1 /* Queue suspended. */ 1282 #define TQF_FABRIC_DEVICE BIT_2 1283 #define TQF_INITIATOR_DEVICE BIT_3 1284 #define TQF_RSCN_RCVD BIT_4 1285 #define TQF_NEED_AUTHENTICATION BIT_5 1286 #define TQF_PLOGI_PROGRS BIT_6 1287 #define TQF_IIDMA_NEEDED BIT_7 1288 /* 1289 * Tempoary N_Port information 1290 */ 1291 typedef struct ql_n_port_info { 1292 uint16_t n_port_handle; 1293 uint8_t port_name[8]; /* Big endian. */ 1294 uint8_t node_name[8]; /* Big endian. */ 1295 } ql_n_port_info_t; 1296 1297 /* 1298 * iiDMA 1299 */ 1300 #define IIDMA_RATE_INIT 0xffffffff /* init state */ 1301 #define IIDMA_RATE_NDEF 0xfffffffe /* not defined in conf file */ 1302 #define IIDMA_RATE_1GB 0x0 1303 #define IIDMA_RATE_2GB 0x1 1304 #define IIDMA_RATE_4GB 0x3 1305 #define IIDMA_RATE_8GB 0x4 1306 #define IIDMA_RATE_10GB 0x13 1307 #define IIDMA_RATE_MAX IIDMA_RATE_10GB 1308 1309 /* 1310 * Kernel statistic structure definitions. 1311 */ 1312 typedef struct ql_device_stat { 1313 int logouts_recvd; 1314 int task_mgmt_failures; 1315 int data_ro_mismatches; 1316 int dl_len_mismatches; 1317 } ql_device_stat_t; 1318 1319 typedef struct ql_adapter_24xx_stat { 1320 int version; /* version of this struct */ 1321 int lip_count; /* lips forced */ 1322 int ncmds; /* outstanding commands */ 1323 ql_adapter_revlvl_t revlvl; /* adapter revision levels */ 1324 ql_device_stat_t d_stats[MAX_24_FIBRE_DEVICES]; /* per device stats */ 1325 } ql_adapter_stat_t; 1326 1327 /* 1328 * Firmware code segment. 1329 */ 1330 #define MAX_RISC_CODE_SEGMENTS 3 1331 typedef struct fw_code { 1332 caddr_t code; 1333 uint32_t addr; 1334 uint32_t length; 1335 } ql_fw_code_t; 1336 1337 /* diagnostic els ECHO defines */ 1338 #define QL_ECHO_CMD 0x10000000 /* echo opcode */ 1339 #define QL_ECHO_CMD_LENGTH 220 /* command length */ 1340 1341 /* DUMP state flags. */ 1342 #define QL_DUMPING BIT_0 1343 #define QL_DUMP_VALID BIT_1 1344 #define QL_DUMP_UPLOADED BIT_2 1345 1346 typedef struct el_trace_desc { 1347 kmutex_t mutex; 1348 uint16_t next; 1349 uint32_t trace_buffer_size; 1350 char *trace_buffer; 1351 } el_trace_desc_t; 1352 1353 /* 1354 * ql attach progress indication 1355 */ 1356 #define QL_SOFT_STATE_ALLOCED BIT_0 1357 #define QL_REGS_MAPPED BIT_1 1358 #define QL_HBA_BUFFER_SETUP BIT_2 1359 #define QL_MUTEX_CV_INITED BIT_3 1360 #define QL_INTR_ADDED BIT_4 1361 #define QL_CONFIG_SPACE_SETUP BIT_5 1362 #define QL_TASK_DAEMON_STARTED BIT_6 1363 #define QL_KSTAT_CREATED BIT_7 1364 #define QL_MINOR_NODE_CREATED BIT_8 1365 #define QL_FCA_TRAN_ALLOCED BIT_9 1366 #define QL_FCA_ATTACH_DONE BIT_10 1367 #define QL_IOMAP_IOBASE_MAPPED BIT_11 1368 #define QL_N_PORT_INFO_CREATED BIT_12 1369 /* Device queue head list size (based on AL_PA address). */ 1370 #define DEVICE_HEAD_LIST_SIZE 0x81 1371 1372 /* 1373 * Adapter state structure. 1374 */ 1375 typedef struct ql_adapter_state { 1376 ql_link_t hba; 1377 1378 kmutex_t mutex; 1379 volatile uint32_t flags; /* State flags. */ 1380 uint32_t state; 1381 port_id_t d_id; 1382 uint16_t loop_id; 1383 uint8_t topology; 1384 uint16_t sfp_stat; 1385 1386 uint16_t idle_timer; 1387 uint8_t loop_down_abort_time; 1388 uint8_t port_retry_timer; 1389 uint8_t loop_down_timer; 1390 uint8_t watchdog_timer; 1391 uint16_t r_a_tov; /* 2 * R_A_TOV + 5 */ 1392 1393 /* Task Daemon context. */ 1394 callb_cpr_t cprinfo; 1395 kmutex_t task_daemon_mutex; 1396 kcondvar_t cv_dr_suspended; 1397 kcondvar_t cv_task_daemon; 1398 volatile uint32_t task_daemon_flags; 1399 ql_head_t callback_queue; 1400 1401 /* Interrupt context. */ 1402 kmutex_t intr_mutex; 1403 uint8_t *iobase; 1404 uint8_t rev_id; 1405 uint16_t device_id; 1406 uint16_t subsys_id; 1407 uint16_t subven_id; 1408 uint16_t ven_id; 1409 uint16_t fw_class; 1410 ql_srb_t *status_srb; 1411 volatile uint8_t intr_claimed; 1412 1413 /* 1414 * ISP request queue, response queue, mailbox buffer and 1415 * IP receive queue buffer. 1416 */ 1417 dma_mem_t hba_buf; 1418 1419 /* ISP request queue context. */ 1420 kmutex_t req_ring_mutex; 1421 struct cmd_entry *request_ring_bp; 1422 struct cmd_entry *request_ring_ptr; 1423 uint64_t request_dvma; 1424 uint16_t req_ring_index; 1425 uint16_t req_q_cnt; /* # of available entries. */ 1426 ql_head_t pending_cmds; 1427 ql_srb_t **outstanding_cmds; 1428 uint16_t osc_index; 1429 1430 /* ISP response queue context. */ 1431 struct sts_entry *response_ring_bp; 1432 struct sts_entry *response_ring_ptr; 1433 uint64_t response_dvma; 1434 uint16_t rsp_ring_index; 1435 uint16_t isp_rsp_index; 1436 1437 /* Mailbox context. */ 1438 kmutex_t mbx_mutex; 1439 caddr_t mbx_bp; 1440 struct mbx_cmd *mcp; 1441 kcondvar_t cv_mbx_wait; 1442 kcondvar_t cv_mbx_intr; 1443 volatile uint8_t mailbox_flags; 1444 1445 /* ISP receive buffer queue context. */ 1446 ql_tgt_t *rcv_dev_q; 1447 struct rcvbuf *rcvbuf_ring_bp; 1448 struct rcvbuf *rcvbuf_ring_ptr; 1449 uint64_t rcvbuf_dvma; 1450 uint16_t rcvbuf_ring_index; 1451 1452 /* Unsolicited buffer data. */ 1453 uint16_t ub_outcnt; 1454 uint8_t ub_seq_id; 1455 uint8_t ub_command_count; 1456 uint8_t ub_notify_count; 1457 uint32_t ub_allocated; 1458 kmutex_t ub_mutex; 1459 kcondvar_t cv_ub; 1460 fc_unsol_buf_t **ub_array; 1461 1462 /* Head of device queue list. */ 1463 ql_head_t *dev; 1464 1465 /* Kernel statistics. */ 1466 kstat_t *k_stats; 1467 ql_adapter_stat_t *adapter_stats; 1468 1469 /* Solaris adapter configuration data */ 1470 ddi_acc_handle_t dev_handle; 1471 ddi_acc_handle_t pci_handle; /* config space */ 1472 ddi_acc_handle_t iomap_dev_handle; 1473 caddr_t iomap_iobase; 1474 dev_info_t *dip; 1475 ddi_iblock_cookie_t iblock_cookie; 1476 fc_fca_tran_t *tran; 1477 uint32_t instance; 1478 int8_t *devpath; 1479 uint32_t fru_hba_index; 1480 uint32_t fru_port_index; 1481 uint8_t adapInfo[18]; 1482 1483 /* Adapter context */ 1484 la_els_logi_t loginparams; 1485 fc_fca_bind_info_t bind_info; 1486 ddi_modhandle_t fw_module; 1487 uint16_t fw_major_version; 1488 uint16_t fw_minor_version; 1489 uint16_t fw_subminor_version; 1490 uint16_t fw_attributes; 1491 uint32_t fw_ext_memory_size; 1492 uint32_t parity_pause_errors; 1493 uint16_t parity_hccr_err; 1494 uint32_t parity_stat_err; 1495 reg_off_t *reg_off; 1496 caddr_t risc_code; 1497 uint32_t risc_code_size; 1498 ql_fw_code_t risc_fw[MAX_RISC_CODE_SEGMENTS]; 1499 uint32_t risc_dump_size; 1500 void (*fcp_cmd)(struct ql_adapter_state *, 1501 ql_srb_t *, void *); 1502 void (*ip_cmd)(struct ql_adapter_state *, 1503 ql_srb_t *, void *); 1504 void (*ms_cmd)(struct ql_adapter_state *, 1505 ql_srb_t *, void *); 1506 uint8_t cmd_segs; 1507 uint8_t cmd_cont_segs; 1508 1509 /* NVRAM configuration data */ 1510 uint32_t cfg_flags; 1511 ql_comb_init_cb_t init_ctrl_blk; 1512 ql_comb_ip_init_cb_t ip_init_ctrl_blk; 1513 uint16_t nvram_version; 1514 uint16_t adapter_features; 1515 uint32_t fw_transfer_size; 1516 uint16_t execution_throttle; 1517 uint16_t port_down_retry_count; 1518 uint8_t port_down_retry_delay; 1519 uint8_t qfull_retry_count; 1520 uint8_t qfull_retry_delay; 1521 uint16_t serdes_param[4]; 1522 uint8_t loop_reset_delay; 1523 1524 /* Power management context. */ 1525 kmutex_t pm_mutex; 1526 uint32_t busy; 1527 uint8_t power_level; 1528 uint8_t pm_capable; 1529 uint8_t config_saved; 1530 uint8_t lip_on_panic; 1531 port_id_t port_hard_address; 1532 1533 /* sbus card data */ 1534 caddr_t sbus_fpga_iobase; 1535 ddi_acc_handle_t sbus_fpga_dev_handle; 1536 ddi_acc_handle_t sbus_config_handle; 1537 caddr_t sbus_config_base; 1538 1539 /* XIOCTL context pointer. */ 1540 struct ql_xioctl *xioctl; 1541 1542 kmutex_t cache_mutex; 1543 struct ql_fcache *fcache; 1544 int8_t *vcache; 1545 1546 /* AIF (Advanced Interrupt Framework) support */ 1547 ddi_intr_handle_t *htable; 1548 uint32_t hsize; 1549 int32_t intr_cnt; 1550 uint32_t intr_pri; 1551 int32_t intr_cap; 1552 uint32_t iflags; 1553 1554 /* PCI maximum read request override */ 1555 uint16_t pci_max_read_req; 1556 1557 /* port manage mutex */ 1558 kmutex_t portmutex; 1559 uint16_t maximum_luns_per_target; 1560 1561 /* f/w dump mutex */ 1562 uint32_t ql_dump_size; 1563 uint32_t ql_dump_state; 1564 void *ql_dump_ptr; 1565 kmutex_t dump_mutex; 1566 1567 uint8_t fwwait; 1568 1569 dma_mem_t fwexttracebuf; /* extended trace */ 1570 dma_mem_t fwfcetracebuf; /* event trace */ 1571 uint32_t fwfcetraceopt; 1572 uint32_t flash_errlog_start; /* 32bit word addr */ 1573 uint32_t flash_errlog_ptr; /* 32bit word addr */ 1574 uint8_t send_plogi_timer; 1575 1576 /* Virtual port context. */ 1577 fca_port_attrs_t *pi_attrs; 1578 struct ql_adapter_state *pha; 1579 struct ql_adapter_state *vp_next; 1580 uint8_t vp_index; 1581 1582 uint16_t free_loop_id; 1583 1584 /* Tempoary N_Port information */ 1585 struct ql_n_port_info *n_port; 1586 1587 void (*els_cmd)(struct ql_adapter_state *, 1588 ql_srb_t *, void *); 1589 el_trace_desc_t *el_trace_desc; 1590 1591 uint32_t flash_data_addr; 1592 uint32_t flash_fw_addr; 1593 uint32_t flash_golden_fw_addr; 1594 uint32_t flash_vpd_addr; 1595 uint32_t flash_nvram_addr; 1596 uint32_t flash_desc_addr; 1597 uint32_t mpi_capability_list; 1598 uint8_t phy_fw_major_version; 1599 uint8_t phy_fw_minor_version; 1600 uint8_t phy_fw_subminor_version; 1601 uint8_t mpi_fw_major_version; 1602 uint8_t mpi_fw_minor_version; 1603 uint8_t mpi_fw_subminor_version; 1604 1605 uint8_t idc_flash_acc; 1606 uint8_t idc_restart_mpi; 1607 uint16_t idc_mb[8]; 1608 uint8_t restart_mpi_timer; 1609 uint8_t flash_acc_timer; 1610 1611 /* VLAN ID and MAC address */ 1612 uint8_t fcoe_vnport_mac[6]; 1613 uint16_t fabric_params; 1614 uint16_t fcoe_vlan_id; 1615 uint16_t fcoe_fcf_idx; 1616 } ql_adapter_state_t; 1617 1618 /* 1619 * adapter state flags 1620 */ 1621 #define FCA_BOUND BIT_0 1622 #define QL_OPENED BIT_1 1623 #define ONLINE BIT_2 1624 #define INTERRUPTS_ENABLED BIT_3 1625 #define ABORT_CMDS_LOOP_DOWN_TMO BIT_4 1626 #define POINT_TO_POINT BIT_5 1627 #define IP_ENABLED BIT_6 1628 #define IP_INITIALIZED BIT_7 1629 #define MENLO_LOGIN_OPERATIONAL BIT_8 1630 #define ADAPTER_SUSPENDED BIT_9 1631 #define ADAPTER_TIMER_BUSY BIT_10 1632 #define PARITY_ERROR BIT_11 1633 #define FLASH_ERRLOG_MARKER BIT_12 1634 #define VP_ENABLED BIT_13 1635 #define FDISC_ENABLED BIT_14 1636 #define FUNCTION_1 BIT_15 1637 #define MPI_RESET_NEEDED BIT_16 1638 1639 /* 1640 * task daemon flags 1641 */ 1642 #define TASK_DAEMON_STOP_FLG BIT_0 1643 #define TASK_DAEMON_SLEEPING_FLG BIT_1 1644 #define TASK_DAEMON_ALIVE_FLG BIT_2 1645 #define TASK_DAEMON_IDLE_CHK_FLG BIT_3 1646 #define SUSPENDED_WAKEUP_FLG BIT_4 1647 #define FC_STATE_CHANGE BIT_5 1648 #define NEED_UNSOLICITED_BUFFERS BIT_6 1649 #define RESET_MARKER_NEEDED BIT_7 1650 #define RESET_ACTIVE BIT_8 1651 #define ISP_ABORT_NEEDED BIT_9 1652 #define ABORT_ISP_ACTIVE BIT_10 1653 #define LOOP_RESYNC_NEEDED BIT_11 1654 #define LOOP_RESYNC_ACTIVE BIT_12 1655 #define LOOP_DOWN BIT_13 1656 #define DRIVER_STALL BIT_14 1657 #define COMMAND_WAIT_NEEDED BIT_15 1658 #define COMMAND_WAIT_ACTIVE BIT_16 1659 #define STATE_ONLINE BIT_17 1660 #define ABORT_QUEUES_NEEDED BIT_18 1661 #define TASK_DAEMON_STALLED_FLG BIT_19 1662 #define TASK_THREAD_CALLED BIT_20 1663 #define FIRMWARE_UP BIT_21 1664 #define LIP_RESET_PENDING BIT_22 1665 #define FIRMWARE_LOADED BIT_23 1666 #define RSCN_UPDATE_NEEDED BIT_24 1667 #define HANDLE_PORT_BYPASS_CHANGE BIT_25 1668 #define PORT_RETRY_NEEDED BIT_26 1669 #define TASK_DAEMON_POWERING_DOWN BIT_27 1670 #define TD_IIDMA_NEEDED BIT_28 1671 #define SEND_PLOGI BIT_29 1672 #define IDC_ACK_NEEDED BIT_30 1673 1674 /* 1675 * Mailbox flags 1676 */ 1677 #define MBX_WANT_FLG BIT_0 1678 #define MBX_BUSY_FLG BIT_1 1679 #define MBX_INTERRUPT BIT_2 1680 #define MBX_ABORT BIT_3 1681 1682 /* 1683 * Configuration flags 1684 */ 1685 #define CFG_ENABLE_HARD_ADDRESS BIT_0 1686 #define CFG_ENABLE_64BIT_ADDRESSING BIT_1 1687 #define CFG_ENABLE_LIP_RESET BIT_2 1688 #define CFG_ENABLE_FULL_LIP_LOGIN BIT_3 1689 #define CFG_ENABLE_TARGET_RESET BIT_4 1690 #define CFG_ENABLE_LINK_DOWN_REPORTING BIT_5 1691 #define CFG_DISABLE_EXTENDED_LOGGING_TRACE BIT_6 1692 #define CFG_ENABLE_FCP_2_SUPPORT BIT_7 1693 #define CFG_MULTI_CHIP_ADAPTER BIT_8 1694 #define CFG_SBUS_CARD BIT_9 1695 #define CFG_CTRL_2300 BIT_10 1696 #define CFG_CTRL_6322 BIT_11 1697 #define CFG_CTRL_2200 BIT_12 1698 #define CFG_CTRL_2422 BIT_13 1699 #define CFG_CTRL_25XX BIT_14 1700 #define CFG_ENABLE_EXTENDED_LOGGING BIT_15 1701 #define CFG_DISABLE_RISC_CODE_LOAD BIT_16 1702 #define CFG_SET_CACHE_LINE_SIZE_1 BIT_17 1703 #define CFG_CTRL_MENLO BIT_18 1704 #define CFG_EXT_FW_INTERFACE BIT_19 1705 #define CFG_LOAD_FLASH_FW BIT_20 1706 #define CFG_DUMP_MAILBOX_TIMEOUT BIT_21 1707 #define CFG_DUMP_ISP_SYSTEM_ERROR BIT_22 1708 #define CFG_DUMP_DRIVER_COMMAND_TIMEOUT BIT_23 1709 #define CFG_DUMP_LOOP_OFFLINE_TIMEOUT BIT_24 1710 #define CFG_ENABLE_FWEXTTRACE BIT_25 1711 #define CFG_ENABLE_FWFCETRACE BIT_26 1712 #define CFG_FW_MISMATCH BIT_27 1713 #define CFG_CTRL_81XX BIT_28 1714 1715 #define CFG_CTRL_2425 (CFG_CTRL_2422 | CFG_CTRL_25XX) 1716 #define CFG_CTRL_2581 (CFG_CTRL_25XX | CFG_CTRL_81XX) 1717 #define CFG_CTRL_242581 (CFG_CTRL_2422 | CFG_CTRL_25XX | CFG_CTRL_81XX) 1718 1719 #define CFG_IST(ha, cfgflags) (ha->cfg_flags & cfgflags) 1720 1721 /* 1722 * Interrupt configuration flags 1723 */ 1724 #define IFLG_INTR_LEGACY BIT_0 1725 #define IFLG_INTR_FIXED BIT_1 1726 #define IFLG_INTR_MSI BIT_2 1727 #define IFLG_INTR_MSIX BIT_3 1728 1729 #define IFLG_INTR_AIF (IFLG_INTR_MSI | IFLG_INTR_FIXED | IFLG_INTR_MSIX) 1730 1731 /* 1732 * Macros to help code, maintain, etc. 1733 */ 1734 #define LSB(x) (uint8_t)(x) 1735 #define MSB(x) (uint8_t)((uint16_t)(x) >> 8) 1736 #define MSW(x) (uint16_t)((uint32_t)(x) >> 16) 1737 #define LSW(x) (uint16_t)(x) 1738 #define LSD(x) (uint32_t)(x) 1739 #define MSD(x) (uint32_t)((uint64_t)(x) >> 32) 1740 1741 #define SHORT_TO_LONG(lsw, msw) (uint32_t)((uint16_t)msw << 16 | (uint16_t)lsw) 1742 #define CHAR_TO_SHORT(lsb, msb) (uint16_t)((uint8_t)msb << 8 | (uint8_t)lsb) 1743 #define CHAR_TO_LONG(lsb, b1, b2, msb) \ 1744 (uint32_t)(SHORT_TO_LONG(CHAR_TO_SHORT(lsb, b1), \ 1745 CHAR_TO_SHORT(b2, msb))) 1746 1747 /* Little endian machine correction defines. */ 1748 #ifdef _LITTLE_ENDIAN 1749 #define LITTLE_ENDIAN_16(x) 1750 #define LITTLE_ENDIAN_24(x) 1751 #define LITTLE_ENDIAN_32(x) 1752 #define LITTLE_ENDIAN_64(x) 1753 #define LITTLE_ENDIAN(bp, bytes) 1754 #define BIG_ENDIAN_16(x) ql_chg_endian((uint8_t *)x, 2) 1755 #define BIG_ENDIAN_24(x) ql_chg_endian((uint8_t *)x, 3) 1756 #define BIG_ENDIAN_32(x) ql_chg_endian((uint8_t *)x, 4) 1757 #define BIG_ENDIAN_64(x) ql_chg_endian((uint8_t *)x, 8) 1758 #define BIG_ENDIAN(bp, bytes) ql_chg_endian((uint8_t *)bp, bytes) 1759 #endif /* _LITTLE_ENDIAN */ 1760 1761 /* Big endian machine correction defines. */ 1762 #ifdef _BIG_ENDIAN 1763 #define LITTLE_ENDIAN_16(x) ql_chg_endian((uint8_t *)x, 2) 1764 #define LITTLE_ENDIAN_24(x) ql_chg_endian((uint8_t *)x, 3) 1765 #define LITTLE_ENDIAN_32(x) ql_chg_endian((uint8_t *)x, 4) 1766 #define LITTLE_ENDIAN_64(x) ql_chg_endian((uint8_t *)x, 8) 1767 #define LITTLE_ENDIAN(bp, bytes) ql_chg_endian((uint8_t *)bp, bytes) 1768 #define BIG_ENDIAN_16(x) 1769 #define BIG_ENDIAN_24(x) 1770 #define BIG_ENDIAN_32(x) 1771 #define BIG_ENDIAN_64(x) 1772 #define BIG_ENDIAN(bp, bytes) 1773 #endif /* _BIG_ENDIAN */ 1774 1775 #define LOCAL_LOOP_ID(x) (x <= LAST_LOCAL_LOOP_ID) 1776 1777 #define FABRIC_LOOP_ID(x) (x == FL_PORT_LOOP_ID || \ 1778 x == SIMPLE_NAME_SERVER_LOOP_ID) 1779 1780 #define SNS_LOOP_ID(x) (x >= SNS_FIRST_LOOP_ID && \ 1781 x <= SNS_LAST_LOOP_ID) 1782 1783 #define BROADCAST_LOOP_ID(x) (x == IP_BROADCAST_LOOP_ID) 1784 1785 #define VALID_LOOP_ID(x) (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x) || \ 1786 FABRIC_LOOP_ID(x) || BROADCAST_LOOP_ID(x)) 1787 1788 #define VALID_N_PORT_HDL(x) (x <= LAST_N_PORT_HDL || \ 1789 (x >= SNS_24XX_HDL && x <= BROADCAST_24XX_HDL)) 1790 1791 #define VALID_DEVICE_ID(ha, x) (CFG_IST(ha, CFG_CTRL_242581) ? \ 1792 VALID_N_PORT_HDL(x) : VALID_LOOP_ID(x)) 1793 1794 #define VALID_TARGET_ID(ha, x) (CFG_IST(ha, CFG_CTRL_242581) ? \ 1795 (x <= LAST_N_PORT_HDL) : (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x))) 1796 1797 #define RESERVED_LOOP_ID(ha, x) (CFG_IST(ha, CFG_CTRL_242581) ? \ 1798 (x > LAST_N_PORT_HDL && x <= FL_PORT_24XX_HDL) : \ 1799 (x >= FL_PORT_LOOP_ID && x <= SIMPLE_NAME_SERVER_LOOP_ID)) 1800 1801 #define QL_LOOP_TRANSITION (RESET_MARKER_NEEDED | RESET_ACTIVE | \ 1802 ISP_ABORT_NEEDED | ABORT_ISP_ACTIVE | \ 1803 LOOP_RESYNC_NEEDED | LOOP_RESYNC_ACTIVE | \ 1804 COMMAND_WAIT_NEEDED | COMMAND_WAIT_ACTIVE) 1805 1806 #define QL_SUSPENDED (QL_LOOP_TRANSITION | LOOP_DOWN | DRIVER_STALL) 1807 1808 #define LOOP_RECONFIGURE(ha) (ha->task_daemon_flags & (QL_LOOP_TRANSITION | \ 1809 DRIVER_STALL)) 1810 1811 #define DRIVER_SUSPENDED(ha) (ha->task_daemon_flags & QL_SUSPENDED) 1812 1813 #define LOOP_NOT_READY(ha) (ha->task_daemon_flags & (QL_LOOP_TRANSITION | \ 1814 LOOP_DOWN)) 1815 1816 #define LOOP_READY(ha) (LOOP_NOT_READY(ha) == 0) 1817 1818 #define QL_TASK_PENDING(ha) ( \ 1819 ha->task_daemon_flags & (QL_LOOP_TRANSITION | ABORT_QUEUES_NEEDED | \ 1820 PORT_RETRY_NEEDED) || ha->callback_queue.first != NULL) 1821 1822 #define QL_DAEMON_NOT_ACTIVE(ha) ( \ 1823 !(ha->task_daemon_flags & TASK_DAEMON_ALIVE_FLG) || \ 1824 ha->task_daemon_flags & (TASK_DAEMON_SLEEPING_FLG | \ 1825 TASK_DAEMON_STOP_FLG)) 1826 1827 #define QL_DAEMON_SUSPENDED(ha) (\ 1828 (((ha)->cprinfo.cc_events & CALLB_CPR_START) ||\ 1829 ((ha)->flags & ADAPTER_SUSPENDED))) 1830 1831 /* 1832 * Locking Macro Definitions 1833 */ 1834 #define GLOBAL_STATE_LOCK() mutex_enter(&ql_global_mutex) 1835 #define GLOBAL_STATE_UNLOCK() mutex_exit(&ql_global_mutex) 1836 1837 #define TRY_DEVICE_QUEUE_LOCK(q) mutex_tryenter(&q->mutex) 1838 #define DEVICE_QUEUE_LOCK(q) mutex_enter(&q->mutex) 1839 #define DEVICE_QUEUE_UNLOCK(q) mutex_exit(&q->mutex) 1840 1841 #define MBX_REGISTER_LOCK(ha) mutex_enter(&ha->pha->mbx_mutex) 1842 #define MBX_REGISTER_UNLOCK(ha) mutex_exit(&ha->pha->mbx_mutex) 1843 1844 #define INTR_LOCK(ha) mutex_enter(&ha->pha->intr_mutex) 1845 #define INTR_UNLOCK(ha) mutex_exit(&ha->pha->intr_mutex) 1846 1847 #define TASK_DAEMON_LOCK(ha) mutex_enter(&ha->pha->task_daemon_mutex) 1848 #define TASK_DAEMON_UNLOCK(ha) mutex_exit(&ha->pha->task_daemon_mutex) 1849 1850 #define REQUEST_RING_LOCK(ha) mutex_enter(&ha->pha->req_ring_mutex) 1851 #define REQUEST_RING_UNLOCK(ha) mutex_exit(&ha->pha->req_ring_mutex) 1852 1853 #define CACHE_LOCK(ha) mutex_enter(&ha->pha->cache_mutex); 1854 #define CACHE_UNLOCK(ha) mutex_exit(&ha->pha->cache_mutex); 1855 1856 #define PORTMANAGE_LOCK(ha) mutex_enter(&ha->pha->portmutex); 1857 #define PORTMANAGE_UNLOCK(ha) mutex_exit(&ha->pha->portmutex); 1858 1859 #define ADAPTER_STATE_LOCK(ha) mutex_enter(&ha->pha->mutex) 1860 #define ADAPTER_STATE_UNLOCK(ha) mutex_exit(&ha->pha->mutex) 1861 1862 #define QL_DUMP_LOCK(ha) mutex_enter(&ha->pha->dump_mutex) 1863 #define QL_DUMP_UNLOCK(ha) mutex_exit(&ha->pha->dump_mutex) 1864 1865 #define QL_PM_LOCK(ha) mutex_enter(&ha->pha->pm_mutex) 1866 #define QL_PM_UNLOCK(ha) mutex_exit(&ha->pha->pm_mutex) 1867 1868 #define QL_UB_LOCK(ha) mutex_enter(&ha->pha->ub_mutex) 1869 #define QL_UB_UNLOCK(ha) mutex_exit(&ha->pha->ub_mutex) 1870 1871 #define GLOBAL_HW_LOCK() mutex_enter(&ql_global_hw_mutex) 1872 #define GLOBAL_HW_UNLOCK() mutex_exit(&ql_global_hw_mutex) 1873 1874 /* 1875 * PCI power management control/status register location 1876 */ 1877 #define QL_PM_CS_REG 0x48 1878 1879 /* 1880 * ql component 1881 */ 1882 #define QL_POWER_COMPONENT 0 1883 1884 typedef struct ql_config_space { 1885 uint16_t chs_command; 1886 uint8_t chs_cache_line_size; 1887 uint8_t chs_latency_timer; 1888 uint8_t chs_header_type; 1889 uint8_t chs_sec_latency_timer; 1890 uint8_t chs_bridge_control; 1891 uint32_t chs_base0; 1892 uint32_t chs_base1; 1893 uint32_t chs_base2; 1894 uint32_t chs_base3; 1895 uint32_t chs_base4; 1896 uint32_t chs_base5; 1897 } ql_config_space_t; 1898 1899 #ifdef USE_DDI_INTERFACES 1900 1901 #define QL_SAVE_CONFIG_REGS(dip) pci_save_config_regs(dip) 1902 #define QL_RESTORE_CONFIG_REGS(dip) pci_restore_config_regs(dip) 1903 1904 #else /* USE_DDI_INTERFACES */ 1905 1906 #define QL_SAVE_CONFIG_REGS(dip) ql_save_config_regs(dip) 1907 #define QL_RESTORE_CONFIG_REGS(dip) ql_restore_config_regs(dip) 1908 1909 #endif /* USE_DDI_INTERFACES */ 1910 1911 #define QL_IS_SET(x, y) (((x) & (y)) == (y)) 1912 1913 /* 1914 * QL local function return status codes 1915 */ 1916 #define QL_SUCCESS 0x4000 1917 #define QL_INVALID_COMMAND 0x4001 1918 #define QL_INTERFACE_ERROR 0x4002 1919 #define QL_TEST_FAILED 0x4003 1920 #define QL_COMMAND_ERROR 0x4005 1921 #define QL_PARAMETER_ERROR 0x4006 1922 #define QL_PORT_ID_USED 0x4007 1923 #define QL_LOOP_ID_USED 0x4008 1924 #define QL_ALL_IDS_IN_USE 0x4009 1925 #define QL_NOT_LOGGED_IN 0x400A 1926 #define QL_LOOP_DOWN 0x400B 1927 #define QL_LOOP_BACK_ERROR 0x400C 1928 #define QL_CHECKSUM_ERROR 0x4010 1929 #define QL_CONSUMED 0x4011 1930 1931 #define QL_FUNCTION_TIMEOUT 0x100 1932 #define QL_FUNCTION_PARAMETER_ERROR 0x101 1933 #define QL_FUNCTION_FAILED 0x102 1934 #define QL_MEMORY_ALLOC_FAILED 0x103 1935 #define QL_FABRIC_NOT_INITIALIZED 0x104 1936 #define QL_LOCK_TIMEOUT 0x105 1937 #define QL_ABORTED 0x106 1938 #define QL_FUNCTION_SUSPENDED 0x107 1939 #define QL_END_OF_DATA 0x108 1940 #define QL_IP_UNSUPPORTED 0x109 1941 #define QL_PM_ERROR 0x10a 1942 #define QL_DATA_EXISTS 0x10b 1943 #define QL_NOT_SUPPORTED 0x10c 1944 #define QL_MEMORY_FULL 0x10d 1945 #define QL_FW_NOT_SUPPORTED 0x10e 1946 #define QL_FWMODLOAD_FAILED 0x10f 1947 #define QL_FWSYM_NOT_FOUND 0x110 1948 #define QL_LOGIN_NOT_SUPPORTED 0x111 1949 1950 /* 1951 * SBus card FPGA register offsets. 1952 */ 1953 #define FPGA_CONF 0x100 1954 #define FPGA_EEPROM_LOADDR 0x102 1955 #define FPGA_EEPROM_HIADDR 0x104 1956 #define FPGA_EEPROM_DATA 0x106 1957 #define FPGA_REVISION 0x108 1958 1959 #define SBUS_FLASH_WRITE_ENABLE 0x0080 1960 #define QL_SBUS_FCODE_SIZE 0x30000 1961 #define QL_FCODE_OFFSET 0 1962 #define QL_FPGA_SIZE 0x40000 1963 #define QL_FPGA_OFFSET 0x40000 1964 1965 #define READ_PORT_ID(addr) ((uint32_t)((((uint32_t)((addr)[0])) << 16) | \ 1966 (((uint32_t)((addr)[1])) << 8) | \ 1967 (((uint32_t)((addr)[2]))))) 1968 #define READ_PORT_NAME(addr) ((u_longlong_t)((((uint64_t)((addr)[0])) << 56) | \ 1969 (((uint64_t)((addr)[1])) << 48) | \ 1970 (((uint64_t)((addr)[2])) << 40) | \ 1971 (((uint64_t)((addr)[3])) << 32) | \ 1972 (((uint64_t)((addr)[4])) << 24) | \ 1973 (((uint64_t)((addr)[5])) << 16) | \ 1974 (((uint64_t)((addr)[6])) << 8) | \ 1975 (((uint64_t)((addr)[7]))))) 1976 /* 1977 * Structure used to associate cmds with strings which describe them. 1978 */ 1979 typedef struct cmd_table_entry { 1980 uint16_t cmd; 1981 char *string; 1982 } cmd_table_t; 1983 1984 /* 1985 * ELS command table initializer 1986 */ 1987 #define ELS_CMD_TABLE() \ 1988 { \ 1989 {LA_ELS_RJT, "LA_ELS_RJT"}, \ 1990 {LA_ELS_ACC, "LA_ELS_ACC"}, \ 1991 {LA_ELS_PLOGI, "LA_ELS_PLOGI"}, \ 1992 {LA_ELS_PDISC, "LA_ELS_PDISC"}, \ 1993 {LA_ELS_FLOGI, "LA_ELS_FLOGI"}, \ 1994 {LA_ELS_FDISC, "LA_ELS_FDISC"}, \ 1995 {LA_ELS_LOGO, "LA_ELS_LOGO"}, \ 1996 {LA_ELS_PRLI, "LA_ELS_PRLI"}, \ 1997 {LA_ELS_PRLO, "LA_ELS_PRLO"}, \ 1998 {LA_ELS_ADISC, "LA_ELS_ADISC"}, \ 1999 {LA_ELS_LINIT, "LA_ELS_LINIT"}, \ 2000 {LA_ELS_LPC, "LA_ELS_LPC"}, \ 2001 {LA_ELS_LSTS, "LA_ELS_LSTS"}, \ 2002 {LA_ELS_SCR, "LA_ELS_SCR"}, \ 2003 {LA_ELS_RSCN, "LA_ELS_RSCN"}, \ 2004 {LA_ELS_FARP_REQ, "LA_ELS_FARP_REQ"}, \ 2005 {LA_ELS_FARP_REPLY, "LA_ELS_FARP_REPLY"}, \ 2006 {LA_ELS_RLS, "LA_ELS_RLS"}, \ 2007 {LA_ELS_RNID, "LA_ELS_RNID"}, \ 2008 {NULL, NULL} \ 2009 } 2010 2011 /* 2012 * ELS Passthru IOCB data segment descriptor. 2013 */ 2014 typedef struct data_seg_desc { 2015 uint32_t addr[2]; 2016 uint32_t length; 2017 } data_seg_desc_t; 2018 2019 /* 2020 * ELS descriptor used to abstract the hosts fibre channel packet 2021 * from the ISP ELS code. 2022 */ 2023 typedef struct els_desc { 2024 uint8_t els; /* the ELS command code */ 2025 ddi_acc_handle_t els_handle; 2026 uint16_t n_port_handle; 2027 port_id_t d_id; 2028 port_id_t s_id; 2029 uint16_t control_flags; 2030 uint32_t cmd_byte_count; 2031 uint32_t rsp_byte_count; 2032 data_seg_desc_t tx_dsd; /* FC frame payload */ 2033 data_seg_desc_t rx_dsd; /* ELS resp payload buffer */ 2034 } els_descriptor_t; 2035 2036 typedef struct prli_svc_pram_resp_page { 2037 uint8_t type_code; 2038 uint8_t type_code_ext; 2039 uint16_t prli_resp_flags; 2040 uint32_t orig_process_associator; 2041 uint32_t resp_process_associator; 2042 uint32_t common_parameters; 2043 } prli_svc_pram_resp_page_t; 2044 2045 /* 2046 * PRLI accept Service Parameter Page Word 3 2047 */ 2048 #define PRLI_W3_WRITE_FCP_XFR_RDY_DISABLED BIT_0 2049 #define PRLI_W3_READ_FCP_XFR_RDY_DISABLED BIT_1 2050 #define PRLI_W3_OBSOLETE_BIT_2 BIT_2 2051 #define PRLI_W3_OBSOLETE_BIT_3 BIT_3 2052 #define PRLI_W3_TARGET_FUNCTION BIT_4 2053 #define PRLI_W3_INITIATOR_FUNCTION BIT_5 2054 #define PRLI_W3_DATA_OVERLAY_ALLOWED BIT_6 2055 #define PRLI_W3_CONFIRMED_COMP_ALLOWED BIT_7 2056 #define PRLI_W3_RETRY BIT_8 2057 #define PRLI_W3_TASK_RETRY_ID_REQUESTED BIT_9 2058 2059 typedef struct prli_acc_resp { 2060 uint8_t ls_code; 2061 uint8_t page_length; 2062 uint16_t payload_length; 2063 struct prli_svc_pram_resp_page svc_params; 2064 } prli_acc_resp_t; 2065 2066 #define EL_TRACE_BUF_SIZE 8192 2067 2068 /* 2069 * Global Data in ql_api.c source file. 2070 */ 2071 extern void *ql_state; /* for soft state routine */ 2072 extern uint32_t ql_os_release_level; 2073 extern ql_head_t ql_hba; 2074 extern kmutex_t ql_global_mutex; 2075 extern kmutex_t ql_global_hw_mutex; 2076 extern kmutex_t ql_global_el_mutex; 2077 extern uint8_t ql_ip_fast_post_count; 2078 extern uint32_t ql_ip_buffer_count; 2079 extern uint32_t ql_ip_low_water; 2080 extern uint8_t ql_alpa_to_index[]; 2081 extern uint32_t ql_gfru_hba_index; 2082 2083 /* 2084 * Global Function Prototypes in ql_api.c source file. 2085 */ 2086 void ql_chg_endian(uint8_t *, size_t); 2087 void ql_populate_hba_fru_details(ql_adapter_state_t *, fc_fca_port_info_t *); 2088 void ql_setup_fruinfo(ql_adapter_state_t *); 2089 uint16_t ql_pci_config_get16(ql_adapter_state_t *, off_t); 2090 uint32_t ql_pci_config_get32(ql_adapter_state_t *, off_t); 2091 void ql_pci_config_put8(ql_adapter_state_t *, off_t, uint8_t); 2092 void ql_pci_config_put16(ql_adapter_state_t *, off_t, uint16_t); 2093 void ql_delay(ql_adapter_state_t *, clock_t); 2094 void ql_awaken_task_daemon(ql_adapter_state_t *, ql_srb_t *, uint32_t, 2095 uint32_t); 2096 int ql_abort_device(ql_adapter_state_t *, ql_tgt_t *, int); 2097 int ql_binary_fw_dump(ql_adapter_state_t *, int); 2098 void ql_done(ql_link_t *); 2099 int ql_24xx_flash_id(ql_adapter_state_t *); 2100 int ql_24xx_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t); 2101 int ql_poll_flash(ql_adapter_state_t *, uint32_t, uint8_t); 2102 void ql_flash_disable(ql_adapter_state_t *); 2103 void ql_flash_enable(ql_adapter_state_t *); 2104 int ql_erase_flash(ql_adapter_state_t *, int); 2105 void ql_write_flash_byte(ql_adapter_state_t *, uint32_t, uint8_t); 2106 uint8_t ql_read_flash_byte(ql_adapter_state_t *, uint32_t); 2107 int ql_24xx_read_flash(ql_adapter_state_t *, uint32_t, uint32_t *); 2108 int ql_24xx_write_flash(ql_adapter_state_t *, uint32_t, uint32_t); 2109 fc_unsol_buf_t *ql_get_unsolicited_buffer(ql_adapter_state_t *, uint32_t); 2110 size_t ql_ascii_fw_dump(ql_adapter_state_t *, caddr_t); 2111 void ql_add_link_b(ql_head_t *, ql_link_t *); 2112 void ql_add_link_t(ql_head_t *, ql_link_t *); 2113 void ql_remove_link(ql_head_t *, ql_link_t *); 2114 void ql_next(ql_adapter_state_t *, ql_lun_t *); 2115 void ql_send_logo(ql_adapter_state_t *, ql_tgt_t *, ql_head_t *); 2116 void ql_cthdr_endian(ddi_acc_handle_t, caddr_t, boolean_t); 2117 ql_tgt_t *ql_d_id_to_queue(ql_adapter_state_t *, port_id_t); 2118 ql_tgt_t *ql_loop_id_to_queue(ql_adapter_state_t *, uint16_t); 2119 void ql_cmd_wait(ql_adapter_state_t *); 2120 void ql_loop_online(ql_adapter_state_t *); 2121 ql_tgt_t *ql_dev_init(ql_adapter_state_t *, port_id_t, uint16_t); 2122 int ql_ub_frame_hdr(ql_adapter_state_t *, ql_tgt_t *, uint16_t, ql_head_t *); 2123 void ql_rcv_rscn_els(ql_adapter_state_t *, uint16_t *, ql_head_t *); 2124 int ql_stall_driver(ql_adapter_state_t *, uint32_t); 2125 void ql_restart_driver(ql_adapter_state_t *); 2126 int ql_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t); 2127 int ql_get_dma_mem(ql_adapter_state_t *, dma_mem_t *, uint32_t, 2128 mem_alloc_type_t, mem_alignment_t); 2129 int ql_alloc_phys(ql_adapter_state_t *, dma_mem_t *, int); 2130 void ql_free_phys(ql_adapter_state_t *, dma_mem_t *); 2131 void ql_24xx_protect_flash(ql_adapter_state_t *); 2132 void ql_free_dma_resource(ql_adapter_state_t *, dma_mem_t *); 2133 uint8_t ql_pci_config_get8(ql_adapter_state_t *, off_t); 2134 void ql_pci_config_put32(ql_adapter_state_t *, off_t, uint32_t); 2135 int ql_24xx_unprotect_flash(ql_adapter_state_t *); 2136 char *els_cmd_text(int); 2137 char *mbx_cmd_text(int); 2138 char *cmd_text(cmd_table_t *, int); 2139 uint32_t ql_fwmodule_resolve(ql_adapter_state_t *); 2140 void ql_port_state(ql_adapter_state_t *, uint32_t, uint32_t); 2141 void ql_isp_els_handle_cmd_endian(ql_adapter_state_t *ha, ql_srb_t *srb); 2142 void ql_isp_els_handle_rsp_endian(ql_adapter_state_t *ha, ql_srb_t *srb); 2143 void ql_isp_els_handle_endian(ql_adapter_state_t *ha, uint8_t *ptr, 2144 uint8_t ls_code); 2145 int ql_el_trace_desc_ctor(ql_adapter_state_t *ha); 2146 int ql_el_trace_desc_dtor(ql_adapter_state_t *ha); 2147 int ql_wwn_cmp(ql_adapter_state_t *, la_wwn_t *, la_wwn_t *); 2148 void ql_dev_free(ql_adapter_state_t *, ql_tgt_t *); 2149 2150 #ifdef __cplusplus 2151 } 2152 #endif 2153 2154 #endif /* _QL_API_H */ 2155