1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Header file defining the HW IO elements 29 */ 30 31 #ifndef _OCE_IO_H_ 32 #define _OCE_IO_H_ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 #include <sys/dditypes.h> 40 #include <sys/mutex.h> 41 #include <sys/stream.h> 42 #include <sys/debug.h> 43 #include <sys/byteorder.h> 44 #include <oce_hw.h> 45 #include <oce_buf.h> 46 47 #define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000) /* 5 sec (in usec) */ 48 #define DEFAULT_DRAIN_TIME 200 /* Default Drain Time */ 49 #define MBX_TIMEOUT_SEC 5 50 #define STAT_TIMEOUT 2000000 /* update stats every 2 sec */ 51 52 struct oce_dev; 53 54 enum eq_len { 55 EQ_LEN_256 = 256, 56 EQ_LEN_512 = 512, 57 EQ_LEN_1024 = 1024, 58 EQ_LEN_2048 = 2048, 59 EQ_LEN_4096 = 4096 60 }; 61 62 enum eqe_size { 63 EQE_SIZE_4 = 4, 64 EQE_SIZE_16 = 16 65 }; 66 67 enum qtype { 68 QTYPE_EQ, 69 QTYPE_MQ, 70 QTYPE_WQ, 71 QTYPE_RQ, 72 QTYPE_CQ, 73 QTYPE_RSS 74 }; 75 76 typedef enum qstate_e { 77 QDELETED = 0x0, 78 QCREATED = 0x1 79 }qstate_t; 80 81 struct eq_config { 82 /* number of entries in the eq */ 83 enum eq_len q_len; 84 /* size of each entry */ 85 enum eqe_size item_size; 86 /* vector associated with this eq */ 87 uint32_t q_vector_num; 88 /* minimum possible eq delay i usec */ 89 uint8_t min_eqd; 90 /* max eq delay in usec */ 91 uint8_t max_eqd; 92 /* currently configured eq delay in usec */ 93 uint8_t cur_eqd; 94 /* pad */ 95 uint8_t pad; 96 }; 97 98 struct oce_eq { 99 /* configuration of this eq */ 100 struct eq_config eq_cfg; 101 /* id assigned by the hw to this eq */ 102 uint32_t eq_id; 103 /* handle to the creating parent dev */ 104 void *parent; 105 /* callback context */ 106 void *cb_context; 107 /* reference count of this structure */ 108 uint32_t ref_count; 109 /* ring buffer for this eq */ 110 oce_ring_buffer_t *ring; 111 /* Queue state */ 112 qstate_t qstate; 113 /* Lock for this queue */ 114 kmutex_t lock; 115 }; 116 117 enum cq_len { 118 CQ_LEN_256 = 256, 119 CQ_LEN_512 = 512, 120 CQ_LEN_1024 = 1024 121 }; 122 123 struct cq_config { 124 /* length of queue */ 125 enum cq_len q_len; 126 /* size of each item */ 127 uint32_t item_size; 128 /* is eventable */ 129 boolean_t is_eventable; 130 /* solicited eventable? */ 131 boolean_t sol_eventable; 132 /* no delay? */ 133 boolean_t nodelay; 134 /* dma coalescing */ 135 uint16_t dma_coalescing; 136 }; 137 138 typedef uint16_t (*cq_handler_t)(void *arg1); 139 140 struct oce_cq { 141 /* configuration of this cq */ 142 struct cq_config cq_cfg; 143 /* reference count of this structure */ 144 uint32_t ref_count; 145 /* id given by the hardware */ 146 uint32_t cq_id; 147 /* parent device to which this cq belongs */ 148 void *parent; 149 /* event queue associated with this cq */ 150 struct oce_eq *eq; 151 cq_handler_t cq_handler; 152 /* placeholder for callback context */ 153 void *cb_arg; 154 /* ring buffer for this cq */ 155 oce_ring_buffer_t *ring; 156 /* Queue state */ 157 qstate_t qstate; 158 /* lock */ 159 kmutex_t lock; 160 }; 161 162 struct mq_config { 163 uint32_t eqd; 164 uint8_t q_len; 165 uint8_t pad[3]; 166 167 }; 168 169 struct oce_mq { 170 /* configuration of this mq */ 171 struct mq_config cfg; 172 /* handle to the parent device */ 173 void *parent; 174 /* send queue */ 175 oce_ring_buffer_t *ring; 176 /* idnetifier for the mq */ 177 uint32_t mq_id; 178 struct oce_cq *cq; 179 struct oce_cq *async_cq; 180 /* free entries in Queue */ 181 uint32_t mq_free; 182 /* Queue state */ 183 qstate_t qstate; 184 /* lock for the mq */ 185 kmutex_t lock; 186 }; 187 188 189 /* 190 * utility structure that handles context of mbx 191 */ 192 struct oce_mbx_ctx { 193 /* pointer to mbx */ 194 struct oce_mbx *mbx; 195 /* call back functioin [optional] */ 196 void (*cb)(void *ctx); 197 /* call back context [optional] */ 198 void *cb_ctx; 199 }; 200 201 struct wq_config { 202 /* qtype */ 203 uint8_t wq_type; 204 uint8_t pad[3]; 205 uint32_t q_len; /* number of wqes */ 206 uint16_t pd_id; /* protection domain id */ 207 uint16_t pci_fn_num; /* pci function number */ 208 uint32_t eqd; /* interrupt delay */ 209 uint32_t nbufs; /* copy buffers */ 210 uint32_t nhdl; /* preallocated memory handles */ 211 }; 212 213 struct oce_wq { 214 struct wq_config cfg; /* q config */ 215 void *parent; /* parent of this wq */ 216 uint16_t wq_id; /* wq ID */ 217 oce_ring_buffer_t *ring; /* ring buffer managing the wqes */ 218 struct oce_cq *cq; /* cq associated with this wq */ 219 kmem_cache_t *wqed_cache; /* packet desc cache */ 220 OCE_LIST_T wqe_desc_list; /* packet descriptor list */ 221 oce_wq_bdesc_t *wq_bdesc_array; /* buffer desc array */ 222 OCE_LIST_T wq_buf_list; /* buffer list */ 223 OCE_LIST_T wq_mdesc_list; /* free list of memory handles */ 224 oce_wq_mdesc_t *wq_mdesc_array; /* preallocated memory handles */ 225 uint32_t wqm_used; /* memory handles uses */ 226 boolean_t resched; /* used for mac_tx_update */ 227 uint32_t wq_free; /* Wqe free */ 228 uint32_t tx_deferd; /* Wqe free */ 229 uint32_t pkt_drops; /* drops */ 230 /* Queue state */ 231 qstate_t qstate; 232 kmutex_t tx_lock; /* lock for the WQ */ 233 kmutex_t txc_lock; /* tx compl lock */ 234 kmutex_t resched_lock; /* tx compl lock */ 235 }; 236 237 struct rq_config { 238 uint32_t q_len; /* q length */ 239 uint32_t frag_size; /* fragment size. Send log2(size) in commmand */ 240 uint32_t mtu; /* max frame size for this RQ */ 241 uint32_t if_id; /* interface ID to associate this RQ with */ 242 uint32_t is_rss_queue; /* is this RQ an RSS queue? */ 243 uint32_t eqd; /* interrupt delay */ 244 uint32_t nbufs; /* Total data buffers */ 245 }; 246 247 struct rq_shadow_entry { 248 oce_rq_bdesc_t *rqbd; 249 }; 250 251 struct oce_rq { 252 /* RQ config */ 253 struct rq_config cfg; 254 /* RQ id */ 255 uint32_t rq_id; 256 /* parent of this rq */ 257 void *parent; 258 /* CPU ID assigend to this RQ if it is an RSS queue */ 259 uint32_t rss_cpuid; 260 /* ring buffer managing the RQEs */ 261 oce_ring_buffer_t *ring; 262 /* RQ Buffer cache */ 263 /* kmem_cache_t *rqb_cache; */ 264 /* shadow list of mblk for rq ring */ 265 struct rq_shadow_entry *shadow_ring; 266 /* cq associated with this queue */ 267 struct oce_cq *cq; 268 oce_rq_bdesc_t *rq_bdesc_array; 269 OCE_LIST_T rq_buf_list; /* Free list */ 270 uint32_t buf_avail; /* buffer avaialable with hw */ 271 uint32_t pending; /* Buffers sent up */ 272 /* Queue state */ 273 qstate_t qstate; 274 /* rq lock */ 275 kmutex_t rx_lock; 276 kmutex_t rc_lock; 277 }; 278 279 struct link_status { 280 /* dw 0 */ 281 uint8_t physical_port; 282 uint8_t mac_duplex; 283 uint8_t mac_speed; 284 uint8_t mac_fault; 285 /* dw 1 */ 286 uint8_t mgmt_mac_duplex; 287 uint8_t mgmt_mac_speed; 288 uint16_t rsvd0; 289 }; 290 291 oce_dma_buf_t *oce_alloc_dma_buffer(struct oce_dev *dev, 292 uint32_t size, uint32_t flags); 293 void oce_free_dma_buffer(struct oce_dev *dev, oce_dma_buf_t *dbuf); 294 295 oce_ring_buffer_t *create_ring_buffer(struct oce_dev *dev, 296 uint32_t num_items, uint32_t item_size, 297 uint32_t flags); 298 void destroy_ring_buffer(struct oce_dev *dev, oce_ring_buffer_t *ring); 299 300 /* Queues */ 301 int oce_set_eq_delay(struct oce_dev *dev, uint32_t *eq_arr, 302 uint32_t eq_cnt, uint32_t eq_delay); 303 void oce_arm_eq(struct oce_dev *dev, int16_t qid, int npopped, 304 boolean_t rearm, boolean_t clearint); 305 void oce_arm_cq(struct oce_dev *dev, int16_t qid, int npopped, 306 boolean_t rearm); 307 void oce_drain_eq(struct oce_eq *eq); 308 309 310 /* Bootstrap */ 311 int oce_mbox_init(struct oce_dev *dev); 312 int oce_mbox_fini(struct oce_dev *dev); 313 int oce_mbox_dispatch(struct oce_dev *dev, uint32_t tmo_sec); 314 int oce_mbox_wait(struct oce_dev *dev, uint32_t tmo_sec); 315 int oce_mbox_post(struct oce_dev *dev, struct oce_mbx *mbx, 316 struct oce_mbx_ctx *mbxctx); 317 318 /* Hardware */ 319 boolean_t oce_is_reset_pci(struct oce_dev *dev); 320 int oce_pci_soft_reset(struct oce_dev *dev); 321 int oce_POST(struct oce_dev *dev); 322 int oce_pci_init(struct oce_dev *dev); 323 void oce_pci_fini(struct oce_dev *dev); 324 int oce_init_txrx(struct oce_dev *dev); 325 void oce_fini_txrx(struct oce_dev *dev); 326 int oce_create_queues(struct oce_dev *dev); 327 void oce_delete_queues(struct oce_dev *dev); 328 void oce_delete_nw_interface(struct oce_dev *dev); 329 int oce_create_nw_interface(struct oce_dev *dev); 330 int oce_reset_fun(struct oce_dev *dev); 331 332 /* Transmit */ 333 struct oce_wq *oce_get_wq(struct oce_dev *dev, mblk_t *pkt); 334 uint16_t oce_drain_wq_cq(void *arg); 335 mblk_t *oce_send_packet(struct oce_wq *wq, mblk_t *mp); 336 int oce_start_wq(struct oce_wq *wq); 337 void oce_clean_wq(struct oce_wq *wq); 338 339 340 /* Recieve */ 341 uint16_t oce_drain_rq_cq(void *arg); 342 int oce_start_rq(struct oce_rq *rq); 343 void oce_clean_rq(struct oce_rq *rq); 344 void oce_rq_discharge(struct oce_rq *rq); 345 int oce_rx_pending(struct oce_dev *dev); 346 347 /* event handling */ 348 uint16_t oce_drain_mq_cq(void *arg); 349 int oce_mq_mbox_post(struct oce_dev *dev, struct oce_mbx *mbx, 350 struct oce_mbx_ctx *mbxctx); 351 struct oce_mbx *oce_mq_get_mbx(struct oce_dev *dev); 352 void oce_clean_mq(struct oce_mq *mq); 353 int oce_start_mq(struct oce_mq *mq); 354 355 356 /* mbx functions */ 357 void mbx_common_req_hdr_init(struct mbx_hdr *hdr, uint8_t dom, 358 uint8_t port, uint8_t subsys, uint8_t opcode, 359 uint32_t timeout, uint32_t pyld_len); 360 void mbx_nic_req_hdr_init(struct mbx_hdr *hdr, uint8_t dom, uint8_t port, 361 uint8_t opcode, uint32_t timeout, uint32_t pyld_len); 362 int oce_get_fw_version(struct oce_dev *dev); 363 int oce_read_mac_addr(struct oce_dev *dev, uint32_t if_id, uint8_t perm, 364 uint8_t type, struct mac_address_format *mac); 365 int oce_if_create(struct oce_dev *dev, uint32_t cap_flags, uint32_t en_flags, 366 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id); 367 int oce_if_del(struct oce_dev *dev, uint32_t if_id); 368 int oce_num_intr_vectors_set(struct oce_dev *dev, uint32_t num_vectors); 369 370 int oce_get_link_status(struct oce_dev *dev, struct link_status *link); 371 int oce_set_rx_filter(struct oce_dev *dev, 372 struct mbx_set_common_ntwk_rx_filter *filter); 373 int oce_set_multicast_table(struct oce_dev *dev, uint32_t if_id, 374 struct ether_addr *mca_table, uint16_t mca_cnt, boolean_t promisc); 375 int oce_get_fw_config(struct oce_dev *dev); 376 int oce_get_hw_stats(struct oce_dev *dev); 377 int oce_set_flow_control(struct oce_dev *dev, uint32_t flow_control); 378 int oce_get_flow_control(struct oce_dev *dev, uint32_t *flow_control); 379 int oce_set_promiscuous(struct oce_dev *dev, boolean_t enable); 380 int oce_add_mac(struct oce_dev *dev, uint32_t if_id, 381 const uint8_t *mac, uint32_t *pmac_id); 382 int oce_del_mac(struct oce_dev *dev, uint32_t if_id, uint32_t *pmac_id); 383 int oce_config_vlan(struct oce_dev *dev, uint32_t if_id, 384 struct normal_vlan *vtag_arr, 385 uint8_t vtag_cnt, boolean_t untagged, 386 boolean_t enable_promisc); 387 int oce_config_link(struct oce_dev *dev, boolean_t enable); 388 389 int oce_issue_mbox(struct oce_dev *dev, queue_t *wq, mblk_t *mp, 390 uint32_t *payload_length); 391 392 #ifdef __cplusplus 393 } 394 #endif 395 396 #endif /* _OCE_IO_H_ */ 397