1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Header file containing the command structures for Hardware 29 */ 30 31 #ifndef _OCE_HW_H_ 32 #define _OCE_HW_H_ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 40 #pragma pack(1) 41 42 /* PCI CSR offsets */ 43 #define PCICFG_F1_CSR 0x0 /* F1 for NIC */ 44 #define PCICFG_SEMAPHORE 0xbc 45 #define PCICFG_SOFT_RESET 0x5c 46 #define PCICFG_UE_STATUS_HI_MASK 0xac 47 #define PCICFG_UE_STATUS_LO_MASK 0xa8 48 #define PCICFG_ONLINE0 0xb0 49 #define PCICFG_ONLINE1 0xb4 50 #define INTR_EN 0x20000000 51 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 52 53 /* CSR register offsets */ 54 #define MPU_EP_CONTROL 0 55 #define MPU_EP_SEMAPHORE 0xac 56 #define PCICFG_INTR_CTRL 0xfc 57 #define HOSTINTR_MASK (1 << 29) 58 #define HOSTINTR_PFUNC_SHIFT 26 59 #define HOSTINTR_PFUNC_MASK 7 60 61 /* POST status reg struct */ 62 #define POST_STAGE_POWER_ON_RESET 0x00 63 #define POST_STAGE_AWAITING_HOST_RDY 0x01 64 #define POST_STAGE_HOST_RDY 0x02 65 #define POST_STAGE_CHIP_RESET 0x03 66 #define POST_STAGE_ARMFW_READY 0xc000 67 #define POST_STAGE_ARMFW_UE 0xf000 68 69 /* DOORBELL registers */ 70 #define PD_RXULP_DB 0x0100 71 #define PD_TXULP_DB 0x0060 72 #define DB_RQ_ID_MASK 0x3FF 73 74 #define PD_CQ_DB 0x0120 75 #define PD_EQ_DB PD_CQ_DB 76 #define PD_MPU_MBOX_DB 0x0160 77 #define PD_MQ_DB 0x0140 78 79 /* EQE completion types */ 80 #define EQ_MINOR_CODE_COMPLETION 0x00 81 #define EQ_MINOR_CODE_OTHER 0x01 82 #define EQ_MAJOR_CODE_COMPLETION 0x00 83 84 /* Link Status field values */ 85 #define PHY_LINK_FAULT_NONE 0x0 86 #define PHY_LINK_FAULT_LOCAL 0x01 87 #define PHY_LINK_FAULT_REMOTE 0x02 88 89 #define PHY_LINK_SPEED_ZERO 0x0 /* No link */ 90 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 91 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 92 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 93 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 94 95 #define PHY_LINK_DUPLEX_NONE 0x0 96 #define PHY_LINK_DUPLEX_HALF 0x1 97 #define PHY_LINK_DUPLEX_FULL 0x2 98 99 #define NTWK_PORT_A 0x0 /* (Port A) */ 100 #define NTWK_PORT_B 0x1 /* (Port B) */ 101 102 #define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */ 103 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 104 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 105 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 106 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 107 108 /* Hardware Address types */ 109 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */ 110 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */ 111 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */ 112 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */ 113 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */ 114 115 /* CREATE_IFACE capability and cap_en flags */ 116 #define MBX_RX_IFACE_FLAGS_RSS 0x4 117 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8 118 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10 119 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20 120 #define MBX_RX_IFACE_FLAGS_ULP 0x40 121 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80 122 #define MBX_RX_IFACE_FLAGS_VLAN 0x100 123 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200 124 #define MBX_RX_IFACE_FLAGS_PASS_L2 0x400 125 #define MBX_RX_IFACE_FLAGS_PASS_L3L4 0x800 126 127 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */ 128 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */ 129 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */ 130 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */ 131 132 133 #define MBX_DB_READY_BIT 0x1 134 #define MBX_DB_HI_BIT 0x2 135 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 136 #define ASYNC_EVENT_LINK_UP 0x1 137 #define ASYNC_EVENT_LINK_DOWN 0x0 138 139 /* Rx filter bits */ 140 #define NTWK_RX_FILTER_IP_CKSUM 0x1 141 #define NTWK_RX_FILTER_TCP_CKSUM 0x2 142 #define NTWK_RX_FILTER_UDP_CKSUM 0x4 143 #define NTWK_RX_FILTER_STRIP_CRC 0x8 144 145 /* max SGE per mbx */ 146 #define MAX_MBX_SGE 19 147 148 /* physical address structure to be used in MBX */ 149 struct phys_addr { 150 /* dw0 */ 151 uint32_t lo; 152 /* dw1 */ 153 uint32_t hi; 154 }; 155 156 typedef union pcicfg_intr_ctl_u { 157 uint32_t dw0; 158 struct { 159 #ifdef _BIG_ENDIAN 160 uint32_t winselect:2; 161 uint32_t hostintr:1; 162 uint32_t pfnum:3; 163 uint32_t vf_cev_int_line_en:1; 164 uint32_t winaddr:23; 165 uint32_t membarwinen:1; 166 #else 167 uint32_t membarwinen:1; 168 uint32_t winaddr:23; 169 uint32_t vf_cev_int_line_en:1; 170 uint32_t pfnum:3; 171 uint32_t hostintr:1; 172 uint32_t winselect:2; 173 #endif 174 } bits; 175 }pcicfg_intr_ctl_t; 176 177 typedef union pcicfg_semaphore_u { 178 uint32_t dw0; 179 struct { 180 #ifdef _BIG_ENDIAN 181 uint32_t rsvd:31; 182 uint32_t lock:1; 183 #else 184 uint32_t lock:1; 185 uint32_t rsvd:31; 186 #endif 187 }bits; 188 }pcicfg_semaphore_t; 189 190 typedef union pcicfg_soft_reset_u { 191 uint32_t dw0; 192 struct { 193 #ifdef _BIG_ENDIAN 194 uint32_t nec_ll_rcvdetect:8; 195 uint32_t dbg_all_reqs_62_49:14; 196 uint32_t scratchpad0:1; 197 uint32_t exception_oe:1; 198 uint32_t soft_reset:1; 199 uint32_t rsvd0:7; 200 #else 201 uint32_t rsvd0:7; 202 uint32_t soft_reset:1; 203 uint32_t exception_oe:1; 204 uint32_t scratchpad0:1; 205 uint32_t dbg_all_reqs_62_49:14; 206 uint32_t nec_ll_rcvdetect:8; 207 #endif 208 }bits; 209 }pcicfg_soft_reset_t; 210 211 typedef union pcicfg_online1_u { 212 uint32_t dw0; 213 struct { 214 #ifdef _BIG_ENDIAN 215 uint32_t host8_online:1; 216 uint32_t host7_online:1; 217 uint32_t host6_online:1; 218 uint32_t host5_online:1; 219 uint32_t host4_online:1; 220 uint32_t host3_online:1; 221 uint32_t host2_online:1; 222 uint32_t ipc_online:1; 223 uint32_t arm_online:1; 224 uint32_t txp_online:1; 225 uint32_t xaui_online:1; 226 uint32_t rxpp_online:1; 227 uint32_t txpb_online:1; 228 uint32_t rr_online:1; 229 uint32_t pmem_online:1; 230 uint32_t pctl1_online:1; 231 uint32_t pctl0_online:1; 232 uint32_t pcs1online_online:1; 233 uint32_t mpu_iram_online:1; 234 uint32_t pcs0online_online:1; 235 uint32_t mgmt_mac_online:1; 236 uint32_t lpcmemhost_online:1; 237 #else 238 uint32_t lpcmemhost_online:1; 239 uint32_t mgmt_mac_online:1; 240 uint32_t pcs0online_online:1; 241 uint32_t mpu_iram_online:1; 242 uint32_t pcs1online_online:1; 243 uint32_t pctl0_online:1; 244 uint32_t pctl1_online:1; 245 uint32_t pmem_online:1; 246 uint32_t rr_online:1; 247 uint32_t txpb_online:1; 248 uint32_t rxpp_online:1; 249 uint32_t xaui_online:1; 250 uint32_t txp_online:1; 251 uint32_t arm_online:1; 252 uint32_t ipc_online:1; 253 uint32_t host2_online:1; 254 uint32_t host3_online:1; 255 uint32_t host4_online:1; 256 uint32_t host5_online:1; 257 uint32_t host6_online:1; 258 uint32_t host7_online:1; 259 uint32_t host8_online:1; 260 #endif 261 }bits; 262 }pcicfg_online1_t; 263 264 typedef union mpu_ep_semaphore_u { 265 uint32_t dw0; 266 struct { 267 #ifdef _BIG_ENDIAN 268 uint32_t error:1; 269 uint32_t backup_fw:1; 270 uint32_t iscsi_no_ip:1; 271 uint32_t iscsi_ip_conflict:1; 272 uint32_t option_rom_installed:1; 273 uint32_t iscsi_drv_loaded:1; 274 uint32_t rsvd0:10; 275 uint32_t stage:16; 276 #else 277 uint32_t stage:16; 278 uint32_t rsvd0:10; 279 uint32_t iscsi_drv_loaded:1; 280 uint32_t option_rom_installed:1; 281 uint32_t iscsi_ip_conflict:1; 282 uint32_t iscsi_no_ip:1; 283 uint32_t backup_fw:1; 284 uint32_t error:1; 285 #endif 286 }bits; 287 }mpu_ep_semaphore_t; 288 289 typedef union mpu_ep_control_u { 290 uint32_t dw0; 291 struct { 292 #ifdef _BIG_ENDIAN 293 uint32_t cpu_reset:1; 294 uint32_t rsvd1:15; 295 uint32_t ep_ram_init_status:1; 296 uint32_t rsvd0:12; 297 uint32_t m2_rxpbuf:1; 298 uint32_t m1_rxpbuf:1; 299 uint32_t m0_rxpbuf:1; 300 #else 301 uint32_t m0_rxpbuf:1; 302 uint32_t m1_rxpbuf:1; 303 uint32_t m2_rxpbuf:1; 304 uint32_t rsvd0:12; 305 uint32_t ep_ram_init_status:1; 306 uint32_t rsvd1:15; 307 uint32_t cpu_reset:1; 308 #endif 309 }bits; 310 }mpu_ep_control_t; 311 312 /* RX doorbell */ 313 typedef union pd_rxulp_db_u { 314 uint32_t dw0; 315 struct { 316 #ifdef _BIG_ENDIAN 317 uint32_t num_posted:8; 318 uint32_t invalidate:1; 319 uint32_t rsvd1:13; 320 uint32_t qid:10; 321 #else 322 uint32_t qid:10; 323 uint32_t rsvd1:13; 324 uint32_t invalidate:1; 325 uint32_t num_posted:8; 326 #endif 327 }bits; 328 }pd_rxulp_db_t; 329 330 /* TX doorbell */ 331 typedef union pd_txulp_db_u { 332 uint32_t dw0; 333 struct { 334 #ifdef _BIG_ENDIAN 335 uint32_t rsvd1:2; 336 uint32_t num_posted:14; 337 uint32_t rsvd0:6; 338 uint32_t qid:10; 339 #else 340 uint32_t qid:10; 341 uint32_t rsvd0:6; 342 uint32_t num_posted:14; 343 uint32_t rsvd1:2; 344 #endif 345 }bits; 346 }pd_txulp_db_t; 347 348 /* CQ doorbell */ 349 typedef union cq_db_u { 350 uint32_t dw0; 351 struct { 352 #ifdef _BIG_ENDIAN 353 uint32_t rsvd1:2; 354 uint32_t rearm:1; 355 uint32_t num_popped:13; 356 uint32_t rsvd0:5; 357 uint32_t event:1; 358 uint32_t qid:10; 359 #else 360 uint32_t qid:10; 361 uint32_t event:1; 362 uint32_t rsvd0:5; 363 uint32_t num_popped:13; 364 uint32_t rearm:1; 365 uint32_t rsvd1:2; 366 #endif 367 }bits; 368 }cq_db_t; 369 370 /* EQ doorbell */ 371 typedef union eq_db_u { 372 uint32_t dw0; 373 struct { 374 #ifdef _BIG_ENDIAN 375 uint32_t rsvd1:2; 376 uint32_t rearm:1; 377 uint32_t num_popped:13; 378 uint32_t rsvd0:5; 379 uint32_t event:1; 380 uint32_t clrint:1; 381 uint32_t qid:9; 382 #else 383 uint32_t qid:9; 384 uint32_t clrint:1; 385 uint32_t event:1; 386 uint32_t rsvd0:5; 387 uint32_t num_popped:13; 388 uint32_t rearm:1; 389 uint32_t rsvd1:2; 390 #endif 391 }bits; 392 }eq_db_t; 393 394 /* bootstrap mbox doorbell */ 395 typedef union pd_mpu_mbox_db_u { 396 uint32_t dw0; 397 struct { 398 #ifdef _BIG_ENDIAN 399 uint32_t address:30; 400 uint32_t hi:1; 401 uint32_t ready:1; 402 #else 403 uint32_t ready:1; 404 uint32_t hi:1; 405 uint32_t address:30; 406 #endif 407 }bits; 408 }pd_mpu_mbox_db_t; 409 410 411 /* MQ ring doorbell */ 412 typedef union pd_mq_db_u { 413 uint32_t dw0; 414 struct { 415 #ifdef _BIG_ENDIAN 416 uint32_t rsvd1:2; 417 uint32_t num_posted:14; 418 uint32_t rsvd0:5; 419 uint32_t mq_id:11; 420 #else 421 uint32_t mq_id:11; 422 uint32_t rsvd0:5; 423 uint32_t num_posted:14; 424 uint32_t rsvd1:2; 425 #endif 426 }bits; 427 }pd_mq_db_t; 428 429 /* 430 * Event Queue Entry 431 */ 432 struct oce_eqe { 433 union { 434 struct { 435 #ifdef _BIG_ENDIAN 436 uint32_t resource_id:16; 437 uint32_t minor_code:12; 438 uint32_t major_code:3; 439 uint32_t valid:1; 440 #else 441 uint32_t valid:1; 442 uint32_t major_code:3; 443 uint32_t minor_code:12; 444 uint32_t resource_id:16; 445 #endif 446 }s; 447 uint32_t dw0; 448 }u0; 449 }; 450 451 /* MQ scatter gather entry. Array of these make an SGL */ 452 struct oce_mq_sge { 453 uint32_t pa_lo; 454 uint32_t pa_hi; 455 uint32_t length; 456 }; 457 458 /* 459 * payload can contain an SGL or an embedded array of upto 59 dwords 460 */ 461 struct oce_mbx_payload { 462 union { 463 union { 464 struct oce_mq_sge sgl[MAX_MBX_SGE]; 465 uint32_t embedded[59]; 466 }u1; 467 uint32_t dw[59]; 468 }u0; 469 }; 470 471 /* 472 * MQ MBX structure 473 */ 474 struct oce_mbx { 475 union { 476 struct { 477 #ifdef _BIG_ENDIAN 478 uint32_t special : 8; 479 uint32_t rsvd1 : 16; 480 uint32_t sge_count : 5; 481 uint32_t rsvd0 : 2; 482 uint32_t embedded : 1; 483 #else 484 uint32_t embedded:1; 485 uint32_t rsvd0:2; 486 uint32_t sge_count:5; 487 uint32_t rsvd1:16; 488 uint32_t special:8; 489 #endif 490 }s; 491 uint32_t dw0; 492 }u0; 493 494 uint32_t payload_length; 495 uint32_t tag[2]; 496 uint32_t rsvd2[1]; 497 struct oce_mbx_payload payload; 498 }; 499 500 /* completion queue entry for MQ */ 501 struct oce_mq_cqe { 502 union { 503 struct { 504 #ifdef _BIG_ENDIAN 505 /* dw0 */ 506 uint32_t extended_status:16; 507 uint32_t completion_status:16; 508 /* dw1 dw2 */ 509 uint32_t mq_tag[2]; 510 /* dw3 */ 511 uint32_t valid:1; 512 uint32_t async_event:1; 513 uint32_t hpi_buffer_cmpl:1; 514 uint32_t completed:1; 515 uint32_t consumed:1; 516 uint32_t rsvd0:27; 517 #else 518 /* dw0 */ 519 uint32_t completion_status:16; 520 uint32_t extended_status:16; 521 /* dw1 dw2 */ 522 uint32_t mq_tag[2]; 523 /* dw3 */ 524 uint32_t rsvd0:27; 525 uint32_t consumed:1; 526 uint32_t completed:1; 527 uint32_t hpi_buffer_cmpl:1; 528 uint32_t async_event:1; 529 uint32_t valid:1; 530 #endif 531 }s; 532 uint32_t dw[4]; 533 }u0; 534 }; 535 536 struct oce_async_cqe_link_state { 537 union { 538 struct { 539 #ifdef _BIG_ENDIAN 540 /* dw0 */ 541 uint8_t speed; 542 uint8_t duplex; 543 uint8_t link_status; 544 uint8_t phy_port; 545 /* dw1 */ 546 uint8_t rsvd0[3]; 547 uint8_t fault; 548 /* dw2 */ 549 uint32_t event_tag; 550 /* dw3 */ 551 uint32_t valid:1; 552 uint32_t async_event:1; 553 uint32_t rsvd2:6; 554 uint32_t event_type:8; 555 uint32_t event_code:8; 556 uint32_t rsvd1:8; 557 #else 558 /* dw0 */ 559 uint8_t phy_port; 560 uint8_t link_status; 561 uint8_t duplex; 562 uint8_t speed; 563 /* dw1 */ 564 uint8_t fault; 565 uint8_t rsvd0[3]; 566 /* dw2 */ 567 uint32_t event_tag; 568 /* dw3 */ 569 uint32_t rsvd1:8; 570 uint32_t event_code:8; 571 uint32_t event_type:8; 572 uint32_t rsvd2:6; 573 uint32_t async_event:1; 574 uint32_t valid:1; 575 #endif 576 }s; 577 uint32_t dw[4]; 578 }u0; 579 }; 580 581 /* MQ mailbox structure */ 582 struct oce_bmbx { 583 struct oce_mbx mbx; 584 struct oce_mq_cqe cqe; 585 }; 586 587 /* ---[ MBXs start here ]---------------------------------------------- */ 588 /* MBXs sub system codes */ 589 enum { 590 MBX_SUBSYSTEM_RSVD = 0, 591 MBX_SUBSYSTEM_COMMON = 1, 592 MBX_SUBSYSTEM_COMMON_ISCSI = 2, 593 MBX_SUBSYSTEM_NIC = 3, 594 MBX_SUBSYSTEM_TOE = 4, 595 MBX_SUBSYSTEM_PXE_UNDI = 5, 596 MBX_SUBSYSTEM_ISCSI_INI = 6, 597 MBX_SUBSYSTEM_ISCSI_TGT = 7, 598 MBX_SUBSYSTEM_MILI_PTL = 8, 599 MBX_SUBSYSTEM_MILI_TMD = 9, 600 MBX_SUBSYSTEM_RDMA = 10, 601 MBX_SUBSYSTEM_LOWLEVEL = 11, 602 MBX_SUBSYSTEM_LRO = 13, 603 IOCBMBX_SUBSYSTEM_DCBX = 15, 604 IOCBMBX_SUBSYSTEM_DIAG = 16, 605 IOCBMBX_SUBSYSTEM_VENDOR = 17 606 }; 607 608 /* common ioctl opcodes */ 609 enum { 610 OPCODE_QUERY_COMMON_IFACE_MAC = 1, 611 OPCODE_SET_COMMON_IFACE_MAC = 2, 612 OPCODE_SET_COMMON_IFACE_MULTICAST = 3, 613 OPCODE_CONFIG_COMMON_IFACE_VLAN = 4, 614 OPCODE_QUERY_COMMON_LINK_STATUS = 5, 615 OPCODE_READ_COMMON_FLASHROM = 6, 616 OPCODE_WRITE_COMMON_FLASHROM = 7, 617 OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE = 8, 618 OPCODE_ADD_COMMON_PAGE_TABLES = 9, 619 OPCODE_REMOVE_COMMON_PAGE_TABLES = 10, 620 OPCODE_CREATE_COMMON_CQ = 12, 621 OPCODE_CREATE_COMMON_EQ = 13, 622 OPCODE_CREATE_COMMON_MQ = 21, 623 OPCODE_COMMON_JELL_CONFIG = 22, 624 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS = 24, 625 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS = 25, 626 OPCODE_COMMON_POST_ZERO_BUFFER = 26, 627 OPCODE_COMMON_GET_QOS = 27, 628 OPCODE_COMMON_SET_QOS = 28, 629 OPCODE_COMMON_TCP_GET_STATISTICS = 29, 630 OPCODE_READ_COMMON_SEEPROM = 30, 631 OPCODE_COMMON_TCP_STATE_QUERY = 31, 632 OPCODE_GET_COMMON_CNTL_ATTRIBUTES = 32, 633 OPCODE_COMMON_NOP = 33, 634 OPCODE_COMMON_NTWK_RX_FILTER = 34, 635 OPCODE_GET_COMMON_FW_VERSION = 35, 636 OPCODE_SET_COMMON_FLOW_CONTROL = 36, 637 OPCODE_GET_COMMON_FLOW_CONTROL = 37, 638 OPCODE_COMMON_SET_TCP_PARAMETERS = 38, 639 OPCODE_SET_COMMON_FRAME_SIZE = 39, 640 OPCODE_COMMON_GET_FAT = 40, 641 OPCODE_MODIFY_COMMON_EQ_DELAY = 41, 642 OPCODE_COMMON_FIRMWARE_CONFIG = 42, 643 OPCODE_COMMON_ENABLE_DISABLE_DOMAINS = 43, 644 OPCODE_COMMON_GET_DOMAIN_CONFIG = 44, 645 OPCODE_COMMON_GET_PORT_EQUALIZATION = 47, 646 OPCODE_COMMON_SET_PORT_EQUALIZATION = 48, 647 OPCODE_COMMON_RED_CONFIG = 49, 648 OPCODE_CREATE_COMMON_IFACE = 50, 649 OPCODE_DESTROY_COMMON_IFACE = 51, 650 OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES = 52, 651 OPCODE_DESTROY_COMMON_MQ = 53, 652 OPCODE_DESTROY_COMMON_CQ = 54, 653 OPCODE_DESTROY_COMMON_EQ = 55, 654 OPCODE_COMMON_TCP_UPL_OAD = 56, 655 OPCODE_SET_COMMON_LINK_SPEED = 57, 656 OPCODE_QUERY_COMMON_FIRMWARE_CONFIG = 58, 657 OPCODE_ADD_COMMON_IFACE_MAC = 59, 658 OPCODE_DEL_COMMON_IFACE_MAC = 60, 659 OPCODE_COMMON_FUNCTION_RESET = 61, 660 OPCODE_COMMON_FUNCTION_LINK_CONFIG = 80 661 }; 662 663 /* common ioctl header */ 664 struct mbx_hdr { 665 union { 666 struct { 667 #ifdef _BIG_ENDIAN 668 uint8_t domain; 669 uint8_t port_number; 670 uint8_t subsystem; 671 uint8_t opcode; 672 #else 673 uint8_t opcode; 674 uint8_t subsystem; 675 uint8_t port_number; 676 uint8_t domain; 677 #endif 678 uint32_t timeout; 679 uint32_t request_length; 680 uint32_t rsvd0; 681 }req; 682 683 struct { 684 /* dw 0 */ 685 uint8_t opcode; 686 uint8_t subsystem; 687 uint8_t rsvd0; 688 uint8_t domain; 689 /* dw 1 */ 690 uint8_t status; 691 uint8_t additional_status; 692 uint16_t rsvd1; 693 694 uint32_t rsp_length; 695 uint32_t actual_rsp_length; 696 }rsp; 697 uint32_t dw[4]; 698 }u0; 699 }; 700 #define OCE_BMBX_RHDR_SZ 20 701 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr) 702 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status) 703 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status) 704 705 /* [05] OPCODE_QUERY_COMMON_LINK_STATUS */ 706 struct mbx_query_common_link_status { 707 struct mbx_hdr hdr; 708 union { 709 struct { 710 uint32_t rsvd0; 711 }req; 712 713 struct { 714 /* dw 0 */ 715 uint8_t physical_port; 716 uint8_t mac_duplex; 717 uint8_t mac_speed; 718 uint8_t mac_fault; 719 /* dw 1 */ 720 uint8_t mgmt_mac_duplex; 721 uint8_t mgmt_mac_speed; 722 uint16_t rsvd0; 723 }rsp; 724 }params; 725 }; 726 727 /* [57] OPCODE_SET_COMMON_LINK_SPEED */ 728 struct mbx_set_common_link_speed { 729 struct mbx_hdr hdr; 730 union { 731 struct { 732 #ifdef _BIG_ENDIAN 733 uint8_t rsvd0; 734 uint8_t mac_speed; 735 uint8_t virtual_port; 736 uint8_t physical_port; 737 #else 738 uint8_t physical_port; 739 uint8_t virtual_port; 740 uint8_t mac_speed; 741 uint8_t rsvd0; 742 #endif 743 }req; 744 745 struct { 746 uint32_t rsvd0; 747 }rsp; 748 749 uint32_t dw; 750 }params; 751 }; 752 753 struct mac_address_format { 754 uint16_t size_of_struct; 755 uint8_t mac_addr[6]; 756 }; 757 758 /* [01] OPCODE_QUERY_COMMON_IFACE_MAC */ 759 struct mbx_query_common_iface_mac { 760 struct mbx_hdr hdr; 761 union { 762 struct { 763 #ifdef _BIG_ENDIAN 764 uint16_t if_id; 765 uint8_t permanent; 766 uint8_t type; 767 #else 768 uint8_t type; 769 uint8_t permanent; 770 uint16_t if_id; 771 #endif 772 773 }req; 774 775 struct { 776 struct mac_address_format mac; 777 }rsp; 778 }params; 779 }; 780 781 /* [02] OPCODE_SET_COMMON_IFACE_MAC */ 782 struct mbx_set_common_iface_mac { 783 struct mbx_hdr hdr; 784 union { 785 struct { 786 #ifdef _BIG_ENDIAN 787 /* dw 0 */ 788 uint16_t if_id; 789 uint8_t invalidate; 790 uint8_t type; 791 #else 792 /* dw 0 */ 793 uint8_t type; 794 uint8_t invalidate; 795 uint16_t if_id; 796 #endif 797 /* dw 1 */ 798 struct mac_address_format mac; 799 }req; 800 801 struct { 802 uint32_t rsvd0; 803 }rsp; 804 805 uint32_t dw[2]; 806 }params; 807 }; 808 809 /* [03] OPCODE_SET_COMMON_IFACE_MULTICAST */ 810 struct mbx_set_common_iface_multicast { 811 struct mbx_hdr hdr; 812 union { 813 struct { 814 #ifdef _BIG_ENDIAN 815 /* dw 0 */ 816 uint8_t if_id; 817 uint8_t promiscuous; 818 uint16_t num_mac; 819 #else 820 /* dw 0 */ 821 uint16_t num_mac; 822 uint8_t promiscuous; 823 uint8_t if_id; 824 #endif 825 /* dw 1-48 */ 826 struct { 827 uint8_t byte[6]; 828 } mac[32]; 829 830 }req; 831 832 struct { 833 uint32_t rsvd0; 834 }rsp; 835 836 uint32_t dw[49]; 837 }params; 838 }; 839 840 struct qinq_vlan { 841 #ifdef _BIG_ENDIAN 842 uint16_t inner; 843 uint16_t outer; 844 #else 845 uint16_t outer; 846 uint16_t inner; 847 #endif 848 }; 849 850 struct normal_vlan { 851 uint16_t vtag; 852 }; 853 854 struct ntwk_if_vlan_tag { 855 union { 856 struct normal_vlan normal; 857 struct qinq_vlan qinq; 858 }u0; 859 }; 860 861 /* [50] OPCODE_CREATE_COMMON_IFACE */ 862 struct mbx_create_common_iface { 863 struct mbx_hdr hdr; 864 union { 865 struct { 866 uint32_t version; 867 uint32_t cap_flags; 868 uint32_t enable_flags; 869 uint8_t mac_addr[6]; 870 uint8_t rsvd0; 871 uint8_t mac_invalid; 872 struct ntwk_if_vlan_tag vlan_tag; 873 }req; 874 875 struct { 876 uint32_t if_id; 877 uint32_t pmac_id; 878 }rsp; 879 uint32_t dw[4]; 880 }params; 881 }; 882 883 /* [51] OPCODE_DESTROY_COMMON_IFACE */ 884 struct mbx_destroy_common_iface { 885 struct mbx_hdr hdr; 886 union { 887 struct { 888 uint32_t if_id; 889 }req; 890 891 struct { 892 uint32_t rsvd0; 893 }rsp; 894 895 uint32_t dw; 896 }params; 897 }; 898 899 /* event queue context structure */ 900 struct oce_eq_ctx { 901 #ifdef _BIG_ENDIAN 902 /* dw0 */ 903 uint32_t size:1; 904 uint32_t rsvd1:1; 905 uint32_t valid:1; 906 uint32_t epidx:13; 907 uint32_t rsvd0:3; 908 uint32_t cidx:13; 909 910 /* dw1 */ 911 uint32_t armed:1; 912 uint32_t stalled:1; 913 uint32_t sol_event:1; 914 uint32_t count:3; 915 uint32_t pd:10; 916 uint32_t rsvd2:3; 917 uint32_t pidx:13; 918 919 /* dw2 */ 920 uint32_t rsvd6:4; 921 uint32_t nodelay:1; 922 uint32_t phase:2; 923 uint32_t rsvd5:2; 924 uint32_t delay_mult:10; 925 uint32_t rsvd4:1; 926 uint32_t function:8; 927 uint32_t rsvd3:4; 928 929 /* dw 3 */ 930 uint32_t rsvd7; 931 #else 932 /* dw0 */ 933 uint32_t cidx:13; 934 uint32_t rsvd0:3; 935 uint32_t epidx:13; 936 uint32_t valid:1; 937 uint32_t rsvd1:1; 938 uint32_t size:1; 939 940 /* dw1 */ 941 uint32_t pidx:13; 942 uint32_t rsvd2:3; 943 uint32_t pd:10; 944 uint32_t count:3; 945 uint32_t sol_event:1; 946 uint32_t stalled:1; 947 uint32_t armed:1; 948 949 /* dw2 */ 950 uint32_t rsvd3:4; 951 uint32_t function:8; 952 uint32_t rsvd4:1; 953 uint32_t delay_mult:10; 954 uint32_t rsvd5:2; 955 uint32_t phase:2; 956 uint32_t nodelay:1; 957 uint32_t rsvd6:4; 958 959 /* dw3 */ 960 uint32_t rsvd7; 961 #endif 962 }; 963 964 /* [13] OPCODE_CREATE_COMMON_EQ */ 965 struct mbx_create_common_eq { 966 struct mbx_hdr hdr; 967 union { 968 struct { 969 #ifdef _BIG_ENDIAN 970 uint16_t rsvd0; 971 uint16_t num_pages; 972 #else 973 uint16_t num_pages; 974 uint16_t rsvd0; 975 #endif 976 struct oce_eq_ctx eq_ctx; 977 struct phys_addr pages[8]; 978 }req; 979 980 struct { 981 uint16_t eq_id; 982 uint16_t rsvd0; 983 }rsp; 984 }params; 985 }; 986 987 /* [55] OPCODE_DESTROY_COMMON_EQ */ 988 struct mbx_destroy_common_eq { 989 struct mbx_hdr hdr; 990 union { 991 struct { 992 #ifdef _BIG_ENDIAN 993 uint16_t rsvd0; 994 uint16_t id; 995 #else 996 uint16_t id; 997 uint16_t rsvd0; 998 #endif 999 }req; 1000 1001 struct { 1002 uint32_t rsvd0; 1003 }rsp; 1004 }params; 1005 }; 1006 1007 struct oce_cq_ctx { 1008 #ifdef _BIG_ENDIAN 1009 /* dw0 */ 1010 uint32_t eventable:1; 1011 uint32_t sol_event:1; 1012 uint32_t valid:1; 1013 uint32_t count:2; 1014 uint32_t rsvd1:1; 1015 uint32_t epidx:11; 1016 uint32_t nodelay:1; 1017 uint32_t coalesce_wm:2; 1018 uint32_t rsvd0:1; 1019 uint32_t cidx:11; 1020 1021 /* dw1 */ 1022 uint32_t armed:1; 1023 uint32_t stalled:1; 1024 uint32_t eq_id:8; 1025 uint32_t pd:10; 1026 uint32_t rsvd2:1; 1027 uint32_t pidx:11; 1028 1029 /* dw2 */ 1030 uint32_t rsvd4:20; 1031 uint32_t function:8; 1032 uint32_t rsvd3:4; 1033 #else 1034 /* dw0 */ 1035 uint32_t cidx:11; 1036 uint32_t rsvd0:1; 1037 uint32_t coalesce_wm:2; 1038 uint32_t nodelay:1; 1039 uint32_t epidx:11; 1040 uint32_t rsvd1:1; 1041 uint32_t count:2; 1042 uint32_t valid:1; 1043 uint32_t sol_event:1; 1044 uint32_t eventable:1; 1045 1046 /* dw1 */ 1047 uint32_t pidx:11; 1048 uint32_t rsvd2:1; 1049 uint32_t pd:10; 1050 uint32_t eq_id:8; 1051 uint32_t stalled:1; 1052 uint32_t armed:1; 1053 1054 /* dw2 */ 1055 uint32_t rsvd3:4; 1056 uint32_t function:8; 1057 uint32_t rsvd4:20; 1058 #endif 1059 uint32_t rsvd5; 1060 }; 1061 1062 /* [12] OPCODE_CREATE_COMMON_CQ */ 1063 struct mbx_create_common_cq { 1064 struct mbx_hdr hdr; 1065 union { 1066 struct { 1067 #ifdef _BIG_ENDIAN 1068 uint16_t rsvd0; 1069 uint16_t num_pages; 1070 #else 1071 uint16_t num_pages; 1072 uint16_t rsvd0; 1073 #endif 1074 struct oce_cq_ctx cq_ctx; 1075 struct phys_addr pages[8]; 1076 }req; 1077 1078 struct { 1079 uint16_t cq_id; 1080 uint16_t rsvd0; 1081 }rsp; 1082 }params; 1083 }; 1084 1085 /* [54] OPCODE_DESTROY_COMMON_CQ */ 1086 struct mbx_destroy_common_cq { 1087 struct mbx_hdr hdr; 1088 union { 1089 struct { 1090 #ifdef _BIG_ENDIAN 1091 uint16_t rsvd0; 1092 uint16_t id; 1093 #else 1094 uint16_t id; 1095 uint16_t rsvd0; 1096 #endif 1097 }req; 1098 1099 struct { 1100 uint32_t rsvd0; 1101 }rsp; 1102 }params; 1103 }; 1104 1105 struct mq_ring_ctx { 1106 union { 1107 struct { 1108 #ifdef _BIG_ENDIAN 1109 /* dw 0 */ 1110 uint32_t cq_id:10; 1111 uint32_t fetch_r2t:1; 1112 uint32_t fetch_wrb:1; 1113 uint32_t ring_size:4; 1114 uint32_t rsvd0:2; 1115 uint32_t con_index:14; 1116 1117 /* dw1 */ 1118 uint32_t valid:1; 1119 uint32_t pdid:9; 1120 uint32_t fid:8; 1121 uint32_t prod_index:14; 1122 1123 /* dw 2 */ 1124 uint32_t rsvd1:21; 1125 uint32_t async_cq_id:10; 1126 uint32_t async_cq_valid:1; 1127 #else 1128 /* dw 0 */ 1129 uint32_t con_index:14; 1130 uint32_t rsvd0:2; 1131 uint32_t ring_size:4; 1132 uint32_t fetch_wrb:1; 1133 uint32_t fetch_r2t:1; 1134 uint32_t cq_id:10; 1135 1136 /* dw1 */ 1137 uint32_t prod_index:14; 1138 uint32_t fid:8; 1139 uint32_t pdid:9; 1140 uint32_t valid:1; 1141 1142 /* dw 2 */ 1143 uint32_t async_cq_valid:1; 1144 uint32_t async_cq_id:10; 1145 uint32_t rsvd1:21; 1146 #endif 1147 /* dw3 */ 1148 uint32_t rsvd3; 1149 }s; 1150 uint32_t dw[4]; 1151 }u0; 1152 }; 1153 1154 /* [21] OPCODE_CREATE_COMMON_MQ */ 1155 struct mbx_create_common_mq { 1156 struct mbx_hdr hdr; 1157 union { 1158 struct { 1159 #ifdef _BIG_ENDIAN 1160 uint16_t rsvd0; 1161 uint16_t num_pages; 1162 #else 1163 uint16_t num_pages; 1164 uint16_t rsvd0; 1165 #endif 1166 struct mq_ring_ctx context; 1167 struct phys_addr pages[8]; 1168 }req; 1169 1170 struct { 1171 uint32_t mq_id:16; 1172 uint32_t rsvd0:16; 1173 }rsp; 1174 }params; 1175 }; 1176 1177 /* [53] OPCODE_DESTROY_COMMON_MQ */ 1178 struct mbx_destroy_common_mq { 1179 struct mbx_hdr hdr; 1180 union { 1181 struct { 1182 #ifdef _BIG_ENDIAN 1183 uint16_t rsvd0; 1184 uint16_t id; 1185 #else 1186 uint16_t id; 1187 uint16_t rsvd0; 1188 #endif 1189 }req; 1190 1191 struct { 1192 uint32_t rsvd0; 1193 }rsp; 1194 }params; 1195 }; 1196 1197 /* [35] OPCODE_GET_COMMON_ FW_VERSION */ 1198 struct mbx_get_common_fw_version { 1199 struct mbx_hdr hdr; 1200 union { 1201 struct { 1202 uint32_t rsvd0; 1203 }req; 1204 1205 struct { 1206 uint8_t fw_ver_str[32]; 1207 uint8_t fw_on_flash_ver_str[32]; 1208 }rsp; 1209 }params; 1210 }; 1211 1212 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */ 1213 struct mbx_common_cev_modify_msi_messages { 1214 struct mbx_hdr hdr; 1215 union { 1216 struct { 1217 uint32_t num_msi_msgs; 1218 }req; 1219 1220 struct { 1221 uint32_t rsvd0; 1222 }rsp; 1223 }params; 1224 }; 1225 1226 /* [36] OPCODE_SET_COMMON_FLOW_CONTROL */ 1227 /* [37] OPCODE_GET_COMMON_FLOW_CONTROL */ 1228 struct mbx_common_get_set_flow_control { 1229 struct mbx_hdr hdr; 1230 #ifdef _BIG_ENDIAN 1231 uint16_t tx_flow_control; 1232 uint16_t rx_flow_control; 1233 #else 1234 uint16_t rx_flow_control; 1235 uint16_t tx_flow_control; 1236 #endif 1237 }; 1238 1239 enum e_flash_opcode { 1240 MGMT_FLASHROM_OPCODE_FLASH = 1, 1241 MGMT_FLASHROM_OPCODE_SAVE = 2 1242 }; 1243 1244 /* [06] OPCODE_READ_COMMON_FLASHROM */ 1245 /* [07] OPCODE_WRITE_COMMON_FLASHROM */ 1246 1247 struct mbx_common_read_write_flashrom { 1248 struct mbx_hdr hdr; 1249 uint32_t flash_op_code; 1250 uint32_t flash_op_type; 1251 uint32_t data_buffer_size; 1252 uint32_t data_offset; 1253 uint8_t data_buffer[4]; /* + IMAGE_TRANSFER_SIZE */ 1254 }; 1255 1256 struct mbx_common_query_fw_config { 1257 struct mbx_hdr hdr; 1258 union { 1259 struct { 1260 uint32_t rsvd0[30]; 1261 }req; 1262 1263 struct { 1264 uint32_t config_number; 1265 uint32_t asic_revision; 1266 uint32_t port_id; /* used for stats retrieval */ 1267 uint32_t function_mode; 1268 uint32_t ulp0_mode; 1269 uint32_t ulp0_nic_wqid_base; 1270 uint32_t ulp0_nic_wq_tot; 1271 uint32_t ulp0_toe_wqid_base; 1272 uint32_t ulp0_toe_wq_tot; 1273 uint32_t ulp0_toe_rqid_base; 1274 uint32_t ulp0_toe_rqid_tot; 1275 uint32_t ulp0_toe_defrqid_base; 1276 uint32_t ulp0_toe_defrq_tot; 1277 uint32_t ulp0_lro_rqid_base; 1278 uint32_t ulp0_lro_rqid_tot; 1279 uint32_t ulp0_iscsi_icd_base; 1280 uint32_t ulp0_iscsi_icd_tot; 1281 uint32_t ulp1_mode; 1282 uint32_t ulp1_nic_wqid_base; 1283 uint32_t ulp1_wq_tot; 1284 uint32_t ulp1_toe_wqid_base; 1285 uint32_t ulp1_toe_wq_tot; 1286 uint32_t ulp1_toe_rqid_base; 1287 uint32_t ulp1_toe_rqid_tot; 1288 uint32_t ulp1_toe_defrqid_base; 1289 uint32_t ulp1_toe_defrq_tot; 1290 uint32_t ulp1_lro_rqid_base; 1291 uint32_t ulp1_lro_rqid_tot; 1292 uint32_t ulp1_iscsi_icd_base; 1293 uint32_t ulp1_iscsi_icd_tot; 1294 }rsp; 1295 }params; 1296 }; 1297 1298 struct mbx_common_config_vlan { 1299 struct mbx_hdr hdr; 1300 union { 1301 struct { 1302 #ifdef _BIG_ENDIAN 1303 uint8_t num_vlans; 1304 uint8_t untagged; 1305 uint8_t promisc; 1306 uint8_t if_id; 1307 #else 1308 uint8_t if_id; 1309 uint8_t promisc; 1310 uint8_t untagged; 1311 uint8_t num_vlans; 1312 #endif 1313 union { 1314 struct normal_vlan normal_vlans[64]; 1315 struct qinq_vlan qinq_vlans[32]; 1316 }tags; 1317 }req; 1318 1319 struct { 1320 uint32_t rsvd; 1321 }rsp; 1322 }params; 1323 }; 1324 1325 /* [34] OPCODE_COMMON_NTWK_RX_FILTER */ 1326 struct mbx_set_common_ntwk_rx_filter { 1327 struct mbx_hdr hdr; 1328 uint32_t global_flags_mask; 1329 uint32_t global_flags; 1330 uint32_t iface_flags_mask; 1331 uint32_t iface_flags; 1332 uint32_t if_id; 1333 uint32_t num_mcast; 1334 struct { 1335 uint8_t byte[6]; 1336 }mac[32]; 1337 }; 1338 /* [41] OPCODE_MODIFY_COMMON_EQ_DELAY */ 1339 struct mbx_modify_common_eq_delay { 1340 struct mbx_hdr hdr; 1341 union { 1342 struct { 1343 uint32_t num_eq; 1344 struct { 1345 uint32_t eq_id; 1346 uint32_t phase; 1347 uint32_t dm; 1348 }delay[8]; 1349 }req; 1350 1351 struct { 1352 uint32_t rsvd0; 1353 }rsp; 1354 }params; 1355 }; 1356 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */ 1357 struct mbx_add_common_iface_mac { 1358 struct mbx_hdr hdr; 1359 union { 1360 struct { 1361 uint32_t if_id; 1362 uint8_t mac_address[6]; 1363 uint8_t rsvd0[2]; 1364 }req; 1365 struct { 1366 uint32_t pmac_id; 1367 }rsp; 1368 } params; 1369 }; 1370 1371 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */ 1372 struct mbx_del_common_iface_mac { 1373 struct mbx_hdr hdr; 1374 union { 1375 struct { 1376 uint32_t if_id; 1377 uint32_t pmac_id; 1378 }req; 1379 struct { 1380 uint32_t rsvd0; 1381 }rsp; 1382 } params; 1383 }; 1384 1385 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */ 1386 struct mbx_query_common_max_mbx_buffer_size { 1387 struct mbx_hdr hdr; 1388 struct { 1389 uint32_t max_ioctl_bufsz; 1390 } rsp; 1391 }; 1392 1393 /* [61] OPCODE_COMMON_FUNCTION_RESET */ 1394 struct ioctl_common_function_reset { 1395 struct mbx_hdr hdr; 1396 }; 1397 1398 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */ 1399 struct mbx_common_func_link_cfg { 1400 struct mbx_hdr hdr; 1401 union { 1402 struct { 1403 uint32_t enable; 1404 }req; 1405 struct { 1406 uint32_t rsvd0; 1407 }rsp; 1408 } params; 1409 }; 1410 1411 #pragma pack() 1412 1413 #ifdef __cplusplus 1414 } 1415 #endif 1416 1417 #endif /* _OCE_HW_H_ */ 1418