xref: /illumos-gate/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_queue.h (revision 8f23e9fa)

/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at
 * http://www.opensource.org/licenses/cddl1.txt.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2004-2012 Emulex. All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _EMLXS_QUEUE_H
#define	_EMLXS_QUEUE_H

#ifdef	__cplusplus
extern "C" {
#endif


/* Queue entry defines */

/* EQ entries */
typedef struct EQE
{
#ifdef EMLXS_BIG_ENDIAN
	uint32_t	CQId: 16;
	uint32_t	MinorCode: 12;
	uint32_t	MajorCode: 3;
	uint32_t	Valid: 1;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint32_t	Valid: 1;
	uint32_t	MajorCode: 3;
	uint32_t	MinorCode: 12;
	uint32_t	CQId: 16;
#endif

} EQE_t;

typedef union
{
	uint32_t	word;
	EQE_t		entry;

} EQE_u;

#define	EQE_VALID	0x00000001  /* Mask for EQE valid */
#define	EQE_CQID	0xFFFF0000  /* Mask for EQE CQID */

/* CQ entries */
typedef struct CQE_CmplWQ
{
#ifdef EMLXS_BIG_ENDIAN
	uint16_t	RequestTag;	/* Word 0 */
	uint8_t		Status;
	uint8_t		hw_status;

	uint32_t	CmdSpecific;	/* Word 1 */
	uint32_t	Parameter;	/* Word 2 */

	uint32_t	Valid: 1;	/* Word 3 */
	uint32_t	Rsvd1: 2;
	uint32_t	XB: 1;
	uint32_t	PV: 1;
	uint32_t	Priority: 3;
	uint32_t	Code: 8;
	uint32_t	Rsvd2: 16;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		hw_status;
	uint8_t		Status;
	uint16_t	RequestTag;	/* Word 0 */

	uint32_t	CmdSpecific;	/* Word 1 */
	uint32_t	Parameter;	/* Word 2 */

	uint32_t	Rsvd2: 16;
	uint32_t	Code: 8;
	uint32_t	Priority: 3;
	uint32_t	PV: 1;
	uint32_t	XB: 1;
	uint32_t	Rsvd1: 2;
	uint32_t	Valid: 1;	/* Word 3 */
#endif
} CQE_CmplWQ_t;

typedef struct CQE_RelWQ
{
#ifdef EMLXS_BIG_ENDIAN
	uint32_t	Reserved1;	/* Word 0 */
	uint32_t	Reserved2;	/* Word 1 */

	uint16_t	WQid;		/* Word 2 */
	uint16_t	WQindex;

	uint32_t	Valid: 1;	/* Word 3 */
	uint32_t	Rsvd1: 7;
	uint32_t	Code: 8;
	uint32_t	Rsvd2: 16;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint32_t	Reserved1;	/* Word 0 */
	uint32_t	Reserved2;	/* Word 1 */

	uint16_t	WQindex;
	uint16_t	WQid;		/* Word 2 */

	uint32_t	Rsvd2: 16;
	uint32_t	Code: 8;
	uint32_t	Rsvd1: 7;
	uint32_t	Valid: 1;	/* Word 3 */
#endif
} CQE_RelWQ_t;

typedef struct CQE_UnsolRcv
{
#ifdef EMLXS_BIG_ENDIAN
	uint16_t	RQindex;	/* Word 0 */
	uint8_t		Status;
	uint8_t		Rsvd1;

	uint32_t	Rsvd2;		/* Word 1 */

	uint32_t	data_size: 16;	/* Word 2 */
	uint32_t	RQid: 10;
	uint32_t	FCFId: 6;

	uint32_t	Valid: 1;	/* Word 3 */
	uint32_t	Rsvd3: 1;
	uint32_t	hdr_size: 6;
	uint32_t	Code: 8;
	uint32_t	eof: 8;
	uint32_t	sof: 8;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		Rsvd1;
	uint8_t		Status;
	uint16_t	RQindex;	/* Word 0 */

	uint32_t	Rsvd2;		/* Word 1 */

	uint32_t	FCFId: 6;
	uint32_t	RQid: 10;
	uint32_t	data_size: 16;	/* Word 2 */

	uint32_t	sof: 8;
	uint32_t	eof: 8;
	uint32_t	Code: 8;
	uint32_t	hdr_size: 6;
	uint32_t	Rsvd3: 1;
	uint32_t	Valid: 1;	/* Word 3 */
#endif
} CQE_UnsolRcv_t;


typedef struct CQE_UnsolRcvV1
{
#ifdef EMLXS_BIG_ENDIAN
	uint16_t	RQindex;	/* Word 0 */
	uint8_t		Status;
	uint8_t		Rsvd1;

	uint32_t	Rsvd2: 26;	/* Word 1 */
	uint32_t	FCFId: 6;

	uint16_t	data_size;	/* Word 2 */
	uint16_t	RQid;

	uint32_t	Valid: 1;	/* Word 3 */
	uint32_t	Rsvd3: 1;
	uint32_t	hdr_size: 6;
	uint32_t	Code: 8;
	uint32_t	eof: 8;
	uint32_t	sof: 8;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		Rsvd1;
	uint8_t		Status;
	uint16_t	RQindex;	/* Word 0 */

	uint32_t	FCFId: 6;
	uint32_t	Rsvd2: 26;	/* Word 1 */

	uint16_t	RQid;
	uint16_t	data_size;	/* Word 2 */

	uint32_t	sof: 8;
	uint32_t	eof: 8;
	uint32_t	Code: 8;
	uint32_t	hdr_size: 6;
	uint32_t	Rsvd3: 1;
	uint32_t	Valid: 1;	/* Word 3 */
#endif
} CQE_UnsolRcvV1_t;

/* Status defines */
#define	RQ_STATUS_SUCCESS		0x10
#define	RQ_STATUS_BUFLEN_EXCEEDED	0x11
#define	RQ_STATUS_NEED_BUFFER		0x12
#define	RQ_STATUS_FRAME_DISCARDED	0x13


typedef struct CQE_XRI_Abort
{
#ifdef EMLXS_BIG_ENDIAN
	uint16_t	Rsvd1;		/* Word 0 */
	uint8_t		Status;
	uint8_t		Rsvd2;

	uint32_t	rjtStatus;	/* Word 1 */

	uint16_t	RemoteXID;	/* Word 2 */
	uint16_t	XRI;

	uint32_t	Valid: 1;	/* Word 3 */
	uint32_t	IA: 1;
	uint32_t	BR: 1;
	uint32_t	EO: 1;
	uint32_t	Rsvd3: 4;
	uint32_t	Code: 8;
	uint32_t	Rsvd4: 16;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		Rsvd2;
	uint8_t		Status;
	uint16_t	Rsvd1;		/* Word 0 */

	uint32_t	rjtStatus;	/* Word 1 */

	uint16_t	XRI;
	uint16_t	RemoteXID;	/* Word 2 */

	uint32_t	Rsvd4: 16;
	uint32_t	Code: 8;
	uint32_t	Rsvd3: 4;
	uint32_t	EO: 1;
	uint32_t	BR: 1;
	uint32_t	IA: 1;
	uint32_t	Valid: 1;	/* Word 3 */
#endif
} CQE_XRI_Abort_t;



#define	CQE_VALID    0x80000000  /* Mask for CQE valid */

/* Defines for CQE Codes */
#define	CQE_TYPE_WQ_COMPLETION	1
#define	CQE_TYPE_RELEASE_WQE	2
#define	CQE_TYPE_UNSOL_RCV	4
#define	CQE_TYPE_XRI_ABORTED	5
#define	CQE_TYPE_UNSOL_RCV_V1	9


typedef struct CQE_ASYNC_FCOE
{
#ifdef EMLXS_BIG_ENDIAN
	uint32_t	ref_index;	/* Word 0 */

	uint16_t	evt_type;	/* Word 1 */
	uint16_t	fcf_count;

	uint32_t	event_tag;	/* Word 2 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint32_t	ref_index;	/* Word 0 */

	uint16_t	fcf_count;
	uint16_t	evt_type;	/* Word 1 */

	uint32_t	event_tag;	/* Word 2 */
#endif
} CQE_ASYNC_FCOE_t;

typedef struct CQE_ASYNC_LINK_STATE
{
#ifdef EMLXS_BIG_ENDIAN
	uint8_t		port_speed;	/* Word 0 */
	uint8_t		port_duplex;
	uint8_t		link_status;
	uint8_t		phys_port;

	uint16_t	qos_link_speed;	/* Word 1 */
	uint8_t		Rsvd1;
	uint8_t		port_fault;

	uint32_t	event_tag;	/* Word 2 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		phys_port;
	uint8_t		link_status;
	uint8_t		port_duplex;
	uint8_t		port_speed;	/* Word 0 */

	uint8_t		port_fault;	/* Word 1 */
	uint8_t		Rsvd1;
	uint16_t	qos_link_speed;

	uint32_t	event_tag;	/* Word 2 */
#endif
} CQE_ASYNC_LINK_STATE_t;

typedef struct CQE_ASYNC_GRP_5_QOS
{
#ifdef EMLXS_BIG_ENDIAN
	uint8_t		Rsvd2;
	uint8_t		Rsvd1;
	uint8_t		Rsvd0;
	uint8_t		phys_port;	/* Word 0 */

	uint16_t	qos_link_speed;
	uint8_t		Rsvd4;
	uint8_t		Rsvd3;		/* Word 1 */

	uint32_t	event_tag;	/* Word 2 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		phys_port;
	uint8_t		Rsvd0;
	uint8_t		Rsvd1;
	uint8_t		Rsvd2;		/* Word 0 */

	uint8_t		Rsvd3;
	uint8_t		Rsvd4;
	uint16_t	qos_link_speed;	/* Word 1 */

	uint32_t	event_tag;	/* Word 2 */
#endif
} CQE_ASYNC_GRP_5_QOS_t;


typedef struct CQE_ASYNC_FC_LINK_ATT
{
#ifdef EMLXS_BIG_ENDIAN
	uint8_t		port_speed;	/* Word 0 */
	uint8_t		topology;
	uint8_t		att_type;
	uint8_t		link_number;

	uint16_t	link_speed;	/* Word 1 */
	uint8_t		shared_link_status;
	uint8_t		port_fault;

	uint32_t	event_tag;	/* Word 2 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		link_number;
	uint8_t		att_type;
	uint8_t		topology;
	uint8_t		port_speed;	/* Word 0 */

	uint8_t		port_fault;
	uint8_t		shared_link_status;
	uint16_t	link_speed;	/* Word 1 */

	uint32_t	event_tag;	/* Word 2 */
#endif
} CQE_ASYNC_FC_LINK_ATT_t;

typedef struct CQE_ASYNC_PORT
{
	uint8_t		link_status[4];
	uint32_t	data_word2;
	uint32_t	Rsvd;
} CQE_ASYNC_PORT_t;

/* topology */
#define	TOPOLOGY_UNKNOWN	0
#define	TOPOLOGY_NPORT		1
#define	TOPOLOGY_LPORT		2
#define	TOPOLOGY_INTERNAL_LB	3
#define	TOPOLOGY_SERDES_LB	4

/* att_type */
#define	ATT_TYPE_LINK_UP	1
#define	ATT_TYPE_LINK_DOWN	2
#define	ATT_TYPE_NO_HARD_ALPA	3

/* shared_link_status */
#define	SHARED_STATUS_NONE			0
#define	SHARED_STATUS_LD_UNUSABLE		1
#define	SHARED_STATUS_LD_TRAN_FAULT		2
#define	SHARED_STATUS_LD_NO_SIGNAL		3
#define	SHARED_STATUS_LD_MGMT_DISABLED		4
#define	SHARED_STATUS_LU_FAILED_P2P		5
#define	SHARED_STATUS_LU_FAILED_FLOGI_TMO	6
#define	SHARED_STATUS_LU_FAILED_NO_FPORT	7
#define	SHARED_STATUS_LU_FAILED_NO_NPIV		8
#define	SHARED_STATUS_LU_FAILED_FLOGO		9
#define	SHARED_STATUS_LU_LOOPBACK		20
#define	SHARED_STATUS_LU_NORMAL			40

/* port_fault */
#define	PORT_FAULT_NONE		0