1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_OS_H 28 #define _EMLXS_OS_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #define EMLXS_MODREV2 2 /* Old Solaris 8 & 9 interface */ 35 #define EMLXS_MODREV3 3 /* New Solaris 10 & 11 interface */ 36 #define EMLXS_MODREV4 4 /* Sun FC packet change */ 37 /* Symbolic Node Name interface */ 38 #define EMLXS_MODREV5 5 /* New Sun NPIV Interface */ 39 40 #define EMLXS_MODREV2X 2 /* Old Solaris 8 & 9 x86 interface */ 41 #define EMLXS_MODREV3X 3 /* New Solaris 10 & 11 x86 interface */ 42 43 44 /* 45 * DRIVER LEVEL FEATURES 46 */ 47 #define DHCHAP_SUPPORT /* 2.21 driver */ 48 49 #define SATURN_MSI_SUPPORT /* 2.30 driver */ 50 #define MENLO_SUPPORT /* 2.30 driver */ 51 #define MBOX_EXT_SUPPORT /* 2.30 driver */ 52 53 #define DUMP_SUPPORT /* 2.40 driver */ 54 #define SAN_DIAG_SUPPORT /* 2.40 driver */ 55 #define FMA_SUPPORT /* 2.40 driver */ 56 57 /* #define IDLE_TIMER Not yet - untested */ 58 59 /* 60 * OS LEVEL FEATURES 61 */ 62 #ifdef S10 63 #define EMLXS_MODREV EMLXS_MODREV3 64 #define MSI_SUPPORT 65 66 67 #ifdef EMLXS_I386 68 #define EMLXS_MODREVX EMLXS_MODREV2X 69 #endif /* i386 */ 70 #endif /* S10 */ 71 72 73 #ifdef S11 74 #define MSI_SUPPORT 75 #define SFCT_SUPPORT /* COMSTAR Support */ 76 #define MODFW_SUPPORT /* Dynamic firmware module support */ 77 #define EMLXS_MODREV EMLXS_MODREV5 /* Sun NPIV Enhancement */ 78 79 #ifdef EMLXS_I386 80 #define EMLXS_MODREVX EMLXS_MODREV2X 81 #endif /* i386 */ 82 #endif /* S11 */ 83 84 /* 85 * SUBFEATURES 86 */ 87 #ifdef SFCT_SUPPORT 88 #define MODSYM_SUPPORT /* Dynamic Module Loading Support */ 89 #define FCIO_SUPPORT /* FCIO IOCTL support */ 90 #endif /* SFCT_SUPPORT */ 91 92 93 #ifndef EMLXS_MODREV 94 #define EMLXS_MODREV 0 95 #endif /* EMLXS_MODREV */ 96 97 #ifndef EMLXS_MODREVX 98 #define EMLXS_MODREVX 0 99 #endif /* EMLXS_MODREVX */ 100 101 /* Create combined definition */ 102 #if defined(S10) || defined(S11) 103 #define S10S11 104 #endif /* S10 or S11 */ 105 106 #define DRIVER_NAME "emlxs" 107 108 #include <sys/types.h> 109 #include <sys/varargs.h> 110 #include <sys/devops.h> 111 #include <sys/param.h> 112 #include <sys/user.h> 113 #include <sys/buf.h> 114 #include <sys/ioctl.h> 115 #include <sys/uio.h> 116 #include <sys/fcntl.h> 117 118 #include <sys/cmn_err.h> 119 #include <sys/stropts.h> 120 #include <sys/kmem.h> 121 122 #include <sys/errno.h> 123 #include <sys/open.h> 124 #include <sys/kmem.h> 125 #include <sys/poll.h> 126 #include <sys/thread.h> 127 #include <sys/taskq.h> 128 #include <sys/debug.h> 129 #include <sys/cpu.h> 130 #include <sys/autoconf.h> 131 #include <sys/conf.h> 132 #include <sys/stat.h> 133 #include <sys/var.h> 134 135 #include <sys/map.h> 136 #include <sys/file.h> 137 #include <sys/syslog.h> 138 #include <sys/disp.h> 139 #include <sys/taskq.h> 140 141 #include <sys/ddi.h> 142 #include <sys/sunddi.h> 143 #include <sys/promif.h> 144 #include <sys/ethernet.h> 145 #include <vm/seg_kmem.h> 146 #include <sys/utsname.h> 147 #include <sys/modctl.h> 148 #include <sys/scsi/scsi.h> 149 #include <sys/varargs.h> 150 #include <sys/atomic.h> 151 152 #include <emlxs_hbaapi.h> 153 154 #ifdef FMA_SUPPORT 155 #include <sys/ddifm.h> 156 #include <sys/fm/protocol.h> 157 #include <sys/fm/util.h> 158 #endif /* FMA_SUPPORT */ 159 #include <sys/fm/io/ddi.h> 160 161 #ifdef S11 162 163 /* ULP header files */ 164 #include <sys/fibre-channel/fc.h> 165 #include <sys/fibre-channel/impl/fc_fcaif.h> 166 167 #else /* !S11 */ 168 169 /* ULP header files */ 170 #include <sys/fibre-channel/fcio.h> 171 #include <sys/fibre-channel/fc.h> 172 #include <sys/fibre-channel/fc_appif.h> 173 #include <sys/fibre-channel/fc_types.h> 174 #include <sys/fibre-channel/impl/fc_error.h> 175 #include <sys/fibre-channel/impl/fc_fla.h> 176 #include <sys/fibre-channel/impl/fc_linkapp.h> 177 #include <sys/fibre-channel/impl/fcal.h> 178 #include <sys/fibre-channel/impl/fcgs2.h> 179 #include <sys/fibre-channel/impl/fcph.h> 180 #include <sys/fibre-channel/impl/fc_ulpif.h> 181 #include <sys/fibre-channel/impl/fc_fcaif.h> 182 #include <sys/fibre-channel/impl/fctl.h> 183 #include <sys/fibre-channel/impl/fctl_private.h> 184 #include <sys/fibre-channel/ulp/fcp.h> 185 #include <sys/fibre-channel/ulp/fcp_util.h> 186 187 #endif /* S11 */ 188 189 #ifndef FC_HBA_PORTSPEED_8GBIT 190 #define FC_HBA_PORTSPEED_8GBIT 16 191 #endif /* FC_HBA_PORTSPEED_8GBIT */ 192 193 #ifndef FP_DEFAULT_SID 194 #define FP_DEFAULT_SID (0x000AE) 195 #endif /* FP_DEFAULT_SID */ 196 197 #ifndef FP_DEFAULT_DID 198 #define FP_DEFAULT_DID (0x000EA) 199 #endif /* FP_DEFAULT_DID */ 200 201 #ifdef MSI_SUPPORT 202 #pragma weak ddi_intr_get_supported_types 203 #pragma weak ddi_intr_get_nintrs 204 #pragma weak ddi_intr_add_handler 205 #pragma weak ddi_intr_remove_handler 206 #pragma weak ddi_intr_get_hilevel_pri 207 #pragma weak ddi_intr_enable 208 #pragma weak ddi_intr_disable 209 #pragma weak ddi_intr_get_cap 210 #pragma weak ddi_intr_get_pri 211 #pragma weak ddi_intr_alloc 212 #pragma weak ddi_intr_free 213 #pragma weak ddi_intr_block_enable 214 #pragma weak ddi_intr_block_disable 215 extern int ddi_intr_get_supported_types(); 216 #endif /* MSI_SUPPORT */ 217 218 #ifndef MODSYM_SUPPORT 219 #pragma weak fc_fca_init 220 #pragma weak fc_fca_attach 221 #pragma weak fc_fca_detach 222 #endif /* MODSYM_SUPPORT */ 223 224 /* S11 flag for dma_attr_flags for ddi_dma_attr_t */ 225 #ifndef DDI_DMA_RELAXED_ORDERING 226 #define DDI_DMA_RELAXED_ORDERING 0x400 227 #endif /* DDI_DMA_RELAXED_ORDERING */ 228 229 #ifdef FMA_SUPPORT 230 /* FMA Support */ 231 #pragma weak ddi_fm_acc_err_clear 232 extern void ddi_fm_acc_err_clear(); 233 #endif /* FMA_SUPPORT */ 234 235 #ifdef EMLXS_SPARC 236 #define EMLXS_BIG_ENDIAN 237 #endif /* EMLXS_SPARC */ 238 239 #ifdef EMLXS_I386 240 #define EMLXS_LITTLE_ENDIAN 241 #endif /* EMLXS_I386 */ 242 243 244 /* Solaris 8 does not define this */ 245 #ifndef TASKQ_DYNAMIC 246 #define TASKQ_DYNAMIC 0x0004 247 #endif /* TASKQ_DYNAMIC */ 248 249 #ifdef _LP64 250 #define DEAD_PTR 0xdeadbeefdeadbeef 251 #else 252 #define DEAD_PTR 0xdeadbeef 253 #endif /* _LP64 */ 254 255 #ifndef FC_STATE_8GBIT_SPEED 256 /* This was obtained from OpenSolaris */ 257 #define FC_STATE_8GBIT_SPEED 0x0700 /* 8 Gbit/sec */ 258 #endif /* FC_STATE_8GBIT_SPEED */ 259 260 #define FC_STATE_QUAD_SPEED 0x0500 261 262 #ifndef BURSTSIZE 263 #define BURSTSIZE 264 #define BURST1 0x01 265 #define BURST2 0x02 266 #define BURST4 0x04 267 #define BURST8 0x08 268 #define BURST16 0x10 269 #define BURST32 0x20 270 #define BURST64 0x40 271 #ifdef _LP64 272 #define BURSTSIZE_MASK 0x7f 273 #else 274 #define BURSTSIZE_MASK 0x3f 275 #endif /* _LP64 */ 276 #define DEFAULT_BURSTSIZE (BURSTSIZE_MASK) /* all burst sizes */ 277 #endif /* BURSTSIZE */ 278 279 #define PADDR_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xffffffff)) 280 #define PADDR_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 281 #define PADDR(high, low) ((uint64_t)((((uint64_t)(high)) << 32) \ 282 | (((uint64_t)(low)) & 0xffffffff))) 283 284 #ifndef TRUE 285 #define TRUE 1 286 #endif /* TRUE */ 287 288 #ifndef FALSE 289 #define FALSE 0 290 #endif /* FALSE */ 291 292 #define DMA_READ_WRITE 0 293 #define DMA_READ_ONLY 1 294 #define DMA_WRITE_ONLY 2 295 296 #define DMA_SUCC 1 297 298 #define MAX_FC_BRDS 256 /* Maximum # boards per system */ 299 300 #define DELAYMS(ms) drv_usecwait((ms*1000)) 301 #define DELAYUS(us) drv_usecwait(us) 302 303 #define EMLXS_MPDATA_SYNC(h, a, b, c) \ 304 if (h) { \ 305 (void) ddi_dma_sync((ddi_dma_handle_t)(h), \ 306 (off_t)(a), (size_t)(b), (uint_t)c); \ 307 } 308 309 #define PKT2PRIV(pkt) ((emlxs_buf_t *)(pkt)->pkt_fca_private) 310 #define PRIV2PKT(sbp) sbp->pkt 311 312 #define EMLXS_INUMBER 0 313 #define EMLXS_MSI_INUMBER 0 314 315 #define EMLXS_DMA_ALIGN BURST16 316 317 /* 318 * Register indices in PCI configuration space. 319 */ 320 #define SBUS_FLASH_RD 0 /* FCODE-Flash Read only */ 321 /* index */ 322 #define SBUS_FLASH_RDWR 1 /* FCODE-Flash Read/Write */ 323 /* index */ 324 #define SBUS_DFLY_SLIM_RINDEX 2 /* DragonFly SLIM regs index */ 325 #define SBUS_DFLY_CSR_RINDEX 3 /* DragonFly I/O regs index */ 326 #define SBUS_TITAN_CORE_RINDEX 4 /* TITAN Core register index */ 327 #define SBUS_DFLY_PCI_CFG_RINDEX 5 /* DragonFly PCI ConfigSpace */ 328 /* regs index */ 329 #define SBUS_TITAN_PCI_CFG_RINDEX 6 /* TITAN PCI ConfigSpace regs */ 330 /* index */ 331 #define SBUS_TITAN_CSR_RINDEX 7 /* TITAN Control/Status regs */ 332 /* index */ 333 334 #define PCI_CFG_RINDEX 0 335 #define PCI_SLIM_RINDEX 1 336 #define PCI_CSR_RINDEX 2 337 338 #define PCI_BAR1_RINDEX 2 339 #define PCI_BAR2_RINDEX 3 340 341 342 #define EMLXS_MAX_UBUFS 65535 343 344 /* Tokens < EMLXS_UB_TOKEN_OFFSET are reserved for ELS response oxids */ 345 #define EMLXS_UB_TOKEN_OFFSET 0x100 346 347 typedef struct emlxs_ub_priv 348 { 349 fc_unsol_buf_t *ubp; 350 void *port; 351 352 uint32_t bpl_size; 353 uint8_t *bpl_virt; /* virtual address ptr */ 354 uint64_t bpl_phys; /* mapped address */ 355 void *bpl_data_handle; 356 void *bpl_dma_handle; 357 358 uint32_t ip_ub_size; 359 uint8_t *ip_ub_virt; /* virtual address ptr */ 360 ddi_dma_cookie_t ip_ub_dma_cookies[64]; 361 ddi_acc_handle_t ip_ub_data_handle; 362 ddi_dma_handle_t ip_ub_dma_handle; 363 uint32_t ip_ub_cookie_cnt; 364 uint32_t FC4type; 365 366 uint16_t flags; 367 #define EMLXS_UB_FREE 0x0000 368 #define EMLXS_UB_IN_USE 0x0001 369 #define EMLXS_UB_REPLY 0x0002 370 #define EMLXS_UB_RESV 0x0004 371 #define EMLXS_UB_TIMEOUT 0x0008 372 #define EMLXS_UB_INTERCEPT 0x0010 373 374 uint16_t available; 375 376 uint32_t timeout; /* Timeout period in seconds */ 377 uint32_t time; /* EMLXS_UB_IN_USE timestamp */ 378 uint32_t cmd; 379 uint32_t token; 380 381 struct emlxs_unsol_buf *pool; 382 struct emlxs_ub_priv *next; 383 } emlxs_ub_priv_t; 384 385 386 typedef struct emlxs_unsol_buf 387 { 388 struct emlxs_unsol_buf *pool_prev; /* ptr to prev type */ 389 /* of unsol_buf hdr */ 390 struct emlxs_unsol_buf *pool_next; /* ptr to next type */ 391 /* of unsol_buf hdr */ 392 393 uint32_t pool_type; /* FC-4 type */ 394 uint32_t pool_buf_size; /* buffer size for */ 395 /* this pool */ 396 397 uint32_t pool_nentries; /* no. of bufs in */ 398 /* pool */ 399 uint32_t pool_available; /* no. of bufs avail */ 400 /* in pool */ 401 402 uint32_t pool_flags; 403 #define POOL_DESTROY 0x00000001 /* Pool is marked for */ 404 /* destruction */ 405 406 uint32_t pool_free; /* Number of free */ 407 /* buffers */ 408 uint32_t pool_free_resv; /* Number of free */ 409 /* reserved buffers */ 410 411 uint32_t pool_first_token; /* First token */ 412 /* in pool */ 413 uint32_t pool_last_token; /* Last token */ 414 /* in pool */ 415 416 fc_unsol_buf_t *fc_ubufs; /* array of unsol buf */ 417 /* structs */ 418 } emlxs_unsol_buf_t; 419 420 421 #ifndef FC_REASON_NONE 422 #define FC_REASON_NONE 0 423 #endif /* FC_REASON_NONE */ 424 425 #ifndef FC_ACTION_NONE 426 #define FC_ACTION_NONE 0 427 #endif /* FC_ACTION_NONE */ 428 429 /* 430 * emlx status translation table 431 */ 432 typedef struct emlxs_xlat_err 433 { 434 uint32_t emlxs_status; 435 uint32_t pkt_state; 436 uint32_t pkt_reason; 437 uint32_t pkt_expln; 438 uint32_t pkt_action; 439 } emlxs_xlat_err_t; 440 441 442 typedef struct emlxs_table 443 { 444 uint32_t code; 445 char string[32]; 446 } emlxs_table_t; 447 448 449 /* PATCH MASK DEFINES */ 450 #define EMLXS_PATCH1 0x00000001 451 #define EMLXS_PATCH2 0x00000002 452 #define EMLXS_PATCH3 0x00000004 453 #define EMLXS_PATCH4 0x00000008 454 #define EMLXS_PATCH5 0x00000010 455 #define EMLXS_PATCH6 0x00000020 456 #define EMLXS_PATCH7 0x00000040 457 #define EMLXS_PATCH8 0x00000080 458 #define EMLXS_PATCH9 0x00000100 459 #define EMLXS_PATCH10 0x00000200 460 #define EMLXS_PATCH11 0x00000400 461 #define EMLXS_PATCH12 0x00000800 462 #define EMLXS_PATCH13 0x00001000 463 #define EMLXS_PATCH14 0x00002000 464 #define EMLXS_PATCH15 0x00004000 465 #define EMLXS_PATCH16 0x00008000 466 #define EMLXS_PATCH17 0x00010000 467 #define EMLXS_PATCH18 0x00020000 468 #define EMLXS_PATCH19 0x00040000 469 #define EMLXS_PATCH20 0x00080000 470 #define EMLXS_PATCH21 0x00100000 471 #define EMLXS_PATCH22 0x00200000 472 #define EMLXS_PATCH23 0x00400000 473 #define EMLXS_PATCH24 0x00800000 474 #define EMLXS_PATCH25 0x01000000 475 #define EMLXS_PATCH26 0x02000000 476 #define EMLXS_PATCH27 0x04000000 477 #define EMLXS_PATCH28 0x08000000 478 #define EMLXS_PATCH29 0x10000000 479 #define EMLXS_PATCH30 0x20000000 480 #define EMLXS_PATCH31 0x40000000 481 #define EMLXS_PATCH32 0x80000000 482 483 484 /* ULP Patches: */ 485 486 /* This patch enables the driver to auto respond to unsolicited LOGO's */ 487 /* This is needed because ULP is sometimes doesn't reply itself */ 488 #define ULP_PATCH2 EMLXS_PATCH2 489 490 /* This patch enables the driver to auto respond to unsolicited PRLI's */ 491 /* This is needed because ULP is known to panic sometimes */ 492 #define ULP_PATCH3 EMLXS_PATCH3 493 494 /* This patch enables the driver to auto respond to unsolicited PRLO's */ 495 /* This is needed because ULP is known to panic sometimes */ 496 #define ULP_PATCH4 EMLXS_PATCH4 497 498 /* This patch enables the driver to fail pkt abort requests */ 499 #define ULP_PATCH5 EMLXS_PATCH5 500 501 /* This patch enables the driver to generate an RSCN for unsolicited PRLO's */ 502 /* and LOGO's */ 503 #define ULP_PATCH6 EMLXS_PATCH6 504 505 /* Sun Disk Array Patches: */ 506 507 /* This patch enables the driver to fix a residual underrun issue with */ 508 /* check conditions */ 509 #define FCP_UNDERRUN_PATCH1 EMLXS_PATCH9 510 511 /* This patch enables the driver to fix a residual underrun issue with */ 512 /* SCSI inquiry commands */ 513 #define FCP_UNDERRUN_PATCH2 EMLXS_PATCH10 514 515 516 #define DEFAULT_PATCHES (ULP_PATCH2 | ULP_PATCH3 | \ 517 ULP_PATCH5 | ULP_PATCH6 | \ 518 FCP_UNDERRUN_PATCH1 | FCP_UNDERRUN_PATCH2) 519 520 #ifdef __cplusplus 521 } 522 #endif 523 524 #endif /* _EMLXS_OS_H */ 525