1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Emulex.  All rights reserved.
24  * Use is subject to License terms.
25  */
26 
27 
28 #ifndef _EMLXS_OS_H
29 #define	_EMLXS_OS_H
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #define	EMLXS_MODREV2    2	/* Old Solaris 8 & 9 interface */
36 #define	EMLXS_MODREV3    3	/* New Solaris 10 & 11 interface */
37 #define	EMLXS_MODREV4    4	/* Sun FC packet change */
38 				/* Symbolic Node Name interface */
39 #define	EMLXS_MODREV5    5	/* New Sun NPIV Interface */
40 
41 #define	EMLXS_MODREV2X   2	/* Old Solaris 8 & 9 x86 interface */
42 #define	EMLXS_MODREV3X   3	/* New Solaris 10 & 11 x86 interface */
43 
44 
45 /*
46  * DRIVER LEVEL FEATURES
47  */
48 #define	DFC_SUPPORT		/* 2.20 driver */
49 #define	DHCHAP_SUPPORT		/* 2.21 driver */
50 
51 #define	SATURN_MSI_SUPPORT	/* 2.30 driver */
52 
53 #define	MENLO_SUPPORT		/* 2.30 driver */
54 
55 #define	MBOX_EXT_SUPPORT	/* 2.30 driver */
56 #define	SLI3_SUPPORT		/* 2.30 driver - Required for NPIV */
57 
58 #define	DUMP_SUPPORT		/* 2.40 driver */
59 #define	SAN_DIAG_SUPPORT	/* 2.40 driver */
60 #define	FMA_SUPPORT		/* 2.40 driver */
61 
62 /* #define	IDLE_TIMER	 Not yet - untested */
63 
64 /*
65  * OS LEVEL FEATURES
66  */
67 #ifdef S10
68 #define	 EMLXS_MODREV EMLXS_MODREV3
69 #define	 MSI_SUPPORT
70 
71 #ifdef SLI3_SUPPORT
72 #define	NPIV_SUPPORT
73 #endif	/* SLI3_SUPPORT */
74 
75 #ifdef EMLXS_I386
76 #define	 EMLXS_MODREVX EMLXS_MODREV2X
77 #endif	/* EMLXS_I386 */
78 #endif	/* S10 */
79 
80 
81 #ifdef S11
82 #define	MSI_SUPPORT
83 #define	SFCT_SUPPORT  /* COMSTAR Support */
84 #define	MODFW_SUPPORT /* Dynamic firmware module support */
85 
86 #ifdef SLI3_SUPPORT
87 #define	NPIV_SUPPORT
88 
89 #ifdef NPIV_SUPPORT
90 #define	SUN_NPIV_SUPPORT  /* Nevada Build 92+ */
91 #endif /* NPIV_SUPPORT */
92 #endif	/* SLI3_SUPPORT */
93 
94 #ifdef SUN_NPIV_SUPPORT
95 #define	 EMLXS_MODREV EMLXS_MODREV5		/* Sun NPIV Enhancement */
96 #else
97 define	EMLXS_MODREV	EMLXS_MODREV4
98 #endif /* SUN_NPIV_SUPPORT */
99 
100 #ifdef EMLXS_I386
101 #define	 EMLXS_MODREVX EMLXS_MODREV2X
102 #endif	/* EMLXS_I386 */
103 #endif	/* S11 */
104 
105 /*
106  * SUBFEATURES
107  */
108 #ifdef SFCT_SUPPORT
109 #define	MODSYM_SUPPORT		/* Dynamic Module Loading Support */
110 #define	FCIO_SUPPORT		/* FCIO IOCTL support */
111 #endif /* SFCT_SUPPORT */
112 
113 
114 #ifndef EMLXS_MODREV
115 #define	EMLXS_MODREV			0
116 #endif /* EMLXS_MODREV */
117 
118 #ifndef EMLXS_MODREVX
119 #define	EMLXS_MODREVX			0
120 #endif /* EMLXS_MODREVX */
121 
122 /* Create combined definition */
123 #if defined(S10) || defined(S11)
124 #define	S10S11
125 #endif /* S10 or S11 */
126 
127 #define	DRIVER_NAME   "emlxs"
128 
129 #include <sys/types.h>
130 #include <sys/varargs.h>
131 #include <sys/devops.h>
132 #include <sys/param.h>
133 #include <sys/user.h>
134 #include <sys/buf.h>
135 #include <sys/ioctl.h>
136 #include <sys/uio.h>
137 #include <sys/fcntl.h>
138 
139 #include <sys/cmn_err.h>
140 #include <sys/stropts.h>
141 #include <sys/kmem.h>
142 
143 #include <sys/errno.h>
144 #include <sys/open.h>
145 #include <sys/kmem.h>
146 #include <sys/poll.h>
147 #include <sys/thread.h>
148 #include <sys/taskq.h>
149 #include <sys/debug.h>
150 #include <sys/cpu.h>
151 #include <sys/autoconf.h>
152 #include <sys/conf.h>
153 #include <sys/stat.h>
154 #include <sys/var.h>
155 
156 #include <sys/map.h>
157 #include <sys/file.h>
158 #include <sys/syslog.h>
159 #include <sys/disp.h>
160 #include <sys/taskq.h>
161 
162 #include <sys/ddi.h>
163 #include <sys/sunddi.h>
164 #include <sys/promif.h>
165 #include <sys/ethernet.h>
166 #include <vm/seg_kmem.h>
167 #include <sys/utsname.h>
168 #include <sys/modctl.h>
169 #include <sys/scsi/scsi.h>
170 #include <sys/varargs.h>
171 #include <sys/atomic.h>
172 
173 #include <emlxs_hbaapi.h>
174 
175 #ifdef FMA_SUPPORT
176 #include <sys/ddifm.h>
177 #include <sys/fm/protocol.h>
178 #include <sys/fm/util.h>
179 #endif	/* FMA_SUPPORT */
180 #include <sys/fm/io/ddi.h>
181 
182 #ifdef S11
183 
184 /* ULP header files */
185 #include <sys/fibre-channel/fc.h>
186 #include <sys/fibre-channel/impl/fc_fcaif.h>
187 
188 #else	/* !S11 */
189 
190 /* ULP header files */
191 #include <sys/fibre-channel/fcio.h>
192 #include <sys/fibre-channel/fc.h>
193 #include <sys/fibre-channel/fc_appif.h>
194 #include <sys/fibre-channel/fc_types.h>
195 #include <sys/fibre-channel/impl/fc_error.h>
196 #include <sys/fibre-channel/impl/fc_fla.h>
197 #include <sys/fibre-channel/impl/fc_linkapp.h>
198 #include <sys/fibre-channel/impl/fcal.h>
199 #include <sys/fibre-channel/impl/fcgs2.h>
200 #include <sys/fibre-channel/impl/fcph.h>
201 #include <sys/fibre-channel/impl/fc_ulpif.h>
202 #include <sys/fibre-channel/impl/fc_fcaif.h>
203 #include <sys/fibre-channel/impl/fctl.h>
204 #include <sys/fibre-channel/impl/fctl_private.h>
205 #include <sys/fibre-channel/ulp/fcp.h>
206 #include <sys/fibre-channel/ulp/fcp_util.h>
207 
208 #endif	/* S11 */
209 
210 #ifndef FC_HBA_PORTSPEED_8GBIT
211 #define	FC_HBA_PORTSPEED_8GBIT		16
212 #endif	/* FC_HBA_PORTSPEED_8GBIT */
213 
214 #ifndef FP_DEFAULT_SID
215 #define	FP_DEFAULT_SID		(0x000AE)
216 #endif	/* FP_DEFAULT_SID */
217 
218 #ifndef FP_DEFAULT_DID
219 #define	FP_DEFAULT_DID		(0x000EA)
220 #endif	/* FP_DEFAULT_DID */
221 
222 #ifdef MSI_SUPPORT
223 #pragma weak ddi_intr_get_supported_types
224 #pragma weak ddi_intr_get_nintrs
225 #pragma weak ddi_intr_add_handler
226 #pragma weak ddi_intr_remove_handler
227 #pragma weak ddi_intr_get_hilevel_pri
228 #pragma weak ddi_intr_enable
229 #pragma weak ddi_intr_disable
230 #pragma weak ddi_intr_get_cap
231 #pragma weak ddi_intr_get_pri
232 #pragma weak ddi_intr_alloc
233 #pragma weak ddi_intr_free
234 #pragma weak ddi_intr_block_enable
235 #pragma weak ddi_intr_block_disable
236 extern int ddi_intr_get_supported_types();
237 #endif	/* MSI_SUPPORT */
238 
239 #ifndef MODSYM_SUPPORT
240 #pragma weak fc_fca_init
241 #pragma weak fc_fca_attach
242 #pragma weak fc_fca_detach
243 #endif /* MODSYM_SUPPORT */
244 
245 /* S11 flag for dma_attr_flags for ddi_dma_attr_t */
246 #ifndef DDI_DMA_RELAXED_ORDERING
247 #define	DDI_DMA_RELAXED_ORDERING	0x400
248 #endif	/* DDI_DMA_RELAXED_ORDERING */
249 
250 #ifdef FMA_SUPPORT
251 /* FMA Support */
252 #pragma weak ddi_fm_acc_err_clear
253 extern void ddi_fm_acc_err_clear();
254 #endif	/* FMA_SUPPORT */
255 
256 #ifdef EMLXS_SPARC
257 #define	EMLXS_BIG_ENDIAN
258 #endif	/* EMLXS_SPARC */
259 
260 #ifdef EMLXS_I386
261 #define	EMLXS_LITTLE_ENDIAN
262 #endif	/* EMLXS_I386 */
263 
264 
265 /* Solaris 8 does not define this */
266 #ifndef TASKQ_DYNAMIC
267 #define	TASKQ_DYNAMIC	0x0004
268 #endif	/* TASKQ_DYNAMIC */
269 
270 #ifdef _LP64
271 #define	DEAD_PTR   0xdeadbeefdeadbeef
272 #else
273 #define	DEAD_PTR   0xdeadbeef
274 #endif	/* _LP64 */
275 
276 #ifndef FC_STATE_8GBIT_SPEED
277 /* This was obtained from OpenSolaris */
278 #define	FC_STATE_8GBIT_SPEED		0x0700	/* 8 Gbit/sec */
279 #endif	/* FC_STATE_8GBIT_SPEED */
280 
281 #define	FC_STATE_QUAD_SPEED		0x0500
282 
283 #ifndef BURSTSIZE
284 #define	BURSTSIZE
285 #define	BURST1			0x01
286 #define	BURST2			0x02
287 #define	BURST4			0x04
288 #define	BURST8			0x08
289 #define	BURST16			0x10
290 #define	BURST32			0x20
291 #define	BURST64			0x40
292 #ifdef _LP64
293 #define	BURSTSIZE_MASK		0x7f
294 #else
295 #define	BURSTSIZE_MASK		0x3f
296 #endif	/* _LP64 */
297 #define	DEFAULT_BURSTSIZE	(BURSTSIZE_MASK)	/* all burst sizes */
298 #endif	/* BURSTSIZE */
299 
300 #define	putPaddrLow(addr)	((uint32_t)(((uint64_t)(addr)) & 0xffffffff))
301 #define	putPaddrHigh(addr)	((uint32_t)(((uint64_t)(addr)) >> 32))
302 #define	getPaddr(high, low)	((uint64_t)((((uint64_t)(high)) << 32) \
303 					| (((uint64_t)(low)) & 0xffffffff)))
304 
305 #ifndef TRUE
306 #define	TRUE	1
307 #endif	/* TRUE */
308 
309 #ifndef FALSE
310 #define	FALSE	0
311 #endif	/* FALSE */
312 
313 #define	DMA_READ_WRITE		0
314 #define	DMA_READ_ONLY		1
315 #define	DMA_WRITE_ONLY		2
316 
317 #define	DMA_SUCC		1
318 
319 #define	MAX_FC_BRDS		256	/* Maximum # boards per system */
320 
321 #define	DELAYMS(ms)		drv_usecwait((ms*1000))
322 #define	DELAYUS(us)		drv_usecwait(us)
323 
324 #ifdef FMA_SUPPORT
325 #define	emlxs_mpdata_sync(h, a, b, c)  \
326 	if (h)  { \
327 		(void) ddi_dma_sync((ddi_dma_handle_t)(h), \
328 			(off_t)(a), (size_t)(b), (uint_t)c); \
329 		if (emlxs_fm_check_dma_handle(hba, h) != DDI_FM_OK) { \
330 			EMLXS_MSGF(EMLXS_CONTEXT, \
331 			    &emlxs_invalid_dma_handle_msg, \
332 			    "ddi_dma_sync hdl=%p off=%x " \
333 			    "size=%d dir=%x ", \
334 			    h, a, b, c); \
335 		} \
336 	}
337 #else	/* !FMA_SUPPORT */
338 #define	emlxs_mpdata_sync(h, a, b, c)  \
339 	if (h)  { \
340 		(void) ddi_dma_sync((ddi_dma_handle_t)(h), \
341 			(off_t)(a), (size_t)(b), (uint_t)c); \
342 	}
343 #endif	/* FMA_SUPPORT */
344 
345 
346 
347 #define	PKT2PRIV(pkt)		((emlxs_buf_t *)(pkt)->pkt_fca_private)
348 #define	PRIV2PKT(sbp)		sbp->pkt
349 
350 #define	EMLXS_INUMBER		0
351 #define	EMLXS_MSI_INUMBER 	0
352 
353 #define	EMLXS_DMA_ALIGN		BURST16
354 
355 /*
356  * Register indices in PCI configuration space.
357  */
358 #define	SBUS_FLASH_RD			0	/* FCODE-Flash Read only */
359 						/* index */
360 #define	SBUS_FLASH_RDWR			1	/* FCODE-Flash Read/Write */
361 						/* index */
362 #define	SBUS_DFLY_SLIM_RINDEX	  2	/* DragonFly SLIM regs index */
363 #define	SBUS_DFLY_CSR_RINDEX	  3	/* DragonFly I/O regs index */
364 #define	SBUS_TITAN_CORE_RINDEX	  4	/* TITAN Core register index */
365 #define	SBUS_DFLY_PCI_CFG_RINDEX	5	/* DragonFly PCI ConfigSpace */
366 						/* regs index */
367 #define	SBUS_TITAN_PCI_CFG_RINDEX	6	/* TITAN PCI ConfigSpace regs */
368 						/* index */
369 #define	SBUS_TITAN_CSR_RINDEX		7	/* TITAN Control/Status regs */
370 						/* index */
371 
372 #define	PCI_CFG_RINDEX		  0
373 #define	PCI_SLIM_RINDEX		  1
374 #define	PCI_CSR_RINDEX		  2
375 
376 #define	EMLXS_MAX_UBUFS		65535
377 
378 /* Tokens < EMLXS_UB_TOKEN_OFFSET are reserved for ELS response oxids */
379 #define	EMLXS_UB_TOKEN_OFFSET	0x100
380 
381 typedef struct emlxs_ub_priv
382 {
383 	fc_unsol_buf_t	*ubp;
384 	void		*port;
385 
386 	uint32_t	bpl_size;
387 	uint8_t		*bpl_virt;	/* virtual address ptr */
388 	uint64_t	bpl_phys;	/* mapped address */
389 	void		*bpl_data_handle;
390 	void		*bpl_dma_handle;
391 
392 	uint32_t	ip_ub_size;
393 	uint8_t		*ip_ub_virt;	/* virtual address ptr */
394 	ddi_dma_cookie_t ip_ub_dma_cookies[64];
395 	ddi_acc_handle_t ip_ub_data_handle;
396 	ddi_dma_handle_t ip_ub_dma_handle;
397 	uint32_t	ip_ub_cookie_cnt;
398 	uint32_t	FC4type;
399 
400 	uint16_t	flags;
401 #define	EMLXS_UB_FREE		0x0000
402 #define	EMLXS_UB_IN_USE		0x0001
403 #define	EMLXS_UB_REPLY		0x0002
404 #define	EMLXS_UB_RESV		0x0004
405 #define	EMLXS_UB_TIMEOUT	0x0008
406 #define	EMLXS_UB_INTERCEPT	0x0010
407 
408 	uint16_t	available;
409 
410 	uint32_t	timeout;	/* Timeout period in seconds */
411 	uint32_t	time;	/* EMLXS_UB_IN_USE timestamp */
412 	uint32_t	cmd;
413 	uint32_t	token;
414 
415 	struct emlxs_unsol_buf *pool;
416 	struct emlxs_ub_priv *next;
417 } emlxs_ub_priv_t;
418 
419 
420 typedef struct emlxs_unsol_buf
421 {
422 	struct emlxs_unsol_buf	*pool_prev;		/* ptr to prev type */
423 							/* of unsol_buf hdr */
424 	struct emlxs_unsol_buf	*pool_next;		/* ptr to next type */
425 							/* of unsol_buf hdr */
426 
427 	uint32_t		pool_type;		/* FC-4 type */
428 	uint32_t		pool_buf_size;		/* buffer size for */
429 							/* this pool */
430 
431 	uint32_t		pool_nentries;		/* no. of bufs in */
432 							/* pool */
433 	uint32_t		pool_available;		/* no. of bufs avail */
434 							/* in pool */
435 
436 	uint32_t		pool_flags;
437 #define	POOL_DESTROY		0x00000001		/* Pool is marked for */
438 							/* destruction */
439 
440 	uint32_t		pool_free;		/* Number of free */
441 							/* buffers */
442 	uint32_t		pool_free_resv;		/* Number of free */
443 							/* reserved buffers */
444 
445 	uint32_t		pool_first_token;	/* First token */
446 							/* in pool */
447 	uint32_t		pool_last_token;	/* Last token */
448 							/* in pool */
449 
450 	fc_unsol_buf_t		*fc_ubufs;		/* array of unsol buf */
451 							/* structs */
452 } emlxs_unsol_buf_t;
453 
454 
455 #ifndef FC_REASON_NONE
456 #define	FC_REASON_NONE			0
457 #endif /* FC_REASON_NONE */
458 
459 #ifndef FC_ACTION_NONE
460 #define	FC_ACTION_NONE			0
461 #endif /* FC_ACTION_NONE */
462 
463 /*
464  * emlx status translation table
465  */
466 typedef struct emlxs_xlat_err
467 {
468 	uint32_t	emlxs_status;
469 	uint32_t	pkt_state;
470 	uint32_t	pkt_reason;
471 	uint32_t	pkt_expln;
472 	uint32_t	pkt_action;
473 } emlxs_xlat_err_t;
474 
475 
476 typedef struct emlxs_table
477 {
478 	uint32_t	code;
479 	char		string[32];
480 } emlxs_table_t;
481 
482 #ifdef	__cplusplus
483 }
484 #endif
485 
486 #endif	/* _EMLXS_OS_H */
487