1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Emulex. All rights reserved. 24 * Use is subject to License terms. 25 */ 26 27 28 #ifndef _EMLXS_MENLO_H 29 #define _EMLXS_MENLO_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #ifdef MENLO_SUPPORT 36 37 /* 38 * COMMANDS 39 */ 40 41 typedef struct menlo_init_cmd { 42 uint32_t code; /* Command code = MENLO_CMD_INITIALIZE */ 43 uint32_t bb_credit; /* Menlo FC BB Credit */ 44 uint32_t frame_size; /* Menlo FC receive frame size */ 45 46 } menlo_init_cmd_t; 47 48 49 typedef struct menlo_fw_download_cmd { 50 uint32_t code; /* Command code = MENLO_CMD_FW_DOWNLOAD */ 51 uint32_t length; /* Firmware image length in bytes (4 byte */ 52 /* aligned) */ 53 uint32_t type; /* Firmware image type */ 54 55 #define MENLO_IMAGE_TYPE_OP 1 56 #define MENLO_IMAGE_TYPE_DIAG 2 57 58 /* Followed by length bytes of firmware image */ 59 /* Firmware image will be in Little Endian format */ 60 61 } menlo_fw_download_cmd_t; 62 63 64 typedef struct menlo_memory_cmd { 65 uint32_t code; /* Command code */ 66 uint32_t address; /* Menlo memory address */ 67 uint32_t length; /* Number of words */ 68 69 } menlo_memory_cmd_t; 70 71 72 typedef struct menlo_fte_insert_cmd { 73 uint32_t code; /* Command code = MENLO_CMD_FTE_INSERT */ 74 uint32_t mask; /* mask = True or False */ 75 76 #define MENLO_SRC_MASK_FALSE 0 77 #define MENLO_SRC_MASK_TRUE 1 78 79 uint32_t fcid; /* FCID of remote port */ 80 uint8_t wwpn[8]; /* WWPN of remote port */ 81 82 } menlo_fte_insert_cmd_t; 83 84 85 typedef struct menlo_fte_delete_cmd { 86 uint32_t code; /* Command code = MENLO_CMD_FTE_DELETE */ 87 uint32_t fcid; /* FCID of remote port */ 88 uint8_t wwpn[8]; /* WWPN of remote port */ 89 90 } menlo_fte_delete_cmd_t; 91 92 93 typedef struct menlo_get_cmd { 94 uint32_t code; /* Command code */ 95 uint32_t context; /* Context */ 96 97 /* MENLO_CMD_GET_PORT_STATS */ 98 #define MENLO_PORT_ETH0 0 99 #define MENLO_PORT_ETH1 1 100 #define MENLO_PORT_NSL0 2 101 #define MENLO_PORT_NSL1 3 102 #define MENLO_PORT_FC0 4 103 #define MENLO_PORT_FC1 5 104 105 /* MENLO_CMD_GET_LIF_STATS */ 106 #define MENLO_LIF_ETH0 0 107 #define MENLO_LIF_ETH1 1 108 #define MENLO_LIF_FC0 2 109 #define MENLO_LIF_FC1 3 110 111 /* MENLO_CMD_GET_LB_MODE */ 112 #define MENLO_NSL_PORT_ID_0 0 113 #define MENLO_NSL_PORT_ID_1 1 114 115 uint32_t length; /* Max response length */ 116 117 } menlo_get_cmd_t; 118 119 120 typedef struct menlo_set_cmd { 121 uint32_t code; /* Command code = MENLO_CMD_SET_PAUSE */ 122 uint32_t value1; /* value1 */ 123 uint32_t value2; /* value2 */ 124 125 /* MENLO_CMD_SET_PAUSE values */ 126 #define MENLO_PAUSE_TYPE_SP 1 127 #define MENLO_PAUSE_TYPE_PPP 2 128 129 /* PPP Priority bits: [ ][ ][ ][ ][X][ ][ ][ ] */ 130 /* COS: 7 6 5 4 3 2 1 0 */ 131 #define MENLO_PPP_COS0 0x01 132 #define MENLO_PPP_COS1 0x02 133 #define MENLO_PPP_COS2 0x04 134 #define MENLO_PPP_COS3 0x08 135 #define MENLO_PPP_COS4 0x10 136 #define MENLO_PPP_COS5 0x20 137 #define MENLO_PPP_COS6 0x40 138 #define MENLO_PPP_COS7 0x80 139 140 /* MENLO_CMD_SET_FCOE_COS values */ 141 #define MENLO_FCOE_COS 3 142 143 /* MENLO_CMD_SET_UIF_PORT_TYPE values */ 144 #define MENLO_PORT_TYPE_ACCESS 1 145 #define MENLO_PORT_TYPE_TRUNK 2 146 147 /* MENLO_CMD_SET_MODE values */ 148 #define MENLO_MAINTENANCE_MODE_DISABLE 0 149 #define MENLO_MAINTENANCE_MODE_ENABLE 1 150 151 } menlo_set_cmd_t; 152 153 154 typedef struct menlo_loopback_cmd { 155 uint32_t code; /* Command code = MENLO_CMD_LOOPBACK */ 156 uint32_t context; /* context = NSL port 0 or 1 */ 157 158 #define MENLO_NSL_PORT_ID_0 0 159 #define MENLO_NSL_PORT_ID_1 1 160 161 uint32_t type; /* type = loopback mode enable or disable */ 162 163 #define MENLO_LOOPBACK_DISABLE 0 164 #define MENLO_LOOPBACK_ENABLE 1 165 166 } menlo_loopback_cmd_t; 167 168 169 typedef struct menlo_reset_cmd { 170 uint32_t code; /* Command code = MENLO_CMD_RESET */ 171 uint32_t firmware; 172 173 #define MENLO_FW_OPERATIONAL 0 174 #define MENLO_FW_GOLDEN 1 175 176 } menlo_reset_cmd_t; 177 178 typedef struct menlo_fru_data_cmd { 179 uint32_t code; /* Response code */ 180 uint8_t mac0[8]; /* MAC address of port 0 */ 181 uint8_t mac1[8]; /* MAC address of port 1 */ 182 uint32_t flags; 183 184 /* Valid flags */ 185 #define MENLO_FLAG_SINGLE_CHANNEL 0x00000001 186 #define MENLO_FLAG_DUAL_CHANNEL 0x00000002 187 188 } menlo_fru_data_cmd_t; 189 190 191 typedef struct menlo_diag_cmd { 192 uint32_t code; /* Response code */ 193 uint32_t loop_count; /* loop_count = 0 indicates loop forever */ 194 /* loop_count > 0 indicates number of test iterations */ 195 /* NOTE : one test iteration takes approximately 2-3 seconds */ 196 uint32_t test_bitmap; /* Each bit represents a separate test to be */ 197 /* performed */ 198 /* 199 * test_bitmap = 0 will result in a MENLO_ERR_INVALID_FLAG 200 * error 201 */ 202 203 } menlo_diag_cmd_t; 204 205 206 typedef union menlo_cmd { 207 uint32_t word[5]; 208 uint32_t code; /* Command code */ 209 210 /* Command codes */ 211 #define MENLO_CMD_INITIALIZE 0x00000001 212 #define MENLO_CMD_FW_DOWNLOAD 0x00000002 213 #define MENLO_CMD_READ_MEMORY 0x00000003 214 #define MENLO_CMD_WRITE_MEMORY 0x00000004 215 #define MENLO_CMD_FTE_INSERT 0x00000005 216 #define MENLO_CMD_FTE_DELETE 0x00000006 217 218 #define MENLO_CMD_GET_INIT 0x00000007 219 #define MENLO_CMD_GET_CONFIG 0x00000008 220 #define MENLO_CMD_GET_PORT_STATS 0x00000009 221 #define MENLO_CMD_GET_LIF_STATS 0x0000000A 222 #define MENLO_CMD_GET_ASIC_STATS 0x0000000B 223 #define MENLO_CMD_GET_LOG_CONFIG 0x0000000C 224 #define MENLO_CMD_GET_LOG_DATA 0x0000000D 225 #define MENLO_CMD_GET_PANIC_LOG 0x0000000E 226 #define MENLO_CMD_GET_LB_MODE 0x0000000F 227 228 #define MENLO_CMD_SET_PAUSE 0x00000010 229 #define MENLO_CMD_SET_FCOE_COS 0x00000011 230 #define MENLO_CMD_SET_UIF_PORT_TYPE 0x00000012 231 232 #define MENLO_CMD_DIAGNOSTICS 0x00000013 233 #define MENLO_CMD_LOOPBACK 0x00000014 234 #define MENLO_CMD_GET_FTABLE 0x00000015 235 #define MENLO_CMD_GET_SFP_DATA 0x00000016 236 #define MENLO_CMD_SET_FRU_DATA 0x00000017 237 #define MENLO_CMD_GET_FRU_DATA 0x00000018 238 #define MENLO_CMD_SET_FCOE_FORMAT 0x00000019 239 #define MENLO_CMD_GET_DIAG_LOG 0x00000020 240 #define MENLO_CMD_PANIC 0x00000021 241 242 /* Zephyr specific Menlo commands */ 243 #define MENLO_CMD_RESET 0x80000001 244 #define MENLO_CMD_SET_MODE 0x80000002 245 246 menlo_init_cmd_t init; 247 menlo_fw_download_cmd_t fw; 248 menlo_memory_cmd_t mem; 249 menlo_fte_insert_cmd_t fte_insert; 250 menlo_fte_delete_cmd_t fte_delete; 251 menlo_get_cmd_t get; 252 menlo_set_cmd_t set; 253 menlo_loopback_cmd_t lb; 254 menlo_reset_cmd_t reset; 255 menlo_fru_data_cmd_t fru; 256 menlo_diag_cmd_t diag; 257 258 } menlo_cmd_t; 259 260 261 /* 262 * RESPONSES 263 */ 264 265 typedef struct menlo_init_rsp { 266 uint32_t code; 267 uint32_t bb_credit; /* Menlo FC BB Credit */ 268 uint32_t frame_size; /* Menlo FC receive frame size */ 269 uint32_t fw_version; /* Menlo firmware version */ 270 uint32_t reset_status; /* Reason for previous reset */ 271 272 #define MENLO_RESET_STATUS_NORMAL 0 273 #define MENLO_RESET_STATUS_PANIC 1 274 275 uint32_t maint_status; /* Menlo Maintenance Mode status at link up */ 276 277 #define MENLO_MAINTENANCE_MODE_DISABLE 0 278 #define MENLO_MAINTENANCE_MODE_ENABLE 1 279 280 uint32_t fw_type; 281 282 #define MENLO_FW_TYPE_OPERATIONAL 0xABCD0001 283 #define MENLO_FW_TYPE_GOLDEN 0xABCD0002 284 #define MENLO_FW_TYPE_DIAG 0xABCD0003 285 286 uint32_t fru_data_valid; /* 0=invalid, 1=valid */ 287 288 } menlo_init_rsp_t; 289 290 291 #define MENLO_MAX_FC_PORTS 2 292 #define MENLO_MAX_UIF_PORTS 2 293 294 typedef struct menlo_get_config_rsp { 295 uint32_t code; 296 297 uint32_t pause_type[MENLO_MAX_UIF_PORTS]; 298 uint32_t priority[MENLO_MAX_UIF_PORTS]; 299 uint32_t fcoe_cos[MENLO_MAX_FC_PORTS]; 300 uint32_t uif_port_type[MENLO_MAX_UIF_PORTS]; 301 302 uint32_t log_cfg_size; /* Size of log config region. Needed for */ 303 /* MENLO_CMD_GET_LOG_CONFIG */ 304 uint32_t panic_log_size; /* Size of panic log region. Needed */ 305 /* for MENLO_CMD_GET_PANIC_LOG */ 306 307 uint32_t dcx_present[MENLO_MAX_UIF_PORTS]; 308 309 uint32_t current_pause_type[MENLO_MAX_UIF_PORTS]; 310 uint32_t current_priority[MENLO_MAX_UIF_PORTS]; 311 uint32_t current_fcoe_cos[MENLO_MAX_FC_PORTS]; 312 uint32_t current_uif_port_type[MENLO_MAX_UIF_PORTS]; 313 314 uint32_t fcoe_format; /* Bit field - single bit will be set (See */ 315 /* below) */ 316 uint32_t current_fcoe_format; /* Bit field - single bit will be set */ 317 /* (See below) */ 318 uint32_t supported_fcoe_format; /* Bit field - multiple bits may be */ 319 /* set (See below) */ 320 321 #define FCOE_FRAME_FORMAT_P0 0x00010000 /* Pre-T11 format */ 322 #define FCOE_FRAME_FORMAT_T0 0x00000001 /* T11 format Rev 0 */ 323 #define FCOE_FRAME_FORMAT_T1 0x00000002 324 #define FCOE_FRAME_FORMAT_T2 0x00000004 325 #define FCOE_FRAME_FORMAT_T3 0x00000008 326 #define FCOE_FRAME_FORMAT_T4 0x00000010 327 #define FCOE_FRAME_FORMAT_T5 0x00000020 328 #define FCOE_FRAME_FORMAT_T6 0x00000040 329 #define FCOE_FRAME_FORMAT_T7 0x00000080 330 #define FCOE_FRAME_FORMAT_T8 0x00000100 331 #define FCOE_FRAME_FORMAT_T9 0x00000200 332 #define FCOE_FRAME_FORMAT_T10 0x00000400 333 #define FCOE_FRAME_FORMAT_T11 0x00000800 334 #define FCOE_FRAME_FORMAT_T12 0x00001000 335 #define FCOE_FRAME_FORMAT_T13 0x00002000 336 #define FCOE_FRAME_FORMAT_T14 0x00004000 337 #define FCOE_FRAME_FORMAT_T15 0x00008000 338 339 } menlo_get_config_rsp_t; 340 341 342 typedef struct menlo_fc_stats_rsp { 343 uint32_t code; 344 345 uint64_t rx_class_2_frames; 346 uint64_t rx_class_3_frames; 347 uint64_t rx_class_F_frames; 348 uint64_t rx_class_other_frames; 349 350 uint64_t tx_class_2_frames; 351 uint64_t tx_class_3_frames; 352 uint64_t tx_class_F_frames; 353 uint64_t tx_class_other_frames; 354 355 uint64_t rx_class_2_words; 356 uint64_t rx_class_3_words; 357 uint64_t rx_class_F_words; 358 uint64_t rx_class_other_words; 359 360 uint64_t tx_class_2_words; 361 uint64_t tx_class_3_words; 362 uint64_t tx_class_F_words; 363 uint64_t tx_class_other_words; 364 365 uint64_t rx_class_2_frames_bad; 366 uint64_t rx_class_3_frames_bad; 367 uint64_t rx_class_F_frames_bad; 368 uint64_t rx_class_other_frames_bad; 369 370 uint64_t tx_class_2_frames_bad; 371 uint64_t tx_class_3_frames_bad; 372 uint64_t tx_class_F_frames_bad; 373 uint64_t tx_class_other_frames_bad; 374 375 } menlo_fc_stats_rsp_t; 376 377 378 typedef struct menlo_network_stats_rsp { 379 uint32_t code; 380 381 uint64_t tx_pkt_lt64; 382 uint64_t tx_pkt_64; 383 uint64_t tx_pkt_65; 384 uint64_t tx_pkt_128; 385 uint64_t tx_pkt_256; 386 uint64_t tx_pkt_512; 387 uint64_t tx_pkt_1024; 388 uint64_t tx_pkt_1519; 389 uint64_t tx_pkt_2048; 390 uint64_t tx_pkt_4096; 391 uint64_t tx_pkt_8192; 392 uint64_t tx_pkt_gt9216; 393 uint64_t tx_pkt_total; 394 uint64_t tx_octet_sok; 395 uint64_t tx_pkt_ok; 396 uint64_t tx_ucast; 397 uint64_t tx_mcast; 398 uint64_t tx_bcast; 399 uint64_t tx_vlan; 400 uint64_t tx_pause; 401 uint64_t tx_priority_pause; 402 uint64_t tx_frame_error; 403 404 uint64_t rx_pkt_lt64; 405 uint64_t rx_pkt_64; 406 uint64_t rx_pkt_65; 407 uint64_t rx_pkt_128; 408 uint64_t rx_pkt_256; 409 uint64_t rx_pkt_512; 410 uint64_t rx_pkt_1024; 411 uint64_t rx_pkt_1519; 412 uint64_t rx_pkt_2048; 413 uint64_t rx_pkt_4096; 414 uint64_t rx_pkt_8192; 415 uint64_t rx_pkt_gt9216; 416 uint64_t rx_pkt_total; 417 uint64_t rx_octet_sok; 418 uint64_t rx_pkt_ok; 419 uint64_t rx_ucast; 420 uint64_t rx_mcast; 421 uint64_t rx_bcast; 422 uint64_t rx_vlan; 423 uint64_t rx_oversize; 424 uint64_t rx_toolong; 425 uint64_t rx_discard; 426 uint64_t rx_undersize; 427 uint64_t rx_fragment; 428 uint64_t rx_crc_err; 429 uint64_t rx_inrange_err; 430 uint64_t rx_jabber; 431 uint64_t rx_pause; 432 uint64_t rx_priority_pause; 433 434 } menlo_network_stats_rsp_t; 435 436 437 typedef struct menlo_lif_stats_rsp { 438 uint32_t code; 439 440 uint64_t eg_pkt_count; 441 uint64_t ig_pkt_count; 442 443 uint64_t eg_byte_count; 444 uint64_t ig_byte_count; 445 446 uint64_t eg_error_count; 447 uint64_t ig_error_count; 448 449 uint64_t eg_drop_count; 450 uint64_t ig_drop_count; 451 452 } menlo_lif_stats_rsp_t; 453 454 455 typedef struct menlo_asic_stats_rsp { 456 uint32_t code; 457 458 uint64_t eq_cputx0_cecount; 459 uint64_t eq_cputx0_dropacl; 460 uint64_t eq_cputx0_dropovr; 461 uint64_t eq_cputx0_droprunt; 462 uint64_t eq_cputx0_poperr; 463 uint64_t eq_cputx0_pusherr; 464 uint64_t eq_cputx0_truncovr; 465 uint64_t eq_cputx0_uecount; 466 467 uint64_t eq_cputx1_cecount; 468 uint64_t eq_cputx1_dropacl; 469 uint64_t eq_cputx1_dropovr; 470 uint64_t eq_cputx1_droprunt; 471 uint64_t eq_cputx1_poperr; 472 uint64_t eq_cputx1_pusherr; 473 uint64_t eq_cputx1_truncovr; 474 uint64_t eq_cputx1_uecount; 475 476 uint64_t eq_eth0_dropovr; 477 uint64_t eq_eth0_droprunt; 478 uint64_t eq_eth0_truncovr; 479 480 uint64_t eq_eth0a_cecount; 481 uint64_t eq_eth0a_dropacl; 482 uint64_t eq_eth0a_poperr; 483 uint64_t eq_eth0a_pusherr; 484 uint64_t eq_eth0a_uecount; 485 486 uint64_t eq_eth0b_cecount; 487 uint64_t eq_eth0b_dropacl; 488 uint64_t eq_eth0b_poperr; 489 uint64_t eq_eth0b_pusherr; 490 uint64_t eq_eth0b_uecount; 491 492 uint64_t eq_eth1_dropovr; 493 uint64_t eq_eth1_droprunt; 494 uint64_t eq_eth1_truncovr; 495 496 uint64_t eq_eth1a_cecount; 497 uint64_t eq_eth1a_dropacl; 498 uint64_t eq_eth1a_poperr; 499 uint64_t eq_eth1a_pusherr; 500 uint64_t eq_eth1a_uecount; 501 502 uint64_t eq_eth1b_cecount; 503 uint64_t eq_eth1b_dropacl; 504 uint64_t eq_eth1b_poperr; 505 uint64_t eq_eth1b_pusherr; 506 uint64_t eq_eth1b_uecount; 507 508 uint64_t eq_fc0_cecount; 509 uint64_t eq_fc0_dropacl; 510 uint64_t eq_fc0_dropovr; 511 uint64_t eq_fc0_droprunt; 512 uint64_t eq_fc0_poperr; 513 uint64_t eq_fc0_pusherr; 514 uint64_t eq_fc0_truncovr; 515 uint64_t eq_fc0_uecount; 516 517 uint64_t eq_fc1_cecount; 518 uint64_t eq_fc1_dropacl; 519 uint64_t eq_fc1_dropovr; 520 uint64_t eq_fc1_droprunt; 521 uint64_t eq_fc1_poperr; 522 uint64_t eq_fc1_pusherr; 523 uint64_t eq_fc1_truncovr; 524 uint64_t eq_fc1_uecount; 525 526 uint64_t eq_fl_cecount; 527 uint64_t eq_fl_uecount; 528 529 uint64_t eq_pkt_buf_cecount; 530 uint64_t eq_pkt_buf_uecount; 531 532 uint64_t iq_cpurx0_cecount; 533 uint64_t iq_cpurx0_n0_dropovr; 534 uint64_t iq_cpurx0_n0_truncovr; 535 uint64_t iq_cpurx0_n1_dropovr; 536 uint64_t iq_cpurx0_n1_truncovr; 537 uint64_t iq_cpurx0_poperr; 538 uint64_t iq_cpurx0_pusherr; 539 uint64_t iq_cpurx0_uecount; 540 541 uint64_t iq_cpurx1_cecount; 542 uint64_t iq_cpurx1_n0_dropovr; 543 uint64_t iq_cpurx1_n0_truncovr; 544 uint64_t iq_cpurx1_n1_dropovr; 545 uint64_t iq_cpurx1_n1_truncovr; 546 uint64_t iq_cpurx1_poperr; 547 uint64_t iq_cpurx1_pusherr; 548 uint64_t iq_cpurx1_uecount; 549 550 uint64_t iq_cputx_cecount; 551 uint64_t iq_cputx_dropovr; 552 uint64_t iq_cputx_droprunt; 553 uint64_t iq_cputx_poperr; 554 uint64_t iq_cputx_pusherr; 555 uint64_t iq_cputx_truncovr; 556 uint64_t iq_cputx_uecount; 557 558 uint64_t iq_eth0a_cecount; 559 uint64_t iq_eth0a_n0_dropovr; 560 uint64_t iq_eth0a_n0_truncovr; 561 uint64_t iq_eth0a_n1_dropovr; 562 uint64_t iq_eth0a_n1_truncovr; 563 uint64_t iq_eth0a_poperr; 564 uint64_t iq_eth0a_pusherr; 565 uint64_t iq_eth0a_uecount; 566 567 uint64_t iq_eth0b_cecount; 568 uint64_t iq_eth0b_n0_dropovr; 569 uint64_t iq_eth0b_n0_truncovr; 570 uint64_t iq_eth0b_n1_dropovr; 571 uint64_t iq_eth0b_n1_truncovr; 572 uint64_t iq_eth0b_poperr; 573 uint64_t iq_eth0b_pusherr; 574 uint64_t iq_eth0b_uecount; 575 576 uint64_t iq_eth1a_cecount; 577 uint64_t iq_eth1a_n0_dropovr; 578 uint64_t iq_eth1a_n0_truncovr; 579 uint64_t iq_eth1a_n1_dropovr; 580 uint64_t iq_eth1a_n1_truncovr; 581 uint64_t iq_eth1a_poperr; 582 uint64_t iq_eth1a_pusherr; 583 uint64_t iq_eth1a_uecount; 584 585 uint64_t iq_eth1b_cecount; 586 uint64_t iq_eth1b_n0_dropovr; 587 uint64_t iq_eth1b_n0_truncovr; 588 uint64_t iq_eth1b_n1_dropovr; 589 uint64_t iq_eth1b_n1_truncovr; 590 uint64_t iq_eth1b_poperr; 591 uint64_t iq_eth1b_pusherr; 592 uint64_t iq_eth1b_uecount; 593 594 uint64_t iq_fc0_cecount; 595 uint64_t iq_fc0_n0_dropovr; 596 uint64_t iq_fc0_n0_truncovr; 597 uint64_t iq_fc0_n1_dropovr; 598 uint64_t iq_fc0_n1_truncovr; 599 uint64_t iq_fc0_poperr; 600 uint64_t iq_fc0_pusherr; 601 uint64_t iq_fc0_uecount; 602 603 uint64_t iq_fc1_cecount; 604 uint64_t iq_fc1_n0_dropovr; 605 uint64_t iq_fc1_n0_truncovr; 606 uint64_t iq_fc1_n1_dropovr; 607 uint64_t iq_fc1_n1_truncovr; 608 uint64_t iq_fc1_poperr; 609 uint64_t iq_fc1_pusherr; 610 uint64_t iq_fc1_uecount; 611 612 uint64_t iq_fl_cecount; 613 uint64_t iq_fl_uecount; 614 615 uint64_t iq_n0_cecount; 616 uint64_t iq_n0_dropacl; 617 uint64_t iq_n0_dropovr; 618 uint64_t iq_n0_droprunt; 619 uint64_t iq_n0_poperr; 620 uint64_t iq_n0_pusherr; 621 uint64_t iq_n0_truncovr; 622 uint64_t iq_n0_uecount; 623 624 uint64_t iq_n1_cecount; 625 uint64_t iq_n1_dropacl; 626 uint64_t iq_n1_dropovr; 627 uint64_t iq_n1_droprunt; 628 uint64_t iq_n1_poperr; 629 uint64_t iq_n1_pusherr; 630 uint64_t iq_n1_truncovr; 631 uint64_t iq_n1_uecount; 632 633 uint64_t iq_pkt_buf_cecount; 634 uint64_t iq_pkt_buf_uecount; 635 636 uint64_t iq_rc_cecount; 637 uint64_t iq_rc_uecount; 638 639 uint64_t misc_mmem_cecount; 640 uint64_t misc_mmem_uecount; 641 642 uint64_t net_eg0_learn_req_drop; 643 uint64_t net_eg0_pkt_drop_cmd; 644 uint64_t net_eg0_pkt_drop_lifcfg_invalid; 645 uint64_t net_eg0_pkt_drop_lifmap_no_hit; 646 uint64_t net_eg0_pkt_drop_src_bind; 647 648 uint64_t net_eg1_learn_req_drop; 649 uint64_t net_eg1_pkt_drop_cmd; 650 uint64_t net_eg1_pkt_drop_lifcfg_invalid; 651 uint64_t net_eg1_pkt_drop_lifmap_no_hit; 652 uint64_t net_eg1_pkt_drop_src_bind; 653 654 uint64_t net_ig0_fwd_lookup_no_hit; 655 uint64_t net_ig0_pkt_drop_fc_multicast; 656 uint64_t net_ig0_pkt_drop_invalid_fc_lif; 657 uint64_t net_ig0_pkt_null_pif; 658 659 uint64_t net_ig1_fwd_lookup_no_hit; 660 uint64_t net_ig1_pkt_drop_fc_multicast; 661 uint64_t net_ig1_pkt_drop_invalid_fc_lif; 662 uint64_t net_ig1_pkt_null_pif; 663 664 uint64_t host10gbe_port0_rx_pause_cfc; 665 uint64_t host10gbe_port0_rx_pause_pfc; 666 uint64_t host10gbe_port0_tx_pause_cfc; 667 uint64_t host10gbe_port0_tx_pause_pfc; 668 669 uint64_t host10gbe_port1_rx_pause_cfc; 670 uint64_t host10gbe_port1_rx_pause_pfc; 671 uint64_t host10gbe_port1_tx_pause_cfc; 672 uint64_t host10gbe_port1_tx_pause_pfc; 673 674 uint64_t dce_port0_rx_pause_cfc; 675 uint64_t dce_port0_rx_pause_pfc; 676 uint64_t dce_port0_tx_pause_cfc; 677 uint64_t dce_port0_tx_pause_pfc; 678 679 uint64_t dce_port1_rx_pause_cfc; 680 uint64_t dce_port1_rx_pause_pfc; 681 uint64_t dce_port1_tx_pause_cfc; 682 uint64_t dce_port1_tx_pause_pfc; 683 684 } menlo_asic_stats_rsp_t; 685 686 687 #define MENLO_LOG_NAME_SIZE 20 688 689 typedef struct menlo_log { 690 #ifdef EMLXS_BIG_ENDIAN 691 uint16_t num_entries; 692 uint16_t id; 693 694 uint16_t rsvd; 695 uint16_t entry_size; 696 #endif /* EMLXS_BIG_ENDIAN */ 697 698 #ifdef EMLXS_LITTLE_ENDIAN 699 uint16_t id; 700 uint16_t num_entries; 701 702 uint16_t entry_size; 703 uint16_t rsvd; 704 #endif /* EMLXS_LITTLE_ENDIAN */ 705 706 char name[MENLO_LOG_NAME_SIZE]; 707 708 } menlo_log_t; 709 710 711 typedef struct menlo_log_config_rsp { 712 uint32_t code; 713 714 #ifdef EMLXS_BIG_ENDIAN 715 uint16_t rsvd; 716 uint16_t num_logs; /* Number of logs in log array */ 717 #endif /* EMLXS_BIG_ENDIAN */ 718 719 #ifdef EMLXS_LITTLE_ENDIAN 720 uint16_t num_logs; /* Number of logs in log array */ 721 uint16_t rsvd; 722 #endif /* EMLXS_LITTLE_ENDIAN */ 723 724 uint32_t data; /* First word of array: menlo_log_t log[num_logs] */ 725 726 } menlo_log_config_rsp_t; 727 728 729 typedef struct menlo_log_data_rsp { 730 uint32_t code; 731 732 #ifdef EMLXS_BIG_ENDIAN 733 uint16_t rsvd; 734 uint16_t head; /* Index of oldest log entry in circular data array */ 735 #endif /* EMLXS_BIG_ENDIAN */ 736 737 #ifdef EMLXS_LITTLE_ENDIAN 738 uint16_t head; /* Index of oldest log entry in circular data array */ 739 uint16_t rsvd; 740 #endif /* EMLXS_LITTLE_ENDIAN */ 741 742 uint32_t data; /* char array[menlo_log_t.num_entries] */ 743 /* [menlo_log_t.entry_size] */ 744 745 } menlo_log_data_rsp_t; 746 747 748 #define MENLO_NUM_GP_REGS 32 749 750 typedef struct menlo_panic_log_data_rsp { 751 uint32_t code; 752 uint32_t rsvd_flag; /* N/A to mgmt utility */ 753 uint32_t type; /* Panic type (See beleow) */ 754 755 #define MENLO_PANIC_TYPE_SOLICITED 0xdead0001 756 #define MENLO_PANIC_TYPE_EXCEPTION 0xdead0002 757 758 uint32_t regs_epc; 759 uint32_t regs_cp0_cause; 760 uint32_t regs_cp0_status; 761 uint32_t regs_gp[MENLO_NUM_GP_REGS]; 762 763 #ifdef EMLXS_BIG_ENDIAN 764 uint16_t num_entries; /* Number of entries in data array */ 765 uint16_t log_present; /* Number of entries in data array */ 766 767 uint16_t head; /* Index of oldest log entry in circular data buffer */ 768 uint16_t entry_size; /* Size of each entry */ 769 #endif /* EMLXS_BIG_ENDIAN */ 770 771 #ifdef EMLXS_LITTLE_ENDIAN 772 uint16_t log_present; /* Number of entries in data array */ 773 uint16_t num_entries; /* Number of entries in data array */ 774 775 uint16_t entry_size; /* Size of each entry */ 776 uint16_t head; /* Index of oldest log entry in circular data buffer */ 777 #endif /* EMLXS_LITTLE_ENDIAN */ 778 779 uint32_t data; /* char array[num_entries][entry_size] */ 780 781 } menlo_panic_log_data_rsp_t; 782 783 784 typedef struct menlo_lb_mode_rsp { 785 uint32_t code; 786 uint32_t mode; /* Menlo loopback mode */ 787 788 } menlo_lb_mode_rsp_t; 789 790 791 #define MENLO_MAX_FTABLE_ENTRIES 256 792 793 typedef struct menlo_fte { 794 #ifdef EMLXS_BIG_ENDIAN 795 uint8_t type_mask; 796 uint8_t type; 797 uint16_t flags; 798 799 uint16_t tag_mask; 800 uint16_t tag; /* Ehternet VLAN tag */ 801 #endif /* EMLXS_BIG_ENDIAN */ 802 803 #ifdef EMLXS_LITTLE_ENDIAN 804 uint16_t flags; 805 uint8_t type; 806 uint8_t type_mask; 807 808 uint16_t tag; /* Ehternet VLAN tag */ 809 uint16_t tag_mask; 810 #endif /* EMLXS_LITTLE_ENDIAN */ 811 812 #define MENLO_FTABLE_ENTRY_VALID 0x8000 /* flags field */ 813 814 uint8_t mac_addr[8]; /* mac addr */ 815 uint8_t mac_addr_mask[8]; /* mac addr mask */ 816 uint8_t fc_wwpn[8]; /* wwpn */ 817 818 uint32_t lif_bitmap; /* forwarding vector */ 819 uint32_t rsvd; 820 821 } menlo_fte_t; 822 823 typedef struct menlo_ftable_rsp { 824 uint32_t code; /* Response code */ 825 826 menlo_fte_t entry[MENLO_MAX_FTABLE_ENTRIES]; 827 828 } menlo_ftable_rsp_t; 829 830 831 #define MENLO_SFP_PAGE_SIZE 256 832 833 typedef struct menlo_sfp_rsp { 834 uint32_t code; /* Response code */ 835 uint8_t page_a0[MENLO_SFP_PAGE_SIZE]; 836 uint8_t page_a2[MENLO_SFP_PAGE_SIZE]; 837 838 } menlo_sfp_rsp_t; 839 840 841 typedef struct menlo_fru_data_rsp { 842 uint32_t code; /* Response code */ 843 uint8_t mac0[8]; /* MAC address of port 0 */ 844 uint8_t mac1[8]; /* MAC address of port 1 */ 845 uint32_t flags; 846 847 } menlo_fru_data_rsp_t; 848 849 850 typedef struct menlo_diag_log_data_rsp { 851 uint32_t code; /* Response code */ 852 uint32_t data_length; /* Length of the diagnostic log buffer */ 853 /* (bytes) */ 854 uint32_t data; /* menlo_diag_log_t log of size data_length bytes */ 855 856 } menlo_diag_log_data_rsp_t; 857 858 859 typedef struct menlo_diag_log { 860 uint32_t num_tests; /* Number of entries in data array */ 861 uint32_t status_length; /* Size (words) of the */ 862 /* menlo_diag_log_entry_t.data array */ 863 uint32_t requested_loop_cnt; /* Number of test iterations */ 864 /* requested */ 865 uint32_t completed_loop_cnt; /* Number of test iterations actually */ 866 /* completed */ 867 uint32_t test_summary; /* Overal test status */ 868 869 #define DIAG_TEST_STATUS_SUCCESS 0xD0000001 870 #define DIAG_TEST_STATUS_FAIL 0xD0000002 871 #define DIAG_TEST_STATUS_ABORT 0xD0000003 872 873 uint32_t data; /* menlo_diag_log_entry_t entry[num_tests] */ 874 875 } menlo_diag_log_t; 876 877 typedef struct menlo_diag_log_entry { 878 uint32_t status; /* Test status See DIAG_TEST_STATUS_XXXXX */ 879 /* above */ 880 uint32_t data; /* uint32_t array[menlo_diag_log_t.status_length] */ 881 882 } menlo_diag_log_entry_t; 883 884 885 886 typedef union menlo_rsp { 887 uint32_t word[32]; 888 uint32_t code; 889 890 /* Response codes */ 891 #define MENLO_RSP_SUCCESS 0x00000000 892 #define MENLO_ERR_FAILED 0x00000001 893 #define MENLO_ERR_INVALID_CMD 0x00000002 894 #define MENLO_ERR_INVALID_CREDIT 0x00000003 895 #define MENLO_ERR_INVALID_SIZE 0x00000004 896 #define MENLO_ERR_INVALID_ADDRESS 0x00000005 897 #define MENLO_ERR_INVALID_CONTEXT 0x00000006 898 #define MENLO_ERR_INVALID_LENGTH 0x00000007 899 #define MENLO_ERR_INVALID_TYPE 0x00000008 900 #define MENLO_ERR_INVALID_DATA 0x00000009 901 #define MENLO_ERR_INVALID_VALUE1 0x0000000A 902 #define MENLO_ERR_INVALID_VALUE2 0x0000000B 903 #define MENLO_ERR_INVALID_MASK 0x0000000C 904 #define MENLO_ERR_CHECKSUM 0x0000000D 905 #define MENLO_ERR_UNKNOWN_FCID 0x0000000E 906 #define MENLO_ERR_UNKNOWN_WWN 0x0000000F 907 #define MENLO_ERR_BUSY 0x00000010 908 #define MENLO_ERR_INVALID_FLAG 0x00000011 909 #define MENLO_ERR_SFP_ABSENT 0x00000012 910 911 menlo_init_rsp_t init; 912 menlo_get_config_rsp_t config; 913 menlo_fc_stats_rsp_t fc_stats; 914 menlo_network_stats_rsp_t net_stats; 915 menlo_lif_stats_rsp_t lif_stats; 916 menlo_log_config_rsp_t log_cfg; 917 menlo_log_data_rsp_t log; 918 menlo_panic_log_data_rsp_t panic_log; 919 menlo_lb_mode_rsp_t lb_mode; 920 menlo_asic_stats_rsp_t asic_stats; 921 menlo_ftable_rsp_t ftable; 922 menlo_sfp_rsp_t sfp; 923 menlo_fru_data_rsp_t fru; 924 menlo_diag_log_data_rsp_t diag_log; 925 926 } menlo_rsp_t; 927 928 929 /* 930 * FIRMWARE IMAGE 931 */ 932 933 typedef struct menlo_image_hdr { 934 uint32_t rsvd1; 935 uint32_t rsvd2; 936 uint32_t version; 937 uint32_t file_length; /* Length of entire file */ 938 uint32_t image_length; /* length of the image without padding */ 939 uint32_t rsvd3; 940 uint32_t rsvd4; 941 uint32_t checksum_offset; /* Byte offset to image checksum */ 942 943 } menlo_image_hdr_t; 944 945 946 /* The version header structure needs to be a multiple of 4 bytes */ 947 typedef struct menlo_version_hdr { 948 uint32_t padded; /* 1 = Image padded, 0 = Image not padded */ 949 950 uint32_t type; 951 952 /* Type */ 953 #define MENLO_IMAGE_TYPE_FIRMWARE 1 954 #define MENLO_IMAGE_TYPE_DIAGNOSTICS 2 955 956 uint32_t version; /* fw or diag version */ 957 uint32_t checksum; /* 32bit XOR checksum -- needs to be at the */ 958 /* end */ 959 960 } menlo_version_hdr_t; 961 962 963 #endif /* MENLO_SUPPORT */ 964 965 #ifdef __cplusplus 966 } 967 #endif 968 969 #endif /* _EMLXS_MENLO_H */ 970