xref: /illumos-gate/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_mbox.h (revision e2ca2865a6870e9c6cbef6becbcc68cafde64537)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Emulex.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _EMLXS_MBOX_H
28 #define	_EMLXS_MBOX_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 /* SLI 2/3 Mailbox defines */
35 
36 #define	MBOX_SIZE			256
37 #define	MBOX_EXTENSION_OFFSET		MBOX_SIZE
38 
39 #ifdef MBOX_EXT_SUPPORT
40 #define	MBOX_EXTENSION_SIZE		1024
41 #else
42 #define	MBOX_EXTENSION_SIZE		0
43 #endif /* MBOX_EXT_SUPPORT */
44 
45 
46 
47 /* ==== Mailbox Commands ==== */
48 #define	MBX_SHUTDOWN			0x00	/* terminate testing */
49 #define	MBX_LOAD_SM			0x01
50 #define	MBX_READ_NV			0x02
51 #define	MBX_WRITE_NV			0x03
52 #define	MBX_RUN_BIU_DIAG		0x04
53 #define	MBX_INIT_LINK			0x05
54 #define	MBX_DOWN_LINK			0x06
55 #define	MBX_CONFIG_LINK			0x07
56 #define	MBX_PART_SLIM			0x08
57 #define	MBX_CONFIG_RING			0x09
58 #define	MBX_RESET_RING			0x0A
59 #define	MBX_READ_CONFIG			0x0B
60 #define	MBX_READ_RCONFIG		0x0C
61 #define	MBX_READ_SPARM			0x0D
62 #define	MBX_READ_STATUS			0x0E
63 #define	MBX_READ_RPI			0x0F
64 #define	MBX_READ_XRI			0x10
65 #define	MBX_READ_REV			0x11
66 #define	MBX_READ_LNK_STAT		0x12
67 #define	MBX_REG_LOGIN			0x13
68 #define	MBX_UNREG_LOGIN			0x14  /* SLI2/3 */
69 #define	MBX_UNREG_RPI			0x14  /* SLI4 */
70 #define	MBX_READ_LA			0x15
71 #define	MBX_CLEAR_LA			0x16
72 #define	MBX_DUMP_MEMORY			0x17
73 #define	MBX_DUMP_CONTEXT		0x18
74 #define	MBX_RUN_DIAGS			0x19
75 #define	MBX_RESTART			0x1A
76 #define	MBX_UPDATE_CFG			0x1B
77 #define	MBX_DOWN_LOAD			0x1C
78 #define	MBX_DEL_LD_ENTRY		0x1D
79 #define	MBX_RUN_PROGRAM			0x1E
80 #define	MBX_SET_MASK			0x20
81 #define	MBX_SET_VARIABLE		0x21
82 #define	MBX_UNREG_D_ID			0x23
83 #define	MBX_KILL_BOARD			0x24
84 #define	MBX_CONFIG_FARP			0x25
85 #define	MBX_BEACON			0x2A
86 #define	MBX_READ_VPI			0x2B
87 #define	MBX_CONFIG_MSIX			0x30
88 #define	MBX_HEARTBEAT			0x31
89 #define	MBX_WRITE_VPARMS		0x32
90 #define	MBX_ASYNC_EVENT			0x33
91 
92 #define	MBX_READ_EVENT_LOG_STATUS	0x37
93 #define	MBX_READ_EVENT_LOG		0x38
94 #define	MBX_WRITE_EVENT_LOG		0x39
95 #define	MBX_NV_LOG			0x3A
96 #define	MBX_PORT_CAPABILITIES		0x3B
97 #define	MBX_IOV_CONTROL			0x3C
98 #define	MBX_IOV_MBX			0x3D
99 
100 
101 #define	MBX_CONFIG_HBQ			0x7C  /* SLI3 */
102 #define	MBX_LOAD_AREA			0x81
103 #define	MBX_RUN_BIU_DIAG64		0x84
104 #define	MBX_GET_DEBUG			0x86
105 #define	MBX_CONFIG_PORT			0x88
106 #define	MBX_READ_SPARM64		0x8D
107 #define	MBX_READ_RPI64			0x8F
108 #define	MBX_CONFIG_MSI			0x90
109 #define	MBX_REG_LOGIN64			0x93  /* SLI2/3 */
110 #define	MBX_REG_RPI			0x93  /* SLI4 */
111 #define	MBX_READ_LA64			0x95
112 #define	MBX_REG_VPI			0x96	/* NPIV */
113 #define	MBX_UNREG_VPI			0x97	/* NPIV */
114 #define	MBX_FLASH_WR_ULA		0x98
115 #define	MBX_SET_DEBUG			0x99
116 #define	MBX_SLI_CONFIG			0x9B
117 #define	MBX_LOAD_EXP_ROM		0x9C
118 #define	MBX_REQUEST_FEATURES		0x9D
119 #define	MBX_RESUME_RPI			0x9E
120 #define	MBX_REG_VFI			0x9F
121 #define	MBX_REG_FCFI			0xA0
122 #define	MBX_UNREG_VFI			0xA1
123 #define	MBX_UNREG_FCFI			0xA2
124 #define	MBX_INIT_VFI			0xA3
125 #define	MBX_INIT_VPI			0xA4
126 #define	MBX_ACCESS_VDATA		0xA5
127 #define	MBX_MAX_CMDS			0xA6
128 
129 
130 /*
131  * Define Status
132  */
133 #define	MBX_SUCCESS			0x0
134 #define	MBX_FAILURE			0x1
135 #define	MBXERR_NUM_IOCBS		0x2
136 #define	MBXERR_IOCBS_EXCEEDED		0x3
137 #define	MBXERR_BAD_RING_NUMBER		0x4
138 #define	MBXERR_MASK_ENTRIES_RANGE	0x5
139 #define	MBXERR_MASKS_EXCEEDED		0x6
140 #define	MBXERR_BAD_PROFILE		0x7
141 #define	MBXERR_BAD_DEF_CLASS		0x8
142 #define	MBXERR_BAD_MAX_RESPONDER	0x9
143 #define	MBXERR_BAD_MAX_ORIGINATOR	0xA
144 #define	MBXERR_RPI_REGISTERED		0xB
145 #define	MBXERR_RPI_FULL			0xC
146 #define	MBXERR_NO_RESOURCES		0xD
147 #define	MBXERR_BAD_RCV_LENGTH		0xE
148 #define	MBXERR_DMA_ERROR		0xF
149 #define	MBXERR_NOT_SUPPORTED		0x10
150 #define	MBXERR_UNSUPPORTED_FEATURE	0x11
151 #define	MBXERR_UNKNOWN_COMMAND		0x12
152 
153 /* Driver special codes */
154 #define	MBX_DRIVER_RESERVED		0xF9 /* Set to lowest drv status */
155 #define	MBX_NONEMBED_ERROR		0xF9
156 #define	MBX_OVERTEMP_ERROR		0xFA
157 #define	MBX_HARDWARE_ERROR		0xFB
158 #define	MBX_DRVR_ERROR			0xFC
159 #define	MBX_BUSY			0xFD
160 #define	MBX_TIMEOUT			0xFE
161 #define	MBX_NOT_FINISHED		0xFF
162 
163 /*
164  * flags for EMLXS_SLI_ISSUE_MBOX_CMD()
165  */
166 #define	MBX_POLL	0x01	/* poll mailbox till command done, */
167 				/* then return */
168 #define	MBX_SLEEP	0x02	/* sleep till mailbox intr cmpl */
169 				/* wakes thread up */
170 #define	MBX_WAIT	0x03	/* wait for comand done, then return */
171 #define	MBX_NOWAIT	0x04	/* issue command then return immediately */
172 #define	MBX_BOOTSTRAP	0x80	/* issue a command on the bootstrap mbox */
173 
174 
175 
176 /*
177  * Begin Structure Definitions for Mailbox Commands
178  */
179 
180 typedef struct revcompat
181 {
182 #ifdef EMLXS_BIG_ENDIAN
183 	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
184 	uint32_t	ldcount:7;	/* For use by program load */
185 	uint32_t	kernel:4;	/* Kernel ID */
186 	uint32_t	kver:4;	/* Kernel compatibility version */
187 	uint32_t	SMver:4;	/* Sequence Manager version */
188 					/* 0 if none */
189 	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
190 	uint32_t	BIUtype:4;	/* PCI = 0 */
191 	uint32_t	BIUver:4;	/* BIU version, 0 if none */
192 #endif
193 #ifdef EMLXS_LITTLE_ENDIAN
194 	uint32_t	BIUver:4;	/* BIU version, 0 if none */
195 	uint32_t	BIUtype:4;	/* PCI = 0 */
196 	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
197 	uint32_t	SMver:4;	/* Sequence Manager version */
198 					/* 0 if none */
199 	uint32_t	kver:4;	/* Kernel compatibility version */
200 	uint32_t	kernel:4;	/* Kernel ID */
201 	uint32_t	ldcount:7;	/* For use by program load */
202 	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
203 #endif
204 } REVCOMPAT;
205 
206 typedef struct id_word
207 {
208 #ifdef EMLXS_BIG_ENDIAN
209 	uint8_t		Type;
210 	uint8_t		Id;
211 	uint8_t		Ver;
212 	uint8_t		Rev;
213 #endif
214 #ifdef EMLXS_LITTLE_ENDIAN
215 	uint8_t		Rev;
216 	uint8_t		Ver;
217 	uint8_t		Id;
218 	uint8_t		Type;
219 #endif
220 	union
221 	{
222 		REVCOMPAT	cp;
223 		uint32_t	revcomp;
224 	} un;
225 } PROG_ID;
226 
227 typedef struct
228 {
229 #ifdef EMLXS_BIG_ENDIAN
230 	uint8_t		tval;
231 	uint8_t		tmask;
232 	uint8_t		rval;
233 	uint8_t		rmask;
234 #endif
235 #ifdef EMLXS_LITTLE_ENDIAN
236 	uint8_t		rmask;
237 	uint8_t		rval;
238 	uint8_t		tmask;
239 	uint8_t		tval;
240 #endif
241 } RR_REG;
242 
243 
244 /* Structure used for a HBQ entry */
245 typedef struct
246 {
247 	ULP_BDE64	bde;
248 	union UN_TAG
249 	{
250 		uint32_t	w;
251 		struct
252 		{
253 #ifdef EMLXS_BIG_ENDIAN
254 			uint32_t	HBQ_tag:4;
255 			uint32_t	HBQE_tag:28;
256 #endif
257 #ifdef EMLXS_LITTLE_ENDIAN
258 			uint32_t	HBQE_tag:28;
259 			uint32_t	HBQ_tag:4;
260 #endif
261 		} ext;
262 	} unt;
263 } HBQE_t;
264 
265 typedef struct
266 {
267 #ifdef EMLXS_BIG_ENDIAN
268 	uint8_t		tmatch;
269 	uint8_t		tmask;
270 	uint8_t		rctlmatch;
271 	uint8_t		rctlmask;
272 #endif
273 #ifdef EMLXS_LITTLE_ENDIAN
274 	uint8_t		rctlmask;
275 	uint8_t		rctlmatch;
276 	uint8_t		tmask;
277 	uint8_t		tmatch;
278 #endif
279 } HBQ_MASK;
280 
281 #define	EMLXS_MAX_HBQ_BUFFERS	4096
282 
283 typedef struct
284 {
285 	uint32_t	HBQ_num_mask;		/* number of mask entries in */
286 						/* port array */
287 	uint32_t	HBQ_recvNotify;		/* Rcv buffer notification */
288 	uint32_t	HBQ_numEntries;		/* # of entries in HBQ */
289 	uint32_t	HBQ_headerLen;		/* 0 if not profile 4 or 5 */
290 	uint32_t	HBQ_logEntry;		/* Set to 1 if this HBQ used */
291 						/* for LogEntry */
292 	uint32_t	HBQ_profile;		/* Selection profile 0=all, */
293 						/* 7=logentry */
294 	uint32_t	HBQ_ringMask;		/* Binds HBQ to a ring e.g. */
295 						/* Ring0=b0001, ring2=b0100 */
296 	uint32_t	HBQ_id;			/* index of this hbq in ring */
297 						/* of HBQs[] */
298 	uint32_t	HBQ_PutIdx_next;	/* Index to next HBQ slot to */
299 						/* use */
300 	uint32_t	HBQ_PutIdx;		/* HBQ slot to use */
301 	uint32_t	HBQ_GetIdx;		/* Local copy of Get index */
302 						/* from Port */
303 	uint16_t	HBQ_PostBufCnt;		/* Current number of entries */
304 						/* in list */
305 	MATCHMAP	*HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS];
306 	MATCHMAP	HBQ_host_buf;		/* HBQ host buffer for HBQEs */
307 	HBQ_MASK	HBQ_Masks[6];
308 
309 	union
310 	{
311 		uint32_t	allprofiles[12];
312 
313 		struct
314 		{
315 #ifdef EMLXS_BIG_ENDIAN
316 			uint32_t	seqlenoff:16;
317 			uint32_t	maxlen:16;
318 #endif
319 #ifdef EMLXS_LITTLE_ENDIAN
320 			uint32_t	maxlen:16;
321 			uint32_t	seqlenoff:16;
322 #endif
323 #ifdef EMLXS_BIG_ENDIAN
324 			uint32_t	rsvd1:28;
325 			uint32_t	seqlenbcnt:4;
326 #endif
327 #ifdef EMLXS_LITTLE_ENDIAN
328 			uint32_t	seqlenbcnt:4;
329 			uint32_t	rsvd1:28;
330 #endif
331 			uint32_t	rsvd[10];
332 		} profile2;
333 
334 		struct
335 		{
336 #ifdef EMLXS_BIG_ENDIAN
337 			uint32_t	seqlenoff:16;
338 			uint32_t	maxlen:16;
339 #endif
340 #ifdef EMLXS_LITTLE_ENDIAN
341 			uint32_t	maxlen:16;
342 			uint32_t	seqlenoff:16;
343 #endif
344 #ifdef EMLXS_BIG_ENDIAN
345 			uint32_t	cmdcodeoff:28;
346 			uint32_t	rsvd1:12;
347 			uint32_t	seqlenbcnt:4;
348 #endif
349 #ifdef EMLXS_LITTLE_ENDIAN
350 			uint32_t	seqlenbcnt:4;
351 			uint32_t	rsvd1:12;
352 			uint32_t	cmdcodeoff:28;
353 #endif
354 			uint32_t	cmdmatch[8];
355 
356 			uint32_t	rsvd[2];
357 		} profile3;
358 
359 		struct
360 		{
361 #ifdef EMLXS_BIG_ENDIAN
362 			uint32_t	seqlenoff:16;
363 			uint32_t	maxlen:16;
364 #endif
365 #ifdef EMLXS_LITTLE_ENDIAN
366 			uint32_t	maxlen:16;
367 			uint32_t	seqlenoff:16;
368 #endif
369 #ifdef EMLXS_BIG_ENDIAN
370 			uint32_t	cmdcodeoff:28;
371 			uint32_t	rsvd1:12;
372 			uint32_t	seqlenbcnt:4;
373 #endif
374 #ifdef EMLXS_LITTLE_ENDIAN
375 			uint32_t	seqlenbcnt:4;
376 			uint32_t	rsvd1:12;
377 			uint32_t	cmdcodeoff:28;
378 #endif
379 			uint32_t	cmdmatch[8];
380 
381 			uint32_t	rsvd[2];
382 		} profile5;
383 	} profiles;
384 } HBQ_INIT_t;
385 
386 
387 
388 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
389 
390 
391 typedef struct
392 {
393 #ifdef EMLXS_BIG_ENDIAN
394 	uint32_t	rsvd2:25;
395 	uint32_t	acknowledgment:1;
396 	uint32_t	version:1;
397 	uint32_t	erase_or_prog:1;
398 	uint32_t	update_flash:1;
399 	uint32_t	update_ram:1;
400 	uint32_t	method:1;
401 	uint32_t	load_cmplt:1;
402 #endif
403 #ifdef EMLXS_LITTLE_ENDIAN
404 	uint32_t	load_cmplt:1;
405 	uint32_t	method:1;
406 	uint32_t	update_ram:1;
407 	uint32_t	update_flash:1;
408 	uint32_t	erase_or_prog:1;
409 	uint32_t	version:1;
410 	uint32_t	acknowledgment:1;
411 	uint32_t	rsvd2:25;
412 #endif
413 
414 #define	DL_FROM_BDE	0	/* method */
415 #define	DL_FROM_SLIM	1
416 
417 #define	PROGRAM_FLASH	0	/* erase_or_prog */
418 #define	ERASE_FLASH	1
419 
420 	uint32_t	dl_to_adr;
421 	uint32_t	dl_len;
422 	union
423 	{
424 		uint32_t	dl_from_slim_offset;
425 		ULP_BDE		dl_from_bde;
426 		ULP_BDE64	dl_from_bde64;
427 		PROG_ID		prog_id;
428 	} un;
429 } LOAD_SM_VAR;
430 
431 
432 /* Structure for MB Command READ_NVPARM (02) */
433 /* Good for SLI2/3 and SLI4 */
434 
435 typedef struct
436 {
437 	uint32_t	rsvd1[3];	/* Read as all one's */
438 	uint32_t	rsvd2;		/* Read as all zero's */
439 	uint32_t	portname[2];	/* N_PORT name */
440 	uint32_t	nodename[2];	/* NODE name */
441 #ifdef EMLXS_BIG_ENDIAN
442 	uint32_t	pref_DID:24;
443 	uint32_t	hardAL_PA:8;
444 #endif
445 #ifdef EMLXS_LITTLE_ENDIAN
446 	uint32_t	hardAL_PA:8;
447 	uint32_t	pref_DID:24;
448 #endif
449 	uint32_t	rsvd3[21];	/* Read as all one's */
450 } READ_NV_VAR;
451 
452 
453 /* Structure for MB Command WRITE_NVPARMS (03) */
454 /* Good for SLI2/3 and SLI4 */
455 
456 typedef struct
457 {
458 	uint32_t	rsvd1[3];	/* Must be all one's */
459 	uint32_t	rsvd2;		/* Must be all zero's */
460 	uint32_t	portname[2];	/* N_PORT name */
461 	uint32_t	nodename[2];	/* NODE name */
462 #ifdef EMLXS_BIG_ENDIAN
463 	uint32_t	pref_DID:24;
464 	uint32_t	hardAL_PA:8;
465 #endif
466 #ifdef EMLXS_LITTLE_ENDIAN
467 	uint32_t	hardAL_PA:8;
468 	uint32_t	pref_DID:24;
469 #endif
470 	uint32_t	rsvd3[21];	/* Must be all one's */
471 } WRITE_NV_VAR;
472 
473 
474 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
475 /* Good for SLI2/3 and SLI4 */
476 
477 typedef struct
478 {
479 	uint32_t	rsvd1;
480 	union
481 	{
482 		struct
483 		{
484 			ULP_BDE64	xmit_bde64;
485 			ULP_BDE64	rcv_bde64;
486 		} s2;
487 	} un;
488 } BIU_DIAG_VAR;
489 
490 
491 /* Structure for MB Command INIT_LINK (05) */
492 /* Good for SLI2/3 and SLI4 */
493 
494 typedef struct
495 {
496 #ifdef EMLXS_BIG_ENDIAN
497 	uint32_t	rsvd1:24;
498 	uint32_t	lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective */
499 					/* Reset to */
500 #endif
501 #ifdef EMLXS_LITTLE_ENDIAN
502 	uint32_t	lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective */
503 					/* Reset to */
504 	uint32_t	rsvd1:24;
505 #endif
506 
507 #ifdef EMLXS_BIG_ENDIAN
508 	uint8_t		fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
509 	uint8_t		rsvd2;
510 	uint16_t	link_flags;
511 #endif
512 #ifdef EMLXS_LITTLE_ENDIAN
513 	uint16_t	link_flags;
514 	uint8_t		rsvd2;
515 	uint8_t		fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
516 #endif
517 #define	FLAGS_LOCAL_LB			0x01	/* link_flags (=1) */
518 						/* ENDEC loopback */
519 #define	FLAGS_TOPOLOGY_MODE_LOOP_PT	0x00	/* Attempt loop then pt-pt */
520 #define	FLAGS_TOPOLOGY_MODE_PT_PT	0x02	/* Attempt pt-pt only */
521 #define	FLAGS_TOPOLOGY_MODE_LOOP	0x04	/* Attempt loop only */
522 #define	FLAGS_TOPOLOGY_MODE_PT_LOOP	0x06	/* Attempt pt-pt then loop */
523 #define	FLAGS_LIRP_LILP			0x80	/* LIRP / LILP is disabled */
524 
525 #define	FLAGS_TOPOLOGY_FAILOVER		0x0400	/* Bit 10 */
526 #define	FLAGS_LINK_SPEED		0x0800	/* Bit 11 */
527 #define	FLAGS_PREABORT_RETURN		0x4000	/* Bit 14 */
528 
529 	uint32_t	link_speed;	/* NEW_FEATURE */
530 #define	LINK_SPEED_AUTO			0	/* Auto selection */
531 #define	LINK_SPEED_1G			1	/* 1 Gigabaud */
532 #define	LINK_SPEED_2G			2	/* 2 Gigabaud */
533 } INIT_LINK_VAR;
534 
535 
536 /* Structure for MB Command DOWN_LINK (06) */
537 /* Good for SLI2/3 and SLI4 */
538 
539 typedef struct
540 {
541 	uint32_t	rsvd1;
542 } DOWN_LINK_VAR;
543 
544 
545 /* Structure for MB Command CONFIG_LINK (07) */
546 
547 typedef struct
548 {
549 #ifdef EMLXS_BIG_ENDIAN
550 	uint32_t	cr:1;
551 	uint32_t	ci:1;
552 	uint32_t	cr_delay:6;
553 	uint32_t	cr_count:8;
554 	uint32_t	rsvd1:8;
555 	uint32_t	MaxBBC:8;
556 #endif
557 #ifdef EMLXS_LITTLE_ENDIAN
558 	uint32_t	MaxBBC:8;
559 	uint32_t	rsvd1:8;
560 	uint32_t	cr_count:8;
561 	uint32_t	cr_delay:6;
562 	uint32_t	ci:1;
563 	uint32_t	cr:1;
564 #endif
565 	uint32_t	myId;
566 	uint32_t	rsvd2;
567 	uint32_t	edtov;
568 	uint32_t	arbtov;
569 	uint32_t	ratov;
570 	uint32_t	rttov;
571 	uint32_t	altov;
572 	uint32_t	crtov;
573 	uint32_t	citov;
574 #ifdef EMLXS_BIG_ENDIAN
575 	uint32_t	rrq_enable:1;
576 	uint32_t	rrq_immed:1;
577 	uint32_t	rsvd4:29;
578 	uint32_t	ack0_enable:1;
579 #endif
580 #ifdef EMLXS_LITTLE_ENDIAN
581 	uint32_t	ack0_enable:1;
582 	uint32_t	rsvd4:29;
583 	uint32_t	rrq_immed:1;
584 	uint32_t	rrq_enable:1;
585 #endif
586 } CONFIG_LINK;
587 
588 
589 /* Structure for MB Command PART_SLIM (08) */
590 
591 typedef struct
592 {
593 #ifdef EMLXS_BIG_ENDIAN
594 	uint32_t		unused1:24;
595 	uint32_t		numRing:8;
596 #endif
597 #ifdef EMLXS_LITTLE_ENDIAN
598 	uint32_t		numRing:8;
599 	uint32_t		unused1:24;
600 #endif
601 	emlxs_ring_def_t	ringdef[4];
602 	uint32_t		hbainit;
603 } PART_SLIM_VAR;
604 
605 
606 /* Structure for MB Command CONFIG_RING (09) */
607 
608 typedef struct
609 {
610 #ifdef EMLXS_BIG_ENDIAN
611 	uint32_t	unused2:6;
612 	uint32_t	recvSeq:1;
613 	uint32_t	recvNotify:1;
614 	uint32_t	numMask:8;
615 	uint32_t	profile:8;
616 	uint32_t	unused1:4;
617 	uint32_t	ring:4;
618 #endif
619 #ifdef EMLXS_LITTLE_ENDIAN
620 	uint32_t	ring:4;
621 	uint32_t	unused1:4;
622 	uint32_t	profile:8;
623 	uint32_t	numMask:8;
624 	uint32_t	recvNotify:1;
625 	uint32_t	recvSeq:1;
626 	uint32_t	unused2:6;
627 #endif
628 #ifdef EMLXS_BIG_ENDIAN
629 	uint16_t	maxRespXchg;
630 	uint16_t	maxOrigXchg;
631 #endif
632 #ifdef EMLXS_LITTLE_ENDIAN
633 	uint16_t	maxOrigXchg;
634 	uint16_t	maxRespXchg;
635 #endif
636 	RR_REG		rrRegs[6];
637 } CONFIG_RING_VAR;
638 
639 
640 /* Structure for MB Command RESET_RING (10) */
641 
642 typedef struct
643 {
644 	uint32_t	ring_no;
645 } RESET_RING_VAR;
646 
647 
648 /* Structure for MB Command READ_CONFIG (11) */
649 /* Good for SLI2/3 only */
650 
651 typedef struct
652 {
653 #ifdef EMLXS_BIG_ENDIAN
654 	uint32_t	cr:1;
655 	uint32_t	ci:1;
656 	uint32_t	cr_delay:6;
657 	uint32_t	cr_count:8;
658 	uint32_t	InitBBC:8;
659 	uint32_t	MaxBBC:8;
660 #endif
661 #ifdef EMLXS_LITTLE_ENDIAN
662 	uint32_t	MaxBBC:8;
663 	uint32_t	InitBBC:8;
664 	uint32_t	cr_count:8;
665 	uint32_t	cr_delay:6;
666 	uint32_t	ci:1;
667 	uint32_t	cr:1;
668 #endif
669 #ifdef EMLXS_BIG_ENDIAN
670 	uint32_t	topology:8;
671 	uint32_t	myDid:24;
672 #endif
673 #ifdef EMLXS_LITTLE_ENDIAN
674 	uint32_t	myDid:24;
675 	uint32_t	topology:8;
676 #endif
677 	/* Defines for topology (defined previously) */
678 #ifdef EMLXS_BIG_ENDIAN
679 	uint32_t	AR:1;
680 	uint32_t	IR:1;
681 	uint32_t	rsvd1:29;
682 	uint32_t	ack0:1;
683 #endif
684 #ifdef EMLXS_LITTLE_ENDIAN
685 	uint32_t	ack0:1;
686 	uint32_t	rsvd1:29;
687 	uint32_t	IR:1;
688 	uint32_t	AR:1;
689 #endif
690 	uint32_t	edtov;
691 	uint32_t	arbtov;
692 	uint32_t	ratov;
693 	uint32_t	rttov;
694 	uint32_t	altov;
695 	uint32_t	lmt;
696 
697 #define	LMT_1GB_CAPABLE		0x0004
698 #define	LMT_2GB_CAPABLE		0x0008
699 #define	LMT_4GB_CAPABLE		0x0040
700 #define	LMT_8GB_CAPABLE		0x0080
701 #define	LMT_10GB_CAPABLE	0x0100
702 /* E2E supported on adapters >= 8GB */
703 #define	LMT_E2E_CAPABLE		(LMT_8GB_CAPABLE|LMT_10GB_CAPABLE)
704 
705 	uint32_t	rsvd2;
706 	uint32_t	rsvd3;
707 	uint32_t	max_xri;
708 	uint32_t	max_iocb;
709 	uint32_t	max_rpi;
710 	uint32_t	avail_xri;
711 	uint32_t	avail_iocb;
712 	uint32_t	avail_rpi;
713 	uint32_t	max_vpi;
714 	uint32_t	max_alpa;
715 	uint32_t	rsvd4;
716 	uint32_t	avail_vpi;
717 
718 } READ_CONFIG_VAR;
719 
720 
721 /* Structure for MB Command READ_CONFIG(0x11) */
722 /* Good for SLI4 only */
723 
724 typedef struct
725 {
726 	uint32_t	rsvd1;		/* Word 1 */
727 #ifdef EMLXS_BIG_ENDIAN
728 	uint32_t	topology:8;
729 	uint32_t	rsvd2:24;	/* Word 2 */
730 #endif
731 #ifdef EMLXS_LITTLE_ENDIAN
732 	uint32_t	rsvd2:24;	/* Word 2 */
733 	uint32_t	topology:8;
734 #endif
735 	uint32_t	rsvd3;		/* Word 3 */
736 	uint32_t	edtov;		/* Word 4 */
737 	uint32_t	rsvd4;		/* Word 5 */
738 	uint32_t	ratov;		/* Word 6 */
739 	uint32_t	rsvd5;		/* Word 7 */
740 	uint32_t	rsvd6;		/* Word 8 */
741 	uint32_t	lmt;		/* Word 9 */
742 	uint32_t	rsvd8;		/* Word 10 */
743 	uint32_t	rsvd9;		/* Word 11 */
744 
745 #ifdef EMLXS_BIG_ENDIAN
746 	uint16_t	XRICount;	/* Word 12 */
747 	uint16_t	XRIBase;	/* Word 12 */
748 
749 	uint16_t	RPICount;	/* Word 13 */
750 	uint16_t	RPIBase;	/* Word 13 */
751 
752 	uint16_t	VPICount;	/* Word 14 */
753 	uint16_t	VPIBase;	/* Word 14 */
754 
755 	uint16_t	VFICount;	/* Word 15 */
756 	uint16_t	VFIBase;	/* Word 15 */
757 
758 	uint16_t	FCFICount;	/* Word 16 */
759 	uint16_t	rsvd10;		/* Word 16 */
760 
761 	uint16_t	EQCount;	/* Word 17 */
762 	uint16_t	RQCount;	/* Word 17 */
763 
764 	uint16_t	CQCount;	/* Word 18 */
765 	uint16_t	WQCount;	/* Word 18 */
766 #endif
767 #ifdef EMLXS_LITTLE_ENDIAN
768 	uint16_t	XRIBase;	/* Word 12 */
769 	uint16_t	XRICount;	/* Word 12 */
770 
771 	uint16_t	RPIBase;	/* Word 13 */
772 	uint16_t	RPICount;	/* Word 13 */
773 
774 	uint16_t	VPIBase;	/* Word 14 */
775 	uint16_t	VPICount;	/* Word 14 */
776 
777 	uint16_t	VFIBase;	/* Word 15 */
778 	uint16_t	VFICount;	/* Word 15 */
779 
780 	uint16_t	rsvd10;		/* Word 16 */
781 	uint16_t	FCFICount;	/* Word 16 */
782 
783 	uint16_t	EQCount;	/* Word 17 */
784 	uint16_t	RQCount;	/* Word 17 */
785 
786 	uint16_t	CQCount;	/* Word 18 */
787 	uint16_t	WQCount;	/* Word 18 */
788 #endif
789 
790 } READ_CONFIG4_VAR;
791 
792 /* Structure for MB Command READ_RCONFIG (12) */
793 
794 typedef struct
795 {
796 #ifdef EMLXS_BIG_ENDIAN
797 	uint32_t	rsvd2:7;
798 	uint32_t	recvNotify:1;
799 	uint32_t	numMask:8;
800 	uint32_t	profile:8;
801 	uint32_t	rsvd1:4;
802 	uint32_t	ring:4;
803 #endif
804 #ifdef EMLXS_LITTLE_ENDIAN
805 	uint32_t	ring:4;
806 	uint32_t	rsvd1:4;
807 	uint32_t	profile:8;
808 	uint32_t	numMask:8;
809 	uint32_t	recvNotify:1;
810 	uint32_t	rsvd2:7;
811 #endif
812 #ifdef EMLXS_BIG_ENDIAN
813 	uint16_t	maxResp;
814 	uint16_t	maxOrig;
815 #endif
816 #ifdef EMLXS_LITTLE_ENDIAN
817 	uint16_t	maxOrig;
818 	uint16_t	maxResp;
819 #endif
820 	RR_REG		rrRegs[6];
821 #ifdef EMLXS_BIG_ENDIAN
822 	uint16_t	cmdRingOffset;
823 	uint16_t	cmdEntryCnt;
824 	uint16_t	rspRingOffset;
825 	uint16_t	rspEntryCnt;
826 	uint16_t	nextCmdOffset;
827 	uint16_t	rsvd3;
828 	uint16_t	nextRspOffset;
829 	uint16_t	rsvd4;
830 #endif
831 #ifdef EMLXS_LITTLE_ENDIAN
832 	uint16_t	cmdEntryCnt;
833 	uint16_t	cmdRingOffset;
834 	uint16_t	rspEntryCnt;
835 	uint16_t	rspRingOffset;
836 	uint16_t	rsvd3;
837 	uint16_t	nextCmdOffset;
838 	uint16_t	rsvd4;
839 	uint16_t	nextRspOffset;
840 #endif
841 } READ_RCONF_VAR;
842 
843 
844 /* Structure for MB Command READ_SPARM (13) */
845 /* Structure for MB Command READ_SPARM64 (0x8D) */
846 /* Good for SLI2/3 and SLI4 */
847 
848 typedef struct
849 {
850 	uint32_t	rsvd1;
851 	uint32_t	rsvd2;
852 	union
853 	{
854 		ULP_BDE		sp;	/* This BDE points to SERV_PARM */
855 					/* structure */
856 		ULP_BDE64	sp64;
857 	} un;
858 	uint32_t	rsvd3;
859 
860 #ifdef EMLXS_BIG_ENDIAN
861 	uint16_t	portNameCnt;
862 	uint16_t	portNameOffset;
863 
864 	uint16_t	fabricNameCnt;
865 	uint16_t	fabricNameOffset;
866 
867 	uint16_t	lportNameCnt;
868 	uint16_t	lportNameOffset;
869 
870 	uint16_t	lfabricNameCnt;
871 	uint16_t	lfabricNameOffset;
872 
873 #endif
874 #ifdef EMLXS_LITTLE_ENDIAN
875 	uint16_t	portNameOffset;
876 	uint16_t	portNameCnt;
877 
878 	uint16_t	fabricNameOffset;
879 	uint16_t	fabricNameCnt;
880 
881 	uint16_t	lportNameOffset;
882 	uint16_t	lportNameCnt;
883 
884 	uint16_t	lfabricNameOffset;
885 	uint16_t	lfabricNameCnt;
886 
887 #endif
888 
889 } READ_SPARM_VAR;
890 
891 
892 /* Structure for MB Command READ_STATUS (14) */
893 /* Good for SLI2/3 and SLI4 */
894 
895 typedef struct
896 {
897 #ifdef EMLXS_BIG_ENDIAN
898 	uint32_t	rsvd1:31;
899 	uint32_t	clrCounters:1;
900 
901 	uint16_t	activeXriCnt;
902 	uint16_t	activeRpiCnt;
903 #endif
904 #ifdef EMLXS_LITTLE_ENDIAN
905 	uint32_t	clrCounters:1;
906 	uint32_t	rsvd1:31;
907 
908 	uint16_t	activeRpiCnt;
909 	uint16_t	activeXriCnt;
910 #endif
911 	uint32_t	xmitByteCnt;
912 	uint32_t	rcvByteCnt;
913 	uint32_t	xmitFrameCnt;
914 	uint32_t	rcvFrameCnt;
915 	uint32_t	xmitSeqCnt;
916 	uint32_t	rcvSeqCnt;
917 	uint32_t	totalOrigExchanges;
918 	uint32_t	totalRespExchanges;
919 	uint32_t	rcvPbsyCnt;
920 	uint32_t	rcvFbsyCnt;
921 } READ_STATUS_VAR;
922 
923 
924 /* Structure for MB Command READ_RPI (15) */
925 /* Structure for MB Command READ_RPI64 (0x8F) */
926 
927 typedef struct
928 {
929 #ifdef EMLXS_BIG_ENDIAN
930 	uint16_t	nextRpi;
931 	uint16_t	reqRpi;
932 	uint32_t	rsvd2:8;
933 	uint32_t	DID:24;
934 #endif
935 #ifdef EMLXS_LITTLE_ENDIAN
936 	uint16_t	reqRpi;
937 	uint16_t	nextRpi;
938 	uint32_t	DID:24;
939 	uint32_t	rsvd2:8;
940 #endif
941 	union
942 	{
943 		ULP_BDE		sp;
944 		ULP_BDE64	sp64;
945 	} un;
946 } READ_RPI_VAR;
947 
948 
949 /* Structure for MB Command READ_XRI (16) */
950 
951 typedef struct
952 {
953 #ifdef EMLXS_BIG_ENDIAN
954 	uint16_t	nextXri;
955 	uint16_t	reqXri;
956 	uint16_t	rsvd1;
957 	uint16_t	rpi;
958 	uint32_t	rsvd2:8;
959 	uint32_t	DID:24;
960 	uint32_t	rsvd3:8;
961 	uint32_t	SID:24;
962 	uint32_t	rsvd4;
963 	uint8_t		seqId;
964 	uint8_t		rsvd5;
965 	uint16_t	seqCount;
966 	uint16_t	oxId;
967 	uint16_t	rxId;
968 	uint32_t	rsvd6:30;
969 	uint32_t	si:1;
970 	uint32_t	exchOrig:1;
971 #endif
972 #ifdef EMLXS_LITTLE_ENDIAN
973 	uint16_t	reqXri;
974 	uint16_t	nextXri;
975 	uint16_t	rpi;
976 	uint16_t	rsvd1;
977 	uint32_t	DID:24;
978 	uint32_t	rsvd2:8;
979 	uint32_t	SID:24;
980 	uint32_t	rsvd3:8;
981 	uint32_t	rsvd4;
982 	uint16_t	seqCount;
983 	uint8_t		rsvd5;
984 	uint8_t		seqId;
985 	uint16_t	rxId;
986 	uint16_t	oxId;
987 	uint32_t	exchOrig:1;
988 	uint32_t	si:1;
989 	uint32_t	rsvd6:30;
990 #endif
991 } READ_XRI_VAR;
992 
993 
994 /* Structure for MB Command READ_REV (17) */
995 /* Good for SLI2/3 only */
996 
997 typedef struct
998 {
999 #ifdef EMLXS_BIG_ENDIAN
1000 	uint32_t	cv:1;
1001 	uint32_t	rr:1;
1002 	uint32_t	co:1;
1003 	uint32_t	rp:1;
1004 	uint32_t	cv3:1;
1005 	uint32_t	rf3:1;
1006 	uint32_t	rsvd1:10;
1007 	uint32_t	offset:14;
1008 	uint32_t	rv:2;
1009 #endif
1010 #ifdef EMLXS_LITTLE_ENDIAN
1011 	uint32_t	rv:2;
1012 	uint32_t	offset:14;
1013 	uint32_t	rsvd1:10;
1014 	uint32_t	rf3:1;
1015 	uint32_t	cv3:1;
1016 	uint32_t	rp:1;
1017 	uint32_t	co:1;
1018 	uint32_t	rr:1;
1019 	uint32_t	cv:1;
1020 #endif
1021 	uint32_t	biuRev;
1022 	uint32_t	smRev;
1023 	union
1024 	{
1025 		uint32_t	smFwRev;
1026 		struct
1027 		{
1028 #ifdef EMLXS_BIG_ENDIAN
1029 			uint8_t		ProgType;
1030 			uint8_t		ProgId;
1031 			uint16_t	ProgVer:4;
1032 			uint16_t	ProgRev:4;
1033 			uint16_t	ProgFixLvl:2;
1034 			uint16_t	ProgDistType:2;
1035 			uint16_t	DistCnt:4;
1036 #endif
1037 #ifdef EMLXS_LITTLE_ENDIAN
1038 			uint16_t	DistCnt:4;
1039 			uint16_t	ProgDistType:2;
1040 			uint16_t	ProgFixLvl:2;
1041 			uint16_t	ProgRev:4;
1042 			uint16_t	ProgVer:4;
1043 			uint8_t		ProgId;
1044 			uint8_t		ProgType;
1045 #endif
1046 		} b;
1047 	} un;
1048 	uint32_t	endecRev;
1049 #ifdef EMLXS_BIG_ENDIAN
1050 	uint8_t		feaLevelHigh;
1051 	uint8_t		feaLevelLow;
1052 	uint8_t		fcphHigh;
1053 	uint8_t		fcphLow;
1054 #endif
1055 #ifdef EMLXS_LITTLE_ENDIAN
1056 	uint8_t		fcphLow;
1057 	uint8_t		fcphHigh;
1058 	uint8_t		feaLevelLow;
1059 	uint8_t		feaLevelHigh;
1060 #endif
1061 	uint32_t	postKernRev;
1062 	uint32_t	opFwRev;
1063 	uint8_t		opFwName[16];
1064 
1065 	uint32_t	sliFwRev1;
1066 	uint8_t		sliFwName1[16];
1067 	uint32_t	sliFwRev2;
1068 	uint8_t		sliFwName2[16];
1069 } READ_REV_VAR;
1070 
1071 /* Structure for MB Command READ_REV (17) */
1072 /* Good for SLI4 only */
1073 
1074 typedef struct
1075 {
1076 #ifdef EMLXS_BIG_ENDIAN
1077 	uint32_t	Rsvd3:2;
1078 	uint32_t	VPD:1;
1079 	uint32_t	rsvd2:6;
1080 	uint32_t	dcbxMode:2;
1081 	uint32_t	FCoE:1;
1082 	uint32_t	sliLevel:4;
1083 	uint32_t	rsvd1:16;
1084 #endif
1085 #ifdef EMLXS_LITTLE_ENDIAN
1086 	uint32_t	rsvd1:16;
1087 	uint32_t	sliLevel:4;
1088 	uint32_t	FCoE:1;
1089 	uint32_t	dcbxMode:2;
1090 	uint32_t	rsvd2:6;
1091 	uint32_t	VPD:1;
1092 	uint32_t	Rsvd3:2;
1093 #endif
1094 
1095 	uint32_t	HwRev1;
1096 	uint32_t	HwRev2;
1097 	uint32_t	Rsvd4;
1098 	uint32_t	HwRev3;
1099 
1100 #ifdef EMLXS_BIG_ENDIAN
1101 	uint8_t		feaLevelHigh;
1102 	uint8_t		feaLevelLow;
1103 	uint8_t		fcphHigh;
1104 	uint8_t		fcphLow;
1105 #endif
1106 #ifdef EMLXS_LITTLE_ENDIAN
1107 	uint8_t		fcphLow;
1108 	uint8_t		fcphHigh;
1109 	uint8_t		feaLevelLow;
1110 	uint8_t		feaLevelHigh;
1111 #endif
1112 
1113 	uint32_t	Redboot;
1114 
1115 	uint32_t	ARMFwId;
1116 	uint8_t		ARMFwName[16];
1117 
1118 	uint32_t	ULPFwId;
1119 	uint8_t		ULPFwName[16];
1120 
1121 	uint32_t	Rsvd6[30];
1122 
1123 	ULP_BDE64	VPDBde;
1124 
1125 	uint32_t	ReturnedVPDLength;
1126 
1127 } READ_REV4_VAR;
1128 
1129 #define	EMLXS_DCBX_MODE_CIN	0	/* Mapped to nonFIP mode */
1130 #define	EMLXS_DCBX_MODE_CEE	1	/* Mapped to FIP mode */
1131 
1132 /* Structure for MB Command READ_LINK_STAT (18) */
1133 /* Good for SLI2/3 and SLI4 */
1134 
1135 typedef struct
1136 {
1137 	uint32_t	rsvd1;
1138 	uint32_t	linkFailureCnt;
1139 	uint32_t	lossSyncCnt;
1140 
1141 	uint32_t	lossSignalCnt;
1142 	uint32_t	primSeqErrCnt;
1143 	uint32_t	invalidXmitWord;
1144 	uint32_t	crcCnt;
1145 	uint32_t	primSeqTimeout;
1146 	uint32_t	elasticOverrun;
1147 	uint32_t	arbTimeout;
1148 
1149 	uint32_t	rxBufCredit;
1150 	uint32_t	rxBufCreditCur;
1151 
1152 	uint32_t	txBufCredit;
1153 	uint32_t	txBufCreditCur;
1154 
1155 	uint32_t	EOFaCnt;
1156 	uint32_t	EOFdtiCnt;
1157 	uint32_t	EOFniCnt;
1158 	uint32_t	SOFfCnt;
1159 	uint32_t	DropAERCnt;
1160 	uint32_t	DropRcv;
1161 } READ_LNK_VAR;
1162 
1163 
1164 /* Structure for MB Command REG_LOGIN (19) */
1165 /* Structure for MB Command REG_LOGIN64 (0x93) */
1166 /* Structure for MB Command REG_RPI (0x93) */
1167 /* Good for SLI2/3 and SLI4 */
1168 
1169 typedef struct
1170 {
1171 #ifdef EMLXS_BIG_ENDIAN
1172 	uint16_t	rsvd1;
1173 	uint16_t	rpi;
1174 	uint32_t	CI:1;
1175 	uint32_t	rsvd2:7;
1176 	uint32_t	did:24;
1177 #endif
1178 #ifdef EMLXS_LITTLE_ENDIAN
1179 	uint16_t	rpi;
1180 	uint16_t	rsvd1;
1181 	uint32_t	did:24;
1182 	uint32_t	rsvd2:7;
1183 	uint32_t	CI:1;
1184 #endif
1185 	union
1186 	{
1187 		ULP_BDE		sp;
1188 		ULP_BDE64	sp64;
1189 	} un;
1190 
1191 #ifdef EMLXS_BIG_ENDIAN
1192 	uint16_t	rsvd6;
1193 	uint16_t	vpi;
1194 #endif
1195 #ifdef EMLXS_LITTLE_ENDIAN
1196 	uint16_t	vpi;
1197 	uint16_t	rsvd6;
1198 #endif
1199 } REG_LOGIN_VAR;
1200 
1201 /* Word 30 contents for REG_LOGIN */
1202 typedef union
1203 {
1204 	struct
1205 	{
1206 #ifdef EMLXS_BIG_ENDIAN
1207 		uint16_t	rsvd1:12;
1208 		uint16_t	class:4;
1209 		uint16_t	xri;
1210 #endif
1211 #ifdef EMLXS_LITTLE_ENDIAN
1212 		uint16_t	xri;
1213 		uint16_t	class:4;
1214 		uint16_t	rsvd1:12;
1215 #endif
1216 	} f;
1217 	uint32_t	word;
1218 } REG_WD30;
1219 
1220 
1221 /* Structure for MB Command UNREG_LOGIN (0x14) - SLI2/3 */
1222 /* Structure for MB Command UNREG_RPI (0x14) - SLI4 */
1223 
1224 typedef struct
1225 {
1226 #ifdef EMLXS_BIG_ENDIAN
1227 	uint16_t	ll:2;		/* SLI4 only */
1228 	uint16_t	rsvd1:14;
1229 	uint16_t	rpi;
1230 #endif
1231 #ifdef EMLXS_LITTLE_ENDIAN
1232 	uint16_t	rpi;
1233 	uint16_t	rsvd1:14;
1234 	uint16_t	ll:2;		/* SLI4 only */
1235 #endif
1236 
1237 	uint32_t	rsvd2;
1238 	uint32_t	rsvd3;
1239 	uint32_t	rsvd4;
1240 	uint32_t	rsvd5;
1241 #ifdef EMLXS_BIG_ENDIAN
1242 	uint16_t	rsvd6;
1243 	uint16_t	vpi;
1244 #endif
1245 #ifdef EMLXS_LITTLE_ENDIAN
1246 	uint16_t	vpi;
1247 	uint16_t	rsvd6;
1248 #endif
1249 } UNREG_LOGIN_VAR;
1250 
1251 /* Structure for MB Command REG_FCFI (0xA0) */
1252 /* Good for SLI4 only */
1253 
1254 typedef struct
1255 {
1256 #ifdef EMLXS_BIG_ENDIAN
1257 	uint16_t	FCFI;
1258 	uint16_t	InfoIndex;
1259 
1260 	uint16_t	RQId0;
1261 	uint16_t	RQId1;
1262 	uint16_t	RQId2;
1263 	uint16_t	RQId3;
1264 
1265 	uint8_t		Id0_type;
1266 	uint8_t		Id0_type_mask;
1267 	uint8_t		Id0_rctl;
1268 	uint8_t		Id0_rctl_mask;
1269 
1270 	uint8_t		Id1_type;
1271 	uint8_t		Id1_type_mask;
1272 	uint8_t		Id1_rctl;
1273 	uint8_t		Id1_rctl_mask;
1274 
1275 	uint8_t		Id2_type;
1276 	uint8_t		Id2_type_mask;
1277 	uint8_t		Id2_rctl;
1278 	uint8_t		Id2_rctl_mask;
1279 
1280 	uint8_t		Id3_type;
1281 	uint8_t		Id3_type_mask;
1282 	uint8_t		Id3_rctl;
1283 	uint8_t		Id3_rctl_mask;
1284 
1285 	uint32_t	Rsvd1: 17;
1286 	uint32_t	mam: 2;
1287 	uint32_t	vv: 1;
1288 	uint32_t	vlanTag: 12;
1289 #endif
1290 #ifdef EMLXS_LITTLE_ENDIAN
1291 	uint16_t	InfoIndex;
1292 	uint16_t	FCFI;
1293 
1294 	uint16_t	RQId1;
1295 	uint16_t	RQId0;
1296 	uint16_t	RQId3;
1297 	uint16_t	RQId2;
1298 
1299 	uint8_t		Id0_rctl_mask;
1300 	uint8_t		Id0_rctl;
1301 	uint8_t		Id0_type_mask;
1302 	uint8_t		Id0_type;
1303 
1304 	uint8_t		Id1_rctl_mask;
1305 	uint8_t		Id1_rctl;
1306 	uint8_t		Id1_type_mask;
1307 	uint8_t		Id1_type;
1308 
1309 	uint8_t		Id2_rctl_mask;
1310 	uint8_t		Id2_rctl;
1311 	uint8_t		Id2_type_mask;
1312 	uint8_t		Id2_type;
1313 
1314 	uint8_t		Id3_rctl_mask;
1315 	uint8_t		Id3_rctl;
1316 	uint8_t		Id3_type_mask;
1317 	uint8_t		Id3_type;
1318 
1319 	uint32_t	vlanTag: 12;
1320 	uint32_t	vv: 1;
1321 	uint32_t	mam: 2;
1322 	uint32_t	Rsvd1: 17;
1323 #endif
1324 
1325 }  REG_FCFI_VAR;
1326 
1327 /* Defines for mam */
1328 #define	EMLXS_REG_FCFI_MAM_SPMA	1	/* Server Provided MAC Address */
1329 #define	EMLXS_REG_FCFI_MAM_FPMA	2	/* Fabric Provided MAC Address */
1330 
1331 /* Structure for MB Command UNREG_FCFI (0xA2) */
1332 /* Good for SLI4 only */
1333 
1334 typedef struct
1335 {
1336 	uint32_t	Rsvd1;
1337 #ifdef EMLXS_BIG_ENDIAN
1338 	uint16_t	Rsvd2;
1339 	uint16_t	FCFI;
1340 #endif
1341 #ifdef EMLXS_LITTLE_ENDIAN
1342 	uint16_t	FCFI;
1343 	uint16_t	Rsvd2;
1344 #endif
1345 }  UNREG_FCFI_VAR;
1346 
1347 /* Structure for MB Command RESUME_RPI (0x9E) */
1348 /* Good for SLI4 only */
1349 
1350 typedef struct
1351 {
1352 #ifdef EMLXS_BIG_ENDIAN
1353 	uint16_t	Rsvd1;
1354 	uint16_t	RPI;
1355 
1356 	uint32_t	EventTag;
1357 	uint32_t	rsvd2[3];
1358 
1359 	uint16_t	VFI;
1360 	uint16_t	VPI;
1361 #endif
1362 #ifdef EMLXS_LITTLE_ENDIAN
1363 	uint16_t	RPI;
1364 	uint16_t	Rsvd1;
1365 
1366 	uint32_t	EventTag;
1367 	uint32_t	rsvd2[3];
1368 
1369 	uint16_t	VPI;
1370 	uint16_t	VFI;
1371 #endif
1372 
1373 }  RESUME_RPI_VAR;
1374 
1375 
1376 /* Structure for MB Command UNREG_D_ID (0x23) */
1377 
1378 typedef struct
1379 {
1380 	uint32_t	did;
1381 
1382 	uint32_t	rsvd2;
1383 	uint32_t	rsvd3;
1384 	uint32_t	rsvd4;
1385 	uint32_t	rsvd5;
1386 #ifdef EMLXS_BIG_ENDIAN
1387 	uint16_t	rsvd6;
1388 	uint16_t	vpi;
1389 #endif
1390 #ifdef EMLXS_LITTLE_ENDIAN
1391 	uint16_t	vpi;
1392 	uint16_t	rsvd6;
1393 #endif
1394 } UNREG_D_ID_VAR;
1395 
1396 
1397 /* Structure for MB Command READ_LA (21) */
1398 /* Structure for MB Command READ_LA64 (0x95) */
1399 
1400 typedef struct
1401 {
1402 	uint32_t	eventTag;	/* Event tag */
1403 #ifdef EMLXS_BIG_ENDIAN
1404 	uint32_t	rsvd2:19;
1405 	uint32_t	fa:1;
1406 	uint32_t	mm:1;
1407 	uint32_t	tc:1;
1408 	uint32_t	pb:1;
1409 	uint32_t	il:1;
1410 	uint32_t	attType:8;
1411 #endif
1412 #ifdef EMLXS_LITTLE_ENDIAN
1413 	uint32_t	attType:8;
1414 	uint32_t	il:1;
1415 	uint32_t	pb:1;
1416 	uint32_t	tc:1;
1417 	uint32_t	mm:1;
1418 	uint32_t	fa:1;
1419 	uint32_t	rsvd2:19;
1420 #endif
1421 #define	AT_RESERVED	0x00	/* Reserved - attType */
1422 #define	AT_LINK_UP	0x01	/* Link is up */
1423 #define	AT_LINK_DOWN	0x02	/* Link is down */
1424 #ifdef EMLXS_BIG_ENDIAN
1425 	uint8_t		granted_AL_PA;
1426 	uint8_t		lipAlPs;
1427 	uint8_t		lipType;
1428 	uint8_t		topology;
1429 #endif
1430 #ifdef EMLXS_LITTLE_ENDIAN
1431 	uint8_t		topology;
1432 	uint8_t		lipType;
1433 	uint8_t		lipAlPs;
1434 	uint8_t		granted_AL_PA;
1435 #endif
1436 
1437 	/* lipType */
1438 #define	LT_PORT_INIT	0x00	/* An L_PORT initing (F7, AL_PS) - lipType */
1439 #define	LT_PORT_ERR	0x01	/* Err @L_PORT rcv'er (F8, AL_PS) */
1440 #define	LT_RESET_APORT	0x02	/* Lip Reset of some other port */
1441 #define	LT_RESET_MYPORT	0x03	/* Lip Reset of my port */
1442 
1443 	/* topology */
1444 #define	TOPOLOGY_PT_PT	0x01	/* Topology is pt-pt / pt-fabric */
1445 #define	TOPOLOGY_LOOP	0x02	/* Topology is FC-AL (private) */
1446 
1447 	union
1448 	{
1449 		ULP_BDE		lilpBde;	/* This BDE points to a */
1450 						/* 128 byte buffer to store */
1451 						/* the LILP AL_PA position */
1452 						/* map into */
1453 		ULP_BDE64	lilpBde64;
1454 	} un;
1455 #ifdef EMLXS_BIG_ENDIAN
1456 	uint32_t	Dlu:1;
1457 	uint32_t	Dtf:1;
1458 	uint32_t	Drsvd2:14;
1459 	uint32_t	DlnkSpeed:8;
1460 	uint32_t	DnlPort:4;
1461 	uint32_t	Dtx:2;
1462 	uint32_t	Drx:2;
1463 #endif
1464 #ifdef EMLXS_LITTLE_ENDIAN
1465 	uint32_t	Drx:2;
1466 	uint32_t	Dtx:2;
1467 	uint32_t	DnlPort:4;
1468 	uint32_t	DlnkSpeed:8;
1469 	uint32_t	Drsvd2:14;
1470 	uint32_t	Dtf:1;
1471 	uint32_t	Dlu:1;
1472 #endif
1473 #ifdef EMLXS_BIG_ENDIAN
1474 	uint32_t	Ulu:1;
1475 	uint32_t	Utf:1;
1476 	uint32_t	Ursvd2:14;
1477 	uint32_t	UlnkSpeed:8;
1478 	uint32_t	UnlPort:4;
1479 	uint32_t	Utx:2;
1480 	uint32_t	Urx:2;
1481 #endif
1482 #ifdef EMLXS_LITTLE_ENDIAN
1483 	uint32_t	Urx:2;
1484 	uint32_t	Utx:2;
1485 	uint32_t	UnlPort:4;
1486 	uint32_t	UlnkSpeed:8;
1487 	uint32_t	Ursvd2:14;
1488 	uint32_t	Utf:1;
1489 	uint32_t	Ulu:1;
1490 #endif
1491 
1492 #define	LA_1GHZ_LINK   0x04	/* lnkSpeed */
1493 #define	LA_2GHZ_LINK   0x08	/* lnkSpeed */
1494 #define	LA_4GHZ_LINK   0x10	/* lnkSpeed */
1495 #define	LA_8GHZ_LINK   0x20	/* lnkSpeed */
1496 #define	LA_10GHZ_LINK  0x40	/* lnkSpeed */
1497 } READ_LA_VAR;
1498 
1499 
1500 /* Structure for MB Command CLEAR_LA (22) */
1501 
1502 typedef struct
1503 {
1504 	uint32_t	eventTag;	/* Event tag */
1505 	uint32_t	rsvd1;
1506 } CLEAR_LA_VAR;
1507 
1508 /* Structure for MB Command DUMP */
1509 /* Good for SLI2/3 only */
1510 
1511 typedef struct
1512 {
1513 #ifdef EMLXS_BIG_ENDIAN
1514 	uint32_t	rsvd:25;
1515 	uint32_t	ra:1;
1516 	uint32_t	co:1;
1517 	uint32_t	cv:1;
1518 	uint32_t	type:4;
1519 
1520 	uint32_t	entry_index:16;
1521 	uint32_t	region_id:16;
1522 #endif
1523 #ifdef EMLXS_LITTLE_ENDIAN
1524 	uint32_t	type:4;
1525 	uint32_t	cv:1;
1526 	uint32_t	co:1;
1527 	uint32_t	ra:1;
1528 	uint32_t	rsvd:25;
1529 
1530 	uint32_t	region_id:16;
1531 	uint32_t	entry_index:16;
1532 #endif
1533 	uint32_t	base_adr;
1534 	uint32_t	word_cnt;
1535 	uint32_t	resp_offset;
1536 } DUMP_VAR;
1537 
1538 /* Structure for MB Command DUMP */
1539 /* Good for SLI4 only */
1540 
1541 typedef struct
1542 {
1543 #ifdef EMLXS_BIG_ENDIAN
1544 	uint32_t	ppi:4;
1545 	uint32_t	phy_index:4;
1546 	uint32_t	rsvd:20;
1547 	uint32_t	type:4;
1548 
1549 	uint32_t	entry_index:16;
1550 	uint32_t	region_id:16;
1551 #endif
1552 #ifdef EMLXS_LITTLE_ENDIAN
1553 	uint32_t	type:4;
1554 	uint32_t	rsvd:20;
1555 	uint32_t	phy_index:4;
1556 	uint32_t	ppi:4;
1557 
1558 	uint32_t	region_id:16;
1559 	uint32_t	entry_index:16;
1560 #endif
1561 	uint32_t	available_cnt;
1562 	uint32_t	addrLow;
1563 	uint32_t	addrHigh;
1564 	uint32_t	rsp_cnt;
1565 } DUMP4_VAR;
1566 
1567 /*
1568  * Dump type
1569  */
1570 #define	DMP_MEM_REG	0x1
1571 #define	DMP_NV_PARAMS	0x2
1572 
1573 /*
1574  * Dump region ID
1575  */
1576 #define	NODE_CFG_A_REGION_ID	0
1577 #define	NODE_CFG_B_REGION_ID	1
1578 #define	NODE_CFG_C_REGION_ID	2
1579 #define	NODE_CFG_D_REGION_ID	3
1580 #define	WAKE_UP_PARMS_REGION_ID	4
1581 #define	DEF_PCI_CFG_REGION_ID	5
1582 #define	PCI_CFG_1_REGION_ID	6
1583 #define	PCI_CFG_2_REGION_ID	7
1584 #define	RSVD1_REGION_ID		8
1585 #define	RSVD2_REGION_ID		9
1586 #define	RSVD3_REGION_ID		10
1587 #define	RSVD4_REGION_ID		11
1588 #define	RSVD5_REGION_ID		12
1589 #define	RSVD6_REGION_ID		13
1590 #define	RSVD7_REGION_ID		14
1591 #define	DIAG_TRACE_REGION_ID	15
1592 #define	WWN_REGION_ID		16
1593 
1594 #define	DMP_VPD_REGION		14
1595 #define	DMP_VPD_SIZE		1024
1596 #define	DMP_VPD_DUMP_WCOUNT	24
1597 
1598 #define	DMP_FCOE_REGION		23
1599 #define	DMP_FCOE_DUMP_WCOUNT	256
1600 
1601 
1602 /* Structure for MB Command UPDATE_CFG */
1603 /* Good for SLI2/3 and SLI4 */
1604 
1605 typedef struct
1606 {
1607 #ifdef EMLXS_BIG_ENDIAN
1608 	uint32_t	rsvd2:16;
1609 	uint32_t	proc_type:8;
1610 	uint32_t	rsvd1:1;
1611 	uint32_t	Abit:1;
1612 	uint32_t	Obit:1;
1613 	uint32_t	Vbit:1;
1614 	uint32_t	req_type:4;
1615 #define	INIT_REGION	1
1616 #define	UPDATE_DATA	2
1617 #define	CLEAN_UP_CFG	3
1618 	uint32_t	entry_len:16;
1619 	uint32_t	region_id:16;
1620 #endif
1621 
1622 #ifdef EMLXS_LITTLE_ENDIAN
1623 	uint32_t	req_type:4;
1624 #define	INIT_REGION	1
1625 #define	UPDATE_DATA	2
1626 #define	CLEAN_UP_CFG	3
1627 	uint32_t	Vbit:1;
1628 	uint32_t	Obit:1;
1629 	uint32_t	Abit:1;
1630 	uint32_t	rsvd1:1;
1631 	uint32_t	proc_type:8;
1632 	uint32_t	rsvd2:16;
1633 
1634 	uint32_t	region_id:16;
1635 	uint32_t	entry_len:16;
1636 #endif
1637 
1638 	uint32_t	rsp_info;
1639 	uint32_t	byte_len;
1640 	uint32_t	cfg_data;
1641 } UPDATE_CFG_VAR;
1642 
1643 /* Structure for MB Command DEL_LD_ENTRY (29) */
1644 
1645 typedef struct
1646 {
1647 #ifdef EMLXS_LITTLE_ENDIAN
1648 	uint32_t	list_req:2;
1649 	uint32_t	list_rsp:2;
1650 	uint32_t	rsvd:28;
1651 #else
1652 	uint32_t	rsvd:28;
1653 	uint32_t	list_rsp:2;
1654 	uint32_t	list_req:2;
1655 #endif
1656 
1657 #define	FLASH_LOAD_LIST	1
1658 #define	RAM_LOAD_LIST	2
1659 #define	BOTH_LISTS	3
1660 
1661 	PROG_ID		prog_id;
1662 } DEL_LD_ENTRY_VAR;
1663 
1664 /* Structure for MB Command LOAD_AREA (81) */
1665 typedef struct
1666 {
1667 #ifdef EMLXS_LITTLE_ENDIAN
1668 	uint32_t	load_cmplt:1;
1669 	uint32_t	method:1;
1670 	uint32_t	rsvd1:1;
1671 	uint32_t	update_flash:1;
1672 	uint32_t	erase_or_prog:1;
1673 	uint32_t	version:1;
1674 	uint32_t	rsvd2:2;
1675 	uint32_t	progress:8;
1676 	uint32_t	step:8;
1677 	uint32_t	area_id:8;
1678 #else
1679 	uint32_t	area_id:8;
1680 	uint32_t	step:8;
1681 	uint32_t	progress:8;
1682 	uint32_t	rsvd2:2;
1683 	uint32_t	version:1;
1684 	uint32_t	erase_or_prog:1;
1685 	uint32_t	update_flash:1;
1686 	uint32_t	rsvd1:1;
1687 	uint32_t	method:1;
1688 	uint32_t	load_cmplt:1;
1689 #endif
1690 	uint32_t	dl_to_adr;
1691 	uint32_t	dl_len;
1692 	union
1693 	{
1694 		uint32_t	dl_from_slim_offset;
1695 		ULP_BDE		dl_from_bde;
1696 		ULP_BDE64	dl_from_bde64;
1697 		PROG_ID		prog_id;
1698 	} un;
1699 } LOAD_AREA_VAR;
1700 
1701 /* Structure for MB Command LOAD_EXP_ROM (9C) */
1702 typedef struct
1703 {
1704 #ifdef EMLXS_LITTLE_ENDIAN
1705 	uint32_t	rsvd1:8;
1706 	uint32_t	progress:8;
1707 	uint32_t	step:8;
1708 	uint32_t	rsvd2:8;
1709 #else
1710 	uint32_t	rsvd2:8;
1711 	uint32_t	step:8;
1712 	uint32_t	progress:8;
1713 	uint32_t	rsvd1:8;
1714 #endif
1715 	uint32_t	dl_to_adr;
1716 	uint32_t	rsvd3;
1717 	union
1718 	{
1719 		uint32_t	word[2];
1720 		PROG_ID		prog_id;
1721 	} un;
1722 } LOAD_EXP_ROM_VAR;
1723 
1724 
1725 /* Structure for MB Command CONFIG_HBQ (7C) */
1726 
1727 typedef struct
1728 {
1729 #ifdef EMLXS_BIG_ENDIAN
1730 	uint32_t	rsvd1:7;
1731 	uint32_t	recvNotify:1;	/* Receive Notification */
1732 	uint32_t	numMask:8;	/* # Mask Entries */
1733 	uint32_t	profile:8;	/* Selection Profile */
1734 	uint32_t	rsvd2:8;
1735 #endif
1736 #ifdef EMLXS_LITTLE_ENDIAN
1737 	uint32_t	rsvd2:8;
1738 	uint32_t	profile:8;	/* Selection Profile */
1739 	uint32_t	numMask:8;	/* # Mask Entries */
1740 	uint32_t	recvNotify:1;	/* Receive Notification */
1741 	uint32_t	rsvd1:7;
1742 #endif
1743 
1744 #ifdef EMLXS_BIG_ENDIAN
1745 	uint32_t	hbqId:16;
1746 	uint32_t	rsvd3:12;
1747 	uint32_t	ringMask:4;
1748 #endif
1749 #ifdef EMLXS_LITTLE_ENDIAN
1750 	uint32_t	ringMask:4;
1751 	uint32_t	rsvd3:12;
1752 	uint32_t	hbqId:16;
1753 #endif
1754 
1755 #ifdef EMLXS_BIG_ENDIAN
1756 	uint32_t	numEntries:16;
1757 	uint32_t	rsvd4:8;
1758 	uint32_t	headerLen:8;
1759 #endif
1760 #ifdef EMLXS_LITTLE_ENDIAN
1761 	uint32_t	headerLen:8;
1762 	uint32_t	rsvd4:8;
1763 	uint32_t	numEntries:16;
1764 #endif
1765 
1766 	uint32_t	hbqaddrLow;
1767 	uint32_t	hbqaddrHigh;
1768 
1769 #ifdef EMLXS_BIG_ENDIAN
1770 	uint32_t	rsvd5:31;
1771 	uint32_t	logEntry:1;
1772 #endif
1773 #ifdef EMLXS_LITTLE_ENDIAN
1774 	uint32_t	logEntry:1;
1775 	uint32_t	rsvd5:31;
1776 #endif
1777 
1778 	uint32_t	rsvd6;	/* w7 */
1779 	uint32_t	rsvd7;	/* w8 */
1780 	uint32_t	rsvd8;	/* w9 */
1781 
1782 	HBQ_MASK	hbqMasks[6];
1783 
1784 	union
1785 	{
1786 		uint32_t	allprofiles[12];
1787 
1788 		struct
1789 		{
1790 #ifdef EMLXS_BIG_ENDIAN
1791 			uint32_t	seqlenoff:16;
1792 			uint32_t	maxlen:16;
1793 #endif
1794 #ifdef EMLXS_LITTLE_ENDIAN
1795 			uint32_t	maxlen:16;
1796 			uint32_t	seqlenoff:16;
1797 #endif
1798 #ifdef EMLXS_BIG_ENDIAN
1799 			uint32_t	rsvd1:28;
1800 			uint32_t	seqlenbcnt:4;
1801 #endif
1802 #ifdef EMLXS_LITTLE_ENDIAN
1803 			uint32_t	seqlenbcnt:4;
1804 			uint32_t	rsvd1:28;
1805 #endif
1806 			uint32_t	rsvd[10];
1807 		} profile2;
1808 
1809 		struct
1810 		{
1811 #ifdef EMLXS_BIG_ENDIAN
1812 			uint32_t	seqlenoff:16;
1813 			uint32_t	maxlen:16;
1814 #endif
1815 #ifdef EMLXS_LITTLE_ENDIAN
1816 			uint32_t	maxlen:16;
1817 			uint32_t	seqlenoff:16;
1818 #endif
1819 #ifdef EMLXS_BIG_ENDIAN
1820 			uint32_t	cmdcodeoff:28;
1821 			uint32_t	rsvd1:12;
1822 			uint32_t	seqlenbcnt:4;
1823 #endif
1824 #ifdef EMLXS_LITTLE_ENDIAN
1825 			uint32_t	seqlenbcnt:4;
1826 			uint32_t	rsvd1:12;
1827 			uint32_t	cmdcodeoff:28;
1828 #endif
1829 			uint32_t	cmdmatch[8];
1830 
1831 			uint32_t	rsvd[2];
1832 		} profile3;
1833 
1834 		struct
1835 		{
1836 #ifdef EMLXS_BIG_ENDIAN
1837 			uint32_t	seqlenoff:16;
1838 			uint32_t	maxlen:16;
1839 #endif
1840 #ifdef EMLXS_LITTLE_ENDIAN
1841 			uint32_t	maxlen:16;
1842 			uint32_t	seqlenoff:16;
1843 #endif
1844 #ifdef EMLXS_BIG_ENDIAN
1845 			uint32_t	cmdcodeoff:28;
1846 			uint32_t	rsvd1:12;
1847 			uint32_t	seqlenbcnt:4;
1848 #endif
1849 #ifdef EMLXS_LITTLE_ENDIAN
1850 			uint32_t	seqlenbcnt:4;
1851 			uint32_t	rsvd1:12;
1852 			uint32_t	cmdcodeoff:28;
1853 #endif
1854 			uint32_t	cmdmatch[8];
1855 
1856 			uint32_t	rsvd[2];
1857 		} profile5;
1858 	} profiles;
1859 } CONFIG_HBQ_VAR;
1860 
1861 
1862 /* Structure for MB Command REG_VPI(0x96) */
1863 /* Good for SLI2/3 and SLI4 */
1864 
1865 typedef struct
1866 {
1867 #ifdef EMLXS_BIG_ENDIAN
1868 	uint32_t	rsvd1;
1869 	uint32_t	rsvd2:8;
1870 	uint32_t	sid:24;
1871 	uint32_t	rsvd3;
1872 	uint32_t	rsvd4;
1873 	uint32_t	rsvd5;
1874 	uint16_t	vfi;
1875 	uint16_t	vpi;
1876 #endif
1877 #ifdef EMLXS_LITTLE_ENDIAN
1878 	uint32_t	rsvd1;
1879 	uint32_t	sid:24;
1880 	uint32_t	rsvd2:8;
1881 	uint32_t	rsvd3;
1882 	uint32_t	rsvd4;
1883 	uint32_t	rsvd5;
1884 	uint16_t	vpi;
1885 	uint16_t	vfi;
1886 #endif
1887 } REG_VPI_VAR;
1888 
1889 /* Structure for MB Command INIT_VPI(0xA3) */
1890 /* Good for SLI4 only */
1891 
1892 typedef struct
1893 {
1894 #ifdef EMLXS_BIG_ENDIAN
1895 	uint16_t	vfi;
1896 	uint16_t	vpi;
1897 #endif
1898 #ifdef EMLXS_LITTLE_ENDIAN
1899 	uint16_t	vpi;
1900 	uint16_t	vfi;
1901 #endif
1902 } INIT_VPI_VAR;
1903 
1904 /* Structure for MB Command UNREG_VPI (0x97) */
1905 /* Good for SLI2/3 */
1906 
1907 typedef struct
1908 {
1909 	uint32_t	rsvd1;
1910 	uint32_t	rsvd2;
1911 	uint32_t	rsvd3;
1912 	uint32_t	rsvd4;
1913 	uint32_t	rsvd5;
1914 #ifdef EMLXS_BIG_ENDIAN
1915 	uint16_t	rsvd6;
1916 	uint16_t	vpi;
1917 #endif
1918 #ifdef EMLXS_LITTLE_ENDIAN
1919 	uint16_t	vpi;
1920 	uint16_t	rsvd6;
1921 #endif
1922 } UNREG_VPI_VAR;
1923 
1924 /* Structure for MB Command UNREG_VPI (0x97) */
1925 /* Good for SLI4 */
1926 
1927 typedef struct
1928 {
1929 	uint32_t	rsvd1;
1930 #ifdef EMLXS_BIG_ENDIAN
1931 	uint8_t		ii:2;
1932 	uint16_t	rsvd2:14;
1933 	uint16_t	index;
1934 #endif
1935 #ifdef EMLXS_LITTLE_ENDIAN
1936 	uint16_t	index;
1937 	uint16_t	rsvd2:14;
1938 	uint8_t		ii:2;
1939 #endif
1940 } UNREG_VPI_VAR4;
1941 
1942 /* Structure for MB Command REG_VFI(0x9F) */
1943 /* Good for SLI4 only */
1944 
1945 typedef struct
1946 {
1947 #ifdef EMLXS_BIG_ENDIAN
1948 	uint32_t	rsvd1:3;
1949 	uint32_t	vp:1;
1950 	uint32_t	rsvd2:12;
1951 	uint16_t	vfi;
1952 
1953 	uint16_t	vpi;
1954 	uint16_t	fcfi;
1955 
1956 	uint32_t	rsvd3;
1957 	uint32_t	rsvd4;
1958 
1959 	ULP_BDE64	bde;
1960 
1961 /* CHANGE with next firmware drop */
1962 	uint32_t	edtov;
1963 	uint32_t	ratov;
1964 
1965 	uint32_t	rsvd5:8;
1966 	uint32_t	sid:24;
1967 #endif
1968 #ifdef EMLXS_LITTLE_ENDIAN
1969 	uint16_t	vfi;
1970 	uint32_t	rsvd2:12;
1971 	uint32_t	vp:1;
1972 	uint32_t	rsvd1:3;
1973 
1974 	uint16_t	fcfi;
1975 	uint16_t	vpi;
1976 
1977 	uint32_t	rsvd3;
1978 	uint32_t	rsvd4;
1979 
1980 	ULP_BDE64	bde;
1981 
1982 /* CHANGE with next firmware drop */
1983 	uint32_t	edtov;
1984 	uint32_t	ratov;
1985 
1986 	uint32_t	sid:24;
1987 	uint32_t	rsvd5:8;
1988 #endif
1989 } REG_VFI_VAR;
1990 
1991 /* Structure for MB Command INIT_VFI(0xA4) */
1992 /* Good for SLI4 only */
1993 
1994 typedef struct
1995 {
1996 #ifdef EMLXS_BIG_ENDIAN
1997 	uint32_t	vr:1;
1998 	uint32_t	vt:1;
1999 	uint32_t	vf:1;
2000 	uint32_t	rsvd1:13;
2001 	uint32_t	vfi:16;
2002 
2003 	uint16_t	rsvd2;
2004 	uint16_t	fcfi;
2005 
2006 	uint32_t	rsvd3:16;
2007 	uint32_t	pri:3;
2008 	uint32_t	vf_id:12;
2009 	uint32_t	rsvd4:1;
2010 
2011 	uint32_t	hop_count:8;
2012 	uint32_t	rsvd5:24;
2013 #endif
2014 #ifdef EMLXS_LITTLE_ENDIAN
2015 	uint32_t	vfi:16;
2016 	uint32_t	rsvd1:13;
2017 	uint32_t	vf:1;
2018 	uint32_t	vt:1;
2019 	uint32_t	vr:1;
2020 
2021 	uint16_t	fcfi;
2022 	uint16_t	rsvd2;
2023 
2024 	uint32_t	rsvd4:1;
2025 	uint32_t	vf_id:12;
2026 	uint32_t	pri:3;
2027 	uint32_t	rsvd3:16;
2028 
2029 	uint32_t	rsvd5:24;
2030 	uint32_t	hop_count:8;
2031 #endif
2032 } INIT_VFI_VAR;
2033 
2034 /* Structure for MB Command UNREG_VFI (0xA1) */
2035 /* Good for SLI4 only */
2036 
2037 typedef struct
2038 {
2039 #ifdef EMLXS_BIG_ENDIAN
2040 	uint32_t	rsvd1:3;
2041 	uint32_t	vp:1;
2042 	uint32_t	rsvd2:28;
2043 
2044 	uint16_t	vpi;
2045 	uint16_t	vfi;
2046 #endif
2047 #ifdef EMLXS_LITTLE_ENDIAN
2048 	uint32_t	rsvd2:28;
2049 	uint32_t	vp:1;
2050 	uint32_t	rsvd1:3;
2051 
2052 	uint16_t	vfi;
2053 	uint16_t	vpi;
2054 #endif
2055 } UNREG_VFI_VAR;
2056 
2057 
2058 
2059 typedef struct
2060 {
2061 #ifdef EMLXS_BIG_ENDIAN
2062 	uint32_t	read_log:1;
2063 	uint32_t	clear_log:1;
2064 	uint32_t	mbox_rsp:1;
2065 	uint32_t	resv:28;
2066 #endif
2067 #ifdef EMLXS_LITTLE_ENDIAN
2068 	uint32_t	resv:28;
2069 	uint32_t	mbox_rsp:1;
2070 	uint32_t	clear_log:1;
2071 	uint32_t	read_log:1;
2072 #endif
2073 
2074 	uint32_t	offset;
2075 
2076 	union
2077 	{
2078 		ULP_BDE		sp;
2079 		ULP_BDE64	sp64;
2080 	} un;
2081 } READ_EVT_LOG_VAR;
2082 
2083 typedef struct
2084 {
2085 
2086 #ifdef EMLXS_BIG_ENDIAN
2087 	uint16_t	split_log_next;
2088 	uint16_t	log_next;
2089 
2090 	uint32_t	size;
2091 
2092 	uint32_t	format:8;
2093 	uint32_t	resv2:22;
2094 	uint32_t	log_level:1;
2095 	uint32_t	split_log:1;
2096 #endif
2097 #ifdef EMLXS_LITTLE_ENDIAN
2098 	uint16_t	log_next;
2099 	uint16_t	split_log_next;
2100 
2101 	uint32_t	size;
2102 
2103 	uint32_t	split_log:1;
2104 	uint32_t	log_level:1;
2105 	uint32_t	resv2:22;
2106 	uint32_t	format:8;
2107 #endif
2108 
2109 	uint32_t	offset;
2110 } LOG_STATUS_VAR;
2111 
2112 
2113 /* Structure for MB Command CONFIG_PORT (0x88) */
2114 typedef struct
2115 {
2116 #ifdef EMLXS_BIG_ENDIAN
2117 	uint32_t	cBE:1;
2118 	uint32_t	cET:1;
2119 	uint32_t	cHpcb:1;
2120 	uint32_t	rMA:1;
2121 	uint32_t	sli_mode:4;
2122 	uint32_t	pcbLen:24;	/* bit 23:0 of memory based port */
2123 					/* config block */
2124 #endif
2125 #ifdef EMLXS_LITTLE_ENDIAN
2126 	uint32_t	pcbLen:24;	/* bit 23:0 of memory based port */
2127 					/* config block */
2128 	uint32_t	sli_mode:4;
2129 	uint32_t	rMA:1;
2130 	uint32_t	cHpcb:1;
2131 	uint32_t	cET:1;
2132 	uint32_t	cBE:1;
2133 #endif
2134 
2135 	uint32_t	pcbLow;		/* bit 31:0 of memory based port */
2136 					/* config block */
2137 	uint32_t	pcbHigh; 	/* bit 63:32 of memory based port */
2138 					/* config block */
2139 	uint32_t	hbainit[5];
2140 
2141 #ifdef EMLXS_BIG_ENDIAN
2142 	uint32_t	hps:1; /* Host pointers in SLIM */
2143 	uint32_t	rsvd:31;
2144 #endif
2145 #ifdef EMLXS_LITTLE_ENDIAN
2146 	uint32_t	rsvd:31;
2147 	uint32_t	hps:1; /* Host pointers in SLIM */
2148 #endif
2149 
2150 #ifdef EMLXS_BIG_ENDIAN
2151 	uint32_t	rsvd1:24;
2152 	uint32_t	cmv:1;		/* Configure Max VPIs */
2153 	uint32_t	ccrp:1;		/* Config Command Ring Polling */
2154 	uint32_t	csah:1;		/* Configure Synchronous Abort */
2155 					/* Handling */
2156 	uint32_t	chbs:1;		/* Cofigure Host Backing store */
2157 	uint32_t	cinb:1;		/* Enable Interrupt Notification */
2158 					/* Block */
2159 	uint32_t	cerbm:1;	/* Configure Enhanced Receive */
2160 					/* Buffer Management */
2161 	uint32_t	cmx:1;		/* Configure Max XRIs */
2162 	uint32_t	cmr:1;		/* Configure Max RPIs */
2163 #endif
2164 #ifdef EMLXS_LITTLE_ENDIAN
2165 	uint32_t	cmr:1;		/* Configure Max RPIs */
2166 	uint32_t	cmx:1;		/* Configure Max XRIs */
2167 	uint32_t	cerbm:1;	/* Configure Enhanced Receive */
2168 					/* Buffer Management */
2169 	uint32_t	cinb:1;		/* Enable Interrupt Notification */
2170 					/* Block */
2171 	uint32_t	chbs:1;		/* Cofigure Host Backing store */
2172 	uint32_t	csah:1;		/* Configure Synchronous Abort */
2173 					/* Handling */
2174 	uint32_t	ccrp:1;		/* Config Command Ring Polling */
2175 	uint32_t	cmv:1;		/* Configure Max VPIs */
2176 	uint32_t	rsvd1:24;
2177 #endif
2178 #ifdef EMLXS_BIG_ENDIAN
2179 	uint32_t	rsvd2:24;
2180 	uint32_t	gmv:1;		/* Grant Max VPIs */
2181 	uint32_t	gcrp:1;		/* Grant Command Ring Polling */
2182 	uint32_t	gsah:1;		/* Grant Synchronous Abort Handling */
2183 	uint32_t	ghbs:1;		/* Grant Host Backing Store */
2184 	uint32_t	ginb:1;		/* Grant Interrupt Notification Block */
2185 	uint32_t	gerbm:1;	/* Grant ERBM Request */
2186 	uint32_t	gmx:1;		/* Grant Max XRIs */
2187 	uint32_t	gmr:1;		/* Grant Max RPIs */
2188 #endif
2189 #ifdef EMLXS_LITTLE_ENDIAN
2190 	uint32_t	gmr:1;		/* Grant Max RPIs */
2191 	uint32_t	gmx:1;		/* Grant Max XRIs */
2192 	uint32_t	gerbm:1;	/* Grant ERBM Request */
2193 	uint32_t	ginb:1;		/* Grant Interrupt Notification Block */
2194 	uint32_t	ghbs:1;		/* Grant Host Backing Store */
2195 	uint32_t	gsah:1;		/* Grant Synchronous Abort Handling */
2196 	uint32_t	gcrp:1;		/* Grant Command Ring Polling */
2197 	uint32_t	gmv:1;		/* Grant Max VPIs */
2198 	uint32_t	rsvd2:24;
2199 #endif
2200 
2201 #ifdef EMLXS_BIG_ENDIAN
2202 	uint32_t	max_rpi:16;	/* Max RPIs Port should configure */
2203 	uint32_t	max_xri:16;	/* Max XRIs Port should configure */
2204 #endif
2205 #ifdef EMLXS_LITTLE_ENDIAN
2206 	uint32_t	max_xri:16;	/* Max XRIs Port should configure */
2207 	uint32_t	max_rpi:16;	/* Max RPIs Port should configure */
2208 #endif
2209 
2210 #ifdef EMLXS_BIG_ENDIAN
2211 	uint32_t	max_hbq:16;	/* Max HBQs Host expect to configure */
2212 	uint32_t	rsvd3:16;	/* Max HBQs Host expect to configure */
2213 #endif
2214 #ifdef EMLXS_LITTLE_ENDIAN
2215 	uint32_t	rsvd3:16;	/* Max HBQs Host expect to configure */
2216 	uint32_t	max_hbq:16;	/* Max HBQs Host expect to configure */
2217 #endif
2218 
2219 	uint32_t	rsvd4;	/* Reserved */
2220 
2221 #ifdef EMLXS_BIG_ENDIAN
2222 	uint32_t	rsvd5:16;	/* Reserved */
2223 	uint32_t	vpi_max:16;	/* Max number of virt N-Ports */
2224 #endif
2225 #ifdef EMLXS_LITTLE_ENDIAN
2226 	uint32_t	vpi_max:16;	/* Max number of virt N-Ports */
2227 	uint32_t	rsvd5:16;	/* Reserved */
2228 #endif
2229 } CONFIG_PORT_VAR;
2230 
2231 /* Structure for MB Command REQUEST_FEATURES (0x9D) */
2232 /* Good for SLI4 only */
2233 
2234 typedef struct
2235 {
2236 #ifdef EMLXS_BIG_ENDIAN
2237 	uint32_t	rsvd1:31;
2238 	uint32_t	QueryMode:1;
2239 #endif
2240 #ifdef EMLXS_LITTLE_ENDIAN
2241 	uint32_t	QueryMode:1;
2242 	uint32_t	rsvd1:31;
2243 #endif
2244 
2245 	uint32_t	featuresRequested;
2246 	uint32_t	featuresEnabled;
2247 
2248 } REQUEST_FEATURES_VAR;
2249 
2250 #define	SLI4_FEATURE_INHIBIT_AUTO_ABTS	0x0001
2251 #define	SLI4_FEATURE_NPIV		0x0002
2252 #define	SLI4_FEATURE_DIF		0x0004
2253 #define	SLI4_FEATURE_VIRTUAL_FABRICS	0x0008
2254 #define	SLI4_FEATURE_FCP_INITIATOR	0x0010
2255 #define	SLI4_FEATURE_FCP_TARGET		0x0020
2256 #define	SLI4_FEATURE_FCP_COMBO		0x0040
2257 #define	SLI4_FEATURE_INHIBIT_FIP	0x0080
2258 
2259 
2260 /* SLI-2 Port Control Block */
2261 
2262 /* SLIM POINTER */
2263 #define	SLIMOFF	0x30	/* WORD */
2264 
2265 typedef struct _SLI2_RDSC
2266 {
2267 	uint32_t	cmdEntries;
2268 	uint32_t	cmdAddrLow;
2269 	uint32_t	cmdAddrHigh;
2270 
2271 	uint32_t	rspEntries;
2272 	uint32_t	rspAddrLow;
2273 	uint32_t	rspAddrHigh;
2274 } SLI2_RDSC;
2275 
2276 typedef struct _PCB
2277 {
2278 #ifdef EMLXS_BIG_ENDIAN
2279 	uint32_t	type:8;
2280 #define	TYPE_NATIVE_SLI2	0x01;
2281 	uint32_t	feature:8;
2282 #define	FEATURE_INITIAL_SLI2	0x01;
2283 	uint32_t	rsvd:12;
2284 	uint32_t	maxRing:4;
2285 #endif
2286 #ifdef EMLXS_LITTLE_ENDIAN
2287 	uint32_t	maxRing:4;
2288 	uint32_t	rsvd:12;
2289 	uint32_t	feature:8;
2290 #define	FEATURE_INITIAL_SLI2	0x01;
2291 	uint32_t	type:8;
2292 #define	TYPE_NATIVE_SLI2	0x01;
2293 #endif
2294 
2295 	uint32_t	mailBoxSize;
2296 	uint32_t	mbAddrLow;
2297 	uint32_t	mbAddrHigh;
2298 
2299 	uint32_t	hgpAddrLow;
2300 	uint32_t	hgpAddrHigh;
2301 
2302 	uint32_t	pgpAddrLow;
2303 	uint32_t	pgpAddrHigh;
2304 	SLI2_RDSC	rdsc[MAX_RINGS_AVAILABLE];
2305 } PCB;
2306 
2307 /* NEW_FEATURE */
2308 typedef struct
2309 {
2310 #ifdef EMLXS_BIG_ENDIAN
2311 	uint32_t	rsvd0:27;
2312 	uint32_t	discardFarp:1;
2313 	uint32_t	IPEnable:1;
2314 	uint32_t	nodeName:1;
2315 	uint32_t	portName:1;
2316 	uint32_t	filterEnable:1;
2317 #endif
2318 #ifdef EMLXS_LITTLE_ENDIAN
2319 	uint32_t	filterEnable:1;
2320 	uint32_t	portName:1;
2321 	uint32_t	nodeName:1;
2322 	uint32_t	IPEnable:1;
2323 	uint32_t	discardFarp:1;
2324 	uint32_t	rsvd:27;
2325 #endif
2326 	NAME_TYPE	portname;
2327 	NAME_TYPE	nodename;
2328 	uint32_t	rsvd1;
2329 	uint32_t	rsvd2;
2330 	uint32_t	rsvd3;
2331 	uint32_t	IPAddress;
2332 } CONFIG_FARP_VAR;
2333 
2334 
2335 /* NEW_FEATURE */
2336 typedef struct
2337 {
2338 #ifdef EMLXS_BIG_ENDIAN
2339 	uint32_t	defaultMessageNumber:16;
2340 	uint32_t	rsvd1:3;
2341 	uint32_t	nid:5;
2342 	uint32_t	rsvd2:5;
2343 	uint32_t	defaultPresent:1;
2344 	uint32_t	addAssociations:1;
2345 	uint32_t	reportAssociations:1;
2346 #endif
2347 #ifdef EMLXS_LITTLE_ENDIAN
2348 	uint32_t	reportAssociations:1;
2349 	uint32_t	addAssociations:1;
2350 	uint32_t	defaultPresent:1;
2351 	uint32_t	rsvd2:5;
2352 	uint32_t	nid:5;
2353 	uint32_t	rsvd1:3;
2354 	uint32_t	defaultMessageNumber:16;
2355 #endif
2356 	uint32_t	attConditions;
2357 	uint8_t		attentionId[16];
2358 	uint16_t	messageNumberByHA[32];
2359 	uint16_t	messageNumberByID[16];
2360 	uint32_t	rsvd3;
2361 } CONFIG_MSI_VAR;
2362 
2363 
2364 /* NEW_FEATURE */
2365 typedef struct
2366 {
2367 #ifdef EMLXS_BIG_ENDIAN
2368 	uint32_t	defaultMessageNumber:8;
2369 	uint32_t	rsvd1:11;
2370 	uint32_t	nid:5;
2371 	uint32_t	rsvd2:5;
2372 	uint32_t	defaultPresent:1;
2373 	uint32_t	addAssociations:1;
2374 	uint32_t	reportAssociations:1;
2375 #endif
2376 #ifdef EMLXS_LITTLE_ENDIAN
2377 	uint32_t	reportAssociations:1;
2378 	uint32_t	addAssociations:1;
2379 	uint32_t	defaultPresent:1;
2380 	uint32_t	rsvd2:5;
2381 	uint32_t	nid:5;
2382 	uint32_t	rsvd1:11;
2383 	uint32_t	defaultMessageNumber:8;
2384 #endif
2385 	uint32_t	attConditions1;
2386 	uint32_t	attConditions2;
2387 	uint8_t		attentionId[16];
2388 	uint8_t		messageNumberByHA[64];
2389 	uint8_t		messageNumberByID[16];
2390 	uint32_t	autoClearByHA1;
2391 	uint32_t	autoClearByHA2;
2392 	uint32_t	autoClearByID;
2393 	uint32_t	resv3;
2394 } CONFIG_MSIX_VAR;
2395 
2396 
2397 /* Union of all Mailbox Command types */
2398 
2399 typedef union
2400 {
2401 	uint32_t		varWords[31];
2402 	LOAD_SM_VAR		varLdSM;	/* cmd =  1 (LOAD_SM) */
2403 	READ_NV_VAR		varRDnvp;	/* cmd =  2 (READ_NVPARMS) */
2404 	WRITE_NV_VAR		varWTnvp;	/* cmd =  3 (WRITE_NVPARMS) */
2405 	BIU_DIAG_VAR		varBIUdiag;	/* cmd =  4 (RUN_BIU_DIAG) */
2406 	INIT_LINK_VAR		varInitLnk;	/* cmd =  5 (INIT_LINK) */
2407 	DOWN_LINK_VAR		varDwnLnk;	/* cmd =  6 (DOWN_LINK) */
2408 	CONFIG_LINK		varCfgLnk;	/* cmd =  7 (CONFIG_LINK) */
2409 	PART_SLIM_VAR		varSlim;	/* cmd =  8 (PART_SLIM) */
2410 	CONFIG_RING_VAR		varCfgRing;	/* cmd =  9 (CONFIG_RING) */
2411 	RESET_RING_VAR		varRstRing;	/* cmd = 10 (RESET_RING) */
2412 	READ_CONFIG_VAR		varRdConfig;	/* cmd = 11 (READ_CONFIG) */
2413 	READ_RCONF_VAR		varRdRConfig;	/* cmd = 12 (READ_RCONFIG) */
2414 	READ_SPARM_VAR		varRdSparm;	/* cmd = 13 (READ_SPARM(64)) */
2415 	READ_STATUS_VAR		varRdStatus;	/* cmd = 14 (READ_STATUS) */
2416 	READ_RPI_VAR		varRdRPI;	/* cmd = 15 (READ_RPI(64)) */
2417 	READ_XRI_VAR		varRdXRI;	/* cmd = 16 (READ_XRI) */
2418 	READ_REV_VAR		varRdRev;	/* cmd = 17 (READ_REV) */
2419 	READ_LNK_VAR		varRdLnk;	/* cmd = 18 (READ_LNK_STAT) */
2420 	REG_LOGIN_VAR		varRegLogin;	/* cmd = 19 (REG_LOGIN(64)) */
2421 	UNREG_LOGIN_VAR		varUnregLogin;	/* cmd = 20 (UNREG_LOGIN) */
2422 	READ_LA_VAR		varReadLA;	/* cmd = 21 (READ_LA(64)) */
2423 	CLEAR_LA_VAR		varClearLA;	/* cmd = 22 (CLEAR_LA) */
2424 	DUMP_VAR		varDmp;		/* Warm Start DUMP mbx cmd */
2425 	UPDATE_CFG_VAR		varUpdateCfg;	/* cmd = 0x1b Warm Start */
2426 						/* UPDATE_CFG cmd */
2427 	DEL_LD_ENTRY_VAR	varDelLdEntry;	/* cmd = 0x1d (DEL_LD_ENTRY) */
2428 	UNREG_D_ID_VAR		varUnregDID;	/* cmd = 0x23 (UNREG_D_ID) */
2429 	CONFIG_FARP_VAR		varCfgFarp;	/* cmd = 0x25 (CONFIG_FARP) */
2430 	CONFIG_MSI_VAR		varCfgMSI;	/* cmd = 0x90 (CONFIG_MSI) */
2431 	CONFIG_MSIX_VAR		varCfgMSIX;	/* cmd = 0x30 (CONFIG_MSIX) */
2432 	CONFIG_HBQ_VAR		varCfgHbq;	/* cmd = 0x7C (CONFIG_HBQ) */
2433 	LOAD_AREA_VAR		varLdArea;	/* cmd = 0x81 (LOAD_AREA) */
2434 	CONFIG_PORT_VAR		varCfgPort;	/* cmd = 0x88 (CONFIG_PORT) */
2435 	LOAD_EXP_ROM_VAR	varLdExpRom;	/* cmd = 0x9C (LOAD_XP_ROM) */
2436 	REG_VPI_VAR		varRegVpi;	/* cmd = 0x96 (REG_VPI) */
2437 	UNREG_VPI_VAR		varUnregVpi;	/* cmd = 0x97 (UNREG_VPI) */
2438 	READ_EVT_LOG_VAR	varRdEvtLog;	/* cmd = 0x38 (READ_EVT_LOG) */
2439 	LOG_STATUS_VAR		varLogStat;	/* cmd = 0x37 */
2440 
2441 } MAILVARIANTS;
2442 
2443 #define	MAILBOX_CMD_BSIZE	128
2444 #define	MAILBOX_CMD_WSIZE	32
2445 
2446 /*
2447  * SLI-2 specific structures
2448  */
2449 
2450 typedef struct _SLI1_DESC
2451 {
2452 	emlxs_rings_t	mbxCring[4];
2453 	uint32_t	mbxUnused[24];
2454 } SLI1_DESC; /* 128 bytes */
2455 
2456 typedef struct
2457 {
2458 	uint32_t	cmdPutInx;
2459 	uint32_t	rspGetInx;
2460 } HGP;
2461 
2462 typedef struct
2463 {
2464 	uint32_t	cmdGetInx;
2465 	uint32_t	rspPutInx;
2466 } PGP;
2467 
2468 typedef struct _SLI2_DESC
2469 {
2470 	HGP		host[4];
2471 	PGP		port[4];
2472 	uint32_t	HBQ_PortGetIdx[16];
2473 } SLI2_DESC; /* 128 bytes */
2474 
2475 typedef union
2476 {
2477 	SLI1_DESC	s1;	/* 32 words, 128 bytes */
2478 	SLI2_DESC	s2;	/* 32 words, 128 bytes */
2479 } SLI_VAR;
2480 
2481 typedef volatile struct
2482 {
2483 #ifdef EMLXS_BIG_ENDIAN
2484 	uint16_t	mbxStatus;
2485 	uint8_t		mbxCommand;
2486 	uint8_t		mbxReserved:6;
2487 	uint8_t		mbxHc:1;
2488 	uint8_t		mbxOwner:1;	/* Low order bit first word */
2489 #endif
2490 #ifdef EMLXS_LITTLE_ENDIAN
2491 	uint8_t		mbxOwner:1;	/* Low order bit first word */
2492 	uint8_t		mbxHc:1;
2493 	uint8_t		mbxReserved:6;
2494 	uint8_t		mbxCommand;
2495 	uint16_t	mbxStatus;
2496 #endif
2497 	MAILVARIANTS	un;		/* 124 bytes */
2498 	SLI_VAR		us;		/* 128 bytes */
2499 } MAILBOX;				/* 256 bytes */
2500 
2501 
2502 
2503 /* SLI4 IOCTL Mailbox */
2504 /* ALL SLI4 specific mbox commands have a standard request /response header */
2505 /* Word 0 is just like SLI 3 */
2506 
2507 typedef struct mbox_req_hdr
2508 {
2509 #ifdef EMLXS_BIG_ENDIAN
2510 	uint32_t	domain:8;		/* word 6 */
2511 	uint32_t	port:8;
2512 	uint32_t	subsystem:8;
2513 	uint32_t	opcode:8;
2514 #endif
2515 #ifdef EMLXS_LITTLE_ENDIAN
2516 	uint32_t	opcode:8;
2517 	uint32_t	subsystem:8;
2518 	uint32_t	port:8;
2519 	uint32_t	domain:8;		/* word 6 */
2520 #endif
2521 	uint32_t	timeout;		/* word 7 */
2522 	uint32_t	req_length;		/* word 8 */
2523 	uint32_t	reserved1;		/* word 9 */
2524 } mbox_req_hdr_t;
2525 
2526 typedef struct mbox_rsp_hdr
2527 {
2528 #ifdef EMLXS_BIG_ENDIAN
2529 	uint32_t	domain:8;		/* word 6 */
2530 	uint32_t	reserved1:8;
2531 	uint32_t	subsystem:8;
2532 	uint32_t	opcode:8;
2533 
2534 	uint32_t	reserved2:16;		/* word 7 */
2535 	uint32_t	extra_status:8;
2536 	uint32_t	status:8;
2537 #endif
2538 #ifdef EMLXS_LITTLE_ENDIAN
2539 	uint32_t	opcode:8;
2540 	uint32_t	subsystem:8;
2541 	uint32_t	reserved1:8;
2542 	uint32_t	domain:8;		/* word 6 */
2543 
2544 	uint32_t	status:8;
2545 	uint32_t	extra_status:8;
2546 	uint32_t	reserved2:16;		/* word 7 */
2547 #endif
2548 	uint32_t	rsp_length;		/* word 8 */
2549 	uint32_t	allocated_length;	/* word 9 */
2550 } mbox_rsp_hdr_t;
2551 
2552 typedef struct be_req_hdr
2553 {
2554 #ifdef EMLXS_BIG_ENDIAN
2555 	uint32_t	special:8;		/* word 1 */
2556 	uint32_t	reserved2:16;		/* word 1 */
2557 	uint32_t	sge_cnt:5;		/* word 1 */
2558 	uint32_t	reserved1:2;		/* word 1 */
2559 	uint32_t	embedded:1;		/* word 1 */
2560 #endif
2561 #ifdef EMLXS_LITTLE_ENDIAN
2562 	uint32_t	embedded:1;		/* word 1 */
2563 	uint32_t	reserved1:2;		/* word 1 */
2564 	uint32_t	sge_cnt:5;		/* word 1 */
2565 	uint32_t	reserved2:16;		/* word 1 */
2566 	uint32_t	special:8;		/* word 1 */
2567 #endif
2568 	uint32_t	payload_length;		/* word 2 */
2569 	uint32_t	tag_low;		/* word 3 */
2570 	uint32_t	tag_hi;			/* word 4 */
2571 	uint32_t	reserved3;		/* word 5 */
2572 	union
2573 	{
2574 		mbox_req_hdr_t	hdr_req;
2575 		mbox_rsp_hdr_t	hdr_rsp;
2576 	} un_hdr;
2577 } be_req_hdr_t;
2578 
2579 #define	EMLXS_MAX_NONEMBED_SIZE		(1024 * 64)
2580 
2581 /* SLI_CONFIG Mailbox commands */
2582 
2583 #define	IOCTL_SUBSYSTEM_COMMON			0x01
2584 #define	IOCTL_SUBSYSTEM_FCOE			0x0C
2585 #define	IOCTL_SUBSYSTEM_DCBX			0x10
2586 
2587 #define	COMMON_OPCODE_READ_FLASHROM		0x06
2588 #define	COMMON_OPCODE_WRITE_FLASHROM		0x07
2589 #define	COMMON_OPCODE_CQ_CREATE			0x0C
2590 #define	COMMON_OPCODE_EQ_CREATE			0x0D
2591 #define	COMMON_OPCODE_MQ_CREATE 		0x15
2592 #define	COMMON_OPCODE_GET_CNTL_ATTRIB		0x20
2593 #define	COMMON_OPCODE_NOP			0x21
2594 #define	COMMON_OPCODE_QUERY_FIRMWARE_CONFIG	0x3A
2595 #define	COMMON_OPCODE_RESET			0x3D
2596 #define	COMMON_OPCODE_MANAGE_FAT		0x44
2597 
2598 #define	FCOE_OPCODE_WQ_CREATE			0x01
2599 #define	FCOE_OPCODE_CFG_POST_SGL_PAGES		0x03
2600 #define	FCOE_OPCODE_RQ_CREATE			0x05
2601 #define	FCOE_OPCODE_READ_FCF_TABLE		0x08
2602 #define	FCOE_OPCODE_ADD_FCF_TABLE		0x09
2603 #define	FCOE_OPCODE_POST_HDR_TEMPLATES		0x0B
2604 
2605 #define	DCBX_OPCODE_GET_DCBX_MODE		0x04
2606 #define	DCBX_OPCODE_SET_DCBX_MODE		0x05
2607 
2608 typedef	struct
2609 {
2610 	struct
2611 	{
2612 		uint32_t opcode;
2613 #define	MGMT_FLASHROM_OPCODE_FLASH		1
2614 #define	MGMT_FLASHROM_OPCODE_SAVE		2
2615 #define	MGMT_FLASHROM_OPCODE_CLEAR		3
2616 #define	MGMT_FLASHROM_OPCODE_REPORT		4
2617 #define	MGMT_FLASHROM_OPCODE_INFO		5
2618 #define	MGMT_FLASHROM_OPCODE_CRC		6
2619 
2620 		uint32_t optype;
2621 #define	MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE	0
2622 #define	MGMT_FLASHROM_OPTYPE_REDBOOT		1
2623 #define	MGMT_FLASHROM_OPTYPE_ISCSI_BIOS		2
2624 #define	MGMT_FLASHROM_OPTYPE_PXE_BIOS		3
2625 #define	MGMT_FLASHROM_OPTYPE_CTRLS		4
2626 #define	MGMT_FLASHROM_OPTYPE_CFG_IPSEC		5
2627 #define	MGMT_FLASHROM_OPTYPE_CFG_INI		6
2628 #define	MGMT_FLASHROM_OPTYPE_ROM_OFFSET		7
2629 #define	MGMT_FLASHROM_OPTYPE_FCOE_BIOS		8
2630 #define	MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP	9
2631 #define	MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE	10
2632 #define	MGMT_FLASHROM_OPTYPE_FCOE_BACKUP	11
2633 #define	MGMT_FLASHROM_OPTYPE_CTRLP		12
2634 
2635 		uint32_t data_buffer_size; /* Align to 4KB */
2636 		uint32_t offset;
2637 		uint32_t data_buffer; /* image starts here */
2638 
2639 	} params;
2640 
2641 } IOCTL_COMMON_FLASHROM;
2642 
2643 
2644 typedef	struct
2645 {
2646 	union
2647 	{
2648 		struct
2649 		{
2650 			uint32_t fat_operation;
2651 #define	RETRIEVE_FAT		0
2652 #define	QUERY_FAT		1
2653 #define	CLEAR_FAT		2
2654 
2655 			uint32_t read_log_offset;
2656 			uint32_t read_log_length;
2657 			uint32_t data_buffer_size;
2658 			uint32_t data_buffer;
2659 		} request;
2660 
2661 		struct
2662 		{
2663 			uint32_t log_size;
2664 			uint32_t read_log_length;
2665 			uint32_t rsvd0;
2666 			uint32_t rsvd1;
2667 			uint32_t data_buffer;
2668 		} response;
2669 
2670 	} params;
2671 
2672 } IOCTL_COMMON_MANAGE_FAT;
2673 
2674 
2675 /* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */
2676 typedef struct _BE_FW_CFG
2677 {
2678 	uint32_t	BEConfigNumber;
2679 	uint32_t	ASICRevision;
2680 	uint32_t	PhysicalPort;
2681 	uint32_t	FunctionMode;
2682 	uint32_t	ULPMode;
2683 
2684 } BE_FW_CFG;
2685 
2686 typedef	struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG
2687 {
2688 	union
2689 	{
2690 		struct
2691 		{
2692 			uint32_t	rsvd0;
2693 		} request;
2694 
2695 		BE_FW_CFG	response;
2696 
2697 	}	params;
2698 
2699 } IOCTL_COMMON_QUERY_FIRMWARE_CONFIG;
2700 
2701 
2702 
2703 /* IOCTL_FCOE_READ_FCF_TABLE */
2704 typedef struct
2705 {
2706 	uint32_t	max_recv_size;
2707 	uint32_t	fka_adv_period;
2708 	uint32_t	fip_priority;
2709 
2710 #ifdef EMLXS_BIG_ENDIAN
2711 	uint8_t		fcf_mac_address_hi[4];
2712 
2713 	uint8_t		mac_address_provider;
2714 	uint8_t		fcf_available;
2715 	uint8_t		fcf_mac_address_low[2];
2716 
2717 	uint8_t		fabric_name_identifier[8];
2718 
2719 	uint8_t		fcf_valid;
2720 	uint8_t		fc_map[3];
2721 
2722 	uint16_t	fcf_state;
2723 	uint16_t	fcf_index;
2724 #endif
2725 #ifdef EMLXS_LITTLE_ENDIAN
2726 	uint8_t		fcf_mac_address_hi[4];
2727 
2728 	uint8_t		fcf_mac_address_low[2];
2729 	uint8_t		fcf_available;
2730 	uint8_t		mac_address_provider;
2731 
2732 	uint8_t		fabric_name_identifier[8];
2733 
2734 	uint8_t		fc_map[3];
2735 	uint8_t		fcf_valid;
2736 
2737 	uint16_t	fcf_index;
2738 	uint16_t	fcf_state;
2739 #endif
2740 
2741 	uint8_t		vlan_bitmap[512];
2742 	uint8_t		switch_name_identifier[8];
2743 
2744 } FCF_RECORD_t;
2745 
2746 #define	EMLXS_FCOE_MAX_RCV_SZ	0x800
2747 
2748 /* defines for mac_address_provider */
2749 #define	EMLXS_MAM_BOTH	0	/* Both SPMA and FPMA */
2750 #define	EMLXS_MAM_FPMA	1	/* Fabric Provided MAC Address */
2751 #define	EMLXS_MAM_SPMA	2	/* Server Provided MAC Address */
2752 
2753 typedef struct
2754 {
2755 	union
2756 	{
2757 		struct
2758 		{
2759 #ifdef EMLXS_BIG_ENDIAN
2760 			uint16_t	rsvd0;
2761 			uint16_t	fcf_index;
2762 #endif
2763 #ifdef EMLXS_LITTLE_ENDIAN
2764 			uint16_t	fcf_index;
2765 			uint16_t	rsvd0;
2766 #endif
2767 
2768 		} request;
2769 
2770 		struct
2771 		{
2772 			uint32_t	event_tag;
2773 #ifdef EMLXS_BIG_ENDIAN
2774 			uint16_t	rsvd0;
2775 			uint16_t	next_valid_fcf_index;
2776 #endif
2777 #ifdef EMLXS_LITTLE_ENDIAN
2778 			uint16_t	next_valid_fcf_index;
2779 			uint16_t	rsvd0;
2780 #endif
2781 			FCF_RECORD_t fcf_entry[1];
2782 
2783 		} response;
2784 
2785 	} params;
2786 
2787 } IOCTL_FCOE_READ_FCF_TABLE;
2788 
2789 
2790 /* IOCTL_FCOE_ADD_FCF_TABLE */
2791 typedef struct
2792 {
2793 	union
2794 	{
2795 		struct
2796 		{
2797 #ifdef EMLXS_BIG_ENDIAN
2798 			uint16_t	rsvd0;
2799 			uint16_t	fcf_index;
2800 #endif
2801 #ifdef EMLXS_LITTLE_ENDIAN
2802 			uint16_t	fcf_index;
2803 			uint16_t	rsvd0;
2804 #endif
2805 			FCF_RECORD_t fcf_entry;
2806 
2807 		} request;
2808 
2809 		struct
2810 		{
2811 #ifdef EMLXS_BIG_ENDIAN
2812 			uint16_t	rsvd0;
2813 			uint16_t	fcf_index;
2814 #endif
2815 #ifdef EMLXS_LITTLE_ENDIAN
2816 			uint16_t	fcf_index;
2817 			uint16_t	rsvd0;
2818 #endif
2819 		} response;
2820 	} params;
2821 
2822 } IOCTL_FCOE_ADD_FCF_TABLE;
2823 
2824 #define	FCOE_FCF_MAC0	0x0E
2825 #define	FCOE_FCF_MAC1	0xFC
2826 #define	FCOE_FCF_MAC2	0x00
2827 #define	FCOE_FCF_MAC3	0xFF
2828 #define	FCOE_FCF_MAC4	0xFF
2829 #define	FCOE_FCF_MAC5	0xFE
2830 
2831 #define	FCOE_FCF_MAP0	0x0E
2832 #define	FCOE_FCF_MAP1	0xFC
2833 #define	FCOE_FCF_MAP2	0x00
2834 
2835 #define	MGMT_STATUS_FCF_IN_USE	0x3a
2836 
2837 /* IOCTL_COMMON_NOP */
2838 typedef	struct _IOCTL_COMMON_NOP
2839 {
2840 	union
2841 	{
2842 		struct
2843 		{
2844 			uint64_t	context;
2845 		} request;
2846 
2847 		struct
2848 		{
2849 			uint64_t	context;
2850 		} response;
2851 
2852 	} params;
2853 
2854 } IOCTL_COMMON_NOP;
2855 
2856 
2857 /*	Context for EQ create	*/
2858 typedef	struct _EQ_CONTEXT
2859 {
2860 #ifdef EMLXS_BIG_ENDIAN
2861 	uint32_t	Size:1;
2862 	uint32_t	Rsvd2:1;
2863 	uint32_t	Valid:1;
2864 	uint32_t	EPIndex:13;
2865 	uint32_t	Rsvd1:3;
2866 	uint32_t	ConsumerIndex:13;
2867 
2868 	uint32_t	Armed:1;
2869 	uint32_t	Stalled:1;
2870 	uint32_t	SolEvent:1;
2871 	uint32_t	Count:3;
2872 	uint32_t	ProtectionDomain:10;
2873 	uint32_t	Rsvd3:3;
2874 	uint32_t	ProduderIndex:13;
2875 
2876 	uint32_t	Rsvd7:4;
2877 	uint32_t	NoDelay:1;
2878 	uint32_t	Phase:2;
2879 	uint32_t	Rsvd6:2;
2880 	uint32_t	DelayMult:10;
2881 	uint32_t	Rsvd5:1;
2882 	uint32_t	Func:8;
2883 	uint32_t	Rsvd4:4;
2884 #endif
2885 #ifdef EMLXS_LITTLE_ENDIAN
2886 	uint32_t	ConsumerIndex:13;
2887 	uint32_t	Rsvd1:3;
2888 	uint32_t	EPIndex:13;
2889 	uint32_t	Valid:1;
2890 	uint32_t	Rsvd2:1;
2891 	uint32_t	Size:1;
2892 
2893 	uint32_t	ProduderIndex:13;
2894 	uint32_t	Rsvd3:3;
2895 	uint32_t	ProtectionDomain:10;
2896 	uint32_t	Count:3;
2897 	uint32_t	SolEvent:1;
2898 	uint32_t	Stalled:1;
2899 	uint32_t	Armed:1;
2900 
2901 	uint32_t	Rsvd4:4;
2902 	uint32_t	Func:8;
2903 	uint32_t	Rsvd5:1;
2904 	uint32_t	DelayMult:10;
2905 	uint32_t	Rsvd6:2;
2906 	uint32_t	Phase:2;
2907 	uint32_t	NoDelay:1;
2908 	uint32_t	Rsvd7:4;
2909 #endif
2910 
2911 	uint32_t	Rsvd8;
2912 
2913 }EQ_CONTEXT;
2914 
2915 /* define for Count field */
2916 #define	EQ_ELEMENT_COUNT_1024	2
2917 #define	EQ_ELEMENT_COUNT_2048	3
2918 #define	EQ_ELEMENT_COUNT_4096	4
2919 
2920 /* define for Size field */
2921 #define	EQ_ELEMENT_SIZE_4	0
2922 
2923 /* define for DelayMullt - used for interrupt coalescing */
2924 #define	EQ_DELAY_MULT		256
2925 
2926 /*	Context for CQ create	*/
2927 typedef	struct _CQ_CONTEXT
2928 {
2929 #ifdef EMLXS_BIG_ENDIAN
2930 	uint32_t	Eventable:1;
2931 	uint32_t	SolEvent:1;
2932 	uint32_t	Valid:1;
2933 	uint32_t	Count:2;
2934 	uint32_t	Rsvd2:1;
2935 	uint32_t	EPIndex:11;
2936 	uint32_t	NoDelay:1;
2937 	uint32_t	CoalesceWM:2;
2938 	uint32_t	Rsvd1:1;
2939 	uint32_t	ConsumerIndex:11;
2940 
2941 	uint32_t	Armed:1;
2942 	uint32_t	Stalled:1;
2943 	uint32_t	EQId:8;
2944 	uint32_t	ProtectionDomain:10;
2945 	uint32_t	Rsvd3:1;
2946 	uint32_t	ProduderIndex:11;
2947 
2948 	uint32_t	Rsvd5:20;
2949 	uint32_t	Func:8;
2950 	uint32_t	Rsvd4:4;
2951 #endif
2952 #ifdef EMLXS_LITTLE_ENDIAN
2953 	uint32_t	ConsumerIndex:11;
2954 	uint32_t	Rsvd1:1;
2955 	uint32_t	CoalesceWM:2;
2956 	uint32_t	NoDelay:1;
2957 	uint32_t	EPIndex:11;
2958 	uint32_t	Rsvd2:1;
2959 	uint32_t	Count:2;
2960 	uint32_t	Valid:1;
2961 	uint32_t	SolEvent:1;
2962 	uint32_t	Eventable:1;
2963 
2964 	uint32_t	ProduderIndex:11;
2965 	uint32_t	Rsvd3:1;
2966 	uint32_t	ProtectionDomain:10;
2967 	uint32_t	EQId:8;
2968 	uint32_t	Stalled:1;
2969 	uint32_t	Armed:1;
2970 
2971 	uint32_t	Rsvd4:4;
2972 	uint32_t	Func:8;
2973 	uint32_t	Rsvd5:20;
2974 #endif
2975 
2976 	uint32_t	Rsvd6;
2977 
2978 } CQ_CONTEXT;
2979 
2980 /* define for Count field */
2981 #define	CQ_ELEMENT_COUNT_256	0
2982 #define	CQ_ELEMENT_COUNT_512	1
2983 #define	CQ_ELEMENT_COUNT_1024	2
2984 
2985 /*	Context for MQ create	*/
2986 typedef	struct _MQ_CONTEXT
2987 {
2988 #ifdef EMLXS_BIG_ENDIAN
2989 	uint32_t	CQId:10;
2990 	uint32_t	Rsvd2:2;
2991 	uint32_t	Size:4;
2992 	uint32_t	Rsvd1:2;
2993 	uint32_t	ConsumerIndex:14;
2994 
2995 	uint32_t	Valid:1;
2996 	uint32_t	ProtectionDomain:9;
2997 	uint32_t	FunctionNumber:8;
2998 	uint32_t	ProduderIndex:14;
2999 #endif
3000 #ifdef EMLXS_LITTLE_ENDIAN
3001 	uint32_t	ConsumerIndex:14;
3002 	uint32_t	Rsvd1:2;
3003 	uint32_t	Size:4;
3004 	uint32_t	Rsvd2:2;
3005 	uint32_t	CQId:10;
3006 
3007 	uint32_t	ProduderIndex:14;
3008 	uint32_t	FunctionNumber:8;
3009 	uint32_t	ProtectionDomain:9;
3010 	uint32_t	Valid:1;
3011 #endif
3012 
3013 	uint32_t	Rsvd3;
3014 	uint32_t	Rsvd4;
3015 
3016 } MQ_CONTEXT;
3017 
3018 /* define for Size field */
3019 #define	MQ_ELEMENT_COUNT_16 0x05
3020 
3021 /*	Context for RQ create	*/
3022 typedef	struct _RQ_CONTEXT
3023 {
3024 #ifdef EMLXS_BIG_ENDIAN
3025 	uint32_t	Rsvd2:8;
3026 	uint32_t	RQState:4;
3027 	uint32_t	RQSize:4;
3028 	uint32_t	Rsvd1:16;
3029 
3030 	uint32_t	Rsvd3;
3031 
3032 	uint32_t	Rsvd4:6;
3033 	uint32_t	CQIdRecv:10;
3034 	uint32_t	BufferSize:16;
3035 #endif
3036 #ifdef EMLXS_LITTLE_ENDIAN
3037 	uint32_t	Rsvd1:16;
3038 	uint32_t	RQSize:4;
3039 	uint32_t	RQState:4;
3040 	uint32_t	Rsvd2:8;
3041 
3042 	uint32_t	Rsvd3;
3043 
3044 	uint32_t	BufferSize:16;
3045 	uint32_t	CQIdRecv:10;
3046 	uint32_t	Rsvd4:6;
3047 #endif
3048 
3049 	uint32_t  Rsvd5;
3050 
3051 } RQ_CONTEXT;
3052 
3053 
3054 /* IOCTL_COMMON_EQ_CREATE */
3055 typedef	struct
3056 {
3057 	union
3058 	{
3059 		struct
3060 		{
3061 #ifdef EMLXS_BIG_ENDIAN
3062 			uint16_t	Rsvd1;
3063 			uint16_t	NumPages;
3064 #endif
3065 #ifdef EMLXS_LITTLE_ENDIAN
3066 			uint16_t	NumPages;
3067 			uint16_t	Rsvd1;
3068 #endif
3069 			EQ_CONTEXT	EQContext;
3070 			BE_PHYS_ADDR	Pages[8];
3071 		} request;
3072 
3073 		struct
3074 		{
3075 #ifdef EMLXS_BIG_ENDIAN
3076 			uint16_t	Rsvd1;
3077 			uint16_t	EQId;
3078 #endif
3079 #ifdef EMLXS_LITTLE_ENDIAN
3080 			uint16_t	EQId;
3081 			uint16_t	Rsvd1;
3082 #endif
3083 		} response;
3084 	} params;
3085 
3086 } IOCTL_COMMON_EQ_CREATE;
3087 
3088 
3089 /* IOCTL_COMMON_CQ_CREATE */
3090 typedef	struct
3091 {
3092 	union
3093 	{
3094 		struct
3095 		{
3096 #ifdef EMLXS_BIG_ENDIAN
3097 			uint16_t	Rsvd1;
3098 			uint16_t	NumPages;
3099 #endif
3100 #ifdef EMLXS_LITTLE_ENDIAN
3101 			uint16_t	NumPages;
3102 			uint16_t	Rsvd1;
3103 #endif
3104 			CQ_CONTEXT	CQContext;
3105 			BE_PHYS_ADDR	Pages[4];
3106 		} request;
3107 
3108 		struct
3109 		{
3110 #ifdef EMLXS_BIG_ENDIAN
3111 			uint16_t	Rsvd1;
3112 			uint16_t	CQId;
3113 #endif
3114 #ifdef EMLXS_LITTLE_ENDIAN
3115 			uint16_t	CQId;
3116 			uint16_t	Rsvd1;
3117 #endif
3118 		} response;
3119 	} params;
3120 
3121 } IOCTL_COMMON_CQ_CREATE;
3122 
3123 
3124 /* IOCTL_COMMON_MQ_CREATE */
3125 typedef	struct
3126 {
3127 	union
3128 	{
3129 		struct
3130 		{
3131 #ifdef EMLXS_BIG_ENDIAN
3132 			uint16_t	Rsvd1;
3133 			uint16_t	NumPages;
3134 #endif
3135 #ifdef EMLXS_LITTLE_ENDIAN
3136 			uint16_t	NumPages;
3137 			uint16_t	Rsvd1;
3138 #endif
3139 			MQ_CONTEXT	MQContext;
3140 			BE_PHYS_ADDR	Pages[8];
3141 		} request;
3142 
3143 		struct
3144 		{
3145 #ifdef EMLXS_BIG_ENDIAN
3146 			uint16_t	Rsvd1;
3147 			uint16_t	MQId;
3148 #endif
3149 #ifdef EMLXS_LITTLE_ENDIAN
3150 			uint16_t	MQId;
3151 			uint16_t	Rsvd1;
3152 #endif
3153 		} response;
3154 	} params;
3155 
3156 } IOCTL_COMMON_MQ_CREATE;
3157 
3158 
3159 /* IOCTL_FCOE_RQ_CREATE */
3160 typedef	struct
3161 {
3162 	union
3163 	{
3164 		struct
3165 		{
3166 #ifdef EMLXS_BIG_ENDIAN
3167 			uint8_t		rsvd0;
3168 			uint8_t		ulpNum;
3169 			uint16_t	NumPages;
3170 #endif
3171 #ifdef EMLXS_LITTLE_ENDIAN
3172 			uint16_t	NumPages;
3173 			uint8_t		ulpNum;
3174 			uint8_t		rsvd0;
3175 #endif
3176 			RQ_CONTEXT	RQContext;
3177 			BE_PHYS_ADDR	Pages[8];
3178 		} request;
3179 
3180 		struct
3181 		{
3182 #ifdef EMLXS_BIG_ENDIAN
3183 			uint16_t	Rsvd1;
3184 			uint16_t	RQId;
3185 #endif
3186 #ifdef EMLXS_LITTLE_ENDIAN
3187 			uint16_t	RQId;
3188 			uint16_t	Rsvd1;
3189 #endif
3190 		} response;
3191 
3192 	} params;
3193 
3194 } IOCTL_FCOE_RQ_CREATE;
3195 
3196 
3197 /* IOCTL_FCOE_WQ_CREATE */
3198 typedef	struct
3199 {
3200 	union
3201 	{
3202 		struct
3203 		{
3204 #ifdef EMLXS_BIG_ENDIAN
3205 			uint16_t	CQId;
3206 			uint16_t	NumPages;
3207 #endif
3208 #ifdef EMLXS_LITTLE_ENDIAN
3209 			uint16_t	NumPages;
3210 			uint16_t	CQId;
3211 #endif
3212 			BE_PHYS_ADDR	Pages[4];
3213 		} request;
3214 
3215 		struct
3216 		{
3217 #ifdef EMLXS_BIG_ENDIAN
3218 			uint16_t	Rsvd0;
3219 			uint16_t	WQId;
3220 #endif
3221 #ifdef EMLXS_LITTLE_ENDIAN
3222 			uint16_t	WQId;
3223 			uint16_t	Rsvd0;
3224 #endif
3225 		} response;
3226 
3227 	} params;
3228 
3229 } IOCTL_FCOE_WQ_CREATE;
3230 
3231 
3232 /* IOCTL_FCOE_CFG_POST_SGL_PAGES */
3233 typedef	struct _FCOE_SGL_PAGES
3234 {
3235 	BE_PHYS_ADDR	sgl_page0;	/* 1st page per XRI */
3236 	BE_PHYS_ADDR	sgl_page1;	/* 2nd page per XRI */
3237 
3238 } FCOE_SGL_PAGES;
3239 
3240 typedef	struct
3241 {
3242 	union
3243 	{
3244 		struct
3245 		{
3246 #ifdef EMLXS_BIG_ENDIAN
3247 			uint16_t	xri_count;
3248 			uint16_t	xri_start;
3249 #endif
3250 #ifdef EMLXS_LITTLE_ENDIAN
3251 			uint16_t	xri_start;
3252 			uint16_t	xri_count;
3253 #endif
3254 			FCOE_SGL_PAGES	pages[1];
3255 		} request;
3256 
3257 		struct
3258 		{
3259 			uint32_t	rsvd0;
3260 		} response;
3261 
3262 	} params;
3263 
3264 	uint32_t	rsvd0[2];
3265 
3266 } IOCTL_FCOE_CFG_POST_SGL_PAGES;
3267 
3268 
3269 /* IOCTL_FCOE_POST_HDR_TEMPLATES */
3270 typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES
3271 {
3272 	union
3273 	{
3274 		struct
3275 		{
3276 #ifdef EMLXS_BIG_ENDIAN
3277 			uint16_t	num_pages;
3278 			uint16_t	starting_rpi_index;
3279 #endif
3280 #ifdef EMLXS_LITTLE_ENDIAN
3281 			uint16_t	starting_rpi_index;
3282 			uint16_t	num_pages;
3283 #endif
3284 			BE_PHYS_ADDR	pages[32];
3285 
3286 		}request;
3287 
3288 	}params;
3289 
3290 } IOCTL_FCOE_POST_HDR_TEMPLATES;
3291 
3292 
3293 
3294 #define	EMLXS_IOCTL_DCBX_MODE_CEE	0	/* Mapped to FIP mode */
3295 #define	EMLXS_IOCTL_DCBX_MODE_CIN	1	/* Mapped to nonFIP mode */
3296 
3297 /* IOCTL_DCBX_GET_DCBX_MODE */
3298 typedef struct _IOCTL_DCBX_GET_DCBX_MODE
3299 {
3300 	union
3301 	{
3302 		struct
3303 		{
3304 #ifdef EMLXS_BIG_ENDIAN
3305 			uint8_t		rsvd0[3];
3306 			uint8_t		port_num;
3307 #endif
3308 #ifdef EMLXS_LITTLE_ENDIAN
3309 			uint8_t		port_num;
3310 			uint8_t		rsvd0[3];
3311 #endif
3312 		} request;
3313 
3314 		struct
3315 		{
3316 #ifdef EMLXS_BIG_ENDIAN
3317 			uint8_t		rsvd1[3];
3318 			uint8_t		dcbx_mode;
3319 #endif
3320 #ifdef EMLXS_LITTLE_ENDIAN
3321 			uint8_t		dcbx_mode;
3322 			uint8_t		rsvd1[3];
3323 #endif
3324 		} response;
3325 
3326 	} params;
3327 
3328 } IOCTL_DCBX_GET_DCBX_MODE;
3329 
3330 
3331 /* IOCTL_DCBX_SET_DCBX_MODE */
3332 typedef struct _IOCTL_DCBX_SET_DCBX_MODE
3333 {
3334 	union
3335 	{
3336 		struct
3337 		{
3338 #ifdef EMLXS_BIG_ENDIAN
3339 			uint8_t		rsvd0[2];
3340 			uint8_t		dcbx_mode;
3341 			uint8_t		port_num;
3342 #endif
3343 #ifdef EMLXS_LITTLE_ENDIAN
3344 			uint8_t		port_num;
3345 			uint8_t		dcbx_mode;
3346 			uint8_t		rsvd0[2];
3347 #endif
3348 		} request;
3349 
3350 		struct
3351 		{
3352 			uint32_t	rsvd1;
3353 		} response;
3354 
3355 	} params;
3356 
3357 } IOCTL_DCBX_SET_DCBX_MODE;
3358 
3359 
3360 /* IOCTL_COMMON_GET_CNTL_ATTRIB */
3361 typedef	struct
3362 {
3363 	char		flashrom_version_string[32];
3364 	char		manufacturer_name[32];
3365 	char		rsvd0[28];
3366 	uint32_t	default_extended_timeout;
3367 	char		controller_model_number[32];
3368 	char		controller_description[64];
3369 	char		controller_serial_number[32];
3370 	char		ip_version_string[32];
3371 	char		firmware_version_string[32];
3372 	char		bios_version_string[32];
3373 	char		redboot_version_string[32];
3374 	char		driver_version_string[32];
3375 	char		fw_on_flash_version_string[32];
3376 	uint32_t	functionalities_supported;
3377 	uint16_t	max_cdblength;
3378 	uint8_t		asic_revision;
3379 	uint8_t		generational_guid[16];
3380 	uint8_t		hba_port_count;
3381 	uint16_t	default_link_down_timeout;
3382 	uint8_t		iscsi_ver_min_max;
3383 	uint8_t		multifunction_device;
3384 	uint8_t		cache_valid;
3385 	uint8_t		hba_status;
3386 	uint8_t		max_domains_supported;
3387 	uint8_t		phy_port;
3388 	uint32_t	firmware_post_status;
3389 	uint32_t	hba_mtu[2];
3390 
3391 } MGMT_HBA_ATTRIB;
3392 
3393 typedef	struct
3394 {
3395 	MGMT_HBA_ATTRIB		hba_attribs;
3396 	uint16_t		pci_vendor_id;
3397 	uint16_t		pci_device_id;
3398 	uint16_t		pci_sub_vendor_id;
3399 	uint16_t		pci_sub_system_id;
3400 	uint8_t			pci_bus_number;
3401 	uint8_t			pci_device_number;
3402 	uint8_t			pci_function_number;
3403 	uint8_t			interface_type;
3404 	uint64_t		unique_identifier;
3405 
3406 } MGMT_CONTROLLER_ATTRIB;
3407 
3408 typedef	struct
3409 {
3410 	union
3411 	{
3412 		struct
3413 		{
3414 			uint32_t rsvd0;
3415 		} request;
3416 
3417 		struct
3418 		{
3419 			MGMT_CONTROLLER_ATTRIB cntl_attributes_info;
3420 		} response;
3421 
3422 	} params;
3423 
3424 } IOCTL_COMMON_GET_CNTL_ATTRIB;
3425 
3426 
3427 typedef	union
3428 {
3429 	IOCTL_COMMON_NOP		NOPVar;
3430 	IOCTL_FCOE_WQ_CREATE		WQCreateVar;
3431 	IOCTL_COMMON_EQ_CREATE		EQCreateVar;
3432 	IOCTL_COMMON_CQ_CREATE		CQCreateVar;
3433 	IOCTL_COMMON_MQ_CREATE		MQCreateVar;
3434 	IOCTL_FCOE_CFG_POST_SGL_PAGES	PostSGLVar;
3435 	IOCTL_COMMON_GET_CNTL_ATTRIB	GetCntlAttributesVar;
3436 	IOCTL_FCOE_READ_FCF_TABLE	ReadFCFTableVar;
3437 	IOCTL_FCOE_ADD_FCF_TABLE	AddFCFTableVar;
3438 	IOCTL_COMMON_FLASHROM		FlashRomVar;
3439 	IOCTL_COMMON_MANAGE_FAT		FATVar;
3440 	IOCTL_DCBX_GET_DCBX_MODE	GetDCBX;
3441 	IOCTL_DCBX_SET_DCBX_MODE	SetDCBX;
3442 
3443 } IOCTL_VARIANTS;
3444 
3445 /* Structure for MB Command SLI_CONFIG(0x9b) */
3446 /* Good for SLI4 only */
3447 
3448 typedef struct
3449 {
3450 	be_req_hdr_t	be;
3451 	BE_PHYS_ADDR	payload;
3452 } SLI_CONFIG_VAR;
3453 
3454 #define	IOCTL_HEADER_SZ	(4 * sizeof (uint32_t))
3455 
3456 
3457 typedef union
3458 {
3459 	uint32_t		varWords[63];
3460 	READ_NV_VAR		varRDnvp;	/* cmd = x02 (READ_NVPARMS) */
3461 	INIT_LINK_VAR		varInitLnk;	/* cmd = x05 (INIT_LINK) */
3462 	CONFIG_LINK		varCfgLnk;	/* cmd = x07 (CONFIG_LINK) */
3463 	READ_REV4_VAR		varRdRev4;	/* cmd = x11 (READ_REV) */
3464 	READ_LNK_VAR		varRdLnk;	/* cmd = x12 (READ_LNK_STAT) */
3465 	DUMP4_VAR		varDmp4;	/* cmd = x17 (DUMP) */
3466 	READ_SPARM_VAR		varRdSparm;	/* cmd = x8D (READ_SPARM64) */
3467 	REG_FCFI_VAR		varRegFCFI;	/* cmd = xA0 (REG_FCFI) */
3468 	UNREG_FCFI_VAR		varUnRegFCFI;	/* cmd = xA2 (UNREG_FCFI) */
3469 	READ_LA_VAR		varReadLA;	/* cmd = x95 (READ_LA64) */
3470 	READ_CONFIG4_VAR	varRdConfig4;	/* cmd = x0B (READ_CONFIG) */
3471 	RESUME_RPI_VAR		varResumeRPI;	/* cmd = x9E (RESUME_RPI) */
3472 	REG_LOGIN_VAR		varRegLogin;	/* cmd = x93 (REG_RPI) */
3473 	UNREG_LOGIN_VAR		varUnregLogin;	/* cmd = x14 (UNREG_RPI) */
3474 	REG_VPI_VAR		varRegVPI4;	/* cmd = x96 (REG_VPI) */
3475 	UNREG_VPI_VAR4		varUnRegVPI4;	/* cmd = x97 (UNREG_VPI) */
3476 	REG_VFI_VAR		varRegVFI4;	/* cmd = x9F (REG_VFI) */
3477 	UNREG_VFI_VAR		varUnRegVFI4;	/* cmd = xA1 (UNREG_VFI) */
3478 	REQUEST_FEATURES_VAR	varReqFeatures;	/* cmd = x9D (REQ_FEATURES) */
3479 	SLI_CONFIG_VAR		varSLIConfig;	/* cmd = x9B (SLI_CONFIG) */
3480 	INIT_VPI_VAR		varInitVPI4;	/* cmd = xA3 (INIT_VPI) */
3481 	INIT_VFI_VAR		varInitVFI4;	/* cmd = xA4 (INIT_VFI) */
3482 
3483 } MAILVARIANTS4;		/* Used for SLI-4 */
3484 
3485 #define	MAILBOX_CMD_SLI4_BSIZE	256
3486 #define	MAILBOX_CMD_SLI4_WSIZE	64
3487 
3488 #define	MAILBOX_CMD_MAX_BSIZE	256
3489 #define	MAILBOX_CMD_MAX_WSIZE	64
3490 
3491 
3492 typedef volatile struct
3493 {
3494 #ifdef EMLXS_BIG_ENDIAN
3495 	uint16_t	mbxStatus;
3496 	uint8_t		mbxCommand;
3497 	uint8_t		mbxReserved:6;
3498 	uint8_t		mbxHc:1;
3499 	uint8_t		mbxOwner:1;	/* Low order bit first word */
3500 #endif
3501 #ifdef EMLXS_LITTLE_ENDIAN
3502 	uint8_t		mbxOwner:1;	/* Low order bit first word */
3503 	uint8_t		mbxHc:1;
3504 	uint8_t		mbxReserved:6;
3505 	uint8_t		mbxCommand;
3506 	uint16_t	mbxStatus;
3507 #endif
3508 	MAILVARIANTS4	un;		/* 124 bytes */
3509 } MAILBOX4;				/* Used for SLI-4 */
3510 
3511 /*
3512  * End Structure Definitions for Mailbox Commands
3513  */
3514 
3515 
3516 typedef struct emlxs_mbq
3517 {
3518 	volatile uint32_t	mbox[MAILBOX_CMD_MAX_WSIZE];
3519 	struct emlxs_mbq	*next;
3520 
3521 	/* Defferred handling pointers */
3522 	uint8_t			*nonembed;	/* ptr to data buffer */
3523 						/* structure */
3524 	uint8_t			*bp;		/* ptr to data buffer */
3525 						/* structure */
3526 	uint8_t			*sbp;		/* ptr to emlxs_buf_t */
3527 						/* structure */
3528 	uint8_t			*ubp;		/* ptr to fc_unsol_buf_t */
3529 						/* structure */
3530 	uint8_t			*iocbq;		/* ptr to IOCBQ structure */
3531 	uint8_t			*context;	/* ptr to mbox context data */
3532 	uint32_t		flag;
3533 
3534 #define	MBQ_POOL_ALLOCATED	0x00000001
3535 #define	MBQ_PASSTHRU		0x00000002
3536 #define	MBQ_EMBEDDED		0x00000004
3537 #define	MBQ_BOOTSTRAP		0x00000008
3538 #define	MBQ_COMPLETED		0x00010000	/* Used for MBX_SLEEP */
3539 #define	MBQ_INIT_MASK		0x0000ffff
3540 
3541 #ifdef MBOX_EXT_SUPPORT
3542 	uint8_t			*extbuf;	/* ptr to mailbox ext buffer */
3543 	uint32_t		extsize;	/* size of mailbox ext buffer */
3544 #endif /* MBOX_EXT_SUPPORT */
3545 	int			(*mbox_cmpl)(void *, struct emlxs_mbq *);
3546 } emlxs_mbq_t;
3547 typedef emlxs_mbq_t MAILBOXQ;
3548 
3549 
3550 /* We currently do not support IOCBs in SLI1 mode */
3551 typedef struct
3552 {
3553 	MAILBOX		mbx;
3554 #ifdef MBOX_EXT_SUPPORT
3555 	uint8_t		mbxExt[MBOX_EXTENSION_SIZE];
3556 #endif /* MBOX_EXT_SUPPORT */
3557 	uint8_t		pad[(SLI_SLIM1_SIZE -
3558 				(sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))];
3559 } SLIM1;
3560 
3561 
3562 typedef struct
3563 {
3564 	MAILBOX		mbx;
3565 #ifdef MBOX_EXT_SUPPORT
3566 	uint8_t		mbxExt[MBOX_EXTENSION_SIZE];
3567 #endif /* MBOX_EXT_SUPPORT */
3568 	PCB		pcb;
3569 	uint8_t		IOCBs[SLI_IOCB_MAX_SIZE];
3570 } SLIM2;
3571 
3572 
3573 /* def for new 2MB Flash (Pegasus ...) */
3574 #define	MBX_LOAD_AREA		0x81
3575 #define	MBX_LOAD_EXP_ROM	0x9C
3576 
3577 #define	FILE_TYPE_AWC		0xE1A01001
3578 #define	FILE_TYPE_DWC		0xE1A02002
3579 #define	FILE_TYPE_BWC		0xE1A03003
3580 
3581 #define	AREA_ID_MASK		0xFFFFFF0F
3582 #define	AREA_ID_AWC		0x00000001
3583 #define	AREA_ID_DWC		0x00000002
3584 #define	AREA_ID_BWC		0x00000003
3585 
3586 #define	CMD_START_ERASE		1
3587 #define	CMD_CONTINUE_ERASE	2
3588 #define	CMD_DOWNLOAD		3
3589 #define	CMD_END_DOWNLOAD	4
3590 
3591 #define	RSP_ERASE_STARTED	1
3592 #define	RSP_ERASE_COMPLETE	2
3593 #define	RSP_DOWNLOAD_MORE	3
3594 #define	RSP_DOWNLOAD_DONE	4
3595 
3596 #define	EROM_CMD_FIND_IMAGE	8
3597 #define	EROM_CMD_CONTINUE_ERASE	9
3598 #define	EROM_CMD_COPY		10
3599 
3600 #define	EROM_RSP_ERASE_STARTED	8
3601 #define	EROM_RSP_ERASE_COMPLETE	9
3602 #define	EROM_RSP_COPY_MORE	10
3603 #define	EROM_RSP_COPY_DONE	11
3604 
3605 #define	ALLext			1
3606 #define	DWCext			2
3607 #define	BWCext			3
3608 
3609 #define	NO_ALL			0
3610 #define	ALL_WITHOUT_BWC		1
3611 #define	ALL_WITH_BWC		2
3612 
3613 #define	KERNEL_START_ADDRESS	0x000000
3614 #define	DOWNLOAD_START_ADDRESS	0x040000
3615 #define	EXP_ROM_START_ADDRESS	0x180000
3616 #define	SCRATCH_START_ADDRESS	0x1C0000
3617 #define	CONFIG_START_ADDRESS	0x1E0000
3618 
3619 
3620 typedef struct SliAifHdr
3621 {
3622 	uint32_t	CompressBr;
3623 	uint32_t	RelocBr;
3624 	uint32_t	ZinitBr;
3625 	uint32_t	EntryBr;
3626 	uint32_t	Area_ID;
3627 	uint32_t	RoSize;
3628 	uint32_t	RwSize;
3629 	uint32_t	DbgSize;
3630 	uint32_t	ZinitSize;
3631 	uint32_t	DbgType;
3632 	uint32_t	ImageBase;
3633 	uint32_t	Area_Size;
3634 	uint32_t	AddressMode;
3635 	uint32_t	DataBase;
3636 	uint32_t	AVersion;
3637 	uint32_t	Spare2;
3638 	uint32_t	DebugSwi;
3639 	uint32_t	ZinitCode[15];
3640 } AIF_HDR, *PAIF_HDR;
3641 
3642 typedef struct ImageHdr
3643 {
3644 	uint32_t	BlockSize;
3645 	PROG_ID		Id;
3646 	uint32_t	Flags;
3647 	uint32_t	EntryAdr;
3648 	uint32_t	InitAdr;
3649 	uint32_t	ExitAdr;
3650 	uint32_t	ImageBase;
3651 	uint32_t	ImageSize;
3652 	uint32_t	ZinitSize;
3653 	uint32_t	RelocSize;
3654 	uint32_t	HdrCks;
3655 } IMAGE_HDR, *PIMAGE_HDR;
3656 
3657 
3658 
3659 typedef struct
3660 {
3661 	PROG_ID		prog_id;
3662 #ifdef EMLXS_BIG_ENDIAN
3663 	uint32_t	pci_cfg_rsvd:27;
3664 	uint32_t	use_hdw_def:1;
3665 	uint32_t	pci_cfg_sel:3;
3666 	uint32_t	pci_cfg_lookup_sel:1;
3667 #endif
3668 #ifdef EMLXS_LITTLE_ENDIAN
3669 	uint32_t	pci_cfg_lookup_sel:1;
3670 	uint32_t	pci_cfg_sel:3;
3671 	uint32_t	use_hdw_def:1;
3672 	uint32_t	pci_cfg_rsvd:27;
3673 #endif
3674 	union
3675 	{
3676 		PROG_ID		boot_bios_id;
3677 		uint32_t	boot_bios_wd[2];
3678 	} u0;
3679 	PROG_ID		sli1_prog_id;
3680 	PROG_ID		sli2_prog_id;
3681 	PROG_ID		sli3_prog_id;
3682 	PROG_ID		sli4_prog_id;
3683 	union
3684 	{
3685 		PROG_ID		EROM_prog_id;
3686 		uint32_t	EROM_prog_wd[2];
3687 	} u1;
3688 } WAKE_UP_PARMS, *PWAKE_UP_PARMS;
3689 
3690 
3691 #define	PROG_DESCR_STR_LEN	24
3692 #define	MAX_LOAD_ENTRY		10
3693 
3694 typedef struct
3695 {
3696 	uint32_t	next;
3697 	uint32_t	prev;
3698 	uint32_t	start_adr;
3699 	uint32_t	len;
3700 	union
3701 	{
3702 		PROG_ID		id;
3703 		uint32_t	wd[2];
3704 	} un;
3705 	uint8_t		prog_descr[PROG_DESCR_STR_LEN];
3706 } LOAD_ENTRY;
3707 
3708 typedef struct
3709 {
3710 	uint32_t	head;
3711 	uint32_t	tail;
3712 	uint32_t	entry_cnt;
3713 	LOAD_ENTRY	load_entry[MAX_LOAD_ENTRY];
3714 } LOAD_LIST;
3715 
3716 #ifdef	__cplusplus
3717 }
3718 #endif
3719 
3720 #endif	/* _EMLXS_MBOX_H */
3721