xref: /illumos-gate/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_mbox.h (revision a3170057)

/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at
 * http://www.opensource.org/licenses/cddl1.txt.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2004-2012 Emulex. All rights reserved.
 * Use is subject to license terms.
 * Copyright 2020 RackTop Systems, Inc.
 */

#ifndef _EMLXS_MBOX_H
#define	_EMLXS_MBOX_H

#ifdef	__cplusplus
extern "C" {
#endif

/* SLI 2/3 Mailbox defines */

#define	MBOX_SIZE			256
#define	MBOX_EXTENSION_OFFSET		MBOX_SIZE

#ifdef MBOX_EXT_SUPPORT
#define	MBOX_EXTENSION_SIZE		1024
#else
#define	MBOX_EXTENSION_SIZE		0
#endif /* MBOX_EXT_SUPPORT */



/* ==== Mailbox Commands ==== */
#define	MBX_SHUTDOWN			0x00	/* terminate testing */
#define	MBX_LOAD_SM			0x01
#define	MBX_READ_NV			0x02
#define	MBX_WRITE_NV			0x03
#define	MBX_RUN_BIU_DIAG		0x04
#define	MBX_INIT_LINK			0x05
#define	MBX_DOWN_LINK			0x06
#define	MBX_CONFIG_LINK			0x07
#define	MBX_PART_SLIM			0x08
#define	MBX_CONFIG_RING			0x09
#define	MBX_RESET_RING			0x0A
#define	MBX_READ_CONFIG			0x0B
#define	MBX_READ_RCONFIG		0x0C
#define	MBX_READ_SPARM			0x0D
#define	MBX_READ_STATUS			0x0E
#define	MBX_READ_RPI			0x0F
#define	MBX_READ_XRI			0x10
#define	MBX_READ_REV			0x11
#define	MBX_READ_LNK_STAT		0x12
#define	MBX_REG_LOGIN			0x13
#define	MBX_UNREG_LOGIN			0x14  /* SLI2/3 */
#define	MBX_UNREG_RPI			0x14  /* SLI4 */
#define	MBX_READ_LA			0x15
#define	MBX_CLEAR_LA			0x16
#define	MBX_DUMP_MEMORY			0x17
#define	MBX_DUMP_CONTEXT		0x18
#define	MBX_RUN_DIAGS			0x19
#define	MBX_RESTART			0x1A
#define	MBX_UPDATE_CFG			0x1B
#define	MBX_DOWN_LOAD			0x1C
#define	MBX_DEL_LD_ENTRY		0x1D
#define	MBX_RUN_PROGRAM			0x1E
#define	MBX_SET_MASK			0x20
#define	MBX_SET_VARIABLE		0x21
#define	MBX_UNREG_D_ID			0x23
#define	MBX_KILL_BOARD			0x24
#define	MBX_CONFIG_FARP			0x25
#define	MBX_BEACON			0x2A
#define	MBX_READ_VPI			0x2B
#define	MBX_CONFIG_MSIX			0x30
#define	MBX_HEARTBEAT			0x31
#define	MBX_WRITE_VPARMS		0x32
#define	MBX_ASYNC_EVENT			0x33

#define	MBX_READ_EVENT_LOG_STATUS	0x37
#define	MBX_READ_EVENT_LOG		0x38
#define	MBX_WRITE_EVENT_LOG		0x39
#define	MBX_NV_LOG			0x3A
#define	MBX_PORT_CAPABILITIES		0x3B
#define	MBX_IOV_CONTROL			0x3C
#define	MBX_IOV_MBX			0x3D


#define	MBX_CONFIG_HBQ			0x7C  /* SLI3 */
#define	MBX_LOAD_AREA			0x81
#define	MBX_RUN_BIU_DIAG64		0x84
#define	MBX_GET_DEBUG			0x86
#define	MBX_CONFIG_PORT			0x88
#define	MBX_READ_SPARM64		0x8D
#define	MBX_READ_RPI64			0x8F
#define	MBX_CONFIG_MSI			0x90
#define	MBX_REG_LOGIN64			0x93 /* SLI2/3 */
#define	MBX_REG_RPI			0x93 /* SLI4 */
#define	MBX_READ_LA64			0x95 /* SLI2/3 */
#define	MBX_READ_TOPOLOGY		0x95 /* SLI4 */
#define	MBX_REG_VPI			0x96 /* NPIV */
#define	MBX_UNREG_VPI			0x97 /* NPIV */
#define	MBX_FLASH_WR_ULA		0x98
#define	MBX_SET_DEBUG			0x99
#define	MBX_SLI_CONFIG			0x9B
#define	MBX_LOAD_EXP_ROM		0x9C
#define	MBX_REQUEST_FEATURES		0x9D
#define	MBX_RESUME_RPI			0x9E
#define	MBX_REG_VFI			0x9F
#define	MBX_REG_FCFI			0xA0
#define	MBX_UNREG_VFI			0xA1
#define	MBX_UNREG_FCFI			0xA2
#define	MBX_INIT_VFI			0xA3
#define	MBX_INIT_VPI			0xA4
#define	MBX_ACCESS_VDATA		0xA5
#define	MBX_MAX_CMDS			0xA6


/*
 * Define Status
 */
#define	MBX_SUCCESS			0x0
#define	MBX_FAILURE			0x1
#define	MBXERR_NUM_IOCBS		0x2
#define	MBXERR_IOCBS_EXCEEDED		0x3
#define	MBXERR_BAD_RING_NUMBER		0x4
#define	MBXERR_MASK_ENTRIES_RANGE	0x5
#define	MBXERR_MASKS_EXCEEDED		0x6
#define	MBXERR_BAD_PROFILE		0x7
#define	MBXERR_BAD_DEF_CLASS		0x8
#define	MBXERR_BAD_MAX_RESPONDER	0x9
#define	MBXERR_BAD_MAX_ORIGINATOR	0xA
#define	MBXERR_RPI_REGISTERED		0xB
#define	MBXERR_RPI_FULL			0xC
#define	MBXERR_NO_RESOURCES		0xD
#define	MBXERR_BAD_RCV_LENGTH		0xE
#define	MBXERR_DMA_ERROR		0xF
#define	MBXERR_NOT_SUPPORTED		0x10
#define	MBXERR_UNSUPPORTED_FEATURE	0x11
#define	MBXERR_UNKNOWN_COMMAND		0x12
#define	MBXERR_BAD_IP_BIT		0x13
#define	MBXERR_BAD_PCB_ALIGN		0x14
#define	MBXERR_BAD_HBQ_ID		0x15
#define	MBXERR_BAD_HBQ_STATE		0x16
#define	MBXERR_BAD_HBQ_MASK_NUM		0x17
#define	MBXERR_BAD_HBQ_MASK_SUBSET	0x18
#define	MBXERR_HBQ_CREATE_FAIL		0x19
#define	MBXERR_HBQ_EXISTING		0x1A
#define	MBXERR_HBQ_RSPRING_FULL		0x1B
#define	MBXERR_HBQ_DUP_MASK		0x1C
#define	MBXERR_HBQ_INVAL_GET_PTR	0x1D
#define	MBXERR_BAD_HBQ_SIZE		0x1E
#define	MBXERR_BAD_HBQ_ORDER		0x1F
#define	MBXERR_INVALID_ID		0x20

#define	MBXERR_INVALID_VFI		0x30

#define	MBXERR_FLASH_WRITE_FAILED	0x100

#define	MBXERR_INVALID_LINKSPEED	0x500

#define	MBXERR_BAD_REDIRECT		0x900
#define	MBXERR_RING_ALREADY_CONFIG	0x901

#define	MBXERR_RING_INACTIVE		0xA00

#define	MBXERR_RPI_INACTIVE		0xF00

#define	MBXERR_NO_ACTIVE_XRI		0x1100
#define	MBXERR_XRI_NOT_ACTIVE		0x1101

#define	MBXERR_RPI_INUSE		0x1400

#define	MBXERR_NO_LINK_ATTENTION	0x1500

#define	MBXERR_INVALID_SLI_MODE		0x8800
#define	MBXERR_INVALID_HOST_PTR		0x8801
#define	MBXERR_CANT_CFG_SLI_MODE	0x8802
#define	MBXERR_BAD_OVERLAY		0x8803
#define	MBXERR_INVALID_FEAT_REQ		0x8804

#define	MBXERR_CONFIG_CANT_COMPLETE	0x88FF

#define	MBXERR_DID_ALREADY_REGISTERED	0x9600
#define	MBXERR_DID_INCONSISTENT		0x9601
#define	MBXERR_VPI_TOO_LARGE		0x9603

#define	MBXERR_STILL_ASSOCIATED		0x9700

#define	MBXERR_INVALID_VF_STATE		0x9F00
#define	MBXERR_VFI_ALREADY_REGISTERED	0x9F02
#define	MBXERR_VFI_TOO_LARGE		0x9F03

#define	MBXERR_LOAD_FW_FAILED		0xFFFE
#define	MBXERR_FIND_FW_FAILED		0xFFFF

/* Driver special codes */
#define	MBX_DRIVER_RESERVED		0xF9 /* Set to lowest drv status */
#define	MBX_NONEMBED_ERROR		0xF9
#define	MBX_OVERTEMP_ERROR		0xFA
#define	MBX_HARDWARE_ERROR		0xFB
#define	MBX_DRVR_ERROR			0xFC
#define	MBX_BUSY			0xFD
#define	MBX_TIMEOUT			0xFE
#define	MBX_NOT_FINISHED		0xFF

/*
 * flags for EMLXS_SLI_ISSUE_MBOX_CMD()
 */
#define	MBX_POLL	0x01	/* poll mailbox till command done, */
				/* then return */
#define	MBX_SLEEP	0x02	/* sleep till mailbox intr cmpl */
				/* wakes thread up */
#define	MBX_WAIT	0x03	/* wait for comand done, then return */
#define	MBX_NOWAIT	0x04	/* issue command then return immediately */
#define	MBX_BOOTSTRAP	0x80	/* issue a command on the bootstrap mbox */



/*
 * Begin Structure Definitions for Mailbox Commands
 */

typedef struct revcompat
{
#ifdef EMLXS_BIG_ENDIAN
	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
	uint32_t	ldcount:7;	/* For use by program load */
	uint32_t	kernel:4;	/* Kernel ID */
	uint32_t	kver:4;	/* Kernel compatibility version */
	uint32_t	SMver:4;	/* Sequence Manager version */
					/* 0 if none */
	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
	uint32_t	BIUtype:4;	/* PCI = 0 */
	uint32_t	BIUver:4;	/* BIU version, 0 if none */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint32_t	BIUver:4;	/* BIU version, 0 if none */
	uint32_t	BIUtype:4;	/* PCI = 0 */
	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
	uint32_t	SMver:4;	/* Sequence Manager version */
					/* 0 if none */
	uint32_t	kver:4;	/* Kernel compatibility version */
	uint32_t	kernel:4;	/* Kernel ID */
	uint32_t	ldcount:7;	/* For use by program load */
	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
#endif
} REVCOMPAT;

typedef struct id_word
{
#ifdef EMLXS_BIG_ENDIAN
	uint8_t		Type;
	uint8_t		Id;
	uint8_t		Ver;
	uint8_t		Rev;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		Rev;
	uint8_t		Ver;
	uint8_t		Id;
	uint8_t		Type;
#endif
	union
	{
		REVCOMPAT	cp;
		uint32_t	revcomp;
	} un;
} PROG_ID;

typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
	uint8_t		tval;
	uint8_t		tmask;
	uint8_t		rval;
	uint8_t		rmask;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		rmask;
	uint8_t		rval;
	uint8_t		tmask;
	uint8_t		tval;
#endif
} RR_REG;


/* Structure used for a HBQ entry */
typedef struct
{
	ULP_BDE64	bde;
	union UN_TAG
	{
		uint32_t	w;
		struct
		{
#ifdef EMLXS_BIG_ENDIAN
			uint32_t	HBQ_tag:4;
			uint32_t	HBQE_tag:28;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
			uint32_t	HBQE_tag:28;
			uint32_t	HBQ_tag:4;
#endif
		} ext;
	} unt;
} HBQE_t;

typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
	uint8_t		tmatch;
	uint8_t		tmask;
	uint8_t		rctlmatch;
	uint8_t		rctlmask;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
	uint8_t		rctlmask;
	uint8_t		rctlmatch;
	uint8_t		tmask;
	uint8_t		tmatch;
#endif
} HBQ_MASK;

#define	EMLXS_MAX_HBQ_BUFFERS	4096

typedef struct
{
	uint32_t	HBQ_num_mask;		/* number of mask entries in */
						/* port array */
	uint32_t	HBQ_recvNotify;		/* Rcv buffer notification */
	uint32_t	HBQ_numEntries;		/* # of entries in HBQ */
	uint32_t	HBQ_headerLen;		/* 0 if not profile 4 or 5 */
	uint32_t	HBQ_logEntry;		/* Set to 1 if this HBQ used */
						/* for LogEntry */
	uint32_t	HBQ_profile;		/* Selection profile 0=all, */
						/* 7=logentry */
	uint32_t	HBQ_ringMask;		/* Binds HBQ to a ring e.g. */
						/* Ring0=b0001, ring2=b0100 */
	uint32_t	HBQ_id;			/* index of this hbq in ring */
						/* of HBQs[] */
	uint32_t	HBQ_PutIdx_next;	/* Index to next HBQ slot to */
						/* use */
	uint32_t	HBQ_PutIdx;		/* HBQ slot to use */
	uint32_t	HBQ_GetIdx;		/* Local copy of Get index */
						/* from Port */
	uint16_t	HBQ_PostBufCnt;		/* Current number of entries */
						/* in list */