182527734SSukumar Swaminathan /* 282527734SSukumar Swaminathan * CDDL HEADER START 382527734SSukumar Swaminathan * 482527734SSukumar Swaminathan * The contents of this file are subject to the terms of the 582527734SSukumar Swaminathan * Common Development and Distribution License (the "License"). 682527734SSukumar Swaminathan * You may not use this file except in compliance with the License. 782527734SSukumar Swaminathan * 88f23e9faSHans Rosenfeld * You can obtain a copy of the license at 98f23e9faSHans Rosenfeld * http://www.opensource.org/licenses/cddl1.txt. 1082527734SSukumar Swaminathan * See the License for the specific language governing permissions 1182527734SSukumar Swaminathan * and limitations under the License. 1282527734SSukumar Swaminathan * 1382527734SSukumar Swaminathan * When distributing Covered Code, include this CDDL HEADER in each 1482527734SSukumar Swaminathan * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1582527734SSukumar Swaminathan * If applicable, add the following below this CDDL HEADER, with the 1682527734SSukumar Swaminathan * fields enclosed by brackets "[]" replaced with your own identifying 1782527734SSukumar Swaminathan * information: Portions Copyright [yyyy] [name of copyright owner] 1882527734SSukumar Swaminathan * 1982527734SSukumar Swaminathan * CDDL HEADER END 2082527734SSukumar Swaminathan */ 2182527734SSukumar Swaminathan 2282527734SSukumar Swaminathan /* 238f23e9faSHans Rosenfeld * Copyright (c) 2004-2012 Emulex. All rights reserved. 2482527734SSukumar Swaminathan * Use is subject to license terms. 25*a3170057SPaul Winder * Copyright 2020 RackTop Systems, Inc. 2682527734SSukumar Swaminathan */ 2782527734SSukumar Swaminathan 2882527734SSukumar Swaminathan #ifndef _EMLXS_MBOX_H 2982527734SSukumar Swaminathan #define _EMLXS_MBOX_H 3082527734SSukumar Swaminathan 3182527734SSukumar Swaminathan #ifdef __cplusplus 3282527734SSukumar Swaminathan extern "C" { 3382527734SSukumar Swaminathan #endif 3482527734SSukumar Swaminathan 3582527734SSukumar Swaminathan /* SLI 2/3 Mailbox defines */ 3682527734SSukumar Swaminathan 3782527734SSukumar Swaminathan #define MBOX_SIZE 256 3882527734SSukumar Swaminathan #define MBOX_EXTENSION_OFFSET MBOX_SIZE 3982527734SSukumar Swaminathan 4082527734SSukumar Swaminathan #ifdef MBOX_EXT_SUPPORT 4182527734SSukumar Swaminathan #define MBOX_EXTENSION_SIZE 1024 4282527734SSukumar Swaminathan #else 4382527734SSukumar Swaminathan #define MBOX_EXTENSION_SIZE 0 4482527734SSukumar Swaminathan #endif /* MBOX_EXT_SUPPORT */ 4582527734SSukumar Swaminathan 4682527734SSukumar Swaminathan 4782527734SSukumar Swaminathan 4882527734SSukumar Swaminathan /* ==== Mailbox Commands ==== */ 4982527734SSukumar Swaminathan #define MBX_SHUTDOWN 0x00 /* terminate testing */ 5082527734SSukumar Swaminathan #define MBX_LOAD_SM 0x01 5182527734SSukumar Swaminathan #define MBX_READ_NV 0x02 5282527734SSukumar Swaminathan #define MBX_WRITE_NV 0x03 5382527734SSukumar Swaminathan #define MBX_RUN_BIU_DIAG 0x04 5482527734SSukumar Swaminathan #define MBX_INIT_LINK 0x05 5582527734SSukumar Swaminathan #define MBX_DOWN_LINK 0x06 5682527734SSukumar Swaminathan #define MBX_CONFIG_LINK 0x07 5782527734SSukumar Swaminathan #define MBX_PART_SLIM 0x08 5882527734SSukumar Swaminathan #define MBX_CONFIG_RING 0x09 5982527734SSukumar Swaminathan #define MBX_RESET_RING 0x0A 6082527734SSukumar Swaminathan #define MBX_READ_CONFIG 0x0B 6182527734SSukumar Swaminathan #define MBX_READ_RCONFIG 0x0C 6282527734SSukumar Swaminathan #define MBX_READ_SPARM 0x0D 6382527734SSukumar Swaminathan #define MBX_READ_STATUS 0x0E 6482527734SSukumar Swaminathan #define MBX_READ_RPI 0x0F 6582527734SSukumar Swaminathan #define MBX_READ_XRI 0x10 6682527734SSukumar Swaminathan #define MBX_READ_REV 0x11 6782527734SSukumar Swaminathan #define MBX_READ_LNK_STAT 0x12 6882527734SSukumar Swaminathan #define MBX_REG_LOGIN 0x13 6982527734SSukumar Swaminathan #define MBX_UNREG_LOGIN 0x14 /* SLI2/3 */ 7082527734SSukumar Swaminathan #define MBX_UNREG_RPI 0x14 /* SLI4 */ 7182527734SSukumar Swaminathan #define MBX_READ_LA 0x15 7282527734SSukumar Swaminathan #define MBX_CLEAR_LA 0x16 7382527734SSukumar Swaminathan #define MBX_DUMP_MEMORY 0x17 7482527734SSukumar Swaminathan #define MBX_DUMP_CONTEXT 0x18 7582527734SSukumar Swaminathan #define MBX_RUN_DIAGS 0x19 7682527734SSukumar Swaminathan #define MBX_RESTART 0x1A 7782527734SSukumar Swaminathan #define MBX_UPDATE_CFG 0x1B 7882527734SSukumar Swaminathan #define MBX_DOWN_LOAD 0x1C 7982527734SSukumar Swaminathan #define MBX_DEL_LD_ENTRY 0x1D 8082527734SSukumar Swaminathan #define MBX_RUN_PROGRAM 0x1E 8182527734SSukumar Swaminathan #define MBX_SET_MASK 0x20 8282527734SSukumar Swaminathan #define MBX_SET_VARIABLE 0x21 8382527734SSukumar Swaminathan #define MBX_UNREG_D_ID 0x23 8482527734SSukumar Swaminathan #define MBX_KILL_BOARD 0x24 8582527734SSukumar Swaminathan #define MBX_CONFIG_FARP 0x25 8682527734SSukumar Swaminathan #define MBX_BEACON 0x2A 8782527734SSukumar Swaminathan #define MBX_READ_VPI 0x2B 8882527734SSukumar Swaminathan #define MBX_CONFIG_MSIX 0x30 8982527734SSukumar Swaminathan #define MBX_HEARTBEAT 0x31 9082527734SSukumar Swaminathan #define MBX_WRITE_VPARMS 0x32 9182527734SSukumar Swaminathan #define MBX_ASYNC_EVENT 0x33 9282527734SSukumar Swaminathan 9382527734SSukumar Swaminathan #define MBX_READ_EVENT_LOG_STATUS 0x37 9482527734SSukumar Swaminathan #define MBX_READ_EVENT_LOG 0x38 9582527734SSukumar Swaminathan #define MBX_WRITE_EVENT_LOG 0x39 9682527734SSukumar Swaminathan #define MBX_NV_LOG 0x3A 9782527734SSukumar Swaminathan #define MBX_PORT_CAPABILITIES 0x3B 9882527734SSukumar Swaminathan #define MBX_IOV_CONTROL 0x3C 9982527734SSukumar Swaminathan #define MBX_IOV_MBX 0x3D 10082527734SSukumar Swaminathan 10182527734SSukumar Swaminathan 10282527734SSukumar Swaminathan #define MBX_CONFIG_HBQ 0x7C /* SLI3 */ 10382527734SSukumar Swaminathan #define MBX_LOAD_AREA 0x81 10482527734SSukumar Swaminathan #define MBX_RUN_BIU_DIAG64 0x84 10582527734SSukumar Swaminathan #define MBX_GET_DEBUG 0x86 10682527734SSukumar Swaminathan #define MBX_CONFIG_PORT 0x88 10782527734SSukumar Swaminathan #define MBX_READ_SPARM64 0x8D 10882527734SSukumar Swaminathan #define MBX_READ_RPI64 0x8F 10982527734SSukumar Swaminathan #define MBX_CONFIG_MSI 0x90 1108f23e9faSHans Rosenfeld #define MBX_REG_LOGIN64 0x93 /* SLI2/3 */ 1118f23e9faSHans Rosenfeld #define MBX_REG_RPI 0x93 /* SLI4 */ 1128f23e9faSHans Rosenfeld #define MBX_READ_LA64 0x95 /* SLI2/3 */ 1138f23e9faSHans Rosenfeld #define MBX_READ_TOPOLOGY 0x95 /* SLI4 */ 1148f23e9faSHans Rosenfeld #define MBX_REG_VPI 0x96 /* NPIV */ 1158f23e9faSHans Rosenfeld #define MBX_UNREG_VPI 0x97 /* NPIV */ 11682527734SSukumar Swaminathan #define MBX_FLASH_WR_ULA 0x98 11782527734SSukumar Swaminathan #define MBX_SET_DEBUG 0x99 11882527734SSukumar Swaminathan #define MBX_SLI_CONFIG 0x9B 11982527734SSukumar Swaminathan #define MBX_LOAD_EXP_ROM 0x9C 12082527734SSukumar Swaminathan #define MBX_REQUEST_FEATURES 0x9D 12182527734SSukumar Swaminathan #define MBX_RESUME_RPI 0x9E 12282527734SSukumar Swaminathan #define MBX_REG_VFI 0x9F 12382527734SSukumar Swaminathan #define MBX_REG_FCFI 0xA0 12482527734SSukumar Swaminathan #define MBX_UNREG_VFI 0xA1 12582527734SSukumar Swaminathan #define MBX_UNREG_FCFI 0xA2 12682527734SSukumar Swaminathan #define MBX_INIT_VFI 0xA3 12782527734SSukumar Swaminathan #define MBX_INIT_VPI 0xA4 12882527734SSukumar Swaminathan #define MBX_ACCESS_VDATA 0xA5 12982527734SSukumar Swaminathan #define MBX_MAX_CMDS 0xA6 13082527734SSukumar Swaminathan 13182527734SSukumar Swaminathan 13282527734SSukumar Swaminathan /* 13382527734SSukumar Swaminathan * Define Status 13482527734SSukumar Swaminathan */ 13582527734SSukumar Swaminathan #define MBX_SUCCESS 0x0 13682527734SSukumar Swaminathan #define MBX_FAILURE 0x1 13782527734SSukumar Swaminathan #define MBXERR_NUM_IOCBS 0x2 13882527734SSukumar Swaminathan #define MBXERR_IOCBS_EXCEEDED 0x3 13982527734SSukumar Swaminathan #define MBXERR_BAD_RING_NUMBER 0x4 14082527734SSukumar Swaminathan #define MBXERR_MASK_ENTRIES_RANGE 0x5 14182527734SSukumar Swaminathan #define MBXERR_MASKS_EXCEEDED 0x6 14282527734SSukumar Swaminathan #define MBXERR_BAD_PROFILE 0x7 14382527734SSukumar Swaminathan #define MBXERR_BAD_DEF_CLASS 0x8 14482527734SSukumar Swaminathan #define MBXERR_BAD_MAX_RESPONDER 0x9 14582527734SSukumar Swaminathan #define MBXERR_BAD_MAX_ORIGINATOR 0xA 14682527734SSukumar Swaminathan #define MBXERR_RPI_REGISTERED 0xB 14782527734SSukumar Swaminathan #define MBXERR_RPI_FULL 0xC 14882527734SSukumar Swaminathan #define MBXERR_NO_RESOURCES 0xD 14982527734SSukumar Swaminathan #define MBXERR_BAD_RCV_LENGTH 0xE 15082527734SSukumar Swaminathan #define MBXERR_DMA_ERROR 0xF 15182527734SSukumar Swaminathan #define MBXERR_NOT_SUPPORTED 0x10 15282527734SSukumar Swaminathan #define MBXERR_UNSUPPORTED_FEATURE 0x11 15382527734SSukumar Swaminathan #define MBXERR_UNKNOWN_COMMAND 0x12 1548f23e9faSHans Rosenfeld #define MBXERR_BAD_IP_BIT 0x13 1558f23e9faSHans Rosenfeld #define MBXERR_BAD_PCB_ALIGN 0x14 1568f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_ID 0x15 1578f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_STATE 0x16 1588f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_MASK_NUM 0x17 1598f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_MASK_SUBSET 0x18 1608f23e9faSHans Rosenfeld #define MBXERR_HBQ_CREATE_FAIL 0x19 1618f23e9faSHans Rosenfeld #define MBXERR_HBQ_EXISTING 0x1A 1628f23e9faSHans Rosenfeld #define MBXERR_HBQ_RSPRING_FULL 0x1B 1638f23e9faSHans Rosenfeld #define MBXERR_HBQ_DUP_MASK 0x1C 1648f23e9faSHans Rosenfeld #define MBXERR_HBQ_INVAL_GET_PTR 0x1D 1658f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_SIZE 0x1E 1668f23e9faSHans Rosenfeld #define MBXERR_BAD_HBQ_ORDER 0x1F 1678f23e9faSHans Rosenfeld #define MBXERR_INVALID_ID 0x20 1688f23e9faSHans Rosenfeld 1698f23e9faSHans Rosenfeld #define MBXERR_INVALID_VFI 0x30 1708f23e9faSHans Rosenfeld 1718f23e9faSHans Rosenfeld #define MBXERR_FLASH_WRITE_FAILED 0x100 1728f23e9faSHans Rosenfeld 1738f23e9faSHans Rosenfeld #define MBXERR_INVALID_LINKSPEED 0x500 1748f23e9faSHans Rosenfeld 1758f23e9faSHans Rosenfeld #define MBXERR_BAD_REDIRECT 0x900 1768f23e9faSHans Rosenfeld #define MBXERR_RING_ALREADY_CONFIG 0x901 1778f23e9faSHans Rosenfeld 1788f23e9faSHans Rosenfeld #define MBXERR_RING_INACTIVE 0xA00 1798f23e9faSHans Rosenfeld 1808f23e9faSHans Rosenfeld #define MBXERR_RPI_INACTIVE 0xF00 1818f23e9faSHans Rosenfeld 1828f23e9faSHans Rosenfeld #define MBXERR_NO_ACTIVE_XRI 0x1100 1838f23e9faSHans Rosenfeld #define MBXERR_XRI_NOT_ACTIVE 0x1101 1848f23e9faSHans Rosenfeld 1858f23e9faSHans Rosenfeld #define MBXERR_RPI_INUSE 0x1400 1868f23e9faSHans Rosenfeld 1878f23e9faSHans Rosenfeld #define MBXERR_NO_LINK_ATTENTION 0x1500 1888f23e9faSHans Rosenfeld 1898f23e9faSHans Rosenfeld #define MBXERR_INVALID_SLI_MODE 0x8800 1908f23e9faSHans Rosenfeld #define MBXERR_INVALID_HOST_PTR 0x8801 1918f23e9faSHans Rosenfeld #define MBXERR_CANT_CFG_SLI_MODE 0x8802 1928f23e9faSHans Rosenfeld #define MBXERR_BAD_OVERLAY 0x8803 1938f23e9faSHans Rosenfeld #define MBXERR_INVALID_FEAT_REQ 0x8804 1948f23e9faSHans Rosenfeld 1958f23e9faSHans Rosenfeld #define MBXERR_CONFIG_CANT_COMPLETE 0x88FF 1968f23e9faSHans Rosenfeld 1978f23e9faSHans Rosenfeld #define MBXERR_DID_ALREADY_REGISTERED 0x9600 1988f23e9faSHans Rosenfeld #define MBXERR_DID_INCONSISTENT 0x9601 1998f23e9faSHans Rosenfeld #define MBXERR_VPI_TOO_LARGE 0x9603 2008f23e9faSHans Rosenfeld 2018f23e9faSHans Rosenfeld #define MBXERR_STILL_ASSOCIATED 0x9700 2028f23e9faSHans Rosenfeld 2038f23e9faSHans Rosenfeld #define MBXERR_INVALID_VF_STATE 0x9F00 2048f23e9faSHans Rosenfeld #define MBXERR_VFI_ALREADY_REGISTERED 0x9F02 2058f23e9faSHans Rosenfeld #define MBXERR_VFI_TOO_LARGE 0x9F03 2068f23e9faSHans Rosenfeld 2078f23e9faSHans Rosenfeld #define MBXERR_LOAD_FW_FAILED 0xFFFE 2088f23e9faSHans Rosenfeld #define MBXERR_FIND_FW_FAILED 0xFFFF 20982527734SSukumar Swaminathan 21082527734SSukumar Swaminathan /* Driver special codes */ 21182527734SSukumar Swaminathan #define MBX_DRIVER_RESERVED 0xF9 /* Set to lowest drv status */ 21282527734SSukumar Swaminathan #define MBX_NONEMBED_ERROR 0xF9 21382527734SSukumar Swaminathan #define MBX_OVERTEMP_ERROR 0xFA 21482527734SSukumar Swaminathan #define MBX_HARDWARE_ERROR 0xFB 21582527734SSukumar Swaminathan #define MBX_DRVR_ERROR 0xFC 21682527734SSukumar Swaminathan #define MBX_BUSY 0xFD 21782527734SSukumar Swaminathan #define MBX_TIMEOUT 0xFE 21882527734SSukumar Swaminathan #define MBX_NOT_FINISHED 0xFF 21982527734SSukumar Swaminathan 22082527734SSukumar Swaminathan /* 22182527734SSukumar Swaminathan * flags for EMLXS_SLI_ISSUE_MBOX_CMD() 22282527734SSukumar Swaminathan */ 22382527734SSukumar Swaminathan #define MBX_POLL 0x01 /* poll mailbox till command done, */ 22482527734SSukumar Swaminathan /* then return */ 22582527734SSukumar Swaminathan #define MBX_SLEEP 0x02 /* sleep till mailbox intr cmpl */ 22682527734SSukumar Swaminathan /* wakes thread up */ 22782527734SSukumar Swaminathan #define MBX_WAIT 0x03 /* wait for comand done, then return */ 22882527734SSukumar Swaminathan #define MBX_NOWAIT 0x04 /* issue command then return immediately */ 22982527734SSukumar Swaminathan #define MBX_BOOTSTRAP 0x80 /* issue a command on the bootstrap mbox */ 23082527734SSukumar Swaminathan 23182527734SSukumar Swaminathan 23282527734SSukumar Swaminathan 23382527734SSukumar Swaminathan /* 23482527734SSukumar Swaminathan * Begin Structure Definitions for Mailbox Commands 23582527734SSukumar Swaminathan */ 23682527734SSukumar Swaminathan 23782527734SSukumar Swaminathan typedef struct revcompat 23882527734SSukumar Swaminathan { 23982527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 24082527734SSukumar Swaminathan uint32_t ldflag:1; /* Set in SRAM descriptor */ 24182527734SSukumar Swaminathan uint32_t ldcount:7; /* For use by program load */ 24282527734SSukumar Swaminathan uint32_t kernel:4; /* Kernel ID */ 24382527734SSukumar Swaminathan uint32_t kver:4; /* Kernel compatibility version */ 24482527734SSukumar Swaminathan uint32_t SMver:4; /* Sequence Manager version */ 24582527734SSukumar Swaminathan /* 0 if none */ 24682527734SSukumar Swaminathan uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */ 24782527734SSukumar Swaminathan uint32_t BIUtype:4; /* PCI = 0 */ 24882527734SSukumar Swaminathan uint32_t BIUver:4; /* BIU version, 0 if none */ 24982527734SSukumar Swaminathan #endif 25082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 25182527734SSukumar Swaminathan uint32_t BIUver:4; /* BIU version, 0 if none */ 25282527734SSukumar Swaminathan uint32_t BIUtype:4; /* PCI = 0 */ 25382527734SSukumar Swaminathan uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */ 25482527734SSukumar Swaminathan uint32_t SMver:4; /* Sequence Manager version */ 25582527734SSukumar Swaminathan /* 0 if none */ 25682527734SSukumar Swaminathan uint32_t kver:4; /* Kernel compatibility version */ 25782527734SSukumar Swaminathan uint32_t kernel:4; /* Kernel ID */ 25882527734SSukumar Swaminathan uint32_t ldcount:7; /* For use by program load */ 25982527734SSukumar Swaminathan uint32_t ldflag:1; /* Set in SRAM descriptor */ 26082527734SSukumar Swaminathan #endif 26182527734SSukumar Swaminathan } REVCOMPAT; 26282527734SSukumar Swaminathan 26382527734SSukumar Swaminathan typedef struct id_word 26482527734SSukumar Swaminathan { 26582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 26682527734SSukumar Swaminathan uint8_t Type; 26782527734SSukumar Swaminathan uint8_t Id; 26882527734SSukumar Swaminathan uint8_t Ver; 26982527734SSukumar Swaminathan uint8_t Rev; 27082527734SSukumar Swaminathan #endif 27182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 27282527734SSukumar Swaminathan uint8_t Rev; 27382527734SSukumar Swaminathan uint8_t Ver; 27482527734SSukumar Swaminathan uint8_t Id; 27582527734SSukumar Swaminathan uint8_t Type; 27682527734SSukumar Swaminathan #endif 27782527734SSukumar Swaminathan union 27882527734SSukumar Swaminathan { 27982527734SSukumar Swaminathan REVCOMPAT cp; 28082527734SSukumar Swaminathan uint32_t revcomp; 28182527734SSukumar Swaminathan } un; 28282527734SSukumar Swaminathan } PROG_ID; 28382527734SSukumar Swaminathan 28482527734SSukumar Swaminathan typedef struct 28582527734SSukumar Swaminathan { 28682527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 28782527734SSukumar Swaminathan uint8_t tval; 28882527734SSukumar Swaminathan uint8_t tmask; 28982527734SSukumar Swaminathan uint8_t rval; 29082527734SSukumar Swaminathan uint8_t rmask; 29182527734SSukumar Swaminathan #endif 29282527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 29382527734SSukumar Swaminathan uint8_t rmask; 29482527734SSukumar Swaminathan uint8_t rval; 29582527734SSukumar Swaminathan uint8_t tmask; 29682527734SSukumar Swaminathan uint8_t tval; 29782527734SSukumar Swaminathan #endif 29882527734SSukumar Swaminathan } RR_REG; 29982527734SSukumar Swaminathan 30082527734SSukumar Swaminathan 30182527734SSukumar Swaminathan /* Structure used for a HBQ entry */ 30282527734SSukumar Swaminathan typedef struct 30382527734SSukumar Swaminathan { 30482527734SSukumar Swaminathan ULP_BDE64 bde; 30582527734SSukumar Swaminathan union UN_TAG 30682527734SSukumar Swaminathan { 30782527734SSukumar Swaminathan uint32_t w; 30882527734SSukumar Swaminathan struct 30982527734SSukumar Swaminathan { 31082527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 31182527734SSukumar Swaminathan uint32_t HBQ_tag:4; 31282527734SSukumar Swaminathan uint32_t HBQE_tag:28; 31382527734SSukumar Swaminathan #endif 31482527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 31582527734SSukumar Swaminathan uint32_t HBQE_tag:28; 31682527734SSukumar Swaminathan uint32_t HBQ_tag:4; 31782527734SSukumar Swaminathan #endif 31882527734SSukumar Swaminathan } ext; 31982527734SSukumar Swaminathan } unt; 32082527734SSukumar Swaminathan } HBQE_t; 32182527734SSukumar Swaminathan 32282527734SSukumar Swaminathan typedef struct 32382527734SSukumar Swaminathan { 32482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 32582527734SSukumar Swaminathan uint8_t tmatch; 32682527734SSukumar Swaminathan uint8_t tmask; 32782527734SSukumar Swaminathan uint8_t rctlmatch; 32882527734SSukumar Swaminathan uint8_t rctlmask; 32982527734SSukumar Swaminathan #endif 33082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 33182527734SSukumar Swaminathan uint8_t rctlmask; 33282527734SSukumar Swaminathan uint8_t rctlmatch; 33382527734SSukumar Swaminathan uint8_t tmask; 33482527734SSukumar Swaminathan uint8_t tmatch; 33582527734SSukumar Swaminathan #endif 33682527734SSukumar Swaminathan } HBQ_MASK; 33782527734SSukumar Swaminathan 33882527734SSukumar Swaminathan #define EMLXS_MAX_HBQ_BUFFERS 4096 33982527734SSukumar Swaminathan 34082527734SSukumar Swaminathan typedef struct 34182527734SSukumar Swaminathan { 34282527734SSukumar Swaminathan uint32_t HBQ_num_mask; /* number of mask entries in */ 34382527734SSukumar Swaminathan /* port array */ 34482527734SSukumar Swaminathan uint32_t HBQ_recvNotify; /* Rcv buffer notification */ 34582527734SSukumar Swaminathan uint32_t HBQ_numEntries; /* # of entries in HBQ */ 34682527734SSukumar Swaminathan uint32_t HBQ_headerLen; /* 0 if not profile 4 or 5 */ 34782527734SSukumar Swaminathan uint32_t HBQ_logEntry; /* Set to 1 if this HBQ used */ 34882527734SSukumar Swaminathan /* for LogEntry */ 34982527734SSukumar Swaminathan uint32_t HBQ_profile; /* Selection profile 0=all, */ 35082527734SSukumar Swaminathan /* 7=logentry */ 35182527734SSukumar Swaminathan uint32_t HBQ_ringMask; /* Binds HBQ to a ring e.g. */ 35282527734SSukumar Swaminathan /* Ring0=b0001, ring2=b0100 */ 35382527734SSukumar Swaminathan uint32_t HBQ_id; /* index of this hbq in ring */ 35482527734SSukumar Swaminathan /* of HBQs[] */ 35582527734SSukumar Swaminathan uint32_t HBQ_PutIdx_next; /* Index to next HBQ slot to */ 35682527734SSukumar Swaminathan /* use */ 35782527734SSukumar Swaminathan uint32_t HBQ_PutIdx; /* HBQ slot to use */ 35882527734SSukumar Swaminathan uint32_t HBQ_GetIdx; /* Local copy of Get index */ 35982527734SSukumar Swaminathan /* from Port */ 36082527734SSukumar Swaminathan uint16_t HBQ_PostBufCnt; /* Current number of entries */ 36182527734SSukumar Swaminathan /* in list */ 36282527734SSukumar Swaminathan