182527734SSukumar Swaminathan /*
282527734SSukumar Swaminathan  * CDDL HEADER START
382527734SSukumar Swaminathan  *
482527734SSukumar Swaminathan  * The contents of this file are subject to the terms of the
582527734SSukumar Swaminathan  * Common Development and Distribution License (the "License").
682527734SSukumar Swaminathan  * You may not use this file except in compliance with the License.
782527734SSukumar Swaminathan  *
8*8f23e9faSHans Rosenfeld  * You can obtain a copy of the license at
9*8f23e9faSHans Rosenfeld  * http://www.opensource.org/licenses/cddl1.txt.
1082527734SSukumar Swaminathan  * See the License for the specific language governing permissions
1182527734SSukumar Swaminathan  * and limitations under the License.
1282527734SSukumar Swaminathan  *
1382527734SSukumar Swaminathan  * When distributing Covered Code, include this CDDL HEADER in each
1482527734SSukumar Swaminathan  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1582527734SSukumar Swaminathan  * If applicable, add the following below this CDDL HEADER, with the
1682527734SSukumar Swaminathan  * fields enclosed by brackets "[]" replaced with your own identifying
1782527734SSukumar Swaminathan  * information: Portions Copyright [yyyy] [name of copyright owner]
1882527734SSukumar Swaminathan  *
1982527734SSukumar Swaminathan  * CDDL HEADER END
2082527734SSukumar Swaminathan  */
2182527734SSukumar Swaminathan 
2282527734SSukumar Swaminathan /*
23*8f23e9faSHans Rosenfeld  * Copyright (c) 2004-2012 Emulex. All rights reserved.
2482527734SSukumar Swaminathan  * Use is subject to license terms.
2582527734SSukumar Swaminathan  */
2682527734SSukumar Swaminathan 
2782527734SSukumar Swaminathan #ifndef _EMLXS_MBOX_H
2882527734SSukumar Swaminathan #define	_EMLXS_MBOX_H
2982527734SSukumar Swaminathan 
3082527734SSukumar Swaminathan #ifdef	__cplusplus
3182527734SSukumar Swaminathan extern "C" {
3282527734SSukumar Swaminathan #endif
3382527734SSukumar Swaminathan 
3482527734SSukumar Swaminathan /* SLI 2/3 Mailbox defines */
3582527734SSukumar Swaminathan 
3682527734SSukumar Swaminathan #define	MBOX_SIZE			256
3782527734SSukumar Swaminathan #define	MBOX_EXTENSION_OFFSET		MBOX_SIZE
3882527734SSukumar Swaminathan 
3982527734SSukumar Swaminathan #ifdef MBOX_EXT_SUPPORT
4082527734SSukumar Swaminathan #define	MBOX_EXTENSION_SIZE		1024
4182527734SSukumar Swaminathan #else
4282527734SSukumar Swaminathan #define	MBOX_EXTENSION_SIZE		0
4382527734SSukumar Swaminathan #endif /* MBOX_EXT_SUPPORT */
4482527734SSukumar Swaminathan 
4582527734SSukumar Swaminathan 
4682527734SSukumar Swaminathan 
4782527734SSukumar Swaminathan /* ==== Mailbox Commands ==== */
4882527734SSukumar Swaminathan #define	MBX_SHUTDOWN			0x00	/* terminate testing */
4982527734SSukumar Swaminathan #define	MBX_LOAD_SM			0x01
5082527734SSukumar Swaminathan #define	MBX_READ_NV			0x02
5182527734SSukumar Swaminathan #define	MBX_WRITE_NV			0x03
5282527734SSukumar Swaminathan #define	MBX_RUN_BIU_DIAG		0x04
5382527734SSukumar Swaminathan #define	MBX_INIT_LINK			0x05
5482527734SSukumar Swaminathan #define	MBX_DOWN_LINK			0x06
5582527734SSukumar Swaminathan #define	MBX_CONFIG_LINK			0x07
5682527734SSukumar Swaminathan #define	MBX_PART_SLIM			0x08
5782527734SSukumar Swaminathan #define	MBX_CONFIG_RING			0x09
5882527734SSukumar Swaminathan #define	MBX_RESET_RING			0x0A
5982527734SSukumar Swaminathan #define	MBX_READ_CONFIG			0x0B
6082527734SSukumar Swaminathan #define	MBX_READ_RCONFIG		0x0C
6182527734SSukumar Swaminathan #define	MBX_READ_SPARM			0x0D
6282527734SSukumar Swaminathan #define	MBX_READ_STATUS			0x0E
6382527734SSukumar Swaminathan #define	MBX_READ_RPI			0x0F
6482527734SSukumar Swaminathan #define	MBX_READ_XRI			0x10
6582527734SSukumar Swaminathan #define	MBX_READ_REV			0x11
6682527734SSukumar Swaminathan #define	MBX_READ_LNK_STAT		0x12
6782527734SSukumar Swaminathan #define	MBX_REG_LOGIN			0x13
6882527734SSukumar Swaminathan #define	MBX_UNREG_LOGIN			0x14  /* SLI2/3 */
6982527734SSukumar Swaminathan #define	MBX_UNREG_RPI			0x14  /* SLI4 */
7082527734SSukumar Swaminathan #define	MBX_READ_LA			0x15
7182527734SSukumar Swaminathan #define	MBX_CLEAR_LA			0x16
7282527734SSukumar Swaminathan #define	MBX_DUMP_MEMORY			0x17
7382527734SSukumar Swaminathan #define	MBX_DUMP_CONTEXT		0x18
7482527734SSukumar Swaminathan #define	MBX_RUN_DIAGS			0x19
7582527734SSukumar Swaminathan #define	MBX_RESTART			0x1A
7682527734SSukumar Swaminathan #define	MBX_UPDATE_CFG			0x1B
7782527734SSukumar Swaminathan #define	MBX_DOWN_LOAD			0x1C
7882527734SSukumar Swaminathan #define	MBX_DEL_LD_ENTRY		0x1D
7982527734SSukumar Swaminathan #define	MBX_RUN_PROGRAM			0x1E
8082527734SSukumar Swaminathan #define	MBX_SET_MASK			0x20
8182527734SSukumar Swaminathan #define	MBX_SET_VARIABLE		0x21
8282527734SSukumar Swaminathan #define	MBX_UNREG_D_ID			0x23
8382527734SSukumar Swaminathan #define	MBX_KILL_BOARD			0x24
8482527734SSukumar Swaminathan #define	MBX_CONFIG_FARP			0x25
8582527734SSukumar Swaminathan #define	MBX_BEACON			0x2A
8682527734SSukumar Swaminathan #define	MBX_READ_VPI			0x2B
8782527734SSukumar Swaminathan #define	MBX_CONFIG_MSIX			0x30
8882527734SSukumar Swaminathan #define	MBX_HEARTBEAT			0x31
8982527734SSukumar Swaminathan #define	MBX_WRITE_VPARMS		0x32
9082527734SSukumar Swaminathan #define	MBX_ASYNC_EVENT			0x33
9182527734SSukumar Swaminathan 
9282527734SSukumar Swaminathan #define	MBX_READ_EVENT_LOG_STATUS	0x37
9382527734SSukumar Swaminathan #define	MBX_READ_EVENT_LOG		0x38
9482527734SSukumar Swaminathan #define	MBX_WRITE_EVENT_LOG		0x39
9582527734SSukumar Swaminathan #define	MBX_NV_LOG			0x3A
9682527734SSukumar Swaminathan #define	MBX_PORT_CAPABILITIES		0x3B
9782527734SSukumar Swaminathan #define	MBX_IOV_CONTROL			0x3C
9882527734SSukumar Swaminathan #define	MBX_IOV_MBX			0x3D
9982527734SSukumar Swaminathan 
10082527734SSukumar Swaminathan 
10182527734SSukumar Swaminathan #define	MBX_CONFIG_HBQ			0x7C  /* SLI3 */
10282527734SSukumar Swaminathan #define	MBX_LOAD_AREA			0x81
10382527734SSukumar Swaminathan #define	MBX_RUN_BIU_DIAG64		0x84
10482527734SSukumar Swaminathan #define	MBX_GET_DEBUG			0x86
10582527734SSukumar Swaminathan #define	MBX_CONFIG_PORT			0x88
10682527734SSukumar Swaminathan #define	MBX_READ_SPARM64		0x8D
10782527734SSukumar Swaminathan #define	MBX_READ_RPI64			0x8F
10882527734SSukumar Swaminathan #define	MBX_CONFIG_MSI			0x90
109*8f23e9faSHans Rosenfeld #define	MBX_REG_LOGIN64			0x93 /* SLI2/3 */
110*8f23e9faSHans Rosenfeld #define	MBX_REG_RPI			0x93 /* SLI4 */
111*8f23e9faSHans Rosenfeld #define	MBX_READ_LA64			0x95 /* SLI2/3 */
112*8f23e9faSHans Rosenfeld #define	MBX_READ_TOPOLOGY		0x95 /* SLI4 */
113*8f23e9faSHans Rosenfeld #define	MBX_REG_VPI			0x96 /* NPIV */
114*8f23e9faSHans Rosenfeld #define	MBX_UNREG_VPI			0x97 /* NPIV */
11582527734SSukumar Swaminathan #define	MBX_FLASH_WR_ULA		0x98
11682527734SSukumar Swaminathan #define	MBX_SET_DEBUG			0x99
11782527734SSukumar Swaminathan #define	MBX_SLI_CONFIG			0x9B
11882527734SSukumar Swaminathan #define	MBX_LOAD_EXP_ROM		0x9C
11982527734SSukumar Swaminathan #define	MBX_REQUEST_FEATURES		0x9D
12082527734SSukumar Swaminathan #define	MBX_RESUME_RPI			0x9E
12182527734SSukumar Swaminathan #define	MBX_REG_VFI			0x9F
12282527734SSukumar Swaminathan #define	MBX_REG_FCFI			0xA0
12382527734SSukumar Swaminathan #define	MBX_UNREG_VFI			0xA1
12482527734SSukumar Swaminathan #define	MBX_UNREG_FCFI			0xA2
12582527734SSukumar Swaminathan #define	MBX_INIT_VFI			0xA3
12682527734SSukumar Swaminathan #define	MBX_INIT_VPI			0xA4
12782527734SSukumar Swaminathan #define	MBX_ACCESS_VDATA		0xA5
12882527734SSukumar Swaminathan #define	MBX_MAX_CMDS			0xA6
12982527734SSukumar Swaminathan 
13082527734SSukumar Swaminathan 
13182527734SSukumar Swaminathan /*
13282527734SSukumar Swaminathan  * Define Status
13382527734SSukumar Swaminathan  */
13482527734SSukumar Swaminathan #define	MBX_SUCCESS			0x0
13582527734SSukumar Swaminathan #define	MBX_FAILURE			0x1
13682527734SSukumar Swaminathan #define	MBXERR_NUM_IOCBS		0x2
13782527734SSukumar Swaminathan #define	MBXERR_IOCBS_EXCEEDED		0x3
13882527734SSukumar Swaminathan #define	MBXERR_BAD_RING_NUMBER		0x4
13982527734SSukumar Swaminathan #define	MBXERR_MASK_ENTRIES_RANGE	0x5
14082527734SSukumar Swaminathan #define	MBXERR_MASKS_EXCEEDED		0x6
14182527734SSukumar Swaminathan #define	MBXERR_BAD_PROFILE		0x7
14282527734SSukumar Swaminathan #define	MBXERR_BAD_DEF_CLASS		0x8
14382527734SSukumar Swaminathan #define	MBXERR_BAD_MAX_RESPONDER	0x9
14482527734SSukumar Swaminathan #define	MBXERR_BAD_MAX_ORIGINATOR	0xA
14582527734SSukumar Swaminathan #define	MBXERR_RPI_REGISTERED		0xB
14682527734SSukumar Swaminathan #define	MBXERR_RPI_FULL			0xC
14782527734SSukumar Swaminathan #define	MBXERR_NO_RESOURCES		0xD
14882527734SSukumar Swaminathan #define	MBXERR_BAD_RCV_LENGTH		0xE
14982527734SSukumar Swaminathan #define	MBXERR_DMA_ERROR		0xF
15082527734SSukumar Swaminathan #define	MBXERR_NOT_SUPPORTED		0x10
15182527734SSukumar Swaminathan #define	MBXERR_UNSUPPORTED_FEATURE	0x11
15282527734SSukumar Swaminathan #define	MBXERR_UNKNOWN_COMMAND		0x12
153*8f23e9faSHans Rosenfeld #define	MBXERR_BAD_IP_BIT		0x13
154*8f23e9faSHans Rosenfeld #define	MBXERR_BAD_PCB_ALIGN		0x14
155*8f23e9faSHans Rosenfeld #define	MBXERR_BAD_HBQ_ID		0x15
156*8f23e9faSHans Rosenfeld #define	MBXERR_BAD_HBQ_STATE		0x16
157*8f23e9faSHans Rosenfeld #define	MBXERR_BAD_HBQ_MASK_NUM		0x17
158*8f23e9faSHans Rosenfeld #define	MBXERR_BAD_HBQ_MASK_SUBSET	0x18
159*8f23e9faSHans Rosenfeld #define	MBXERR_HBQ_CREATE_FAIL		0x19
160*8f23e9faSHans Rosenfeld #define	MBXERR_HBQ_EXISTING		0x1A
161*8f23e9faSHans Rosenfeld #define	MBXERR_HBQ_RSPRING_FULL		0x1B
162*8f23e9faSHans Rosenfeld #define	MBXERR_HBQ_DUP_MASK		0x1C
163*8f23e9faSHans Rosenfeld #define	MBXERR_HBQ_INVAL_GET_PTR	0x1D
164*8f23e9faSHans Rosenfeld #define	MBXERR_BAD_HBQ_SIZE		0x1E
165*8f23e9faSHans Rosenfeld #define	MBXERR_BAD_HBQ_ORDER		0x1F
166*8f23e9faSHans Rosenfeld #define	MBXERR_INVALID_ID		0x20
167*8f23e9faSHans Rosenfeld 
168*8f23e9faSHans Rosenfeld #define	MBXERR_INVALID_VFI		0x30
169*8f23e9faSHans Rosenfeld 
170*8f23e9faSHans Rosenfeld #define	MBXERR_FLASH_WRITE_FAILED	0x100
171*8f23e9faSHans Rosenfeld 
172*8f23e9faSHans Rosenfeld #define	MBXERR_INVALID_LINKSPEED	0x500
173*8f23e9faSHans Rosenfeld 
174*8f23e9faSHans Rosenfeld #define	MBXERR_BAD_REDIRECT		0x900
175*8f23e9faSHans Rosenfeld #define	MBXERR_RING_ALREADY_CONFIG	0x901
176*8f23e9faSHans Rosenfeld 
177*8f23e9faSHans Rosenfeld #define	MBXERR_RING_INACTIVE		0xA00
178*8f23e9faSHans Rosenfeld 
179*8f23e9faSHans Rosenfeld #define	MBXERR_RPI_INACTIVE		0xF00
180*8f23e9faSHans Rosenfeld 
181*8f23e9faSHans Rosenfeld #define	MBXERR_NO_ACTIVE_XRI		0x1100
182*8f23e9faSHans Rosenfeld #define	MBXERR_XRI_NOT_ACTIVE		0x1101
183*8f23e9faSHans Rosenfeld 
184*8f23e9faSHans Rosenfeld #define	MBXERR_RPI_INUSE		0x1400
185*8f23e9faSHans Rosenfeld 
186*8f23e9faSHans Rosenfeld #define	MBXERR_NO_LINK_ATTENTION	0x1500
187*8f23e9faSHans Rosenfeld 
188*8f23e9faSHans Rosenfeld #define	MBXERR_INVALID_SLI_MODE		0x8800
189*8f23e9faSHans Rosenfeld #define	MBXERR_INVALID_HOST_PTR		0x8801
190*8f23e9faSHans Rosenfeld #define	MBXERR_CANT_CFG_SLI_MODE	0x8802
191*8f23e9faSHans Rosenfeld #define	MBXERR_BAD_OVERLAY		0x8803
192*8f23e9faSHans Rosenfeld #define	MBXERR_INVALID_FEAT_REQ		0x8804
193*8f23e9faSHans Rosenfeld 
194*8f23e9faSHans Rosenfeld #define	MBXERR_CONFIG_CANT_COMPLETE	0x88FF
195*8f23e9faSHans Rosenfeld 
196*8f23e9faSHans Rosenfeld #define	MBXERR_DID_ALREADY_REGISTERED	0x9600
197*8f23e9faSHans Rosenfeld #define	MBXERR_DID_INCONSISTENT		0x9601
198*8f23e9faSHans Rosenfeld #define	MBXERR_VPI_TOO_LARGE		0x9603
199*8f23e9faSHans Rosenfeld 
200*8f23e9faSHans Rosenfeld #define	MBXERR_STILL_ASSOCIATED		0x9700
201*8f23e9faSHans Rosenfeld 
202*8f23e9faSHans Rosenfeld #define	MBXERR_INVALID_VF_STATE		0x9F00
203*8f23e9faSHans Rosenfeld #define	MBXERR_VFI_ALREADY_REGISTERED	0x9F02
204*8f23e9faSHans Rosenfeld #define	MBXERR_VFI_TOO_LARGE		0x9F03
205*8f23e9faSHans Rosenfeld 
206*8f23e9faSHans Rosenfeld #define	MBXERR_LOAD_FW_FAILED		0xFFFE
207*8f23e9faSHans Rosenfeld #define	MBXERR_FIND_FW_FAILED		0xFFFF
20882527734SSukumar Swaminathan 
20982527734SSukumar Swaminathan /* Driver special codes */
21082527734SSukumar Swaminathan #define	MBX_DRIVER_RESERVED		0xF9 /* Set to lowest drv status */
21182527734SSukumar Swaminathan #define	MBX_NONEMBED_ERROR		0xF9
21282527734SSukumar Swaminathan #define	MBX_OVERTEMP_ERROR		0xFA
21382527734SSukumar Swaminathan #define	MBX_HARDWARE_ERROR		0xFB
21482527734SSukumar Swaminathan #define	MBX_DRVR_ERROR			0xFC
21582527734SSukumar Swaminathan #define	MBX_BUSY			0xFD
21682527734SSukumar Swaminathan #define	MBX_TIMEOUT			0xFE
21782527734SSukumar Swaminathan #define	MBX_NOT_FINISHED		0xFF
21882527734SSukumar Swaminathan 
21982527734SSukumar Swaminathan /*
22082527734SSukumar Swaminathan  * flags for EMLXS_SLI_ISSUE_MBOX_CMD()
22182527734SSukumar Swaminathan  */
22282527734SSukumar Swaminathan #define	MBX_POLL	0x01	/* poll mailbox till command done, */
22382527734SSukumar Swaminathan 				/* then return */
22482527734SSukumar Swaminathan #define	MBX_SLEEP	0x02	/* sleep till mailbox intr cmpl */
22582527734SSukumar Swaminathan 				/* wakes thread up */
22682527734SSukumar Swaminathan #define	MBX_WAIT	0x03	/* wait for comand done, then return */
22782527734SSukumar Swaminathan #define	MBX_NOWAIT	0x04	/* issue command then return immediately */
22882527734SSukumar Swaminathan #define	MBX_BOOTSTRAP	0x80	/* issue a command on the bootstrap mbox */
22982527734SSukumar Swaminathan 
23082527734SSukumar Swaminathan 
23182527734SSukumar Swaminathan 
23282527734SSukumar Swaminathan /*
23382527734SSukumar Swaminathan  * Begin Structure Definitions for Mailbox Commands
23482527734SSukumar Swaminathan  */
23582527734SSukumar Swaminathan 
23682527734SSukumar Swaminathan typedef struct revcompat
23782527734SSukumar Swaminathan {
23882527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
23982527734SSukumar Swaminathan 	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
24082527734SSukumar Swaminathan 	uint32_t	ldcount:7;	/* For use by program load */
24182527734SSukumar Swaminathan 	uint32_t	kernel:4;	/* Kernel ID */
24282527734SSukumar Swaminathan 	uint32_t	kver:4;	/* Kernel compatibility version */
24382527734SSukumar Swaminathan 	uint32_t	SMver:4;	/* Sequence Manager version */
24482527734SSukumar Swaminathan 					/* 0 if none */
24582527734SSukumar Swaminathan 	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
24682527734SSukumar Swaminathan 	uint32_t	BIUtype:4;	/* PCI = 0 */
24782527734SSukumar Swaminathan 	uint32_t	BIUver:4;	/* BIU version, 0 if none */
24882527734SSukumar Swaminathan #endif
24982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
25082527734SSukumar Swaminathan 	uint32_t	BIUver:4;	/* BIU version, 0 if none */
25182527734SSukumar Swaminathan 	uint32_t	BIUtype:4;	/* PCI = 0 */
25282527734SSukumar Swaminathan 	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
25382527734SSukumar Swaminathan 	uint32_t	SMver:4;	/* Sequence Manager version */
25482527734SSukumar Swaminathan 					/* 0 if none */
25582527734SSukumar Swaminathan 	uint32_t	kver:4;	/* Kernel compatibility version */
25682527734SSukumar Swaminathan 	uint32_t	kernel:4;	/* Kernel ID */
25782527734SSukumar Swaminathan 	uint32_t	ldcount:7;	/* For use by program load */
25882527734SSukumar Swaminathan 	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
25982527734SSukumar Swaminathan #endif
26082527734SSukumar Swaminathan } REVCOMPAT;
26182527734SSukumar Swaminathan 
26282527734SSukumar Swaminathan typedef struct id_word
26382527734SSukumar Swaminathan {
26482527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
26582527734SSukumar Swaminathan 	uint8_t		Type;
26682527734SSukumar Swaminathan 	uint8_t		Id;
26782527734SSukumar Swaminathan 	uint8_t		Ver;
26882527734SSukumar Swaminathan 	uint8_t		Rev;
26982527734SSukumar Swaminathan #endif
27082527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
27182527734SSukumar Swaminathan 	uint8_t		Rev;
27282527734SSukumar Swaminathan 	uint8_t		Ver;
27382527734SSukumar Swaminathan 	uint8_t		Id;
27482527734SSukumar Swaminathan 	uint8_t		Type;
27582527734SSukumar Swaminathan #endif
27682527734SSukumar Swaminathan 	union
27782527734SSukumar Swaminathan 	{
27882527734SSukumar Swaminathan 		REVCOMPAT	cp;
27982527734SSukumar Swaminathan 		uint32_t	revcomp;
28082527734SSukumar Swaminathan 	} un;
28182527734SSukumar Swaminathan } PROG_ID;
28282527734SSukumar Swaminathan 
28382527734SSukumar Swaminathan typedef struct
28482527734SSukumar Swaminathan {
28582527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
28682527734SSukumar Swaminathan 	uint8_t		tval;
28782527734SSukumar Swaminathan 	uint8_t		tmask;
28882527734SSukumar Swaminathan 	uint8_t		rval;
28982527734SSukumar Swaminathan 	uint8_t		rmask;
29082527734SSukumar Swaminathan #endif
29182527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
29282527734SSukumar Swaminathan 	uint8_t		rmask;
29382527734SSukumar Swaminathan 	uint8_t		rval;
29482527734SSukumar Swaminathan 	uint8_t		tmask;
29582527734SSukumar Swaminathan 	uint8_t		tval;
29682527734SSukumar Swaminathan #endif
29782527734SSukumar Swaminathan } RR_REG;
29882527734SSukumar Swaminathan 
29982527734SSukumar Swaminathan 
30082527734SSukumar Swaminathan /* Structure used for a HBQ entry */
30182527734SSukumar Swaminathan typedef struct
30282527734SSukumar Swaminathan {
30382527734SSukumar Swaminathan 	ULP_BDE64	bde;
30482527734SSukumar Swaminathan 	union UN_TAG
30582527734SSukumar Swaminathan 	{
30682527734SSukumar Swaminathan 		uint32_t	w;
30782527734SSukumar Swaminathan 		struct
30882527734SSukumar Swaminathan 		{
30982527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
31082527734SSukumar Swaminathan 			uint32_t	HBQ_tag:4;
31182527734SSukumar Swaminathan 			uint32_t	HBQE_tag:28;
31282527734SSukumar Swaminathan #endif
31382527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
31482527734SSukumar Swaminathan 			uint32_t	HBQE_tag:28;
31582527734SSukumar Swaminathan 			uint32_t	HBQ_tag:4;
31682527734SSukumar Swaminathan #endif
31782527734SSukumar Swaminathan 		} ext;
31882527734SSukumar Swaminathan 	} unt;
31982527734SSukumar Swaminathan } HBQE_t;
32082527734SSukumar Swaminathan 
32182527734SSukumar Swaminathan typedef struct
32282527734SSukumar Swaminathan {
32382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
32482527734SSukumar Swaminathan 	uint8_t		tmatch;
32582527734SSukumar Swaminathan 	uint8_t		tmask;
32682527734SSukumar Swaminathan 	uint8_t		rctlmatch;
32782527734SSukumar Swaminathan 	uint8_t		rctlmask;
32882527734SSukumar Swaminathan #endif
32982527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
33082527734SSukumar Swaminathan 	uint8_t		rctlmask;
33182527734SSukumar Swaminathan 	uint8_t		rctlmatch;
33282527734SSukumar Swaminathan 	uint8_t		tmask;
33382527734SSukumar Swaminathan 	uint8_t		tmatch;
33482527734SSukumar Swaminathan #endif
33582527734SSukumar Swaminathan } HBQ_MASK;
33682527734SSukumar Swaminathan 
33782527734SSukumar Swaminathan #define	EMLXS_MAX_HBQ_BUFFERS	4096
33882527734SSukumar Swaminathan 
33982527734SSukumar Swaminathan typedef struct
34082527734SSukumar Swaminathan {
34182527734SSukumar Swaminathan 	uint32_t	HBQ_num_mask;		/* number of mask entries in */
34282527734SSukumar Swaminathan 						/* port array */
34382527734SSukumar Swaminathan 	uint32_t	HBQ_recvNotify;		/* Rcv buffer notification */
34482527734SSukumar Swaminathan 	uint32_t	HBQ_numEntries;		/* # of entries in HBQ */
34582527734SSukumar Swaminathan 	uint32_t	HBQ_headerLen;		/* 0 if not profile 4 or 5 */
34682527734SSukumar Swaminathan 	uint32_t	HBQ_logEntry;		/* Set to 1 if this HBQ used */
34782527734SSukumar Swaminathan 						/* for LogEntry */
34882527734SSukumar Swaminathan 	uint32_t	HBQ_profile;		/* Selection profile 0=all, */
34982527734SSukumar Swaminathan 						/* 7=logentry */
35082527734SSukumar Swaminathan 	uint32_t	HBQ_ringMask;		/* Binds HBQ to a ring e.g. */
35182527734SSukumar Swaminathan 						/* Ring0=b0001, ring2=b0100 */
35282527734SSukumar Swaminathan 	uint32_t	HBQ_id;			/* index of this hbq in ring */
35382527734SSukumar Swaminathan 						/* of HBQs[] */
35482527734SSukumar Swaminathan 	uint32_t	HBQ_PutIdx_next;	/* Index to next HBQ slot to */
35582527734SSukumar Swaminathan 						/* use */
35682527734SSukumar Swaminathan 	uint32_t	HBQ_PutIdx;		/* HBQ slot to use */
35782527734SSukumar Swaminathan 	uint32_t	HBQ_GetIdx;		/* Local copy of Get index */
35882527734SSukumar Swaminathan 						/* from Port */
35982527734SSukumar Swaminathan 	uint16_t	HBQ_PostBufCnt;		/* Current number of entries */
36082527734SSukumar Swaminathan 						/* in list */
36182527734SSukumar Swaminathan 	MATCHMAP	*HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS];
36282527734SSukumar Swaminathan 	MATCHMAP	HBQ_host_buf;		/* HBQ host buffer for HBQEs */
36382527734SSukumar Swaminathan 	HBQ_MASK	HBQ_Masks[6];
36482527734SSukumar Swaminathan 
36582527734SSukumar Swaminathan 	union
36682527734SSukumar Swaminathan 	{
36782527734SSukumar Swaminathan 		uint32_t	allprofiles[12];
36882527734SSukumar Swaminathan 
36982527734SSukumar Swaminathan 		struct
370