1*82527734SSukumar Swaminathan /*
2*82527734SSukumar Swaminathan  * CDDL HEADER START
3*82527734SSukumar Swaminathan  *
4*82527734SSukumar Swaminathan  * The contents of this file are subject to the terms of the
5*82527734SSukumar Swaminathan  * Common Development and Distribution License (the "License").
6*82527734SSukumar Swaminathan  * You may not use this file except in compliance with the License.
7*82527734SSukumar Swaminathan  *
8*82527734SSukumar Swaminathan  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*82527734SSukumar Swaminathan  * or http://www.opensolaris.org/os/licensing.
10*82527734SSukumar Swaminathan  * See the License for the specific language governing permissions
11*82527734SSukumar Swaminathan  * and limitations under the License.
12*82527734SSukumar Swaminathan  *
13*82527734SSukumar Swaminathan  * When distributing Covered Code, include this CDDL HEADER in each
14*82527734SSukumar Swaminathan  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*82527734SSukumar Swaminathan  * If applicable, add the following below this CDDL HEADER, with the
16*82527734SSukumar Swaminathan  * fields enclosed by brackets "[]" replaced with your own identifying
17*82527734SSukumar Swaminathan  * information: Portions Copyright [yyyy] [name of copyright owner]
18*82527734SSukumar Swaminathan  *
19*82527734SSukumar Swaminathan  * CDDL HEADER END
20*82527734SSukumar Swaminathan  */
21*82527734SSukumar Swaminathan 
22*82527734SSukumar Swaminathan /*
23*82527734SSukumar Swaminathan  * Copyright 2009 Emulex.  All rights reserved.
24*82527734SSukumar Swaminathan  * Use is subject to license terms.
25*82527734SSukumar Swaminathan  */
26*82527734SSukumar Swaminathan 
27*82527734SSukumar Swaminathan #ifndef _EMLXS_MBOX_H
28*82527734SSukumar Swaminathan #define	_EMLXS_MBOX_H
29*82527734SSukumar Swaminathan 
30*82527734SSukumar Swaminathan #ifdef	__cplusplus
31*82527734SSukumar Swaminathan extern "C" {
32*82527734SSukumar Swaminathan #endif
33*82527734SSukumar Swaminathan 
34*82527734SSukumar Swaminathan /* SLI 2/3 Mailbox defines */
35*82527734SSukumar Swaminathan 
36*82527734SSukumar Swaminathan #define	MBOX_SIZE			256
37*82527734SSukumar Swaminathan #define	MBOX_EXTENSION_OFFSET		MBOX_SIZE
38*82527734SSukumar Swaminathan 
39*82527734SSukumar Swaminathan #ifdef MBOX_EXT_SUPPORT
40*82527734SSukumar Swaminathan #define	MBOX_EXTENSION_SIZE		1024
41*82527734SSukumar Swaminathan #else
42*82527734SSukumar Swaminathan #define	MBOX_EXTENSION_SIZE		0
43*82527734SSukumar Swaminathan #endif /* MBOX_EXT_SUPPORT */
44*82527734SSukumar Swaminathan 
45*82527734SSukumar Swaminathan 
46*82527734SSukumar Swaminathan 
47*82527734SSukumar Swaminathan /* ==== Mailbox Commands ==== */
48*82527734SSukumar Swaminathan #define	MBX_SHUTDOWN			0x00	/* terminate testing */
49*82527734SSukumar Swaminathan #define	MBX_LOAD_SM			0x01
50*82527734SSukumar Swaminathan #define	MBX_READ_NV			0x02
51*82527734SSukumar Swaminathan #define	MBX_WRITE_NV			0x03
52*82527734SSukumar Swaminathan #define	MBX_RUN_BIU_DIAG		0x04
53*82527734SSukumar Swaminathan #define	MBX_INIT_LINK			0x05
54*82527734SSukumar Swaminathan #define	MBX_DOWN_LINK			0x06
55*82527734SSukumar Swaminathan #define	MBX_CONFIG_LINK			0x07
56*82527734SSukumar Swaminathan #define	MBX_PART_SLIM			0x08
57*82527734SSukumar Swaminathan #define	MBX_CONFIG_RING			0x09
58*82527734SSukumar Swaminathan #define	MBX_RESET_RING			0x0A
59*82527734SSukumar Swaminathan #define	MBX_READ_CONFIG			0x0B
60*82527734SSukumar Swaminathan #define	MBX_READ_RCONFIG		0x0C
61*82527734SSukumar Swaminathan #define	MBX_READ_SPARM			0x0D
62*82527734SSukumar Swaminathan #define	MBX_READ_STATUS			0x0E
63*82527734SSukumar Swaminathan #define	MBX_READ_RPI			0x0F
64*82527734SSukumar Swaminathan #define	MBX_READ_XRI			0x10
65*82527734SSukumar Swaminathan #define	MBX_READ_REV			0x11
66*82527734SSukumar Swaminathan #define	MBX_READ_LNK_STAT		0x12
67*82527734SSukumar Swaminathan #define	MBX_REG_LOGIN			0x13
68*82527734SSukumar Swaminathan #define	MBX_UNREG_LOGIN			0x14  /* SLI2/3 */
69*82527734SSukumar Swaminathan #define	MBX_UNREG_RPI			0x14  /* SLI4 */
70*82527734SSukumar Swaminathan #define	MBX_READ_LA			0x15
71*82527734SSukumar Swaminathan #define	MBX_CLEAR_LA			0x16
72*82527734SSukumar Swaminathan #define	MBX_DUMP_MEMORY			0x17
73*82527734SSukumar Swaminathan #define	MBX_DUMP_CONTEXT		0x18
74*82527734SSukumar Swaminathan #define	MBX_RUN_DIAGS			0x19
75*82527734SSukumar Swaminathan #define	MBX_RESTART			0x1A
76*82527734SSukumar Swaminathan #define	MBX_UPDATE_CFG			0x1B
77*82527734SSukumar Swaminathan #define	MBX_DOWN_LOAD			0x1C
78*82527734SSukumar Swaminathan #define	MBX_DEL_LD_ENTRY		0x1D
79*82527734SSukumar Swaminathan #define	MBX_RUN_PROGRAM			0x1E
80*82527734SSukumar Swaminathan #define	MBX_SET_MASK			0x20
81*82527734SSukumar Swaminathan #define	MBX_SET_VARIABLE		0x21
82*82527734SSukumar Swaminathan #define	MBX_UNREG_D_ID			0x23
83*82527734SSukumar Swaminathan #define	MBX_KILL_BOARD			0x24
84*82527734SSukumar Swaminathan #define	MBX_CONFIG_FARP			0x25
85*82527734SSukumar Swaminathan #define	MBX_BEACON			0x2A
86*82527734SSukumar Swaminathan #define	MBX_READ_VPI			0x2B
87*82527734SSukumar Swaminathan #define	MBX_CONFIG_MSIX			0x30
88*82527734SSukumar Swaminathan #define	MBX_HEARTBEAT			0x31
89*82527734SSukumar Swaminathan #define	MBX_WRITE_VPARMS		0x32
90*82527734SSukumar Swaminathan #define	MBX_ASYNC_EVENT			0x33
91*82527734SSukumar Swaminathan 
92*82527734SSukumar Swaminathan #define	MBX_READ_EVENT_LOG_STATUS	0x37
93*82527734SSukumar Swaminathan #define	MBX_READ_EVENT_LOG		0x38
94*82527734SSukumar Swaminathan #define	MBX_WRITE_EVENT_LOG		0x39
95*82527734SSukumar Swaminathan #define	MBX_NV_LOG			0x3A
96*82527734SSukumar Swaminathan #define	MBX_PORT_CAPABILITIES		0x3B
97*82527734SSukumar Swaminathan #define	MBX_IOV_CONTROL			0x3C
98*82527734SSukumar Swaminathan #define	MBX_IOV_MBX			0x3D
99*82527734SSukumar Swaminathan 
100*82527734SSukumar Swaminathan 
101*82527734SSukumar Swaminathan #define	MBX_CONFIG_HBQ			0x7C  /* SLI3 */
102*82527734SSukumar Swaminathan #define	MBX_LOAD_AREA			0x81
103*82527734SSukumar Swaminathan #define	MBX_RUN_BIU_DIAG64		0x84
104*82527734SSukumar Swaminathan #define	MBX_GET_DEBUG			0x86
105*82527734SSukumar Swaminathan #define	MBX_CONFIG_PORT			0x88
106*82527734SSukumar Swaminathan #define	MBX_READ_SPARM64		0x8D
107*82527734SSukumar Swaminathan #define	MBX_READ_RPI64			0x8F
108*82527734SSukumar Swaminathan #define	MBX_CONFIG_MSI			0x90
109*82527734SSukumar Swaminathan #define	MBX_REG_LOGIN64			0x93  /* SLI2/3 */
110*82527734SSukumar Swaminathan #define	MBX_REG_RPI			0x93  /* SLI4 */
111*82527734SSukumar Swaminathan #define	MBX_READ_LA64			0x95
112*82527734SSukumar Swaminathan #define	MBX_REG_VPI			0x96	/* NPIV */
113*82527734SSukumar Swaminathan #define	MBX_UNREG_VPI			0x97	/* NPIV */
114*82527734SSukumar Swaminathan #define	MBX_FLASH_WR_ULA		0x98
115*82527734SSukumar Swaminathan #define	MBX_SET_DEBUG			0x99
116*82527734SSukumar Swaminathan #define	MBX_SLI_CONFIG			0x9B
117*82527734SSukumar Swaminathan #define	MBX_LOAD_EXP_ROM		0x9C
118*82527734SSukumar Swaminathan #define	MBX_REQUEST_FEATURES		0x9D
119*82527734SSukumar Swaminathan #define	MBX_RESUME_RPI			0x9E
120*82527734SSukumar Swaminathan #define	MBX_REG_VFI			0x9F
121*82527734SSukumar Swaminathan #define	MBX_REG_FCFI			0xA0
122*82527734SSukumar Swaminathan #define	MBX_UNREG_VFI			0xA1
123*82527734SSukumar Swaminathan #define	MBX_UNREG_FCFI			0xA2
124*82527734SSukumar Swaminathan #define	MBX_INIT_VFI			0xA3
125*82527734SSukumar Swaminathan #define	MBX_INIT_VPI			0xA4
126*82527734SSukumar Swaminathan #define	MBX_ACCESS_VDATA		0xA5
127*82527734SSukumar Swaminathan #define	MBX_MAX_CMDS			0xA6
128*82527734SSukumar Swaminathan 
129*82527734SSukumar Swaminathan 
130*82527734SSukumar Swaminathan /*
131*82527734SSukumar Swaminathan  * Define Status
132*82527734SSukumar Swaminathan  */
133*82527734SSukumar Swaminathan #define	MBX_SUCCESS			0x0
134*82527734SSukumar Swaminathan #define	MBX_FAILURE			0x1
135*82527734SSukumar Swaminathan #define	MBXERR_NUM_IOCBS		0x2
136*82527734SSukumar Swaminathan #define	MBXERR_IOCBS_EXCEEDED		0x3
137*82527734SSukumar Swaminathan #define	MBXERR_BAD_RING_NUMBER		0x4
138*82527734SSukumar Swaminathan #define	MBXERR_MASK_ENTRIES_RANGE	0x5
139*82527734SSukumar Swaminathan #define	MBXERR_MASKS_EXCEEDED		0x6
140*82527734SSukumar Swaminathan #define	MBXERR_BAD_PROFILE		0x7
141*82527734SSukumar Swaminathan #define	MBXERR_BAD_DEF_CLASS		0x8
142*82527734SSukumar Swaminathan #define	MBXERR_BAD_MAX_RESPONDER	0x9
143*82527734SSukumar Swaminathan #define	MBXERR_BAD_MAX_ORIGINATOR	0xA
144*82527734SSukumar Swaminathan #define	MBXERR_RPI_REGISTERED		0xB
145*82527734SSukumar Swaminathan #define	MBXERR_RPI_FULL			0xC
146*82527734SSukumar Swaminathan #define	MBXERR_NO_RESOURCES		0xD
147*82527734SSukumar Swaminathan #define	MBXERR_BAD_RCV_LENGTH		0xE
148*82527734SSukumar Swaminathan #define	MBXERR_DMA_ERROR		0xF
149*82527734SSukumar Swaminathan #define	MBXERR_NOT_SUPPORTED		0x10
150*82527734SSukumar Swaminathan #define	MBXERR_UNSUPPORTED_FEATURE	0x11
151*82527734SSukumar Swaminathan #define	MBXERR_UNKNOWN_COMMAND		0x12
152*82527734SSukumar Swaminathan 
153*82527734SSukumar Swaminathan /* Driver special codes */
154*82527734SSukumar Swaminathan #define	MBX_DRIVER_RESERVED		0xF9 /* Set to lowest drv status */
155*82527734SSukumar Swaminathan #define	MBX_NONEMBED_ERROR		0xF9
156*82527734SSukumar Swaminathan #define	MBX_OVERTEMP_ERROR		0xFA
157*82527734SSukumar Swaminathan #define	MBX_HARDWARE_ERROR		0xFB
158*82527734SSukumar Swaminathan #define	MBX_DRVR_ERROR			0xFC
159*82527734SSukumar Swaminathan #define	MBX_BUSY			0xFD
160*82527734SSukumar Swaminathan #define	MBX_TIMEOUT			0xFE
161*82527734SSukumar Swaminathan #define	MBX_NOT_FINISHED		0xFF
162*82527734SSukumar Swaminathan 
163*82527734SSukumar Swaminathan /*
164*82527734SSukumar Swaminathan  * flags for EMLXS_SLI_ISSUE_MBOX_CMD()
165*82527734SSukumar Swaminathan  */
166*82527734SSukumar Swaminathan #define	MBX_POLL	0x01	/* poll mailbox till command done, */
167*82527734SSukumar Swaminathan 				/* then return */
168*82527734SSukumar Swaminathan #define	MBX_SLEEP	0x02	/* sleep till mailbox intr cmpl */
169*82527734SSukumar Swaminathan 				/* wakes thread up */
170*82527734SSukumar Swaminathan #define	MBX_WAIT	0x03	/* wait for comand done, then return */
171*82527734SSukumar Swaminathan #define	MBX_NOWAIT	0x04	/* issue command then return immediately */
172*82527734SSukumar Swaminathan #define	MBX_BOOTSTRAP	0x80	/* issue a command on the bootstrap mbox */
173*82527734SSukumar Swaminathan 
174*82527734SSukumar Swaminathan 
175*82527734SSukumar Swaminathan 
176*82527734SSukumar Swaminathan /*
177*82527734SSukumar Swaminathan  * Begin Structure Definitions for Mailbox Commands
178*82527734SSukumar Swaminathan  */
179*82527734SSukumar Swaminathan 
180*82527734SSukumar Swaminathan typedef struct revcompat
181*82527734SSukumar Swaminathan {
182*82527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
183*82527734SSukumar Swaminathan 	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
184*82527734SSukumar Swaminathan 	uint32_t	ldcount:7;	/* For use by program load */
185*82527734SSukumar Swaminathan 	uint32_t	kernel:4;	/* Kernel ID */
186*82527734SSukumar Swaminathan 	uint32_t	kver:4;	/* Kernel compatibility version */
187*82527734SSukumar Swaminathan 	uint32_t	SMver:4;	/* Sequence Manager version */
188*82527734SSukumar Swaminathan 					/* 0 if none */
189*82527734SSukumar Swaminathan 	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
190*82527734SSukumar Swaminathan 	uint32_t	BIUtype:4;	/* PCI = 0 */
191*82527734SSukumar Swaminathan 	uint32_t	BIUver:4;	/* BIU version, 0 if none */
192*82527734SSukumar Swaminathan #endif
193*82527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
194*82527734SSukumar Swaminathan 	uint32_t	BIUver:4;	/* BIU version, 0 if none */
195*82527734SSukumar Swaminathan 	uint32_t	BIUtype:4;	/* PCI = 0 */
196*82527734SSukumar Swaminathan 	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
197*82527734SSukumar Swaminathan 	uint32_t	SMver:4;	/* Sequence Manager version */
198*82527734SSukumar Swaminathan 					/* 0 if none */
199*82527734SSukumar Swaminathan 	uint32_t	kver:4;	/* Kernel compatibility version */
200*82527734SSukumar Swaminathan 	uint32_t	kernel:4;	/* Kernel ID */
201*82527734SSukumar Swaminathan 	uint32_t	ldcount:7;	/* For use by program load */
202*82527734SSukumar Swaminathan 	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
203*82527734SSukumar Swaminathan #endif
204*82527734SSukumar Swaminathan } REVCOMPAT;
205*82527734SSukumar Swaminathan 
206*82527734SSukumar Swaminathan typedef struct id_word
207*82527734SSukumar Swaminathan {
208*82527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
209*82527734SSukumar Swaminathan 	uint8_t		Type;
210*82527734SSukumar Swaminathan 	uint8_t		Id;
211*82527734SSukumar Swaminathan 	uint8_t		Ver;
212*82527734SSukumar Swaminathan 	uint8_t		Rev;
213*82527734SSukumar Swaminathan #endif
214*82527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
215*82527734SSukumar Swaminathan 	uint8_t		Rev;
216*82527734SSukumar Swaminathan 	uint8_t		Ver;
217*82527734SSukumar Swaminathan 	uint8_t		Id;
218*82527734SSukumar Swaminathan 	uint8_t		Type;
219*82527734SSukumar Swaminathan #endif
220*82527734SSukumar Swaminathan 	union
221*82527734SSukumar Swaminathan 	{
222*82527734SSukumar Swaminathan 		REVCOMPAT	cp;
223*82527734SSukumar Swaminathan 		uint32_t	revcomp;
224*82527734SSukumar Swaminathan 	} un;
225*82527734SSukumar Swaminathan } PROG_ID;
226*82527734SSukumar Swaminathan 
227*82527734SSukumar Swaminathan typedef struct
228*82527734SSukumar Swaminathan {
229*82527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
230*82527734SSukumar Swaminathan 	uint8_t		tval;
231*82527734SSukumar Swaminathan 	uint8_t		tmask;
232*82527734SSukumar Swaminathan 	uint8_t		rval;
233*82527734SSukumar Swaminathan 	uint8_t		rmask;
234*82527734SSukumar Swaminathan #endif
235*82527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
236*82527734SSukumar Swaminathan 	uint8_t		rmask;
237*82527734SSukumar Swaminathan 	uint8_t		rval;
238*82527734SSukumar Swaminathan 	uint8_t		tmask;
239*82527734SSukumar Swaminathan 	uint8_t		tval;
240*82527734SSukumar Swaminathan #endif
241*82527734SSukumar Swaminathan } RR_REG;
242*82527734SSukumar Swaminathan 
243*82527734SSukumar Swaminathan 
244*82527734SSukumar Swaminathan /* Structure used for a HBQ entry */
245*82527734SSukumar Swaminathan typedef struct
246*82527734SSukumar Swaminathan {
247*82527734SSukumar Swaminathan 	ULP_BDE64	bde;
248*82527734SSukumar Swaminathan 	union UN_TAG
249*82527734SSukumar Swaminathan 	{
250*82527734SSukumar Swaminathan 		uint32_t	w;
251*82527734SSukumar Swaminathan 		struct
252*82527734SSukumar Swaminathan 		{
253*82527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
254*82527734SSukumar Swaminathan 			uint32_t	HBQ_tag:4;
255*82527734SSukumar Swaminathan 			uint32_t	HBQE_tag:28;
256*82527734SSukumar Swaminathan #endif
257*82527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
258*82527734SSukumar Swaminathan 			uint32_t	HBQE_tag:28;
259*82527734SSukumar Swaminathan 			uint32_t	HBQ_tag:4;
260*82527734SSukumar Swaminathan #endif
261*82527734SSukumar Swaminathan 		} ext;
262*82527734SSukumar Swaminathan 	} unt;
263*82527734SSukumar Swaminathan } HBQE_t;
264*82527734SSukumar Swaminathan 
265*82527734SSukumar Swaminathan typedef struct
266*82527734SSukumar Swaminathan {
267*82527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
268*82527734SSukumar Swaminathan 	uint8_t		tmatch;
269*82527734SSukumar Swaminathan 	uint8_t		tmask;
270*82527734SSukumar Swaminathan 	uint8_t		rctlmatch;
271*82527734SSukumar Swaminathan 	uint8_t		rctlmask;
272*82527734SSukumar Swaminathan #endif
273*82527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
274*82527734SSukumar Swaminathan 	uint8_t		rctlmask;
275*82527734SSukumar Swaminathan 	uint8_t		rctlmatch;
276*82527734SSukumar Swaminathan 	uint8_t		tmask;
277*82527734SSukumar Swaminathan 	uint8_t		tmatch;
278*82527734SSukumar Swaminathan #endif
279*82527734SSukumar Swaminathan } HBQ_MASK;
280*82527734SSukumar Swaminathan 
281*82527734SSukumar Swaminathan #define	EMLXS_MAX_HBQ_BUFFERS	4096
282*82527734SSukumar Swaminathan 
283*82527734SSukumar Swaminathan typedef struct
284*82527734SSukumar Swaminathan {
285*82527734SSukumar Swaminathan 	uint32_t	HBQ_num_mask;		/* number of mask entries in */
286*82527734SSukumar Swaminathan 						/* port array */
287*82527734SSukumar Swaminathan 	uint32_t	HBQ_recvNotify;		/* Rcv buffer notification */
288*82527734SSukumar Swaminathan 	uint32_t	HBQ_numEntries;		/* # of entries in HBQ */
289*82527734SSukumar Swaminathan 	uint32_t	HBQ_headerLen;		/* 0 if not profile 4 or 5 */
290*82527734SSukumar Swaminathan 	uint32_t	HBQ_logEntry;		/* Set to 1 if this HBQ used */
291*82527734SSukumar Swaminathan 						/* for LogEntry */
292*82527734SSukumar Swaminathan 	uint32_t	HBQ_profile;		/* Selection profile 0=all, */
293*82527734SSukumar Swaminathan 						/* 7=logentry */
294*82527734SSukumar Swaminathan 	uint32_t	HBQ_ringMask;		/* Binds HBQ to a ring e.g. */
295*82527734SSukumar Swaminathan 						/* Ring0=b0001, ring2=b0100 */
296*82527734SSukumar Swaminathan 	uint32_t	HBQ_id;			/* index of this hbq in ring */
297*82527734SSukumar Swaminathan 						/* of HBQs[] */
298*82527734SSukumar Swaminathan 	uint32_t	HBQ_PutIdx_next;	/* Index to next HBQ slot to */
299*82527734SSukumar Swaminathan 						/* use */
300*82527734SSukumar Swaminathan 	uint32_t	HBQ_PutIdx;		/* HBQ slot to use */
301*82527734SSukumar Swaminathan 	uint32_t	HBQ_GetIdx;		/* Local copy of Get index */
302*82527734SSukumar Swaminathan 						/* from Port */
303*82527734SSukumar Swaminathan 	uint16_t	HBQ_PostBufCnt;		/* Current number of entries */
304*82527734SSukumar Swaminathan 						/* in list */
305*82527734SSukumar Swaminathan 	MATCHMAP	*HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS];
306*82527734SSukumar Swaminathan 	MATCHMAP	HBQ_host_buf;		/* HBQ host buffer for HBQEs */
307*82527734SSukumar Swaminathan 	HBQ_MASK	HBQ_Masks[6];
308*82527734SSukumar Swaminathan 
309*82527734SSukumar Swaminathan 	union
310*82527734SSukumar Swaminathan 	{
311*82527734SSukumar Swaminathan 		uint32_t	allprofiles[12];
312*82527734SSukumar Swaminathan 
313*82527734SSukumar Swaminathan 		struct
314*82527734SSukumar Swaminathan 		{
315*82527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
316*82527734SSukumar Swaminathan 			uint32_t	seqlenoff:16;
317*82527734SSukumar Swaminathan 			uint32_t	maxlen:16;
318*82527734SSukumar Swaminathan #endif
319*82527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
320*82527734SSukumar Swaminathan 			uint32_t	maxlen:16;
321*82527734SSukumar Swaminathan 			uint32_t	seqlenoff:16;
322*82527734SSukumar Swaminathan #endif
323*82527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN
324*82527734SSukumar Swaminathan 			uint32_t	rsvd1:28;
325*82527734SSukumar Swaminathan 			uint32_t	seqlenbcnt:4;
326*82527734SSukumar Swaminathan #endif
327*82527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN
328*82527734SSukumar Swaminathan 			uint32_t	seqlenbcnt:4;
329*82527734SSukumar Swaminathan 			uint32_t	rsvd1:28;
330*82527734SSukumar Swaminathan #endif
331*82527734SSukumar Swaminathan 			uint32_t	rsvd[10];
332*82527734SSukumar Swaminathan 		} profile2;