1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at
9 * http://www.opensource.org/licenses/cddl1.txt.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 * Copyright 2020 RackTop Systems, Inc.
26 */
27
28#ifndef _EMLXS_MBOX_H
29#define	_EMLXS_MBOX_H
30
31#ifdef	__cplusplus
32extern "C" {
33#endif
34
35/* SLI 2/3 Mailbox defines */
36
37#define	MBOX_SIZE			256
38#define	MBOX_EXTENSION_OFFSET		MBOX_SIZE
39
40#ifdef MBOX_EXT_SUPPORT
41#define	MBOX_EXTENSION_SIZE		1024
42#else
43#define	MBOX_EXTENSION_SIZE		0
44#endif /* MBOX_EXT_SUPPORT */
45
46
47
48/* ==== Mailbox Commands ==== */
49#define	MBX_SHUTDOWN			0x00	/* terminate testing */
50#define	MBX_LOAD_SM			0x01
51#define	MBX_READ_NV			0x02
52#define	MBX_WRITE_NV			0x03
53#define	MBX_RUN_BIU_DIAG		0x04
54#define	MBX_INIT_LINK			0x05
55#define	MBX_DOWN_LINK			0x06
56#define	MBX_CONFIG_LINK			0x07
57#define	MBX_PART_SLIM			0x08
58#define	MBX_CONFIG_RING			0x09
59#define	MBX_RESET_RING			0x0A
60#define	MBX_READ_CONFIG			0x0B
61#define	MBX_READ_RCONFIG		0x0C
62#define	MBX_READ_SPARM			0x0D
63#define	MBX_READ_STATUS			0x0E
64#define	MBX_READ_RPI			0x0F
65#define	MBX_READ_XRI			0x10
66#define	MBX_READ_REV			0x11
67#define	MBX_READ_LNK_STAT		0x12
68#define	MBX_REG_LOGIN			0x13
69#define	MBX_UNREG_LOGIN			0x14  /* SLI2/3 */
70#define	MBX_UNREG_RPI			0x14  /* SLI4 */
71#define	MBX_READ_LA			0x15
72#define	MBX_CLEAR_LA			0x16
73#define	MBX_DUMP_MEMORY			0x17
74#define	MBX_DUMP_CONTEXT		0x18
75#define	MBX_RUN_DIAGS			0x19
76#define	MBX_RESTART			0x1A
77#define	MBX_UPDATE_CFG			0x1B
78#define	MBX_DOWN_LOAD			0x1C
79#define	MBX_DEL_LD_ENTRY		0x1D
80#define	MBX_RUN_PROGRAM			0x1E
81#define	MBX_SET_MASK			0x20
82#define	MBX_SET_VARIABLE		0x21
83#define	MBX_UNREG_D_ID			0x23
84#define	MBX_KILL_BOARD			0x24
85#define	MBX_CONFIG_FARP			0x25
86#define	MBX_BEACON			0x2A
87#define	MBX_READ_VPI			0x2B
88#define	MBX_CONFIG_MSIX			0x30
89#define	MBX_HEARTBEAT			0x31
90#define	MBX_WRITE_VPARMS		0x32
91#define	MBX_ASYNC_EVENT			0x33
92
93#define	MBX_READ_EVENT_LOG_STATUS	0x37
94#define	MBX_READ_EVENT_LOG		0x38
95#define	MBX_WRITE_EVENT_LOG		0x39
96#define	MBX_NV_LOG			0x3A
97#define	MBX_PORT_CAPABILITIES		0x3B
98#define	MBX_IOV_CONTROL			0x3C
99#define	MBX_IOV_MBX			0x3D
100
101
102#define	MBX_CONFIG_HBQ			0x7C  /* SLI3 */
103#define	MBX_LOAD_AREA			0x81
104#define	MBX_RUN_BIU_DIAG64		0x84
105#define	MBX_GET_DEBUG			0x86
106#define	MBX_CONFIG_PORT			0x88
107#define	MBX_READ_SPARM64		0x8D
108#define	MBX_READ_RPI64			0x8F
109#define	MBX_CONFIG_MSI			0x90
110#define	MBX_REG_LOGIN64			0x93 /* SLI2/3 */
111#define	MBX_REG_RPI			0x93 /* SLI4 */
112#define	MBX_READ_LA64			0x95 /* SLI2/3 */
113#define	MBX_READ_TOPOLOGY		0x95 /* SLI4 */
114#define	MBX_REG_VPI			0x96 /* NPIV */
115#define	MBX_UNREG_VPI			0x97 /* NPIV */
116#define	MBX_FLASH_WR_ULA		0x98
117#define	MBX_SET_DEBUG			0x99
118#define	MBX_SLI_CONFIG			0x9B
119#define	MBX_LOAD_EXP_ROM		0x9C
120#define	MBX_REQUEST_FEATURES		0x9D
121#define	MBX_RESUME_RPI			0x9E
122#define	MBX_REG_VFI			0x9F
123#define	MBX_REG_FCFI			0xA0
124#define	MBX_UNREG_VFI			0xA1
125#define	MBX_UNREG_FCFI			0xA2
126#define	MBX_INIT_VFI			0xA3
127#define	MBX_INIT_VPI			0xA4
128#define	MBX_ACCESS_VDATA		0xA5
129#define	MBX_MAX_CMDS			0xA6
130
131
132/*
133 * Define Status
134 */
135#define	MBX_SUCCESS			0x0
136#define	MBX_FAILURE			0x1
137#define	MBXERR_NUM_IOCBS		0x2
138#define	MBXERR_IOCBS_EXCEEDED		0x3
139#define	MBXERR_BAD_RING_NUMBER		0x4
140#define	MBXERR_MASK_ENTRIES_RANGE	0x5
141#define	MBXERR_MASKS_EXCEEDED		0x6
142#define	MBXERR_BAD_PROFILE		0x7
143#define	MBXERR_BAD_DEF_CLASS		0x8
144#define	MBXERR_BAD_MAX_RESPONDER	0x9
145#define	MBXERR_BAD_MAX_ORIGINATOR	0xA
146#define	MBXERR_RPI_REGISTERED		0xB
147#define	MBXERR_RPI_FULL			0xC
148#define	MBXERR_NO_RESOURCES		0xD
149#define	MBXERR_BAD_RCV_LENGTH		0xE
150#define	MBXERR_DMA_ERROR		0xF
151#define	MBXERR_NOT_SUPPORTED		0x10
152#define	MBXERR_UNSUPPORTED_FEATURE	0x11
153#define	MBXERR_UNKNOWN_COMMAND		0x12
154#define	MBXERR_BAD_IP_BIT		0x13
155#define	MBXERR_BAD_PCB_ALIGN		0x14
156#define	MBXERR_BAD_HBQ_ID		0x15
157#define	MBXERR_BAD_HBQ_STATE		0x16
158#define	MBXERR_BAD_HBQ_MASK_NUM		0x17
159#define	MBXERR_BAD_HBQ_MASK_SUBSET	0x18
160#define	MBXERR_HBQ_CREATE_FAIL		0x19
161#define	MBXERR_HBQ_EXISTING		0x1A
162#define	MBXERR_HBQ_RSPRING_FULL		0x1B
163#define	MBXERR_HBQ_DUP_MASK		0x1C
164#define	MBXERR_HBQ_INVAL_GET_PTR	0x1D
165#define	MBXERR_BAD_HBQ_SIZE		0x1E
166#define	MBXERR_BAD_HBQ_ORDER		0x1F
167#define	MBXERR_INVALID_ID		0x20
168
169#define	MBXERR_INVALID_VFI		0x30
170
171#define	MBXERR_FLASH_WRITE_FAILED	0x100
172
173#define	MBXERR_INVALID_LINKSPEED	0x500
174
175#define	MBXERR_BAD_REDIRECT		0x900
176#define	MBXERR_RING_ALREADY_CONFIG	0x901
177
178#define	MBXERR_RING_INACTIVE		0xA00
179
180#define	MBXERR_RPI_INACTIVE		0xF00
181
182#define	MBXERR_NO_ACTIVE_XRI		0x1100
183#define	MBXERR_XRI_NOT_ACTIVE		0x1101
184
185#define	MBXERR_RPI_INUSE		0x1400
186
187#define	MBXERR_NO_LINK_ATTENTION	0x1500
188
189#define	MBXERR_INVALID_SLI_MODE		0x8800
190#define	MBXERR_INVALID_HOST_PTR		0x8801
191#define	MBXERR_CANT_CFG_SLI_MODE	0x8802
192#define	MBXERR_BAD_OVERLAY		0x8803
193#define	MBXERR_INVALID_FEAT_REQ		0x8804
194
195#define	MBXERR_CONFIG_CANT_COMPLETE	0x88FF
196
197#define	MBXERR_DID_ALREADY_REGISTERED	0x9600
198#define	MBXERR_DID_INCONSISTENT		0x9601
199#define	MBXERR_VPI_TOO_LARGE		0x9603
200
201#define	MBXERR_STILL_ASSOCIATED		0x9700
202
203#define	MBXERR_INVALID_VF_STATE		0x9F00
204#define	MBXERR_VFI_ALREADY_REGISTERED	0x9F02
205#define	MBXERR_VFI_TOO_LARGE		0x9F03
206
207#define	MBXERR_LOAD_FW_FAILED		0xFFFE
208#define	MBXERR_FIND_FW_FAILED		0xFFFF
209
210/* Driver special codes */
211#define	MBX_DRIVER_RESERVED		0xF9 /* Set to lowest drv status */
212#define	MBX_NONEMBED_ERROR		0xF9
213#define	MBX_OVERTEMP_ERROR		0xFA
214#define	MBX_HARDWARE_ERROR		0xFB
215#define	MBX_DRVR_ERROR			0xFC
216#define	MBX_BUSY			0xFD
217#define	MBX_TIMEOUT			0xFE
218#define	MBX_NOT_FINISHED		0xFF
219
220/*
221 * flags for EMLXS_SLI_ISSUE_MBOX_CMD()
222 */
223#define	MBX_POLL	0x01	/* poll mailbox till command done, */
224				/* then return */
225#define	MBX_SLEEP	0x02	/* sleep till mailbox intr cmpl */
226				/* wakes thread up */
227#define	MBX_WAIT	0x03	/* wait for comand done, then return */
228#define	MBX_NOWAIT	0x04	/* issue command then return immediately */
229#define	MBX_BOOTSTRAP	0x80	/* issue a command on the bootstrap mbox */
230
231
232
233/*
234 * Begin Structure Definitions for Mailbox Commands
235 */
236
237typedef struct revcompat
238{
239#ifdef EMLXS_BIG_ENDIAN
240	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
241	uint32_t	ldcount:7;	/* For use by program load */
242	uint32_t	kernel:4;	/* Kernel ID */
243	uint32_t	kver:4;	/* Kernel compatibility version */
244	uint32_t	SMver:4;	/* Sequence Manager version */
245					/* 0 if none */
246	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
247	uint32_t	BIUtype:4;	/* PCI = 0 */
248	uint32_t	BIUver:4;	/* BIU version, 0 if none */
249#endif
250#ifdef EMLXS_LITTLE_ENDIAN
251	uint32_t	BIUver:4;	/* BIU version, 0 if none */
252	uint32_t	BIUtype:4;	/* PCI = 0 */
253	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
254	uint32_t	SMver:4;	/* Sequence Manager version */
255					/* 0 if none */
256	uint32_t	kver:4;	/* Kernel compatibility version */
257	uint32_t	kernel:4;	/* Kernel ID */
258	uint32_t	ldcount:7;	/* For use by program load */
259	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
260#endif
261} REVCOMPAT;
262
263typedef struct id_word
264{
265#ifdef EMLXS_BIG_ENDIAN
266	uint8_t		Type;
267	uint8_t		Id;
268	uint8_t		Ver;
269	uint8_t		Rev;
270#endif
271#ifdef EMLXS_LITTLE_ENDIAN
272	uint8_t		Rev;
273	uint8_t		Ver;
274	uint8_t		Id;
275	uint8_t		Type;
276#endif
277	union
278	{
279		REVCOMPAT	cp;
280		uint32_t	revcomp;
281	} un;
282} PROG_ID;
283
284typedef struct
285{
286#ifdef EMLXS_BIG_ENDIAN
287	uint8_t		tval;
288	uint8_t		tmask;
289	uint8_t		rval;
290	uint8_t		rmask;
291#endif
292#ifdef EMLXS_LITTLE_ENDIAN
293	uint8_t		rmask;
294	uint8_t		rval;
295	uint8_t		tmask;
296	uint8_t		tval;
297#endif
298} RR_REG;
299
300
301/* Structure used for a HBQ entry */
302typedef struct
303{
304	ULP_BDE64	bde;
305	union UN_TAG
306	{
307		uint32_t	w;
308		struct
309		{
310#ifdef EMLXS_BIG_ENDIAN
311			uint32_t	HBQ_tag:4;
312			uint32_t	HBQE_tag:28;
313#endif
314#ifdef EMLXS_LITTLE_ENDIAN
315			uint32_t	HBQE_tag:28;
316			uint32_t	HBQ_tag:4;
317#endif
318		} ext;
319	} unt;
320} HBQE_t;
321
322typedef struct
323{
324#ifdef EMLXS_BIG_ENDIAN
325	uint8_t		tmatch;
326	uint8_t		tmask;
327	uint8_t		rctlmatch;
328	uint8_t		rctlmask;
329#endif
330#ifdef EMLXS_LITTLE_ENDIAN
331	uint8_t		rctlmask;
332	uint8_t		rctlmatch;
333	uint8_t		tmask;
334	uint8_t		tmatch;
335#endif
336} HBQ_MASK;
337
338#define	EMLXS_MAX_HBQ_BUFFERS	4096
339
340typedef struct
341{
342	uint32_t	HBQ_num_mask;		/* number of mask entries in */
343						/* port array */
344	uint32_t	HBQ_recvNotify;		/* Rcv buffer notification */
345	uint32_t	HBQ_numEntries;		/* # of entries in HBQ */
346	uint32_t	HBQ_headerLen;		/* 0 if not profile 4 or 5 */
347	uint32_t	HBQ_logEntry;		/* Set to 1 if this HBQ used */
348						/* for LogEntry */
349	uint32_t	HBQ_profile;		/* Selection profile 0=all, */
350						/* 7=logentry */
351	uint32_t	HBQ_ringMask;		/* Binds HBQ to a ring e.g. */
352						/* Ring0=b0001, ring2=b0100 */
353	uint32_t	HBQ_id;			/* index of this hbq in ring */
354						/* of HBQs[] */
355	uint32_t	HBQ_PutIdx_next;	/* Index to next HBQ slot to */
356						/* use */
357	uint32_t	HBQ_PutIdx;		/* HBQ slot to use */
358	uint32_t	HBQ_GetIdx;		/* Local copy of Get index */
359						/* from Port */
360	uint16_t	HBQ_PostBufCnt;		/* Current number of entries */
361						/* in list */
362	MATCHMAP	*HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS];
363	MATCHMAP	HBQ_host_buf;		/* HBQ host buffer for HBQEs */
364	HBQ_MASK	HBQ_Masks[6];
365
366	union
367	{
368		uint32_t	allprofiles[12];
369
370		struct
371		{
372#ifdef EMLXS_BIG_ENDIAN
373			uint32_t	seqlenoff:16;
374			uint32_t	maxlen:16;
375#endif
376#ifdef EMLXS_LITTLE_ENDIAN
377			uint32_t	maxlen:16;
378			uint32_t	seqlenoff:16;
379#endif
380#ifdef EMLXS_BIG_ENDIAN
381			uint32_t	rsvd1:28;
382			uint32_t	seqlenbcnt:4;
383#endif
384#ifdef EMLXS_LITTLE_ENDIAN
385			uint32_t	seqlenbcnt:4;
386			uint32_t	rsvd1:28;
387#endif
388			uint32_t	rsvd[10];
389		} profile2;
390
391		struct
392		{
393#ifdef EMLXS_BIG_ENDIAN
394			uint32_t	seqlenoff:16;
395			uint32_t	maxlen:16;
396#endif
397#ifdef EMLXS_LITTLE_ENDIAN
398			uint32_t	maxlen:16;
399			uint32_t	seqlenoff:16;
400#endif
401#ifdef EMLXS_BIG_ENDIAN
402			uint32_t	cmdcodeoff:28;
403			uint32_t	rsvd1:12;
404			uint32_t	seqlenbcnt:4;
405#endif
406#ifdef EMLXS_LITTLE_ENDIAN
407			uint32_t	seqlenbcnt:4;
408			uint32_t	rsvd1:12;
409			uint32_t	cmdcodeoff:28;
410#endif
411			uint32_t	cmdmatch[8];
412
413			uint32_t	rsvd[2];
414		} profile3;
415
416		struct
417		{
418#ifdef EMLXS_BIG_ENDIAN
419			uint32_t	seqlenoff:16;
420			uint32_t	maxlen:16;
421#endif
422#ifdef EMLXS_LITTLE_ENDIAN
423			uint32_t	maxlen:16;
424			uint32_t	seqlenoff:16;
425#endif
426#ifdef EMLXS_BIG_ENDIAN
427			uint32_t	cmdcodeoff:28;
428			uint32_t	rsvd1:12;
429			uint32_t	seqlenbcnt:4;
430#endif
431#ifdef EMLXS_LITTLE_ENDIAN
432			uint32_t	seqlenbcnt:4;
433			uint32_t	rsvd1:12;
434			uint32_t	cmdcodeoff:28;
435#endif
436			uint32_t	cmdmatch[8];
437
438			uint32_t	rsvd[2];
439		} profile5;
440	} profiles;
441} HBQ_INIT_t;
442
443
444
445/* Structure for MB Command LOAD_SM and DOWN_LOAD */
446
447
448typedef struct
449{
450#ifdef EMLXS_BIG_ENDIAN
451	uint32_t	rsvd2:24;
452	uint32_t	keep:1;
453	uint32_t	acknowledgment:1;
454	uint32_t	version:1;
455	uint32_t	erase_or_prog:1;
456	uint32_t	update_flash:1;
457	uint32_t	update_ram:1;
458	uint32_t	method:1;
459	uint32_t	load_cmplt:1;
460#endif
461#ifdef EMLXS_LITTLE_ENDIAN
462	uint32_t	load_cmplt:1;
463	uint32_t	method:1;
464	uint32_t	update_ram:1;
465	uint32_t	update_flash:1;
466	uint32_t	erase_or_prog:1;
467	uint32_t	version:1;
468	uint32_t	acknowledgment:1;
469	uint32_t	keep:1;
470	uint32_t	rsvd2:24;
471#endif
472
473#define	DL_FROM_BDE	0	/* method */
474#define	DL_FROM_SLIM	1
475
476#define	PROGRAM_FLASH	0	/* erase_or_prog */
477#define	ERASE_FLASH	1
478
479	uint32_t	dl_to_adr;
480	uint32_t	dl_len;
481	union
482	{
483		uint32_t	dl_from_slim_offset;
484		ULP_BDE		dl_from_bde;
485		ULP_BDE64	dl_from_bde64;
486		PROG_ID		prog_id;
487	} un;
488} LOAD_SM_VAR;
489
490
491/* Structure for MB Command READ_NVPARM (02) */
492/* Good for SLI2/3 and SLI4 */
493
494typedef struct
495{
496	uint32_t	rsvd1[3];	/* Read as all one's */
497	uint32_t	rsvd2;		/* Read as all zero's */
498	uint32_t	portname[2];	/* N_PORT name */
499	uint32_t	nodename[2];	/* NODE name */
500#ifdef EMLXS_BIG_ENDIAN
501	uint32_t	pref_DID:24;
502	uint32_t	hardAL_PA:8;
503#endif
504#ifdef EMLXS_LITTLE_ENDIAN
505	uint32_t	hardAL_PA:8;
506	uint32_t	pref_DID:24;
507#endif
508	uint32_t	rsvd3[21];	/* Read as all one's */
509} READ_NV_VAR;
510
511
512/* Structure for MB Command WRITE_NVPARMS (03) */
513/* Good for SLI2/3 and SLI4 */
514
515typedef struct
516{
517	uint32_t	rsvd1[3];	/* Must be all one's */
518	uint32_t	rsvd2;		/* Must be all zero's */
519	uint32_t	portname[2];	/* N_PORT name */
520	uint32_t	nodename[2];	/* NODE name */
521#ifdef EMLXS_BIG_ENDIAN
522	uint32_t	pref_DID:24;
523	uint32_t	hardAL_PA:8;
524#endif
525#ifdef EMLXS_LITTLE_ENDIAN
526	uint32_t	hardAL_PA:8;
527	uint32_t	pref_DID:24;
528#endif
529	uint32_t	rsvd3[21];	/* Must be all one's */
530} WRITE_NV_VAR;
531
532
533/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
534/* Good for SLI2/3 and SLI4 */
535
536typedef struct
537{
538	uint32_t	rsvd1;
539	union
540	{
541		struct
542		{
543			ULP_BDE64	xmit_bde64;
544			ULP_BDE64	rcv_bde64;
545		} s2;
546	} un;
547} BIU_DIAG_VAR;
548
549
550/* Structure for MB Command INIT_LINK (05) */
551/* Good for SLI2/3 and SLI4 */
552
553typedef struct
554{
555#ifdef EMLXS_BIG_ENDIAN
556	uint32_t	rsvd1:24;
557	uint32_t	lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective */
558					/* Reset to */
559#endif
560#ifdef EMLXS_LITTLE_ENDIAN
561	uint32_t	lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective */
562					/* Reset to */
563	uint32_t	rsvd1:24;
564#endif
565
566#ifdef EMLXS_BIG_ENDIAN
567	uint8_t		fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
568	uint8_t		rsvd2;
569	uint16_t	link_flags;
570#endif
571#ifdef EMLXS_LITTLE_ENDIAN
572	uint16_t	link_flags;
573	uint8_t		rsvd2;
574	uint8_t		fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
575#endif
576#define	FLAGS_LOCAL_LB			0x01	/* link_flags (=1) */
577						/* ENDEC loopback */
578#define	FLAGS_TOPOLOGY_MODE_LOOP_PT	0x00	/* Attempt loop then pt-pt */
579#define	FLAGS_TOPOLOGY_MODE_PT_PT	0x02	/* Attempt pt-pt only */
580#define	FLAGS_TOPOLOGY_MODE_LOOP	0x04	/* Attempt loop only */
581#define	FLAGS_TOPOLOGY_MODE_PT_LOOP	0x06	/* Attempt pt-pt then loop */
582#define	FLAGS_LIRP_LILP			0x80	/* LIRP / LILP is disabled */
583
584#define	FLAGS_TOPOLOGY_FAILOVER		0x0400	/* Bit 10 */
585#define	FLAGS_LINK_SPEED		0x0800	/* Bit 11 */
586#define	FLAGS_PREABORT_RETURN		0x4000	/* Bit 14 */
587
588	uint32_t	link_speed;	/* NEW_FEATURE */
589#define	LINK_SPEED_AUTO			0x0	/* Auto selection */
590#define	LINK_SPEED_1G			0x1	/* 1 Gigabaud */
591#define	LINK_SPEED_2G			0x2	/* 2 Gigabaud */
592#define	LINK_SPEED_4G			0x4	/* 4 Gigabaud */
593#define	LINK_SPEED_8G			0x8	/* 8 Gigabaud */
594#define	LINK_SPEED_10G			0x10	/* 10 Gigabaud */
595#define	LINK_SPEED_16G			0x11	/* 16 Gigabaud */
596#define	LINK_SPEED_32G			0x14	/* 32 Gigabaud */
597
598} INIT_LINK_VAR;
599
600
601/* Structure for MB Command DOWN_LINK (06) */
602/* Good for SLI2/3 and SLI4 */
603
604typedef struct
605{
606	uint32_t	rsvd1;
607} DOWN_LINK_VAR;
608
609
610/* Structure for MB Command CONFIG_LINK (07) */
611
612typedef struct
613{
614#ifdef EMLXS_BIG_ENDIAN
615	uint32_t	cr:1;
616	uint32_t	ci:1;
617	uint32_t	cr_delay:6;
618	uint32_t	cr_count:8;
619	uint32_t	rsvd1:8;
620	uint32_t	MaxBBC:8;
621#endif
622#ifdef EMLXS_LITTLE_ENDIAN
623	uint32_t	MaxBBC:8;
624	uint32_t	rsvd1:8;
625	uint32_t	cr_count:8;
626	uint32_t	cr_delay:6;
627	uint32_t	ci:1;
628	uint32_t	cr:1;
629#endif
630	uint32_t	myId;
631	uint32_t	rsvd2;
632	uint32_t	edtov;
633	uint32_t	arbtov;
634	uint32_t	ratov;
635	uint32_t	rttov;
636	uint32_t	altov;
637	uint32_t	crtov;
638	uint32_t	citov;
639#ifdef EMLXS_BIG_ENDIAN
640	uint32_t	rrq_enable:1;
641	uint32_t	rrq_immed:1;
642	uint32_t	rsvd4:29;
643	uint32_t	ack0_enable:1;
644#endif
645#ifdef EMLXS_LITTLE_ENDIAN
646	uint32_t	ack0_enable:1;
647	uint32_t	rsvd4:29;
648	uint32_t	rrq_immed:1;
649	uint32_t	rrq_enable:1;
650#endif
651} CONFIG_LINK;
652
653
654/* Structure for MB Command PART_SLIM (08) */
655
656typedef struct
657{
658#ifdef EMLXS_BIG_ENDIAN
659	uint32_t		unused1:24;
660	uint32_t		numRing:8;
661#endif
662#ifdef EMLXS_LITTLE_ENDIAN
663	uint32_t		numRing:8;
664	uint32_t		unused1:24;
665#endif
666	emlxs_ring_def_t	ringdef[4];
667	uint32_t		hbainit;
668} PART_SLIM_VAR;
669
670
671/* Structure for MB Command CONFIG_RING (09) */
672
673typedef struct
674{
675#ifdef EMLXS_BIG_ENDIAN
676	uint32_t	unused2:6;
677	uint32_t	recvSeq:1;
678	uint32_t	recvNotify:1;
679	uint32_t	numMask:8;
680	uint32_t	profile:8;
681	uint32_t	unused1:4;
682	uint32_t	ring:4;
683#endif
684#ifdef EMLXS_LITTLE_ENDIAN
685	uint32_t	ring:4;
686	uint32_t	unused1:4;
687	uint32_t	profile:8;
688	uint32_t	numMask:8;
689	uint32_t	recvNotify:1;
690	uint32_t	recvSeq:1;
691	uint32_t	unused2:6;
692#endif
693#ifdef EMLXS_BIG_ENDIAN
694	uint16_t	maxRespXchg;
695	uint16_t	maxOrigXchg;
696#endif
697#ifdef EMLXS_LITTLE_ENDIAN
698	uint16_t	maxOrigXchg;
699	uint16_t	maxRespXchg;
700#endif
701	RR_REG		rrRegs[6];
702} CONFIG_RING_VAR;
703
704
705/* Structure for MB Command RESET_RING (10) */
706
707typedef struct
708{
709	uint32_t	ring_no;
710} RESET_RING_VAR;
711
712
713/* Structure for MB Command READ_CONFIG (11) */
714/* Good for SLI2/3 only */
715
716typedef struct
717{
718#ifdef EMLXS_BIG_ENDIAN
719	uint32_t	cr:1;
720	uint32_t	ci:1;
721	uint32_t	cr_delay:6;
722	uint32_t	cr_count:8;
723	uint32_t	InitBBC:8;
724	uint32_t	MaxBBC:8;
725#endif
726#ifdef EMLXS_LITTLE_ENDIAN
727	uint32_t	MaxBBC:8;
728	uint32_t	InitBBC:8;
729	uint32_t	cr_count:8;
730	uint32_t	cr_delay:6;
731	uint32_t	ci:1;
732	uint32_t	cr:1;
733#endif
734#ifdef EMLXS_BIG_ENDIAN
735	uint32_t	topology:8;
736	uint32_t	myDid:24;
737#endif
738#ifdef EMLXS_LITTLE_ENDIAN
739	uint32_t	myDid:24;
740	uint32_t	topology:8;
741#endif
742	/* Defines for topology (defined previously) */
743#ifdef EMLXS_BIG_ENDIAN
744	uint32_t	AR:1;
745	uint32_t	IR:1;
746	uint32_t	rsvd1:29;
747	uint32_t	ack0:1;
748#endif
749#ifdef EMLXS_LITTLE_ENDIAN
750	uint32_t	ack0:1;
751	uint32_t	rsvd1:29;
752	uint32_t	IR:1;
753	uint32_t	AR:1;
754#endif
755	uint32_t	edtov;
756	uint32_t	arbtov;
757	uint32_t	ratov;
758	uint32_t	rttov;
759	uint32_t	altov;
760	uint32_t	lmt;
761
762#define	LMT_1GB_CAPABLE		0x0004
763#define	LMT_2GB_CAPABLE		0x0008
764#define	LMT_4GB_CAPABLE		0x0040
765#define	LMT_8GB_CAPABLE		0x0080
766#define	LMT_10GB_CAPABLE	0x0100
767#define	LMT_16GB_CAPABLE	0x0200
768#define	LMT_32GB_CAPABLE	0x0400
769/* E2E supported on adapters >= 8GB */
770#define	LMT_E2E_CAPABLE		(LMT_8GB_CAPABLE|LMT_10GB_CAPABLE)
771
772	uint32_t	rsvd2;
773	uint32_t	rsvd3;
774	uint32_t	max_xri;
775	uint32_t	max_iocb;
776	uint32_t	max_rpi;
777	uint32_t	avail_xri;
778	uint32_t	avail_iocb;
779	uint32_t	avail_rpi;
780	uint32_t	max_vpi;
781	uint32_t	max_alpa;
782	uint32_t	rsvd4;
783	uint32_t	avail_vpi;
784
785} READ_CONFIG_VAR;
786
787
788/* Structure for MB Command READ_CONFIG(0x11) */
789/* Good for SLI4 only */
790
791typedef struct
792{
793#ifdef EMLXS_BIG_ENDIAN
794	uint32_t	extents:1;	/* Word 1 */
795	uint32_t	rsvd1:31;
796
797	uint32_t	topology:8;	/* Word 2 */
798	uint32_t	rsvd2:15;
799	uint32_t	ldv:1;
800	uint32_t	link_type:2;
801	uint32_t	link_number:6;
802#endif
803#ifdef EMLXS_LITTLE_ENDIAN
804	uint32_t	rsvd1:31;	/* Word 1 */
805	uint32_t	extents:1;
806
807	uint32_t	link_number:6;	/* Word 2 */
808	uint32_t	link_type:2;
809	uint32_t	ldv:1;
810	uint32_t	rsvd2:15;
811	uint32_t	topology:8;
812#endif
813	uint32_t	rsvd3;		/* Word 3 */
814	uint32_t	edtov;		/* Word 4 */
815	uint32_t	rsvd4;		/* Word 5 */
816	uint32_t	ratov;		/* Word 6 */
817	uint32_t	rsvd5;		/* Word 7 */
818	uint32_t	rsvd6;		/* Word 8 */
819	uint32_t	lmt;		/* Word 9 */
820	uint32_t	rsvd8;		/* Word 10 */
821	uint32_t	rsvd9;		/* Word 11 */
822
823#ifdef EMLXS_BIG_ENDIAN
824	uint16_t	XRICount;	/* Word 12 */
825	uint16_t	XRIBase;	/* Word 12 */
826
827	uint16_t	RPICount;	/* Word 13 */
828	uint16_t	RPIBase;	/* Word 13 */
829
830	uint16_t	VPICount;	/* Word 14 */
831	uint16_t	VPIBase;	/* Word 14 */
832
833	uint16_t	VFICount;	/* Word 15 */
834	uint16_t	VFIBase;	/* Word 15 */
835
836	uint16_t	FCFICount;	/* Word 16 */
837	uint16_t	rsvd10;		/* Word 16 */
838
839	uint16_t	EQCount;	/* Word 17 */
840	uint16_t	RQCount;	/* Word 17 */
841
842	uint16_t	CQCount;	/* Word 18 */
843	uint16_t	WQCount;	/* Word 18 */
844#endif
845#ifdef EMLXS_LITTLE_ENDIAN
846	uint16_t	XRIBase;	/* Word 12 */
847	uint16_t	XRICount;	/* Word 12 */
848
849	uint16_t	RPIBase;	/* Word 13 */
850	uint16_t	RPICount;	/* Word 13 */
851
852	uint16_t	VPIBase;	/* Word 14 */
853	uint16_t	VPICount;	/* Word 14 */
854
855	uint16_t	VFIBase;	/* Word 15 */
856	uint16_t	VFICount;	/* Word 15 */
857
858	uint16_t	rsvd10;		/* Word 16 */
859	uint16_t	FCFICount;	/* Word 16 */
860
861	uint16_t	RQCount;	/* Word 17 */
862	uint16_t	EQCount;	/* Word 17 */
863
864	uint16_t	WQCount;	/* Word 18 */
865	uint16_t	CQCount;	/* Word 18 */
866#endif
867
868} READ_CONFIG4_VAR;
869
870/* Structure for MB Command READ_RCONFIG (12) */
871
872typedef struct
873{
874#ifdef EMLXS_BIG_ENDIAN
875	uint32_t	rsvd2:7;
876	uint32_t	recvNotify:1;
877	uint32_t	numMask:8;
878	uint32_t	profile:8;
879	uint32_t	rsvd1:4;
880	uint32_t	ring:4;
881#endif
882#ifdef EMLXS_LITTLE_ENDIAN
883	uint32_t	ring:4;
884	uint32_t	rsvd1:4;
885	uint32_t	profile:8;
886	uint32_t	numMask:8;
887	uint32_t	recvNotify:1;
888	uint32_t	rsvd2:7;
889#endif
890#ifdef EMLXS_BIG_ENDIAN
891	uint16_t	maxResp;
892	uint16_t	maxOrig;
893#endif
894#ifdef EMLXS_LITTLE_ENDIAN
895	uint16_t	maxOrig;
896	uint16_t	maxResp;
897#endif
898	RR_REG		rrRegs[6];
899#ifdef EMLXS_BIG_ENDIAN
900	uint16_t	cmdRingOffset;
901	uint16_t	cmdEntryCnt;
902	uint16_t	rspRingOffset;
903	uint16_t	rspEntryCnt;
904	uint16_t	nextCmdOffset;
905	uint16_t	rsvd3;
906	uint16_t	nextRspOffset;
907	uint16_t	rsvd4;
908#endif
909#ifdef EMLXS_LITTLE_ENDIAN
910	uint16_t	cmdEntryCnt;
911	uint16_t	cmdRingOffset;
912	uint16_t	rspEntryCnt;
913	uint16_t	rspRingOffset;
914	uint16_t	rsvd3;
915	uint16_t	nextCmdOffset;
916	uint16_t	rsvd4;
917	uint16_t	nextRspOffset;
918#endif
919} READ_RCONF_VAR;
920
921
922/* Structure for MB Command READ_SPARM (13) */
923/* Structure for MB Command READ_SPARM64 (0x8D) */
924/* Good for SLI2/3 and SLI4 */
925
926typedef struct
927{
928	uint32_t	rsvd1;
929	uint32_t	rsvd2;
930	union
931	{
932		ULP_BDE		sp;	/* This BDE points to SERV_PARM */
933					/* structure */
934		ULP_BDE64	sp64;
935	} un;
936	uint32_t	rsvd3;
937
938#ifdef EMLXS_BIG_ENDIAN
939	uint16_t	portNameCnt;
940	uint16_t	portNameOffset;
941
942	uint16_t	fabricNameCnt;
943	uint16_t	fabricNameOffset;
944
945	uint16_t	lportNameCnt;
946	uint16_t	lportNameOffset;
947
948	uint16_t	lfabricNameCnt;
949	uint16_t	lfabricNameOffset;
950
951#endif
952#ifdef EMLXS_LITTLE_ENDIAN
953	uint16_t	portNameOffset;
954	uint16_t	portNameCnt;
955
956	uint16_t	fabricNameOffset;
957	uint16_t	fabricNameCnt;
958
959	uint16_t	lportNameOffset;
960	uint16_t	lportNameCnt;
961
962	uint16_t	lfabricNameOffset;
963	uint16_t	lfabricNameCnt;
964
965#endif
966
967} READ_SPARM_VAR;
968
969
970/* Structure for MB Command READ_STATUS (14) */
971/* Good for SLI2/3 and SLI4 */
972
973typedef struct
974{
975#ifdef EMLXS_BIG_ENDIAN
976	uint32_t	rsvd1:31;
977	uint32_t	clrCounters:1;
978
979	uint16_t	activeXriCnt;
980	uint16_t	activeRpiCnt;
981#endif
982#ifdef EMLXS_LITTLE_ENDIAN
983	uint32_t	clrCounters:1;
984	uint32_t	rsvd1:31;
985
986	uint16_t	activeRpiCnt;
987	uint16_t	activeXriCnt;
988#endif
989	uint32_t	xmitByteCnt;
990	uint32_t	rcvByteCnt;
991	uint32_t	xmitFrameCnt;
992	uint32_t	rcvFrameCnt;
993	uint32_t	xmitSeqCnt;
994	uint32_t	rcvSeqCnt;
995	uint32_t	totalOrigExchanges;
996	uint32_t	totalRespExchanges;
997	uint32_t	rcvPbsyCnt;
998	uint32_t	rcvFbsyCnt;
999} READ_STATUS_VAR;
1000
1001
1002/* Structure for MB Command READ_RPI (15) */
1003/* Structure for MB Command READ_RPI64 (0x8F) */
1004
1005typedef struct
1006{
1007#ifdef EMLXS_BIG_ENDIAN
1008	uint16_t	nextRpi;
1009	uint16_t	reqRpi;
1010	uint32_t	rsvd2:8;
1011	uint32_t	DID:24;
1012#endif
1013#ifdef EMLXS_LITTLE_ENDIAN
1014	uint16_t	reqRpi;
1015	uint16_t	nextRpi;
1016	uint32_t	DID:24;
1017	uint32_t	rsvd2:8;
1018#endif
1019	union
1020	{
1021		ULP_BDE		sp;
1022		ULP_BDE64	sp64;
1023	} un;
1024} READ_RPI_VAR;
1025
1026
1027/* Structure for MB Command READ_XRI (16) */
1028
1029typedef struct
1030{
1031#ifdef EMLXS_BIG_ENDIAN
1032	uint16_t	nextXri;
1033	uint16_t	reqXri;
1034	uint16_t	rsvd1;
1035	uint16_t	rpi;
1036	uint32_t	rsvd2:8;
1037	uint32_t	DID:24;
1038	uint32_t	rsvd3:8;
1039	uint32_t	SID:24;
1040	uint32_t	rsvd4;
1041	uint8_t		seqId;
1042	uint8_t		rsvd5;
1043	uint16_t	seqCount;
1044	uint16_t	oxId;
1045	uint16_t	rxId;
1046	uint32_t	rsvd6:30;
1047	uint32_t	si:1;
1048	uint32_t	exchOrig:1;
1049#endif
1050#ifdef EMLXS_LITTLE_ENDIAN
1051	uint16_t	reqXri;
1052	uint16_t	nextXri;
1053	uint16_t	rpi;
1054	uint16_t	rsvd1;
1055	uint32_t	DID:24;
1056	uint32_t	rsvd2:8;
1057	uint32_t	SID:24;
1058	uint32_t	rsvd3:8;
1059	uint32_t	rsvd4;
1060	uint16_t	seqCount;
1061	uint8_t		rsvd5;
1062	uint8_t		seqId;
1063	uint16_t	rxId;
1064	uint16_t	oxId;
1065	uint32_t	exchOrig:1;
1066	uint32_t	si:1;
1067	uint32_t	rsvd6:30;
1068#endif
1069} READ_XRI_VAR;
1070
1071
1072/* Structure for MB Command READ_REV (17) */
1073/* Good for SLI2/3 only */
1074
1075typedef struct
1076{
1077#ifdef EMLXS_BIG_ENDIAN
1078	uint32_t	cv:1;
1079	uint32_t	rr:1;
1080	uint32_t	co:1;
1081	uint32_t	rp:1;
1082	uint32_t	cv3:1;
1083	uint32_t	rf3:1;
1084	uint32_t	rsvd1:10;
1085	uint32_t	offset:14;
1086	uint32_t	rv:2;
1087#endif
1088#ifdef EMLXS_LITTLE_ENDIAN
1089	uint32_t	rv:2;
1090	uint32_t	offset:14;
1091	uint32_t	rsvd1:10;
1092	uint32_t	rf3:1;
1093	uint32_t	cv3:1;
1094	uint32_t	rp:1;
1095	uint32_t	co:1;
1096	uint32_t	rr:1;
1097	uint32_t	cv:1;
1098#endif
1099	uint32_t	biuRev;
1100	uint32_t	smRev;
1101	union
1102	{
1103		uint32_t	smFwRev;
1104		struct
1105		{
1106#ifdef EMLXS_BIG_ENDIAN
1107			uint8_t		ProgType;
1108			uint8_t		ProgId;
1109			uint16_t	ProgVer:4;
1110			uint16_t	ProgRev:4;
1111			uint16_t	ProgFixLvl:2;
1112			uint16_t	ProgDistType:2;
1113			uint16_t	DistCnt:4;
1114#endif
1115#ifdef EMLXS_LITTLE_ENDIAN
1116			uint16_t	DistCnt:4;
1117			uint16_t	ProgDistType:2;
1118			uint16_t	ProgFixLvl:2;
1119			uint16_t	ProgRev:4;
1120			uint16_t	ProgVer:4;
1121			uint8_t		ProgId;
1122			uint8_t		ProgType;
1123#endif
1124		} b;
1125	} un;
1126	uint32_t	endecRev;
1127#ifdef EMLXS_BIG_ENDIAN
1128	uint8_t		feaLevelHigh;
1129	uint8_t		feaLevelLow;
1130	uint8_t		fcphHigh;
1131	uint8_t		fcphLow;
1132#endif
1133#ifdef EMLXS_LITTLE_ENDIAN
1134	uint8_t		fcphLow;
1135	uint8_t		fcphHigh;
1136	uint8_t		feaLevelLow;
1137	uint8_t		feaLevelHigh;
1138#endif
1139	uint32_t	postKernRev;
1140	uint32_t	opFwRev;
1141	uint8_t		opFwName[16];
1142
1143	uint32_t	sliFwRev1;
1144	uint8_t		sliFwName1[16];
1145	uint32_t	sliFwRev2;
1146	uint8_t		sliFwName2[16];
1147} READ_REV_VAR;
1148
1149/* Structure for MB Command READ_REV (17) */
1150/* Good for SLI4 only */
1151
1152typedef struct
1153{
1154#ifdef EMLXS_BIG_ENDIAN
1155	uint32_t	Rsvd3:2;
1156	uint32_t	VPD:1;
1157	uint32_t	rsvd2:6;
1158	uint32_t	dcbxMode:2;
1159	uint32_t	FCoE:1;
1160	uint32_t	sliLevel:4;
1161	uint32_t	rsvd1:16;
1162#endif
1163#ifdef EMLXS_LITTLE_ENDIAN
1164	uint32_t	rsvd1:16;
1165	uint32_t	sliLevel:4;
1166	uint32_t	FCoE:1;
1167	uint32_t	dcbxMode:2;
1168	uint32_t	rsvd2:6;
1169	uint32_t	VPD:1;
1170	uint32_t	Rsvd3:2;
1171#endif
1172
1173	uint32_t	HwRev1;
1174	uint32_t	HwRev2;
1175	uint32_t	Rsvd4;
1176	uint32_t	HwRev3;
1177
1178#ifdef EMLXS_BIG_ENDIAN
1179	uint8_t		feaLevelHigh;
1180	uint8_t		feaLevelLow;
1181	uint8_t		fcphHigh;
1182	uint8_t		fcphLow;
1183#endif
1184#ifdef EMLXS_LITTLE_ENDIAN
1185	uint8_t		fcphLow;
1186	uint8_t		fcphHigh;
1187	uint8_t		feaLevelLow;
1188	uint8_t		feaLevelHigh;
1189#endif
1190
1191	uint32_t	Redboot;
1192
1193	uint32_t	ARMFwId;
1194	uint8_t		ARMFwName[16];
1195
1196	uint32_t	ULPFwId;
1197	uint8_t		ULPFwName[16];
1198
1199	uint32_t	Rsvd6[30];
1200
1201	ULP_BDE64	VPDBde;
1202
1203	uint32_t	ReturnedVPDLength;
1204
1205} READ_REV4_VAR;
1206
1207#define	EMLXS_DCBX_MODE_CIN	0	/* Mapped to nonFIP mode */
1208#define	EMLXS_DCBX_MODE_CEE	1	/* Mapped to FIP mode */
1209
1210/* Structure for MB Command READ_LINK_STAT (18) */
1211/* Good for SLI2/3 and SLI4 */
1212
1213typedef struct
1214{
1215	uint32_t	rsvd1;
1216	uint32_t	linkFailureCnt;
1217	uint32_t	lossSyncCnt;
1218
1219	uint32_t	lossSignalCnt;
1220	uint32_t	primSeqErrCnt;
1221	uint32_t	invalidXmitWord;
1222	uint32_t	crcCnt;
1223	uint32_t	primSeqTimeout;
1224	uint32_t	elasticOverrun;
1225	uint32_t	arbTimeout;
1226
1227	uint32_t	rxBufCredit;
1228	uint32_t	rxBufCreditCur;
1229
1230	uint32_t	txBufCredit;
1231	uint32_t	txBufCreditCur;
1232
1233	uint32_t	EOFaCnt;
1234	uint32_t	EOFdtiCnt;
1235	uint32_t	EOFniCnt;
1236	uint32_t	SOFfCnt;
1237	uint32_t	DropAERCnt;
1238	uint32_t	DropRcv;
1239} READ_LNK_VAR;
1240
1241
1242/* Structure for MB Command REG_LOGIN (19) */
1243/* Structure for MB Command REG_LOGIN64 (0x93) */
1244/* Structure for MB Command REG_RPI (0x93) */
1245/* Good for SLI2/3 and SLI4 */
1246
1247typedef struct
1248{
1249#ifdef EMLXS_BIG_ENDIAN
1250	uint16_t	rsvd1;
1251	uint16_t	rpi;
1252	uint32_t	CI:1;
1253	uint32_t	rsvd2:1;
1254	uint32_t	TERP:1;
1255	uint32_t	rsvd3:4;
1256	uint32_t	update:1;
1257	uint32_t	did:24;
1258#endif
1259#ifdef EMLXS_LITTLE_ENDIAN
1260	uint16_t	rpi;
1261	uint16_t	rsvd1;
1262	uint32_t	did:24;
1263	uint32_t	update:1;
1264	uint32_t	rsvd3:4;
1265	uint32_t	TERP:1;
1266	uint32_t	rsvd2:1;
1267	uint32_t	CI:1;
1268#endif
1269	union
1270	{
1271		ULP_BDE		sp;
1272		ULP_BDE64	sp64;
1273	} un;
1274
1275#ifdef EMLXS_BIG_ENDIAN
1276	uint16_t	rsvd6;
1277	uint16_t	vpi;
1278#endif
1279#ifdef EMLXS_LITTLE_ENDIAN
1280	uint16_t	vpi;
1281	uint16_t	rsvd6;
1282#endif
1283} REG_LOGIN_VAR;
1284
1285/* Word 30 contents for REG_LOGIN */
1286typedef union
1287{
1288	struct
1289	{
1290#ifdef EMLXS_BIG_ENDIAN
1291		uint16_t	rsvd1:12;
1292		uint16_t	class:4;
1293		uint16_t	xri;
1294#endif
1295#ifdef EMLXS_LITTLE_ENDIAN
1296		uint16_t	xri;
1297		uint16_t	class:4;
1298		uint16_t	rsvd1:12;
1299#endif
1300	} f;
1301	uint32_t	word;
1302} REG_WD30;
1303
1304
1305/* Structure for MB Command UNREG_LOGIN (0x14) - SLI2/3 */
1306/* Structure for MB Command UNREG_RPI (0x14) - SLI4 */
1307
1308typedef struct
1309{
1310#ifdef EMLXS_BIG_ENDIAN
1311	uint16_t	ll:2;		/* SLI4 only */
1312	uint16_t	rsvd1:14;
1313	uint16_t	rpi;
1314#endif
1315#ifdef EMLXS_LITTLE_ENDIAN
1316	uint16_t	rpi;
1317	uint16_t	rsvd1:14;
1318	uint16_t	ll:2;		/* SLI4 only */
1319#endif
1320
1321	uint32_t	rsvd2;
1322	uint32_t	rsvd3;
1323	uint32_t	rsvd4;
1324	uint32_t	rsvd5;
1325#ifdef EMLXS_BIG_ENDIAN
1326	uint16_t	rsvd6;
1327	uint16_t	vpi;
1328#endif
1329#ifdef EMLXS_LITTLE_ENDIAN
1330	uint16_t	vpi;
1331	uint16_t	rsvd6;
1332#endif
1333} UNREG_LOGIN_VAR;
1334
1335/* Structure for MB Command REG_FCFI (0xA0) */
1336/* Good for SLI4 only */
1337
1338typedef struct
1339{
1340#ifdef EMLXS_BIG_ENDIAN
1341	uint16_t	FCFI;
1342	uint16_t	InfoIndex;
1343
1344	uint16_t	RQId0;
1345	uint16_t	RQId1;
1346	uint16_t	RQId2;
1347	uint16_t	RQId3;
1348
1349	uint8_t		Id0_type;
1350	uint8_t		Id0_type_mask;
1351	uint8_t		Id0_rctl;
1352	uint8_t		Id0_rctl_mask;
1353
1354	uint8_t		Id1_type;
1355	uint8_t		Id1_type_mask;
1356	uint8_t		Id1_rctl;
1357	uint8_t		Id1_rctl_mask;
1358
1359	uint8_t		Id2_type;
1360	uint8_t		Id2_type_mask;
1361	uint8_t		Id2_rctl;
1362	uint8_t		Id2_rctl_mask;
1363
1364	uint8_t		Id3_type;
1365	uint8_t		Id3_type_mask;
1366	uint8_t		Id3_rctl;
1367	uint8_t		Id3_rctl_mask;
1368
1369	uint32_t	Rsvd1: 17;
1370	uint32_t	mam: 2;
1371	uint32_t	vv: 1;
1372	uint32_t	vlanTag: 12;
1373#endif
1374#ifdef EMLXS_LITTLE_ENDIAN
1375	uint16_t	InfoIndex;
1376	uint16_t	FCFI;
1377
1378	uint16_t	RQId1;
1379	uint16_t	RQId0;
1380	uint16_t	RQId3;
1381	uint16_t	RQId2;
1382
1383	uint8_t		Id0_rctl_mask;
1384	uint8_t		Id0_rctl;
1385	uint8_t		Id0_type_mask;
1386	uint8_t		Id0_type;
1387
1388	uint8_t		Id1_rctl_mask;
1389	uint8_t		Id1_rctl;
1390	uint8_t		Id1_type_mask;
1391	uint8_t		Id1_type;
1392
1393	uint8_t		Id2_rctl_mask;
1394	uint8_t		Id2_rctl;
1395	uint8_t		Id2_type_mask;
1396	uint8_t		Id2_type;
1397
1398	uint8_t		Id3_rctl_mask;
1399	uint8_t		Id3_rctl;
1400	uint8_t		Id3_type_mask;
1401	uint8_t		Id3_type;
1402
1403	uint32_t	vlanTag: 12;
1404	uint32_t	vv: 1;
1405	uint32_t	mam: 2;
1406	uint32_t	Rsvd1: 17;
1407#endif
1408
1409}  REG_FCFI_VAR;
1410
1411/* Defines for mam */
1412#define	EMLXS_REG_FCFI_MAM_SPMA	1	/* Server Provided MAC Address */
1413#define	EMLXS_REG_FCFI_MAM_FPMA	2	/* Fabric Provided MAC Address */
1414
1415/* Structure for MB Command UNREG_FCFI (0xA2) */
1416/* Good for SLI4 only */
1417
1418typedef struct
1419{
1420	uint32_t	Rsvd1;
1421#ifdef EMLXS_BIG_ENDIAN
1422	uint16_t	Rsvd2;
1423	uint16_t	FCFI;
1424#endif
1425#ifdef EMLXS_LITTLE_ENDIAN
1426	uint16_t	FCFI;
1427	uint16_t	Rsvd2;
1428#endif
1429}  UNREG_FCFI_VAR;
1430
1431/* Structure for MB Command RESUME_RPI (0x9E) */
1432/* Good for SLI4 only */
1433
1434typedef struct
1435{
1436#ifdef EMLXS_BIG_ENDIAN
1437	uint16_t	Rsvd1;
1438	uint16_t	RPI;
1439
1440	uint32_t	EventTag;
1441	uint32_t	rsvd2[3];
1442
1443	uint16_t	VFI;
1444	uint16_t	VPI;
1445#endif
1446#ifdef EMLXS_LITTLE_ENDIAN
1447	uint16_t	RPI;
1448	uint16_t	Rsvd1;
1449
1450	uint32_t	EventTag;
1451	uint32_t	rsvd2[3];
1452
1453	uint16_t	VPI;
1454	uint16_t	VFI;
1455#endif
1456
1457}  RESUME_RPI_VAR;
1458
1459
1460/* Structure for MB Command UNREG_D_ID (0x23) */
1461
1462typedef struct
1463{
1464	uint32_t	did;
1465
1466	uint32_t	rsvd2;
1467	uint32_t	rsvd3;
1468	uint32_t	rsvd4;
1469	uint32_t	rsvd5;
1470#ifdef EMLXS_BIG_ENDIAN
1471	uint16_t	rsvd6;
1472	uint16_t	vpi;
1473#endif
1474#ifdef EMLXS_LITTLE_ENDIAN
1475	uint16_t	vpi;
1476	uint16_t	rsvd6;
1477#endif
1478} UNREG_D_ID_VAR;
1479
1480
1481/* Structure for MB Command READ_LA (21) */
1482/* Structure for MB Command READ_LA64 (0x95) */
1483
1484typedef struct
1485{
1486	uint32_t	eventTag;	/* Event tag */
1487#ifdef EMLXS_BIG_ENDIAN
1488	uint32_t	rsvd2:19;
1489	uint32_t	fa:1;
1490	uint32_t	mm:1;
1491	uint32_t	tc:1;
1492	uint32_t	pb:1;
1493	uint32_t	il:1;
1494	uint32_t	attType:8;
1495#endif
1496#ifdef EMLXS_LITTLE_ENDIAN
1497	uint32_t	attType:8;
1498	uint32_t	il:1;
1499	uint32_t	pb:1;
1500	uint32_t	tc:1;
1501	uint32_t	mm:1;
1502	uint32_t	fa:1;
1503	uint32_t	rsvd2:19;
1504#endif
1505#define	AT_RESERVED	0x00	/* Reserved - attType */
1506#define	AT_LINK_UP	0x01	/* Link is up */
1507#define	AT_LINK_DOWN	0x02	/* Link is down */
1508#define	AT_NO_HARD_ALPA	0x03	/* SLI4 */
1509
1510#ifdef EMLXS_BIG_ENDIAN
1511	uint8_t		granted_AL_PA;
1512	uint8_t		lipAlPs;
1513	uint8_t		lipType;
1514	uint8_t		topology;
1515#endif
1516#ifdef EMLXS_LITTLE_ENDIAN
1517	uint8_t		topology;
1518	uint8_t		lipType;
1519	uint8_t		lipAlPs;
1520	uint8_t		granted_AL_PA;
1521#endif
1522
1523	/* lipType */
1524#define	LT_PORT_INIT	0x00	/* An L_PORT initing (F7, AL_PS) - lipType */
1525#define	LT_PORT_ERR	0x01	/* Err @L_PORT rcv'er (F8, AL_PS) */
1526#define	LT_RESET_APORT	0x02	/* Lip Reset of some other port */
1527#define	LT_RESET_MYPORT	0x03	/* Lip Reset of my port */
1528
1529	/* topology */
1530#define	TOPOLOGY_PT_PT	0x01	/* Topology is pt-pt / pt-fabric */
1531#define	TOPOLOGY_LOOP	0x02	/* Topology is FC-AL (private) */
1532
1533	union
1534	{
1535		ULP_BDE		lilpBde;	/* This BDE points to a */
1536						/* 128 byte buffer to store */
1537						/* the LILP AL_PA position */
1538						/* map into */
1539		ULP_BDE64	lilpBde64;
1540	} un;
1541#ifdef EMLXS_BIG_ENDIAN
1542	uint32_t	Dlu:1;
1543	uint32_t	Dtf:1;
1544	uint32_t	Drsvd2:14;
1545	uint32_t	DlnkSpeed:8;
1546	uint32_t	DnlPort:4;
1547	uint32_t	Dtx:2;
1548	uint32_t	Drx:2;
1549#endif
1550#ifdef EMLXS_LITTLE_ENDIAN
1551	uint32_t	Drx:2;
1552	uint32_t	Dtx:2;
1553	uint32_t	DnlPort:4;
1554	uint32_t	DlnkSpeed:8;
1555	uint32_t	Drsvd2:14;
1556	uint32_t	Dtf:1;
1557	uint32_t	Dlu:1;
1558#endif
1559#ifdef EMLXS_BIG_ENDIAN
1560	uint32_t	Ulu:1;
1561	uint32_t	Utf:1;
1562	uint32_t	Ursvd2:14;
1563	uint32_t	UlnkSpeed:8;
1564	uint32_t	UnlPort:4;
1565	uint32_t	Utx:2;
1566	uint32_t	Urx:2;
1567#endif
1568#ifdef EMLXS_LITTLE_ENDIAN
1569	uint32_t	Urx:2;
1570	uint32_t	Utx:2;
1571	uint32_t	UnlPort:4;
1572	uint32_t	UlnkSpeed:8;
1573	uint32_t	Ursvd2:14;
1574	uint32_t	Utf:1;
1575	uint32_t	Ulu:1;
1576#endif
1577#define	LA_1GHZ_LINK   0x04	/* lnkSpeed */
1578#define	LA_2GHZ_LINK   0x08	/* lnkSpeed */
1579#define	LA_4GHZ_LINK   0x10	/* lnkSpeed */
1580#define	LA_8GHZ_LINK   0x20	/* lnkSpeed */
1581#define	LA_10GHZ_LINK  0x40	/* lnkSpeed */
1582#define	LA_16GHZ_LINK  0x80	/* lnkSpeed */
1583#define	LA_32GHZ_LINK  0x90	/* lnkSpeed */
1584} READ_LA_VAR;
1585
1586
1587/* Structure for MB Command CLEAR_LA (22) */
1588
1589typedef struct
1590{
1591	uint32_t	eventTag;	/* Event tag */
1592	uint32_t	rsvd1;
1593} CLEAR_LA_VAR;
1594
1595/* Structure for MB Command DUMP */
1596/* Good for SLI2/3 only */
1597
1598typedef struct
1599{
1600#ifdef EMLXS_BIG_ENDIAN
1601	uint32_t	rsvd:25;
1602	uint32_t	ra:1;
1603	uint32_t	co:1;
1604	uint32_t	cv:1;
1605	uint32_t	type:4;
1606
1607	uint32_t	entry_index:16;
1608	uint32_t	region_id:16;
1609#endif
1610#ifdef EMLXS_LITTLE_ENDIAN
1611	uint32_t	type:4;
1612	uint32_t	cv:1;
1613	uint32_t	co:1;
1614	uint32_t	ra:1;
1615	uint32_t	rsvd:25;
1616
1617	uint32_t	region_id:16;
1618	uint32_t	entry_index:16;
1619#endif
1620	uint32_t	base_adr;
1621	uint32_t	word_cnt;
1622	uint32_t	resp_offset;
1623} DUMP_VAR;
1624
1625/* Structure for MB Command DUMP */
1626/* Good for SLI4 only */
1627
1628typedef struct
1629{
1630#ifdef EMLXS_BIG_ENDIAN
1631	uint32_t	ppi:4;
1632	uint32_t	phy_index:4;
1633	uint32_t	rsvd:20;
1634	uint32_t	type:4;
1635
1636	uint32_t	entry_index:16;
1637	uint32_t	region_id:16;
1638#endif
1639#ifdef EMLXS_LITTLE_ENDIAN
1640	uint32_t	type:4;
1641	uint32_t	rsvd:20;
1642	uint32_t	phy_index:4;
1643	uint32_t	ppi:4;
1644
1645	uint32_t	region_id:16;
1646	uint32_t	entry_index:16;
1647#endif
1648	uint32_t	available_cnt;
1649	uint32_t	addrLow;
1650	uint32_t	addrHigh;
1651	uint32_t	rsp_cnt;
1652} DUMP4_VAR;
1653
1654/*
1655 * Dump type
1656 */
1657#define	DMP_MEM_REG	0x1
1658#define	DMP_NV_PARAMS	0x2
1659
1660/*
1661 * Dump region ID
1662 */
1663#define	NODE_CFG_A_REGION_ID	0
1664#define	NODE_CFG_B_REGION_ID	1
1665#define	NODE_CFG_C_REGION_ID	2
1666#define	NODE_CFG_D_REGION_ID	3
1667#define	WAKE_UP_PARMS_REGION_ID	4
1668#define	DEF_PCI_CFG_REGION_ID	5
1669#define	PCI_CFG_1_REGION_ID	6
1670#define	PCI_CFG_2_REGION_ID	7
1671#define	RSVD1_REGION_ID		8
1672#define	RSVD2_REGION_ID		9
1673#define	RSVD3_REGION_ID		10
1674#define	RSVD4_REGION_ID		11
1675#define	RSVD5_REGION_ID		12
1676#define	RSVD6_REGION_ID		13
1677#define	RSVD7_REGION_ID		14
1678#define	DIAG_TRACE_REGION_ID	15
1679#define	WWN_REGION_ID		16
1680
1681#define	DMP_VPD_REGION		14
1682#define	DMP_VPD_SIZE		1024
1683#define	DMP_VPD_DUMP_WCOUNT	24
1684
1685#define	DMP_FCOE_REGION		23
1686#define	DMP_FCOE_DUMP_WCOUNT	256
1687
1688
1689/* Structure for MB Command UPDATE_CFG */
1690/* Good for SLI2/3 and SLI4 */
1691
1692typedef struct
1693{
1694#ifdef EMLXS_BIG_ENDIAN
1695	uint32_t	rsvd2:16;
1696	uint32_t	proc_type:8;
1697	uint32_t	rsvd1:1;
1698	uint32_t	Abit:1;
1699	uint32_t	Obit:1;
1700	uint32_t	Vbit:1;
1701	uint32_t	req_type:4;
1702#define	INIT_REGION	1
1703#define	UPDATE_DATA	2
1704#define	CLEAN_UP_CFG	3
1705	uint32_t	entry_len:16;
1706	uint32_t	region_id:16;
1707#endif
1708
1709#ifdef EMLXS_LITTLE_ENDIAN
1710	uint32_t	req_type:4;
1711#define	INIT_REGION	1
1712#define	UPDATE_DATA	2
1713#define	CLEAN_UP_CFG	3
1714	uint32_t	Vbit:1;
1715	uint32_t	Obit:1;
1716	uint32_t	Abit:1;
1717	uint32_t	rsvd1:1;
1718	uint32_t	proc_type:8;
1719	uint32_t	rsvd2:16;
1720
1721	uint32_t	region_id:16;
1722	uint32_t	entry_len:16;
1723#endif
1724
1725	uint32_t	rsp_info;
1726	uint32_t	byte_len;
1727	uint32_t	cfg_data;
1728} UPDATE_CFG_VAR;
1729
1730/* Structure for MB Command DEL_LD_ENTRY (29) */
1731
1732typedef struct
1733{
1734#ifdef EMLXS_LITTLE_ENDIAN
1735	uint32_t	list_req:2;
1736	uint32_t	list_rsp:2;
1737	uint32_t	rsvd:28;
1738#else
1739	uint32_t	rsvd:28;
1740	uint32_t	list_rsp:2;
1741	uint32_t	list_req:2;
1742#endif
1743
1744#define	FLASH_LOAD_LIST	1
1745#define	RAM_LOAD_LIST	2
1746#define	BOTH_LISTS	3
1747
1748	PROG_ID		prog_id;
1749} DEL_LD_ENTRY_VAR;
1750
1751/* Structure for MB Command LOAD_AREA (81) */
1752typedef struct
1753{
1754#ifdef EMLXS_LITTLE_ENDIAN
1755	uint32_t	load_cmplt:1;
1756	uint32_t	method:1;
1757	uint32_t	rsvd1:1;
1758	uint32_t	update_flash:1;
1759	uint32_t	erase_or_prog:1;
1760	uint32_t	version:1;
1761	uint32_t	rsvd2:2;
1762	uint32_t	progress:8;
1763	uint32_t	step:8;
1764	uint32_t	area_id:8;
1765#else
1766	uint32_t	area_id:8;
1767	uint32_t	step:8;
1768	uint32_t	progress:8;
1769	uint32_t	rsvd2:2;
1770	uint32_t	version:1;
1771	uint32_t	erase_or_prog:1;
1772	uint32_t	update_flash:1;
1773	uint32_t	rsvd1:1;
1774	uint32_t	method:1;
1775	uint32_t	load_cmplt:1;
1776#endif
1777	uint32_t	dl_to_adr;
1778	uint32_t	dl_len;
1779	union
1780	{
1781		uint32_t	dl_from_slim_offset;
1782		ULP_BDE		dl_from_bde;
1783		ULP_BDE64	dl_from_bde64;
1784		PROG_ID		prog_id;
1785	} un;
1786} LOAD_AREA_VAR;
1787
1788/* Structure for MB Command LOAD_EXP_ROM (9C) */
1789typedef struct
1790{
1791#ifdef EMLXS_LITTLE_ENDIAN
1792	uint32_t	rsvd1:8;
1793	uint32_t	progress:8;
1794	uint32_t	step:8;
1795	uint32_t	rsvd2:8;
1796#else
1797	uint32_t	rsvd2:8;
1798	uint32_t	step:8;
1799	uint32_t	progress:8;
1800	uint32_t	rsvd1:8;
1801#endif
1802	uint32_t	dl_to_adr;
1803	uint32_t	rsvd3;
1804	union
1805	{
1806		uint32_t	word[2];
1807		PROG_ID		prog_id;
1808	} un;
1809} LOAD_EXP_ROM_VAR;
1810
1811
1812/* Structure for MB Command CONFIG_HBQ (7C) */
1813
1814typedef struct
1815{
1816#ifdef EMLXS_BIG_ENDIAN
1817	uint32_t	rsvd1:7;
1818	uint32_t	recvNotify:1;	/* Receive Notification */
1819	uint32_t	numMask:8;	/* # Mask Entries */
1820	uint32_t	profile:8;	/* Selection Profile */
1821	uint32_t	rsvd2:8;
1822#endif
1823#ifdef EMLXS_LITTLE_ENDIAN
1824	uint32_t	rsvd2:8;
1825	uint32_t	profile:8;	/* Selection Profile */
1826	uint32_t	numMask:8;	/* # Mask Entries */
1827	uint32_t	recvNotify:1;	/* Receive Notification */
1828	uint32_t	rsvd1:7;
1829#endif
1830
1831#ifdef EMLXS_BIG_ENDIAN
1832	uint32_t	hbqId:16;
1833	uint32_t	rsvd3:12;
1834	uint32_t	ringMask:4;
1835#endif
1836#ifdef EMLXS_LITTLE_ENDIAN
1837	uint32_t	ringMask:4;
1838	uint32_t	rsvd3:12;
1839	uint32_t	hbqId:16;
1840#endif
1841
1842#ifdef EMLXS_BIG_ENDIAN
1843	uint32_t	numEntries:16;
1844	uint32_t	rsvd4:8;
1845	uint32_t	headerLen:8;
1846#endif
1847#ifdef EMLXS_LITTLE_ENDIAN
1848	uint32_t	headerLen:8;
1849	uint32_t	rsvd4:8;
1850	uint32_t	numEntries:16;
1851#endif
1852
1853	uint32_t	hbqaddrLow;
1854	uint32_t	hbqaddrHigh;
1855
1856#ifdef EMLXS_BIG_ENDIAN
1857	uint32_t	rsvd5:31;
1858	uint32_t	logEntry:1;
1859#endif
1860#ifdef EMLXS_LITTLE_ENDIAN
1861	uint32_t	logEntry:1;
1862	uint32_t	rsvd5:31;
1863#endif
1864
1865	uint32_t	rsvd6;	/* w7 */
1866	uint32_t	rsvd7;	/* w8 */
1867	uint32_t	rsvd8;	/* w9 */
1868
1869	HBQ_MASK	hbqMasks[6];
1870
1871	union
1872	{
1873		uint32_t	allprofiles[12];
1874
1875		struct
1876		{
1877#ifdef EMLXS_BIG_ENDIAN
1878			uint32_t	seqlenoff:16;
1879			uint32_t	maxlen:16;
1880#endif
1881#ifdef EMLXS_LITTLE_ENDIAN
1882			uint32_t	maxlen:16;
1883			uint32_t	seqlenoff:16;
1884#endif
1885#ifdef EMLXS_BIG_ENDIAN
1886			uint32_t	rsvd1:28;
1887			uint32_t	seqlenbcnt:4;
1888#endif
1889#ifdef EMLXS_LITTLE_ENDIAN
1890			uint32_t	seqlenbcnt:4;
1891			uint32_t	rsvd1:28;
1892#endif
1893			uint32_t	rsvd[10];
1894		} profile2;
1895
1896		struct
1897		{
1898#ifdef EMLXS_BIG_ENDIAN
1899			uint32_t	seqlenoff:16;
1900			uint32_t	maxlen:16;
1901#endif
1902#ifdef EMLXS_LITTLE_ENDIAN
1903			uint32_t	maxlen:16;
1904			uint32_t	seqlenoff:16;
1905#endif
1906#ifdef EMLXS_BIG_ENDIAN
1907			uint32_t	cmdcodeoff:28;
1908			uint32_t	rsvd1:12;
1909			uint32_t	seqlenbcnt:4;
1910#endif
1911#ifdef EMLXS_LITTLE_ENDIAN
1912			uint32_t	seqlenbcnt:4;
1913			uint32_t	rsvd1:12;
1914			uint32_t	cmdcodeoff:28;
1915#endif
1916			uint32_t	cmdmatch[8];
1917
1918			uint32_t	rsvd[2];
1919		} profile3;
1920
1921		struct
1922		{
1923#ifdef EMLXS_BIG_ENDIAN
1924			uint32_t	seqlenoff:16;
1925			uint32_t	maxlen:16;
1926#endif
1927#ifdef EMLXS_LITTLE_ENDIAN
1928			uint32_t	maxlen:16;
1929			uint32_t	seqlenoff:16;
1930#endif
1931#ifdef EMLXS_BIG_ENDIAN
1932			uint32_t	cmdcodeoff:28;
1933			uint32_t	rsvd1:12;
1934			uint32_t	seqlenbcnt:4;
1935#endif
1936#ifdef EMLXS_LITTLE_ENDIAN
1937			uint32_t	seqlenbcnt:4;
1938			uint32_t	rsvd1:12;
1939			uint32_t	cmdcodeoff:28;
1940#endif
1941			uint32_t	cmdmatch[8];
1942
1943			uint32_t	rsvd[2];
1944		} profile5;
1945	} profiles;
1946} CONFIG_HBQ_VAR;
1947
1948
1949/* Structure for MB Command REG_VPI(0x96) */
1950/* Good for SLI2/3 and SLI4 */
1951
1952typedef struct
1953{
1954#ifdef EMLXS_BIG_ENDIAN
1955	uint32_t	rsvd1;
1956	uint32_t	rsvd2:7;
1957	uint32_t	upd:1;
1958	uint32_t	sid:24;
1959	uint32_t	portname[2];    /* N_PORT name */
1960	uint32_t	rsvd5;
1961	uint16_t	vfi;
1962	uint16_t	vpi;
1963#endif
1964#ifdef EMLXS_LITTLE_ENDIAN
1965	uint32_t	rsvd1;
1966	uint32_t	sid:24;
1967	uint32_t	upd:1;
1968	uint32_t	rsvd2:7;
1969	uint32_t	portname[2];    /* N_PORT name */
1970	uint32_t	rsvd5;
1971	uint16_t	vpi;
1972	uint16_t	vfi;
1973#endif
1974} REG_VPI_VAR;
1975
1976/* Structure for MB Command INIT_VPI(0xA3) */
1977/* Good for SLI4 only */
1978
1979typedef struct
1980{
1981#ifdef EMLXS_BIG_ENDIAN
1982	uint16_t	vfi;
1983	uint16_t	vpi;
1984#endif
1985#ifdef EMLXS_LITTLE_ENDIAN
1986	uint16_t	vpi;
1987	uint16_t	vfi;
1988#endif
1989} INIT_VPI_VAR;
1990
1991/* Structure for MB Command UNREG_VPI (0x97) */
1992/* Good for SLI2/3 */
1993
1994typedef struct
1995{
1996	uint32_t	rsvd1;
1997	uint32_t	rsvd2;
1998	uint32_t	rsvd3;
1999	uint32_t	rsvd4;
2000	uint32_t	rsvd5;
2001#ifdef EMLXS_BIG_ENDIAN
2002	uint16_t	rsvd6;
2003	uint16_t	vpi;
2004#endif
2005#ifdef EMLXS_LITTLE_ENDIAN
2006	uint16_t	vpi;
2007	uint16_t	rsvd6;
2008#endif
2009} UNREG_VPI_VAR;
2010
2011/* Structure for MB Command UNREG_VPI (0x97) */
2012/* Good for SLI4 */
2013
2014typedef struct
2015{
2016	uint32_t	rsvd1;
2017#ifdef EMLXS_BIG_ENDIAN
2018	uint8_t		ii:2;
2019	uint16_t	rsvd2:14;
2020	uint16_t	index;
2021#endif
2022#ifdef EMLXS_LITTLE_ENDIAN
2023	uint16_t	index;
2024	uint16_t	rsvd2:14;
2025	uint8_t		ii:2;
2026#endif
2027} UNREG_VPI_VAR4;
2028
2029/* Structure for MB Command REG_VFI(0x9F) */
2030/* Good for SLI4 only */
2031
2032typedef struct
2033{
2034#ifdef EMLXS_BIG_ENDIAN
2035	uint16_t	rsvd1:2;
2036	uint16_t	upd:1;
2037	uint16_t	vp:1;
2038	uint16_t	rsvd2:12;
2039	uint16_t	vfi;
2040
2041	uint16_t	vpi;
2042	uint16_t	fcfi;
2043
2044	uint32_t	portname[2];    /* N_PORT name */
2045
2046	ULP_BDE64	bde;
2047
2048/* CHANGE with next firmware drop */
2049	uint32_t	edtov;
2050	uint32_t	ratov;
2051
2052	uint32_t	rsvd5:8;
2053	uint32_t	sid:24;
2054#endif
2055#ifdef EMLXS_LITTLE_ENDIAN
2056	uint16_t	vfi;
2057	uint16_t	rsvd2:12;
2058	uint16_t	vp:1;
2059	uint16_t	upd:1;
2060	uint16_t	rsvd1:2;
2061
2062	uint16_t	fcfi;
2063	uint16_t	vpi;
2064
2065	uint32_t	portname[2];    /* N_PORT name */
2066
2067	ULP_BDE64	bde;
2068
2069/* CHANGE with next firmware drop */
2070	uint32_t	edtov;
2071	uint32_t	ratov;
2072
2073	uint32_t	sid:24;
2074	uint32_t	rsvd5:8;
2075#endif
2076} REG_VFI_VAR;
2077
2078/* Structure for MB Command INIT_VFI(0xA4) */
2079/* Good for SLI4 only */
2080
2081typedef struct
2082{
2083#ifdef EMLXS_BIG_ENDIAN
2084	uint32_t	vr:1;
2085	uint32_t	vt:1;
2086	uint32_t	vf:1;
2087	uint32_t	rsvd1:13;
2088	uint32_t	vfi:16;
2089
2090	uint16_t	rsvd2;
2091	uint16_t	fcfi;
2092
2093	uint32_t	rsvd3:16;
2094	uint32_t	pri:3;
2095	uint32_t	vf_id:12;
2096	uint32_t	rsvd4:1;
2097
2098	uint32_t	hop_count:8;
2099	uint32_t	rsvd5:24;
2100#endif
2101#ifdef EMLXS_LITTLE_ENDIAN
2102	uint32_t	vfi:16;
2103	uint32_t	rsvd1:13;
2104	uint32_t	vf:1;
2105	uint32_t	vt:1;
2106	uint32_t	vr:1;
2107
2108	uint16_t	fcfi;
2109	uint16_t	rsvd2;
2110
2111	uint32_t	rsvd4:1;
2112	uint32_t	vf_id:12;
2113	uint32_t	pri:3;
2114	uint32_t	rsvd3:16;
2115
2116	uint32_t	rsvd5:24;
2117	uint32_t	hop_count:8;
2118#endif
2119} INIT_VFI_VAR;
2120
2121/* Structure for MB Command UNREG_VFI (0xA1) */
2122/* Good for SLI4 only */
2123
2124typedef struct
2125{
2126#ifdef EMLXS_BIG_ENDIAN
2127	uint32_t	rsvd1:3;
2128	uint32_t	vp:1;
2129	uint32_t	rsvd2:28;
2130
2131	uint16_t	vpi;
2132	uint16_t	vfi;
2133#endif
2134#ifdef EMLXS_LITTLE_ENDIAN
2135	uint32_t	rsvd2:28;
2136	uint32_t	vp:1;
2137	uint32_t	rsvd1:3;
2138
2139	uint16_t	vfi;
2140	uint16_t	vpi;
2141#endif
2142} UNREG_VFI_VAR;
2143
2144
2145
2146typedef struct
2147{
2148#ifdef EMLXS_BIG_ENDIAN
2149	uint32_t	read_log:1;
2150	uint32_t	clear_log:1;
2151	uint32_t	mbox_rsp:1;
2152	uint32_t	resv:28;
2153#endif
2154#ifdef EMLXS_LITTLE_ENDIAN
2155	uint32_t	resv:28;
2156	uint32_t	mbox_rsp:1;
2157	uint32_t	clear_log:1;
2158	uint32_t	read_log:1;
2159#endif
2160
2161	uint32_t	offset;
2162
2163	union
2164	{
2165		ULP_BDE		sp;
2166		ULP_BDE64	sp64;
2167	} un;
2168} READ_EVT_LOG_VAR;
2169
2170typedef struct
2171{
2172
2173#ifdef EMLXS_BIG_ENDIAN
2174	uint16_t	split_log_next;
2175	uint16_t	log_next;
2176
2177	uint32_t	size;
2178
2179	uint32_t	format:8;
2180	uint32_t	resv2:22;
2181	uint32_t	log_level:1;
2182	uint32_t	split_log:1;
2183#endif
2184#ifdef EMLXS_LITTLE_ENDIAN
2185	uint16_t	log_next;
2186	uint16_t	split_log_next;
2187
2188	uint32_t	size;
2189
2190	uint32_t	split_log:1;
2191	uint32_t	log_level:1;
2192	uint32_t	resv2:22;
2193	uint32_t	format:8;
2194#endif
2195
2196	uint32_t	offset;
2197} LOG_STATUS_VAR;
2198
2199
2200/* Structure for MB Command CONFIG_PORT (0x88) */
2201typedef struct
2202{
2203#ifdef EMLXS_BIG_ENDIAN
2204	uint32_t	cBE:1;
2205	uint32_t	cET:1;
2206	uint32_t	cHpcb:1;
2207	uint32_t	rMA:1;
2208	uint32_t	sli_mode:4;
2209	uint32_t	pcbLen:24;	/* bit 23:0 of memory based port */
2210					/* config block */
2211#endif
2212#ifdef EMLXS_LITTLE_ENDIAN
2213	uint32_t	pcbLen:24;	/* bit 23:0 of memory based port */
2214					/* config block */
2215	uint32_t	sli_mode:4;
2216	uint32_t	rMA:1;
2217	uint32_t	cHpcb:1;
2218	uint32_t	cET:1;
2219	uint32_t	cBE:1;
2220#endif
2221
2222	uint32_t	pcbLow;		/* bit 31:0 of memory based port */
2223					/* config block */
2224	uint32_t	pcbHigh; 	/* bit 63:32 of memory based port */
2225					/* config block */
2226	uint32_t	hbainit[5];
2227
2228#ifdef EMLXS_BIG_ENDIAN
2229	uint32_t	hps:1; /* Host pointers in SLIM */
2230	uint32_t	rsvd:31;
2231#endif
2232#ifdef EMLXS_LITTLE_ENDIAN
2233	uint32_t	rsvd:31;
2234	uint32_t	hps:1; /* Host pointers in SLIM */
2235#endif
2236
2237#ifdef EMLXS_BIG_ENDIAN
2238	uint32_t	rsvd1:24;
2239	uint32_t	cmv:1;		/* Configure Max VPIs */
2240	uint32_t	ccrp:1;		/* Config Command Ring Polling */
2241	uint32_t	csah:1;		/* Configure Synchronous Abort */
2242					/* Handling */
2243	uint32_t	chbs:1;		/* Cofigure Host Backing store */
2244	uint32_t	cinb:1;		/* Enable Interrupt Notification */
2245					/* Block */
2246	uint32_t	cerbm:1;	/* Configure Enhanced Receive */
2247					/* Buffer Management */
2248	uint32_t	cmx:1;		/* Configure Max XRIs */
2249	uint32_t	cmr:1;		/* Configure Max RPIs */
2250#endif
2251#ifdef EMLXS_LITTLE_ENDIAN
2252	uint32_t	cmr:1;		/* Configure Max RPIs */
2253	uint32_t	cmx:1;		/* Configure Max XRIs */
2254	uint32_t	cerbm:1;	/* Configure Enhanced Receive */
2255					/* Buffer Management */
2256	uint32_t	cinb:1;		/* Enable Interrupt Notification */
2257					/* Block */
2258	uint32_t	chbs:1;		/* Cofigure Host Backing store */
2259	uint32_t	csah:1;		/* Configure Synchronous Abort */
2260					/* Handling */
2261	uint32_t	ccrp:1;		/* Config Command Ring Polling */
2262	uint32_t	cmv:1;		/* Configure Max VPIs */
2263	uint32_t	rsvd1:24;
2264#endif
2265#ifdef EMLXS_BIG_ENDIAN
2266	uint32_t	rsvd2:19;	/* Reserved */
2267	uint32_t	gdss:1;		/* Configure Data Security SLI */
2268	uint32_t	rsvd3:3;	/* Reserved */
2269	uint32_t	gbg:1;		/* Grant BlockGuard */
2270	uint32_t	gmv:1;		/* Grant Max VPIs */
2271	uint32_t	gcrp:1;		/* Grant Command Ring Polling */
2272	uint32_t	gsah:1;		/* Grant Synchronous Abort Handling */
2273	uint32_t	ghbs:1;		/* Grant Host Backing Store */
2274	uint32_t	ginb:1;		/* Grant Interrupt Notification Block */
2275	uint32_t	gerbm:1;	/* Grant ERBM Request */
2276	uint32_t	gmx:1;		/* Grant Max XRIs */
2277	uint32_t	gmr:1;		/* Grant Max RPIs */
2278#endif
2279#ifdef EMLXS_LITTLE_ENDIAN
2280	uint32_t	gmr:1;		/* Grant Max RPIs */
2281	uint32_t	gmx:1;		/* Grant Max XRIs */
2282	uint32_t	gerbm:1;	/* Grant ERBM Request */
2283	uint32_t	ginb:1;		/* Grant Interrupt Notification Block */
2284	uint32_t	ghbs:1;		/* Grant Host Backing Store */
2285	uint32_t	gsah:1;		/* Grant Synchronous Abort Handling */
2286	uint32_t	gcrp:1;		/* Grant Command Ring Polling */
2287	uint32_t	gmv:1;		/* Grant Max VPIs */
2288	uint32_t	gbg:1;		/* Grant BlockGuard */
2289	uint32_t	rsvd3:3;	/* Reserved */
2290	uint32_t	gdss:1;		/* Configure Data Security SLI */
2291	uint32_t	rsvd2:19;	/* Reserved */
2292#endif
2293
2294#ifdef EMLXS_BIG_ENDIAN
2295	uint32_t	max_rpi:16;	/* Max RPIs Port should configure */
2296	uint32_t	max_xri:16;	/* Max XRIs Port should configure */
2297#endif
2298#ifdef EMLXS_LITTLE_ENDIAN
2299	uint32_t	max_xri:16;	/* Max XRIs Port should configure */
2300	uint32_t	max_rpi:16;	/* Max RPIs Port should configure */
2301#endif
2302
2303#ifdef EMLXS_BIG_ENDIAN
2304	uint32_t	max_hbq:16;	/* Max HBQs Host expect to configure */
2305	uint32_t	rsvd4:16;	/* Max HBQs Host expect to configure */
2306#endif
2307#ifdef EMLXS_LITTLE_ENDIAN
2308	uint32_t	rsvd4:16;	/* Max HBQs Host expect to configure */
2309	uint32_t	max_hbq:16;	/* Max HBQs Host expect to configure */
2310#endif
2311
2312	uint32_t	rsvd5;		/* Reserved */
2313
2314#ifdef EMLXS_BIG_ENDIAN
2315	uint32_t	rsvd6:16;	/* Reserved */
2316	uint32_t	vpi_max:16;	/* Max number of virt N-Ports */
2317#endif
2318#ifdef EMLXS_LITTLE_ENDIAN
2319	uint32_t	vpi_max:16;	/* Max number of virt N-Ports */
2320	uint32_t	rsvd6:16;	/* Reserved */
2321#endif
2322} CONFIG_PORT_VAR;
2323
2324/* Structure for MB Command REQUEST_FEATURES (0x9D) */
2325/* Good for SLI4 only */
2326
2327typedef struct
2328{
2329#ifdef EMLXS_BIG_ENDIAN
2330	uint32_t	rsvd1:31;
2331	uint32_t	QueryMode:1;
2332#endif
2333#ifdef EMLXS_LITTLE_ENDIAN
2334	uint32_t	QueryMode:1;
2335	uint32_t	rsvd1:31;
2336#endif
2337
2338	uint32_t	featuresRequested;
2339	uint32_t	featuresEnabled;
2340
2341} REQUEST_FEATURES_VAR;
2342
2343#define	SLI4_FEATURE_INHIBIT_AUTO_ABTS		0x0001
2344#define	SLI4_FEATURE_NPIV			0x0002
2345#define	SLI4_FEATURE_DIF			0x0004
2346#define	SLI4_FEATURE_VIRTUAL_FABRICS		0x0008
2347#define	SLI4_FEATURE_FCP_INITIATOR		0x0010
2348#define	SLI4_FEATURE_FCP_TARGET			0x0020
2349#define	SLI4_FEATURE_FCP_COMBO			0x0040
2350#define	SLI4_FEATURE_RSVD1			0x0080
2351#define	SLI4_FEATURE_RQD			0x0100
2352#define	SLI4_FEATURE_INHIBIT_AUTO_ABTS_R	0x0200
2353#define	SLI4_FEATURE_HIGH_LOGIN_MODE		0x0400
2354#define	SLI4_FEATURE_PERF_HINT			0x0800
2355
2356
2357/* SLI-2 Port Control Block */
2358
2359/* SLIM POINTER */
2360#define	SLIMOFF	0x30	/* WORD */
2361
2362typedef struct _SLI2_RDSC
2363{
2364	uint32_t	cmdEntries;
2365	uint32_t	cmdAddrLow;
2366	uint32_t	cmdAddrHigh;
2367
2368	uint32_t	rspEntries;
2369	uint32_t	rspAddrLow;
2370	uint32_t	rspAddrHigh;
2371} SLI2_RDSC;
2372
2373typedef struct _PCB
2374{
2375#ifdef EMLXS_BIG_ENDIAN
2376	uint32_t	type:8;
2377#define	TYPE_NATIVE_SLI2	0x01;
2378	uint32_t	feature:8;
2379#define	FEATURE_INITIAL_SLI2	0x01;
2380	uint32_t	rsvd:12;
2381	uint32_t	maxRing:4;
2382#endif
2383#ifdef EMLXS_LITTLE_ENDIAN
2384	uint32_t	maxRing:4;
2385	uint32_t	rsvd:12;
2386	uint32_t	feature:8;
2387#define	FEATURE_INITIAL_SLI2	0x01;
2388	uint32_t	type:8;
2389#define	TYPE_NATIVE_SLI2	0x01;
2390#endif
2391
2392	uint32_t	mailBoxSize;
2393	uint32_t	mbAddrLow;
2394	uint32_t	mbAddrHigh;
2395
2396	uint32_t	hgpAddrLow;
2397	uint32_t	hgpAddrHigh;
2398
2399	uint32_t	pgpAddrLow;
2400	uint32_t	pgpAddrHigh;
2401	SLI2_RDSC	rdsc[MAX_RINGS_AVAILABLE];
2402} PCB;
2403
2404/* NEW_FEATURE */
2405typedef struct
2406{
2407#ifdef EMLXS_BIG_ENDIAN
2408	uint32_t	rsvd0:27;
2409	uint32_t	discardFarp:1;
2410	uint32_t	IPEnable:1;
2411	uint32_t	nodeName:1;
2412	uint32_t	portName:1;
2413	uint32_t	filterEnable:1;
2414#endif
2415#ifdef EMLXS_LITTLE_ENDIAN
2416	uint32_t	filterEnable:1;
2417	uint32_t	portName:1;
2418	uint32_t	nodeName:1;
2419	uint32_t	IPEnable:1;
2420	uint32_t	discardFarp:1;
2421	uint32_t	rsvd:27;
2422#endif
2423	NAME_TYPE	portname;
2424	NAME_TYPE	nodename;
2425	uint32_t	rsvd1;
2426	uint32_t	rsvd2;
2427	uint32_t	rsvd3;
2428	uint32_t	IPAddress;
2429} CONFIG_FARP_VAR;
2430
2431
2432/* NEW_FEATURE */
2433typedef struct
2434{
2435#ifdef EMLXS_BIG_ENDIAN
2436	uint32_t	defaultMessageNumber:16;
2437	uint32_t	rsvd1:3;
2438	uint32_t	nid:5;
2439	uint32_t	rsvd2:5;
2440	uint32_t	defaultPresent:1;
2441	uint32_t	addAssociations:1;
2442	uint32_t	reportAssociations:1;
2443#endif
2444#ifdef EMLXS_LITTLE_ENDIAN
2445	uint32_t	reportAssociations:1;
2446	uint32_t	addAssociations:1;
2447	uint32_t	defaultPresent:1;
2448	uint32_t	rsvd2:5;
2449	uint32_t	nid:5;
2450	uint32_t	rsvd1:3;
2451	uint32_t	defaultMessageNumber:16;
2452#endif
2453	uint32_t	attConditions;
2454	uint8_t		attentionId[16];
2455	uint16_t	messageNumberByHA[32];
2456	uint16_t	messageNumberByID[16];
2457	uint32_t	rsvd3;
2458} CONFIG_MSI_VAR;
2459
2460
2461/* NEW_FEATURE */
2462typedef struct
2463{
2464#ifdef EMLXS_BIG_ENDIAN
2465	uint32_t	defaultMessageNumber:8;
2466	uint32_t	rsvd1:11;
2467	uint32_t	nid:5;
2468	uint32_t	rsvd2:5;
2469	uint32_t	defaultPresent:1;
2470	uint32_t	addAssociations:1;
2471	uint32_t	reportAssociations:1;
2472#endif
2473#ifdef EMLXS_LITTLE_ENDIAN
2474	uint32_t	reportAssociations:1;
2475	uint32_t	addAssociations:1;
2476	uint32_t	defaultPresent:1;
2477	uint32_t	rsvd2:5;
2478	uint32_t	nid:5;
2479	uint32_t	rsvd1:11;
2480	uint32_t	defaultMessageNumber:8;
2481#endif
2482	uint32_t	attConditions1;
2483	uint32_t	attConditions2;
2484	uint8_t		attentionId[16];
2485	uint8_t		messageNumberByHA[64];
2486	uint8_t		messageNumberByID[16];
2487	uint32_t	autoClearByHA1;
2488	uint32_t	autoClearByHA2;
2489	uint32_t	autoClearByID;
2490	uint32_t	resv3;
2491} CONFIG_MSIX_VAR;
2492
2493
2494/* Union of all Mailbox Command types */
2495
2496typedef union
2497{
2498	uint32_t		varWords[31];
2499	LOAD_SM_VAR		varLdSM;	/* cmd =  1 (LOAD_SM) */
2500	READ_NV_VAR		varRDnvp;	/* cmd =  2 (READ_NVPARMS) */
2501	WRITE_NV_VAR		varWTnvp;	/* cmd =  3 (WRITE_NVPARMS) */
2502	BIU_DIAG_VAR		varBIUdiag;	/* cmd =  4 (RUN_BIU_DIAG) */
2503	INIT_LINK_VAR		varInitLnk;	/* cmd =  5 (INIT_LINK) */
2504	DOWN_LINK_VAR		varDwnLnk;	/* cmd =  6 (DOWN_LINK) */
2505	CONFIG_LINK		varCfgLnk;	/* cmd =  7 (CONFIG_LINK) */
2506	PART_SLIM_VAR		varSlim;	/* cmd =  8 (PART_SLIM) */
2507	CONFIG_RING_VAR		varCfgRing;	/* cmd =  9 (CONFIG_RING) */
2508	RESET_RING_VAR		varRstRing;	/* cmd = 10 (RESET_RING) */
2509	READ_CONFIG_VAR		varRdConfig;	/* cmd = 11 (READ_CONFIG) */
2510	READ_RCONF_VAR		varRdRConfig;	/* cmd = 12 (READ_RCONFIG) */
2511	READ_SPARM_VAR		varRdSparm;	/* cmd = 13 (READ_SPARM(64)) */
2512	READ_STATUS_VAR		varRdStatus;	/* cmd = 14 (READ_STATUS) */
2513	READ_RPI_VAR		varRdRPI;	/* cmd = 15 (READ_RPI(64)) */
2514	READ_XRI_VAR		varRdXRI;	/* cmd = 16 (READ_XRI) */
2515	READ_REV_VAR		varRdRev;	/* cmd = 17 (READ_REV) */
2516	READ_LNK_VAR		varRdLnk;	/* cmd = 18 (READ_LNK_STAT) */
2517	REG_LOGIN_VAR		varRegLogin;	/* cmd = 19 (REG_LOGIN(64)) */
2518	UNREG_LOGIN_VAR		varUnregLogin;	/* cmd = 20 (UNREG_LOGIN) */
2519	READ_LA_VAR		varReadLA;	/* cmd = 21 (READ_LA(64)) */
2520	CLEAR_LA_VAR		varClearLA;	/* cmd = 22 (CLEAR_LA) */
2521	DUMP_VAR		varDmp;		/* Warm Start DUMP mbx cmd */
2522	UPDATE_CFG_VAR		varUpdateCfg;	/* cmd = 0x1b Warm Start */
2523						/* UPDATE_CFG cmd */
2524	DEL_LD_ENTRY_VAR	varDelLdEntry;	/* cmd = 0x1d (DEL_LD_ENTRY) */
2525	UNREG_D_ID_VAR		varUnregDID;	/* cmd = 0x23 (UNREG_D_ID) */
2526	CONFIG_FARP_VAR		varCfgFarp;	/* cmd = 0x25 (CONFIG_FARP) */
2527	CONFIG_MSI_VAR		varCfgMSI;	/* cmd = 0x90 (CONFIG_MSI) */
2528	CONFIG_MSIX_VAR		varCfgMSIX;	/* cmd = 0x30 (CONFIG_MSIX) */
2529	CONFIG_HBQ_VAR		varCfgHbq;	/* cmd = 0x7C (CONFIG_HBQ) */
2530	LOAD_AREA_VAR		varLdArea;	/* cmd = 0x81 (LOAD_AREA) */
2531	CONFIG_PORT_VAR		varCfgPort;	/* cmd = 0x88 (CONFIG_PORT) */
2532	LOAD_EXP_ROM_VAR	varLdExpRom;	/* cmd = 0x9C (LOAD_XP_ROM) */
2533	REG_VPI_VAR		varRegVpi;	/* cmd = 0x96 (REG_VPI) */
2534	UNREG_VPI_VAR		varUnregVpi;	/* cmd = 0x97 (UNREG_VPI) */
2535	READ_EVT_LOG_VAR	varRdEvtLog;	/* cmd = 0x38 (READ_EVT_LOG) */
2536	LOG_STATUS_VAR		varLogStat;	/* cmd = 0x37 */
2537
2538} MAILVARIANTS;
2539
2540#define	MAILBOX_CMD_BSIZE	128
2541#define	MAILBOX_CMD_WSIZE	32
2542
2543/*
2544 * SLI-2 specific structures
2545 */
2546
2547typedef struct _SLI1_DESC
2548{
2549	emlxs_rings_t	mbxCring[4];
2550	uint32_t	mbxUnused[24];
2551} SLI1_DESC; /* 128 bytes */
2552
2553typedef struct
2554{
2555	uint32_t	cmdPutInx;
2556	uint32_t	rspGetInx;
2557} HGP;
2558
2559typedef struct
2560{
2561	uint32_t	cmdGetInx;
2562	uint32_t	rspPutInx;
2563} PGP;
2564
2565typedef struct _SLI2_DESC
2566{
2567	HGP		host[4];
2568	PGP		port[4];
2569	uint32_t	HBQ_PortGetIdx[16];
2570} SLI2_DESC; /* 128 bytes */
2571
2572typedef union
2573{
2574	SLI1_DESC	s1;	/* 32 words, 128 bytes */
2575	SLI2_DESC	s2;	/* 32 words, 128 bytes */
2576} SLI_VAR;
2577
2578typedef volatile struct
2579{
2580#ifdef EMLXS_BIG_ENDIAN
2581	uint16_t	mbxStatus;
2582	uint8_t		mbxCommand;
2583	uint8_t		mbxReserved:6;
2584	uint8_t		mbxHc:1;
2585	uint8_t		mbxOwner:1;	/* Low order bit first word */
2586#endif
2587#ifdef EMLXS_LITTLE_ENDIAN
2588	uint8_t		mbxOwner:1;	/* Low order bit first word */
2589	uint8_t		mbxHc:1;
2590	uint8_t		mbxReserved:6;
2591	uint8_t		mbxCommand;
2592	uint16_t	mbxStatus;
2593#endif
2594	MAILVARIANTS	un;		/* 124 bytes */
2595	SLI_VAR		us;		/* 128 bytes */
2596} MAILBOX;				/* 256 bytes */
2597
2598
2599
2600/* SLI4 IOCTL Mailbox */
2601/* ALL SLI4 specific mbox commands have a standard request /response header */
2602/* Word 0 is just like SLI 3 */
2603
2604typedef struct mbox_req_hdr
2605{
2606#ifdef EMLXS_BIG_ENDIAN
2607	uint32_t	domain:8;		/* word 6 */
2608	uint32_t	port:8;
2609	uint32_t	subsystem:8;
2610	uint32_t	opcode:8;
2611
2612	uint32_t	timeout;		/* word 7 */
2613
2614	uint32_t	req_length;		/* word 8 */
2615
2616	uint32_t	reserved1:24;		/* word 9 */
2617	uint32_t	version:8;		/* word 9 */
2618#endif
2619#ifdef EMLXS_LITTLE_ENDIAN
2620	uint32_t	opcode:8;
2621	uint32_t	subsystem:8;
2622	uint32_t	port:8;
2623	uint32_t	domain:8;		/* word 6 */
2624
2625	uint32_t	timeout;		/* word 7 */
2626
2627	uint32_t	req_length;		/* word 8 */
2628
2629	uint32_t	version:8;		/* word 9 */
2630	uint32_t	reserved1:24;		/* word 9 */
2631#endif
2632
2633} mbox_req_hdr_t;
2634
2635
2636typedef struct mbox_req_hdr2
2637{
2638#ifdef EMLXS_BIG_ENDIAN
2639	uint32_t	vf_number:16;		/* word 6 */
2640	uint32_t	subsystem:8;
2641	uint32_t	opcode:8;
2642
2643	uint32_t	timeout;		/* word 7 */
2644
2645	uint32_t	req_length;		/* word 8 */
2646
2647	uint32_t	vh_number:6;		/* word 9 */
2648	uint32_t	pf_number:10;
2649	uint32_t	reserved1:8;
2650	uint32_t	version:8;
2651#endif
2652#ifdef EMLXS_LITTLE_ENDIAN
2653	uint32_t	opcode:8;
2654	uint32_t	subsystem:8;
2655	uint32_t	vf_number:16;		/* word 6 */
2656
2657	uint32_t	timeout;		/* word 7 */
2658
2659	uint32_t	req_length;		/* word 8 */
2660
2661	uint32_t	version:8;
2662	uint32_t	reserved1:8;
2663	uint32_t	pf_number:10;
2664	uint32_t	vh_number:6;		/* word 9 */
2665#endif
2666
2667} mbox_req_hdr2_t;
2668
2669typedef struct mbox_rsp_hdr
2670{
2671#ifdef EMLXS_BIG_ENDIAN
2672	uint32_t	domain:8;		/* word 6 */
2673	uint32_t	reserved1:8;
2674	uint32_t	subsystem:8;
2675	uint32_t	opcode:8;
2676
2677	uint32_t	reserved2:16;		/* word 7 */
2678	uint32_t	extra_status:8;
2679	uint32_t	status:8;
2680#endif
2681#ifdef EMLXS_LITTLE_ENDIAN
2682	uint32_t	opcode:8;
2683	uint32_t	subsystem:8;
2684	uint32_t	reserved1:8;
2685	uint32_t	domain:8;		/* word 6 */
2686
2687	uint32_t	status:8;
2688	uint32_t	extra_status:8;
2689	uint32_t	reserved2:16;		/* word 7 */
2690#endif
2691	uint32_t	rsp_length;		/* word 8 */
2692	uint32_t	allocated_length;	/* word 9 */
2693} mbox_rsp_hdr_t;
2694
2695#define	MBX_RSP_STATUS_SUCCESS		0x00
2696#define	MBX_RSP_STATUS_FAILED		0x01
2697#define	MBX_RSP_STATUS_ILLEGAL_REQ	0x02
2698#define	MBX_RSP_STATUS_ILLEGAL_FIELD	0x03
2699#define	MBX_RSP_STATUS_FCF_IN_USE	0x3A
2700#define	MBX_RSP_STATUS_NO_FCF		0x43
2701
2702#define	MGMT_ADDI_STATUS_INCOMPATIBLE	0xA2
2703
2704typedef struct be_req_hdr
2705{
2706#ifdef EMLXS_BIG_ENDIAN
2707	uint32_t	special:8;		/* word 1 */
2708	uint32_t	reserved2:16;		/* word 1 */
2709	uint32_t	sge_cnt:5;		/* word 1 */
2710	uint32_t	reserved1:2;		/* word 1 */
2711	uint32_t	embedded:1;		/* word 1 */
2712#endif
2713#ifdef EMLXS_LITTLE_ENDIAN
2714	uint32_t	embedded:1;		/* word 1 */
2715	uint32_t	reserved1:2;		/* word 1 */
2716	uint32_t	sge_cnt:5;		/* word 1 */
2717	uint32_t	reserved2:16;		/* word 1 */
2718	uint32_t	special:8;		/* word 1 */
2719#endif
2720	uint32_t	payload_length;		/* word 2 */
2721	uint32_t	tag_low;		/* word 3 */
2722	uint32_t	tag_hi;			/* word 4 */
2723	uint32_t	reserved3;		/* word 5 */
2724	union
2725	{
2726		mbox_req_hdr_t	hdr_req;
2727		mbox_req_hdr2_t hdr_req2;
2728		mbox_rsp_hdr_t	hdr_rsp;
2729	} un_hdr;
2730} be_req_hdr_t;
2731
2732#define	EMLXS_MAX_NONEMBED_SIZE		(1024 * 64)
2733
2734/* SLI_CONFIG Mailbox commands */
2735
2736#define	IOCTL_SUBSYSTEM_COMMON			0x01
2737#define	IOCTL_SUBSYSTEM_FCOE			0x0C
2738#define	IOCTL_SUBSYSTEM_DCBX			0x10
2739
2740#define	COMMON_OPCODE_READ_FLASHROM		0x06
2741#define	COMMON_OPCODE_WRITE_FLASHROM		0x07
2742#define	COMMON_OPCODE_CQ_CREATE			0x0C
2743#define	COMMON_OPCODE_EQ_CREATE			0x0D
2744#define	COMMON_OPCODE_MQ_CREATE 		0x15
2745#define	COMMON_OPCODE_GET_CNTL_ATTRIB		0x20
2746#define	COMMON_OPCODE_NOP			0x21
2747#define	COMMON_OPCODE_QUERY_FIRMWARE_CONFIG	0x3A
2748#define	COMMON_OPCODE_RESET			0x3D
2749#define	COMMON_OPCODE_SET_PHYSICAL_LINK_CFG_V1	0x3E
2750
2751#define	COMMON_OPCODE_GET_BOOT_CFG		0x42
2752#define	COMMON_OPCODE_SET_BOOT_CFG		0x43
2753#define	COMMON_OPCODE_MANAGE_FAT		0x44
2754#define	COMMON_OPCODE_GET_PHYSICAL_LINK_CFG_V1	0x47
2755#define	COMMON_OPCODE_GET_PORT_NAME		0x4D
2756
2757#define	COMMON_OPCODE_MQ_CREATE_EXT		0x5A
2758#define	COMMON_OPCODE_GET_VPD_DATA		0x5B
2759#define	COMMON_OPCODE_GET_PHY_DETAILS		0x66
2760#define	COMMON_OPCODE_SEND_ACTIVATION		0x73
2761#define	COMMON_OPCODE_RESET_LICENSES		0x74
2762#define	COMMON_OPCODE_GET_CNTL_ADDL_ATTRIB	0x79
2763
2764#define	COMMON_OPCODE_GET_EXTENTS_INFO		0x9A
2765#define	COMMON_OPCODE_GET_EXTENTS		0x9B
2766#define	COMMON_OPCODE_ALLOC_EXTENTS		0x9C
2767#define	COMMON_OPCODE_DEALLOC_EXTENTS		0x9D
2768
2769#define	COMMON_OPCODE_GET_PROFILE_CAPS		0xA1
2770#define	COMMON_OPCODE_GET_MR_PROFILE_CAPS	0xA2
2771#define	COMMON_OPCODE_SET_MR_PROFILE_CAPS	0xA3
2772#define	COMMON_OPCODE_GET_PROFILE_CFG		0xA4
2773#define	COMMON_OPCODE_SET_PROFILE_CFG		0xA5
2774#define	COMMON_OPCODE_GET_PROFILE_LIST		0xA6
2775#define	COMMON_OPCODE_GET_ACTIVE_PROFILE	0xA7
2776#define	COMMON_OPCODE_SET_ACTIVE_PROFILE	0xA8
2777#define	COMMON_OPCODE_SET_FACTORY_PROFILE_CFG	0xA9
2778
2779#define	COMMON_OPCODE_READ_OBJ			0xAB
2780#define	COMMON_OPCODE_WRITE_OBJ			0xAC
2781#define	COMMON_OPCODE_READ_OBJ_LIST		0xAD
2782#define	COMMON_OPCODE_DELETE_OBJ		0xAE
2783#define	COMMON_OPCODE_GET_SLI4_PARAMS		0xB5
2784
2785#define	FCOE_OPCODE_WQ_CREATE			0x01
2786#define	FCOE_OPCODE_CFG_POST_SGL_PAGES		0x03
2787#define	FCOE_OPCODE_RQ_CREATE			0x05
2788#define	FCOE_OPCODE_READ_FCF_TABLE		0x08
2789#define	FCOE_OPCODE_ADD_FCF_TABLE		0x09
2790#define	FCOE_OPCODE_DELETE_FCF_TABLE		0x0A
2791#define	FCOE_OPCODE_POST_HDR_TEMPLATES		0x0B
2792#define	FCOE_OPCODE_REDISCOVER_FCF_TABLE	0x10
2793#define	FCOE_OPCODE_SET_FCLINK_SETTINGS		0x21
2794
2795#define	DCBX_OPCODE_GET_DCBX_MODE		0x04
2796#define	DCBX_OPCODE_SET_DCBX_MODE		0x05
2797
2798typedef	struct
2799{
2800	struct
2801	{
2802		uint32_t opcode;
2803#define	MGMT_FLASHROM_OPCODE_FLASH		1
2804#define	MGMT_FLASHROM_OPCODE_SAVE		2
2805#define	MGMT_FLASHROM_OPCODE_CLEAR		3
2806#define	MGMT_FLASHROM_OPCODE_REPORT		4
2807#define	MGMT_FLASHROM_OPCODE_INFO		5
2808#define	MGMT_FLASHROM_OPCODE_CRC		6
2809#define	MGMT_FLASHROM_OPCODE_OFFSET_FLASH	7
2810#define	MGMT_FLASHROM_OPCODE_OFFSET_SAVE	8
2811#define	MGMT_PHY_FLASHROM_OPCODE_FLASH		9
2812#define	MGMT_PHY_FLASHROM_OPCODE_SAVE		10
2813
2814		uint32_t optype;
2815#define	MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE	0
2816#define	MGMT_FLASHROM_OPTYPE_REDBOOT		1
2817#define	MGMT_FLASHROM_OPTYPE_ISCSI_BIOS		2
2818#define	MGMT_FLASHROM_OPTYPE_PXE_BIOS		3
2819#define	MGMT_FLASHROM_OPTYPE_CTRLS		4
2820#define	MGMT_FLASHROM_OPTYPE_CFG_IPSEC		5
2821#define	MGMT_FLASHROM_OPTYPE_CFG_INI		6
2822#define	MGMT_FLASHROM_OPTYPE_ROM_OFFSET		7
2823#define	MGMT_FLASHROM_OPTYPE_FCOE_BIOS		8
2824#define	MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP	9
2825#define	MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE	10
2826#define	MGMT_FLASHROM_OPTYPE_FCOE_BACKUP	11
2827#define	MGMT_FLASHROM_OPTYPE_CTRLP		12
2828#define	MGMT_FLASHROM_OPTYPE_NCSI_FIRMWARE	13
2829#define	MGMT_FLASHROM_OPTYPE_CFG_NIC		14
2830#define	MGMT_FLASHROM_OPTYPE_CFG_DCBX		15
2831#define	MGMT_FLASHROM_OPTYPE_CFG_PXE_BIOS	16
2832#define	MGMT_FLASHROM_OPTYPE_CFG_ALL		17
2833#define	MGMT_FLASHROM_OPTYPE_PHY_FIRMWARE	0xff /* Driver defined */
2834
2835		uint32_t data_buffer_size; /* Align to 4KB */
2836		uint32_t offset;
2837		uint32_t data_buffer; /* image starts here */
2838
2839	} params;
2840
2841} IOCTL_COMMON_FLASHROM;
2842
2843
2844typedef	struct
2845{
2846	union
2847	{
2848		struct
2849		{
2850			uint32_t rsvd;
2851		} request;
2852
2853
2854		struct
2855		{
2856#ifdef EMLXS_BIG_ENDIAN
2857			uint16_t interface_type;
2858			uint16_t phy_type;
2859#endif
2860#ifdef EMLXS_LITTLE_ENDIAN
2861			uint16_t phy_type;
2862			uint16_t interface_type;
2863#endif
2864
2865/* phy_type */
2866#define	PHY_XAUI		0x0
2867#define	PHY_AEL_2020		0x1 /* eluris/Netlogic */
2868#define	PHY_LSI_BRCM1		0x2 /* Peak pre-production board */
2869#define	PHY_LSI_BRCM2		0x3 /* Peak production board */
2870#define	PHY_SOLARFLARE		0x4 /* Dell recommended */
2871#define	PHY_AMCC_QT2025		0x5 /* AMCC PHY */
2872#define	PHY_AMCC_QT2225		0x6 /* AMCC PHY */
2873#define	PHY_BRCM_5931		0x7 /* Broadcom Phy used by HP LOM */
2874#define	PHY_BE3_INTERNAL_10GB	0x8 /* Internal 10GbPHY in BE3 */
2875#define	PHY_BE3_INTERNAL_1GB	0x9 /* Internal 1Gb PHY in BE3 */
2876#define	PHY_TN_2022		0xa /* Teranetics dual port 65nm PHY */
2877#define	PHY_MARVELL_88E1340	0xb /* Marvel 1G PHY */
2878#define	PHY_MARVELL_88E1322	0xc /* Marvel 1G PHY */
2879#define	PHY_TN_8022		0xd /* Teranetics dual port 40nm PHY */
2880#define	PHY_TYPE_NOT_SUPPORTED
2881
2882/* interface_type */
2883#define	CX4_10GB_TYPE		0x0
2884#define	XFP_10GB_TYPE		0x1
2885#define	SFP_1GB_TYPE		0x2
2886#define	SFP_PLUS_10GB_TYPE	0x3
2887#define	KR_10GB_TYPE		0x4
2888#define	KX4_10GB_TYPE		0x5
2889#define	BASET_10GB_TYPE		0x6 /* 10G BaseT */
2890#define	BASET_1000_TYPE		0x7 /* 1000 BaseT */
2891#define	BASEX_1000_TYPE		0x8 /* 1000 BaseX */
2892#define	SGMII_TYPE		0x9
2893#define	INTERFACE_10GB_DISABLED	0xff /* Interface type not supported */
2894
2895			uint32_t misc_params;
2896			uint32_t rsvd[4];
2897		} response;
2898
2899	} params;
2900
2901} IOCTL_COMMON_GET_PHY_DETAILS;
2902
2903
2904typedef	struct
2905{
2906	union
2907	{
2908		struct
2909		{
2910			uint32_t rsvd;
2911		} request;
2912
2913
2914		struct
2915		{
2916#ifdef EMLXS_BIG_ENDIAN
2917			uint8_t port3_name;
2918			uint8_t port2_name;
2919			uint8_t port1_name;
2920			uint8_t port0_name;
2921#endif
2922#ifdef EMLXS_LITTLE_ENDIAN
2923			uint8_t port0_name;
2924			uint8_t port1_name;
2925			uint8_t port2_name;
2926			uint8_t port3_name;
2927#endif
2928		} response;
2929
2930	} params;
2931
2932} IOCTL_COMMON_GET_PORT_NAME;
2933
2934
2935typedef	struct
2936{
2937	union
2938	{
2939		struct
2940		{
2941#ifdef EMLXS_BIG_ENDIAN
2942			uint32_t rsvd:30;
2943			uint32_t pt:2;
2944#endif
2945#ifdef EMLXS_LITTLE_ENDIAN
2946			uint32_t pt:2;
2947			uint32_t rsvd:30;
2948#endif
2949#define	PORT_TYPE_GIGE		0
2950#define	PORT_TYPE_FC		1
2951		} request;
2952
2953
2954		struct
2955		{
2956#ifdef EMLXS_BIG_ENDIAN
2957			uint8_t port3_name;
2958			uint8_t port2_name;
2959			uint8_t port1_name;
2960			uint8_t port0_name;
2961#endif
2962#ifdef EMLXS_LITTLE_ENDIAN
2963			uint8_t port0_name;
2964			uint8_t port1_name;
2965			uint8_t port2_name;
2966			uint8_t port3_name;
2967#endif
2968		} response;
2969
2970	} params;
2971
2972} IOCTL_COMMON_GET_PORT_NAME_V1;
2973
2974
2975typedef	struct
2976{
2977	union
2978	{
2979		struct
2980		{
2981			uint32_t fat_operation;
2982#define	RETRIEVE_FAT		0
2983#define	QUERY_FAT		1
2984#define	CLEAR_FAT		2
2985
2986			uint32_t read_log_offset;
2987			uint32_t read_log_length;
2988			uint32_t data_buffer_size;
2989			uint32_t data_buffer;
2990		} request;
2991
2992		struct
2993		{
2994			uint32_t log_size;
2995			uint32_t read_log_length;
2996			uint32_t rsvd0;
2997			uint32_t rsvd1;
2998			uint32_t data_buffer;
2999		} response;
3000
3001	} params;
3002
3003} IOCTL_COMMON_MANAGE_FAT;
3004
3005
3006typedef	struct
3007{
3008	union
3009	{
3010		struct
3011		{
3012#ifdef EMLXS_BIG_ENDIAN
3013			uint32_t EOF:1; /* word 4 */
3014			uint32_t rsvd0:7;
3015			uint32_t desired_write_length:24;
3016#endif
3017#ifdef EMLXS_LITTLE_ENDIAN
3018			uint32_t desired_write_length:24;
3019			uint32_t rsvd0:7;
3020			uint32_t EOF:1;  /* word 4 */
3021#endif
3022			uint32_t write_offset;  /* word 5 */
3023			char object_name[(4 * 26)];   /* word 6 - 31 */
3024			uint32_t buffer_desc_count; /* word 32 */
3025
3026#ifdef EMLXS_BIG_ENDIAN
3027			uint32_t rsvd:8; /* word 33 */
3028			uint32_t buffer_length:24;
3029#endif
3030#ifdef EMLXS_LITTLE_ENDIAN
3031			uint32_t buffer_length:24;
3032			uint32_t rsvd:8; /* word 33 */
3033#endif
3034			uint32_t buffer_addrlo; /* word 34 */
3035			uint32_t buffer_addrhi; /* word 35 */
3036		} request;
3037
3038		struct
3039		{
3040			uint32_t actual_write_length;
3041
3042#ifdef EMLXS_BIG_ENDIAN
3043			uint32_t rsvd:24;
3044			uint32_t change_status:8;
3045#endif
3046#ifdef EMLXS_LITTLE_ENDIAN
3047			uint32_t change_status:8;
3048			uint32_t rsvd:24;
3049#endif
3050#define	CS_NO_RESET		0
3051#define	CS_REBOOT_RQD		1
3052#define	CS_FW_RESET_RQD		2
3053#define	CS_PROTO_RESET_RQD	3
3054		} response;
3055
3056	} params;
3057
3058} IOCTL_COMMON_WRITE_OBJECT;
3059
3060
3061typedef	struct
3062{
3063	union
3064	{
3065		struct
3066		{
3067#ifdef EMLXS_BIG_ENDIAN
3068			uint32_t descriptor_offset:16; /* word 4 */
3069			uint32_t descriptor_count:16;
3070#endif
3071#ifdef EMLXS_LITTLE_ENDIAN
3072			uint32_t descriptor_count:16;
3073			uint32_t descriptor_offset:16; /* word 4 */
3074#endif
3075			uint32_t reserved;  /* word 5 */
3076			char object_name[(4 * 26)];   /* word 6 - 31 */
3077			uint32_t buffer_desc_count; /* word 32 */
3078
3079#ifdef EMLXS_BIG_ENDIAN
3080			uint32_t rsvd:8; /* word 33 */
3081			uint32_t buffer_length:24;
3082#endif
3083#ifdef EMLXS_LITTLE_ENDIAN
3084			uint32_t buffer_length:24;
3085			uint32_t rsvd:8; /* word 33 */
3086#endif
3087			uint32_t buffer_addrlo; /* word 34 */
3088			uint32_t buffer_addrhi; /* word 35 */
3089		} request;
3090
3091		struct
3092		{
3093#ifdef EMLXS_BIG_ENDIAN
3094			uint32_t reserved:16;
3095			uint32_t actual_descriptor_count:16;
3096#endif
3097#ifdef EMLXS_LITTLE_ENDIAN
3098			uint32_t actual_descriptor_count:16;
3099			uint32_t reserved:16;
3100#endif
3101		} response;
3102
3103	} params;
3104
3105} IOCTL_COMMON_READ_OBJECT_LIST;
3106
3107
3108typedef	struct
3109{
3110	union
3111	{
3112		struct
3113		{
3114#ifdef EMLXS_BIG_ENDIAN
3115			uint32_t reserved:16; /* word 4 */
3116			uint32_t boot_instance:8;
3117			uint32_t boot_status:8;
3118#endif
3119#ifdef EMLXS_LITTLE_ENDIAN
3120			uint32_t boot_status:8;
3121			uint32_t boot_instance:8;
3122			uint32_t reserved:16; /* word 4 */
3123#endif
3124		} request;
3125
3126		struct
3127		{
3128#ifdef EMLXS_BIG_ENDIAN
3129			uint32_t reserved:16; /* word 4 */
3130			uint32_t boot_instance:8;
3131			uint32_t boot_status:8;
3132#endif
3133#ifdef EMLXS_LITTLE_ENDIAN
3134			uint32_t boot_status:8;
3135			uint32_t boot_instance:8;
3136			uint32_t reserved:16; /* word 4 */
3137#endif
3138		} response;
3139
3140	} params;
3141
3142} IOCTL_COMMON_BOOT_CFG;
3143
3144
3145/* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */
3146typedef struct _BE_FW_CFG
3147{
3148	uint32_t	BEConfigNumber;
3149	uint32_t	ASICRevision;
3150	uint32_t	PhysicalPort;
3151	uint32_t	FunctionMode;
3152	uint32_t	ULPMode;
3153
3154} BE_FW_CFG;
3155
3156typedef	struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG
3157{
3158	union
3159	{
3160		struct
3161		{
3162			uint32_t	rsvd0;
3163		} request;
3164
3165		BE_FW_CFG	response;
3166
3167	}	params;
3168
3169} IOCTL_COMMON_QUERY_FIRMWARE_CONFIG;
3170
3171
3172
3173/* IOCTL_FCOE_READ_FCF_TABLE */
3174typedef struct
3175{
3176	uint32_t	max_recv_size;
3177	uint32_t	fka_adv_period;
3178	uint32_t	fip_priority;
3179
3180#ifdef EMLXS_BIG_ENDIAN
3181	uint8_t		fcf_mac_address_hi[4];
3182
3183	uint8_t		mac_address_provider;
3184	uint8_t		fcf_available;
3185	uint8_t		fcf_mac_address_low[2];
3186
3187	uint8_t		fabric_name_identifier[8];
3188
3189	uint8_t		fcf_sol:1;
3190	uint8_t		rsvd0:5;
3191	uint8_t		fcf_fc:1;
3192	uint8_t		fcf_valid:1;
3193	uint8_t		fc_map[3];
3194
3195	uint16_t	fcf_state;
3196	uint16_t	fcf_index;
3197#endif
3198#ifdef EMLXS_LITTLE_ENDIAN
3199	uint8_t		fcf_mac_address_hi[4];
3200
3201	uint8_t		fcf_mac_address_low[2];
3202	uint8_t		fcf_available;
3203	uint8_t		mac_address_provider;
3204
3205	uint8_t		fabric_name_identifier[8];
3206
3207	uint8_t		fc_map[3];
3208	uint8_t		fcf_valid:1;
3209	uint8_t		fcf_fc:1;
3210	uint8_t		rsvd0:5;
3211	uint8_t		fcf_sol:1;
3212
3213	uint16_t	fcf_index;
3214	uint16_t	fcf_state;
3215#endif
3216
3217	uint8_t		vlan_bitmap[512];
3218	uint8_t		switch_name_identifier[8];
3219
3220} FCF_RECORD_t;
3221
3222#define	EMLXS_FCOE_MAX_RCV_SZ	0x800
3223
3224/* defines for mac_address_provider */
3225#define	EMLXS_MAM_BOTH	0	/* Both SPMA and FPMA */
3226#define	EMLXS_MAM_FPMA	1	/* Fabric Provided MAC Address */
3227#define	EMLXS_MAM_SPMA	2	/* Server Provided MAC Address */
3228
3229typedef struct
3230{
3231	union
3232	{
3233		struct
3234		{
3235#ifdef EMLXS_BIG_ENDIAN
3236			uint16_t	rsvd0;
3237			uint16_t	fcf_index;
3238#endif
3239#ifdef EMLXS_LITTLE_ENDIAN
3240			uint16_t	fcf_index;
3241			uint16_t	rsvd0;
3242#endif
3243
3244		} request;
3245
3246		struct
3247		{
3248			uint32_t	event_tag;
3249#ifdef EMLXS_BIG_ENDIAN
3250			uint16_t	rsvd0;
3251			uint16_t	next_valid_fcf_index;
3252#endif
3253#ifdef EMLXS_LITTLE_ENDIAN
3254			uint16_t	next_valid_fcf_index;
3255			uint16_t	rsvd0;
3256#endif
3257			FCF_RECORD_t fcf_entry[1];
3258
3259		} response;
3260
3261	} params;
3262
3263} IOCTL_FCOE_READ_FCF_TABLE;
3264
3265
3266/* IOCTL_FCOE_ADD_FCF_TABLE */
3267typedef struct
3268{
3269	union
3270	{
3271		struct
3272		{
3273#ifdef EMLXS_BIG_ENDIAN
3274			uint16_t	rsvd0;
3275			uint16_t	fcf_index;
3276#endif
3277#ifdef EMLXS_LITTLE_ENDIAN
3278			uint16_t	fcf_index;
3279			uint16_t	rsvd0;
3280#endif
3281			FCF_RECORD_t fcf_entry;
3282
3283		} request;
3284	} params;
3285
3286} IOCTL_FCOE_ADD_FCF_TABLE;
3287
3288
3289/* IOCTL_FCOE_DELETE_FCF_TABLE */
3290typedef struct
3291{
3292	union
3293	{
3294		struct
3295		{
3296#ifdef EMLXS_BIG_ENDIAN
3297			uint16_t	fcf_indexes[1];
3298			uint16_t	fcf_count;
3299#endif
3300#ifdef EMLXS_LITTLE_ENDIAN
3301			uint16_t	fcf_count;
3302			uint16_t	fcf_indexes[1];
3303#endif
3304
3305		} request;
3306	} params;
3307
3308} IOCTL_FCOE_DELETE_FCF_TABLE;
3309
3310
3311/* IOCTL_FCOE_REDISCOVER_FCF_TABLE */
3312typedef struct
3313{
3314	union
3315	{
3316		struct
3317		{
3318#ifdef EMLXS_BIG_ENDIAN
3319			uint16_t	rsvd0;
3320			uint16_t	fcf_count;
3321#endif
3322#ifdef EMLXS_LITTLE_ENDIAN
3323			uint16_t	fcf_count;
3324			uint16_t	rsvd0;
3325#endif
3326			uint32_t	rsvd1;
3327			uint16_t	fcf_index[1];
3328
3329		} request;
3330	} params;
3331
3332} IOCTL_FCOE_REDISCOVER_FCF_TABLE;
3333
3334
3335#define	FCOE_FCF_MAC0	0x0E
3336#define	FCOE_FCF_MAC1	0xFC
3337#define	FCOE_FCF_MAC2	0x00
3338#define	FCOE_FCF_MAC3	0xFF
3339#define	FCOE_FCF_MAC4	0xFF
3340#define	FCOE_FCF_MAC5	0xFE
3341
3342#define	FCOE_FCF_MAP0	0x0E
3343#define	FCOE_FCF_MAP1	0xFC
3344#define	FCOE_FCF_MAP2	0x00
3345
3346#define	MGMT_STATUS_FCF_IN_USE	0x3a
3347
3348/* IOCTL_COMMON_NOP */
3349typedef	struct _IOCTL_COMMON_NOP
3350{
3351	union
3352	{
3353		struct
3354		{
3355			uint64_t	context;
3356		} request;
3357
3358		struct
3359		{
3360			uint64_t	context;
3361		} response;
3362
3363	} params;
3364
3365} IOCTL_COMMON_NOP;
3366
3367
3368/*	Context for EQ create	*/
3369typedef	struct _EQ_CONTEXT
3370{
3371#ifdef EMLXS_BIG_ENDIAN
3372	uint32_t	Size:1;
3373	uint32_t	Rsvd2:1;
3374	uint32_t	Valid:1;
3375	uint32_t	Rsvd1:29;
3376
3377	uint32_t	Armed:1;
3378	uint32_t	Rsvd4:2;
3379	uint32_t	Count:3;
3380	uint32_t	Rsvd3:26;
3381
3382	uint32_t	Rsvd6:9;
3383	uint32_t	DelayMult:10;
3384	uint32_t	Rsvd5:13;
3385#endif
3386#ifdef EMLXS_LITTLE_ENDIAN
3387	uint32_t	Rsvd1:29;
3388	uint32_t	Valid:1;
3389	uint32_t	Rsvd2:1;
3390	uint32_t	Size:1;
3391
3392	uint32_t	Rsvd3:26;
3393	uint32_t	Count:3;
3394	uint32_t	Rsvd4:2;
3395	uint32_t	Armed:1;
3396
3397	uint32_t	Rsvd5:13;
3398	uint32_t	DelayMult:10;
3399	uint32_t	Rsvd6:9;
3400#endif
3401
3402	uint32_t	Rsvd7;
3403
3404} EQ_CONTEXT;
3405
3406
3407/* define for Count field */
3408#define	EQ_ELEMENT_COUNT_1024	2
3409#define	EQ_ELEMENT_COUNT_2048	3
3410#define	EQ_ELEMENT_COUNT_4096	4
3411
3412/* define for Size field */
3413#define	EQ_ELEMENT_SIZE_4	0
3414
3415/* define for DelayMullt - used for interrupt coalescing */
3416#define	EQ_DELAY_MULT		64
3417
3418/*	Context for CQ create	*/
3419typedef	struct _CQ_CONTEXT
3420{
3421#ifdef EMLXS_BIG_ENDIAN
3422	uint32_t	Eventable:1;
3423	uint32_t	Rsvd3:1;
3424	uint32_t	Valid:1;
3425	uint32_t	Count:2;
3426	uint32_t	Rsvd2:12;
3427	uint32_t	NoDelay:1;
3428	uint32_t	CoalesceWM:2;
3429	uint32_t	Rsvd1:12;
3430
3431	uint32_t	Armed:1;
3432	uint32_t	Rsvd5:1;
3433	uint32_t	EQId:8;
3434	uint32_t	Rsvd4:22;
3435
3436	uint32_t	Rsvd6;
3437#endif
3438#ifdef EMLXS_LITTLE_ENDIAN
3439	uint32_t	Rsvd1:12;
3440	uint32_t	CoalesceWM:2;
3441	uint32_t	NoDelay:1;
3442	uint32_t	Rsvd2:12;
3443	uint32_t	Count:2;
3444	uint32_t	Valid:1;
3445	uint32_t	Rsvd3:1;
3446	uint32_t	Eventable:1;
3447
3448	uint32_t	Rsvd4:22;
3449	uint32_t	EQId:8;
3450	uint32_t	Rsvd5:1;
3451	uint32_t	Armed:1;
3452
3453	uint32_t	Rsvd6;
3454#endif
3455
3456	uint32_t	Rsvd7;
3457
3458} CQ_CONTEXT;
3459
3460typedef	struct _CQ_CONTEXT_V2
3461{
3462#ifdef EMLXS_BIG_ENDIAN
3463	uint32_t	Eventable:1;
3464	uint32_t	Rsvd3:1;
3465	uint32_t	Valid:1;
3466	uint32_t	CqeCnt:2;
3467	uint32_t	CqeSize:2;
3468	uint32_t	Rsvd2:9;
3469	uint32_t	AutoValid:1;
3470	uint32_t	NoDelay:1;
3471	uint32_t	CoalesceWM:2;
3472	uint32_t	Rsvd1:12;
3473
3474	uint32_t	Armed:1;
3475	uint32_t	Rsvd4:15;
3476	uint32_t	EQId:16;
3477
3478	uint32_t	Rsvd5:16;
3479	uint32_t	Count1:16;
3480#endif
3481#ifdef EMLXS_LITTLE_ENDIAN
3482	uint32_t	Rsvd1:12;
3483	uint32_t	CoalesceWM:2;
3484	uint32_t	NoDelay:1;
3485	uint32_t	AutoValid:1;
3486	uint32_t	Rsvd2:9;
3487	uint32_t	CqeSize:2;
3488	uint32_t	CqeCnt:2;
3489	uint32_t	Valid:1;
3490	uint32_t	Rsvd3:1;
3491	uint32_t	Eventable:1;
3492
3493	uint32_t	EQId:16;
3494	uint32_t	Rsvd4:15;
3495	uint32_t	Armed:1;
3496
3497	uint32_t	Count1:16;
3498	uint32_t	Rsvd5:16;
3499#endif
3500
3501	uint32_t	Rsvd7;
3502
3503} CQ_CONTEXT_V2;
3504
3505/* CqeSize */
3506#define	CQE_SIZE_16_BYTES	0
3507#define	CQE_SIZE_32_BYTES	1
3508
3509/* define for Count field */
3510#define	CQ_ELEMENT_COUNT_256	0
3511#define	CQ_ELEMENT_COUNT_512	1
3512#define	CQ_ELEMENT_COUNT_1024	2
3513#define	CQ_ELEMENT_COUNT_SPECIFIED	3
3514
3515/*	Context for MQ create	*/
3516typedef	struct _MQ_CONTEXT
3517{
3518#ifdef EMLXS_BIG_ENDIAN
3519	uint32_t	CQId:10;
3520	uint32_t	Rsvd2:2;
3521	uint32_t	Size:4;
3522	uint32_t	Rsvd1:16;
3523
3524	uint32_t	Valid:1;
3525	uint32_t	Rsvd3:31;
3526
3527	uint32_t	Rsvd4:21;
3528	uint32_t	ACQId:10;
3529	uint32_t	ACQV:1;
3530#endif
3531#ifdef EMLXS_LITTLE_ENDIAN
3532	uint32_t	Rsvd1:16;
3533	uint32_t	Size:4;
3534	uint32_t	Rsvd2:2;
3535	uint32_t	CQId:10;
3536
3537	uint32_t	Rsvd3:31;
3538	uint32_t	Valid:1;
3539
3540	uint32_t	ACQV:1;
3541	uint32_t	ACQId:10;
3542	uint32_t	Rsvd4:21;
3543#endif
3544
3545	uint32_t	Rsvd5;
3546
3547} MQ_CONTEXT;
3548
3549
3550typedef	struct _MQ_CONTEXT_V1
3551{
3552#ifdef EMLXS_BIG_ENDIAN
3553	uint32_t	Rsvd2:12;
3554	uint32_t	Size:4;
3555	uint32_t	ACQId:16;
3556
3557	uint32_t	Valid:1;
3558	uint32_t	Rsvd3:31;
3559
3560	uint32_t	Rsvd4:31;
3561	uint32_t	ACQV:1;
3562#endif
3563#ifdef EMLXS_LITTLE_ENDIAN
3564	uint32_t	ACQId:16;
3565	uint32_t	Size:4;
3566	uint32_t	Rsvd2:12;
3567
3568	uint32_t	Rsvd3:31;
3569	uint32_t	Valid:1;
3570
3571	uint32_t	ACQV:1;
3572	uint32_t	Rsvd4:31;
3573#endif
3574
3575	uint32_t	Rsvd5;
3576
3577} MQ_CONTEXT_V1;
3578
3579
3580/* define for Size field */
3581#define	MQ_ELEMENT_COUNT_16 0x05
3582
3583/*	Context for RQ create	*/
3584typedef	struct _RQ_CONTEXT
3585{
3586#ifdef EMLXS_BIG_ENDIAN
3587	uint32_t	Rsvd2:12;
3588	uint32_t	RqeCnt:4;
3589	uint32_t	Rsvd1:16;
3590
3591	uint32_t	Rsvd3;
3592
3593	uint32_t	CQId:16;
3594	uint32_t	BufferSize:16;
3595#endif
3596#ifdef EMLXS_LITTLE_ENDIAN
3597	uint32_t	Rsvd1:16;
3598	uint32_t	RqeCnt:4;
3599	uint32_t	Rsvd2:12;
3600
3601	uint32_t	Rsvd3;
3602
3603	uint32_t	BufferSize:16;
3604	uint32_t	CQId:16;
3605#endif
3606
3607	uint32_t  Rsvd5;
3608
3609} RQ_CONTEXT;
3610
3611typedef	struct _RQ_CONTEXT_V1
3612{
3613#ifdef EMLXS_BIG_ENDIAN
3614	uint32_t	RqeCnt:16;
3615	uint32_t	Rsvd1:4;
3616	uint32_t	RqeSize:4;
3617	uint32_t	PageSize:8;
3618
3619	uint32_t	Rsvd2;
3620
3621	uint32_t	CQId:16;
3622	uint32_t	Rsvd:16;
3623#endif
3624#ifdef EMLXS_LITTLE_ENDIAN
3625	uint32_t	PageSize:8;
3626	uint32_t	RqeSize:4;
3627	uint32_t	Rsvd1:4;
3628	uint32_t	RqeCnt:16;
3629
3630	uint32_t	Rsvd2;
3631
3632	uint32_t	Rsvd:16;
3633	uint32_t	CQId:16;
3634#endif
3635
3636	uint32_t	BufferSize;
3637
3638} RQ_CONTEXT_V1;
3639
3640/* RqeSize */
3641#define	RQE_SIZE_8_BYTES	0x02
3642#define	RQE_SIZE_16_BYTES	0x03
3643#define	RQE_SIZE_32_BYTES	0x04
3644#define	RQE_SIZE_64_BYTES	0x05
3645#define	RQE_SIZE_128_BYTES	0x06
3646
3647/* RQ PageSize */
3648#define	RQ_PAGE_SIZE_4K		0x01
3649#define	RQ_PAGE_SIZE_8K		0x02
3650#define	RQ_PAGE_SIZE_16K	0x04
3651#define	RQ_PAGE_SIZE_32K	0x08
3652#define	RQ_PAGE_SIZE_64K	0x10
3653
3654
3655/* IOCTL_COMMON_EQ_CREATE */
3656typedef	struct
3657{
3658	union
3659	{
3660		struct
3661		{
3662#ifdef EMLXS_BIG_ENDIAN
3663			uint16_t	Rsvd1;
3664			uint16_t	NumPages;
3665#endif
3666#ifdef EMLXS_LITTLE_ENDIAN
3667			uint16_t	NumPages;
3668			uint16_t	Rsvd1;
3669#endif
3670			EQ_CONTEXT	EQContext;
3671			BE_PHYS_ADDR	Pages[8];
3672		} request;
3673
3674		struct
3675		{
3676#ifdef EMLXS_BIG_ENDIAN
3677			uint16_t	MsiIndex; /* V1 only */
3678			uint16_t	EQId;
3679#endif
3680#ifdef EMLXS_LITTLE_ENDIAN
3681			uint16_t	EQId;
3682			uint16_t	MsiIndex; /* V1 only */
3683#endif
3684		} response;
3685	} params;
3686
3687} IOCTL_COMMON_EQ_CREATE;
3688
3689
3690typedef	struct
3691{
3692#ifdef EMLXS_BIG_ENDIAN
3693		uint32_t	Rsvd1:24;		/* Word 0 */
3694		uint32_t	ProtocolType:8;
3695
3696		uint32_t	Rsvd3:3;		/* Word 1 */
3697		uint32_t	SliHint2:5;
3698		uint32_t	SliHint1:8;
3699		uint32_t	IfType:4;
3700		uint32_t	SliFamily:4;
3701		uint32_t	Revision:4;
3702		uint32_t	Rsvd2:3;
3703		uint32_t	FT:1;
3704
3705		uint32_t	EqRsvd3:4;		/* Word 2 */
3706		uint32_t	EqeCntMethod:4;
3707		uint32_t	EqPageSize:8;
3708		uint32_t	EqRsvd2:4;
3709		uint32_t	EqeSize:4;
3710		uint32_t	EqRsvd1:4;
3711		uint32_t	EqPageCnt:4;
3712
3713		uint32_t	EqRsvd4:16;		/* Word 3 */
3714		uint32_t	EqeCntMask:16;
3715
3716		uint32_t	CqRsvd3:4;		/* Word 4 */
3717		uint32_t	CqeCntMethod:4;
3718		uint32_t	CqPageSize:8;
3719		uint32_t	CQV:2;
3720		uint32_t	CqRsvd2:2;
3721		uint32_t	CqeSize:4;
3722		uint32_t	CqRsvd1:4;
3723		uint32_t	CqPageCnt:4;
3724
3725		uint32_t	CqRsvd4:16;		/* Word 5 */
3726		uint32_t	CqeCntMask:16;
3727
3728		uint32_t	MqRsvd2:4;		/* Word 6 */
3729		uint32_t	MqeCntMethod:4;
3730		uint32_t	MqPageSize:8;
3731		uint32_t	MQV:2;
3732		uint32_t	MqRsvd1:10;
3733		uint32_t	MqPageCnt:4;
3734
3735		uint32_t	MqRsvd3:16;		/* Word 7 */
3736		uint32_t	MqeCntMask:16;
3737
3738		uint32_t	WqRsvd3:4;		/* Word 8 */
3739		uint32_t	WqeCntMethod:4;
3740		uint32_t	WqPageSize:8;
3741		uint32_t	WQV:2;
3742		uint32_t	WqeRsvd2:2;
3743		uint32_t	WqeSize:4;
3744		uint32_t	WqRsvd1:4;
3745		uint32_t	WqPageCnt:4;
3746
3747		uint32_t	WqRsvd4:16;		/* Word 9 */
3748		uint32_t	WqeCntMask:16;
3749
3750		uint32_t	RqRsvd3:4;		/* Word 10 */
3751		uint32_t	RqeCntMethod:4;
3752		uint32_t	RqPageSize:8;
3753		uint32_t	RQV:2;
3754		uint32_t	RqeRsvd2:2;
3755		uint32_t	RqeSize:4;
3756		uint32_t	RqRsvd1:4;
3757		uint32_t	RqPageCnt:4;
3758
3759		uint32_t	RqDbWin:4;		/* Word 11 */
3760		uint32_t	RqRsvd4:12;
3761		uint32_t	RqeCntMask:16;
3762
3763		uint32_t	Loopback:4;		/* Word 12 */
3764		uint32_t	Rsvd4:12;
3765		uint32_t	PHWQ:1;
3766		uint32_t	PHON:1;
3767		uint32_t	PHOFF:1;
3768		uint32_t	TRIR:1;
3769		uint32_t	TRTY:1;
3770		uint32_t	TCCA:1;
3771		uint32_t	MWQE:1;
3772		uint32_t	ASSI:1;
3773		uint32_t	TERP:1;
3774		uint32_t	TGT:1;
3775		uint32_t	AREG:1;
3776		uint32_t	FBRR:1;
3777		uint32_t	SGLR:1;
3778		uint32_t	HDRR:1;
3779		uint32_t	EXT:1;
3780		uint32_t	FCOE:1;
3781
3782		uint32_t	SgeLength;		/* Word 13 */
3783
3784		uint32_t	SglRsvd2:8;		/* Word 14 */
3785		uint32_t	SglAlign:8;
3786		uint32_t	SglPageSize:8;
3787		uint32_t	SglRsvd1:4;
3788		uint32_t	SglPageCnt:4;
3789
3790		uint32_t	Rsvd5:16;		/* Word 15 */
3791		uint32_t	MinRqSize:16;
3792
3793		uint32_t	MaxRqSize;		/* Word 16 */
3794
3795		uint32_t	RPIMax:16;
3796		uint32_t	XRIMax:16;		/* Word 17 */
3797
3798		uint32_t	VFIMax:16;
3799		uint32_t	VPIMax:16;		/* Word 18 */
3800#endif
3801#ifdef EMLXS_LITTLE_ENDIAN
3802		uint32_t	ProtocolType:8;		/* Word 0 */
3803		uint32_t	Rsvd1:24;
3804
3805		uint32_t	FT:1;			/* Word 1 */
3806		uint32_t	Rsvd2:3;
3807		uint32_t	Revision:4;
3808		uint32_t	SliFamily:4;
3809		uint32_t	IfType:4;
3810		uint32_t	SliHint1:8;
3811		uint32_t	SliHint2:5;
3812		uint32_t	Rsvd3:3;
3813
3814		uint32_t	EqPageCnt:4;		/* Word 2 */
3815		uint32_t	EqRsvd1:4;
3816		uint32_t	EqeSize:4;
3817		uint32_t	EqRsvd2:4;
3818		uint32_t	EqPageSize:8;
3819		uint32_t	EqeCntMethod:4;
3820		uint32_t	EqRsvd3:4;
3821
3822		uint32_t	EqeCntMask:16;		/* Word 3 */
3823		uint32_t	EqRsvd4:16;
3824
3825		uint32_t	CqPageCnt:4;		/* Word 4 */
3826		uint32_t	CqRsvd1:4;
3827		uint32_t	CqeSize:4;
3828		uint32_t	CqRsvd2:2;
3829		uint32_t	CQV:2;
3830		uint32_t	CqPageSize:8;
3831		uint32_t	CqeCntMethod:4;
3832		uint32_t	CqRsvd3:4;
3833
3834		uint32_t	CqeCntMask:16;		/* Word 5 */
3835		uint32_t	CqRsvd4:16;
3836
3837		uint32_t	MqPageCnt:4;		/* Word 6 */
3838		uint32_t	MqRsvd1:10;
3839		uint32_t	MQV:2;
3840		uint32_t	MqPageSize:8;
3841		uint32_t	MqeCntMethod:4;
3842		uint32_t	MqRsvd2:4;
3843
3844		uint32_t	MqeCntMask:16;		/* Word 7 */
3845		uint32_t	MqRsvd3:16;
3846
3847		uint32_t	WqPageCnt:4;		/* Word 8 */
3848		uint32_t	WqRsvd1:4;
3849		uint32_t	WqeSize:4;
3850		uint32_t	WqeRsvd2:2;
3851		uint32_t	WQV:2;
3852		uint32_t	WqPageSize:8;
3853		uint32_t	WqeCntMethod:4;
3854		uint32_t	WqRsvd3:4;
3855
3856		uint32_t	WqeCntMask:16;		/* Word 9 */
3857		uint32_t	WqRsvd4:16;
3858
3859		uint32_t	RqPageCnt:4;		/* Word 10 */
3860		uint32_t	RqRsvd1:4;
3861		uint32_t	RqeSize:4;
3862		uint32_t	RqeRsvd2:2;
3863		uint32_t	RQV:2;
3864		uint32_t	RqPageSize:8;
3865		uint32_t	RqeCntMethod:4;
3866		uint32_t	RqRsvd3:4;
3867
3868		uint32_t	RqeCntMask:16;		/* Word 11 */
3869		uint32_t	RqRsvd4:12;
3870		uint32_t	RqDbWin:4;
3871
3872		uint32_t	FCOE:1;			/* Word 12 */
3873		uint32_t	EXT:1;
3874		uint32_t	HDRR:1;
3875		uint32_t	SGLR:1;
3876		uint32_t	FBRR:1;
3877		uint32_t	AREG:1;
3878		uint32_t	TGT:1;
3879		uint32_t	TERP:1;
3880		uint32_t	ASSI:1;
3881		uint32_t	MWQE:1;
3882		uint32_t	TCCA:1;
3883		uint32_t	TRTY:1;
3884		uint32_t	TRIR:1;
3885		uint32_t	PHOFF:1;
3886		uint32_t	PHON:1;
3887		uint32_t	PHWQ:1;
3888		uint32_t	Rsvd4:12;
3889		uint32_t	Loopback:4;
3890
3891		uint32_t	SgeLength;		/* Word 13 */
3892
3893		uint32_t	SglPageCnt:4;		/* Word 14 */
3894		uint32_t	SglRsvd1:4;
3895		uint32_t	SglPageSize:8;
3896		uint32_t	SglAlign:8;
3897		uint32_t	SglRsvd2:8;
3898
3899		uint32_t	MinRqSize:16;		/* Word 15 */
3900		uint32_t	Rsvd5:16;
3901
3902		uint32_t	MaxRqSize;		/* Word 16 */
3903
3904		uint32_t	XRIMax:16;		/* Word 17 */
3905		uint32_t	RPIMax:16;
3906
3907		uint32_t	VPIMax:16;		/* Word 18 */
3908		uint32_t	VFIMax:16;
3909#endif
3910
3911		uint32_t	Rsvd6;			/* Word 19 */
3912
3913} sli_params_t;
3914
3915/* SliFamily values */
3916#define	SLI_FAMILY_BE2		0x0
3917#define	SLI_FAMILY_BE3		0x1
3918#define	SLI_FAMILY_LANCER_A	0xA
3919#define	SLI_FAMILY_LANCER_B	0xB
3920
3921
3922
3923/* IOCTL_COMMON_SLI4_PARAMS */
3924typedef	struct
3925{
3926	union
3927	{
3928		struct
3929		{
3930			uint32_t	Rsvd1;
3931		} request;
3932
3933		struct
3934		{
3935			sli_params_t param;
3936		} response;
3937	} params;
3938
3939} IOCTL_COMMON_SLI4_PARAMS;
3940
3941
3942#define	MAX_EXTENTS		16 /* 1 to 104 */
3943
3944/* IOCTL_COMMON_EXTENTS */
3945typedef	struct
3946{
3947	union
3948	{
3949		struct
3950		{
3951#ifdef EMLXS_BIG_ENDIAN
3952			uint16_t	RscCnt;
3953			uint16_t	RscType;
3954#endif
3955#ifdef EMLXS_LITTLE_ENDIAN
3956			uint16_t	RscType;
3957			uint16_t	RscCnt;
3958#endif
3959		} request;
3960
3961		struct
3962		{
3963#ifdef EMLXS_BIG_ENDIAN
3964			uint16_t	ExtentSize;
3965			uint16_t	ExtentCnt;
3966#endif
3967#ifdef EMLXS_LITTLE_ENDIAN
3968			uint16_t	ExtentCnt;
3969			uint16_t	ExtentSize;
3970#endif
3971
3972			uint16_t	RscId[MAX_EXTENTS];
3973
3974		} response;
3975	} params;
3976
3977} IOCTL_COMMON_EXTENTS;
3978
3979/* RscType */
3980#define	RSC_TYPE_FCOE_VFI	0x20
3981#define	RSC_TYPE_FCOE_VPI	0x21
3982#define	RSC_TYPE_FCOE_RPI	0x22
3983#define	RSC_TYPE_FCOE_XRI	0x23
3984
3985
3986
3987/* IOCTL_COMMON_CQ_CREATE */
3988typedef	struct
3989{
3990	union
3991	{
3992		struct
3993		{
3994#ifdef EMLXS_BIG_ENDIAN
3995			uint16_t	Rsvd1;
3996			uint16_t	NumPages;
3997#endif
3998#ifdef EMLXS_LITTLE_ENDIAN
3999			uint16_t	NumPages;
4000			uint16_t	Rsvd1;
4001#endif
4002			CQ_CONTEXT	CQContext;
4003			BE_PHYS_ADDR	Pages[4];
4004		} request;
4005
4006		struct
4007		{
4008#ifdef EMLXS_BIG_ENDIAN
4009			uint16_t	Rsvd1;
4010			uint16_t	CQId;
4011#endif
4012#ifdef EMLXS_LITTLE_ENDIAN
4013			uint16_t	CQId;
4014			uint16_t	Rsvd1;
4015#endif
4016		} response;
4017	} params;
4018
4019} IOCTL_COMMON_CQ_CREATE;
4020
4021
4022/* IOCTL_COMMON_CQ_CREATE_V2 */
4023typedef	struct
4024{
4025	union
4026	{
4027		struct
4028		{
4029#ifdef EMLXS_BIG_ENDIAN
4030			uint8_t		Rsvd1;
4031			uint8_t		PageSize;
4032			uint16_t	NumPages;
4033#endif
4034#ifdef EMLXS_LITTLE_ENDIAN
4035			uint16_t	NumPages;
4036			uint8_t		PageSize;
4037			uint8_t		Rsvd1;
4038#endif
4039			CQ_CONTEXT_V2	CQContext;
4040			BE_PHYS_ADDR	Pages[8];
4041		} request;
4042
4043		struct
4044		{
4045#ifdef EMLXS_BIG_ENDIAN
4046			uint16_t	Rsvd1;
4047			uint16_t	CQId;
4048#endif
4049#ifdef EMLXS_LITTLE_ENDIAN
4050			uint16_t	CQId;
4051			uint16_t	Rsvd1;
4052#endif
4053		} response;
4054	} params;
4055
4056} IOCTL_COMMON_CQ_CREATE_V2;
4057
4058#define	CQ_PAGE_SIZE_4K		0x01
4059#define	CQ_PAGE_SIZE_8K		0x02
4060#define	CQ_PAGE_SIZE_16K	0x04
4061#define	CQ_PAGE_SIZE_32K	0x08
4062#define	CQ_PAGE_SIZE_64K	0x10
4063
4064
4065
4066/* IOCTL_COMMON_MQ_CREATE */
4067typedef	struct
4068{
4069	union
4070	{
4071		struct
4072		{
4073#ifdef EMLXS_BIG_ENDIAN
4074			uint16_t	Rsvd1;
4075			uint16_t	NumPages;
4076#endif
4077#ifdef EMLXS_LITTLE_ENDIAN
4078			uint16_t	NumPages;
4079			uint16_t	Rsvd1;
4080#endif
4081			MQ_CONTEXT	MQContext;
4082			BE_PHYS_ADDR	Pages[8];
4083		} request;
4084
4085		struct
4086		{
4087#ifdef EMLXS_BIG_ENDIAN
4088			uint16_t	Rsvd1;
4089			uint16_t	MQId;
4090#endif
4091#ifdef EMLXS_LITTLE_ENDIAN
4092			uint16_t	MQId;
4093			uint16_t	Rsvd1;
4094#endif
4095		} response;
4096	} params;
4097
4098} IOCTL_COMMON_MQ_CREATE;
4099
4100
4101/* IOCTL_COMMON_MQ_CREATE_EXT */
4102typedef	struct
4103{
4104	union
4105	{
4106		struct
4107		{
4108#ifdef EMLXS_BIG_ENDIAN
4109			uint16_t	rsvd0;
4110			uint16_t	num_pages;
4111#endif
4112#ifdef EMLXS_LITTLE_ENDIAN
4113			uint16_t	num_pages;
4114			uint16_t	rsvd0;
4115#endif
4116			uint32_t	async_event_bitmap;
4117
4118#define	ASYNC_LINK_EVENT	0x00000002
4119#define	ASYNC_FCF_EVENT		0x00000004
4120#define	ASYNC_DCBX_EVENT	0x00000008
4121#define	ASYNC_iSCSI_EVENT	0x00000010
4122#define	ASYNC_GROUP5_EVENT	0x00000020
4123#define	ASYNC_FC_EVENT		0x00010000
4124#define	ASYNC_PORT_EVENT	0x00020000
4125#define	ASYNC_VF_EVENT		0x00040000
4126#define	ASYNC_MR_EVENT		0x00080000
4127
4128			MQ_CONTEXT	context;
4129			BE_PHYS_ADDR	pages[8];
4130		} request;
4131
4132		struct
4133		{
4134#ifdef EMLXS_BIG_ENDIAN
4135			uint16_t	rsvd0;
4136			uint16_t	MQId;
4137#endif
4138#ifdef EMLXS_LITTLE_ENDIAN
4139			uint16_t	MQId;
4140			uint16_t	rsvd0;
4141#endif
4142		} response;
4143
4144	} params;
4145
4146} IOCTL_COMMON_MQ_CREATE_EXT;
4147
4148
4149/* IOCTL_COMMON_MQ_CREATE_EXT_V1 */
4150typedef	struct
4151{
4152	union
4153	{
4154		struct
4155		{
4156#ifdef EMLXS_BIG_ENDIAN
4157			uint16_t	CQId;
4158			uint16_t	num_pages;
4159#endif
4160#ifdef EMLXS_LITTLE_ENDIAN
4161			uint16_t	num_pages;
4162			uint16_t	CQId;
4163#endif
4164			uint32_t	async_event_bitmap;
4165
4166			MQ_CONTEXT_V1	context;
4167			BE_PHYS_ADDR	pages[8];
4168		} request;
4169
4170		struct
4171		{
4172#ifdef EMLXS_BIG_ENDIAN
4173			uint16_t	rsvd0;
4174			uint16_t	MQId;
4175#endif
4176#ifdef EMLXS_LITTLE_ENDIAN
4177			uint16_t	MQId;
4178			uint16_t	rsvd0;
4179#endif
4180		} response;
4181
4182	} params;
4183
4184} IOCTL_COMMON_MQ_CREATE_EXT_V1;
4185
4186
4187/* IOCTL_FCOE_RQ_CREATE */
4188typedef	struct
4189{
4190	union
4191	{
4192		struct
4193		{
4194#ifdef EMLXS_BIG_ENDIAN
4195			uint16_t	Rsvd0;
4196			uint16_t	NumPages;
4197#endif
4198#ifdef EMLXS_LITTLE_ENDIAN
4199			uint16_t	NumPages;
4200			uint16_t	Rsvd0;
4201#endif
4202			RQ_CONTEXT	RQContext;
4203			BE_PHYS_ADDR	Pages[8];
4204		} request;
4205
4206		struct
4207		{
4208#ifdef EMLXS_BIG_ENDIAN
4209			uint16_t	Rsvd1;
4210			uint16_t	RQId;
4211#endif
4212#ifdef EMLXS_LITTLE_ENDIAN
4213			uint16_t	RQId;
4214			uint16_t	Rsvd1;
4215#endif
4216		} response;
4217
4218	} params;
4219
4220} IOCTL_FCOE_RQ_CREATE;
4221
4222
4223/* IOCTL_FCOE_RQ_CREATE_V1 */
4224typedef	struct
4225{
4226	union
4227	{
4228		struct
4229		{
4230#ifdef EMLXS_BIG_ENDIAN
4231			uint32_t 	DNB:1;
4232			uint32_t 	DFD:1;
4233			uint32_t 	DIM:1;
4234			uint32_t	Rsvd0:13;
4235			uint32_t	NumPages:16;
4236#endif
4237#ifdef EMLXS_LITTLE_ENDIAN
4238			uint32_t	NumPages:16;
4239			uint32_t	Rsvd0:13;
4240			uint32_t 	DIM:1;
4241			uint32_t 	DFD:1;
4242			uint32_t 	DNB:1;
4243#endif
4244			RQ_CONTEXT_V1	RQContext;
4245			BE_PHYS_ADDR	Pages[8];
4246		} request;
4247
4248		struct
4249		{
4250#ifdef EMLXS_BIG_ENDIAN
4251			uint16_t	Rsvd1;
4252			uint16_t	RQId;
4253#endif
4254#ifdef EMLXS_LITTLE_ENDIAN
4255			uint16_t	RQId;
4256			uint16_t	Rsvd1;
4257#endif
4258		} response;
4259
4260	} params;
4261
4262} IOCTL_FCOE_RQ_CREATE_V1;
4263
4264
4265/* IOCTL_FCOE_WQ_CREATE */
4266typedef	struct
4267{
4268	union
4269	{
4270		struct
4271		{
4272#ifdef EMLXS_BIG_ENDIAN
4273			uint16_t	CQId;
4274			uint16_t	NumPages;
4275#endif
4276#ifdef EMLXS_LITTLE_ENDIAN
4277			uint16_t	NumPages;
4278			uint16_t	CQId;
4279#endif
4280			BE_PHYS_ADDR	Pages[4];
4281		} request;
4282
4283		struct
4284		{
4285#ifdef EMLXS_BIG_ENDIAN
4286			uint16_t	Rsvd0;
4287			uint16_t	WQId;
4288#endif
4289#ifdef EMLXS_LITTLE_ENDIAN
4290			uint16_t	WQId;
4291			uint16_t	Rsvd0;
4292#endif
4293		} response;
4294
4295	} params;
4296
4297} IOCTL_FCOE_WQ_CREATE;
4298
4299
4300/* IOCTL_FCOE_WQ_CREATE_V1 */
4301typedef	struct
4302{
4303	union
4304	{
4305		struct
4306		{
4307#ifdef EMLXS_BIG_ENDIAN
4308			uint16_t	CQId;
4309			uint16_t	NumPages;
4310
4311			uint32_t	WqeCnt:16;
4312			uint32_t	Rsvd1:4;
4313			uint32_t	WqeSize:4;
4314			uint32_t	PageSize:8;
4315#endif
4316#ifdef EMLXS_LITTLE_ENDIAN
4317			uint16_t	NumPages;
4318			uint16_t	CQId;
4319
4320			uint32_t	PageSize:8;
4321			uint32_t	WqeSize:4;
4322			uint32_t	Rsvd1:4;
4323			uint32_t	WqeCnt:16;
4324#endif
4325			uint32_t	Rsvd:2;
4326			BE_PHYS_ADDR	Pages[4];
4327		} request;
4328
4329		struct
4330		{
4331#ifdef EMLXS_BIG_ENDIAN
4332			uint16_t	Rsvd0;
4333			uint16_t	WQId;
4334#endif
4335#ifdef EMLXS_LITTLE_ENDIAN
4336			uint16_t	WQId;
4337			uint16_t	Rsvd0;
4338#endif
4339		} response;
4340
4341	} params;
4342
4343} IOCTL_FCOE_WQ_CREATE_V1;
4344
4345/* WqeSize */
4346#define	WQE_SIZE_64_BYTES	0x05
4347#define	WQE_SIZE_128_BYTES	0x06
4348
4349/* PageSize */
4350#define	WQ_PAGE_SIZE_4K		0x01
4351#define	WQ_PAGE_SIZE_8K		0x02
4352#define	WQ_PAGE_SIZE_16K	0x04
4353#define	WQ_PAGE_SIZE_32K	0x08
4354#define	WQ_PAGE_SIZE_64K	0x10
4355
4356
4357
4358/* IOCTL_FCOE_CFG_POST_SGL_PAGES */
4359typedef	struct _FCOE_SGL_PAGES
4360{
4361	BE_PHYS_ADDR	sgl_page0;	/* 1st page per XRI */
4362	BE_PHYS_ADDR	sgl_page1;	/* 2nd page per XRI */
4363
4364} FCOE_SGL_PAGES;
4365
4366typedef	struct
4367{
4368	union
4369	{
4370		struct
4371		{
4372#ifdef EMLXS_BIG_ENDIAN
4373			uint16_t	xri_count;
4374			uint16_t	xri_start;
4375#endif
4376#ifdef EMLXS_LITTLE_ENDIAN
4377			uint16_t	xri_start;
4378			uint16_t	xri_count;
4379#endif
4380			FCOE_SGL_PAGES	pages[1];
4381		} request;
4382
4383		struct
4384		{
4385			uint32_t	rsvd0;
4386		} response;
4387
4388	} params;
4389
4390	uint32_t	rsvd0[2];
4391
4392} IOCTL_FCOE_CFG_POST_SGL_PAGES;
4393
4394
4395/* IOCTL_FCOE_POST_HDR_TEMPLATES */
4396typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES
4397{
4398	union
4399	{
4400		struct
4401		{
4402#ifdef EMLXS_BIG_ENDIAN
4403			uint16_t	num_pages;
4404			uint16_t	rpi_offset;
4405#endif
4406#ifdef EMLXS_LITTLE_ENDIAN
4407			uint16_t	rpi_offset;
4408			uint16_t	num_pages;
4409#endif
4410			BE_PHYS_ADDR	pages[32];
4411
4412		}request;
4413
4414	}params;
4415
4416} IOCTL_FCOE_POST_HDR_TEMPLATES;
4417
4418
4419
4420#define	EMLXS_IOCTL_DCBX_MODE_CEE	0	/* Mapped to FIP mode */
4421#define	EMLXS_IOCTL_DCBX_MODE_CIN	1	/* Mapped to nonFIP mode */
4422
4423/* IOCTL_DCBX_GET_DCBX_MODE */
4424typedef struct _IOCTL_DCBX_GET_DCBX_MODE
4425{
4426	union
4427	{
4428		struct
4429		{
4430#ifdef EMLXS_BIG_ENDIAN
4431			uint8_t		rsvd0[3];
4432			uint8_t		port_num;
4433#endif
4434#ifdef EMLXS_LITTLE_ENDIAN
4435			uint8_t		port_num;
4436			uint8_t		rsvd0[3];
4437#endif
4438		} request;
4439
4440		struct
4441		{
4442#ifdef EMLXS_BIG_ENDIAN
4443			uint8_t		rsvd1[3];
4444			uint8_t		dcbx_mode;
4445#endif
4446#ifdef EMLXS_LITTLE_ENDIAN
4447			uint8_t		dcbx_mode;
4448			uint8_t		rsvd1[3];
4449#endif
4450		} response;
4451
4452	} params;
4453
4454} IOCTL_DCBX_GET_DCBX_MODE;
4455
4456
4457/* IOCTL_DCBX_SET_DCBX_MODE */
4458typedef struct _IOCTL_DCBX_SET_DCBX_MODE
4459{
4460	union
4461	{
4462		struct
4463		{
4464#ifdef EMLXS_BIG_ENDIAN
4465			uint8_t		rsvd0[2];
4466			uint8_t		dcbx_mode;
4467			uint8_t		port_num;
4468#endif
4469#ifdef EMLXS_LITTLE_ENDIAN
4470			uint8_t		port_num;
4471			uint8_t		dcbx_mode;
4472			uint8_t		rsvd0[2];
4473#endif
4474		} request;
4475
4476		struct
4477		{
4478			uint32_t	rsvd1;
4479		} response;
4480
4481	} params;
4482
4483} IOCTL_DCBX_SET_DCBX_MODE;
4484
4485
4486/* IOCTL_COMMON_GET_CNTL_ATTRIB */
4487typedef	struct
4488{
4489	char		flashrom_version_string[32];
4490	char		manufacturer_name[32];
4491	char		rsvd0[28];
4492	uint32_t	default_extended_timeout;
4493	char		controller_model_number[32];
4494	char		controller_description[64];
4495	char		controller_serial_number[32];
4496	char		ip_version_string[32];
4497	char		firmware_version_string[32];
4498	char		bios_version_string[32];
4499	char		redboot_version_string[32];
4500	char		driver_version_string[32];
4501	char		fw_on_flash_version_string[32];
4502	uint32_t	functionalities_supported;
4503	uint16_t	max_cdblength;
4504	uint8_t		asic_revision;
4505	uint8_t		generational_guid[16];
4506	uint8_t		hba_port_count;
4507	uint16_t	default_link_down_timeout;
4508	uint8_t		iscsi_ver_min_max;
4509	uint8_t		multifunction_device;
4510	uint8_t		cache_valid;
4511	uint8_t		hba_status;
4512	uint8_t		max_domains_supported;
4513	uint8_t		phy_port;
4514	uint32_t	firmware_post_status;
4515	uint32_t	hba_mtu[2];
4516
4517} MGMT_HBA_ATTRIB;
4518
4519typedef	struct
4520{
4521	MGMT_HBA_ATTRIB		hba_attribs;
4522	uint16_t		pci_vendor_id;
4523	uint16_t		pci_device_id;
4524	uint16_t		pci_sub_vendor_id;
4525	uint16_t		pci_sub_system_id;
4526	uint8_t			pci_bus_number;
4527	uint8_t			pci_device_number;
4528	uint8_t			pci_function_number;
4529	uint8_t			interface_type;
4530	uint64_t		unique_identifier;
4531
4532} MGMT_CONTROLLER_ATTRIB;
4533
4534typedef	struct
4535{
4536	union
4537	{
4538		struct
4539		{
4540			uint32_t rsvd0;
4541		} request;
4542
4543		struct
4544		{
4545			MGMT_CONTROLLER_ATTRIB cntl_attributes_info;
4546		} response;
4547
4548	} params;
4549
4550} IOCTL_COMMON_GET_CNTL_ATTRIB;
4551
4552
4553typedef	union
4554{
4555	IOCTL_COMMON_NOP		NOPVar;
4556	IOCTL_FCOE_WQ_CREATE		WQCreateVar;
4557	IOCTL_FCOE_WQ_CREATE_V1		WQCreateVar1;
4558	IOCTL_FCOE_RQ_CREATE		RQCreateVar;
4559	IOCTL_FCOE_RQ_CREATE_V1		RQCreateVar1;
4560	IOCTL_COMMON_EQ_CREATE		EQCreateVar;
4561	IOCTL_COMMON_CQ_CREATE		CQCreateVar;
4562	IOCTL_COMMON_CQ_CREATE_V2	CQCreateVar2;
4563	IOCTL_COMMON_MQ_CREATE		MQCreateVar;
4564	IOCTL_COMMON_MQ_CREATE_EXT	MQCreateExtVar;
4565	IOCTL_COMMON_MQ_CREATE_EXT_V1	MQCreateExtVar1;
4566	IOCTL_FCOE_CFG_POST_SGL_PAGES	PostSGLVar;
4567	IOCTL_COMMON_GET_CNTL_ATTRIB	GetCntlAttributesVar;
4568	IOCTL_FCOE_READ_FCF_TABLE	ReadFCFTableVar;
4569	IOCTL_FCOE_ADD_FCF_TABLE	AddFCFTableVar;
4570	IOCTL_FCOE_REDISCOVER_FCF_TABLE	RediscoverFCFTableVar;
4571	IOCTL_COMMON_FLASHROM		FlashRomVar;
4572	IOCTL_COMMON_MANAGE_FAT		FATVar;
4573	IOCTL_DCBX_GET_DCBX_MODE	GetDCBX;
4574	IOCTL_DCBX_SET_DCBX_MODE	SetDCBX;
4575	IOCTL_COMMON_SLI4_PARAMS	Sli4ParamVar;
4576	IOCTL_COMMON_EXTENTS		ExtentsVar;
4577	IOCTL_COMMON_GET_PHY_DETAILS	PHYDetailsVar;
4578	IOCTL_COMMON_GET_PORT_NAME	PortNameVar;
4579	IOCTL_COMMON_GET_PORT_NAME_V1	PortNameVar1;
4580	IOCTL_COMMON_WRITE_OBJECT	WriteObjVar;
4581	IOCTL_COMMON_BOOT_CFG		BootCfgVar;
4582
4583} IOCTL_VARIANTS;
4584
4585/* Structure for MB Command SLI_CONFIG(0x9b) */
4586/* Good for SLI4 only */
4587
4588typedef struct
4589{
4590	be_req_hdr_t	be;
4591	BE_PHYS_ADDR	payload;
4592} SLI_CONFIG_VAR;
4593
4594#define	IOCTL_HEADER_SZ	(4 * sizeof (uint32_t))
4595
4596
4597typedef union
4598{
4599	uint32_t		varWords[63];
4600	READ_NV_VAR		varRDnvp;	/* cmd = x02 (READ_NVPARMS) */
4601	INIT_LINK_VAR		varInitLnk;	/* cmd = x05 (INIT_LINK) */
4602	CONFIG_LINK		varCfgLnk;	/* cmd = x07 (CONFIG_LINK) */
4603	READ_REV4_VAR		varRdRev4;	/* cmd = x11 (READ_REV) */
4604	READ_LNK_VAR		varRdLnk;	/* cmd = x12 (READ_LNK_STAT) */
4605	DUMP4_VAR		varDmp4;	/* cmd = x17 (DUMP) */
4606	UPDATE_CFG_VAR		varUpdateCfg;	/* cmd = x1b (update Cfg) */
4607	BIU_DIAG_VAR		varBIUdiag;	/* cmd = x84 (RUN_BIU_DIAG64) */
4608	READ_SPARM_VAR		varRdSparm;	/* cmd = x8D (READ_SPARM64) */
4609	REG_FCFI_VAR		varRegFCFI;	/* cmd = xA0 (REG_FCFI) */
4610	UNREG_FCFI_VAR		varUnRegFCFI;	/* cmd = xA2 (UNREG_FCFI) */
4611	READ_LA_VAR		varReadLA;	/* cmd = x95 (READ_LA64) */
4612	READ_CONFIG4_VAR	varRdConfig4;	/* cmd = x0B (READ_CONFIG) */
4613	RESUME_RPI_VAR		varResumeRPI;	/* cmd = x9E (RESUME_RPI) */
4614	REG_LOGIN_VAR		varRegLogin;	/* cmd = x93 (REG_RPI) */
4615	UNREG_LOGIN_VAR		varUnregLogin;	/* cmd = x14 (UNREG_RPI) */
4616	REG_VPI_VAR		varRegVPI4;	/* cmd = x96 (REG_VPI) */
4617	UNREG_VPI_VAR4		varUnRegVPI4;	/* cmd = x97 (UNREG_VPI) */
4618	REG_VFI_VAR		varRegVFI4;	/* cmd = x9F (REG_VFI) */
4619	UNREG_VFI_VAR		varUnRegVFI4;	/* cmd = xA1 (UNREG_VFI) */
4620	REQUEST_FEATURES_VAR	varReqFeatures;	/* cmd = x9D (REQ_FEATURES) */
4621	SLI_CONFIG_VAR		varSLIConfig;	/* cmd = x9B (SLI_CONFIG) */
4622	INIT_VPI_VAR		varInitVPI4;	/* cmd = xA3 (INIT_VPI) */
4623	INIT_VFI_VAR		varInitVFI4;	/* cmd = xA4 (INIT_VFI) */
4624
4625} MAILVARIANTS4;		/* Used for SLI-4 */
4626
4627#define	MAILBOX_CMD_SLI4_BSIZE	256
4628#define	MAILBOX_CMD_SLI4_WSIZE	64
4629
4630#define	MAILBOX_CMD_MAX_BSIZE	256
4631#define	MAILBOX_CMD_MAX_WSIZE	64
4632
4633
4634typedef volatile struct
4635{
4636#ifdef EMLXS_BIG_ENDIAN
4637	uint16_t	mbxStatus;
4638	uint8_t		mbxCommand;
4639	uint8_t		mbxReserved:6;
4640	uint8_t		mbxHc:1;
4641	uint8_t		mbxOwner:1;	/* Low order bit first word */
4642#endif
4643#ifdef EMLXS_LITTLE_ENDIAN
4644	uint8_t		mbxOwner:1;	/* Low order bit first word */
4645	uint8_t		mbxHc:1;
4646	uint8_t		mbxReserved:6;
4647	uint8_t		mbxCommand;
4648	uint16_t	mbxStatus;
4649#endif
4650	MAILVARIANTS4	un;		/* 252 bytes */
4651} MAILBOX4;				/* Used for SLI-4 */
4652
4653/*
4654 * End Structure Definitions for Mailbox Commands
4655 */
4656
4657
4658typedef struct emlxs_mbq
4659{
4660	volatile uint32_t	mbox[MAILBOX_CMD_MAX_WSIZE];
4661	struct emlxs_mbq	*next;
4662
4663	/* Defferred handling pointers */
4664	void			*nonembed;	/* ptr to data buffer */
4665						/* structure */
4666	void			*bp;		/* ptr to data buffer */
4667						/* structure */
4668	void			*sbp;		/* ptr to emlxs_buf_t */
4669						/* structure */
4670	void			*ubp;		/* ptr to fc_unsol_buf_t */
4671						/* structure */
4672	void			*iocbq;		/* ptr to IOCBQ structure */
4673	void			*context;	/* ptr to mbox context data */
4674	void			*port;		/* Sending port */
4675	uint32_t		flag;
4676
4677#define	MBQ_POOL_ALLOCATED	0x00000001
4678#define	MBQ_PASSTHRU		0x00000002
4679#define	MBQ_EMBEDDED		0x00000004
4680#define	MBQ_BOOTSTRAP		0x00000008
4681#define	MBQ_COMPLETED		0x00010000	/* Used for MBX_SLEEP */
4682#define	MBQ_INIT_MASK		0x0000ffff
4683
4684#ifdef MBOX_EXT_SUPPORT
4685	uint8_t			*extbuf;	/* ptr to mailbox ext buffer */
4686	uint32_t		extsize;	/* size of mailbox ext buffer */
4687#endif /* MBOX_EXT_SUPPORT */
4688	uint32_t		(*mbox_cmpl)();
4689} emlxs_mbq_t;
4690typedef emlxs_mbq_t MAILBOXQ;
4691
4692
4693/* We currently do not support IOCBs in SLI1 mode */
4694typedef struct
4695{
4696	MAILBOX		mbx;
4697#ifdef MBOX_EXT_SUPPORT
4698	uint8_t		mbxExt[MBOX_EXTENSION_SIZE];
4699#endif /* MBOX_EXT_SUPPORT */
4700	uint8_t		pad[(SLI_SLIM1_SIZE -
4701				(sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))];
4702} SLIM1;
4703
4704
4705typedef struct
4706{
4707	MAILBOX		mbx;
4708#ifdef MBOX_EXT_SUPPORT
4709	uint8_t		mbxExt[MBOX_EXTENSION_SIZE];
4710#endif /* MBOX_EXT_SUPPORT */
4711	PCB		pcb;
4712	uint8_t		IOCBs[SLI_IOCB_MAX_SIZE];
4713} SLIM2;
4714
4715
4716/* def for new 2MB Flash (Pegasus ...) */
4717#define	MBX_LOAD_AREA		0x81
4718#define	MBX_LOAD_EXP_ROM	0x9C
4719
4720#define	FILE_TYPE_AWC		0xE1A01001
4721#define	FILE_TYPE_DWC		0xE1A02002
4722#define	FILE_TYPE_BWC		0xE1A03003
4723
4724#define	AREA_ID_MASK		0xFFFFFF0F
4725#define	AREA_ID_AWC		0x00000001
4726#define	AREA_ID_DWC		0x00000002
4727#define	AREA_ID_BWC		0x00000003
4728
4729#define	CMD_START_ERASE		1
4730#define	CMD_CONTINUE_ERASE	2
4731#define	CMD_DOWNLOAD		3
4732#define	CMD_END_DOWNLOAD	4
4733
4734#define	RSP_ERASE_STARTED	1
4735#define	RSP_ERASE_COMPLETE	2
4736#define	RSP_DOWNLOAD_MORE	3
4737#define	RSP_DOWNLOAD_DONE	4
4738
4739#define	EROM_CMD_FIND_IMAGE	8
4740#define	EROM_CMD_CONTINUE_ERASE	9
4741#define	EROM_CMD_COPY		10
4742
4743#define	EROM_RSP_ERASE_STARTED	8
4744#define	EROM_RSP_ERASE_COMPLETE	9
4745#define	EROM_RSP_COPY_MORE	10
4746#define	EROM_RSP_COPY_DONE	11
4747
4748#define	ALLext			1
4749#define	DWCext			2
4750#define	BWCext			3
4751
4752#define	NO_ALL			0
4753#define	ALL_WITHOUT_BWC		1
4754#define	ALL_WITH_BWC		2
4755
4756#define	KERNEL_START_ADDRESS	0x000000
4757#define	DOWNLOAD_START_ADDRESS	0x040000
4758#define	EXP_ROM_START_ADDRESS	0x180000
4759#define	SCRATCH_START_ADDRESS	0x1C0000
4760#define	CONFIG_START_ADDRESS	0x1E0000
4761
4762
4763typedef struct SliAifHdr
4764{
4765	uint32_t	CompressBr;
4766	uint32_t	RelocBr;
4767	uint32_t	ZinitBr;
4768	uint32_t	EntryBr;
4769	uint32_t	Area_ID;
4770	uint32_t	RoSize;
4771	uint32_t	RwSize;
4772	uint32_t	DbgSize;
4773	uint32_t	ZinitSize;
4774	uint32_t	DbgType;
4775	uint32_t	ImageBase;
4776	uint32_t	Area_Size;
4777	uint32_t	AddressMode;
4778	uint32_t	DataBase;
4779	uint32_t	AVersion;
4780	uint32_t	Spare2;
4781	uint32_t	DebugSwi;
4782	uint32_t	ZinitCode[15];
4783} AIF_HDR, *PAIF_HDR;
4784
4785typedef struct ImageHdr
4786{
4787	uint32_t	BlockSize;
4788	PROG_ID		Id;
4789	uint32_t	Flags;
4790	uint32_t	EntryAdr;
4791	uint32_t	InitAdr;
4792	uint32_t	ExitAdr;
4793	uint32_t	ImageBase;
4794	uint32_t	ImageSize;
4795	uint32_t	ZinitSize;
4796	uint32_t	RelocSize;
4797	uint32_t	HdrCks;
4798} IMAGE_HDR, *PIMAGE_HDR;
4799
4800
4801
4802typedef struct
4803{
4804	PROG_ID		prog_id;
4805#ifdef EMLXS_BIG_ENDIAN
4806	uint32_t	pci_cfg_rsvd:27;
4807	uint32_t	use_hdw_def:1;
4808	uint32_t	pci_cfg_sel:3;
4809	uint32_t	pci_cfg_lookup_sel:1;
4810#endif
4811#ifdef EMLXS_LITTLE_ENDIAN
4812	uint32_t	pci_cfg_lookup_sel:1;
4813	uint32_t	pci_cfg_sel:3;
4814	uint32_t	use_hdw_def:1;
4815	uint32_t	pci_cfg_rsvd:27;
4816#endif
4817	union
4818	{
4819		PROG_ID		boot_bios_id;
4820		uint32_t	boot_bios_wd[2];
4821	} u0;
4822	PROG_ID		sli1_prog_id;
4823	PROG_ID		sli2_prog_id;
4824	PROG_ID		sli3_prog_id;
4825	PROG_ID		sli4_prog_id;
4826	union
4827	{
4828		PROG_ID		EROM_prog_id;
4829		uint32_t	EROM_prog_wd[2];
4830	} u1;
4831} WAKE_UP_PARMS, *PWAKE_UP_PARMS;
4832
4833
4834#define	PROG_DESCR_STR_LEN	24
4835#define	MAX_LOAD_ENTRY		32
4836
4837typedef struct
4838{
4839	uint32_t	next;
4840	uint32_t	prev;
4841	uint32_t	start_adr;
4842	uint32_t	len;
4843	union
4844	{
4845		PROG_ID		id;
4846		uint32_t	wd[2];
4847	} un;
4848	uint8_t		prog_descr[PROG_DESCR_STR_LEN];
4849} LOAD_ENTRY;
4850
4851typedef struct
4852{
4853	uint32_t	head;
4854	uint32_t	tail;
4855	uint32_t	entry_cnt;
4856	LOAD_ENTRY	load_entry[MAX_LOAD_ENTRY];
4857} LOAD_LIST;
4858
4859#ifdef	__cplusplus
4860}
4861#endif
4862
4863#endif	/* _EMLXS_MBOX_H */
4864