1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Emulex.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _EMLXS_HW_H
28 #define	_EMLXS_HW_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 #define	MAX_VPORTS			256	/* Max virtual ports per HBA */
35 						/* (includes physical port) */
36 #define	MAX_VPORTS_LIMITED		101
37 
38 #define	FC_MAX_TRANSFER			0x40000	/* Max transfer size per */
39 						/* operation */
40 
41 #define	MAX_RINGS_AVAILABLE		4	/* # rings available */
42 #define	MAX_RINGS			4	/* Max # rings used */
43 
44 #define	PCB_SIZE			128
45 
46 #define	SLIM_IOCB_CMD_R0_ENTRIES	128	/* SLI FCP cmd ring entries  */
47 #define	SLIM_IOCB_RSP_R0_ENTRIES	128	/* SLI FCP rsp ring entries */
48 #define	SLIM_IOCB_CMD_R1_ENTRIES	128	/* SLI IP cmd ring entries   */
49 #define	SLIM_IOCB_RSP_R1_ENTRIES	128	/* SLI IP rsp ring entries  */
50 #define	SLIM_IOCB_CMD_R2_ENTRIES	128	/* SLI ELS cmd ring entries  */
51 #define	SLIM_IOCB_RSP_R2_ENTRIES	128	/* SLI ELS rspe ring entries */
52 #define	SLIM_IOCB_CMD_R3_ENTRIES	128	/* SLI CT cmd ring entries   */
53 #define	SLIM_IOCB_RSP_R3_ENTRIES	128	/* SLI CT rsp ring entries  */
54 
55 /*
56  * Total: 184 Cmd's + 184 Rsp's = 368
57  * Command and response entry counts are not required to be equal
58  */
59 
60 #define	SLIM_IOCB_CMD_ENTRIES		(SLIM_IOCB_CMD_R0_ENTRIES + \
61 					SLIM_IOCB_CMD_R1_ENTRIES + \
62 					SLIM_IOCB_CMD_R2_ENTRIES + \
63 					SLIM_IOCB_CMD_R3_ENTRIES)
64 
65 #define	SLIM_IOCB_RSP_ENTRIES		(SLIM_IOCB_RSP_R0_ENTRIES + \
66 					SLIM_IOCB_RSP_R1_ENTRIES + \
67 					SLIM_IOCB_RSP_R2_ENTRIES + \
68 					SLIM_IOCB_RSP_R3_ENTRIES)
69 
70 #define	SLIM_IOCB_ENTRIES		(SLIM_IOCB_CMD_ENTRIES + \
71 					SLIM_IOCB_RSP_ENTRIES)
72 
73 
74 /* SLI1 Definitions */
75 #define	SLI_SLIM1_SIZE			4096 /* Fixed size memory */
76 
77 
78 /* SLI2 Definitions */
79 #define	SLI2_IOCB_CMD_SIZE		32
80 #define	SLI2_IOCB_RSP_SIZE		32
81 #define	SLI2_IOCB_MAX_SIZE		((SLI2_IOCB_CMD_SIZE * \
82 					SLIM_IOCB_CMD_ENTRIES) + \
83 					(SLI2_IOCB_RSP_SIZE * \
84 					SLIM_IOCB_RSP_ENTRIES))
85 #define	SLI2_SLIM2_SIZE			(MBOX_SIZE + MBOX_EXTENSION_SIZE + \
86 					PCB_SIZE + SLI2_IOCB_MAX_SIZE)
87 
88 
89 /* SLI3 Definitions */
90 #define	SLI3_MAX_BDE			7
91 #define	SLI3_IOCB_CMD_SIZE		128
92 #define	SLI3_IOCB_RSP_SIZE		64
93 #define	SLI3_IOCB_MAX_SIZE		((SLI3_IOCB_CMD_SIZE * \
94 					SLIM_IOCB_CMD_ENTRIES) + \
95 					(SLI3_IOCB_RSP_SIZE * \
96 					SLIM_IOCB_RSP_ENTRIES))
97 #define	SLI3_SLIM2_SIZE			(MBOX_SIZE + MBOX_EXTENSION_SIZE + \
98 					PCB_SIZE + SLI3_IOCB_MAX_SIZE)
99 
100 #define	SLI_SLIM2_SIZE			SLI3_SLIM2_SIZE
101 #define	SLI_IOCB_MAX_SIZE		SLI3_IOCB_MAX_SIZE
102 
103 
104 /* These two are defined to indicate FCP cmd or non FCP cmd */
105 #define	FC_FCP_CMD		0
106 #define	FC_FCT_CMD		0
107 #define	FC_IP_CMD		1
108 #define	FC_ELS_CMD		2
109 #define	FC_CT_CMD		3
110 
111 #define	FC_NFCP_CMD		1	/* could be a bit mask */
112 
113 #define	FC_MAXRETRY		3	/* max retries for ELS commands */
114 #define	FC_FCP_RING		0	/* use ring 0 for FCP initiator cmds */
115 #define	FC_FCT_RING		0	/* use ring 0 for FCP target cmds */
116 
117 #define	FC_IP_RING		1	/* use ring 1 for IP commands */
118 #define	FC_ELS_RING		2	/* use ring 2 for ELS commands */
119 #define	FC_CT_RING		3	/* use ring 3 for CT commands */
120 
121 #define	FF_DEF_EDTOV		2000	/* Default E_D_TOV (2000ms) */
122 #define	FF_DEF_ALTOV		15	/* Default AL_TIME (15ms) */
123 #define	FF_DEF_RATOV		2	/* Default RA_TOV (2s) */
124 #define	FF_DEF_ARBTOV		1900	/* Default ARB_TOV (1900ms) */
125 #define	MAX_MSG_DATA		28	/* max msg data in CMD_ADAPTER_MSG */
126 					/* iocb */
127 #define	FF_REG_AREA_SIZE	256	/* size, in bytes, of i/o register */
128 					/* area */
129 
130 /*
131  * Miscellaneous stuff....
132  */
133 /* HBA Mgmt */
134 #define	FDMI_DID		((uint32_t)0xfffffa)
135 #define	NAMESERVER_DID		((uint32_t)0xfffffc)
136 #define	SCR_DID			((uint32_t)0xfffffd)
137 #define	FABRIC_DID		((uint32_t)0xfffffe)
138 #define	BCAST_DID		((uint32_t)0xffffff)
139 #define	MASK_DID		((uint32_t)0xffffff)
140 #define	CT_DID_MASK		((uint32_t)0xffff00)
141 #define	FABRIC_DID_MASK		((uint32_t)0xfff000)
142 #define	WELL_KNOWN_DID_MASK	((uint32_t)0xfffff0)
143 
144 #define	EMLXS_MENLO_DID		((uint32_t)0x00fc0e)
145 
146 #define	OWN_CHIP	1	/* IOCB / Mailbox is owned by FireFly */
147 #define	OWN_HOST	0	/* IOCB / Mailbox is owned by Host */
148 #define	END_OF_CHAIN	0
149 
150 
151 /* defines for type field in fc header */
152 #define	FC_ELS_DATA		0x01
153 #define	FC_LLC_SNAP		0x05
154 #define	FC_FCP_DATA		0x08
155 #define	FC_CT_TYPE		0x20
156 #define	EMLXS_MENLO_TYPE	0xFE
157 
158 /* defines for rctl field in fc header */
159 #define	FC_DEV_DATA	0x0
160 #define	FC_UNSOL_CTL	0x2
161 #define	FC_SOL_CTL	0x3
162 #define	FC_UNSOL_DATA	0x4
163 #define	FC_FCP_CMND	0x6
164 #define	FC_ELS_REQ	0x22
165 #define	FC_ELS_RSP	0x23
166 #define	FC_NET_HDR	0x20	/* network headers for Dfctl field */
167 
168 /*
169  * Common Transport structures and definitions
170  *
171  */
172 #define	EMLXS_COMMAND	0
173 #define	EMLXS_RESPONSE	1
174 
175 typedef union CtRevisionId
176 {
177 	/* Structure is in Big Endian format */
178 	struct
179 	{
180 		uint32_t	Revision:8;
181 		uint32_t	InId:24;
182 	} bits;
183 	uint32_t	word;
184 } CtRevisionId_t;
185 
186 typedef union CtCommandResponse
187 {
188 	/* Structure is in Big Endian format */
189 	struct
190 	{
191 		uint32_t	CmdRsp:16;
192 		uint32_t	Size:16;
193 	} bits;
194 	uint32_t	word;
195 } CtCommandResponse_t;
196 
197 typedef struct SliCtRequest
198 {
199 	/* Structure is in Big Endian format */
200 	CtRevisionId_t		RevisionId;
201 	uint8_t			FsType;
202 	uint8_t			FsSubType;
203 	uint8_t			Options;
204 	uint8_t			Rsrvd1;
205 	CtCommandResponse_t	CommandResponse;
206 	uint8_t			Rsrvd2;
207 	uint8_t			ReasonCode;
208 	uint8_t			Explanation;
209 	uint8_t			VendorUnique;
210 
211 	union
212 	{
213 		uint32_t	data;
214 		uint32_t	PortID;
215 
216 		struct gid
217 		{
218 			uint8_t	PortType;	/* for GID_PT requests */
219 			uint8_t	DomainScope;
220 			uint8_t	AreaScope;
221 			uint8_t	Fc4Type;	/* for GID_FT requests */
222 		} gid;
223 		struct rft
224 		{
225 			uint32_t	PortId;	/* For RFT_ID requests */
226 #ifdef EMLXS_BIG_ENDIAN
227 			uint32_t	rsvd0:16;
228 			uint32_t	rsvd1:7;
229 			uint32_t	fcpReg:1;	/* Type 8 */
230 			uint32_t	rsvd2:2;
231 			uint32_t	ipReg:1;	/* Type 5 */
232 			uint32_t	rsvd3:5;
233 #endif
234 #ifdef EMLXS_LITTLE_ENDIAN
235 			uint32_t	rsvd0:16;
236 			uint32_t	fcpReg:1;	/* Type 8 */
237 			uint32_t	rsvd1:7;
238 			uint32_t	rsvd3:5;
239 			uint32_t	ipReg:1;	/* Type 5 */
240 			uint32_t	rsvd2:2;
241 #endif
242 			uint32_t	rsvd[7];
243 		} rft;
244 
245 		struct rsnn
246 		{
247 			uint8_t		wwnn[8];
248 			uint8_t		snn_len;
249 			char		snn[256];
250 		} rsnn;
251 
252 		struct rspn
253 		{
254 			uint32_t	PortId;
255 			uint8_t		spn_len;
256 			char		spn[256];
257 		} rspn;
258 	} un;
259 } SliCtRequest_t;
260 typedef SliCtRequest_t SLI_CT_REQUEST;
261 
262 #define	SLI_CT_REVISION	1
263 
264 
265 /*
266  * FsType Definitions
267  */
268 
269 #define	SLI_CT_MANAGEMENT_SERVICE		0xFA
270 #define	SLI_CT_TIME_SERVICE			0xFB
271 #define	SLI_CT_DIRECTORY_SERVICE		0xFC
272 #define	SLI_CT_FABRIC_CONTROLLER_SERVICE	0xFD
273 
274 /*
275  * Directory Service Subtypes
276  */
277 
278 #define	SLI_CT_DIRECTORY_NAME_SERVER	0x02
279 
280 /*
281  * Response Codes
282  */
283 
284 #define	SLI_CT_RESPONSE_FS_RJT	0x8001
285 #define	SLI_CT_RESPONSE_FS_ACC	0x8002
286 
287 /*
288  * Reason Codes
289  */
290 
291 #define	SLI_CT_NO_ADDITIONAL_EXPL		0x0
292 #define	SLI_CT_INVALID_COMMAND			0x01
293 #define	SLI_CT_INVALID_VERSION			0x02
294 #define	SLI_CT_LOGICAL_ERROR			0x03
295 #define	SLI_CT_INVALID_IU_SIZE			0x04
296 #define	SLI_CT_LOGICAL_BUSY			0x05
297 #define	SLI_CT_PROTOCOL_ERROR			0x07
298 #define	SLI_CT_UNABLE_TO_PERFORM_REQ		0x09
299 #define	SLI_CT_REQ_NOT_SUPPORTED		0x0b
300 #define	SLI_CT_HBA_INFO_NOT_REGISTERED		0x10
301 #define	SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE	0x11
302 #define	SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN	0x12
303 #define	SLI_CT_HBA_ATTR_NOT_PRESENT		0x13
304 #define	SLI_CT_PORT_INFO_NOT_REGISTERED		0x20
305 #define	SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE	0x21
306 #define	SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN	0x22
307 #define	SLI_CT_VENDOR_UNIQUE			0xff
308 
309 /*
310  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
311  */
312 
313 #define	SLI_CT_NO_PORT_ID		0x01
314 #define	SLI_CT_NO_PORT_NAME		0x02
315 #define	SLI_CT_NO_NODE_NAME		0x03
316 #define	SLI_CT_NO_CLASS_OF_SERVICE	0x04
317 #define	SLI_CT_NO_IP_ADDRESS		0x05
318 #define	SLI_CT_NO_IPA			0x06
319 #define	SLI_CT_NO_FC4_TYPES		0x07
320 #define	SLI_CT_NO_SYMBOLIC_PORT_NAME	0x08
321 #define	SLI_CT_NO_SYMBOLIC_NODE_NAME	0x09
322 #define	SLI_CT_NO_PORT_TYPE		0x0A
323 #define	SLI_CT_ACCESS_DENIED		0x10
324 #define	SLI_CT_INVALID_PORT_ID		0x11
325 #define	SLI_CT_DATABASE_EMPTY		0x12
326 
327 #ifdef EMLXS_BIG_ENDIAN
328 #define	CT_CMD_MASK	0xffff0000
329 #endif
330 
331 #ifdef EMLXS_LITTLE_ENDIAN
332 #define	CT_CMD_MASK	0xffff
333 #endif
334 
335 /*
336  * Management Server Interface Command Codes
337  */
338 
339 #define	MS_GTIN		0x0100
340 #define	MS_GIEL		0x0101
341 #define	MS_GIET		0x0111
342 #define	MS_GDID		0x0112
343 #define	MS_GMID		0x0113
344 #define	MS_GFN		0x0114
345 #define	MS_GIELN	0x0115
346 #define	MS_GMAL		0x0116
347 #define	MS_GIEIL	0x0117
348 #define	MS_GPL		0x0118
349 #define	MS_GPT		0x0121
350 #define	MS_GPPN		0x0122
351 #define	MS_GAPNL	0x0124
352 #define	MS_GPS		0x0126
353 #define	MS_GPSC		0x0127
354 #define	MS_GATIN	0x0128
355 #define	MS_GSES		0x0130
356 #define	MS_GPLNL	0x0191
357 #define	MS_GPLT		0x0192
358 #define	MS_GPLML	0x0193
359 #define	MS_GPAB		0x0197
360 #define	MS_GNPL		0x01A1
361 #define	MS_GPNL		0x01A2
362 #define	MS_GPFCP	0x01A4
363 #define	MS_GPLI		0x01A5
364 #define	MS_GNID		0x01B1
365 #define	MS_RIELN	0x0215
366 #define	MS_RPL		0x0280
367 #define	MS_RPLN		0x0291
368 #define	MS_RPLT		0x0292
369 #define	MS_RPLM		0x0293
370 #define	MS_RPAB		0x0298
371 #define	MS_RPFCP	0x029A
372 #define	MS_RPLI		0x029B
373 #define	MS_DPL		0x0380
374 #define	MS_DPLN		0x0391
375 #define	MS_DPLM		0x0392
376 #define	MS_DPLML	0x0393
377 #define	MS_DPLI		0x0394
378 #define	MS_DPAB		0x0395
379 #define	MS_DPALL	0x039F
380 
381 /*
382  * Name Server Command Codes
383  */
384 #define	SLI_CTNS_GA_NXT		0x0100
385 #define	SLI_CTNS_GPN_ID		0x0112
386 #define	SLI_CTNS_GNN_ID		0x0113
387 #define	SLI_CTNS_GCS_ID		0x0114
388 #define	SLI_CTNS_GFT_ID		0x0117
389 #define	SLI_CTNS_GSPN_ID	0x0118
390 #define	SLI_CTNS_GPT_ID		0x011A
391 #define	SLI_CTNS_GID_PN		0x0121
392 #define	SLI_CTNS_GID_NN		0x0131
393 #define	SLI_CTNS_GIP_NN		0x0135
394 #define	SLI_CTNS_GIPA_NN	0x0136
395 #define	SLI_CTNS_GSNN_NN	0x0139
396 #define	SLI_CTNS_GNN_IP		0x0153
397 #define	SLI_CTNS_GIPA_IP	0x0156
398 #define	SLI_CTNS_GID_FT		0x0171
399 #define	SLI_CTNS_GID_PT		0x01A1
400 #define	SLI_CTNS_RPN_ID		0x0212
401 #define	SLI_CTNS_RNN_ID		0x0213
402 #define	SLI_CTNS_RCS_ID		0x0214
403 #define	SLI_CTNS_RFT_ID		0x0217
404 #define	SLI_CTNS_RSPN_ID	0x0218
405 #define	SLI_CTNS_RPT_ID		0x021A
406 #define	SLI_CTNS_RIP_NN		0x0235
407 #define	SLI_CTNS_RIPA_NN	0x0236
408 #define	SLI_CTNS_RSNN_NN	0x0239
409 #define	SLI_CTNS_DA_ID		0x0300
410 
411 #define	SLI_CT_LOOPBACK		0xFCFC
412 
413 
414 /*
415  * Port Types
416  */
417 
418 #define	SLI_CTPT_N_PORT		0x01
419 #define	SLI_CTPT_NL_PORT	0x02
420 #define	SLI_CTPT_FNL_PORT	0x03
421 #define	SLI_CTPT_IP		0x04
422 #define	SLI_CTPT_FCP		0x08
423 #define	SLI_CTPT_NX_PORT	0x7F
424 #define	SLI_CTPT_F_PORT		0x81
425 #define	SLI_CTPT_FL_PORT	0x82
426 #define	SLI_CTPT_E_PORT		0x84
427 
428 #define	SLI_CT_LAST_ENTRY	0x80000000
429 
430 /* ===================================================================== */
431 
432 /*
433  * Start FireFly Register definitions
434  */
435 
436 /* PCI register offsets */
437 #define	MEM_ADDR_OFFSET	0x10	/* SLIM base memory address */
438 #define	MEMH_OFFSET	0x14	/* SLIM base memory high address */
439 #define	REG_ADDR_OFFSET	0x18	/* REGISTER base memory address */
440 #define	REGH_OFFSET	0x1c	/* REGISTER base memory high address */
441 #define	IO_ADDR_OFFSET	0x20	/* BIU I/O registers */
442 #define	REGIOH_OFFSET	0x24	/* REGISTER base io high address */
443 
444 #define	CMD_REG_OFFSET	0x4	/* PCI command configuration */
445 
446 /* General PCI Register Definitions */
447 /* Refer To The PCI Specification For Detailed Explanations */
448 
449 /* Register Offsets in little endian format */
450 #define	PCI_VENDOR_ID_REGISTER		0x00	/* PCI Vendor ID Reg */
451 #define	PCI_DEVICE_ID_REGISTER		0x02	/* PCI Device ID Reg */
452 #define	PCI_CONFIG_ID_REGISTER		0x00	/* PCI Configuration ID Reg */
453 #define	PCI_COMMAND_REGISTER		0x04	/* PCI Command Reg */
454 #define	PCI_STATUS_REGISTER		0x06	/* PCI Status Reg */
455 #define	PCI_REV_ID_REGISTER		0x08	/* PCI Revision ID Reg */
456 #define	PCI_CLASS_CODE_REGISTER		0x09	/* PCI Class Code Reg */
457 #define	PCI_CACHE_LINE_REGISTER		0x0C	/* PCI Cache Line Reg */
458 #define	PCI_LATENCY_TMR_REGISTER	0x0D	/* PCI Latency Timer Reg */
459 #define	PCI_HEADER_TYPE_REGISTER	0x0E	/* PCI Header Type Reg */
460 #define	PCI_BIST_REGISTER		0x0F	/* PCI Built-In SelfTest Reg */
461 #define	PCI_BAR_0_REGISTER		0x10	/* PCI Base Address Reg 0 */
462 #define	PCI_BAR_1_REGISTER		0x14	/* PCI Base Address Reg 1 */
463 #define	PCI_BAR_2_REGISTER		0x18	/* PCI Base Address Reg 2 */
464 #define	PCI_BAR_3_REGISTER		0x1C	/* PCI Base Address Reg 3 */
465 #define	PCI_BAR_4_REGISTER		0x20	/* PCI Base Address Reg 4 */
466 #define	PCI_BAR_5_REGISTER		0x24	/* PCI Base Address Reg 5 */
467 #define	PCI_SSID_REGISTER		0x2C
468 #define	PCI_SSVID_REGISTER		0x2C
469 #define	PCI_SSDID_REGISTER		0x2E
470 #define	PCI_EXPANSION_ROM		0x30	/* PCI Expansion ROM Base Reg */
471 #define	PCI_CAP_POINTER			0x34
472 #define	PCI_INTR_LINE_REGISTER		0x3C	/* PCI Interrupt Line Reg */
473 #define	PCI_INTR_PIN_REGISTER		0x3D	/* PCI Interrupt Pin Reg */
474 #define	PCI_MIN_GNT_REGISTER		0x3E	/* PCI Min-Gnt Reg */
475 #define	PCI_MAX_LAT_REGISTER		0x3F	/* PCI Max_Lat Reg */
476 #define	PCI_NODE_ADDR_REGISTER		0x40	/* PCI Node Address Reg */
477 
478 #define	PCI_PM_CONTROL_REGISTER		0x50	/* PCI Power Mgmt Control Reg */
479 
480 /* PCIe adapters only */
481 #define	PCIe_MSI_CONTROL_REG0	0x60	/* MSI Control */
482 #define	PCIe_MSI_CONTROL_REG1	0x62	/* MSI Control */
483 
484 /* Power management command states */
485 #define	PCI_PM_D0_STATE		0x00	/* Power up state */
486 #define	PCI_PM_D3_STATE		0x03	/* Power down state */
487 
488 
489 /* PCI access methods */
490 #define	P_CONF_T1	1
491 #define	P_CONF_T2	2
492 
493 /* max number of pci buses */
494 #define	MAX_PCI_BUSES	0xFF
495 
496 /* number of PCI config bytes to access */
497 #define	PCI_BYTE	1
498 #define	PCI_WORD	2
499 #define	PCI_DWORD	4
500 
501 /* PCI related constants */
502 #define	CMD_IO_ENBL	0x0001
503 #define	CMD_MEM_ENBL	0x0002
504 #define	CMD_BUS_MASTER	0x0004
505 #define	CMD_MWI		0x0010
506 #define	CMD_PARITY_CHK	0x0040
507 #define	CMD_SERR_ENBL	0x0100
508 
509 #define	CMD_CFG_VALUE	0x156	/* mem enable, master, MWI, SERR, PERR */
510 
511 /* PCI addresses */
512 #define	PCI_SPACE_ENABLE		0x0CF8
513 #define	CF1_CONFIG_ADDR_REGISTER	0x0CF8
514 #define	CF1_CONFIG_DATA_REGISTER	0x0CFC
515 #define	CF2_FORWARD_REGISTER		0x0CFA
516 #define	CF2_BASE_ADDRESS		0xC000
517 
518 
519 #define	DEFAULT_PCI_LATENCY_CLOCKS	0xf8	/* 0xF8 is a special value */
520 						/* for FF11.1N6 firmware. */
521 						/* Use 0x80 for pre-FF11.1N6 */
522 						/* &N7, etc */
523 #define	PCI_LATENCY_VALUE		0xf8
524 
525 
526 
527 /* ==== Register Bit Definitions ==== */
528 
529 /* Used by SBUS adapter */
530 /* SBUS Control Register */
531 #define	SBUS_CTRL_REG_OFFSET	0	/* Word offset from reg base addr */
532 
533 #define	SBUS_CTRL_SBRST 	0x00000001	/* Bit  0 */
534 #define	SBUS_CTRL_BKOFF 	0x00000002	/* Bit  1 */
535 #define	SBUS_CTRL_ENP 		0x00000004	/* Bit  2 */
536 #define	SBUS_CTRL_EN64		0x00000008	/* Bit  3 */
537 #define	SBUS_CTRL_SIR_1 	0x00000010	/* Bit [6:4] IRL 1, */
538 						/* lowset priority */
539 #define	SBUS_CTRL_SIR_2 	0x00000020
540 #define	SBUS_CTRL_SIR_3 	0x00000030
541 #define	SBUS_CTRL_SIR_4 	0x00000040
542 #define	SBUS_CTRL_SIR_5 	0x00000050
543 #define	SBUS_CTRL_SIR_6 	0x00000060
544 #define	SBUS_CTRL_SIR_7 	0x00000070	/* IRL 7, highest priority */
545 
546 /* SBUS Status Register */
547 #define	SBUS_STAT_REG_OFFSET	1	/* Word offset from reg base addr */
548 #define	SBUS_STAT_IP		0x00000001	/* Bit  0 */
549 #define	SBUS_STAT_LERR		0x00000002	/* Bit  1 */
550 #define	SBUS_STAT_SBPE		0x00000004	/* Bit  2 */
551 #define	SBUS_STAT_TE		0x00000008	/* Bit  3 */
552 #define	SBUS_STAT_WPE		0x00000010	/* Bit  4 */
553 #define	SBUS_STAT_PERR		0x00000020	/* Bit  5 */
554 #define	SBUS_STAT_SERR		0x00000040	/* Bit  6 */
555 #define	SBUS_STAT_PTA		0x00000080	/* Bit  7 */
556 
557 /* SBUS Update Register */
558 #define	SBUS_UPDATE_REG_OFFSET	2	/* Word offfset from reg base addr */
559 
560 #define	SBUS_UPDATE_DATA	0x00000001	/* Bit  0 */
561 #define	SBUS_UPDATE_SPCLK	0x00000002	/* Bit  1 */
562 #define	SBUS_UPDATE_SPCE	0x00000004	/* Bit  2 */
563 #define	SBUS_UPDATE_SPRST	0x00000008	/* Bit  3 */
564 #define	SBUS_UPDATE_SPWE	0x00000010	/* Bit  4 */
565 #define	SBUS_UPDATE_LDFPGA	0x00000080	/* Bit  7 */
566 
567 /* Host Attention Register */
568 
569 #define	HA_REG_OFFSET  0	/* Word offset from register base address */
570 
571 #define	HA_R0RE_REQ	0x00000001	/* Bit  0 */
572 #define	HA_R0CE_RSP	0x00000002	/* Bit  1 */
573 #define	HA_R0ATT	0x00000008	/* Bit  3 */
574 #define	HA_R1RE_REQ	0x00000010	/* Bit  4 */
575 #define	HA_R1CE_RSP	0x00000020	/* Bit  5 */
576 #define	HA_R1ATT	0x00000080	/* Bit  7 */
577 #define	HA_R2RE_REQ	0x00000100	/* Bit  8 */
578 #define	HA_R2CE_RSP	0x00000200	/* Bit  9 */
579 #define	HA_R2ATT	0x00000800	/* Bit 11 */
580 #define	HA_R3RE_REQ	0x00001000	/* Bit 12 */
581 #define	HA_R3CE_RSP	0x00002000	/* Bit 13 */
582 #define	HA_R3ATT	0x00008000	/* Bit 15 */
583 #define	HA_LATT		0x20000000	/* Bit 29 */
584 #define	HA_MBATT	0x40000000	/* Bit 30 */
585 #define	HA_ERATT	0x80000000	/* Bit 31 */
586 
587 
588 #ifdef MSI_SUPPORT
589 
590 
591 /* Host attention interrupt map */
592 #define	EMLXS_MSI_MAP8	{0, HA_R0ATT, HA_R1ATT, HA_R2ATT, \
593 	HA_R3ATT, HA_LATT, HA_MBATT, HA_ERATT}
594 #define	EMLXS_MSI_MAP4	{0, HA_R0ATT, HA_R1ATT, HA_R2ATT, 0, 0, 0, 0}
595 #define	EMLXS_MSI_MAP2	{0, HA_R0ATT, 0, 0, 0, 0, 0, 0}
596 #define	EMLXS_MSI_MAP1	{0, 0, 0, 0, 0, 0, 0, 0}
597 
598 /* MSI 0 interrupt mask */
599 #define	EMLXS_MSI0_MASK8	0
600 #define	EMLXS_MSI0_MASK4	(HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \
601 				HC_ERINT_ENA)
602 #define	EMLXS_MSI0_MASK2	(HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA| \
603 				HC_MBINT_ENA|HC_LAINT_ENA|HC_ERINT_ENA)
604 #define	EMLXS_MSI0_MASK1	(HC_R0INT_ENA|HC_R1INT_ENA|HC_R2INT_ENA| \
605 				HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \
606 				HC_ERINT_ENA)
607 
608 
609 #define	EMLXS_MSI_MAX_INTRS	8
610 
611 #define	EMLXS_MSI_MODE1		0
612 #define	EMLXS_MSI_MODE2		1
613 #define	EMLXS_MSI_MODE4		2
614 #define	EMLXS_MSI_MODE8		3
615 #define	EMLXS_MSI_MODES		4
616 
617 #endif	/* MSI_SUPPORT */
618 
619 
620 #define	IO_THROTTLE_RESERVE	12
621 
622 
623 
624 
625 /* Chip Attention Register */
626 
627 #define	CA_REG_OFFSET	1	/* Word offset from register base address */
628 
629 #define	CA_R0CE_REQ	0x00000001	/* Bit  0 */
630 #define	CA_R0RE_RSP	0x00000002	/* Bit  1 */
631 #define	CA_R0ATT	0x00000008	/* Bit  3 */
632 #define	CA_R1CE_REQ	0x00000010	/* Bit  4 */
633 #define	CA_R1RE_RSP	0x00000020	/* Bit  5 */
634 #define	CA_R1ATT	0x00000080	/* Bit  7 */
635 #define	CA_R2CE_REQ	0x00000100	/* Bit  8 */
636 #define	CA_R2RE_RSP	0x00000200	/* Bit  9 */
637 #define	CA_R2ATT	0x00000800	/* Bit 11 */
638 #define	CA_R3CE_REQ	0x00001000	/* Bit 12 */
639 #define	CA_R3RE_RSP	0x00002000	/* Bit 13 */
640 #define	CA_R3ATT	0x00008000	/* Bit 15 */
641 #define	CA_MBATT	0x40000000	/* Bit 30 */
642 
643 /* Host Status Register */
644 
645 #define	HS_REG_OFFSET	2	/* Word offset from register base address */
646 
647 #define	HS_OVERTEMP	0x00000100	/* Bit 8 */
648 #define	HS_MBRDY	0x00400000	/* Bit 22 */
649 #define	HS_FFRDY	0x00800000	/* Bit 23 */
650 #define	HS_FFER8	0x01000000	/* Bit 24 */
651 #define	HS_FFER7	0x02000000	/* Bit 25 */
652 #define	HS_FFER6	0x04000000	/* Bit 26 */
653 #define	HS_FFER5	0x08000000	/* Bit 27 */
654 #define	HS_FFER4	0x10000000	/* Bit 28 */
655 #define	HS_FFER3	0x20000000	/* Bit 29 */
656 #define	HS_FFER2	0x40000000	/* Bit 30 */
657 #define	HS_FFER1	0x80000000	/* Bit 31 */
658 #define	HS_FFERM	0xFF000000	/* Mask for error bits 31:24 */
659 
660 /* Host Control Register */
661 
662 #define	HC_REG_OFFSET	3	/* Word offset from register base address */
663 
664 #define	HC_MBINT_ENA	0x00000001	/* Bit  0 */
665 #define	HC_R0INT_ENA	0x00000002	/* Bit  1 */
666 #define	HC_R1INT_ENA	0x00000004	/* Bit  2 */
667 #define	HC_R2INT_ENA	0x00000008	/* Bit  3 */
668 #define	HC_R3INT_ENA	0x00000010	/* Bit  4 */
669 #define	HC_INITHBI	0x02000000	/* Bit 25 */
670 #define	HC_INITMB	0x04000000	/* Bit 26 */
671 #define	HC_INITFF	0x08000000	/* Bit 27 */
672 #define	HC_LAINT_ENA	0x20000000	/* Bit 29 */
673 #define	HC_ERINT_ENA	0x80000000	/* Bit 31 */
674 
675 /* BIU Configuration Register */
676 
677 #define	BC_REG_OFFSET	4	/* Word offset from register base address */
678 
679 #define	BC_BSE		0x00000001	/* Bit 0 */
680 #define	BC_BSE_SWAP	0x01000000	/* Bit 0 - swapped */
681 
682 /*
683  * End FireFly Register definitions
684  */
685 
686 /*
687  * Start SLI 4 section.
688  */
689 
690 /* PCI Config Register offsets */
691 #define	PCICFG_UE_STATUS_LO_OFFSET	0xA0	/* Error Indication - low */
692 #define	PCICFG_UE_STATUS_HI_OFFSET	0xA4	/* Error Indication - high */
693 #define	PCICFG_UE_MASK_LO_OFFSET	0xA8	/* Error mask - low */
694 #define	PCICFG_UE_MASK_HI_OFFSET	0xAC	/* Error mask - high */
695 #define	PCICFG_UE_STATUS_ONLINE1	0xB0	/* Error status1 */
696 #define	PCICFG_UE_STATUS_ONLINE2	0xB4	/* Error status2 */
697 
698 /* BAR1 and BAR2 register offsets */
699 
700 /* BAR1 offsets for principal registers */
701 #define	CSR_ISR0_OFFSET		0x0C18	/* CSR for EQ interrupt indications */
702 #define	CSR_IMR0_OFFSET		0x0C48	/* CSR for EQ interrupt masking */
703 #define	CSR_ISCR0_OFFSET	0x0C78	/* CSR for EQ interrupt clearing */
704 
705 #define	ISR0_EQ0_INDC	0x00000001	/* Indication bit for EQ0 */
706 #define	ISR0_EQ1_INDC	0x00000002	/* Indication bit for EQ1 */
707 #define	ISR0_EQ2_INDC	0x00000004	/* Indication bit for EQ2 */
708 #define	ISR0_EQ3_INDC	0x00000008	/* Indication bit for EQ3 */
709 #define	ISR0_EQ4_INDC	0x00000010	/* Indication bit for EQ4 */
710 #define	ISR0_EQ5_INDC	0x00000020	/* Indication bit for EQ5 */
711 #define	ISR0_EQ6_INDC	0x00000040	/* Indication bit for EQ6 */
712 #define	ISR0_EQ7_INDC	0x00000080	/* Indication bit for EQ7 */
713 
714 /* MPU EP Semaphore register (ARM POST) */
715 #define	CSR_MPU_EP_SEMAPHORE_OFFSET	0x00AC
716 
717 /* POST Stages of interest */
718 #define	ARM_POST_FATAL	0x80000000
719 #define	ARM_POST_READY	0xc000
720 #define	ARM_POST_MASK	0xffff
721 
722 #define	MPU_EP_DL	0x04000000	/* Driverloadedbitmask */
723 #define	MPU_EP_ORI	0x08000000	/* OptionROMinstalledbitmask */
724 #define	MPU_EP_IPC	0x10000000	/* IPaddressconflictmask */
725 #define	MPU_EP_NIP	0x20000000	/* NoIPaddressmask */
726 #define	MPU_EP_BFW	0x40000000	/* BackupFWinusemask */
727 #define	MPU_EP_ERR	0x80000000	/* POSTfatalerrormask */
728 
729 /* BAR2 offsets for principal doorbell registers */
730 
731 #define	PD_RQ_DB_OFFSET	0x00A0	/* Doorbell notify of posted RQEs */
732 
733 #define	PD_WQ_DB_OFFSET	0x0040	/* Doorbell notify of posted WQEs */
734 
735 #define	PD_CQ_DB_OFFSET	0x0120	/* Doorbell notify of processed CQEs or EQEs */
736 
737 #define	PD_MQ_DB_OFFSET	0x0140	/* Doorbell notify of posted MQEs */
738 
739 #define	PD_MB_DB_OFFSET	0x0160	/* Doorbell Bootstrap Mailbox */
740 
741 /* Doorbell definitions */
742 
743 /* Defines for MQ doorbell */
744 #define	MQ_DB_POP_SHIFT 16		/* shift for entries popped */
745 #define	MQ_DB_POP_MASK  0x1FFF0000	/* Mask for number of entries popped */
746 
747 /* Defines for CQ doorbell */
748 #define	CQ_DB_POP_SHIFT 16		/* shift for entries popped */
749 #define	CQ_DB_POP_MASK  0x1FFF0000	/* Mask for number of entries popped */
750 #define	CQ_DB_REARM	0x20000000	/* Bit 29, rearm */
751 
752 /* Defines for EQ doorbell */
753 #define	EQ_DB_CLEAR	0x00000200	/* Bit 9, designates clear EQ ISR */
754 #define	EQ_DB_EVENT	0x00000400	/* Bit 10, designates EQ */
755 #define	EQ_DB_POP_SHIFT 16		/* shift for entries popped */
756 #define	EQ_DB_POP_MASK  0x1FFF0000	/* Mask for number of entries popped */
757 #define	EQ_DB_REARM	0x20000000	/* Bit 29, rearm */
758 
759 /* bootstrap mailbox doorbell defines */
760 #define	BMBX_READY	0x00000001	/* Mask for Port Ready bit */
761 #define	BMBX_ADDR_HI	0x00000002	/* Mask for Addr Hi bit */
762 #define	BMBX_ADDR	0xFFFFFFFA	/* Mask for Addr bits */
763 
764 /* Sizeof bootstrap mailbox */
765 #define	EMLXS_BOOTSTRAP_MB_SIZE	256
766 
767 #define	MQE_SPECIAL_WORD0	0xFF1234FF	/* Initialize bootstrap wd 0 */
768 #define	MQE_SPECIAL_WORD1	0xFF5678FF	/* Initialize bootstrap wd 1 */
769 
770 
771 /* ===================================================================== */
772 
773 /*
774  * Start of FCP specific structures
775  */
776 
777 typedef struct emlxs_fcp_rsp
778 {
779 	uint32_t	rspRsvd1;	/* FC Word 0, byte 0:3 */
780 	uint32_t	rspRsvd2;	/* FC Word 1, byte 0:3 */
781 
782 	uint8_t		rspStatus0;	/* FCP_STATUS byte 0 (reserved) */
783 	uint8_t		rspStatus1;	/* FCP_STATUS byte 1 (reserved) */
784 	uint8_t		rspStatus2;	/* FCP_STATUS byte 2 field validity */
785 #define	RSP_LEN_VALID	0x01	/* bit 0 */
786 #define	SNS_LEN_VALID	0x02	/* bit 1 */
787 #define	RESID_OVER	0x04	/* bit 2 */
788 #define	RESID_UNDER	0x08	/* bit 3 */
789 
790 	uint8_t		rspStatus3;	/* FCP_STATUS byte 3 SCSI status byte */
791 #define	SCSI_STAT_GOOD		0x00
792 #define	SCSI_STAT_CHECK_COND	0x02
793 #define	SCSI_STAT_COND_MET	0x04
794 #define	SCSI_STAT_BUSY		0x08
795 #define	SCSI_STAT_INTERMED	0x10
796 #define	SCSI_STAT_INTERMED_CM	0x14
797 #define	SCSI_STAT_RES_CNFLCT	0x18
798 #define	SCSI_STAT_CMD_TERM	0x22
799 #define	SCSI_STAT_QUE_FULL	0x28
800 #define	SCSI_STAT_ACA_ACTIVE	0x30
801 #define	SCSI_STAT_TASK_ABORT	0x40
802 
803 	uint32_t	rspResId;	/* Residual xfer if RESID_xxxx set */
804 					/* in fcpStatus2. */
805 					/* Received in Big Endian format */
806 	uint32_t	rspSnsLen;	/* Length of sense data in fcpSnsInfo */
807 					/* Received in Big Endian format */
808 	uint32_t	rspRspLen;	/* Length of FCP response data */
809 					/* in fcpRspInfo */
810 					/* Received in Big Endian format */
811 
812 	uint8_t		rspInfo0;	/* FCP_RSP_INFO byte 0 (reserved) */
813 	uint8_t		rspInfo1;	/* FCP_RSP_INFO byte 1 (reserved) */
814 	uint8_t		rspInfo2;	/* FCP_RSP_INFO byte 2 (reserved) */
815 	uint8_t		rspInfo3;	/* FCP_RSP_INFO RSP_CODE byte 3 */
816 
817 #define	RSP_NO_FAILURE		0x00
818 #define	RSP_DATA_BURST_ERR	0x01
819 #define	RSP_CMD_FIELD_ERR	0x02
820 #define	RSP_RO_MISMATCH_ERR	0x03
821 #define	RSP_TM_NOT_SUPPORTED	0x04	/* Task mgmt function not supported */
822 #define	RSP_TM_NOT_COMPLETED	0x05	/* Task mgmt function not performed */
823 
824 	uint32_t	rspInfoRsvd;	/* FCP_RSP_INFO bytes 4-7 (reserved) */
825 
826 	/*
827 	 * Define maximum size of SCSI Sense buffer.
828 	 * Seagate never issues more than 18 bytes of Sense data
829 	 */
830 #define	MAX_FCP_SNS	128
831 	uint8_t		rspSnsInfo[MAX_FCP_SNS];
832 } emlxs_fcp_rsp;
833 typedef emlxs_fcp_rsp FCP_RSP;
834 
835 
836 typedef struct emlxs_fcp_cmd
837 {
838 	uint32_t	fcpLunMsl;	/* most significant lun word */
839 	uint32_t	fcpLunLsl;	/* least significant lun word */
840 
841 	/*
842 	 * # of bits to shift lun id to end up in right payload word,
843 	 * little endian = 8, big = 16.
844 	 */
845 #ifdef EMLXS_LITTLE_ENDIAN
846 #define	FC_LUN_SHIFT		8
847 #define	FC_ADDR_MODE_SHIFT	0
848 #endif
849 #ifdef EMLXS_BIG_ENDIAN
850 #define	FC_LUN_SHIFT		16
851 #define	FC_ADDR_MODE_SHIFT	24
852 #endif
853 
854 	uint8_t		fcpCntl0;	/* FCP_CNTL byte 0 (reserved) */
855 	uint8_t		fcpCntl1;	/* FCP_CNTL byte 1 task codes */
856 #define	SIMPLE_Q	0x00
857 #define	HEAD_OF_Q	0x01
858 #define	ORDERED_Q	0x02
859 #define	ACA_Q		0x04
860 #define	UNTAGGED	0x05
861 
862 	uint8_t		fcpCntl2;	/* FCP_CTL byte 2 task management */
863 					/* codes */
864 #define	ABORT_TASK_SET	0x02	/* Bit 1 */
865 #define	CLEAR_TASK_SET	0x04	/* bit 2 */
866 #define	LUN_RESET	0x10	/* bit 4 */
867 #define	TARGET_RESET	0x20	/* bit 5 */
868 #define	CLEAR_ACA	0x40	/* bit 6 */
869 #define	TERMINATE_TASK	0x80	/* bit 7 */
870 
871 	uint8_t		fcpCntl3;
872 #define	WRITE_DATA	0x01	/* Bit 0 */
873 #define	READ_DATA	0x02	/* Bit 1 */
874 
875 	uint8_t		fcpCdb[16];	/* SRB cdb field is copied here */
876 	uint32_t	fcpDl;	/* Total transfer length */
877 } emlxs_fcp_cmd_t;
878 typedef emlxs_fcp_cmd_t FCP_CMND;
879 
880 
881 
882 
883 /* SCSI INQUIRY Command Structure */
884 
885 typedef struct emlxs_inquiryDataType
886 {
887 	uint8_t		DeviceType:5;
888 	uint8_t		DeviceTypeQualifier:3;
889 
890 	uint8_t		DeviceTypeModifier:7;
891 	uint8_t		RemovableMedia:1;
892 
893 	uint8_t		Versions;
894 	uint8_t		ResponseDataFormat;
895 	uint8_t		AdditionalLength;
896 	uint8_t		Reserved[2];
897 
898 	uint8_t		SoftReset:1;
899 	uint8_t		CommandQueue:1;
900 	uint8_t		Reserved2:1;
901 	uint8_t		LinkedCommands:1;
902 	uint8_t		Synchronous:1;
903 	uint8_t		Wide16Bit:1;
904 	uint8_t		Wide32Bit:1;
905 	uint8_t		RelativeAddressing:1;
906 
907 	uint8_t		VendorId[8];
908 	uint8_t		ProductId[16];
909 	uint8_t		ProductRevisionLevel[4];
910 	uint8_t		VendorSpecific[20];
911 	uint8_t		Reserved3[40];
912 } emlxs_inquiry_data_type_t;
913 typedef emlxs_inquiry_data_type_t INQUIRY_DATA_DEF;
914 
915 
916 typedef struct emlxs_read_capacity_data
917 {
918 	uint32_t	LogicalBlockAddress;
919 	uint32_t	BytesPerBlock;
920 } emlxs_read_capacity_data_t;
921 typedef emlxs_read_capacity_data_t READ_CAPACITY_DATA_DEF;
922 
923 
924 /* SCSI CDB command codes */
925 #define	FCP_SCSI_FORMAT_UNIT			0x04
926 #define	FCP_SCSI_INQUIRY			0x12
927 #define	FCP_SCSI_MODE_SELECT			0x15
928 #define	FCP_SCSI_MODE_SENSE			0x1A
929 #define	FCP_SCSI_PAUSE_RESUME			0x4B
930 #define	FCP_SCSI_PLAY_AUDIO			0x45
931 #define	FCP_SCSI_PLAY_AUDIO_EXT			0xA5
932 #define	FCP_SCSI_PLAY_AUDIO_MSF			0x47
933 #define	FCP_SCSI_PLAY_AUDIO_TRK_INDX		0x48
934 #define	FCP_SCSI_PREVENT_ALLOW_REMOVAL		0x1E
935 #define	FCP_SCSI_READ_CMD			0x08
936 #define	FCP_SCSI_READ_BUFFER			0x3C
937 #define	FCP_SCSI_READ_CAPACITY			0x25
938 #define	FCP_SCSI_READ_DEFECT_LIST		0x37
939 #define	FCP_SCSI_READ_EXTENDED			0x28
940 #define	FCP_SCSI_READ_HEADER			0x44
941 #define	FCP_SCSI_READ_LONG			0xE8
942 #define	FCP_SCSI_READ_SUB_CHANNEL		0x42
943 #define	FCP_SCSI_READ_TOC			0x43
944 #define	FCP_SCSI_REASSIGN_BLOCK			0x07
945 #define	FCP_SCSI_RECEIVE_DIAGNOSTIC_RESULTS	0x1C
946 #define	FCP_SCSI_RELEASE_UNIT			0x17
947 #define	FCP_SCSI_REPORT_LUNS			0xa0
948 #define	FCP_SCSI_REQUEST_SENSE			0x03
949 #define	FCP_SCSI_RESERVE_UNIT			0x16
950 #define	FCP_SCSI_REZERO_UNIT			0x01
951 #define	FCP_SCSI_SEEK				0x0B
952 #define	FCP_SCSI_SEEK_EXTENDED			0x2B
953 #define	FCP_SCSI_SEND_DIAGNOSTIC		0x1D
954 #define	FCP_SCSI_START_STOP_UNIT		0x1B
955 #define	FCP_SCSI_TEST_UNIT_READY		0x00
956 #define	FCP_SCSI_VERIFY				0x2F
957 #define	FCP_SCSI_WRITE_CMD			0x0A
958 #define	FCP_SCSI_WRITE_AND_VERIFY		0x2E
959 #define	FCP_SCSI_WRITE_BUFFER			0x3B
960 #define	FCP_SCSI_WRITE_EXTENDED			0x2A
961 #define	FCP_SCSI_WRITE_LONG			0xEA
962 #define	FCP_SCSI_RELEASE_LUNR			0xBB
963 #define	FCP_SCSI_RELEASE_LUNV			0xBF
964 
965 #define	HPVA_SETPASSTHROUGHMODE			0x27
966 #define	HPVA_EXECUTEPASSTHROUGH			0x29
967 #define	HPVA_CREATELUN				0xE2
968 #define	HPVA_SETLUNSECURITYLIST			0xED
969 #define	HPVA_SETCLOCK				0xF9
970 #define	HPVA_RECOVER				0xFA
971 #define	HPVA_GENERICSERVICEOUT			0xFD
972 
973 #define	DMEP_EXPORT_IN				0x85
974 #define	DMEP_EXPORT_OUT				0x89
975 
976 #define	MDACIOCTL_DIRECT_CMD			0x22
977 #define	MDACIOCTL_STOREIMAGE			0x2C
978 #define	MDACIOCTL_WRITESIGNATURE		0xA6
979 #define	MDACIOCTL_SETREALTIMECLOCK		0xAC
980 #define	MDACIOCTL_PASS_THRU_CDB			0xAD
981 #define	MDACIOCTL_PASS_THRU_INITIATE		0xAE
982 #define	MDACIOCTL_CREATENEWCONF			0xC0
983 #define	MDACIOCTL_ADDNEWCONF			0xC4
984 #define	MDACIOCTL_MORE				0xC6
985 #define	MDACIOCTL_SETPHYSDEVPARAMETER		0xC8
986 #define	MDACIOCTL_SETLOGDEVPARAMETER		0xCF
987 #define	MDACIOCTL_SETCONTROLLERPARAMETER	0xD1
988 #define	MDACIOCTL_WRITESANMAP			0xD4
989 #define	MDACIOCTL_SETMACADDRESS			0xD5
990 
991 /*
992  * End of FCP specific structures
993  */
994 
995 #define	FL_ALPA		0x00	/* AL_PA of FL_Port */
996 
997 /* Fibre Channel Service Parameter definitions */
998 
999 #define	FC_PH_4_0	6	/* FC-PH version 4.0 */
1000 #define	FC_PH_4_1	7	/* FC-PH version 4.1 */
1001 #define	FC_PH_4_2	8	/* FC-PH version 4.2 */
1002 #define	FC_PH_4_3	9	/* FC-PH version 4.3 */
1003 
1004 #define	FC_PH_LOW	8	/* Lowest supported FC-PH version */
1005 #define	FC_PH_HIGH	9	/* Highest supported FC-PH version */
1006 #define	FC_PH3		0x20	/* FC-PH-3 version */
1007 
1008 #define	FF_FRAME_SIZE	2048
1009 
1010 
1011 typedef struct emlxs_rings
1012 {
1013 #ifdef EMLXS_BIG_ENDIAN
1014 	uint32_t	crReserved:16;
1015 	uint32_t	crBegin:8;
1016 	uint32_t	crEnd:8;	/* Low order bit first word */
1017 	uint32_t	rrReserved:16;
1018 	uint32_t	rrBegin:8;
1019 	uint32_t	rrEnd:8;	/* Low order bit second word */
1020 #endif
1021 #ifdef EMLXS_LITTLE_ENDIAN
1022 	uint32_t	crEnd:8;	/* Low order bit first word */
1023 	uint32_t	crBegin:8;
1024 	uint32_t	crReserved:16;
1025 	uint32_t	rrEnd:8;	/* Low order bit second word */
1026 	uint32_t	rrBegin:8;
1027 	uint32_t	rrReserved:16;
1028 #endif
1029 } emlxs_rings_t;
1030 typedef emlxs_rings_t RINGS;
1031 
1032 
1033 typedef struct emlxs_ring_def
1034 {
1035 #ifdef EMLXS_BIG_ENDIAN
1036 	uint16_t	offCiocb;
1037 	uint16_t	numCiocb;
1038 	uint16_t	offRiocb;
1039 	uint16_t	numRiocb;
1040 #endif
1041 #ifdef EMLXS_LITTLE_ENDIAN
1042 	uint16_t	numCiocb;
1043 	uint16_t	offCiocb;
1044 	uint16_t	numRiocb;
1045 	uint16_t	offRiocb;
1046 #endif
1047 } emlxs_ring_def_t;
1048 typedef emlxs_ring_def_t RING_DEF;
1049 
1050 /*
1051  * The following F.C. frame stuctures are defined in Big Endian format.
1052  */
1053 
1054 typedef struct emlxs_name_type
1055 {
1056 #ifdef EMLXS_BIG_ENDIAN
1057 	uint8_t		nameType:4;	/* FC Word 0, bit 28:31 */
1058 	uint8_t		IEEEextMsn:4;	/* FC Word 0, bit 24:27, bit 8:11 */
1059 					/* of IEEE ext */
1060 #endif
1061 #ifdef EMLXS_LITTLE_ENDIAN
1062 	uint8_t		IEEEextMsn:4;	/* FC Word 0, bit 24:27, bit 8:11 */
1063 					/* of IEEE ext */
1064 	uint8_t		nameType:4;	/* FC Word 0, bit 28:31 */
1065 #endif
1066 #define	NAME_IEEE		0x1	/* IEEE name - nameType */
1067 #define	NAME_IEEE_EXT		0x2	/* IEEE extended name */
1068 #define	NAME_FC_TYPE		0x3	/* FC native name type */
1069 #define	NAME_IP_TYPE		0x4	/* IP address */
1070 #define	NAME_CCITT_TYPE		0xC
1071 #define	NAME_CCITT_GR_TYPE	0xE
1072 	uint8_t		IEEEextLsb;	/* FC Word 0, bit 16:23, */
1073 					/* IEEE extended Lsb */
1074 	uint8_t		IEEE[6];	/* FC IEEE address */
1075 } emlxs_name_type_t;
1076 typedef emlxs_name_type_t NAME_TYPE;
1077 
1078 
1079 typedef struct emlxs_csp
1080 {
1081 	uint8_t		fcphHigh;		/* FC Word 0, byte 0 */
1082 	uint8_t		fcphLow;
1083 	uint8_t		bbCreditMsb;
1084 	uint8_t		bbCreditlsb;		/* FC Word 0, byte 3 */
1085 #ifdef EMLXS_BIG_ENDIAN
1086 	uint16_t	reqMultipleNPort:1;	/* FC Word 1, bit 31 */
1087 	uint16_t	randomOffset:1;		/* FC Word 1, bit 30 */
1088 	uint16_t	rspMultipleNPort:1;	/* FC Word 1, bit 29 */
1089 	uint16_t	fPort:1;		/* FC Word 1, bit 28 */
1090 	uint16_t	altBbCredit:1;		/* FC Word 1, bit 27 */
1091 	uint16_t	edtovResolution:1;	/* FC Word 1, bit 26 */
1092 	uint16_t	multicast:1;		/* FC Word 1, bit 25 */
1093 	uint16_t	broadcast:1;		/* FC Word 1, bit 24 */
1094 
1095 	uint16_t	huntgroup:1;		/* FC Word 1, bit 23 */
1096 	uint16_t	simplex:1;		/* FC Word 1, bit 22 */
1097 
1098 	uint16_t	fcsp_support:1;		/* FC Word 1, bit 21 */
1099 	uint16_t	word1Reserved20:1;	/* FC Word 1, bit 20 */
1100 	uint16_t	word1Reserved19:1;	/* FC Word 1, bit 19 */
1101 
1102 	uint16_t	dhd:1;			/* FC Word 1, bit 18 */
1103 	uint16_t	contIncSeqCnt:1;	/* FC Word 1, bit 17 */
1104 	uint16_t	payloadlength:1;	/* FC Word 1, bit 16 */
1105 #endif
1106 #ifdef EMLXS_LITTLE_ENDIAN
1107 	uint16_t	broadcast:1;		/* FC Word 1, bit 24 */
1108 	uint16_t	multicast:1;		/* FC Word 1, bit 25 */
1109 	uint16_t	edtovResolution:1;	/* FC Word 1, bit 26 */
1110 	uint16_t	altBbCredit:1;		/* FC Word 1, bit 27 */
1111 	uint16_t	fPort:1;		/* FC Word 1, bit 28 */
1112 	uint16_t	rspMultipleNPort:1;	/* FC Word 1, bit 29 */
1113 	uint16_t	randomOffset:1;		/* FC Word 1, bit 30 */
1114 	uint16_t	reqMultipleNPort:1;	/* FC Word 1, bit 31 */
1115 
1116 	uint16_t	payloadlength:1;	/* FC Word 1, bit 16 */
1117 	uint16_t	contIncSeqCnt:1;	/* FC Word 1, bit 17 */
1118 	uint16_t	dhd:1;			/* FC Word 1, bit 18 */
1119 
1120 	uint16_t	word1Reserved19:1;	/* FC Word 1, bit 19 */
1121 	uint16_t	word1Reserved20:1;	/* FC Word 1, bit 20 */
1122 	uint16_t	fcsp_support:1;		/* FC Word 1, bit 21 */
1123 
1124 	uint16_t	simplex:1;		/* FC Word 1, bit 22 */
1125 	uint16_t	huntgroup:1;		/* FC Word 1, bit 23 */
1126 #endif
1127 	uint8_t		bbRcvSizeMsb;		/* Upper nibble is reserved */
1128 	uint8_t		bbRcvSizeLsb;		/* FC Word 1, byte 3 */
1129 	union
1130 	{
1131 		struct
1132 		{
1133 			uint8_t	word2Reserved1;	/* FC Word 2 byte 0 */
1134 
1135 			uint8_t	totalConcurrSeq; /* FC Word 2 byte 1 */
1136 			uint8_t	roByCategoryMsb; /* FC Word 2 byte 2 */
1137 
1138 			uint8_t	roByCategoryLsb; /* FC Word 2 byte 3 */
1139 		} nPort;
1140 		uint32_t	r_a_tov;	/* R_A_TOV must be in Big */
1141 						/* Endian format */
1142 	} w2;
1143 
1144 	uint32_t	e_d_tov;		/* E_D_TOV must be in Big */
1145 						/* Endian format */
1146 } emlxs_csp_t;
1147 typedef emlxs_csp_t CSP;
1148 
1149 
1150 typedef struct emlxs_class_parms
1151 {
1152 #ifdef EMLXS_BIG_ENDIAN
1153 	uint8_t	classValid:1;		/* FC Word 0, bit 31 */
1154 	uint8_t	intermix:1;		/* FC Word 0, bit 30 */
1155 	uint8_t	stackedXparent:1;	/* FC Word 0, bit 29 */
1156 	uint8_t	stackedLockDown:1;	/* FC Word 0, bit 28 */
1157 	uint8_t	seqDelivery:1;		/* FC Word 0, bit 27 */
1158 	uint8_t	word0Reserved1:3;	/* FC Word 0, bit 24:26 */
1159 #endif
1160 #ifdef EMLXS_LITTLE_ENDIAN
1161 	uint8_t	word0Reserved1:3;	/* FC Word 0, bit 24:26 */
1162 	uint8_t	seqDelivery:1;		/* FC Word 0, bit 27 */
1163 	uint8_t	stackedLockDown:1;	/* FC Word 0, bit 28 */
1164 	uint8_t	stackedXparent:1;	/* FC Word 0, bit 29 */
1165 	uint8_t	intermix:1;		/* FC Word 0, bit 30 */
1166 	uint8_t	classValid:1;		/* FC Word 0, bit 31 */
1167 
1168 #endif
1169 	uint8_t	word0Reserved2;		/* FC Word 0, bit 16:23 */
1170 #ifdef EMLXS_BIG_ENDIAN
1171 	uint8_t	iCtlXidReAssgn:2;	/* FC Word 0, Bit 14:15 */
1172 	uint8_t	iCtlInitialPa:2;	/* FC Word 0, bit 12:13 */
1173 	uint8_t	iCtlAck0capable:1;	/* FC Word 0, bit 11 */
1174 	uint8_t	iCtlAckNcapable:1;	/* FC Word 0, bit 10 */
1175 	uint8_t	word0Reserved3:2;	/* FC Word 0, bit  8: 9 */
1176 #endif
1177 #ifdef EMLXS_LITTLE_ENDIAN
1178 	uint8_t	word0Reserved3:2;	/* FC Word 0, bit  8: 9 */
1179 	uint8_t	iCtlAckNcapable:1;	/* FC Word 0, bit 10 */
1180 	uint8_t	iCtlAck0capable:1;	/* FC Word 0, bit 11 */
1181 	uint8_t	iCtlInitialPa:2;	/* FC Word 0, bit 12:13 */
1182 	uint8_t	iCtlXidReAssgn:2;	/* FC Word 0, Bit 14:15 */
1183 #endif
1184 	uint8_t	word0Reserved4;		/* FC Word 0, bit  0: 7 */
1185 #ifdef EMLXS_BIG_ENDIAN
1186 	uint8_t	rCtlAck0capable:1;	/* FC Word 1, bit 31 */
1187 	uint8_t	rCtlAckNcapable:1;	/* FC Word 1, bit 30 */
1188 	uint8_t	rCtlXidInterlck:1;	/* FC Word 1, bit 29 */
1189 	uint8_t	rCtlErrorPolicy:2;	/* FC Word 1, bit 27:28 */
1190 	uint8_t	word1Reserved1:1;	/* FC Word 1, bit 26 */
1191 	uint8_t	rCtlCatPerSeq:2;	/* FC Word 1, bit 24:25 */
1192 #endif
1193 #ifdef EMLXS_LITTLE_ENDIAN
1194 	uint8_t	rCtlCatPerSeq:2;	/* FC Word 1, bit 24:25 */
1195 	uint8_t	word1Reserved1:1;	/* FC Word 1, bit 26 */
1196 	uint8_t	rCtlErrorPolicy:2;	/* FC Word 1, bit 27:28 */
1197 	uint8_t	rCtlXidInterlck:1;	/* FC Word 1, bit 29 */
1198 	uint8_t	rCtlAckNcapable:1;	/* FC Word 1, bit 30 */
1199 	uint8_t	rCtlAck0capable:1;	/* FC Word 1, bit 31 */
1200 #endif
1201 	uint8_t	word1Reserved2;		/* FC Word 1, bit 16:23 */
1202 	uint8_t	rcvDataSizeMsb;		/* FC Word 1, bit  8:15 */
1203 	uint8_t	rcvDataSizeLsb;		/* FC Word 1, bit  0: 7 */
1204 
1205 	uint8_t	concurrentSeqMsb;	/* FC Word 2, bit 24:31 */
1206 	uint8_t	concurrentSeqLsb;	/* FC Word 2, bit 16:23 */
1207 	uint8_t	EeCreditSeqMsb;		/* FC Word 2, bit  8:15 */
1208 	uint8_t	EeCreditSeqLsb;		/* FC Word 2, bit  0: 7 */
1209 
1210 	uint8_t	openSeqPerXchgMsb;	/* FC Word 3, bit 24:31 */
1211 	uint8_t	openSeqPerXchgLsb;	/* FC Word 3, bit 16:23 */
1212 	uint8_t	word3Reserved1;		/* Fc Word 3, bit  8:15 */
1213 	uint8_t	word3Reserved2;		/* Fc Word 3, bit  0: 7 */
1214 } emlxs_class_parms_t;
1215 typedef emlxs_class_parms_t CLASS_PARMS;
1216 
1217 
1218 typedef struct emlxs_serv_parms
1219 { /* Structure is in Big Endian format */
1220 	CSP		cmn;
1221 	NAME_TYPE	portName;
1222 	NAME_TYPE	nodeName;
1223 	CLASS_PARMS	cls1;
1224 	CLASS_PARMS	cls2;
1225 	CLASS_PARMS	cls3;
1226 	CLASS_PARMS	cls4;
1227 	uint8_t		vendorVersion[16];
1228 } emlxs_serv_parms_t;
1229 typedef emlxs_serv_parms_t SERV_PARM;
1230 
1231 typedef struct
1232 {
1233 	union
1234 	{
1235 		uint32_t	word0;
1236 		struct
1237 		{
1238 #ifdef EMLXS_BIG_ENDIAN
1239 			uint32_t rsvd0:8;	/* Word 0, Byte 3 */
1240 			uint32_t oui:24;	/* Elx Organization */
1241 						/* Unique ID (0000C9) */
1242 #endif
1243 #ifdef EMLXS_LITTLE_ENDIAN
1244 			uint32_t oui:24;	/* Elx Organization */
1245 						/* Unique ID (0000C9) */
1246 			uint32_t rsvd0:8;	/* Word 0, Byte 3 */
1247 #endif
1248 		} w0;
1249 	} un0;
1250 	union
1251 	{
1252 		uint32_t	word1;
1253 		struct
1254 		{
1255 #ifdef EMLXS_BIG_ENDIAN
1256 			uint32_t vport:1;	/* Word 1, Bit 31 */
1257 			uint32_t rsvd1:31;	/* Word 1, Bit 0-30 */
1258 #endif
1259 #ifdef EMLXS_LITTLE_ENDIAN
1260 			uint32_t rsvd1:31;	/* Word 1, Bit 0-30 */
1261 			uint32_t vport:1;	/* Word 1, Bit 31 */
1262 #endif
1263 		} w1;
1264 	} un1;
1265 	uint8_t		rsvd2[8];
1266 } emlxs_vvl_fmt_t;
1267 
1268 #define	VALID_VENDOR_VERSION	cmn.rspMultipleNPort
1269 
1270 
1271 
1272 /*
1273  * Extended Link Service LS_COMMAND codes (Payload BYTE 0)
1274  */
1275 #ifdef EMLXS_BIG_ENDIAN
1276 #define	ELS_CMD_SHIFT	24
1277 #define	ELS_CMD_MASK	0xff000000
1278 #define	ELS_RSP_MASK	0xff000000
1279 #define	ELS_CMD_LS_RJT	0x01000000
1280 #define	ELS_CMD_ACC	0x02000000
1281 #define	ELS_CMD_PLOGI	0x03000000
1282 #define	ELS_CMD_FLOGI	0x04000000
1283 #define	ELS_CMD_LOGO	0x05000000
1284 #define	ELS_CMD_ABTX	0x06000000
1285 #define	ELS_CMD_RCS	0x07000000
1286 #define	ELS_CMD_RES	0x08000000
1287 #define	ELS_CMD_RSS	0x09000000
1288 #define	ELS_CMD_RSI	0x0A000000
1289 #define	ELS_CMD_ESTS	0x0B000000
1290 #define	ELS_CMD_ESTC	0x0C000000
1291 #define	ELS_CMD_ADVC	0x0D000000
1292 #define	ELS_CMD_RTV	0x0E000000
1293 #define	ELS_CMD_RLS	0x0F000000
1294 #define	ELS_CMD_ECHO	0x10000000
1295 #define	ELS_CMD_TEST	0x11000000
1296 #define	ELS_CMD_RRQ	0x12000000
1297 #define	ELS_CMD_PRLI	0x20000000
1298 #define	ELS_CMD_PRLO	0x21000000
1299 #define	ELS_CMD_SCN	0x22000000
1300 #define	ELS_CMD_TPLS	0x23000000
1301 #define	ELS_CMD_GPRLO	0x24000000
1302 #define	ELS_CMD_GAID	0x30000000
1303 #define	ELS_CMD_FACT	0x31000000
1304 #define	ELS_CMD_FDACT	0x32000000
1305 #define	ELS_CMD_NACT	0x33000000
1306 #define	ELS_CMD_NDACT	0x34000000
1307 #define	ELS_CMD_QoSR	0x40000000
1308 #define	ELS_CMD_RVCS	0x41000000
1309 #define	ELS_CMD_PDISC	0x50000000
1310 #define	ELS_CMD_FDISC	0x51000000
1311 #define	ELS_CMD_ADISC	0x52000000
1312 #define	ELS_CMD_FARP	0x54000000
1313 #define	ELS_CMD_FARPR	0x55000000
1314 #define	ELS_CMD_FAN	0x60000000
1315 #define	ELS_CMD_RSCN	0x61000000
1316 #define	ELS_CMD_SCR	0x62000000
1317 #define	ELS_CMD_LINIT	0x70000000
1318 #define	ELS_CMD_RNID	0x78000000
1319 #define	ELS_CMD_AUTH	0x90000000
1320 #endif
1321 
1322 #ifdef EMLXS_LITTLE_ENDIAN
1323 #define	ELS_CMD_SHIFT	0
1324 #define	ELS_CMD_MASK	0xff
1325 #define	ELS_RSP_MASK	0xff
1326 #define	ELS_CMD_LS_RJT	0x01
1327 #define	ELS_CMD_ACC	0x02
1328 #define	ELS_CMD_PLOGI	0x03
1329 #define	ELS_CMD_FLOGI	0x04
1330 #define	ELS_CMD_LOGO	0x05
1331 #define	ELS_CMD_ABTX	0x06
1332 #define	ELS_CMD_RCS	0x07
1333 #define	ELS_CMD_RES	0x08
1334 #define	ELS_CMD_RSS	0x09
1335 #define	ELS_CMD_RSI	0x0A
1336 #define	ELS_CMD_ESTS	0x0B
1337 #define	ELS_CMD_ESTC	0x0C
1338 #define	ELS_CMD_ADVC	0x0D
1339 #define	ELS_CMD_RTV	0x0E
1340 #define	ELS_CMD_RLS	0x0F
1341 #define	ELS_CMD_ECHO	0x10
1342 #define	ELS_CMD_TEST	0x11
1343 #define	ELS_CMD_RRQ	0x12
1344 #define	ELS_CMD_PRLI	0x20
1345 #define	ELS_CMD_PRLO	0x21
1346 #define	ELS_CMD_SCN	0x22
1347 #define	ELS_CMD_TPLS	0x23
1348 #define	ELS_CMD_GPRLO	0x24
1349 #define	ELS_CMD_GAID	0x30
1350 #define	ELS_CMD_FACT	0x31
1351 #define	ELS_CMD_FDACT	0x32
1352 #define	ELS_CMD_NACT	0x33
1353 #define	ELS_CMD_NDACT	0x34
1354 #define	ELS_CMD_QoSR	0x40
1355 #define	ELS_CMD_RVCS	0x41
1356 #define	ELS_CMD_PDISC	0x50
1357 #define	ELS_CMD_FDISC	0x51
1358 #define	ELS_CMD_ADISC	0x52
1359 #define	ELS_CMD_FARP	0x54
1360 #define	ELS_CMD_FARPR	0x55
1361 #define	ELS_CMD_FAN	0x60
1362 #define	ELS_CMD_RSCN	0x61
1363 #define	ELS_CMD_SCR	0x62
1364 #define	ELS_CMD_LINIT	0x70
1365 #define	ELS_CMD_RNID	0x78
1366 #define	ELS_CMD_AUTH	0x90
1367 #endif
1368 
1369 
1370 /*
1371  * LS_RJT Payload Definition
1372  */
1373 
1374 typedef struct _LS_RJT
1375 { /* Structure is in Big Endian format */
1376 	union
1377 	{
1378 		uint32_t	lsRjtError;
1379 		struct
1380 		{
1381 			uint8_t	lsRjtRsvd0;	/* FC Word 0, */
1382 						/* bit 24:31 */
1383 
1384 			uint8_t	lsRjtRsnCode;	/* FC Word 0, */
1385 						/* bit 16:23 */
1386 			/* LS_RJT reason codes */
1387 #define	LSRJT_INVALID_CMD	0x01
1388 #define	LSRJT_LOGICAL_ERR	0x03
1389 #define	LSRJT_LOGICAL_BSY	0x05
1390 #define	LSRJT_PROTOCOL_ERR	0x07
1391 #define	LSRJT_UNABLE_TPC	0x09	/* Unable to perform command */
1392 #define	LSRJT_CMD_UNSUPPORTED	0x0B
1393 #define	LSRJT_VENDOR_UNIQUE	0xFF	/* See Byte 3 */
1394 
1395 			uint8_t	lsRjtRsnCodeExp;	/* FC Word 0, */
1396 							/* bit 8:15 */
1397 			/* LS_RJT reason explanation */
1398 #define	LSEXP_NOTHING_MORE	0x00
1399 #define	LSEXP_SPARM_OPTIONS	0x01
1400 #define	LSEXP_SPARM_ICTL	0x03
1401 #define	LSEXP_SPARM_RCTL	0x05
1402 #define	LSEXP_SPARM_RCV_SIZE	0x07
1403 #define	LSEXP_SPARM_CONCUR_SEQ	0x09
1404 #define	LSEXP_SPARM_CREDIT	0x0B
1405 #define	LSEXP_INVALID_PNAME	0x0D
1406 #define	LSEXP_INVALID_NNAME	0x0E
1407 #define	LSEXP_INVALID_CSP	0x0F
1408 #define	LSEXP_INVALID_ASSOC_HDR	0x11
1409 #define	LSEXP_ASSOC_HDR_REQ	0x13
1410 #define	LSEXP_INVALID_O_SID	0x15
1411 #define	LSEXP_INVALID_OX_RX	0x17
1412 #define	LSEXP_CMD_IN_PROGRESS	0x19
1413 #define	LSEXP_INVALID_NPORT_ID	0x1F
1414 #define	LSEXP_INVALID_SEQ_ID	0x21
1415 #define	LSEXP_INVALID_XCHG	0x23
1416 #define	LSEXP_INACTIVE_XCHG	0x25
1417 #define	LSEXP_RQ_REQUIRED	0x27
1418 #define	LSEXP_OUT_OF_RESOURCE	0x29
1419 #define	LSEXP_CANT_GIVE_DATA	0x2A
1420 #define	LSEXP_REQ_UNSUPPORTED	0x2C
1421 			uint8_t	vendorUnique;	/* FC Word 0, bit  0: 7 */
1422 		} b;
1423 	} un;
1424 } LS_RJT;
1425 
1426 
1427 /*
1428  * N_Port Login (FLOGO/PLOGO Request) Payload Definition
1429  */
1430 
1431 typedef struct _LOGO
1432 { /* Structure is in Big Endian format */
1433 	union
1434 	{
1435 		uint32_t	nPortId32;	/* Access nPortId as a word */
1436 		struct
1437 		{
1438 			uint8_t	word1Reserved1;	/* FC Word 1, bit 31:24 */
1439 			uint8_t	nPortIdByte0;	/* N_port  ID bit 16:23 */
1440 			uint8_t	nPortIdByte1;	/* N_port  ID bit  8:15 */
1441 			uint8_t	nPortIdByte2;	/* N_port  ID bit  0: 7 */
1442 		} b;
1443 	} un;
1444 	NAME_TYPE		portName;	/* N_port name field */
1445 } LOGO;
1446 
1447 
1448 /*
1449  * FCP Login (PRLI Request / ACC) Payload Definition
1450  */
1451 
1452 #define	PRLX_PAGE_LEN	0x10
1453 #define	TPRLO_PAGE_LEN	0x14
1454 
1455 typedef struct _PRLI
1456 { /* Structure is in Big Endian format */
1457 	uint8_t		prliType;		/* FC Parm Word 0, bit 24:31 */
1458 
1459 #define	PRLI_FCP_TYPE 0x08
1460 	uint8_t		word0Reserved1;		/* FC Parm Word 0, bit 16:23 */
1461 
1462 #ifdef EMLXS_BIG_ENDIAN
1463 	uint8_t		origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
1464 	uint8_t		respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
1465 	uint8_t		estabImagePair:1;	/* FC Parm Word 0, bit 13 */
1466 
1467 	/* ACC = imagePairEstablished */
1468 	uint8_t		word0Reserved2:1;	/* FC Parm Word 0, bit 12 */
1469 	uint8_t		acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, */
1470 						/* ACC ONLY */
1471 #endif
1472 #ifdef EMLXS_LITTLE_ENDIAN
1473 	uint8_t		acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, */
1474 						/* ACC ONLY */
1475 	uint8_t		word0Reserved2:1;	/* FC Parm Word 0, bit 12 */
1476 	uint8_t		estabImagePair:1;	/* FC Parm Word 0, bit 13 */
1477 	uint8_t		respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
1478 	uint8_t		origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
1479 	/* ACC = imagePairEstablished */
1480 #endif
1481 #define	PRLI_REQ_EXECUTED	0x1		/* acceptRspCode */
1482 #define	PRLI_NO_RESOURCES	0x2
1483 #define	PRLI_INIT_INCOMPLETE	0x3
1484 #define	PRLI_NO_SUCH_PA		0x4
1485 #define	PRLI_PREDEF_CONFIG	0x5
1486 #define	PRLI_PARTIAL_SUCCESS	0x6
1487 #define	PRLI_INVALID_PAGE_CNT	0x7
1488 	uint8_t		word0Reserved3;		/* FC Parm Word 0, bit 0:7 */
1489 
1490 	uint32_t	origProcAssoc;		/* FC Parm Word 1, bit 0:31 */
1491 
1492 	uint32_t	respProcAssoc;		/* FC Parm Word 2, bit 0:31 */
1493 
1494 	uint8_t		word3Reserved1;		/* FC Parm Word 3, bit 24:31 */
1495 	uint8_t		word3Reserved2;		/* FC Parm Word 3, bit 16:23 */
1496 #ifdef EMLXS_BIG_ENDIAN
1497 	uint16_t	Word3bit15Resved:1;	/* FC Parm Word 3, bit 15 */
1498 	uint16_t	Word3bit14Resved:1;	/* FC Parm Word 3, bit 14 */
1499 	uint16_t	Word3bit13Resved:1;	/* FC Parm Word 3, bit 13 */
1500 	uint16_t	Word3bit12Resved:1;	/* FC Parm Word 3, bit 12 */
1501 	uint16_t	Word3bit11Resved:1;	/* FC Parm Word 3, bit 11 */
1502 	uint16_t	Word3bit10Resved:1;	/* FC Parm Word 3, bit 10 */
1503 	uint16_t	TaskRetryIdReq:1;	/* FC Parm Word 3, bit  9 */
1504 	uint16_t	Retry:1;		/* FC Parm Word 3, bit  8 */
1505 	uint16_t	ConfmComplAllowed:1;	/* FC Parm Word 3, bit  7 */
1506 	uint16_t	dataOverLay:1;		/* FC Parm Word 3, bit  6 */
1507 	uint16_t	initiatorFunc:1;	/* FC Parm Word 3, bit  5 */
1508 	uint16_t	targetFunc:1;		/* FC Parm Word 3, bit  4 */
1509 	uint16_t	cmdDataMixEna:1;	/* FC Parm Word 3, bit  3 */
1510 	uint16_t	dataRspMixEna:1;	/* FC Parm Word 3, bit  2 */
1511 	uint16_t	readXferRdyDis:1;	/* FC Parm Word 3, bit  1 */
1512 	uint16_t	writeXferRdyDis:1;	/* FC Parm Word 3, bit  0 */
1513 #endif
1514 #ifdef EMLXS_LITTLE_ENDIAN
1515 	uint16_t	Retry:1;		/* FC Parm Word 3, bit  8 */
1516 	uint16_t	TaskRetryIdReq:1;	/* FC Parm Word 3, bit  9 */
1517 	uint16_t	Word3bit10Resved:1;	/* FC Parm Word 3, bit 10 */
1518 	uint16_t	Word3bit11Resved:1;	/* FC Parm Word 3, bit 11 */
1519 	uint16_t	Word3bit12Resved:1;	/* FC Parm Word 3, bit 12 */
1520 	uint16_t	Word3bit13Resved:1;	/* FC Parm Word 3, bit 13 */
1521 	uint16_t	Word3bit14Resved:1;	/* FC Parm Word 3, bit 14 */
1522 	uint16_t	Word3bit15Resved:1;	/* FC Parm Word 3, bit 15 */
1523 	uint16_t	writeXferRdyDis:1;	/* FC Parm Word 3, bit  0 */
1524 	uint16_t	readXferRdyDis:1;	/* FC Parm Word 3, bit  1 */
1525 	uint16_t	dataRspMixEna:1;	/* FC Parm Word 3, bit  2 */
1526 	uint16_t	cmdDataMixEna:1;	/* FC Parm Word 3, bit  3 */
1527 	uint16_t	targetFunc:1;		/* FC Parm Word 3, bit  4 */
1528 	uint16_t	initiatorFunc:1;	/* FC Parm Word 3, bit  5 */
1529 	uint16_t	dataOverLay:1;		/* FC Parm Word 3, bit  6 */
1530 	uint16_t	ConfmComplAllowed:1;	/* FC Parm Word 3, bit  7 */
1531 #endif
1532 } PRLI;
1533 
1534 /*
1535  * FCP Logout (PRLO Request / ACC) Payload Definition
1536  */
1537 
1538 typedef struct _PRLO
1539 { /* Structure is in Big Endian format */
1540 	uint8_t		prloType;	/* FC Parm Word 0, bit 24:31 */
1541 
1542 #define	PRLO_FCP_TYPE	0x08
1543 	uint8_t		word0Reserved1;	/* FC Parm Word 0, bit 16:23 */
1544 
1545 #ifdef EMLXS_BIG_ENDIAN
1546 	uint8_t		origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
1547 	uint8_t		respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
1548 	uint8_t		word0Reserved2:2;	/* FC Parm Word 0, bit 12:13 */
1549 	uint8_t		acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, */
1550 						/* ACC ONLY */
1551 #endif
1552 #ifdef EMLXS_LITTLE_ENDIAN
1553 	uint8_t		acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, */
1554 						/* ACC ONLY */
1555 	uint8_t		word0Reserved2:2;	/* FC Parm Word 0, bit 12:13 */
1556 	uint8_t		respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
1557 	uint8_t		origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
1558 #endif
1559 #define	PRLO_REQ_EXECUTED	0x1		/* acceptRspCode */
1560 #define	PRLO_NO_SUCH_IMAGE	0x4
1561 #define	PRLO_INVALID_PAGE_CNT	0x7
1562 
1563 	uint8_t		word0Reserved3;		/* FC Parm Word 0, bit 0:7 */
1564 	uint32_t	origProcAssoc;		/* FC Parm Word 1, bit 0:31 */
1565 	uint32_t	respProcAssoc;		/* FC Parm Word 2, bit 0:31 */
1566 	uint32_t	word3Reserved1;		/* FC Parm Word 3, bit 0:31 */
1567 } PRLO;
1568 
1569 
1570 typedef struct _ADISC
1571 { /* Structure is in Big Endian format */
1572 	uint32_t	hardAL_PA;
1573 	NAME_TYPE	portName;
1574 	NAME_TYPE	nodeName;
1575 	uint32_t	DID;
1576 } ADISC;
1577 
1578 
1579 typedef struct _FARP
1580 { /* Structure is in Big Endian format */
1581 	uint32_t	Mflags:8;
1582 	uint32_t	Odid:24;
1583 #define	FARP_NO_ACTION	0	/* FARP information enclosed, no action */
1584 #define	FARP_MATCH_PORT	0x1	/* Match on Responder Port Name */
1585 #define	FARP_MATCH_NODE	0x2	/* Match on Responder Node Name */
1586 #define	FARP_MATCH_IP	0x4	/* Match on IP address, not supported */
1587 #define	FARP_MATCH_IPV4	0x5	/* Match on IPV4 address, not supported */
1588 #define	FARP_MATCH_IPV6	0x6	/* Match on IPV6 address, not supported */
1589 	uint32_t	Rflags:8;
1590 	uint32_t	Rdid:24;
1591 #define	FARP_REQUEST_PLOGI	0x1	/* Request for PLOGI */
1592 #define	FARP_REQUEST_FARPR	0x2	/* Request for FARP Response */
1593 	NAME_TYPE	OportName;
1594 	NAME_TYPE	OnodeName;
1595 	NAME_TYPE	RportName;
1596 	NAME_TYPE	RnodeName;
1597 	uint8_t		Oipaddr[16];
1598 	uint8_t		Ripaddr[16];
1599 } FARP;
1600 
1601 typedef struct _FAN
1602 { /* Structure is in Big Endian format */
1603 	uint32_t	Fdid;
1604 	NAME_TYPE	FportName;
1605 	NAME_TYPE	FnodeName;
1606 } FAN;
1607 
1608 typedef struct _SCR
1609 { /* Structure is in Big Endian format */
1610 	uint8_t		resvd1;
1611 	uint8_t		resvd2;
1612 	uint8_t		resvd3;
1613 	uint8_t		Function;
1614 #define	SCR_FUNC_FABRIC	0x01
1615 #define	SCR_FUNC_NPORT	0x02
1616 #define	SCR_FUNC_FULL	0x03
1617 #define	SCR_CLEAR	0xff
1618 } SCR;
1619 
1620 typedef struct _RNID_TOP_DISC
1621 {
1622 	NAME_TYPE	portName;
1623 	uint8_t		resvd[8];
1624 	uint32_t	unitType;
1625 #define	RNID_HBA	0x7
1626 #define	RNID_HOST	0xa
1627 #define	RNID_DRIVER	0xd
1628 	uint32_t	physPort;
1629 	uint32_t	attachedNodes;
1630 	uint16_t	ipVersion;
1631 #define	RNID_IPV4	0x1
1632 #define	RNID_IPV6	0x2
1633 	uint16_t	UDPport;
1634 	uint8_t		ipAddr[16];
1635 	uint16_t	resvd1;
1636 	uint16_t	flags;
1637 #define	RNID_TD_SUPPORT	0x1
1638 #define	RNID_LP_VALID	0x2
1639 } RNID_TOP_DISC;
1640 
1641 typedef struct _RNID
1642 { /* Structure is in Big Endian format */
1643 	uint8_t		Format;
1644 #define	RNID_TOPOLOGY_DISC  0xdf
1645 	uint8_t		CommonLen;
1646 	uint8_t		resvd1;
1647 	uint8_t		SpecificLen;
1648 	NAME_TYPE	portName;
1649 	NAME_TYPE	nodeName;
1650 	union
1651 	{
1652 		RNID_TOP_DISC topologyDisc;	/* topology disc (0xdf) */
1653 	} un;
1654 } RNID;
1655 
1656 typedef struct _RRQ
1657 { /* Structure is in Big Endian format */
1658 	uint32_t	SID;
1659 	uint16_t	Oxid;
1660 	uint16_t	Rxid;
1661 	uint8_t		resv[32];	/* optional association hdr */
1662 } RRQ;
1663 
1664 
1665 /* This is used for RSCN command */
1666 typedef struct _D_ID
1667 { /* Structure is in Big Endian format */
1668 	union
1669 	{
1670 		uint32_t	word;
1671 		struct
1672 		{
1673 #ifdef EMLXS_BIG_ENDIAN
1674 			uint8_t	resv;
1675 			uint8_t	domain;
1676 			uint8_t	area;
1677 			uint8_t	id;
1678 #endif
1679 #ifdef EMLXS_LITTLE_ENDIAN
1680 			uint8_t	id;
1681 			uint8_t	area;
1682 			uint8_t	domain;
1683 			uint8_t	resv;
1684 #endif
1685 		} b;
1686 	} un;
1687 } D_ID;
1688 
1689 /*
1690  * Structure to define	all ELS Payload types
1691  */
1692 
1693 typedef struct _ELS_PKT
1694 { /* Structure is in Big Endian format */
1695 	uint8_t		elsCode;		/* FC Word 0, bit 24:31 */
1696 	uint8_t		elsByte1;
1697 	uint8_t		elsByte2;
1698 	uint8_t		elsByte3;
1699 	union
1700 	{
1701 		LS_RJT		lsRjt;		/* Payload for LS_RJT */
1702 		SERV_PARM	logi;		/* Payload for PLOGI, FLOGI */
1703 						/* PDISC, ACC */
1704 		LOGO		logo;		/* Payload for PLOGO, FLOGO */
1705 						/* ACC */
1706 		PRLI		prli;		/* Payload for PRLI/ACC */
1707 		PRLO		prlo;		/* Payload for PRLO/ACC */
1708 		ADISC		adisc;		/* Payload for ADISC/ACC */
1709 		FARP		farp;		/* Payload for FARP/ACC */
1710 		FAN		fan;		/* Payload for FAN */
1711 		SCR		scr;		/* Payload for SCR/ACC */
1712 		RRQ		rrq;		/* Payload for RRQ */
1713 		RNID		rnid;		/* Payload for RNID */
1714 		uint8_t		pad[128 - 4];	/* Pad out to payload of */
1715 						/* 128 bytes */
1716 	} un;
1717 } ELS_PKT;
1718 
1719 
1720 typedef struct
1721 {
1722 	uint32_t	bdeAddress;
1723 #ifdef EMLXS_BIG_ENDIAN
1724 	uint32_t	bdeReserved:4;
1725 	uint32_t	bdeAddrHigh:4;
1726 	uint32_t	bdeSize:24;
1727 #endif
1728 #ifdef EMLXS_LITTLE_ENDIAN
1729 	uint32_t	bdeSize:24;
1730 	uint32_t	bdeAddrHigh:4;
1731 	uint32_t	bdeReserved:4;
1732 #endif
1733 } ULP_BDE;
1734 
1735 typedef struct ULP_BDE_64
1736 { /* SLI-2 */
1737 	union ULP_BDE_TUS
1738 	{
1739 		uint32_t	w;
1740 		struct
1741 		{
1742 #ifdef EMLXS_BIG_ENDIAN
1743 			uint32_t	bdeFlags:8;	/* BDE Flags 0 IS A */
1744 							/* SUPPORTED VALUE !! */
1745 			uint32_t	bdeSize:24;	/* buff size in bytes */
1746 #endif
1747 #ifdef EMLXS_LITTLE_ENDIAN
1748 			uint32_t	bdeSize:24;	/* buff size in bytes */
1749 			uint32_t	bdeFlags:8;	/* BDE Flags 0 IS A */
1750 							/* SUPPORTED VALUE !! */
1751 #endif
1752 #define	BUFF_USE_RSVD		0x01	/* bdeFlags */
1753 #define	BUFF_USE_INTRPT		0x02	/* Not Implemented with LP6000 */
1754 #define	BUFF_USE_CMND		0x04	/* Optional, 1=cmd/rsp 0=data buffer */
1755 #define	BUFF_USE_RCV		0x08	/* ""  "", 1=rcv buffer, */
1756 					/* 0=xmit buffer */
1757 #define	BUFF_TYPE_32BIT		0x10	/* ""  "", 1=32 bit addr */
1758 					/* 0=64 bit addr */
1759 #define	BUFF_TYPE_SPECIAL	0x20	/* Not Implemented with LP6000  */
1760 #define	BUFF_TYPE_BDL		0x40	/* Optional,  may be set in BDL */
1761 #define	BUFF_TYPE_INVALID	0x80	/* ""  "" */
1762 		} f;
1763 	} tus;
1764 	uint32_t	addrLow;
1765 	uint32_t	addrHigh;
1766 } ULP_BDE64;
1767 
1768 #define	BDE64_SIZE_WORD	0
1769 #define	BPL64_SIZE_WORD	0x40
1770 
1771 /*  ULP  */
1772 typedef struct ULP_BPL_64
1773 {
1774 	ULP_BDE64	fccmd_payload;
1775 	ULP_BDE64	fcrsp_payload;
1776 	ULP_BDE64	fcdat_payload;
1777 	ULP_BDE64	pat0;
1778 } ULP_BPL64;
1779 
1780 typedef struct ULP_BDL
1781 { /* SLI-2 */
1782 #ifdef EMLXS_BIG_ENDIAN
1783 	uint32_t	bdeFlags:8;	/* BDL Flags */
1784 	uint32_t	bdeSize:24;	/* Size of BDL array in host */
1785 					/* memory (bytes) */
1786 #endif
1787 #ifdef EMLXS_LITTLE_ENDIAN
1788 	uint32_t	bdeSize:24;	/* Size of BDL array in host */
1789 					/* memory (bytes) */
1790 	uint32_t	bdeFlags:8;	/* BDL Flags */
1791 #endif
1792 	uint32_t	addrLow;	/* Address 0:31 */
1793 	uint32_t	addrHigh;	/* Address 32:63 */
1794 	uint32_t	ulpIoTag32;	/* Can be used for 32 bit I/O Tag */
1795 } ULP_BDL;
1796 
1797 typedef struct ULP_SGE_64
1798 { /* SLI-4 */
1799 	uint32_t	addrHigh;	/* Address 32:63 */
1800 	uint32_t	addrLow;	/* Address 0:31 */
1801 #ifdef EMLXS_BIG_ENDIAN
1802 	uint32_t	last:1;		/* Last entry in SGL */
1803 	uint32_t	reserved:11;
1804 	uint32_t	offset:20;
1805 #endif
1806 #ifdef EMLXS_LITTLE_ENDIAN
1807 	uint32_t	offset:20;
1808 	uint32_t	reserved:11;
1809 	uint32_t	last:1;		/* Last entry in SGL */
1810 #endif
1811 	uint32_t	length;
1812 #define	EMLXS_MAX_SGE_SIZE	0x10000	/* 64K max length */
1813 } ULP_SGE64;
1814 
1815 
1816 typedef	struct _BE_PHYS_ADDR
1817 {
1818 	uint32_t	addrLow;
1819 	uint32_t	addrHigh;
1820 } BE_PHYS_ADDR;
1821 
1822 
1823 typedef struct
1824 {
1825 	uint8_t		*fc_mptr;
1826 	struct emlxs_memseg *segment;	/* Parent segment */
1827 
1828 	uint8_t		*virt;		/* virtual address ptr */
1829 	uint64_t	phys;		/* mapped address */
1830 	uint32_t	size;
1831 
1832 	void		*data_handle;
1833 	void		*dma_handle;
1834 	uint32_t	tag;
1835 	uint32_t	flag;
1836 #define	MAP_POOL_ALLOCATED	0x00000001
1837 #define	MAP_BUF_ALLOCATED	0x00000002
1838 #define	MAP_TABLE_ALLOCATED	0x00000004
1839 } MATCHMAP;
1840 
1841 
1842 /*
1843  * This file defines the Header File for the FDMI HBA Management Service
1844  */
1845 
1846 /*
1847  * FDMI HBA MAnagement Operations Command Codes
1848  */
1849 #define	SLI_MGMT_GRHL	0x100	/* Get registered HBA list */
1850 #define	SLI_MGMT_GHAT	0x101	/* Get HBA attributes */
1851 #define	SLI_MGMT_GRPL	0x102	/* Get registered Port list */
1852 #define	SLI_MGMT_GPAT	0x110	/* Get Port attributes */
1853 #define	SLI_MGMT_RHBA	0x200	/* Register HBA */
1854 #define	SLI_MGMT_RHAT	0x201	/* Register HBA atttributes */
1855 #define	SLI_MGMT_RPRT	0x210	/* Register Port */
1856 #define	SLI_MGMT_RPA	0x211	/* Register Port attributes */
1857 #define	SLI_MGMT_DHBA	0x300	/* De-register HBA */
1858 #define	SLI_MGMT_DPRT	0x310	/* De-register Port */
1859 
1860 /*
1861  * Management Service Subtypes
1862  */
1863 #define	SLI_CT_FDMI_SUBTYPES	0x10
1864 
1865 
1866 /*
1867  * HBA Management Service Reject Code
1868  */
1869 #define	REJECT_CODE		0x9	/* Unable to perform command request */
1870 
1871 /*
1872  * HBA Management Service Reject Reason Code
1873  * Please refer to the Reason Codes above
1874  */
1875 
1876 /*
1877  * HBA Attribute Types
1878  */
1879 #define	NODE_NAME		0x1
1880 #define	MANUFACTURER		0x2
1881 #define	SERIAL_NUMBER		0x3
1882 #define	MODEL			0x4
1883 #define	MODEL_DESCRIPTION	0x5
1884 #define	HARDWARE_VERSION	0x6
1885 #define	DRIVER_VERSION		0x7
1886 #define	OPTION_ROM_VERSION	0x8
1887 #define	FIRMWARE_VERSION	0x9
1888 #define	VENDOR_SPECIFIC		0xa
1889 #define	DRV_NAME		0xb
1890 #define	OS_NAME_VERSION		0xc
1891 #define	MAX_CT_PAYLOAD_LEN	0xd
1892 
1893 /*
1894  * Port Attrubute Types
1895  */
1896 #define	SUPPORTED_FC4_TYPES	0x1
1897 #define	SUPPORTED_SPEED		0x2
1898 #define	PORT_SPEED		0x3
1899 #define	MAX_FRAME_SIZE		0x4
1900 #define	OS_DEVICE_NAME		0x5
1901 
1902 union AttributesDef
1903 {
1904 	/* Structure is in Big Endian format */
1905 	struct
1906 	{
1907 		uint32_t	AttrType:16;
1908 		uint32_t	AttrLen:16;
1909 	} bits;
1910 	uint32_t	word;
1911 };
1912 
1913 /*
1914  * HBA Attribute Entry (8 - 260 bytes)
1915  */
1916 typedef struct
1917 {
1918 	union AttributesDef	ad;
1919 	union
1920 	{
1921 		uint32_t	VendorSpecific;
1922 		uint32_t	SupportSpeed;
1923 		uint32_t	PortSpeed;
1924 		uint32_t	MaxFrameSize;
1925 		uint32_t	MaxCTPayloadLen;
1926 		uint8_t		SupportFC4Types[32];
1927 		uint8_t		OsDeviceName[256];
1928 		uint8_t		Manufacturer[64];
1929 		uint8_t		SerialNumber[64];
1930 		uint8_t		Model[256];
1931 		uint8_t		ModelDescription[256];
1932 		uint8_t		HardwareVersion[256];
1933 		uint8_t		DriverVersion[256];
1934 		uint8_t		OptionROMVersion[256];
1935 		uint8_t		FirmwareVersion[256];
1936 		uint8_t		DriverName[256];
1937 		NAME_TYPE	NodeName;
1938 	} un;
1939 } ATTRIBUTE_ENTRY, *PATTRIBUTE_ENTRY;
1940 
1941 
1942 /*
1943  * HBA Attribute Block
1944  */
1945 typedef struct
1946 {
1947 	uint32_t	EntryCnt;	/* Number of HBA attribute entries */
1948 	ATTRIBUTE_ENTRY	Entry;		/* Variable-length array */
1949 } ATTRIBUTE_BLOCK, *PATTRIBUTE_BLOCK;
1950 
1951 
1952 /*
1953  * Port Entry
1954  */
1955 typedef struct
1956 {
1957 	NAME_TYPE	PortName;
1958 } PORT_ENTRY, *PPORT_ENTRY;
1959 
1960 /*
1961  * HBA Identifier
1962  */
1963 typedef struct
1964 {
1965 	NAME_TYPE	PortName;
1966 } HBA_IDENTIFIER, *PHBA_IDENTIFIER;
1967 
1968 /*
1969  * Registered Port List Format
1970  */
1971 typedef struct
1972 {
1973 	uint32_t	EntryCnt;
1974 	PORT_ENTRY	pe;	/* Variable-length array */
1975 } REG_PORT_LIST, *PREG_PORT_LIST;
1976 
1977 /*
1978  * Register HBA(RHBA)
1979  */
1980 typedef struct
1981 {
1982 	HBA_IDENTIFIER	hi;
1983 	REG_PORT_LIST	rpl;	/* variable-length array */
1984 } REG_HBA, *PREG_HBA;
1985 
1986 /*
1987  * Register HBA Attributes (RHAT)
1988  */
1989 typedef struct
1990 {
1991 	NAME_TYPE	HBA_PortName;
1992 	ATTRIBUTE_BLOCK	ab;
1993 } REG_HBA_ATTRIBUTE, *PREG_HBA_ATTRIBUTE;
1994 
1995 /*
1996  * Register Port Attributes (RPA)
1997  */
1998 typedef struct
1999 {
2000 	NAME_TYPE	HBA_PortName;
2001 	NAME_TYPE	PortName;
2002 	ATTRIBUTE_BLOCK	ab;
2003 } REG_PORT_ATTRIBUTE, *PREG_PORT_ATTRIBUTE;
2004 
2005 /*
2006  * Get Registered HBA List (GRHL) Accept Payload Format
2007  */
2008 typedef struct
2009 {
2010 	uint32_t	HBA__Entry_Cnt;	/* Number of Registered HBA Ids */
2011 	NAME_TYPE	HBA_PortName;	/* Variable-length array */
2012 } GRHL_ACC_PAYLOAD, *PGRHL_ACC_PAYLOAD;
2013 
2014 /*
2015  * Get Registered Port List (GRPL) Accept Payload Format
2016  */
2017 typedef struct
2018 {
2019 	uint32_t	RPL_Entry_Cnt;		/* No of Reg Port Entries */
2020 	PORT_ENTRY	eg_Port_Entry[1];	/* Variable-length array */
2021 } GRPL_ACC_PAYLOAD, *PGRPL_ACC_PAYLOAD;
2022 
2023 /*
2024  * Get Port Attributes (GPAT) Accept Payload Format
2025  */
2026 
2027 typedef struct
2028 {
2029 	ATTRIBUTE_BLOCK	pab;
2030 } GPAT_ACC_PAYLOAD, *PGPAT_ACC_PAYLOAD;
2031 
2032 /*
2033  * Use for Firmware DownLoad
2034  */
2035 
2036 /* download.h */
2037 
2038 #define	REDUCED_SRAM_CFG	0x7FFFC	/* 9802DC */
2039 #define	FULL_SRAM_CFG		0x13FFFC	/* 9802   */
2040 
2041 #define	SLI_FW_TYPE_SHIFT(x) ((x << 20))
2042 #define	SLI_FW_ADAPTER_TYPE_MASK   0x00f00000
2043 #define	SLI_FW_TYPE_6000  SLI_FW_TYPE_SHIFT(0)
2044 #define	SLI_FW_TYPE_7000  SLI_FW_TYPE_SHIFT(1)
2045 #define	SLI_FW_TYPE_8000  SLI_FW_TYPE_SHIFT(2)
2046 #define	SLI_FW_TYPE_850   SLI_FW_TYPE_SHIFT(3)
2047 #define	SLI_FW_TYPE_9000  SLI_FW_TYPE_SHIFT(4)
2048 #define	SLI_FW_TYPE_950   SLI_FW_TYPE_SHIFT(5)
2049 #define	SLI_FW_TYPE_9802  SLI_FW_TYPE_SHIFT(6)	/* [022702] */
2050 #define	SLI_FW_TYPE_982   SLI_FW_TYPE_SHIFT(7)
2051 #define	SLI_FW_TYPE_10000 SLI_FW_TYPE_SHIFT(8)
2052 #define	SLI_FW_TYPE_1050  SLI_FW_TYPE_SHIFT(9)
2053 #define	SLI_FW_TYPE_X1000 SLI_FW_TYPE_SHIFT(0xa)
2054 #define	SLI_FW_TYPE_101   SLI_FW_TYPE_SHIFT(0xb)	/* LP101 */
2055 
2056 
2057 enum emlxs_prog_type
2058 {
2059 	TEST_PROGRAM,	/* 0 */
2060 	UTIL_PROGRAM,	/* 1 */
2061 	FUNC_FIRMWARE,	/* 2 */
2062 	BOOT_BIOS,	/* 3 */
2063 	CONFIG_DATA,	/* 4 */
2064 	SEQUENCER_CODE,	/* 5 */
2065 	SLI1_OVERLAY,	/* 6 */
2066 	SLI2_OVERLAY,	/* 7 */
2067 	GASKET,		/* 8 */
2068 	HARDWARE_IMAGE,	/* 9 */
2069 	SBUS_FCODE,	/* A */
2070 	SLI3_OVERLAY,	/* B */
2071 	RESERVED_C,
2072 	RESERVED_D,
2073 	SLI4_OVERLAY,	/* E */
2074 	KERNEL_CODE,	/* F */
2075 	MAX_PROG_TYPES
2076 } emlxs_prog_type_t;
2077 
2078 
2079 typedef struct emlxs_fw_file
2080 {
2081 	uint32_t	version;
2082 	uint32_t	revcomp;
2083 	char		label[16];
2084 	uint32_t	offset;
2085 } emlxs_fw_file_t;
2086 
2087 typedef struct emlxs_fw_image
2088 {
2089 	emlxs_fw_file_t awc;
2090 	emlxs_fw_file_t bwc;
2091 	emlxs_fw_file_t dwc;
2092 	emlxs_fw_file_t prog[MAX_PROG_TYPES];
2093 } emlxs_fw_image_t;
2094 
2095 
2096 
2097 #define	NOP_IMAGE_TYPE		0xe1a00000
2098 
2099 #define	FLASH_BASE_ADR		0x01400000
2100 #define	DL_FROM_SLIM_OFFSET	MBOX_EXTENSION_OFFSET
2101 
2102 #ifdef MBOX_EXT_SUPPORT
2103 #define	DL_SLIM_SEG_BYTE_COUNT	MBOX_EXTENSION_SIZE
2104 #else
2105 #define	DL_SLIM_SEG_BYTE_COUNT	128
2106 #endif /* MBOX_EXT_SUPPORT */
2107 
2108 #define	SLI_CKSUM_LENGTH	4
2109 #define	SLI_CKSUM_SEED		0x55555555
2110 #define	SLI_CKSUM_ERR		0x1982abcd
2111 
2112 #define	AIF_NOOP		0xe1a00000
2113 #define	AIF_BLAL		0xeb000000
2114 #define	OS_EXIT			0xef000011
2115 #define	OS_GETENV		0xef000010
2116 #define	AIF_IMAGEBASE		0x00008000
2117 #define	AIF_BLZINIT		0xeb00000c
2118 #define	DEBUG_TASK		0xef041d41
2119 #define	AIF_DBG_SRC		2
2120 #define	AIF_DBG_LL		1
2121 #define	AIF_DATABASAT		0x100
2122 
2123 #define	JEDEC_ID_ADDRESS	0x0080001c
2124 #define	MAX_RBUS_SRAM_SIZE_ADR	0x788
2125 #define	MAX_IBUS_SRAM_SIZE_ADR	0x78c
2126 #define	FULL_RBUS_SRAM_CFG	0x7fffc
2127 #define	FULL_IBUS_SRAM_CFG	0x187fffc
2128 #define	REDUCED_RBUS_SRAM_CFG	0x5fffc
2129 #define	REDUCED_IBUS_SRAM_CFG	0x183fffc
2130 
2131 #define	FULL_SRAM_CFG_PROG_ID		1
2132 #define	REDUCED_SRAM_CFG_PROG_ID	2
2133 #define	OTHER_SRAM_CFG_PROG_ID		3
2134 
2135 #define	NO_FLASH_MEM_AVAIL	0xf1
2136 
2137 #define	PROG_TYPE_MASK		0xff000000
2138 #define	PROG_TYPE_SHIFT		24
2139 
2140 #define	FLASH_LOAD_LIST_ADR	0x79c
2141 #define	RAM_LOAD_ENTRY_SIZE	9
2142 #define	FLASH_LOAD_ENTRY_SIZE	6
2143 #define	RAM_LOAD_ENTRY_TYPE	0
2144 #define	FLASH_LOAD_ENTRY_TYPE	1
2145 
2146 #define	CFG_DATA_NO_REGION	-3
2147 
2148 #define	SLI_IMAGE_START		0x20080
2149 #define	SLI_VERSION_LOC		0x270
2150 
2151 
2152 #define	SLI_HW_REVISION_CHECK(x, y)	((x & 0xf0) == y)
2153 #define	SLI_FCODE_REVISION_CHECK(x, y)	(x == y)
2154 
2155 
2156 /* ************ Tigershark ************** */
2157 #define	BE_SIGNATURE_SIZE	32
2158 #define	BE_BUILD_SIZE		24
2159 #define	BE_SIGNATURE		"ServerEngines Corp"
2160 #define	BE_DIR_SIGNATURE	"*** SE FLAS"
2161 #define	BE_VERSION_SIZE		32
2162 #define	BE_COOKIE_SIZE		32
2163 #define	BE_CONTROLLER_SIZE	8
2164 #define	BE_FLASH_ENTRIES	32
2165 #define	BE_MAX_XFER_SIZE	32768 /* 4K aligned */
2166 
2167 typedef struct emlxs_sli4_ufi_controller
2168 {
2169 	uint32_t vendor_id;
2170 	uint32_t device_id;
2171 	uint32_t sub_vendor_id;
2172 	uint32_t sub_device_id;
2173 
2174 } emlxs_sli4_ufi_controller_t;
2175 
2176 typedef struct emlxs_sli4_ufi_header /* 96 bytes */
2177 {
2178 	char signature[BE_SIGNATURE_SIZE];
2179 	uint32_t checksum;
2180 	uint32_t antidote;
2181 	emlxs_sli4_ufi_controller_t  controller;
2182 	uint32_t file_length;
2183 	uint32_t chunk_num;
2184 	uint32_t chunk_cnt;
2185 	uint32_t image_cnt;
2186 	char build[BE_BUILD_SIZE];
2187 
2188 } emlxs_sli4_ufi_header_t;
2189 
2190 typedef struct emlxs_sli4_flash_header
2191 {
2192 	uint32_t format_rev;
2193 	uint32_t checksum;
2194 	uint32_t antidote;
2195 	uint32_t build_num;
2196 	emlxs_sli4_ufi_controller_t  controller[BE_CONTROLLER_SIZE];
2197 	uint32_t active_entry_mask;
2198 	uint32_t valid_entry_mask;
2199 	uint32_t orig_content_mask;
2200 	uint32_t resv0;
2201 	uint32_t resv1;
2202 	uint32_t resv2;
2203 	uint32_t resv3;
2204 	uint32_t resv4;
2205 
2206 } emlxs_sli4_flash_header_t;
2207 
2208 typedef struct emlxs_sli4_flash_entry
2209 {
2210 	uint32_t type;
2211 	uint32_t offset;
2212 	uint32_t pad_size;
2213 	uint32_t image_size;
2214 	uint32_t checksum;
2215 	uint32_t entry_point;
2216 	uint32_t resv0;
2217 	uint32_t resv1;
2218 	char version[BE_VERSION_SIZE];
2219 
2220 } emlxs_sli4_flash_entry_t;
2221 
2222 typedef struct emlxs_sli4_flash_dir
2223 {
2224 	char cookie[BE_COOKIE_SIZE];
2225 	emlxs_sli4_flash_header_t header;
2226 	emlxs_sli4_flash_entry_t entry[BE_FLASH_ENTRIES];
2227 
2228 } emlxs_sli4_flash_dir_t;
2229 
2230 
2231 /* FLASH ENTRY TYPES */
2232 #define	BE_FLASHTYPE_PXE_BIOS		0x20
2233 #define	BE_FLASHTYPE_FCOE_BIOS		0x21
2234 #define	BE_FLASHTYPE_ISCSI_BIOS		0x22
2235 #define	BE_FLASHTYPE_ISCSI_FIRMWARE	0xA0
2236 #define	BE_FLASHTYPE_ISCSI_BACKUP	0xB0
2237 #define	BE_FLASHTYPE_FCOE_FIRMWARE	0xA2
2238 #define	BE_FLASHTYPE_FCOE_BACKUP	0xB2
2239 #define	BE_FLASHTYPE_REDBOOT		0xE0
2240 
2241 /* Flash types in download order */
2242 typedef enum emlxs_be_flashtypes
2243 {
2244 	ISCSI_FIRMWARE_FLASHTYPE,
2245 	ISCSI_BACKUP_FLASHTYPE,
2246 	FCOE_FIRMWARE_FLASHTYPE,
2247 	FCOE_BACKUP_FLASHTYPE,
2248 	ISCSI_BIOS_FLASHTYPE,
2249 	FCOE_BIOS_FLASHTYPE,
2250 	PXE_BIOS_FLASHTYPE,
2251 	REDBOOT_FLASHTYPE,
2252 	BE_MAX_FLASHTYPES
2253 
2254 } emlxs_be_flashtypes_t;
2255 
2256 /* Driver level constructs */
2257 typedef struct emlxs_be_fw_file
2258 {
2259 	uint32_t	type;
2260 	uint32_t	image_offset;
2261 	uint32_t	image_size;
2262 	uint32_t	block_size;
2263 	uint32_t	block_crc;
2264 	uint32_t	load_address;
2265 	char		label[BE_VERSION_SIZE];
2266 } emlxs_be_fw_file_t;
2267 
2268 typedef struct emlxs_be_fw_image
2269 {
2270 	uint32_t version;
2271 	char label[BE_VERSION_SIZE];
2272 
2273 	emlxs_be_fw_file_t file[BE_MAX_FLASHTYPES];
2274 } emlxs_be_fw_image_t;
2275 
2276 
2277 #ifdef	__cplusplus
2278 }
2279 #endif
2280 
2281 #endif	/* _EMLXS_HW_H */
2282