1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to License terms. 25 */ 26 27 28 #ifndef _EMLXS_HW_H 29 #define _EMLXS_HW_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #ifdef NPIV_SUPPORT 36 #define MAX_VPORTS 256 /* Max virtual ports per HBA */ 37 /* (includes physical port) */ 38 #define MAX_VPORTS_LIMITED 101 39 #else 40 #define MAX_VPORTS 1 /* Max virtual ports per HBA */ 41 /* (includes physical port) */ 42 #define MAX_VPORTS_LIMITED 1 43 #endif /* NPIV_SUPPORT */ 44 45 46 #define FC_MAX_TRANSFER 0x40000 /* Max transfer size per */ 47 /* operation */ 48 49 #define MAX_RINGS_AVAILABLE 4 /* # rings available */ 50 #define MAX_RINGS 4 /* Max # rings used */ 51 52 53 #define PCB_SIZE 128 54 #define MBOX_SIZE 256 55 #define MBOX_EXTENSION_OFFSET MBOX_SIZE 56 57 58 #ifdef MBOX_EXT_SUPPORT 59 #define MBOX_EXTENSION_SIZE 1024 60 #else 61 #define MBOX_EXTENSION_SIZE 0 62 #endif /* MBOX_EXT_SUPPORT */ 63 64 65 #define SLIM_IOCB_CMD_R0_ENTRIES 128 /* SLI FCP cmd ring entries */ 66 #define SLIM_IOCB_RSP_R0_ENTRIES 128 /* SLI FCP rsp ring entries */ 67 #define SLIM_IOCB_CMD_R1_ENTRIES 32 /* SLI IP cmd ring entries */ 68 #define SLIM_IOCB_RSP_R1_ENTRIES 32 /* SLI IP rsp ring entries */ 69 #define SLIM_IOCB_CMD_R2_ENTRIES 16 /* SLI ELS cmd ring entries */ 70 #define SLIM_IOCB_RSP_R2_ENTRIES 16 /* SLI ELS rspe ring entries */ 71 #define SLIM_IOCB_CMD_R3_ENTRIES 8 /* SLI CT cmd ring entries */ 72 #define SLIM_IOCB_RSP_R3_ENTRIES 8 /* SLI CT rsp ring entries */ 73 74 /* 75 * Total: 184 Cmd's + 184 Rsp's = 368 76 * Command and response entry counts are not required to be equal 77 */ 78 79 #define SLIM_IOCB_CMD_ENTRIES (SLIM_IOCB_CMD_R0_ENTRIES + \ 80 SLIM_IOCB_CMD_R1_ENTRIES + \ 81 SLIM_IOCB_CMD_R2_ENTRIES + \ 82 SLIM_IOCB_CMD_R3_ENTRIES) 83 84 #define SLIM_IOCB_RSP_ENTRIES (SLIM_IOCB_RSP_R0_ENTRIES + \ 85 SLIM_IOCB_RSP_R1_ENTRIES + \ 86 SLIM_IOCB_RSP_R2_ENTRIES + \ 87 SLIM_IOCB_RSP_R3_ENTRIES) 88 89 #define SLIM_IOCB_ENTRIES (SLIM_IOCB_CMD_ENTRIES + \ 90 SLIM_IOCB_RSP_ENTRIES) 91 92 93 /* SLI1 Definitions */ 94 #define SLI_SLIM1_SIZE 4096 /* Fixed size memory */ 95 96 97 /* SLI2 Definitions */ 98 #define SLI2_IOCB_CMD_SIZE 32 99 #define SLI2_IOCB_RSP_SIZE 32 100 #define SLI2_IOCB_MAX_SIZE ((SLI2_IOCB_CMD_SIZE * \ 101 SLIM_IOCB_CMD_ENTRIES) + \ 102 (SLI2_IOCB_RSP_SIZE * \ 103 SLIM_IOCB_RSP_ENTRIES)) 104 #define SLI2_SLIM2_SIZE (MBOX_SIZE + MBOX_EXTENSION_SIZE + \ 105 PCB_SIZE + SLI2_IOCB_MAX_SIZE) 106 107 108 /* SLI3 Definitions */ 109 #define SLI3_MAX_BDE 7 110 #define SLI3_IOCB_CMD_SIZE 128 111 #define SLI3_IOCB_RSP_SIZE 64 112 #define SLI3_IOCB_MAX_SIZE ((SLI3_IOCB_CMD_SIZE * \ 113 SLIM_IOCB_CMD_ENTRIES) + \ 114 (SLI3_IOCB_RSP_SIZE * \ 115 SLIM_IOCB_RSP_ENTRIES)) 116 #define SLI3_SLIM2_SIZE (MBOX_SIZE + MBOX_EXTENSION_SIZE + \ 117 PCB_SIZE + SLI3_IOCB_MAX_SIZE) 118 119 120 #ifdef SLI3_SUPPORT 121 #define SLI_SLIM2_SIZE SLI3_SLIM2_SIZE 122 #define SLI_IOCB_MAX_SIZE SLI3_IOCB_MAX_SIZE 123 #else /* SLI2_SUPPORT */ 124 #define SLI_SLIM2_SIZE SLI2_SLIM2_SIZE 125 #define SLI_IOCB_MAX_SIZE SLI2_IOCB_MAX_SIZE 126 #endif /* SLI3_SUPPORT */ 127 128 129 130 #define FC_MAXRETRY 3 /* max retries for ELS commands */ 131 #define FC_FCP_RING 0 /* use ring 0 for FCP initiator cmds */ 132 #define FC_FCT_RING 0 /* use ring 0 for FCP target cmds */ 133 134 #define FC_IP_RING 1 /* use ring 1 for IP commands */ 135 #define FC_ELS_RING 2 /* use ring 2 for ELS commands */ 136 #define FC_CT_RING 3 /* use ring 3 for CT commands */ 137 138 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 139 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 140 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 141 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 142 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG */ 143 /* iocb */ 144 #define FF_REG_AREA_SIZE 256 /* size, in bytes, of i/o register */ 145 /* area */ 146 147 /* 148 * Miscellaneous stuff.... 149 */ 150 /* HBA Mgmt */ 151 #define FDMI_DID ((uint32_t)0xfffffa) 152 #define NameServer_DID ((uint32_t)0xfffffc) 153 #define SCR_DID ((uint32_t)0xfffffd) 154 #define Fabric_DID ((uint32_t)0xfffffe) 155 #define Bcast_DID ((uint32_t)0xffffff) 156 #define Mask_DID ((uint32_t)0xffffff) 157 #define CT_DID_MASK ((uint32_t)0xffff00) 158 #define Fabric_DID_MASK ((uint32_t)0xfff000) 159 #define WELL_KNOWN_DID_MASK ((uint32_t)0xfffff0) 160 161 #define EMLXS_MENLO_DID ((uint32_t)0x00fc0e) 162 163 164 #define PT2PT_LocalID ((uint32_t)1) 165 #define PT2PT_RemoteID ((uint32_t)2) 166 167 #define OWN_CHIP 1 /* IOCB / Mailbox is owned by FireFly */ 168 #define OWN_HOST 0 /* IOCB / Mailbox is owned by Host */ 169 #define END_OF_CHAIN 0 170 171 172 173 /* defines for type field in fc header */ 174 #define FC_ELS_DATA 0x01 175 #define FC_LLC_SNAP 0x05 176 #define FC_FCP_DATA 0x08 177 #define FC_CT_TYPE 0x20 178 #define EMLXS_MENLO_TYPE 0xFE 179 180 181 /* defines for rctl field in fc header */ 182 #define FC_DEV_DATA 0x0 183 #define FC_UNSOL_CTL 0x2 184 #define FC_SOL_CTL 0x3 185 #define FC_UNSOL_DATA 0x4 186 #define FC_FCP_CMND 0x6 187 #define FC_ELS_REQ 0x22 188 #define FC_ELS_RSP 0x23 189 #define FC_NET_HDR 0x20 /* network headers for Dfctl field */ 190 191 /* 192 * Common Transport structures and definitions 193 * 194 */ 195 #define EMLXS_COMMAND 0 196 #define EMLXS_RESPONSE 1 197 198 typedef union CtRevisionId 199 { 200 /* Structure is in Big Endian format */ 201 struct 202 { 203 uint32_t Revision:8; 204 uint32_t InId:24; 205 } bits; 206 uint32_t word; 207 } CtRevisionId_t; 208 209 typedef union CtCommandResponse 210 { 211 /* Structure is in Big Endian format */ 212 struct 213 { 214 uint32_t CmdRsp:16; 215 uint32_t Size:16; 216 } bits; 217 uint32_t word; 218 } CtCommandResponse_t; 219 220 typedef struct SliCtRequest 221 { 222 /* Structure is in Big Endian format */ 223 CtRevisionId_t RevisionId; 224 uint8_t FsType; 225 uint8_t FsSubType; 226 uint8_t Options; 227 uint8_t Rsrvd1; 228 CtCommandResponse_t CommandResponse; 229 uint8_t Rsrvd2; 230 uint8_t ReasonCode; 231 uint8_t Explanation; 232 uint8_t VendorUnique; 233 234 union 235 { 236 uint32_t data; 237 uint32_t PortID; 238 239 struct gid 240 { 241 uint8_t PortType; /* for GID_PT requests */ 242 uint8_t DomainScope; 243 uint8_t AreaScope; 244 uint8_t Fc4Type; /* for GID_FT requests */ 245 } gid; 246 struct rft 247 { 248 uint32_t PortId; /* For RFT_ID requests */ 249 #ifdef EMLXS_BIG_ENDIAN 250 uint32_t rsvd0:16; 251 uint32_t rsvd1:7; 252 uint32_t fcpReg:1; /* Type 8 */ 253 uint32_t rsvd2:2; 254 uint32_t ipReg:1; /* Type 5 */ 255 uint32_t rsvd3:5; 256 #endif 257 #ifdef EMLXS_LITTLE_ENDIAN 258 uint32_t rsvd0:16; 259 uint32_t fcpReg:1; /* Type 8 */ 260 uint32_t rsvd1:7; 261 uint32_t rsvd3:5; 262 uint32_t ipReg:1; /* Type 5 */ 263 uint32_t rsvd2:2; 264 #endif 265 uint32_t rsvd[7]; 266 } rft; 267 268 struct rsnn 269 { 270 uint8_t wwnn[8]; 271 uint8_t snn_len; 272 char snn[256]; 273 } rsnn; 274 275 struct rspn 276 { 277 uint32_t PortId; 278 uint8_t spn_len; 279 char spn[256]; 280 } rspn; 281 } un; 282 } SliCtRequest_t; 283 typedef SliCtRequest_t SLI_CT_REQUEST; 284 285 #define SLI_CT_REVISION 1 286 287 288 /* 289 * FsType Definitions 290 */ 291 292 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 293 #define SLI_CT_TIME_SERVICE 0xFB 294 #define SLI_CT_DIRECTORY_SERVICE 0xFC 295 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 296 297 /* 298 * Directory Service Subtypes 299 */ 300 301 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 302 303 /* 304 * Response Codes 305 */ 306 307 #define SLI_CT_RESPONSE_FS_RJT 0x8001 308 #define SLI_CT_RESPONSE_FS_ACC 0x8002 309 310 /* 311 * Reason Codes 312 */ 313 314 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 315 #define SLI_CT_INVALID_COMMAND 0x01 316 #define SLI_CT_INVALID_VERSION 0x02 317 #define SLI_CT_LOGICAL_ERROR 0x03 318 #define SLI_CT_INVALID_IU_SIZE 0x04 319 #define SLI_CT_LOGICAL_BUSY 0x05 320 #define SLI_CT_PROTOCOL_ERROR 0x07 321 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 322 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 323 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 324 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 325 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 326 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 327 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 328 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 329 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 330 #define SLI_CT_VENDOR_UNIQUE 0xff 331 332 /* 333 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 334 */ 335 336 #define SLI_CT_NO_PORT_ID 0x01 337 #define SLI_CT_NO_PORT_NAME 0x02 338 #define SLI_CT_NO_NODE_NAME 0x03 339 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 340 #define SLI_CT_NO_IP_ADDRESS 0x05 341 #define SLI_CT_NO_IPA 0x06 342 #define SLI_CT_NO_FC4_TYPES 0x07 343 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 344 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 345 #define SLI_CT_NO_PORT_TYPE 0x0A 346 #define SLI_CT_ACCESS_DENIED 0x10 347 #define SLI_CT_INVALID_PORT_ID 0x11 348 #define SLI_CT_DATABASE_EMPTY 0x12 349 350 #ifdef EMLXS_BIG_ENDIAN 351 #define CT_CMD_MASK 0xffff0000 352 #endif 353 354 #ifdef EMLXS_LITTLE_ENDIAN 355 #define CT_CMD_MASK 0xffff 356 #endif 357 358 /* 359 * Management Server Interface Command Codes 360 */ 361 362 #define MS_GTIN 0x0100 363 #define MS_GIEL 0x0101 364 #define MS_GIET 0x0111 365 #define MS_GDID 0x0112 366 #define MS_GMID 0x0113 367 #define MS_GFN 0x0114 368 #define MS_GIELN 0x0115 369 #define MS_GMAL 0x0116 370 #define MS_GIEIL 0x0117 371 #define MS_GPL 0x0118 372 #define MS_GPT 0x0121 373 #define MS_GPPN 0x0122 374 #define MS_GAPNL 0x0124 375 #define MS_GPS 0x0126 376 #define MS_GPSC 0x0127 377 #define MS_GATIN 0x0128 378 #define MS_GSES 0x0130 379 #define MS_GPLNL 0x0191 380 #define MS_GPLT 0x0192 381 #define MS_GPLML 0x0193 382 #define MS_GPAB 0x0197 383 #define MS_GNPL 0x01A1 384 #define MS_GPNL 0x01A2 385 #define MS_GPFCP 0x01A4 386 #define MS_GPLI 0x01A5 387 #define MS_GNID 0x01B1 388 #define MS_RIELN 0x0215 389 #define MS_RPL 0x0280 390 #define MS_RPLN 0x0291 391 #define MS_RPLT 0x0292 392 #define MS_RPLM 0x0293 393 #define MS_RPAB 0x0298 394 #define MS_RPFCP 0x029A 395 #define MS_RPLI 0x029B 396 #define MS_DPL 0x0380 397 #define MS_DPLN 0x0391 398 #define MS_DPLM 0x0392 399 #define MS_DPLML 0x0393 400 #define MS_DPLI 0x0394 401 #define MS_DPAB 0x0395 402 #define MS_DPALL 0x039F 403 404 405 /* 406 * Name Server Command Codes 407 */ 408 #define SLI_CTNS_GA_NXT 0x0100 409 #define SLI_CTNS_GPN_ID 0x0112 410 #define SLI_CTNS_GNN_ID 0x0113 411 #define SLI_CTNS_GCS_ID 0x0114 412 #define SLI_CTNS_GFT_ID 0x0117 413 #define SLI_CTNS_GSPN_ID 0x0118 414 #define SLI_CTNS_GPT_ID 0x011A 415 #define SLI_CTNS_GID_PN 0x0121 416 #define SLI_CTNS_GID_NN 0x0131 417 #define SLI_CTNS_GIP_NN 0x0135 418 #define SLI_CTNS_GIPA_NN 0x0136 419 #define SLI_CTNS_GSNN_NN 0x0139 420 #define SLI_CTNS_GNN_IP 0x0153 421 #define SLI_CTNS_GIPA_IP 0x0156 422 #define SLI_CTNS_GID_FT 0x0171 423 #define SLI_CTNS_GID_PT 0x01A1 424 #define SLI_CTNS_RPN_ID 0x0212 425 #define SLI_CTNS_RNN_ID 0x0213 426 #define SLI_CTNS_RCS_ID 0x0214 427 #define SLI_CTNS_RFT_ID 0x0217 428 #define SLI_CTNS_RSPN_ID 0x0218 429 #define SLI_CTNS_RPT_ID 0x021A 430 #define SLI_CTNS_RIP_NN 0x0235 431 #define SLI_CTNS_RIPA_NN 0x0236 432 #define SLI_CTNS_RSNN_NN 0x0239 433 #define SLI_CTNS_DA_ID 0x0300 434 435 #define SLI_CT_LOOPBACK 0xFCFC 436 437 438 /* 439 * Port Types 440 */ 441 442 #define SLI_CTPT_N_PORT 0x01 443 #define SLI_CTPT_NL_PORT 0x02 444 #define SLI_CTPT_FNL_PORT 0x03 445 #define SLI_CTPT_IP 0x04 446 #define SLI_CTPT_FCP 0x08 447 #define SLI_CTPT_NX_PORT 0x7F 448 #define SLI_CTPT_F_PORT 0x81 449 #define SLI_CTPT_FL_PORT 0x82 450 #define SLI_CTPT_E_PORT 0x84 451 452 #define SLI_CT_LAST_ENTRY 0x80000000 453 454 /* ===================================================================== */ 455 456 /* 457 * Start FireFly Register definitions 458 */ 459 460 /* PCI register offsets */ 461 #define MEM_ADDR_OFFSET 0x10 /* SLIM base memory address */ 462 #define MEMH_OFFSET 0x14 /* SLIM base memory high address */ 463 #define REG_ADDR_OFFSET 0x18 /* REGISTER base memory address */ 464 #define REGH_OFFSET 0x1c /* REGISTER base memory high address */ 465 #define IO_ADDR_OFFSET 0x20 /* BIU I/O registers */ 466 #define REGIOH_OFFSET 0x24 /* REGISTER base io high address */ 467 468 #define CMD_REG_OFFSET 0x4 /* PCI command configuration */ 469 470 /* General PCI Register Definitions */ 471 /* Refer To The PCI Specification For Detailed Explanations */ 472 473 /* Register Offsets in little endian format */ 474 #define PCI_VENDOR_ID_REGISTER 0x00 /* PCI Vendor ID Reg */ 475 #define PCI_DEVICE_ID_REGISTER 0x02 /* PCI Device ID Reg */ 476 #define PCI_CONFIG_ID_REGISTER 0x00 /* PCI Configuration ID Reg */ 477 #define PCI_COMMAND_REGISTER 0x04 /* PCI Command Reg */ 478 #define PCI_STATUS_REGISTER 0x06 /* PCI Status Reg */ 479 #define PCI_REV_ID_REGISTER 0x08 /* PCI Revision ID Reg */ 480 #define PCI_CLASS_CODE_REGISTER 0x09 /* PCI Class Code Reg */ 481 #define PCI_CACHE_LINE_REGISTER 0x0C /* PCI Cache Line Reg */ 482 #define PCI_LATENCY_TMR_REGISTER 0x0D /* PCI Latency Timer Reg */ 483 #define PCI_HEADER_TYPE_REGISTER 0x0E /* PCI Header Type Reg */ 484 #define PCI_BIST_REGISTER 0x0F /* PCI Built-In SelfTest Reg */ 485 #define PCI_BAR_0_REGISTER 0x10 /* PCI Base Address Reg 0 */ 486 #define PCI_BAR_1_REGISTER 0x14 /* PCI Base Address Reg 1 */ 487 #define PCI_BAR_2_REGISTER 0x18 /* PCI Base Address Reg 2 */ 488 #define PCI_BAR_3_REGISTER 0x1C /* PCI Base Address Reg 3 */ 489 #define PCI_BAR_4_REGISTER 0x20 /* PCI Base Address Reg 4 */ 490 #define PCI_BAR_5_REGISTER 0x24 /* PCI Base Address Reg 5 */ 491 #define PCI_SSID_REGISTER 0x2C 492 #define PCI_SSVID_REGISTER 0x2C 493 #define PCI_SSDID_REGISTER 0x2E 494 #define PCI_EXPANSION_ROM 0x30 /* PCI Expansion ROM Base Reg */ 495 #define PCI_CAP_POINTER 0x34 496 #define PCI_INTR_LINE_REGISTER 0x3C /* PCI Interrupt Line Reg */ 497 #define PCI_INTR_PIN_REGISTER 0x3D /* PCI Interrupt Pin Reg */ 498 #define PCI_MIN_GNT_REGISTER 0x3E /* PCI Min-Gnt Reg */ 499 #define PCI_MAX_LAT_REGISTER 0x3F /* PCI Max_Lat Reg */ 500 #define PCI_NODE_ADDR_REGISTER 0x40 /* PCI Node Address Reg */ 501 502 #define PCI_PM_CONTROL_REGISTER 0x50 /* PCI Power Mgmt Control Reg */ 503 504 /* PCIe adapters only */ 505 #define PCIe_MSI_CONTROL_REG0 0x60 /* MSI Control */ 506 #define PCIe_MSI_CONTROL_REG1 0x62 /* MSI Control */ 507 508 /* Power management command states */ 509 #define PCI_PM_D0_STATE 0x00 /* Power up state */ 510 #define PCI_PM_D3_STATE 0x03 /* Power down state */ 511 512 513 /* PCI access methods */ 514 #define P_CONF_T1 1 515 #define P_CONF_T2 2 516 517 /* max number of pci buses */ 518 #define MAX_PCI_BUSES 0xFF 519 520 /* number of PCI config bytes to access */ 521 #define PCI_BYTE 1 522 #define PCI_WORD 2 523 #define PCI_DWORD 4 524 525 /* PCI related constants */ 526 #define CMD_IO_ENBL 0x0001 527 #define CMD_MEM_ENBL 0x0002 528 #define CMD_BUS_MASTER 0x0004 529 #define CMD_MWI 0x0010 530 #define CMD_PARITY_CHK 0x0040 531 #define CMD_SERR_ENBL 0x0100 532 533 #define CMD_CFG_VALUE 0x156 /* mem enable, master, MWI, SERR, PERR */ 534 535 /* PCI addresses */ 536 #define PCI_SPACE_ENABLE 0x0CF8 537 #define CF1_CONFIG_ADDR_REGISTER 0x0CF8 538 #define CF1_CONFIG_DATA_REGISTER 0x0CFC 539 #define CF2_FORWARD_REGISTER 0x0CFA 540 #define CF2_BASE_ADDRESS 0xC000 541 542 543 #define DEFAULT_PCI_LATENCY_CLOCKS 0xf8 /* 0xF8 is a special value */ 544 /* for FF11.1N6 firmware. */ 545 /* Use 0x80 for pre-FF11.1N6 */ 546 /* &N7, etc */ 547 #define PCI_LATENCY_VALUE 0xf8 548 549 550 551 /* ==== Register Bit Definitions ==== */ 552 553 /* Used by SBUS adapter */ 554 /* SBUS Control Register */ 555 #define SBUS_CTRL_REG_OFFSET 0 /* Word offset from reg base addr */ 556 557 #define SBUS_CTRL_SBRST 0x00000001 /* Bit 0 */ 558 #define SBUS_CTRL_BKOFF 0x00000002 /* Bit 1 */ 559 #define SBUS_CTRL_ENP 0x00000004 /* Bit 2 */ 560 #define SBUS_CTRL_EN64 0x00000008 /* Bit 3 */ 561 #define SBUS_CTRL_SIR_1 0x00000010 /* Bit [6:4] IRL 1, */ 562 /* lowset priority */ 563 #define SBUS_CTRL_SIR_2 0x00000020 564 #define SBUS_CTRL_SIR_3 0x00000030 565 #define SBUS_CTRL_SIR_4 0x00000040 566 #define SBUS_CTRL_SIR_5 0x00000050 567 #define SBUS_CTRL_SIR_6 0x00000060 568 #define SBUS_CTRL_SIR_7 0x00000070 /* IRL 7, highest priority */ 569 570 /* SBUS Status Register */ 571 #define SBUS_STAT_REG_OFFSET 1 /* Word offset from reg base addr */ 572 #define SBUS_STAT_IP 0x00000001 /* Bit 0 */ 573 #define SBUS_STAT_LERR 0x00000002 /* Bit 1 */ 574 #define SBUS_STAT_SBPE 0x00000004 /* Bit 2 */ 575 #define SBUS_STAT_TE 0x00000008 /* Bit 3 */ 576 #define SBUS_STAT_WPE 0x00000010 /* Bit 4 */ 577 #define SBUS_STAT_PERR 0x00000020 /* Bit 5 */ 578 #define SBUS_STAT_SERR 0x00000040 /* Bit 6 */ 579 #define SBUS_STAT_PTA 0x00000080 /* Bit 7 */ 580 581 /* SBUS Update Register */ 582 #define SBUS_UPDATE_REG_OFFSET 2 /* Word offfset from reg base addr */ 583 584 #define SBUS_UPDATE_DATA 0x00000001 /* Bit 0 */ 585 #define SBUS_UPDATE_SPCLK 0x00000002 /* Bit 1 */ 586 #define SBUS_UPDATE_SPCE 0x00000004 /* Bit 2 */ 587 #define SBUS_UPDATE_SPRST 0x00000008 /* Bit 3 */ 588 #define SBUS_UPDATE_SPWE 0x00000010 /* Bit 4 */ 589 #define SBUS_UPDATE_LDFPGA 0x00000080 /* Bit 7 */ 590 591 /* Host Attention Register */ 592 593 #define HA_REG_OFFSET 0 /* Word offset from register base address */ 594 595 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 596 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 597 #define HA_R0ATT 0x00000008 /* Bit 3 */ 598 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 599 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 600 #define HA_R1ATT 0x00000080 /* Bit 7 */ 601 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 602 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 603 #define HA_R2ATT 0x00000800 /* Bit 11 */ 604 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 605 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 606 #define HA_R3ATT 0x00008000 /* Bit 15 */ 607 #define HA_LATT 0x20000000 /* Bit 29 */ 608 #define HA_MBATT 0x40000000 /* Bit 30 */ 609 #define HA_ERATT 0x80000000 /* Bit 31 */ 610 611 612 #ifdef MSI_SUPPORT 613 614 /* Host attention interrupt map */ 615 #define EMLXS_MSI_MAP8 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, \ 616 HA_R3ATT, HA_LATT, HA_MBATT, HA_ERATT} 617 #define EMLXS_MSI_MAP4 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, 0, 0, 0, 0} 618 #define EMLXS_MSI_MAP2 {0, HA_R0ATT, 0, 0, 0, 0, 0, 0} 619 #define EMLXS_MSI_MAP1 {0, 0, 0, 0, 0, 0, 0, 0} 620 621 /* MSI 0 interrupt mask */ 622 #define EMLXS_MSI0_MASK8 0 623 #define EMLXS_MSI0_MASK4 (HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \ 624 HC_ERINT_ENA) 625 #define EMLXS_MSI0_MASK2 (HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA| \ 626 HC_MBINT_ENA|HC_LAINT_ENA|HC_ERINT_ENA) 627 #define EMLXS_MSI0_MASK1 (HC_R0INT_ENA|HC_R1INT_ENA|HC_R2INT_ENA| \ 628 HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \ 629 HC_ERINT_ENA) 630 631 632 #define EMLXS_MSI_MAX_INTRS 8 633 634 #define EMLXS_MSI_MODE1 0 635 #define EMLXS_MSI_MODE2 1 636 #define EMLXS_MSI_MODE4 2 637 #define EMLXS_MSI_MODE8 3 638 #define EMLXS_MSI_MODES 4 639 640 #endif /* MSI_SUPPORT */ 641 642 643 #define IO_THROTTLE_RESERVE 12 644 645 646 647 648 /* Chip Attention Register */ 649 650 #define CA_REG_OFFSET 1 /* Word offset from register base address */ 651 652 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 653 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 654 #define CA_R0ATT 0x00000008 /* Bit 3 */ 655 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 656 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 657 #define CA_R1ATT 0x00000080 /* Bit 7 */ 658 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 659 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 660 #define CA_R2ATT 0x00000800 /* Bit 11 */ 661 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 662 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 663 #define CA_R3ATT 0x00008000 /* Bit 15 */ 664 #define CA_MBATT 0x40000000 /* Bit 30 */ 665 666 667 /* Host Status Register */ 668 669 #define HS_REG_OFFSET 2 /* Word offset from register base address */ 670 671 #define HS_OVERTEMP 0x00000100 /* Bit 8 */ 672 #define HS_MBRDY 0x00400000 /* Bit 22 */ 673 #define HS_FFRDY 0x00800000 /* Bit 23 */ 674 #define HS_FFER8 0x01000000 /* Bit 24 */ 675 #define HS_FFER7 0x02000000 /* Bit 25 */ 676 #define HS_FFER6 0x04000000 /* Bit 26 */ 677 #define HS_FFER5 0x08000000 /* Bit 27 */ 678 #define HS_FFER4 0x10000000 /* Bit 28 */ 679 #define HS_FFER3 0x20000000 /* Bit 29 */ 680 #define HS_FFER2 0x40000000 /* Bit 30 */ 681 #define HS_FFER1 0x80000000 /* Bit 31 */ 682 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */ 683 684 /* Host Control Register */ 685 686 #define HC_REG_OFFSET 3 /* Word offset from register base address */ 687 688 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 689 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 690 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 691 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 692 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 693 #define HC_INITHBI 0x02000000 /* Bit 25 */ 694 #define HC_INITMB 0x04000000 /* Bit 26 */ 695 #define HC_INITFF 0x08000000 /* Bit 27 */ 696 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 697 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 698 699 /* BIU Configuration Register */ 700 701 #define BC_REG_OFFSET 4 /* Word offset from register base address */ 702 703 #define BC_BSE 0x00000001 /* Bit 0 */ 704 #define BC_BSE_SWAP 0x01000000 /* Bit 0 - swapped */ 705 706 707 /* 708 * End FireFly Register definitions 709 */ 710 711 /* ===================================================================== */ 712 713 /* 714 * Start of FCP specific structures 715 */ 716 717 typedef struct emlxs_fcp_rsp 718 { 719 uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 720 uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 721 722 uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 723 uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 724 uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 725 #define RSP_LEN_VALID 0x01 /* bit 0 */ 726 #define SNS_LEN_VALID 0x02 /* bit 1 */ 727 #define RESID_OVER 0x04 /* bit 2 */ 728 #define RESID_UNDER 0x08 /* bit 3 */ 729 730 uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 731 #define SCSI_STAT_GOOD 0x00 732 #define SCSI_STAT_CHECK_COND 0x02 733 #define SCSI_STAT_COND_MET 0x04 734 #define SCSI_STAT_BUSY 0x08 735 #define SCSI_STAT_INTERMED 0x10 736 #define SCSI_STAT_INTERMED_CM 0x14 737 #define SCSI_STAT_RES_CNFLCT 0x18 738 #define SCSI_STAT_CMD_TERM 0x22 739 #define SCSI_STAT_QUE_FULL 0x28 740 #define SCSI_STAT_ACA_ACTIVE 0x30 741 #define SCSI_STAT_TASK_ABORT 0x40 742 743 uint32_t rspResId; /* Residual xfer if RESID_xxxx set */ 744 /* in fcpStatus2. */ 745 /* Received in Big Endian format */ 746 uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 747 /* Received in Big Endian format */ 748 uint32_t rspRspLen; /* Length of FCP response data */ 749 /* in fcpRspInfo */ 750 /* Received in Big Endian format */ 751 752 uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 753 uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 754 uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 755 uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 756 757 #define RSP_NO_FAILURE 0x00 758 #define RSP_DATA_BURST_ERR 0x01 759 #define RSP_CMD_FIELD_ERR 0x02 760 #define RSP_RO_MISMATCH_ERR 0x03 761 #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 762 #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 763 764 uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 765 766 /* 767 * Define maximum size of SCSI Sense buffer. 768 * Seagate never issues more than 18 bytes of Sense data 769 */ 770 #define MAX_FCP_SNS 128 771 uint8_t rspSnsInfo[MAX_FCP_SNS]; 772 } emlxs_fcp_rsp; 773 typedef emlxs_fcp_rsp FCP_RSP; 774 775 776 typedef struct emlxs_fcp_cmd 777 { 778 uint32_t fcpLunMsl; /* most significant lun word */ 779 uint32_t fcpLunLsl; /* least significant lun word */ 780 781 /* 782 * # of bits to shift lun id to end up in right payload word, 783 * little endian = 8, big = 16. 784 */ 785 #ifdef EMLXS_LITTLE_ENDIAN 786 #define FC_LUN_SHIFT 8 787 #define FC_ADDR_MODE_SHIFT 0 788 #endif 789 #ifdef EMLXS_BIG_ENDIAN 790 #define FC_LUN_SHIFT 16 791 #define FC_ADDR_MODE_SHIFT 24 792 #endif 793 794 uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 795 uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 796 #define SIMPLE_Q 0x00 797 #define HEAD_OF_Q 0x01 798 #define ORDERED_Q 0x02 799 #define ACA_Q 0x04 800 #define UNTAGGED 0x05 801 802 uint8_t fcpCntl2; /* FCP_CTL byte 2 task management */ 803 /* codes */ 804 #define ABORT_TASK_SET 0x02 /* Bit 1 */ 805 #define CLEAR_TASK_SET 0x04 /* bit 2 */ 806 #define LUN_RESET 0x10 /* bit 4 */ 807 #define TARGET_RESET 0x20 /* bit 5 */ 808 #define CLEAR_ACA 0x40 /* bit 6 */ 809 #define TERMINATE_TASK 0x80 /* bit 7 */ 810 811 uint8_t fcpCntl3; 812 #define WRITE_DATA 0x01 /* Bit 0 */ 813 #define READ_DATA 0x02 /* Bit 1 */ 814 815 uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 816 uint32_t fcpDl; /* Total transfer length */ 817 } emlxs_fcp_cmd_t; 818 typedef emlxs_fcp_cmd_t FCP_CMND; 819 820 821 822 823 824 825 826 827 828 829 /* SCSI INQUIRY Command Structure */ 830 831 typedef struct emlxs_inquiryDataType 832 { 833 uint8_t DeviceType:5; 834 uint8_t DeviceTypeQualifier:3; 835 836 uint8_t DeviceTypeModifier:7; 837 uint8_t RemovableMedia:1; 838 839 uint8_t Versions; 840 uint8_t ResponseDataFormat; 841 uint8_t AdditionalLength; 842 uint8_t Reserved[2]; 843 844 uint8_t SoftReset:1; 845 uint8_t CommandQueue:1; 846 uint8_t Reserved2:1; 847 uint8_t LinkedCommands:1; 848 uint8_t Synchronous:1; 849 uint8_t Wide16Bit:1; 850 uint8_t Wide32Bit:1; 851 uint8_t RelativeAddressing:1; 852 853 uint8_t VendorId[8]; 854 uint8_t ProductId[16]; 855 uint8_t ProductRevisionLevel[4]; 856 uint8_t VendorSpecific[20]; 857 uint8_t Reserved3[40]; 858 } emlxs_inquiry_data_type_t; 859 typedef emlxs_inquiry_data_type_t INQUIRY_DATA_DEF; 860 861 862 typedef struct emlxs_read_capacity_data 863 { 864 uint32_t LogicalBlockAddress; 865 uint32_t BytesPerBlock; 866 } emlxs_read_capacity_data_t; 867 typedef emlxs_read_capacity_data_t READ_CAPACITY_DATA_DEF; 868 869 870 /* SCSI CDB command codes */ 871 #define FCP_SCSI_FORMAT_UNIT 0x04 872 #define FCP_SCSI_INQUIRY 0x12 873 #define FCP_SCSI_MODE_SELECT 0x15 874 #define FCP_SCSI_MODE_SENSE 0x1A 875 #define FCP_SCSI_PAUSE_RESUME 0x4B 876 #define FCP_SCSI_PLAY_AUDIO 0x45 877 #define FCP_SCSI_PLAY_AUDIO_EXT 0xA5 878 #define FCP_SCSI_PLAY_AUDIO_MSF 0x47 879 #define FCP_SCSI_PLAY_AUDIO_TRK_INDX 0x48 880 #define FCP_SCSI_PREVENT_ALLOW_REMOVAL 0x1E 881 #define FCP_SCSI_READ_CMD 0x08 882 #define FCP_SCSI_READ_BUFFER 0x3C 883 #define FCP_SCSI_READ_CAPACITY 0x25 884 #define FCP_SCSI_READ_DEFECT_LIST 0x37 885 #define FCP_SCSI_READ_EXTENDED 0x28 886 #define FCP_SCSI_READ_HEADER 0x44 887 #define FCP_SCSI_READ_LONG 0xE8 888 #define FCP_SCSI_READ_SUB_CHANNEL 0x42 889 #define FCP_SCSI_READ_TOC 0x43 890 #define FCP_SCSI_REASSIGN_BLOCK 0x07 891 #define FCP_SCSI_RECEIVE_DIAGNOSTIC_RESULTS 0x1C 892 #define FCP_SCSI_RELEASE_UNIT 0x17 893 #define FCP_SCSI_REPORT_LUNS 0xa0 894 #define FCP_SCSI_REQUEST_SENSE 0x03 895 #define FCP_SCSI_RESERVE_UNIT 0x16 896 #define FCP_SCSI_REZERO_UNIT 0x01 897 #define FCP_SCSI_SEEK 0x0B 898 #define FCP_SCSI_SEEK_EXTENDED 0x2B 899 #define FCP_SCSI_SEND_DIAGNOSTIC 0x1D 900 #define FCP_SCSI_START_STOP_UNIT 0x1B 901 #define FCP_SCSI_TEST_UNIT_READY 0x00 902 #define FCP_SCSI_VERIFY 0x2F 903 #define FCP_SCSI_WRITE_CMD 0x0A 904 #define FCP_SCSI_WRITE_AND_VERIFY 0x2E 905 #define FCP_SCSI_WRITE_BUFFER 0x3B 906 #define FCP_SCSI_WRITE_EXTENDED 0x2A 907 #define FCP_SCSI_WRITE_LONG 0xEA 908 #define FCP_SCSI_RELEASE_LUNR 0xBB 909 #define FCP_SCSI_RELEASE_LUNV 0xBF 910 911 #define HPVA_SETPASSTHROUGHMODE 0x27 912 #define HPVA_EXECUTEPASSTHROUGH 0x29 913 #define HPVA_CREATELUN 0xE2 914 #define HPVA_SETLUNSECURITYLIST 0xED 915 #define HPVA_SETCLOCK 0xF9 916 #define HPVA_RECOVER 0xFA 917 #define HPVA_GENERICSERVICEOUT 0xFD 918 919 #define DMEP_EXPORT_IN 0x85 920 #define DMEP_EXPORT_OUT 0x89 921 922 #define MDACIOCTL_DIRECT_CMD 0x22 923 #define MDACIOCTL_STOREIMAGE 0x2C 924 #define MDACIOCTL_WRITESIGNATURE 0xA6 925 #define MDACIOCTL_SETREALTIMECLOCK 0xAC 926 #define MDACIOCTL_PASS_THRU_CDB 0xAD 927 #define MDACIOCTL_PASS_THRU_INITIATE 0xAE 928 #define MDACIOCTL_CREATENEWCONF 0xC0 929 #define MDACIOCTL_ADDNEWCONF 0xC4 930 #define MDACIOCTL_MORE 0xC6 931 #define MDACIOCTL_SETPHYSDEVPARAMETER 0xC8 932 #define MDACIOCTL_SETLOGDEVPARAMETER 0xCF 933 #define MDACIOCTL_SETCONTROLLERPARAMETER 0xD1 934 #define MDACIOCTL_WRITESANMAP 0xD4 935 #define MDACIOCTL_SETMACADDRESS 0xD5 936 937 /* 938 * End of FCP specific structures 939 */ 940 941 #define FL_ALPA 0x00 /* AL_PA of FL_Port */ 942 943 /* Fibre Channel Service Parameter definitions */ 944 945 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 946 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 947 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 948 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 949 950 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 951 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 952 #define FC_PH3 0x20 /* FC-PH-3 version */ 953 954 #define FF_FRAME_SIZE 2048 955 956 957 /* ==== Mailbox Commands ==== */ 958 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 959 #define MBX_LOAD_SM 0x01 960 #define MBX_READ_NV 0x02 961 #define MBX_WRITE_NV 0x03 962 #define MBX_RUN_BIU_DIAG 0x04 963 #define MBX_INIT_LINK 0x05 964 #define MBX_DOWN_LINK 0x06 965 #define MBX_CONFIG_LINK 0x07 966 #define MBX_PART_SLIM 0x08 967 #define MBX_CONFIG_RING 0x09 968 #define MBX_RESET_RING 0x0A 969 #define MBX_READ_CONFIG 0x0B 970 #define MBX_READ_RCONFIG 0x0C 971 #define MBX_READ_SPARM 0x0D 972 #define MBX_READ_STATUS 0x0E 973 #define MBX_READ_RPI 0x0F 974 #define MBX_READ_XRI 0x10 975 #define MBX_READ_REV 0x11 976 #define MBX_READ_LNK_STAT 0x12 977 #define MBX_REG_LOGIN 0x13 978 #define MBX_UNREG_LOGIN 0x14 979 #define MBX_READ_LA 0x15 980 #define MBX_CLEAR_LA 0x16 981 #define MBX_DUMP_MEMORY 0x17 982 #define MBX_DUMP_CONTEXT 0x18 983 #define MBX_RUN_DIAGS 0x19 984 #define MBX_RESTART 0x1A 985 #define MBX_UPDATE_CFG 0x1B 986 #define MBX_DOWN_LOAD 0x1C 987 #define MBX_DEL_LD_ENTRY 0x1D 988 #define MBX_RUN_PROGRAM 0x1E 989 #define MBX_SET_MASK 0x20 990 #define MBX_SET_VARIABLE 0x21 991 #define MBX_UNREG_D_ID 0x23 992 #define MBX_KILL_BOARD 0x24 993 #define MBX_CONFIG_FARP 0x25 994 #define MBX_BEACON 0x2A 995 #define MBX_CONFIG_MSIX 0x30 996 #define MBX_HEARTBEAT 0x31 997 #define MBX_WRITE_VPARMS 0x32 998 #define MBX_ASYNC_EVENT 0x33 999 1000 #define MBX_READ_EVENT_LOG_STATUS 0x37 1001 #define MBX_READ_EVENT_LOG 0x38 1002 #define MBX_WRITE_EVENT_LOG 0x39 1003 #define MBX_NV_LOG 0x3A 1004 #define MBX_PORT_CAPABILITIES 0x3B 1005 #define MBX_IOV_CONTROL 0x3C 1006 #define MBX_IOV_MBX 0x3D 1007 1008 1009 #define MBX_CONFIG_HBQ 0x7C /* SLI3 */ 1010 #define MBX_LOAD_AREA 0x81 1011 #define MBX_RUN_BIU_DIAG64 0x84 1012 #define MBX_GET_DEBUG 0x86 1013 #define MBX_CONFIG_PORT 0x88 1014 #define MBX_READ_SPARM64 0x8D 1015 #define MBX_READ_RPI64 0x8F 1016 #define MBX_CONFIG_MSI 0x90 1017 #define MBX_REG_LOGIN64 0x93 1018 #define MBX_READ_LA64 0x95 1019 #define MBX_REG_VPI 0x96 /* NPIV */ 1020 #define MBX_UNREG_VPI 0x97 /* NPIV */ 1021 #define MBX_FLASH_WR_ULA 0x98 1022 #define MBX_SET_DEBUG 0x99 1023 #define MBX_LOAD_EXP_ROM 0x9C 1024 #define MBX_MAX_CMDS 0x9D 1025 #define MBX_SLI2_CMD_MASK 0x80 1026 1027 1028 /* ==== IOCB Commands ==== */ 1029 1030 #define CMD_RCV_SEQUENCE_CX 0x01 1031 #define CMD_XMIT_SEQUENCE_CR 0x02 1032 #define CMD_XMIT_SEQUENCE_CX 0x03 1033 #define CMD_XMIT_BCAST_CN 0x04 1034 #define CMD_XMIT_BCAST_CX 0x05 1035 #define CMD_QUE_RING_BUF_CN 0x06 1036 #define CMD_QUE_XRI_BUF_CX 0x07 1037 #define CMD_IOCB_CONTINUE_CN 0x08 1038 #define CMD_RET_XRI_BUF_CX 0x09 1039 #define CMD_ELS_REQUEST_CR 0x0A 1040 #define CMD_ELS_REQUEST_CX 0x0B 1041 #define CMD_RCV_ELS_REQ_CX 0x0D 1042 #define CMD_ABORT_XRI_CN 0x0E 1043 #define CMD_ABORT_XRI_CX 0x0F 1044 #define CMD_CLOSE_XRI_CN 0x10 1045 #define CMD_CLOSE_XRI_CX 0x11 1046 #define CMD_CREATE_XRI_CR 0x12 1047 #define CMD_CREATE_XRI_CX 0x13 1048 #define CMD_GET_RPI_CN 0x14 1049 #define CMD_XMIT_ELS_RSP_CX 0x15 1050 #define CMD_GET_RPI_CR 0x16 1051 #define CMD_XRI_ABORTED_CX 0x17 1052 #define CMD_FCP_IWRITE_CR 0x18 1053 #define CMD_FCP_IWRITE_CX 0x19 1054 #define CMD_FCP_IREAD_CR 0x1A 1055 #define CMD_FCP_IREAD_CX 0x1B 1056 #define CMD_FCP_ICMND_CR 0x1C 1057 #define CMD_FCP_ICMND_CX 0x1D 1058 #define CMD_FCP_TSEND_CX 0x1F /* FCP_TARGET_MODE */ 1059 #define CMD_ADAPTER_MSG 0x20 1060 #define CMD_FCP_TRECEIVE_CX 0x21 /* FCP_TARGET_MODE */ 1061 #define CMD_ADAPTER_DUMP 0x22 1062 #define CMD_FCP_TRSP_CX 0x23 /* FCP_TARGET_MODE */ 1063 #define CMD_FCP_AUTO_TRSP_CX 0x29 /* FCP_TARGET_MODE */ 1064 1065 /* LP3000 gasket IOCB Command Set */ 1066 1067 #define CMD_BPL_IWRITE_CR 0x48 1068 #define CMD_BPL_IWRITE_CX 0x49 1069 #define CMD_BPL_IREAD_CR 0x4A 1070 #define CMD_BPL_IREAD_CX 0x4B 1071 #define CMD_BPL_ICMND_CR 0x4C 1072 #define CMD_BPL_ICMND_CX 0x4D 1073 1074 #define CMD_ASYNC_STATUS 0x7C 1075 1076 /* SLI_2 IOCB Command Set */ 1077 #define CMD_RCV_SEQUENCE64_CX 0x81 1078 #define CMD_XMIT_SEQUENCE64_CR 0x82 1079 #define CMD_XMIT_SEQUENCE64_CX 0x83 1080 #define CMD_XMIT_BCAST64_CN 0x84 1081 #define CMD_XMIT_BCAST64_CX 0x85 1082 #define CMD_QUE_RING_BUF64_CN 0x86 1083 #define CMD_QUE_XRI_BUF64_CX 0x87 1084 #define CMD_IOCB_CONTINUE64_CN 0x88 1085 #define CMD_RET_XRI_BUF64_CX 0x89 1086 #define CMD_ELS_REQUEST64_CR 0x8A 1087 #define CMD_ELS_REQUEST64_CX 0x8B 1088 #define CMD_RCV_ELS_REQ64_CX 0x8D 1089 #define CMD_XMIT_ELS_RSP64_CX 0x95 1090 #define CMD_FCP_IWRITE64_CR 0x98 1091 #define CMD_FCP_IWRITE64_CX 0x99 1092 #define CMD_FCP_IREAD64_CR 0x9A 1093 #define CMD_FCP_IREAD64_CX 0x9B 1094 #define CMD_FCP_ICMND64_CR 0x9C 1095 #define CMD_FCP_ICMND64_CX 0x9D 1096 #define CMD_FCP_TSEND64_CX 0x9F /* FCP_TARGET_MODE */ 1097 #define CMD_FCP_TRECEIVE64_CX 0xA1 /* FCP_TARGET_MODE */ 1098 #define CMD_FCP_TRSP64_CX 0xA3 /* FCP_TARGET_MODE */ 1099 #define CMD_RCV_SEQ64_CX 0xB5 /* SLI3 */ 1100 #define CMD_RCV_ELS64_CX 0xB7 /* SLI3 */ 1101 #define CMD_RCV_CONT64_CX 0xBB /* SLI3 */ 1102 #define CMD_RCV_SEQ_LIST64_CX 0xC1 1103 #define CMD_GEN_REQUEST64_CR 0xC2 1104 #define CMD_GEN_REQUEST64_CX 0xC3 1105 #define CMD_QUE_RING_LIST64_CN 0xC6 1106 1107 /* 1108 * Define Status 1109 */ 1110 #define MBX_SUCCESS 0x0 1111 #define MBX_FAILURE 0x1 1112 #define MBXERR_NUM_IOCBS 0x2 1113 #define MBXERR_IOCBS_EXCEEDED 0x3 1114 #define MBXERR_BAD_RING_NUMBER 0x4 1115 #define MBXERR_MASK_ENTRIES_RANGE 0x5 1116 #define MBXERR_MASKS_EXCEEDED 0x6 1117 #define MBXERR_BAD_PROFILE 0x7 1118 #define MBXERR_BAD_DEF_CLASS 0x8 1119 #define MBXERR_BAD_MAX_RESPONDER 0x9 1120 #define MBXERR_BAD_MAX_ORIGINATOR 0xA 1121 #define MBXERR_RPI_REGISTERED 0xB 1122 #define MBXERR_RPI_FULL 0xC 1123 #define MBXERR_NO_RESOURCES 0xD 1124 #define MBXERR_BAD_RCV_LENGTH 0xE 1125 #define MBXERR_DMA_ERROR 0xF 1126 #define MBXERR_NOT_SUPPORTED 0x10 1127 #define MBXERR_UNSUPPORTED_FEATURE 0x11 1128 #define MBXERR_UNKNOWN_COMMAND 0x12 1129 1130 /* Driver special codes */ 1131 #define MBX_OVERTEMP_ERROR 0xFA 1132 #define MBX_HARDWARE_ERROR 0xFB 1133 #define MBX_DRVR_ERROR 0xFC 1134 #define MBX_BUSY 0xFD 1135 #define MBX_TIMEOUT 0xFE 1136 #define MBX_NOT_FINISHED 0xFF 1137 1138 1139 /* 1140 * flags for emlxs_mb_issue_cmd() 1141 */ 1142 #define MBX_POLL 0x01 /* poll mailbox till command done, */ 1143 /* then return */ 1144 #define MBX_SLEEP 0x02 /* sleep till mailbox intr cmpl */ 1145 /* wakes thread up */ 1146 #define MBX_WAIT 0x03 /* wait for comand done, then return */ 1147 #define MBX_NOWAIT 0x04 /* issue command then return immediately */ 1148 1149 typedef struct emlxs_rings 1150 { 1151 #ifdef EMLXS_BIG_ENDIAN 1152 uint32_t crReserved:16; 1153 uint32_t crBegin:8; 1154 uint32_t crEnd:8; /* Low order bit first word */ 1155 uint32_t rrReserved:16; 1156 uint32_t rrBegin:8; 1157 uint32_t rrEnd:8; /* Low order bit second word */ 1158 #endif 1159 #ifdef EMLXS_LITTLE_ENDIAN 1160 uint32_t crEnd:8; /* Low order bit first word */ 1161 uint32_t crBegin:8; 1162 uint32_t crReserved:16; 1163 uint32_t rrEnd:8; /* Low order bit second word */ 1164 uint32_t rrBegin:8; 1165 uint32_t rrReserved:16; 1166 #endif 1167 } emlxs_rings_t; 1168 typedef emlxs_rings_t RINGS; 1169 1170 1171 typedef struct emlxs_ring_def 1172 { 1173 #ifdef EMLXS_BIG_ENDIAN 1174 uint16_t offCiocb; 1175 uint16_t numCiocb; 1176 uint16_t offRiocb; 1177 uint16_t numRiocb; 1178 #endif 1179 #ifdef EMLXS_LITTLE_ENDIAN 1180 uint16_t numCiocb; 1181 uint16_t offCiocb; 1182 uint16_t numRiocb; 1183 uint16_t offRiocb; 1184 #endif 1185 } emlxs_ring_def_t; 1186 typedef emlxs_ring_def_t RING_DEF; 1187 1188 1189 /* 1190 * The following F.C. frame stuctures are defined in Big Endian format. 1191 */ 1192 1193 typedef struct emlxs_name_type 1194 { 1195 #ifdef EMLXS_BIG_ENDIAN 1196 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1197 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 */ 1198 /* of IEEE ext */ 1199 #endif 1200 #ifdef EMLXS_LITTLE_ENDIAN 1201 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 */ 1202 /* of IEEE ext */ 1203 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1204 #endif 1205 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 1206 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 1207 #define NAME_FC_TYPE 0x3 /* FC native name type */ 1208 #define NAME_IP_TYPE 0x4 /* IP address */ 1209 #define NAME_CCITT_TYPE 0xC 1210 #define NAME_CCITT_GR_TYPE 0xE 1211 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, */ 1212 /* IEEE extended Lsb */ 1213 uint8_t IEEE[6]; /* FC IEEE address */ 1214 } emlxs_name_type_t; 1215 typedef emlxs_name_type_t NAME_TYPE; 1216 1217 1218 typedef struct emlxs_csp 1219 { 1220 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 1221 uint8_t fcphLow; 1222 uint8_t bbCreditMsb; 1223 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 1224 #ifdef EMLXS_BIG_ENDIAN 1225 uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1226 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1227 uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1228 uint16_t fPort:1; /* FC Word 1, bit 28 */ 1229 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1230 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1231 uint16_t multicast:1; /* FC Word 1, bit 25 */ 1232 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1233 1234 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1235 uint16_t simplex:1; /* FC Word 1, bit 22 */ 1236 1237 uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1238 uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1239 uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1240 1241 uint16_t dhd:1; /* FC Word 1, bit 18 */ 1242 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1243 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1244 #endif 1245 #ifdef EMLXS_LITTLE_ENDIAN 1246 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1247 uint16_t multicast:1; /* FC Word 1, bit 25 */ 1248 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1249 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1250 uint16_t fPort:1; /* FC Word 1, bit 28 */ 1251 uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1252 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1253 uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1254 1255 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1256 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1257 uint16_t dhd:1; /* FC Word 1, bit 18 */ 1258 1259 uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1260 uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1261 uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1262 1263 uint16_t simplex:1; /* FC Word 1, bit 22 */ 1264 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1265 #endif 1266 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 1267 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 1268 union 1269 { 1270 struct 1271 { 1272 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 1273 1274 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 1275 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 1276 1277 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 1278 } nPort; 1279 uint32_t r_a_tov; /* R_A_TOV must be in Big */ 1280 /* Endian format */ 1281 } w2; 1282 1283 uint32_t e_d_tov; /* E_D_TOV must be in Big */ 1284 /* Endian format */ 1285 } emlxs_csp_t; 1286 typedef emlxs_csp_t CSP; 1287 1288 1289 typedef struct emlxs_class_parms 1290 { 1291 #ifdef EMLXS_BIG_ENDIAN 1292 uint8_t classValid:1; /* FC Word 0, bit 31 */ 1293 uint8_t intermix:1; /* FC Word 0, bit 30 */ 1294 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1295 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1296 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1297 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1298 #endif 1299 #ifdef EMLXS_LITTLE_ENDIAN 1300 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1301 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1302 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1303 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1304 uint8_t intermix:1; /* FC Word 0, bit 30 */ 1305 uint8_t classValid:1; /* FC Word 0, bit 31 */ 1306 1307 #endif 1308 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 1309 #ifdef EMLXS_BIG_ENDIAN 1310 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1311 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1312 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1313 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1314 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1315 #endif 1316 #ifdef EMLXS_LITTLE_ENDIAN 1317 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1318 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1319 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1320 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1321 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1322 #endif 1323 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 1324 #ifdef EMLXS_BIG_ENDIAN 1325 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1326 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1327 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1328 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1329 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1330 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1331 #endif 1332 #ifdef EMLXS_LITTLE_ENDIAN 1333 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1334 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1335 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1336 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1337 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1338 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1339 #endif 1340 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 1341 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 1342 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 1343 1344 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 1345 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 1346 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 1347 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 1348 1349 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 1350 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 1351 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 1352 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 1353 } emlxs_class_parms_t; 1354 typedef emlxs_class_parms_t CLASS_PARMS; 1355 1356 1357 typedef struct emlxs_serv_parms 1358 { /* Structure is in Big Endian format */ 1359 CSP cmn; 1360 NAME_TYPE portName; 1361 NAME_TYPE nodeName; 1362 CLASS_PARMS cls1; 1363 CLASS_PARMS cls2; 1364 CLASS_PARMS cls3; 1365 CLASS_PARMS cls4; 1366 uint8_t vendorVersion[16]; 1367 } emlxs_serv_parms_t; 1368 typedef emlxs_serv_parms_t SERV_PARM; 1369 1370 typedef struct 1371 { 1372 union 1373 { 1374 uint32_t word0; 1375 struct 1376 { 1377 #ifdef EMLXS_BIG_ENDIAN 1378 uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1379 uint32_t oui:24; /* Elx Organization */ 1380 /* Unique ID (0000C9) */ 1381 #endif 1382 #ifdef EMLXS_LITTLE_ENDIAN 1383 uint32_t oui:24; /* Elx Organization */ 1384 /* Unique ID (0000C9) */ 1385 uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1386 #endif 1387 } w0; 1388 } un0; 1389 union 1390 { 1391 uint32_t word1; 1392 struct 1393 { 1394 #ifdef EMLXS_BIG_ENDIAN 1395 uint32_t vport:1; /* Word 1, Bit 31 */ 1396 uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1397 #endif 1398 #ifdef EMLXS_LITTLE_ENDIAN 1399 uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1400 uint32_t vport:1; /* Word 1, Bit 31 */ 1401 #endif 1402 } w1; 1403 } un1; 1404 uint8_t rsvd2[8]; 1405 } emlxs_vvl_fmt_t; 1406 1407 #define valid_vendor_version cmn.rspMultipleNPort 1408 1409 1410 1411 /* 1412 * Extended Link Service LS_COMMAND codes (Payload BYTE 0) 1413 */ 1414 #ifdef EMLXS_BIG_ENDIAN 1415 #define ELS_CMD_SHIFT 24 1416 #define ELS_CMD_MASK 0xff000000 1417 #define ELS_RSP_MASK 0xff000000 1418 #define ELS_CMD_LS_RJT 0x01000000 1419 #define ELS_CMD_ACC 0x02000000 1420 #define ELS_CMD_PLOGI 0x03000000 1421 #define ELS_CMD_FLOGI 0x04000000 1422 #define ELS_CMD_LOGO 0x05000000 1423 #define ELS_CMD_ABTX 0x06000000 1424 #define ELS_CMD_RCS 0x07000000 1425 #define ELS_CMD_RES 0x08000000 1426 #define ELS_CMD_RSS 0x09000000 1427 #define ELS_CMD_RSI 0x0A000000 1428 #define ELS_CMD_ESTS 0x0B000000 1429 #define ELS_CMD_ESTC 0x0C000000 1430 #define ELS_CMD_ADVC 0x0D000000 1431 #define ELS_CMD_RTV 0x0E000000 1432 #define ELS_CMD_RLS 0x0F000000 1433 #define ELS_CMD_ECHO 0x10000000 1434 #define ELS_CMD_TEST 0x11000000 1435 #define ELS_CMD_RRQ 0x12000000 1436 #define ELS_CMD_PRLI 0x20000000 1437 #define ELS_CMD_PRLO 0x21000000 1438 #define ELS_CMD_SCN 0x22000000 1439 #define ELS_CMD_TPLS 0x23000000 1440 #define ELS_CMD_GPRLO 0x24000000 1441 #define ELS_CMD_GAID 0x30000000 1442 #define ELS_CMD_FACT 0x31000000 1443 #define ELS_CMD_FDACT 0x32000000 1444 #define ELS_CMD_NACT 0x33000000 1445 #define ELS_CMD_NDACT 0x34000000 1446 #define ELS_CMD_QoSR 0x40000000 1447 #define ELS_CMD_RVCS 0x41000000 1448 #define ELS_CMD_PDISC 0x50000000 1449 #define ELS_CMD_FDISC 0x51000000 1450 #define ELS_CMD_ADISC 0x52000000 1451 #define ELS_CMD_FARP 0x54000000 1452 #define ELS_CMD_FARPR 0x55000000 1453 #define ELS_CMD_FAN 0x60000000 1454 #define ELS_CMD_RSCN 0x61000000 1455 #define ELS_CMD_SCR 0x62000000 1456 #define ELS_CMD_LINIT 0x70000000 1457 #define ELS_CMD_RNID 0x78000000 1458 #define ELS_CMD_AUTH 0x90000000 1459 #endif 1460 1461 #ifdef EMLXS_LITTLE_ENDIAN 1462 #define ELS_CMD_SHIFT 0 1463 #define ELS_CMD_MASK 0xff 1464 #define ELS_RSP_MASK 0xff 1465 #define ELS_CMD_LS_RJT 0x01 1466 #define ELS_CMD_ACC 0x02 1467 #define ELS_CMD_PLOGI 0x03 1468 #define ELS_CMD_FLOGI 0x04 1469 #define ELS_CMD_LOGO 0x05 1470 #define ELS_CMD_ABTX 0x06 1471 #define ELS_CMD_RCS 0x07 1472 #define ELS_CMD_RES 0x08 1473 #define ELS_CMD_RSS 0x09 1474 #define ELS_CMD_RSI 0x0A 1475 #define ELS_CMD_ESTS 0x0B 1476 #define ELS_CMD_ESTC 0x0C 1477 #define ELS_CMD_ADVC 0x0D 1478 #define ELS_CMD_RTV 0x0E 1479 #define ELS_CMD_RLS 0x0F 1480 #define ELS_CMD_ECHO 0x10 1481 #define ELS_CMD_TEST 0x11 1482 #define ELS_CMD_RRQ 0x12 1483 #define ELS_CMD_PRLI 0x20 1484 #define ELS_CMD_PRLO 0x21 1485 #define ELS_CMD_SCN 0x22 1486 #define ELS_CMD_TPLS 0x23 1487 #define ELS_CMD_GPRLO 0x24 1488 #define ELS_CMD_GAID 0x30 1489 #define ELS_CMD_FACT 0x31 1490 #define ELS_CMD_FDACT 0x32 1491 #define ELS_CMD_NACT 0x33 1492 #define ELS_CMD_NDACT 0x34 1493 #define ELS_CMD_QoSR 0x40 1494 #define ELS_CMD_RVCS 0x41 1495 #define ELS_CMD_PDISC 0x50 1496 #define ELS_CMD_FDISC 0x51 1497 #define ELS_CMD_ADISC 0x52 1498 #define ELS_CMD_FARP 0x54 1499 #define ELS_CMD_FARPR 0x55 1500 #define ELS_CMD_FAN 0x60 1501 #define ELS_CMD_RSCN 0x61 1502 #define ELS_CMD_SCR 0x62 1503 #define ELS_CMD_LINIT 0x70 1504 #define ELS_CMD_RNID 0x78 1505 #define ELS_CMD_AUTH 0x90 1506 #endif 1507 1508 1509 /* 1510 * LS_RJT Payload Definition 1511 */ 1512 1513 typedef struct _LS_RJT 1514 { /* Structure is in Big Endian format */ 1515 union 1516 { 1517 uint32_t lsRjtError; 1518 struct 1519 { 1520 uint8_t lsRjtRsvd0; /* FC Word 0, */ 1521 /* bit 24:31 */ 1522 1523 uint8_t lsRjtRsnCode; /* FC Word 0, */ 1524 /* bit 16:23 */ 1525 /* LS_RJT reason codes */ 1526 #define LSRJT_INVALID_CMD 0x01 1527 #define LSRJT_LOGICAL_ERR 0x03 1528 #define LSRJT_LOGICAL_BSY 0x05 1529 #define LSRJT_PROTOCOL_ERR 0x07 1530 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 1531 #define LSRJT_CMD_UNSUPPORTED 0x0B 1532 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 1533 1534 uint8_t lsRjtRsnCodeExp; /* FC Word 0, */ 1535 /* bit 8:15 */ 1536 /* LS_RJT reason explanation */ 1537 #define LSEXP_NOTHING_MORE 0x00 1538 #define LSEXP_SPARM_OPTIONS 0x01 1539 #define LSEXP_SPARM_ICTL 0x03 1540 #define LSEXP_SPARM_RCTL 0x05 1541 #define LSEXP_SPARM_RCV_SIZE 0x07 1542 #define LSEXP_SPARM_CONCUR_SEQ 0x09 1543 #define LSEXP_SPARM_CREDIT 0x0B 1544 #define LSEXP_INVALID_PNAME 0x0D 1545 #define LSEXP_INVALID_NNAME 0x0E 1546 #define LSEXP_INVALID_CSP 0x0F 1547 #define LSEXP_INVALID_ASSOC_HDR 0x11 1548 #define LSEXP_ASSOC_HDR_REQ 0x13 1549 #define LSEXP_INVALID_O_SID 0x15 1550 #define LSEXP_INVALID_OX_RX 0x17 1551 #define LSEXP_CMD_IN_PROGRESS 0x19 1552 #define LSEXP_INVALID_NPORT_ID 0x1F 1553 #define LSEXP_INVALID_SEQ_ID 0x21 1554 #define LSEXP_INVALID_XCHG 0x23 1555 #define LSEXP_INACTIVE_XCHG 0x25 1556 #define LSEXP_RQ_REQUIRED 0x27 1557 #define LSEXP_OUT_OF_RESOURCE 0x29 1558 #define LSEXP_CANT_GIVE_DATA 0x2A 1559 #define LSEXP_REQ_UNSUPPORTED 0x2C 1560 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 1561 } b; 1562 } un; 1563 } LS_RJT; 1564 1565 1566 /* 1567 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 1568 */ 1569 1570 typedef struct _LOGO 1571 { /* Structure is in Big Endian format */ 1572 union 1573 { 1574 uint32_t nPortId32; /* Access nPortId as a word */ 1575 struct 1576 { 1577 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 1578 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 1579 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 1580 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 1581 } b; 1582 } un; 1583 NAME_TYPE portName; /* N_port name field */ 1584 } LOGO; 1585 1586 1587 /* 1588 * FCP Login (PRLI Request / ACC) Payload Definition 1589 */ 1590 1591 #define PRLX_PAGE_LEN 0x10 1592 #define TPRLO_PAGE_LEN 0x14 1593 1594 typedef struct _PRLI 1595 { /* Structure is in Big Endian format */ 1596 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 1597 1598 #define PRLI_FCP_TYPE 0x08 1599 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1600 1601 #ifdef EMLXS_BIG_ENDIAN 1602 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1603 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1604 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1605 1606 /* ACC = imagePairEstablished */ 1607 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1608 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1609 /* ACC ONLY */ 1610 #endif 1611 #ifdef EMLXS_LITTLE_ENDIAN 1612 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1613 /* ACC ONLY */ 1614 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1615 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1616 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1617 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1618 /* ACC = imagePairEstablished */ 1619 #endif 1620 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 1621 #define PRLI_NO_RESOURCES 0x2 1622 #define PRLI_INIT_INCOMPLETE 0x3 1623 #define PRLI_NO_SUCH_PA 0x4 1624 #define PRLI_PREDEF_CONFIG 0x5 1625 #define PRLI_PARTIAL_SUCCESS 0x6 1626 #define PRLI_INVALID_PAGE_CNT 0x7 1627 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1628 1629 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1630 1631 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1632 1633 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 1634 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 1635 #ifdef EMLXS_BIG_ENDIAN 1636 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1637 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1638 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1639 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1640 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1641 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1642 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1643 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1644 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1645 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1646 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1647 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1648 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1649 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1650 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1651 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1652 #endif 1653 #ifdef EMLXS_LITTLE_ENDIAN 1654 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1655 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1656 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1657 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1658 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1659 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1660 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1661 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1662 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1663 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1664 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1665 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1666 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1667 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1668 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1669 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1670 #endif 1671 } PRLI; 1672 1673 /* 1674 * FCP Logout (PRLO Request / ACC) Payload Definition 1675 */ 1676 1677 typedef struct _PRLO 1678 { /* Structure is in Big Endian format */ 1679 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 1680 1681 #define PRLO_FCP_TYPE 0x08 1682 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1683 1684 #ifdef EMLXS_BIG_ENDIAN 1685 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1686 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1687 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1688 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1689 /* ACC ONLY */ 1690 #endif 1691 #ifdef EMLXS_LITTLE_ENDIAN 1692 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1693 /* ACC ONLY */ 1694 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1695 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1696 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1697 #endif 1698 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 1699 #define PRLO_NO_SUCH_IMAGE 0x4 1700 #define PRLO_INVALID_PAGE_CNT 0x7 1701 1702 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1703 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1704 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1705 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 1706 } PRLO; 1707 1708 1709 typedef struct _ADISC 1710 { /* Structure is in Big Endian format */ 1711 uint32_t hardAL_PA; 1712 NAME_TYPE portName; 1713 NAME_TYPE nodeName; 1714 uint32_t DID; 1715 } ADISC; 1716 1717 1718 typedef struct _FARP 1719 { /* Structure is in Big Endian format */ 1720 uint32_t Mflags:8; 1721 uint32_t Odid:24; 1722 #define FARP_NO_ACTION 0 /* FARP information enclosed, no action */ 1723 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 1724 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 1725 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 1726 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not supported */ 1727 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not supported */ 1728 uint32_t Rflags:8; 1729 uint32_t Rdid:24; 1730 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 1731 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 1732 NAME_TYPE OportName; 1733 NAME_TYPE OnodeName; 1734 NAME_TYPE RportName; 1735 NAME_TYPE RnodeName; 1736 uint8_t Oipaddr[16]; 1737 uint8_t Ripaddr[16]; 1738 } FARP; 1739 1740 typedef struct _FAN 1741 { /* Structure is in Big Endian format */ 1742 uint32_t Fdid; 1743 NAME_TYPE FportName; 1744 NAME_TYPE FnodeName; 1745 } FAN; 1746 1747 typedef struct _SCR 1748 { /* Structure is in Big Endian format */ 1749 uint8_t resvd1; 1750 uint8_t resvd2; 1751 uint8_t resvd3; 1752 uint8_t Function; 1753 #define SCR_FUNC_FABRIC 0x01 1754 #define SCR_FUNC_NPORT 0x02 1755 #define SCR_FUNC_FULL 0x03 1756 #define SCR_CLEAR 0xff 1757 } SCR; 1758 1759 typedef struct _RNID_TOP_DISC 1760 { 1761 NAME_TYPE portName; 1762 uint8_t resvd[8]; 1763 uint32_t unitType; 1764 #define RNID_HBA 0x7 1765 #define RNID_HOST 0xa 1766 #define RNID_DRIVER 0xd 1767 uint32_t physPort; 1768 uint32_t attachedNodes; 1769 uint16_t ipVersion; 1770 #define RNID_IPV4 0x1 1771 #define RNID_IPV6 0x2 1772 uint16_t UDPport; 1773 uint8_t ipAddr[16]; 1774 uint16_t resvd1; 1775 uint16_t flags; 1776 #define RNID_TD_SUPPORT 0x1 1777 #define RNID_LP_VALID 0x2 1778 } RNID_TOP_DISC; 1779 1780 typedef struct _RNID 1781 { /* Structure is in Big Endian format */ 1782 uint8_t Format; 1783 #define RNID_TOPOLOGY_DISC 0xdf 1784 uint8_t CommonLen; 1785 uint8_t resvd1; 1786 uint8_t SpecificLen; 1787 NAME_TYPE portName; 1788 NAME_TYPE nodeName; 1789 union 1790 { 1791 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 1792 } un; 1793 } RNID; 1794 1795 typedef struct _RRQ 1796 { /* Structure is in Big Endian format */ 1797 uint32_t SID; 1798 uint16_t Oxid; 1799 uint16_t Rxid; 1800 uint8_t resv[32]; /* optional association hdr */ 1801 } RRQ; 1802 1803 1804 /* This is used for RSCN command */ 1805 typedef struct _D_ID 1806 { /* Structure is in Big Endian format */ 1807 union 1808 { 1809 uint32_t word; 1810 struct 1811 { 1812 #ifdef EMLXS_BIG_ENDIAN 1813 uint8_t resv; 1814 uint8_t domain; 1815 uint8_t area; 1816 uint8_t id; 1817 #endif 1818 #ifdef EMLXS_LITTLE_ENDIAN 1819 uint8_t id; 1820 uint8_t area; 1821 uint8_t domain; 1822 uint8_t resv; 1823 #endif 1824 } b; 1825 } un; 1826 } D_ID; 1827 1828 /* 1829 * Structure to define all ELS Payload types 1830 */ 1831 1832 typedef struct _ELS_PKT 1833 { /* Structure is in Big Endian format */ 1834 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1835 uint8_t elsByte1; 1836 uint8_t elsByte2; 1837 uint8_t elsByte3; 1838 union 1839 { 1840 LS_RJT lsRjt; /* Payload for LS_RJT */ 1841 SERV_PARM logi; /* Payload for PLOGI, FLOGI */ 1842 /* PDISC, ACC */ 1843 LOGO logo; /* Payload for PLOGO, FLOGO */ 1844 /* ACC */ 1845 PRLI prli; /* Payload for PRLI/ACC */ 1846 PRLO prlo; /* Payload for PRLO/ACC */ 1847 ADISC adisc; /* Payload for ADISC/ACC */ 1848 FARP farp; /* Payload for FARP/ACC */ 1849 FAN fan; /* Payload for FAN */ 1850 SCR scr; /* Payload for SCR/ACC */ 1851 RRQ rrq; /* Payload for RRQ */ 1852 RNID rnid; /* Payload for RNID */ 1853 uint8_t pad[128 - 4]; /* Pad out to payload of */ 1854 /* 128 bytes */ 1855 } un; 1856 } ELS_PKT; 1857 1858 1859 /* 1860 * Begin Structure Definitions for Mailbox Commands 1861 */ 1862 1863 typedef struct revcompat 1864 { 1865 #ifdef EMLXS_BIG_ENDIAN 1866 uint32_t ldflag:1; /* Set in SRAM descriptor */ 1867 uint32_t ldcount:7; /* For use by program load */ 1868 uint32_t kernel:4; /* Kernel ID */ 1869 uint32_t kver:4; /* Kernel compatibility version */ 1870 uint32_t SMver:4; /* Sequence Manager version */ 1871 /* 0 if none */ 1872 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */ 1873 uint32_t BIUtype:4; /* PCI = 0 */ 1874 uint32_t BIUver:4; /* BIU version, 0 if none */ 1875 #endif 1876 #ifdef EMLXS_LITTLE_ENDIAN 1877 uint32_t BIUver:4; /* BIU version, 0 if none */ 1878 uint32_t BIUtype:4; /* PCI = 0 */ 1879 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */ 1880 uint32_t SMver:4; /* Sequence Manager version */ 1881 /* 0 if none */ 1882 uint32_t kver:4; /* Kernel compatibility version */ 1883 uint32_t kernel:4; /* Kernel ID */ 1884 uint32_t ldcount:7; /* For use by program load */ 1885 uint32_t ldflag:1; /* Set in SRAM descriptor */ 1886 #endif 1887 } REVCOMPAT; 1888 1889 typedef struct id_word 1890 { 1891 #ifdef EMLXS_BIG_ENDIAN 1892 uint8_t Type; 1893 uint8_t Id; 1894 uint8_t Ver; 1895 uint8_t Rev; 1896 #endif 1897 #ifdef EMLXS_LITTLE_ENDIAN 1898 uint8_t Rev; 1899 uint8_t Ver; 1900 uint8_t Id; 1901 uint8_t Type; 1902 #endif 1903 union 1904 { 1905 REVCOMPAT cp; 1906 uint32_t revcomp; 1907 } un; 1908 } PROG_ID; 1909 1910 typedef struct 1911 { 1912 #ifdef EMLXS_BIG_ENDIAN 1913 uint8_t tval; 1914 uint8_t tmask; 1915 uint8_t rval; 1916 uint8_t rmask; 1917 #endif 1918 #ifdef EMLXS_LITTLE_ENDIAN 1919 uint8_t rmask; 1920 uint8_t rval; 1921 uint8_t tmask; 1922 uint8_t tval; 1923 #endif 1924 } RR_REG; 1925 1926 typedef struct 1927 { 1928 uint32_t bdeAddress; 1929 #ifdef EMLXS_BIG_ENDIAN 1930 uint32_t bdeReserved:4; 1931 uint32_t bdeAddrHigh:4; 1932 uint32_t bdeSize:24; 1933 #endif 1934 #ifdef EMLXS_LITTLE_ENDIAN 1935 uint32_t bdeSize:24; 1936 uint32_t bdeAddrHigh:4; 1937 uint32_t bdeReserved:4; 1938 #endif 1939 } ULP_BDE; 1940 1941 typedef struct ULP_BDE_64 1942 { /* SLI-2 */ 1943 union ULP_BDE_TUS 1944 { 1945 uint32_t w; 1946 struct 1947 { 1948 #ifdef EMLXS_BIG_ENDIAN 1949 uint32_t bdeFlags:8; /* BDE Flags 0 IS A */ 1950 /* SUPPORTED VALUE !! */ 1951 uint32_t bdeSize:24; /* buff size in bytes */ 1952 #endif 1953 #ifdef EMLXS_LITTLE_ENDIAN 1954 uint32_t bdeSize:24; /* buff size in bytes */ 1955 uint32_t bdeFlags:8; /* BDE Flags 0 IS A */ 1956 /* SUPPORTED VALUE !! */ 1957 #endif 1958 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 1959 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 1960 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 1961 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, */ 1962 /* 0=xmit buffer */ 1963 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr */ 1964 /* 0=64 bit addr */ 1965 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 1966 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 1967 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 1968 } f; 1969 } tus; 1970 uint32_t addrLow; 1971 uint32_t addrHigh; 1972 } ULP_BDE64; 1973 1974 #define BDE64_SIZE_WORD 0 1975 #define BPL64_SIZE_WORD 0x40 1976 1977 /* ULP */ 1978 typedef struct ULP_BPL_64 1979 { 1980 ULP_BDE64 fccmd_payload; 1981 ULP_BDE64 fcrsp_payload; 1982 ULP_BDE64 fcdat_payload; 1983 ULP_BDE64 pat0; 1984 } ULP_BPL64; 1985 1986 typedef struct ULP_BDL 1987 { /* SLI-2 */ 1988 #ifdef EMLXS_BIG_ENDIAN 1989 uint32_t bdeFlags:8; /* BDL Flags */ 1990 uint32_t bdeSize:24; /* Size of BDL array in host */ 1991 /* memory (bytes) */ 1992 #endif 1993 #ifdef EMLXS_LITTLE_ENDIAN 1994 uint32_t bdeSize:24; /* Size of BDL array in host */ 1995 /* memory (bytes) */ 1996 uint32_t bdeFlags:8; /* BDL Flags */ 1997 #endif 1998 uint32_t addrLow; /* Address 0:31 */ 1999 uint32_t addrHigh; /* Address 32:63 */ 2000 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 2001 } ULP_BDL; 2002 2003 typedef struct 2004 { 2005 uint8_t *fc_mptr; 2006 uint8_t *virt; /* virtual address ptr */ 2007 uint64_t phys; /* mapped address */ 2008 uint32_t size; 2009 void *data_handle; 2010 void *dma_handle; 2011 uint32_t tag; 2012 uint32_t flag; 2013 2014 #define MAP_POOL_ALLOCATED 0x00000001 2015 #define MAP_BUF_ALLOCATED 0x00000002 2016 #define MAP_TABLE_ALLOCATED 0x00000004 2017 } MATCHMAP; 2018 2019 /* Structure used for a HBQ entry */ 2020 typedef struct 2021 { 2022 ULP_BDE64 bde; 2023 union UN_TAG 2024 { 2025 uint32_t w; 2026 struct 2027 { 2028 #ifdef EMLXS_BIG_ENDIAN 2029 uint32_t HBQ_tag:4; 2030 uint32_t HBQE_tag:28; 2031 #endif 2032 #ifdef EMLXS_LITTLE_ENDIAN 2033 uint32_t HBQE_tag:28; 2034 uint32_t HBQ_tag:4; 2035 #endif 2036 } ext; 2037 } unt; 2038 } HBQE_t; 2039 2040 typedef struct 2041 { 2042 #ifdef EMLXS_BIG_ENDIAN 2043 uint8_t tmatch; 2044 uint8_t tmask; 2045 uint8_t rctlmatch; 2046 uint8_t rctlmask; 2047 #endif 2048 #ifdef EMLXS_LITTLE_ENDIAN 2049 uint8_t rctlmask; 2050 uint8_t rctlmatch; 2051 uint8_t tmask; 2052 uint8_t tmatch; 2053 #endif 2054 } HBQ_MASK; 2055 2056 #define EMLXS_MAX_HBQ_BUFFERS 4096 2057 2058 typedef struct 2059 { 2060 uint32_t HBQ_num_mask; /* number of mask entries in */ 2061 /* port array */ 2062 uint32_t HBQ_recvNotify; /* Rcv buffer notification */ 2063 uint32_t HBQ_numEntries; /* # of entries in HBQ */ 2064 uint32_t HBQ_headerLen; /* 0 if not profile 4 or 5 */ 2065 uint32_t HBQ_logEntry; /* Set to 1 if this HBQ used */ 2066 /* for LogEntry */ 2067 uint32_t HBQ_profile; /* Selection profile 0=all, */ 2068 /* 7=logentry */ 2069 uint32_t HBQ_ringMask; /* Binds HBQ to a ring e.g. */ 2070 /* Ring0=b0001, ring2=b0100 */ 2071 uint32_t HBQ_id; /* index of this hbq in ring */ 2072 /* of HBQs[] */ 2073 uint32_t HBQ_PutIdx_next; /* Index to next HBQ slot to */ 2074 /* use */ 2075 uint32_t HBQ_PutIdx; /* HBQ slot to use */ 2076 uint32_t HBQ_GetIdx; /* Local copy of Get index */ 2077 /* from Port */ 2078 uint16_t HBQ_PostBufCnt; /* Current number of entries */ 2079 /* in list */ 2080 MATCHMAP *HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS]; 2081 MATCHMAP HBQ_host_buf; /* HBQ host buffer for HBQEs */ 2082 HBQ_MASK HBQ_Masks[6]; 2083 2084 union 2085 { 2086 uint32_t allprofiles[12]; 2087 2088 struct 2089 { 2090 #ifdef EMLXS_BIG_ENDIAN 2091 uint32_t seqlenoff:16; 2092 uint32_t maxlen:16; 2093 #endif 2094 #ifdef EMLXS_LITTLE_ENDIAN 2095 uint32_t maxlen:16; 2096 uint32_t seqlenoff:16; 2097 #endif 2098 #ifdef EMLXS_BIG_ENDIAN 2099 uint32_t rsvd1:28; 2100 uint32_t seqlenbcnt:4; 2101 #endif 2102 #ifdef EMLXS_LITTLE_ENDIAN 2103 uint32_t seqlenbcnt:4; 2104 uint32_t rsvd1:28; 2105 #endif 2106 uint32_t rsvd[10]; 2107 } profile2; 2108 2109 struct 2110 { 2111 #ifdef EMLXS_BIG_ENDIAN 2112 uint32_t seqlenoff:16; 2113 uint32_t maxlen:16; 2114 #endif 2115 #ifdef EMLXS_LITTLE_ENDIAN 2116 uint32_t maxlen:16; 2117 uint32_t seqlenoff:16; 2118 #endif 2119 #ifdef EMLXS_BIG_ENDIAN 2120 uint32_t cmdcodeoff:28; 2121 uint32_t rsvd1:12; 2122 uint32_t seqlenbcnt:4; 2123 #endif 2124 #ifdef EMLXS_LITTLE_ENDIAN 2125 uint32_t seqlenbcnt:4; 2126 uint32_t rsvd1:12; 2127 uint32_t cmdcodeoff:28; 2128 #endif 2129 uint32_t cmdmatch[8]; 2130 2131 uint32_t rsvd[2]; 2132 } profile3; 2133 2134 struct 2135 { 2136 #ifdef EMLXS_BIG_ENDIAN 2137 uint32_t seqlenoff:16; 2138 uint32_t maxlen:16; 2139 #endif 2140 #ifdef EMLXS_LITTLE_ENDIAN 2141 uint32_t maxlen:16; 2142 uint32_t seqlenoff:16; 2143 #endif 2144 #ifdef EMLXS_BIG_ENDIAN 2145 uint32_t cmdcodeoff:28; 2146 uint32_t rsvd1:12; 2147 uint32_t seqlenbcnt:4; 2148 #endif 2149 #ifdef EMLXS_LITTLE_ENDIAN 2150 uint32_t seqlenbcnt:4; 2151 uint32_t rsvd1:12; 2152 uint32_t cmdcodeoff:28; 2153 #endif 2154 uint32_t cmdmatch[8]; 2155 2156 uint32_t rsvd[2]; 2157 } profile5; 2158 } profiles; 2159 } HBQ_INIT_t; 2160 2161 2162 2163 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 2164 2165 2166 typedef struct 2167 { 2168 #ifdef EMLXS_BIG_ENDIAN 2169 uint32_t rsvd2:25; 2170 uint32_t acknowledgment:1; 2171 uint32_t version:1; 2172 uint32_t erase_or_prog:1; 2173 uint32_t update_flash:1; 2174 uint32_t update_ram:1; 2175 uint32_t method:1; 2176 uint32_t load_cmplt:1; 2177 #endif 2178 #ifdef EMLXS_LITTLE_ENDIAN 2179 uint32_t load_cmplt:1; 2180 uint32_t method:1; 2181 uint32_t update_ram:1; 2182 uint32_t update_flash:1; 2183 uint32_t erase_or_prog:1; 2184 uint32_t version:1; 2185 uint32_t acknowledgment:1; 2186 uint32_t rsvd2:25; 2187 #endif 2188 2189 #define DL_FROM_BDE 0 /* method */ 2190 #define DL_FROM_SLIM 1 2191 2192 #define PROGRAM_FLASH 0 /* erase_or_prog */ 2193 #define ERASE_FLASH 1 2194 2195 uint32_t dl_to_adr; 2196 uint32_t dl_len; 2197 union 2198 { 2199 uint32_t dl_from_slim_offset; 2200 ULP_BDE dl_from_bde; 2201 ULP_BDE64 dl_from_bde64; 2202 PROG_ID prog_id; 2203 } un; 2204 } LOAD_SM_VAR; 2205 2206 2207 /* Structure for MB Command READ_NVPARM (02) */ 2208 2209 typedef struct 2210 { 2211 uint32_t rsvd1[3]; /* Read as all one's */ 2212 uint32_t rsvd2; /* Read as all zero's */ 2213 uint32_t portname[2]; /* N_PORT name */ 2214 uint32_t nodename[2]; /* NODE name */ 2215 #ifdef EMLXS_BIG_ENDIAN 2216 uint32_t pref_DID:24; 2217 uint32_t hardAL_PA:8; 2218 #endif 2219 #ifdef EMLXS_LITTLE_ENDIAN 2220 uint32_t hardAL_PA:8; 2221 uint32_t pref_DID:24; 2222 #endif 2223 uint32_t rsvd3[21]; /* Read as all one's */ 2224 } READ_NV_VAR; 2225 2226 2227 /* Structure for MB Command WRITE_NVPARMS (03) */ 2228 2229 typedef struct 2230 { 2231 uint32_t rsvd1[3]; /* Must be all one's */ 2232 uint32_t rsvd2; /* Must be all zero's */ 2233 uint32_t portname[2]; /* N_PORT name */ 2234 uint32_t nodename[2]; /* NODE name */ 2235 #ifdef EMLXS_BIG_ENDIAN 2236 uint32_t pref_DID:24; 2237 uint32_t hardAL_PA:8; 2238 #endif 2239 #ifdef EMLXS_LITTLE_ENDIAN 2240 uint32_t hardAL_PA:8; 2241 uint32_t pref_DID:24; 2242 #endif 2243 uint32_t rsvd3[21]; /* Must be all one's */ 2244 } WRITE_NV_VAR; 2245 2246 2247 /* Structure for MB Command RUN_BIU_DIAG (04) */ 2248 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 2249 2250 typedef struct 2251 { 2252 uint32_t rsvd1; 2253 union 2254 { 2255 struct 2256 { 2257 ULP_BDE xmit_bde; 2258 ULP_BDE rcv_bde; 2259 } s1; 2260 struct 2261 { 2262 ULP_BDE64 xmit_bde64; 2263 ULP_BDE64 rcv_bde64; 2264 } s2; 2265 } un; 2266 } BIU_DIAG_VAR; 2267 2268 2269 /* Structure for MB Command INIT_LINK (05) */ 2270 2271 typedef struct 2272 { 2273 #ifdef EMLXS_BIG_ENDIAN 2274 uint32_t rsvd1:24; 2275 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective */ 2276 /* Reset to */ 2277 #endif 2278 #ifdef EMLXS_LITTLE_ENDIAN 2279 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective */ 2280 /* Reset to */ 2281 uint32_t rsvd1:24; 2282 #endif 2283 2284 #ifdef EMLXS_BIG_ENDIAN 2285 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2286 uint8_t rsvd2; 2287 uint16_t link_flags; 2288 #endif 2289 #ifdef EMLXS_LITTLE_ENDIAN 2290 uint16_t link_flags; 2291 uint8_t rsvd2; 2292 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2293 #endif 2294 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) */ 2295 /* ENDEC loopback */ 2296 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 2297 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 2298 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 2299 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 2300 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 2301 2302 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 2303 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 2304 #define FLAGS_PREABORT_RETURN 0x4000 /* Bit 14 */ 2305 2306 uint32_t link_speed; /* NEW_FEATURE */ 2307 #define LINK_SPEED_AUTO 0 /* Auto selection */ 2308 #define LINK_SPEED_1G 1 /* 1 Gigabaud */ 2309 #define LINK_SPEED_2G 2 /* 2 Gigabaud */ 2310 } INIT_LINK_VAR; 2311 2312 2313 /* Structure for MB Command DOWN_LINK (06) */ 2314 2315 typedef struct 2316 { 2317 uint32_t rsvd1; 2318 } DOWN_LINK_VAR; 2319 2320 2321 /* Structure for MB Command CONFIG_LINK (07) */ 2322 2323 typedef struct 2324 { 2325 #ifdef EMLXS_BIG_ENDIAN 2326 uint32_t cr:1; 2327 uint32_t ci:1; 2328 uint32_t cr_delay:6; 2329 uint32_t cr_count:8; 2330 uint32_t rsvd1:8; 2331 uint32_t MaxBBC:8; 2332 #endif 2333 #ifdef EMLXS_LITTLE_ENDIAN 2334 uint32_t MaxBBC:8; 2335 uint32_t rsvd1:8; 2336 uint32_t cr_count:8; 2337 uint32_t cr_delay:6; 2338 uint32_t ci:1; 2339 uint32_t cr:1; 2340 #endif 2341 uint32_t myId; 2342 uint32_t rsvd2; 2343 uint32_t edtov; 2344 uint32_t arbtov; 2345 uint32_t ratov; 2346 uint32_t rttov; 2347 uint32_t altov; 2348 uint32_t crtov; 2349 uint32_t citov; 2350 #ifdef EMLXS_BIG_ENDIAN 2351 uint32_t rrq_enable:1; 2352 uint32_t rrq_immed:1; 2353 uint32_t rsvd4:29; 2354 uint32_t ack0_enable:1; 2355 #endif 2356 #ifdef EMLXS_LITTLE_ENDIAN 2357 uint32_t ack0_enable:1; 2358 uint32_t rsvd4:29; 2359 uint32_t rrq_immed:1; 2360 uint32_t rrq_enable:1; 2361 #endif 2362 } CONFIG_LINK; 2363 2364 2365 /* Structure for MB Command PART_SLIM (08) */ 2366 2367 typedef struct 2368 { 2369 #ifdef EMLXS_BIG_ENDIAN 2370 uint32_t unused1:24; 2371 uint32_t numRing:8; 2372 #endif 2373 #ifdef EMLXS_LITTLE_ENDIAN 2374 uint32_t numRing:8; 2375 uint32_t unused1:24; 2376 #endif 2377 emlxs_ring_def_t ringdef[4]; 2378 uint32_t hbainit; 2379 } PART_SLIM_VAR; 2380 2381 2382 /* Structure for MB Command CONFIG_RING (09) */ 2383 2384 typedef struct 2385 { 2386 #ifdef EMLXS_BIG_ENDIAN 2387 uint32_t unused2:6; 2388 uint32_t recvSeq:1; 2389 uint32_t recvNotify:1; 2390 uint32_t numMask:8; 2391 uint32_t profile:8; 2392 uint32_t unused1:4; 2393 uint32_t ring:4; 2394 #endif 2395 #ifdef EMLXS_LITTLE_ENDIAN 2396 uint32_t ring:4; 2397 uint32_t unused1:4; 2398 uint32_t profile:8; 2399 uint32_t numMask:8; 2400 uint32_t recvNotify:1; 2401 uint32_t recvSeq:1; 2402 uint32_t unused2:6; 2403 #endif 2404 #ifdef EMLXS_BIG_ENDIAN 2405 uint16_t maxRespXchg; 2406 uint16_t maxOrigXchg; 2407 #endif 2408 #ifdef EMLXS_LITTLE_ENDIAN 2409 uint16_t maxOrigXchg; 2410 uint16_t maxRespXchg; 2411 #endif 2412 RR_REG rrRegs[6]; 2413 } CONFIG_RING_VAR; 2414 2415 2416 /* Structure for MB Command RESET_RING (10) */ 2417 2418 typedef struct 2419 { 2420 uint32_t ring_no; 2421 } RESET_RING_VAR; 2422 2423 2424 /* Structure for MB Command READ_CONFIG (11) */ 2425 2426 typedef struct 2427 { 2428 #ifdef EMLXS_BIG_ENDIAN 2429 uint32_t cr:1; 2430 uint32_t ci:1; 2431 uint32_t cr_delay:6; 2432 uint32_t cr_count:8; 2433 uint32_t InitBBC:8; 2434 uint32_t MaxBBC:8; 2435 #endif 2436 #ifdef EMLXS_LITTLE_ENDIAN 2437 uint32_t MaxBBC:8; 2438 uint32_t InitBBC:8; 2439 uint32_t cr_count:8; 2440 uint32_t cr_delay:6; 2441 uint32_t ci:1; 2442 uint32_t cr:1; 2443 #endif 2444 #ifdef EMLXS_BIG_ENDIAN 2445 uint32_t topology:8; 2446 uint32_t myDid:24; 2447 #endif 2448 #ifdef EMLXS_LITTLE_ENDIAN 2449 uint32_t myDid:24; 2450 uint32_t topology:8; 2451 #endif 2452 /* Defines for topology (defined previously) */ 2453 #ifdef EMLXS_BIG_ENDIAN 2454 uint32_t AR:1; 2455 uint32_t IR:1; 2456 uint32_t rsvd1:29; 2457 uint32_t ack0:1; 2458 #endif 2459 #ifdef EMLXS_LITTLE_ENDIAN 2460 uint32_t ack0:1; 2461 uint32_t rsvd1:29; 2462 uint32_t IR:1; 2463 uint32_t AR:1; 2464 #endif 2465 uint32_t edtov; 2466 uint32_t arbtov; 2467 uint32_t ratov; 2468 uint32_t rttov; 2469 uint32_t altov; 2470 uint32_t lmt; 2471 2472 #define LMT_1GB_CAPABLE 0x0004 2473 #define LMT_2GB_CAPABLE 0x0008 2474 #define LMT_4GB_CAPABLE 0x0040 2475 #define LMT_8GB_CAPABLE 0x0080 2476 #define LMT_10GB_CAPABLE 0x0100 2477 /* E2E supported on adapters >= 8GB */ 2478 #define LMT_E2E_CAPABLE (LMT_8GB_CAPABLE|LMT_10GB_CAPABLE) 2479 2480 uint32_t rsvd2; 2481 uint32_t rsvd3; 2482 uint32_t max_xri; 2483 uint32_t max_iocb; 2484 uint32_t max_rpi; 2485 uint32_t avail_xri; 2486 uint32_t avail_iocb; 2487 uint32_t avail_rpi; 2488 2489 #ifdef SLI3_SUPPORT 2490 uint32_t max_vpi; 2491 uint32_t max_alpa; 2492 uint32_t rsvd4; 2493 uint32_t avail_vpi; 2494 #else 2495 uint32_t default_rpi; 2496 #endif /* SLI3_SUPPORT */ 2497 } READ_CONFIG_VAR; 2498 2499 2500 /* Structure for MB Command READ_RCONFIG (12) */ 2501 2502 typedef struct 2503 { 2504 #ifdef EMLXS_BIG_ENDIAN 2505 uint32_t rsvd2:7; 2506 uint32_t recvNotify:1; 2507 uint32_t numMask:8; 2508 uint32_t profile:8; 2509 uint32_t rsvd1:4; 2510 uint32_t ring:4; 2511 #endif 2512 #ifdef EMLXS_LITTLE_ENDIAN 2513 uint32_t ring:4; 2514 uint32_t rsvd1:4; 2515 uint32_t profile:8; 2516 uint32_t numMask:8; 2517 uint32_t recvNotify:1; 2518 uint32_t rsvd2:7; 2519 #endif 2520 #ifdef EMLXS_BIG_ENDIAN 2521 uint16_t maxResp; 2522 uint16_t maxOrig; 2523 #endif 2524 #ifdef EMLXS_LITTLE_ENDIAN 2525 uint16_t maxOrig; 2526 uint16_t maxResp; 2527 #endif 2528 RR_REG rrRegs[6]; 2529 #ifdef EMLXS_BIG_ENDIAN 2530 uint16_t cmdRingOffset; 2531 uint16_t cmdEntryCnt; 2532 uint16_t rspRingOffset; 2533 uint16_t rspEntryCnt; 2534 uint16_t nextCmdOffset; 2535 uint16_t rsvd3; 2536 uint16_t nextRspOffset; 2537 uint16_t rsvd4; 2538 #endif 2539 #ifdef EMLXS_LITTLE_ENDIAN 2540 uint16_t cmdEntryCnt; 2541 uint16_t cmdRingOffset; 2542 uint16_t rspEntryCnt; 2543 uint16_t rspRingOffset; 2544 uint16_t rsvd3; 2545 uint16_t nextCmdOffset; 2546 uint16_t rsvd4; 2547 uint16_t nextRspOffset; 2548 #endif 2549 } READ_RCONF_VAR; 2550 2551 2552 /* Structure for MB Command READ_SPARM (13) */ 2553 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2554 2555 typedef struct 2556 { 2557 uint32_t rsvd1; 2558 uint32_t rsvd2; 2559 union 2560 { 2561 ULP_BDE sp; /* This BDE points to SERV_PARM */ 2562 /* structure */ 2563 ULP_BDE64 sp64; 2564 } un; 2565 } READ_SPARM_VAR; 2566 2567 2568 /* Structure for MB Command READ_STATUS (14) */ 2569 2570 typedef struct 2571 { 2572 #ifdef EMLXS_BIG_ENDIAN 2573 uint32_t rsvd1:31; 2574 uint32_t clrCounters:1; 2575 uint16_t activeXriCnt; 2576 uint16_t activeRpiCnt; 2577 #endif 2578 #ifdef EMLXS_LITTLE_ENDIAN 2579 uint32_t clrCounters:1; 2580 uint32_t rsvd1:31; 2581 uint16_t activeRpiCnt; 2582 uint16_t activeXriCnt; 2583 #endif 2584 uint32_t xmitByteCnt; 2585 uint32_t rcvByteCnt; 2586 uint32_t xmitFrameCnt; 2587 uint32_t rcvFrameCnt; 2588 uint32_t xmitSeqCnt; 2589 uint32_t rcvSeqCnt; 2590 uint32_t totalOrigExchanges; 2591 uint32_t totalRespExchanges; 2592 uint32_t rcvPbsyCnt; 2593 uint32_t rcvFbsyCnt; 2594 } READ_STATUS_VAR; 2595 2596 2597 /* Structure for MB Command READ_RPI (15) */ 2598 /* Structure for MB Command READ_RPI64 (0x8F) */ 2599 2600 typedef struct 2601 { 2602 #ifdef EMLXS_BIG_ENDIAN 2603 uint16_t nextRpi; 2604 uint16_t reqRpi; 2605 uint32_t rsvd2:8; 2606 uint32_t DID:24; 2607 #endif 2608 #ifdef EMLXS_LITTLE_ENDIAN 2609 uint16_t reqRpi; 2610 uint16_t nextRpi; 2611 uint32_t DID:24; 2612 uint32_t rsvd2:8; 2613 #endif 2614 union 2615 { 2616 ULP_BDE sp; 2617 ULP_BDE64 sp64; 2618 } un; 2619 } READ_RPI_VAR; 2620 2621 2622 /* Structure for MB Command READ_XRI (16) */ 2623 2624 typedef struct 2625 { 2626 #ifdef EMLXS_BIG_ENDIAN 2627 uint16_t nextXri; 2628 uint16_t reqXri; 2629 uint16_t rsvd1; 2630 uint16_t rpi; 2631 uint32_t rsvd2:8; 2632 uint32_t DID:24; 2633 uint32_t rsvd3:8; 2634 uint32_t SID:24; 2635 uint32_t rsvd4; 2636 uint8_t seqId; 2637 uint8_t rsvd5; 2638 uint16_t seqCount; 2639 uint16_t oxId; 2640 uint16_t rxId; 2641 uint32_t rsvd6:30; 2642 uint32_t si:1; 2643 uint32_t exchOrig:1; 2644 #endif 2645 #ifdef EMLXS_LITTLE_ENDIAN 2646 uint16_t reqXri; 2647 uint16_t nextXri; 2648 uint16_t rpi; 2649 uint16_t rsvd1; 2650 uint32_t DID:24; 2651 uint32_t rsvd2:8; 2652 uint32_t SID:24; 2653 uint32_t rsvd3:8; 2654 uint32_t rsvd4; 2655 uint16_t seqCount; 2656 uint8_t rsvd5; 2657 uint8_t seqId; 2658 uint16_t rxId; 2659 uint16_t oxId; 2660 uint32_t exchOrig:1; 2661 uint32_t si:1; 2662 uint32_t rsvd6:30; 2663 #endif 2664 } READ_XRI_VAR; 2665 2666 2667 /* Structure for MB Command READ_REV (17) */ 2668 2669 typedef struct 2670 { 2671 #ifdef EMLXS_BIG_ENDIAN 2672 uint32_t cv:1; 2673 uint32_t rr:1; 2674 uint32_t co:1; 2675 uint32_t rp:1; 2676 uint32_t cv3:1; 2677 uint32_t rf3:1; 2678 uint32_t rsvd1:10; 2679 uint32_t offset:14; 2680 uint32_t rv:2; 2681 #endif 2682 #ifdef EMLXS_LITTLE_ENDIAN 2683 uint32_t rv:2; 2684 uint32_t offset:14; 2685 uint32_t rsvd1:10; 2686 uint32_t rf3:1; 2687 uint32_t cv3:1; 2688 uint32_t rp:1; 2689 uint32_t co:1; 2690 uint32_t rr:1; 2691 uint32_t cv:1; 2692 #endif 2693 uint32_t biuRev; 2694 uint32_t smRev; 2695 union 2696 { 2697 uint32_t smFwRev; 2698 struct 2699 { 2700 #ifdef EMLXS_BIG_ENDIAN 2701 uint8_t ProgType; 2702 uint8_t ProgId; 2703 uint16_t ProgVer:4; 2704 uint16_t ProgRev:4; 2705 uint16_t ProgFixLvl:2; 2706 uint16_t ProgDistType:2; 2707 uint16_t DistCnt:4; 2708 #endif 2709 #ifdef EMLXS_LITTLE_ENDIAN 2710 uint16_t DistCnt:4; 2711 uint16_t ProgDistType:2; 2712 uint16_t ProgFixLvl:2; 2713 uint16_t ProgRev:4; 2714 uint16_t ProgVer:4; 2715 uint8_t ProgId; 2716 uint8_t ProgType; 2717 #endif 2718 } b; 2719 } un; 2720 uint32_t endecRev; 2721 #ifdef EMLXS_BIG_ENDIAN 2722 uint8_t feaLevelHigh; 2723 uint8_t feaLevelLow; 2724 uint8_t fcphHigh; 2725 uint8_t fcphLow; 2726 #endif 2727 #ifdef EMLXS_LITTLE_ENDIAN 2728 uint8_t fcphLow; 2729 uint8_t fcphHigh; 2730 uint8_t feaLevelLow; 2731 uint8_t feaLevelHigh; 2732 #endif 2733 uint32_t postKernRev; 2734 uint32_t opFwRev; 2735 uint8_t opFwName[16]; 2736 2737 uint32_t sliFwRev1; 2738 uint8_t sliFwName1[16]; 2739 uint32_t sliFwRev2; 2740 uint8_t sliFwName2[16]; 2741 } READ_REV_VAR; 2742 2743 #define rxSeqRev postKernRev 2744 #define txSeqRev opFwRev 2745 2746 /* Structure for MB Command READ_LINK_STAT (18) */ 2747 2748 typedef struct 2749 { 2750 uint32_t rsvd1; 2751 uint32_t linkFailureCnt; 2752 uint32_t lossSyncCnt; 2753 2754 uint32_t lossSignalCnt; 2755 uint32_t primSeqErrCnt; 2756 uint32_t invalidXmitWord; 2757 uint32_t crcCnt; 2758 uint32_t primSeqTimeout; 2759 uint32_t elasticOverrun; 2760 uint32_t arbTimeout; 2761 2762 uint32_t rxBufCredit; 2763 uint32_t rxBufCreditCur; 2764 2765 uint32_t txBufCredit; 2766 uint32_t txBufCreditCur; 2767 2768 uint32_t EOFaCnt; 2769 uint32_t EOFdtiCnt; 2770 uint32_t EOFniCnt; 2771 uint32_t SOFfCnt; 2772 } READ_LNK_VAR; 2773 2774 2775 /* Structure for MB Command REG_LOGIN (19) */ 2776 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2777 2778 typedef struct 2779 { 2780 #ifdef EMLXS_BIG_ENDIAN 2781 uint16_t rsvd1; 2782 uint16_t rpi; 2783 uint32_t rsvd2:8; 2784 uint32_t did:24; 2785 #endif 2786 #ifdef EMLXS_LITTLE_ENDIAN 2787 uint16_t rpi; 2788 uint16_t rsvd1; 2789 uint32_t did:24; 2790 uint32_t rsvd2:8; 2791 #endif 2792 union 2793 { 2794 ULP_BDE sp; 2795 ULP_BDE64 sp64; 2796 } un; 2797 2798 #ifdef SLI3_SUPPORT 2799 #ifdef EMLXS_BIG_ENDIAN 2800 uint16_t rsvd6; 2801 uint16_t vpi; 2802 #endif 2803 #ifdef EMLXS_LITTLE_ENDIAN 2804 uint16_t vpi; 2805 uint16_t rsvd6; 2806 #endif 2807 #endif /* SLI3_SUPPORT */ 2808 } REG_LOGIN_VAR; 2809 2810 /* Word 30 contents for REG_LOGIN */ 2811 typedef union 2812 { 2813 struct 2814 { 2815 #ifdef EMLXS_BIG_ENDIAN 2816 uint16_t rsvd1:12; 2817 uint16_t class:4; 2818 uint16_t xri; 2819 #endif 2820 #ifdef EMLXS_LITTLE_ENDIAN 2821 uint16_t xri; 2822 uint16_t class:4; 2823 uint16_t rsvd1:12; 2824 #endif 2825 } f; 2826 uint32_t word; 2827 } REG_WD30; 2828 2829 2830 /* Structure for MB Command UNREG_LOGIN (20) */ 2831 2832 typedef struct 2833 { 2834 #ifdef EMLXS_BIG_ENDIAN 2835 uint16_t rsvd1; 2836 uint16_t rpi; 2837 #endif 2838 #ifdef EMLXS_LITTLE_ENDIAN 2839 uint16_t rpi; 2840 uint16_t rsvd1; 2841 #endif 2842 2843 #ifdef SLI3_SUPPORT 2844 uint32_t rsvd2; 2845 uint32_t rsvd3; 2846 uint32_t rsvd4; 2847 uint32_t rsvd5; 2848 #ifdef EMLXS_BIG_ENDIAN 2849 uint16_t rsvd6; 2850 uint16_t vpi; 2851 #endif 2852 #ifdef EMLXS_LITTLE_ENDIAN 2853 uint16_t vpi; 2854 uint16_t rsvd6; 2855 #endif 2856 #endif /* SLI3_SUPPORT */ 2857 } UNREG_LOGIN_VAR; 2858 2859 2860 /* Structure for MB Command UNREG_D_ID (0x23) */ 2861 2862 typedef struct 2863 { 2864 uint32_t did; 2865 2866 #ifdef SLI3_SUPPORT 2867 uint32_t rsvd2; 2868 uint32_t rsvd3; 2869 uint32_t rsvd4; 2870 uint32_t rsvd5; 2871 #ifdef EMLXS_BIG_ENDIAN 2872 uint16_t rsvd6; 2873 uint16_t vpi; 2874 #endif 2875 #ifdef EMLXS_LITTLE_ENDIAN 2876 uint16_t vpi; 2877 uint16_t rsvd6; 2878 #endif 2879 #endif /* SLI3_SUPPORT */ 2880 } UNREG_D_ID_VAR; 2881 2882 2883 /* Structure for MB Command READ_LA (21) */ 2884 /* Structure for MB Command READ_LA64 (0x95) */ 2885 2886 typedef struct 2887 { 2888 uint32_t eventTag; /* Event tag */ 2889 #ifdef EMLXS_BIG_ENDIAN 2890 uint32_t rsvd2:19; 2891 uint32_t fa:1; 2892 uint32_t mm:1; 2893 uint32_t tc:1; 2894 uint32_t pb:1; 2895 uint32_t il:1; 2896 uint32_t attType:8; 2897 #endif 2898 #ifdef EMLXS_LITTLE_ENDIAN 2899 uint32_t attType:8; 2900 uint32_t il:1; 2901 uint32_t pb:1; 2902 uint32_t tc:1; 2903 uint32_t mm:1; 2904 uint32_t fa:1; 2905 uint32_t rsvd2:19; 2906 #endif 2907 #define AT_RESERVED 0x00 /* Reserved - attType */ 2908 #define AT_LINK_UP 0x01 /* Link is up */ 2909 #define AT_LINK_DOWN 0x02 /* Link is down */ 2910 #ifdef EMLXS_BIG_ENDIAN 2911 uint8_t granted_AL_PA; 2912 uint8_t lipAlPs; 2913 uint8_t lipType; 2914 uint8_t topology; 2915 #endif 2916 #ifdef EMLXS_LITTLE_ENDIAN 2917 uint8_t topology; 2918 uint8_t lipType; 2919 uint8_t lipAlPs; 2920 uint8_t granted_AL_PA; 2921 #endif 2922 2923 /* lipType */ 2924 #define LT_PORT_INIT 0x00 /* An L_PORT initing (F7, AL_PS) - lipType */ 2925 #define LT_PORT_ERR 0x01 /* Err @L_PORT rcv'er (F8, AL_PS) */ 2926 #define LT_RESET_APORT 0x02 /* Lip Reset of some other port */ 2927 #define LT_RESET_MYPORT 0x03 /* Lip Reset of my port */ 2928 2929 /* topology */ 2930 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2931 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL (private) */ 2932 2933 union 2934 { 2935 ULP_BDE lilpBde; /* This BDE points to a */ 2936 /* 128 byte buffer to store */ 2937 /* the LILP AL_PA position */ 2938 /* map into */ 2939 ULP_BDE64 lilpBde64; 2940 } un; 2941 #ifdef EMLXS_BIG_ENDIAN 2942 uint32_t Dlu:1; 2943 uint32_t Dtf:1; 2944 uint32_t Drsvd2:14; 2945 uint32_t DlnkSpeed:8; 2946 uint32_t DnlPort:4; 2947 uint32_t Dtx:2; 2948 uint32_t Drx:2; 2949 #endif 2950 #ifdef EMLXS_LITTLE_ENDIAN 2951 uint32_t Drx:2; 2952 uint32_t Dtx:2; 2953 uint32_t DnlPort:4; 2954 uint32_t DlnkSpeed:8; 2955 uint32_t Drsvd2:14; 2956 uint32_t Dtf:1; 2957 uint32_t Dlu:1; 2958 #endif 2959 #ifdef EMLXS_BIG_ENDIAN 2960 uint32_t Ulu:1; 2961 uint32_t Utf:1; 2962 uint32_t Ursvd2:14; 2963 uint32_t UlnkSpeed:8; 2964 uint32_t UnlPort:4; 2965 uint32_t Utx:2; 2966 uint32_t Urx:2; 2967 #endif 2968 #ifdef EMLXS_LITTLE_ENDIAN 2969 uint32_t Urx:2; 2970 uint32_t Utx:2; 2971 uint32_t UnlPort:4; 2972 uint32_t UlnkSpeed:8; 2973 uint32_t Ursvd2:14; 2974 uint32_t Utf:1; 2975 uint32_t Ulu:1; 2976 #endif 2977 2978 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 2979 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 2980 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 2981 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 2982 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 2983 } READ_LA_VAR; 2984 2985 2986 /* Structure for MB Command CLEAR_LA (22) */ 2987 2988 typedef struct 2989 { 2990 uint32_t eventTag; /* Event tag */ 2991 uint32_t rsvd1; 2992 } CLEAR_LA_VAR; 2993 2994 /* Structure for MB Command DUMP */ 2995 2996 typedef struct 2997 { 2998 #ifdef EMLXS_BIG_ENDIAN 2999 uint32_t rsvd:25; 3000 uint32_t ra:1; 3001 uint32_t co:1; 3002 uint32_t cv:1; 3003 uint32_t type:4; 3004 3005 uint32_t entry_index:16; 3006 uint32_t region_id:16; 3007 #endif 3008 #ifdef EMLXS_LITTLE_ENDIAN 3009 uint32_t type:4; 3010 uint32_t cv:1; 3011 uint32_t co:1; 3012 uint32_t ra:1; 3013 uint32_t rsvd:25; 3014 3015 uint32_t region_id:16; 3016 uint32_t entry_index:16; 3017 #endif 3018 uint32_t base_adr; 3019 uint32_t word_cnt; 3020 uint32_t resp_offset; 3021 } DUMP_VAR; 3022 3023 /* 3024 * Dump type 3025 */ 3026 #define DMP_MEM_REG 0x1 3027 #define DMP_NV_PARAMS 0x2 3028 3029 /* 3030 * Dump region ID 3031 */ 3032 #define NODE_CFG_A_REGION_ID 0 3033 #define NODE_CFG_B_REGION_ID 1 3034 #define NODE_CFG_C_REGION_ID 2 3035 #define NODE_CFG_D_REGION_ID 3 3036 #define WAKE_UP_PARMS_REGION_ID 4 3037 #define DEF_PCI_CFG_REGION_ID 5 3038 #define PCI_CFG_1_REGION_ID 6 3039 #define PCI_CFG_2_REGION_ID 7 3040 #define RSVD1_REGION_ID 8 3041 #define RSVD2_REGION_ID 9 3042 #define RSVD3_REGION_ID 10 3043 #define RSVD4_REGION_ID 11 3044 #define RSVD5_REGION_ID 12 3045 #define RSVD6_REGION_ID 13 3046 #define RSVD7_REGION_ID 14 3047 #define DIAG_TRACE_REGION_ID 15 3048 #define WWN_REGION_ID 16 3049 3050 #define DMP_VPD_REGION 14 3051 #define DMP_VPD_SIZE 1024 3052 #define DMP_VPD_DUMP_WCOUNT 24 3053 3054 3055 3056 /* Structure for MB Command UPDATE_CFG */ 3057 3058 typedef struct 3059 { 3060 #ifdef EMLXS_BIG_ENDIAN 3061 uint32_t rsvd2:16; 3062 uint32_t proc_type:8; 3063 uint32_t rsvd1:1; 3064 uint32_t Abit:1; 3065 uint32_t Obit:1; 3066 uint32_t Vbit:1; 3067 uint32_t req_type:4; 3068 #define INIT_REGION 1 3069 #define UPDATE_DATA 2 3070 #define CLEAN_UP_CFG 3 3071 uint32_t entry_len:16; 3072 uint32_t region_id:16; 3073 #endif 3074 3075 #ifdef EMLXS_LITTLE_ENDIAN 3076 uint32_t req_type:4; 3077 #define INIT_REGION 1 3078 #define UPDATE_DATA 2 3079 #define CLEAN_UP_CFG 3 3080 uint32_t Vbit:1; 3081 uint32_t Obit:1; 3082 uint32_t Abit:1; 3083 uint32_t rsvd1:1; 3084 uint32_t proc_type:8; 3085 uint32_t rsvd2:16; 3086 3087 uint32_t region_id:16; 3088 uint32_t entry_len:16; 3089 #endif 3090 3091 uint32_t rsp_info; 3092 uint32_t byte_len; 3093 uint32_t cfg_data; 3094 } UPDATE_CFG_VAR; 3095 3096 /* Structure for MB Command DEL_LD_ENTRY (29) */ 3097 3098 typedef struct 3099 { 3100 #ifdef EMLXS_LITTLE_ENDIAN 3101 uint32_t list_req:2; 3102 uint32_t list_rsp:2; 3103 uint32_t rsvd:28; 3104 #else 3105 uint32_t rsvd:28; 3106 uint32_t list_rsp:2; 3107 uint32_t list_req:2; 3108 #endif 3109 3110 #define FLASH_LOAD_LIST 1 3111 #define RAM_LOAD_LIST 2 3112 #define BOTH_LISTS 3 3113 3114 PROG_ID prog_id; 3115 } DEL_LD_ENTRY_VAR; 3116 3117 /* Structure for MB Command LOAD_AREA (81) */ 3118 typedef struct 3119 { 3120 #ifdef EMLXS_LITTLE_ENDIAN 3121 uint32_t load_cmplt:1; 3122 uint32_t method:1; 3123 uint32_t rsvd1:1; 3124 uint32_t update_flash:1; 3125 uint32_t erase_or_prog:1; 3126 uint32_t version:1; 3127 uint32_t rsvd2:2; 3128 uint32_t progress:8; 3129 uint32_t step:8; 3130 uint32_t area_id:8; 3131 #else 3132 uint32_t area_id:8; 3133 uint32_t step:8; 3134 uint32_t progress:8; 3135 uint32_t rsvd2:2; 3136 uint32_t version:1; 3137 uint32_t erase_or_prog:1; 3138 uint32_t update_flash:1; 3139 uint32_t rsvd1:1; 3140 uint32_t method:1; 3141 uint32_t load_cmplt:1; 3142 #endif 3143 uint32_t dl_to_adr; 3144 uint32_t dl_len; 3145 union 3146 { 3147 uint32_t dl_from_slim_offset; 3148 ULP_BDE dl_from_bde; 3149 ULP_BDE64 dl_from_bde64; 3150 PROG_ID prog_id; 3151 } un; 3152 } LOAD_AREA_VAR; 3153 3154 /* Structure for MB Command LOAD_EXP_ROM (9C) */ 3155 typedef struct 3156 { 3157 #ifdef EMLXS_LITTLE_ENDIAN 3158 uint32_t rsvd1:8; 3159 uint32_t progress:8; 3160 uint32_t step:8; 3161 uint32_t rsvd2:8; 3162 #else 3163 uint32_t rsvd2:8; 3164 uint32_t step:8; 3165 uint32_t progress:8; 3166 uint32_t rsvd1:8; 3167 #endif 3168 uint32_t dl_to_adr; 3169 uint32_t rsvd3; 3170 union 3171 { 3172 uint32_t word[2]; 3173 PROG_ID prog_id; 3174 } un; 3175 } LOAD_EXP_ROM_VAR; 3176 3177 3178 /* Structure for MB Command CONFIG_HBQ (7C) */ 3179 3180 typedef struct 3181 { 3182 #ifdef EMLXS_BIG_ENDIAN 3183 uint32_t rsvd1:7; 3184 uint32_t recvNotify:1; /* Receive Notification */ 3185 uint32_t numMask:8; /* # Mask Entries */ 3186 uint32_t profile:8; /* Selection Profile */ 3187 uint32_t rsvd2:8; 3188 #endif 3189 #ifdef EMLXS_LITTLE_ENDIAN 3190 uint32_t rsvd2:8; 3191 uint32_t profile:8; /* Selection Profile */ 3192 uint32_t numMask:8; /* # Mask Entries */ 3193 uint32_t recvNotify:1; /* Receive Notification */ 3194 uint32_t rsvd1:7; 3195 #endif 3196 3197 #ifdef EMLXS_BIG_ENDIAN 3198 uint32_t hbqId:16; 3199 uint32_t rsvd3:12; 3200 uint32_t ringMask:4; 3201 #endif 3202 #ifdef EMLXS_LITTLE_ENDIAN 3203 uint32_t ringMask:4; 3204 uint32_t rsvd3:12; 3205 uint32_t hbqId:16; 3206 #endif 3207 3208 #ifdef EMLXS_BIG_ENDIAN 3209 uint32_t numEntries:16; 3210 uint32_t rsvd4:8; 3211 uint32_t headerLen:8; 3212 #endif 3213 #ifdef EMLXS_LITTLE_ENDIAN 3214 uint32_t headerLen:8; 3215 uint32_t rsvd4:8; 3216 uint32_t numEntries:16; 3217 #endif 3218 3219 uint32_t hbqaddrLow; 3220 uint32_t hbqaddrHigh; 3221 3222 #ifdef EMLXS_BIG_ENDIAN 3223 uint32_t rsvd5:31; 3224 uint32_t logEntry:1; 3225 #endif 3226 #ifdef EMLXS_LITTLE_ENDIAN 3227 uint32_t logEntry:1; 3228 uint32_t rsvd5:31; 3229 #endif 3230 3231 uint32_t rsvd6; /* w7 */ 3232 uint32_t rsvd7; /* w8 */ 3233 uint32_t rsvd8; /* w9 */ 3234 3235 HBQ_MASK hbqMasks[6]; 3236 3237 union 3238 { 3239 uint32_t allprofiles[12]; 3240 3241 struct 3242 { 3243 #ifdef EMLXS_BIG_ENDIAN 3244 uint32_t seqlenoff:16; 3245 uint32_t maxlen:16; 3246 #endif 3247 #ifdef EMLXS_LITTLE_ENDIAN 3248 uint32_t maxlen:16; 3249 uint32_t seqlenoff:16; 3250 #endif 3251 #ifdef EMLXS_BIG_ENDIAN 3252 uint32_t rsvd1:28; 3253 uint32_t seqlenbcnt:4; 3254 #endif 3255 #ifdef EMLXS_LITTLE_ENDIAN 3256 uint32_t seqlenbcnt:4; 3257 uint32_t rsvd1:28; 3258 #endif 3259 uint32_t rsvd[10]; 3260 } profile2; 3261 3262 struct 3263 { 3264 #ifdef EMLXS_BIG_ENDIAN 3265 uint32_t seqlenoff:16; 3266 uint32_t maxlen:16; 3267 #endif 3268 #ifdef EMLXS_LITTLE_ENDIAN 3269 uint32_t maxlen:16; 3270 uint32_t seqlenoff:16; 3271 #endif 3272 #ifdef EMLXS_BIG_ENDIAN 3273 uint32_t cmdcodeoff:28; 3274 uint32_t rsvd1:12; 3275 uint32_t seqlenbcnt:4; 3276 #endif 3277 #ifdef EMLXS_LITTLE_ENDIAN 3278 uint32_t seqlenbcnt:4; 3279 uint32_t rsvd1:12; 3280 uint32_t cmdcodeoff:28; 3281 #endif 3282 uint32_t cmdmatch[8]; 3283 3284 uint32_t rsvd[2]; 3285 } profile3; 3286 3287 struct 3288 { 3289 #ifdef EMLXS_BIG_ENDIAN 3290 uint32_t seqlenoff:16; 3291 uint32_t maxlen:16; 3292 #endif 3293 #ifdef EMLXS_LITTLE_ENDIAN 3294 uint32_t maxlen:16; 3295 uint32_t seqlenoff:16; 3296 #endif 3297 #ifdef EMLXS_BIG_ENDIAN 3298 uint32_t cmdcodeoff:28; 3299 uint32_t rsvd1:12; 3300 uint32_t seqlenbcnt:4; 3301 #endif 3302 #ifdef EMLXS_LITTLE_ENDIAN 3303 uint32_t seqlenbcnt:4; 3304 uint32_t rsvd1:12; 3305 uint32_t cmdcodeoff:28; 3306 #endif 3307 uint32_t cmdmatch[8]; 3308 3309 uint32_t rsvd[2]; 3310 } profile5; 3311 } profiles; 3312 } CONFIG_HBQ_VAR; 3313 3314 3315 /* Structure for MB Command REG_VPI(0x96) */ 3316 typedef struct 3317 { 3318 #ifdef EMLXS_BIG_ENDIAN 3319 uint32_t rsvd1; 3320 uint32_t rsvd2:8; 3321 uint32_t sid:24; 3322 uint32_t rsvd3; 3323 uint32_t rsvd4; 3324 uint32_t rsvd5; 3325 uint16_t rsvd6; 3326 uint16_t vpi; 3327 #endif 3328 #ifdef EMLXS_LITTLE_ENDIAN 3329 uint32_t rsvd1; 3330 uint32_t sid:24; 3331 uint32_t rsvd2:8; 3332 uint32_t rsvd3; 3333 uint32_t rsvd4; 3334 uint32_t rsvd5; 3335 uint16_t vpi; 3336 uint16_t rsvd6; 3337 #endif 3338 } REG_VPI_VAR; 3339 3340 /* Structure for MB Command UNREG_VPI (0x97) */ 3341 typedef struct 3342 { 3343 uint32_t rsvd1; 3344 uint32_t rsvd2; 3345 uint32_t rsvd3; 3346 uint32_t rsvd4; 3347 uint32_t rsvd5; 3348 #ifdef EMLXS_BIG_ENDIAN 3349 uint16_t rsvd6; 3350 uint16_t vpi; 3351 #endif 3352 #ifdef EMLXS_LITTLE_ENDIAN 3353 uint16_t vpi; 3354 uint16_t rsvd6; 3355 #endif 3356 } UNREG_VPI_VAR; 3357 3358 3359 typedef struct 3360 { 3361 #ifdef EMLXS_BIG_ENDIAN 3362 uint32_t read_log:1; 3363 uint32_t clear_log:1; 3364 uint32_t mbox_rsp:1; 3365 uint32_t resv:28; 3366 #endif 3367 #ifdef EMLXS_LITTLE_ENDIAN 3368 uint32_t resv:28; 3369 uint32_t mbox_rsp:1; 3370 uint32_t clear_log:1; 3371 uint32_t read_log:1; 3372 #endif 3373 3374 uint32_t offset; 3375 3376 union 3377 { 3378 ULP_BDE sp; 3379 ULP_BDE64 sp64; 3380 } un; 3381 } READ_EVT_LOG_VAR; 3382 3383 typedef struct 3384 { 3385 3386 #ifdef EMLXS_BIG_ENDIAN 3387 uint16_t split_log_next; 3388 uint16_t log_next; 3389 3390 uint32_t size; 3391 3392 uint32_t format:8; 3393 uint32_t resv2:22; 3394 uint32_t log_level:1; 3395 uint32_t split_log:1; 3396 #endif 3397 #ifdef EMLXS_LITTLE_ENDIAN 3398 uint16_t log_next; 3399 uint16_t split_log_next; 3400 3401 uint32_t size; 3402 3403 uint32_t split_log:1; 3404 uint32_t log_level:1; 3405 uint32_t resv2:22; 3406 uint32_t format:8; 3407 #endif 3408 3409 uint32_t offset; 3410 } LOG_STATUS_VAR; 3411 3412 /* Structure for MB Command CONFIG_PORT (0x88) */ 3413 3414 3415 #ifdef SLI3_SUPPORT 3416 3417 typedef struct 3418 { 3419 #ifdef EMLXS_BIG_ENDIAN 3420 uint32_t cBE:1; 3421 uint32_t cET:1; 3422 uint32_t cHpcb:1; 3423 uint32_t rMA:1; 3424 uint32_t sli_mode:4; 3425 uint32_t pcbLen:24; /* bit 23:0 of memory based port */ 3426 /* config block */ 3427 #endif 3428 #ifdef EMLXS_LITTLE_ENDIAN 3429 uint32_t pcbLen:24; /* bit 23:0 of memory based port */ 3430 /* config block */ 3431 uint32_t sli_mode:4; 3432 uint32_t rMA:1; 3433 uint32_t cHpcb:1; 3434 uint32_t cET:1; 3435 uint32_t cBE:1; 3436 #endif 3437 3438 uint32_t pcbLow; /* bit 31:0 of memory based port */ 3439 /* config block */ 3440 uint32_t pcbHigh; /* bit 63:32 of memory based port */ 3441 /* config block */ 3442 uint32_t hbainit[5]; 3443 3444 #ifdef EMLXS_BIG_ENDIAN 3445 uint32_t hps:1; /* Host pointers in SLIM */ 3446 uint32_t rsvd:31; 3447 #endif 3448 #ifdef EMLXS_LITTLE_ENDIAN 3449 uint32_t rsvd:31; 3450 uint32_t hps:1; /* Host pointers in SLIM */ 3451 #endif 3452 3453 #ifdef EMLXS_BIG_ENDIAN 3454 uint32_t rsvd1:24; 3455 uint32_t cmv:1; /* Configure Max VPIs */ 3456 uint32_t ccrp:1; /* Config Command Ring Polling */ 3457 uint32_t csah:1; /* Configure Synchronous Abort */ 3458 /* Handling */ 3459 uint32_t chbs:1; /* Cofigure Host Backing store */ 3460 uint32_t cinb:1; /* Enable Interrupt Notification */ 3461 /* Block */ 3462 uint32_t cerbm:1; /* Configure Enhanced Receive */ 3463 /* Buffer Management */ 3464 uint32_t cmx:1; /* Configure Max XRIs */ 3465 uint32_t cmr:1; /* Configure Max RPIs */ 3466 #endif 3467 #ifdef EMLXS_LITTLE_ENDIAN 3468 uint32_t cmr:1; /* Configure Max RPIs */ 3469 uint32_t cmx:1; /* Configure Max XRIs */ 3470 uint32_t cerbm:1; /* Configure Enhanced Receive */ 3471 /* Buffer Management */ 3472 uint32_t cinb:1; /* Enable Interrupt Notification */ 3473 /* Block */ 3474 uint32_t chbs:1; /* Cofigure Host Backing store */ 3475 uint32_t csah:1; /* Configure Synchronous Abort */ 3476 /* Handling */ 3477 uint32_t ccrp:1; /* Config Command Ring Polling */ 3478 uint32_t cmv:1; /* Configure Max VPIs */ 3479 uint32_t rsvd1:24; 3480 #endif 3481 #ifdef EMLXS_BIG_ENDIAN 3482 uint32_t rsvd2:24; 3483 uint32_t gmv:1; /* Grant Max VPIs */ 3484 uint32_t gcrp:1; /* Grant Command Ring Polling */ 3485 uint32_t gsah:1; /* Grant Synchronous Abort Handling */ 3486 uint32_t ghbs:1; /* Grant Host Backing Store */ 3487 uint32_t ginb:1; /* Grant Interrupt Notification Block */ 3488 uint32_t gerbm:1; /* Grant ERBM Request */ 3489 uint32_t gmx:1; /* Grant Max XRIs */ 3490 uint32_t gmr:1; /* Grant Max RPIs */ 3491 #endif 3492 #ifdef EMLXS_LITTLE_ENDIAN 3493 uint32_t gmr:1; /* Grant Max RPIs */ 3494 uint32_t gmx:1; /* Grant Max XRIs */ 3495 uint32_t gerbm:1; /* Grant ERBM Request */ 3496 uint32_t ginb:1; /* Grant Interrupt Notification Block */ 3497 uint32_t ghbs:1; /* Grant Host Backing Store */ 3498 uint32_t gsah:1; /* Grant Synchronous Abort Handling */ 3499 uint32_t gcrp:1; /* Grant Command Ring Polling */ 3500 uint32_t gmv:1; /* Grant Max VPIs */ 3501 uint32_t rsvd2:24; 3502 #endif 3503 3504 #ifdef EMLXS_BIG_ENDIAN 3505 uint32_t max_rpi:16; /* Max RPIs Port should configure */ 3506 uint32_t max_xri:16; /* Max XRIs Port should configure */ 3507 #endif 3508 #ifdef EMLXS_LITTLE_ENDIAN 3509 uint32_t max_xri:16; /* Max XRIs Port should configure */ 3510 uint32_t max_rpi:16; /* Max RPIs Port should configure */ 3511 #endif 3512 3513 #ifdef EMLXS_BIG_ENDIAN 3514 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */ 3515 uint32_t rsvd3:16; /* Max HBQs Host expect to configure */ 3516 #endif 3517 #ifdef EMLXS_LITTLE_ENDIAN 3518 uint32_t rsvd3:16; /* Max HBQs Host expect to configure */ 3519 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */ 3520 #endif 3521 3522 uint32_t rsvd4; /* Reserved */ 3523 3524 #ifdef EMLXS_BIG_ENDIAN 3525 uint32_t rsvd5:16; /* Reserved */ 3526 uint32_t vpi_max:16; /* Max number of virt N-Ports */ 3527 #endif 3528 #ifdef EMLXS_LITTLE_ENDIAN 3529 uint32_t vpi_max:16; /* Max number of virt N-Ports */ 3530 uint32_t rsvd5:16; /* Reserved */ 3531 #endif 3532 } CONFIG_PORT_VAR; 3533 3534 #else /* !SLI3_SUPPORT */ 3535 3536 typedef struct 3537 { 3538 uint32_t pcbLen; 3539 uint32_t pcbLow; /* bit 31:0 of memory based port */ 3540 /* config block */ 3541 uint32_t pcbHigh; /* bit 63:32 of memory based port */ 3542 /* config block */ 3543 uint32_t hbainit; 3544 } CONFIG_PORT_VAR; 3545 3546 #endif /* SLI3_SUPPORT */ 3547 3548 3549 3550 /* SLI-2 Port Control Block */ 3551 3552 /* SLIM POINTER */ 3553 #define SLIMOFF 0x30 /* WORD */ 3554 3555 typedef struct _SLI2_RDSC 3556 { 3557 uint32_t cmdEntries; 3558 uint32_t cmdAddrLow; 3559 uint32_t cmdAddrHigh; 3560 3561 uint32_t rspEntries; 3562 uint32_t rspAddrLow; 3563 uint32_t rspAddrHigh; 3564 } SLI2_RDSC; 3565 3566 typedef struct _PCB 3567 { 3568 #ifdef EMLXS_BIG_ENDIAN 3569 uint32_t type:8; 3570 #define TYPE_NATIVE_SLI2 0x01; 3571 uint32_t feature:8; 3572 #define FEATURE_INITIAL_SLI2 0x01; 3573 uint32_t rsvd:12; 3574 uint32_t maxRing:4; 3575 #endif 3576 #ifdef EMLXS_LITTLE_ENDIAN 3577 uint32_t maxRing:4; 3578 uint32_t rsvd:12; 3579 uint32_t feature:8; 3580 #define FEATURE_INITIAL_SLI2 0x01; 3581 uint32_t type:8; 3582 #define TYPE_NATIVE_SLI2 0x01; 3583 #endif 3584 3585 uint32_t mailBoxSize; 3586 uint32_t mbAddrLow; 3587 uint32_t mbAddrHigh; 3588 3589 uint32_t hgpAddrLow; 3590 uint32_t hgpAddrHigh; 3591 3592 uint32_t pgpAddrLow; 3593 uint32_t pgpAddrHigh; 3594 SLI2_RDSC rdsc[MAX_RINGS_AVAILABLE]; 3595 } PCB; 3596 3597 /* NEW_FEATURE */ 3598 typedef struct 3599 { 3600 #ifdef EMLXS_BIG_ENDIAN 3601 uint32_t rsvd0:27; 3602 uint32_t discardFarp:1; 3603 uint32_t IPEnable:1; 3604 uint32_t nodeName:1; 3605 uint32_t portName:1; 3606 uint32_t filterEnable:1; 3607 #endif 3608 #ifdef EMLXS_LITTLE_ENDIAN 3609 uint32_t filterEnable:1; 3610 uint32_t portName:1; 3611 uint32_t nodeName:1; 3612 uint32_t IPEnable:1; 3613 uint32_t discardFarp:1; 3614 uint32_t rsvd:27; 3615 #endif 3616 NAME_TYPE portname; 3617 NAME_TYPE nodename; 3618 uint32_t rsvd1; 3619 uint32_t rsvd2; 3620 uint32_t rsvd3; 3621 uint32_t IPAddress; 3622 } CONFIG_FARP_VAR; 3623 3624 3625 /* NEW_FEATURE */ 3626 typedef struct 3627 { 3628 #ifdef EMLXS_BIG_ENDIAN 3629 uint32_t defaultMessageNumber:16; 3630 uint32_t rsvd1:3; 3631 uint32_t nid:5; 3632 uint32_t rsvd2:5; 3633 uint32_t defaultPresent:1; 3634 uint32_t addAssociations:1; 3635 uint32_t reportAssociations:1; 3636 #endif 3637 #ifdef EMLXS_LITTLE_ENDIAN 3638 uint32_t reportAssociations:1; 3639 uint32_t addAssociations:1; 3640 uint32_t defaultPresent:1; 3641 uint32_t rsvd2:5; 3642 uint32_t nid:5; 3643 uint32_t rsvd1:3; 3644 uint32_t defaultMessageNumber:16; 3645 #endif 3646 uint32_t attConditions; 3647 uint8_t attentionId[16]; 3648 uint16_t messageNumberByHA[32]; 3649 uint16_t messageNumberByID[16]; 3650 uint32_t rsvd3; 3651 } CONFIG_MSI_VAR; 3652 3653 3654 /* NEW_FEATURE */ 3655 typedef struct 3656 { 3657 #ifdef EMLXS_BIG_ENDIAN 3658 uint32_t defaultMessageNumber:8; 3659 uint32_t rsvd1:11; 3660 uint32_t nid:5; 3661 uint32_t rsvd2:5; 3662 uint32_t defaultPresent:1; 3663 uint32_t addAssociations:1; 3664 uint32_t reportAssociations:1; 3665 #endif 3666 #ifdef EMLXS_LITTLE_ENDIAN 3667 uint32_t reportAssociations:1; 3668 uint32_t addAssociations:1; 3669 uint32_t defaultPresent:1; 3670 uint32_t rsvd2:5; 3671 uint32_t nid:5; 3672 uint32_t rsvd1:11; 3673 uint32_t defaultMessageNumber:8; 3674 #endif 3675 uint32_t attConditions1; 3676 uint32_t attConditions2; 3677 uint8_t attentionId[16]; 3678 uint8_t messageNumberByHA[64]; 3679 uint8_t messageNumberByID[16]; 3680 uint32_t autoClearByHA1; 3681 uint32_t autoClearByHA2; 3682 uint32_t autoClearByID; 3683 uint32_t resv3; 3684 } CONFIG_MSIX_VAR; 3685 3686 3687 /* Union of all Mailbox Command types */ 3688 3689 typedef union 3690 { 3691 uint32_t varWords[31]; 3692 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3693 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3694 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3695 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3696 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3697 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3698 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3699 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3700 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3701 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3702 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3703 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3704 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3705 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3706 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3707 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3708 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3709 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3710 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3711 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3712 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 3713 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3714 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3715 UPDATE_CFG_VAR varUpdateCfg; /* cmd = 0x1b Warm Start */ 3716 /* UPDATE_CFG cmd */ 3717 DEL_LD_ENTRY_VAR varDelLdEntry; /* cmd = 0x1d (DEL_LD_ENTRY) */ 3718 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3719 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) */ 3720 CONFIG_MSI_VAR varCfgMSI; /* cmd = 0x90 (CONFIG_MSI) */ 3721 CONFIG_MSIX_VAR varCfgMSIX; /* cmd = 0x30 (CONFIG_MSIX) */ 3722 CONFIG_HBQ_VAR varCfgHbq; /* cmd = 0x7C (CONFIG_HBQ) */ 3723 LOAD_AREA_VAR varLdArea; /* cmd = 0x81 (LOAD_AREA) */ 3724 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3725 LOAD_EXP_ROM_VAR varLdExpRom; /* cmd = 0x9C (LOAD_XP_ROM) */ 3726 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3727 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3728 READ_EVT_LOG_VAR varRdEvtLog; /* cmd = 0x38 (READ_EVT_LOG) */ 3729 LOG_STATUS_VAR varLogStat; /* cmd = 0x37 */ 3730 3731 } MAILVARIANTS; 3732 3733 #define MAILBOX_CMD_BSIZE 128 3734 #define MAILBOX_CMD_WSIZE 32 3735 3736 3737 /* 3738 * SLI-2 specific structures 3739 */ 3740 3741 typedef struct _SLI1_DESC 3742 { 3743 emlxs_rings_t mbxCring[4]; 3744 uint32_t mbxUnused[24]; 3745 } SLI1_DESC; /* 128 bytes */ 3746 3747 typedef struct 3748 { 3749 uint32_t cmdPutInx; 3750 uint32_t rspGetInx; 3751 } HGP; 3752 3753 typedef struct 3754 { 3755 uint32_t cmdGetInx; 3756 uint32_t rspPutInx; 3757 } PGP; 3758 3759 #ifdef SLI3_SUPPORT 3760 typedef struct _SLI2_DESC 3761 { 3762 HGP host[4]; 3763 PGP port[4]; 3764 uint32_t HBQ_PortGetIdx[16]; 3765 } SLI2_DESC; /* 128 bytes */ 3766 #else 3767 typedef struct _SLI2_DESC 3768 { 3769 HGP host[4]; /* 8 words */ 3770 uint32_t unused[16]; 3771 PGP port[4]; /* 8 words */ 3772 } SLI2_DESC; /* 128 bytes */ 3773 #endif /* SLI3_SUPPORT */ 3774 3775 typedef union 3776 { 3777 SLI1_DESC s1; /* 32 words, 128 bytes */ 3778 SLI2_DESC s2; /* 32 words, 128 bytes */ 3779 } SLI_VAR; 3780 3781 typedef volatile struct 3782 { 3783 #ifdef EMLXS_BIG_ENDIAN 3784 uint16_t mbxStatus; 3785 uint8_t mbxCommand; 3786 uint8_t mbxReserved:6; 3787 uint8_t mbxHc:1; 3788 uint8_t mbxOwner:1; /* Low order bit first word */ 3789 #endif 3790 #ifdef EMLXS_LITTLE_ENDIAN 3791 uint8_t mbxOwner:1; /* Low order bit first word */ 3792 uint8_t mbxHc:1; 3793 uint8_t mbxReserved:6; 3794 uint8_t mbxCommand; 3795 uint16_t mbxStatus; 3796 #endif 3797 MAILVARIANTS un; /* 124 bytes */ 3798 SLI_VAR us; /* 128 bytes */ 3799 } MAILBOX; /* 256 bytes */ 3800 3801 /* 3802 * End Structure Definitions for Mailbox Commands 3803 */ 3804 3805 3806 /* 3807 * Begin Structure Definitions for IOCB Commands 3808 */ 3809 3810 typedef struct 3811 { 3812 #ifdef EMLXS_BIG_ENDIAN 3813 uint8_t statAction; 3814 uint8_t statRsn; 3815 uint8_t statBaExp; 3816 uint8_t statLocalError; 3817 #endif 3818 #ifdef EMLXS_LITTLE_ENDIAN 3819 uint8_t statLocalError; 3820 uint8_t statBaExp; 3821 uint8_t statRsn; 3822 uint8_t statAction; 3823 #endif 3824 /* statAction FBSY reason codes */ 3825 #define FBSY_RSN_MASK 0xF0 /* Rsn stored in upper nibble */ 3826 #define FBSY_FABRIC_BSY 0x10 /* F_bsy due to Fabric BSY */ 3827 #define FBSY_NPORT_BSY 0x30 /* F_bsy due to N_port BSY */ 3828 3829 /* statAction PBSY action codes */ 3830 #define PBSY_ACTION1 0x01 /* Sequence terminated - retry */ 3831 #define PBSY_ACTION2 0x02 /* Sequence active - retry */ 3832 3833 /* statAction P/FRJT action codes */ 3834 #define RJT_RETRYABLE 0x01 /* Retryable class of error */ 3835 #define RJT_NO_RETRY 0x02 /* Non-Retryable class of error */ 3836 3837 /* statRsn LS_RJT reason codes defined in LS_RJT structure */ 3838 3839 /* statRsn P_BSY reason codes */ 3840 #define PBSY_NPORT_BSY 0x01 /* Physical N_port BSY */ 3841 #define PBSY_RESRCE_BSY 0x03 /* N_port resource BSY */ 3842 #define PBSY_VU_BSY 0xFF /* See VU field for rsn */ 3843 3844 /* statRsn P/F_RJT reason codes */ 3845 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3846 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3847 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3848 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3849 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3850 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3851 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3852 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3853 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3854 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3855 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3856 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3857 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3858 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3859 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3860 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3861 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3862 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3863 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3864 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3865 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3866 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3867 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3868 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3869 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3870 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3871 3872 /* statRsn BA_RJT reason codes */ 3873 #define BARJT_BAD_CMD_CODE 0x01 /* Invalid command code */ 3874 #define BARJT_LOGICAL_ERR 0x03 /* Logical error */ 3875 #define BARJT_LOGICAL_BSY 0x05 /* Logical busy */ 3876 #define BARJT_PROTOCOL_ERR 0x07 /* Protocol error */ 3877 #define BARJT_VU_ERR 0xFF /* Vendor unique error */ 3878 3879 /* LS_RJT reason explanation defined in LS_RJT structure */ 3880 3881 /* BA_RJT reason explanation */ 3882 #define BARJT_EXP_INVALID_ID 0x01 /* Invalid OX_ID/RX_ID */ 3883 #define BARJT_EXP_ABORT_SEQ 0x05 /* Abort SEQ, no more info */ 3884 3885 /* Local Reject errors */ 3886 #define IOERR_SUCCESS 0x00 3887 #define IOERR_MISSING_CONTINUE 0x01 3888 #define IOERR_SEQUENCE_TIMEOUT 0x02 3889 #define IOERR_INTERNAL_ERROR 0x03 3890 #define IOERR_INVALID_RPI 0x04 3891 #define IOERR_NO_XRI 0x05 3892 #define IOERR_ILLEGAL_COMMAND 0x06 3893 #define IOERR_XCHG_DROPPED 0x07 3894 #define IOERR_ILLEGAL_FIELD 0x08 3895 /* RESERVED 0x09 */ 3896 /* RESERVED 0x0A */ 3897 #define IOERR_RCV_BUFFER_WAITING 0x0B 3898 /* RESERVED 0x0C */ 3899 #define IOERR_TX_DMA_FAILED 0x0D 3900 #define IOERR_RX_DMA_FAILED 0x0E 3901 #define IOERR_ILLEGAL_FRAME 0x0F 3902 3903 /* RESERVED 0x10 */ 3904 #define IOERR_NO_RESOURCES 0x11 3905 /* RESERVED 0x12 */ 3906 #define IOERR_ILLEGAL_LENGTH 0x13 3907 #define IOERR_UNSUPPORTED_FEATURE 0x14 3908 #define IOERR_ABORT_IN_PROGRESS 0x15 3909 #define IOERR_ABORT_REQUESTED 0x16 3910 #define IOERR_RCV_BUFFER_TIMEOUT 0x17 3911 #define IOERR_LOOP_OPEN_FAILURE 0x18 3912 #define IOERR_RING_RESET 0x19 3913 #define IOERR_LINK_DOWN 0x1A 3914 #define IOERR_CORRUPTED_DATA 0x1B 3915 #define IOERR_CORRUPTED_RPI 0x1C 3916 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3917 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3918 #define IOERR_DUP_FRAME 0x1F 3919 3920 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3921 #define IOERR_BAD_HOST_ADDRESS 0x21 3922 #define IOERR_RCV_HDRBUF_WAITING 0x22 3923 #define IOERR_MISSING_HDR_BUFFER 0x23 3924 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3925 #define IOERR_ABORTMULT_REQUESTED 0x25 3926 /* RESERVED 0x26 */ 3927 /* RESERVED 0x27 */ 3928 #define IOERR_BUFFER_SHORTAGE 0x28 3929 #define IOERR_XRIBUF_WAITING 0x29 3930 /* RESERVED 0x2A */ 3931 #define IOERR_MISSING_HBQ_ENTRY 0x2B 3932 #define IOERR_ABORT_EXT_REQ 0x2C 3933 #define IOERR_CLOSE_EXT_REQ 0x2D 3934 /* RESERVED 0x2E */ 3935 /* RESERVED 0x2F */ 3936 3937 #define IOERR_XRIBUF_MISSING 0x30 3938 #define IOERR_ASSI_RSP_SUPPRESSED 0x31 3939 /* RESERVED 0x32 - 0x3F */ 3940 3941 #define IOERR_ROFFSET_INVAL 0x40 3942 #define IOERR_ROFFSET_MISSING 0x41 3943 #define IOERR_INSUF_BUFFER 0x42 3944 #define IOERR_MISSING_SI 0x43 3945 #define IOERR_MISSING_ES 0x44 3946 #define IOERR_INCOMP_XFER 0x45 3947 /* RESERVED 0x46 - 0xFF */ 3948 3949 /* Driver defined */ 3950 #define IOERR_ABORT_TIMEOUT 0xF0 3951 } PARM_ERR; 3952 3953 typedef union 3954 { 3955 struct 3956 { 3957 #ifdef EMLXS_BIG_ENDIAN 3958 uint8_t Rctl; /* R_CTL field */ 3959 uint8_t Type; /* TYPE field */ 3960 uint8_t Dfctl; /* DF_CTL field */ 3961 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3962 #endif 3963 #ifdef EMLXS_LITTLE_ENDIAN 3964 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3965 uint8_t Dfctl; /* DF_CTL field */ 3966 uint8_t Type; /* TYPE field */ 3967 uint8_t Rctl; /* R_CTL field */ 3968 #endif 3969 #define FCP_RTYPE 0x08 /* FCP_TARGET_MODE Type - Rctl */ 3970 3971 #define BC 0x02 /* Broadcast Received - Fctl */ 3972 #define SI 0x04 /* Sequence Initiative */ 3973 #define LA 0x08 /* Ignore Link Attention state */ 3974 #define FSEQ 0x40 /* First Sequence */ 3975 #define LSEQ 0x80 /* Last Sequence */ 3976 } hcsw; 3977 uint32_t reserved; 3978 } WORD5; 3979 3980 3981 /* IOCB Command template for a generic response */ 3982 typedef struct 3983 { 3984 uint32_t reserved[4]; 3985 PARM_ERR perr; 3986 } GENERIC_RSP; 3987 3988 3989 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3990 typedef struct 3991 { 3992 ULP_BDE xrsqbde[2]; 3993 uint32_t xrsqRo; /* Starting Relative Offset */ 3994 WORD5 w5; /* Header control/status word */ 3995 } XR_SEQ_FIELDS; 3996 3997 /* IOCB Command template for ELS_REQUEST */ 3998 typedef struct 3999 { 4000 ULP_BDE elsReq; 4001 ULP_BDE elsRsp; 4002 #ifdef EMLXS_BIG_ENDIAN 4003 uint32_t word4Rsvd:7; 4004 uint32_t fl:1; 4005 uint32_t myID:24; 4006 uint32_t word5Rsvd:8; 4007 uint32_t remoteID:24; 4008 #endif 4009 #ifdef EMLXS_LITTLE_ENDIAN 4010 uint32_t myID:24; 4011 uint32_t fl:1; 4012 uint32_t word4Rsvd:7; 4013 uint32_t remoteID:24; 4014 uint32_t word5Rsvd:8; 4015 #endif 4016 } ELS_REQUEST; 4017 4018 /* IOCB Command template for RCV_ELS_REQ */ 4019 typedef struct 4020 { 4021 ULP_BDE elsReq[2]; 4022 uint32_t parmRo; 4023 #ifdef EMLXS_BIG_ENDIAN 4024 uint32_t word5Rsvd:8; 4025 uint32_t remoteID:24; 4026 #endif 4027 #ifdef EMLXS_LITTLE_ENDIAN 4028 uint32_t remoteID:24; 4029 uint32_t word5Rsvd:8; 4030 #endif 4031 } RCV_ELS_REQ; 4032 4033 /* IOCB Command template for ABORT / CLOSE_XRI */ 4034 typedef struct 4035 { 4036 uint32_t rsvd[3]; 4037 uint32_t abortType; 4038 #define ABORT_TYPE_ABTX 0x00000000 4039 #define ABORT_TYPE_ABTS 0x00000001 4040 uint32_t parm; 4041 #ifdef EMLXS_BIG_ENDIAN 4042 uint16_t abortContextTag; /* ulpContext from command to */ 4043 /* abort/close */ 4044 uint16_t abortIoTag; /* ulpIoTag from command to */ 4045 /* abort/close */ 4046 #endif 4047 #ifdef EMLXS_LITTLE_ENDIAN 4048 uint16_t abortIoTag; /* ulpIoTag from command to */ 4049 /* abort/close */ 4050 uint16_t abortContextTag; /* ulpContext from command to */ 4051 /* abort/close */ 4052 #endif 4053 } AC_XRI; 4054 4055 /* IOCB Command template for GET_RPI */ 4056 typedef struct 4057 { 4058 uint32_t rsvd[4]; 4059 uint32_t parmRo; 4060 #ifdef EMLXS_BIG_ENDIAN 4061 uint32_t word5Rsvd:8; 4062 uint32_t remoteID:24; 4063 #endif 4064 #ifdef EMLXS_LITTLE_ENDIAN 4065 uint32_t remoteID:24; 4066 uint32_t word5Rsvd:8; 4067 #endif 4068 } GET_RPI; 4069 4070 /* IOCB Command template for all FCP Initiator commands */ 4071 typedef struct 4072 { 4073 ULP_BDE fcpi_cmnd; /* FCP_CMND payload descriptor */ 4074 ULP_BDE fcpi_rsp; /* Rcv buffer */ 4075 uint32_t fcpi_parm; 4076 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 4077 } FCPI_FIELDS; 4078 4079 /* IOCB Command template for all FCP Target commands */ 4080 typedef struct 4081 { 4082 ULP_BDE fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 4083 uint32_t fcpt_Offset; 4084 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 4085 } FCPT_FIELDS; 4086 4087 /* SLI-2 IOCB structure definitions */ 4088 4089 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 4090 typedef struct 4091 { 4092 ULP_BDL bdl; 4093 uint32_t xrsqRo; /* Starting Relative Offset */ 4094 WORD5 w5; /* Header control/status word */ 4095 } XMT_SEQ_FIELDS64; 4096 4097 4098 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 4099 typedef struct 4100 { 4101 ULP_BDE64 rcvBde; 4102 uint32_t rsvd1; 4103 uint32_t xrsqRo; /* Starting Relative Offset */ 4104 WORD5 w5; /* Header control/status word */ 4105 } RCV_SEQ_FIELDS64; 4106 4107 /* IOCB Command template for ELS_REQUEST64 */ 4108 typedef struct 4109 { 4110 ULP_BDL bdl; 4111 #ifdef EMLXS_BIG_ENDIAN 4112 uint32_t word4Rsvd:7; 4113 uint32_t fl:1; 4114 uint32_t myID:24; 4115 4116 uint32_t word5Rsvd:8; 4117 uint32_t remoteID:24; 4118 #endif 4119 #ifdef EMLXS_LITTLE_ENDIAN 4120 uint32_t myID:24; 4121 uint32_t fl:1; 4122 uint32_t word4Rsvd:7; 4123 4124 uint32_t remoteID:24; 4125 uint32_t word5Rsvd:8; 4126 #endif 4127 } ELS_REQUEST64; 4128 4129 4130 /* IOCB Command template for ASYNC_STATUS */ 4131 typedef struct 4132 { 4133 ULP_BDL resv; 4134 uint32_t parameter; 4135 #ifdef EMLXS_BIG_ENDIAN 4136 uint16_t EventCode; 4137 uint16_t SubContext; 4138 #endif 4139 #ifdef EMLXS_LITTLE_ENDIAN 4140 uint16_t SubContext; 4141 uint16_t EventCode; 4142 #endif 4143 } ASYNC_STATUS; 4144 4145 4146 /* IOCB Command template for QUE_RING_LIST64 */ 4147 typedef struct 4148 { 4149 ULP_BDL bdl; 4150 uint32_t rsvd1; 4151 uint32_t rsvd2; 4152 } QUE_RING_LIST64; 4153 4154 4155 /* IOCB Command template for GEN_REQUEST64 */ 4156 typedef struct 4157 { 4158 ULP_BDL bdl; 4159 uint32_t param; /* Starting Relative Offset */ 4160 WORD5 w5; /* Header control/status word */ 4161 } GEN_REQUEST64; 4162 4163 /* IOCB Command template for RCV_ELS_REQ64 */ 4164 typedef struct 4165 { 4166 ULP_BDE64 elsReq; 4167 uint32_t rcvd1; 4168 uint32_t parmRo; 4169 #ifdef EMLXS_BIG_ENDIAN 4170 uint32_t word5Rsvd:8; 4171 uint32_t remoteID:24; 4172 #endif 4173 #ifdef EMLXS_LITTLE_ENDIAN 4174 uint32_t remoteID:24; 4175 uint32_t word5Rsvd:8; 4176 #endif 4177 } RCV_ELS_REQ64; 4178 4179 /* IOCB Command template for all 64 bit FCP Initiator commands */ 4180 typedef struct 4181 { 4182 ULP_BDL bdl; 4183 uint32_t fcpi_parm; 4184 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 4185 } FCPI_FIELDS64; 4186 4187 /* IOCB Command template for all 64 bit FCP Target commands */ 4188 typedef struct 4189 { 4190 ULP_BDL bdl; 4191 uint32_t fcpt_Offset; 4192 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 4193 } FCPT_FIELDS64; 4194 4195 /* IOCB Command template for all 64 bit FCP Target commands */ 4196 typedef struct 4197 { 4198 uint32_t rsp_length; 4199 uint32_t rsvd1; 4200 uint32_t rsvd2; 4201 uint32_t iotag32; 4202 uint32_t status; 4203 #ifdef EMLXS_BIG_ENDIAN 4204 uint32_t rsvd:30; 4205 uint32_t lnk:1; 4206 #endif /* EMLXS_BIG_ENDIAN */ 4207 4208 #ifdef EMLXS_LITTLE_ENDIAN 4209 uint32_t lnk:1; 4210 uint32_t rsvd:30; 4211 #endif /* EMLXS_LITTLE_ENDIAN */ 4212 } AUTO_TRSP; 4213 4214 4215 typedef struct 4216 { 4217 uint32_t io_tag64_low; /* Word 8 */ 4218 uint32_t io_tag64_high; /* Word 9 */ 4219 #ifdef EMLXS_BIG_ENDIAN 4220 uint32_t cs_ctl:8; /* Word 10, bit 31:24 */ 4221 uint32_t cs_en:1; /* Word 10, bit 23 */ 4222 uint32_t rsv:15; /* Word 10, bit 22:8 */ 4223 uint32_t ebde_count:8; /* Word 10, bit 7:0 */ 4224 #endif 4225 #ifdef EMLXS_LITTLE_ENDIAN 4226 uint32_t ebde_count:8; /* Word 10, bit 7:0 */ 4227 uint32_t rsv:15; /* Word 10, bit 22:8 */ 4228 uint32_t cs_en:1; /* Word 10, bit 23 */ 4229 uint32_t cs_ctl:8; /* Word 10, bit 31:24 */ 4230 #endif 4231 uint32_t rsplen; /* Word 11 */ 4232 ULP_BDE64 ebde1; /* Word 12:14 */ 4233 ULP_BDE64 ebde2; /* Word 15:17 */ 4234 ULP_BDE64 ebde3; /* Word 18:20 */ 4235 ULP_BDE64 ebde4; /* Word 21:23 */ 4236 ULP_BDE64 ebde5; /* Word 24:26 */ 4237 ULP_BDE64 ebde6; /* Word 27:29 */ 4238 } GENERIC_EXT_IOCB; 4239 4240 /* 4241 * IOCB Command Extension template for 4242 * CMD_RCV_ELS64_CX (0xB7) or CMD_RCV_SEQ64_CX (0xB5) 4243 */ 4244 4245 typedef struct 4246 { 4247 uint32_t hdr3; /* word 8 */ 4248 #ifdef EMLXS_BIG_ENDIAN 4249 uint16_t vpi; /* word 9 */ 4250 uint16_t buddy_xri; 4251 4252 uint32_t ccp:8; /* word 10 */ 4253 uint32_t ccpe:1; 4254 uint32_t rsvd:23; 4255 #endif 4256 #ifdef EMLXS_LITTLE_ENDIAN 4257 uint16_t buddy_xri; /* word 9 */ 4258 uint16_t vpi; 4259 4260 uint32_t rsvd:23; /* word 10 */ 4261 uint32_t ccpe:1; 4262 uint32_t ccp:8; 4263 #endif 4264 uint32_t seq_len; /* received sequence length */ 4265 ULP_BDL bde2; /* total 4 words */ 4266 } RCV_SEQ_ELS_64_SLI3_EXT; 4267 4268 4269 4270 typedef volatile struct emlxs_iocb 4271 { /* IOCB structure */ 4272 union 4273 { 4274 GENERIC_RSP grsp; /* Generic response */ 4275 XR_SEQ_FIELDS xrseq; /* XMIT/BCAST/RCV_SEQ */ 4276 ULP_BDE cont[3]; /* up to 3 cont BDEs */ 4277 ELS_REQUEST elsreq; /* ELS_REQ template */ 4278 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ */ 4279 /* template */ 4280 AC_XRI acxri; /* ABORT/CLOSE_XRI */ 4281 /* template */ 4282 GET_RPI getrpi; /* GET_RPI template */ 4283 FCPI_FIELDS fcpi; /* FCP Initiator */ 4284 /* template */ 4285 FCPT_FIELDS fcpt; /* FCP target */ 4286 /* template */ 4287 4288 /* SLI-2 structures */ 4289 4290 ULP_BDE64 cont64[2]; /* up to 2 64 bit */ 4291 /* cont BDE_64s */ 4292 ELS_REQUEST64 elsreq64; /* ELS_REQ64 template */ 4293 QUE_RING_LIST64 qringlist64; /* QUE RING LIST64 */ 4294 /* template */ 4295 GEN_REQUEST64 genreq64; /* GEN_REQUEST64 */ 4296 /* template */ 4297 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ */ 4298 /* template */ 4299 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 4300 FCPI_FIELDS64 fcpi64; /* FCP 64 bit */ 4301 /* Initiator template */ 4302 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target */ 4303 /* template */ 4304 AUTO_TRSP atrsp; /* FCP 64 bit target */ 4305 /* template */ 4306 4307 RCV_SEQ_FIELDS64 rcvseq64; 4308 ASYNC_STATUS astat; 4309 4310 uint32_t ulpWord[6]; /* generic 6 'words' */ 4311 } un; 4312 union 4313 { 4314 struct 4315 { 4316 #ifdef EMLXS_BIG_ENDIAN 4317 uint16_t ulpContext; /* High order bits */ 4318 /* word6 */ 4319 uint16_t ulpIoTag; /* Low order bits */ 4320 /* word6 */ 4321 #endif 4322 #ifdef EMLXS_LITTLE_ENDIAN 4323 uint16_t ulpIoTag; /* Low order bits */ 4324 /* word6 */ 4325 uint16_t ulpContext; /* High order bits */ 4326 /* word6 */ 4327 #endif 4328 } t1; 4329 struct 4330 { 4331 #ifdef EMLXS_BIG_ENDIAN 4332 uint16_t ulpContext; /* High order bits */ 4333 /* word6 */ 4334 uint16_t ulpIoTag1:2; /* Low order bits */ 4335 /* word6 */ 4336 uint16_t ulpIoTag0:14; /* Low order bits */ 4337 /* word6 */ 4338 #endif 4339 #ifdef EMLXS_LITTLE_ENDIAN 4340 uint16_t ulpIoTag0:14; /* Low order bits */ 4341 /* word6 */ 4342 uint16_t ulpIoTag1:2; /* Low order bits */ 4343 /* word6 */ 4344 uint16_t ulpContext; /* High order bits */ 4345 /* word6 */ 4346 #endif 4347 } t2; 4348 } un1; 4349 #define ulpContext un1.t1.ulpContext 4350 #define ulpIoTag un1.t1.ulpIoTag 4351 #define ulpIoTag0 un1.t2.ulpIoTag0 4352 #define ulpDelayXmit un1.t2.ulpIoTag1 4353 4354 #define IOCB_DELAYXMIT_MSK 0x3000 4355 4356 4357 union 4358 { 4359 struct 4360 { 4361 #ifdef EMLXS_BIG_ENDIAN 4362 uint32_t ulpRsvdByte:8; 4363 uint32_t ulpXS:1; 4364 uint32_t ulpFCP2Rcvy:1; 4365 uint32_t ulpPU:2; 4366 uint32_t ulpIr:1; 4367 uint32_t ulpClass:3; 4368 uint32_t ulpCommand:8; 4369 uint32_t ulpStatus:4; 4370 uint32_t ulpBdeCount:2; 4371 uint32_t ulpLe:1; 4372 uint32_t ulpOwner:1; /* Low order bit */ 4373 /* word 7 */ 4374 #endif 4375 #ifdef EMLXS_LITTLE_ENDIAN 4376 uint32_t ulpOwner:1; /* Low order bit */ 4377 /* word 7 */ 4378 uint32_t ulpLe:1; 4379 uint32_t ulpBdeCount:2; 4380 uint32_t ulpStatus:4; 4381 uint32_t ulpCommand:8; 4382 uint32_t ulpClass:3; 4383 uint32_t ulpIr:1; 4384 uint32_t ulpPU:2; 4385 uint32_t ulpFCP2Rcvy:1; 4386 uint32_t ulpXS:1; 4387 uint32_t ulpRsvdByte:8; 4388 #endif 4389 } t1; 4390 4391 struct 4392 { 4393 #ifdef EMLXS_BIG_ENDIAN 4394 uint32_t ulpRsvdByte:8; 4395 uint32_t ulpCT:2; 4396 uint32_t ulpPU:2; 4397 uint32_t ulpIr:1; 4398 uint32_t ulpClass:3; 4399 uint32_t ulpCommand:8; 4400 uint32_t ulpStatus:4; 4401 uint32_t ulpBdeCount:2; 4402 uint32_t ulpLe:1; 4403 uint32_t ulpOwner:1; /* Low order bit */ 4404 /* word 7 */ 4405 #endif 4406 #ifdef EMLXS_LITTLE_ENDIAN 4407 uint32_t ulpOwner:1; /* Low order bit */ 4408 /* word 7 */ 4409 uint32_t ulpLe:1; 4410 uint32_t ulpBdeCount:2; 4411 uint32_t ulpStatus:4; 4412 uint32_t ulpCommand:8; 4413 uint32_t ulpClass:3; 4414 uint32_t ulpIr:1; 4415 uint32_t ulpPU:2; 4416 uint32_t ulpCT:2; 4417 uint32_t ulpRsvdByte:8; 4418 #endif 4419 } t2; 4420 } un2; 4421 4422 #define ulpCT un2.t2.ulpCT 4423 #define ulpRsvdByte un2.t1.ulpRsvdByte 4424 #define ulpXS un2.t1.ulpXS 4425 #define ulpFCP2Rcvy un2.t1.ulpFCP2Rcvy 4426 #define ulpPU un2.t1.ulpPU 4427 #define ulpIr un2.t1.ulpIr 4428 #define ulpClass un2.t1.ulpClass 4429 #define ulpCommand un2.t1.ulpCommand 4430 #define ulpStatus un2.t1.ulpStatus 4431 #define ulpBdeCount un2.t1.ulpBdeCount 4432 #define ulpLe un2.t1.ulpLe 4433 #define ulpOwner un2.t1.ulpOwner 4434 /* 32 bytes at this point */ 4435 4436 #ifdef SLI3_SUPPORT 4437 union 4438 { 4439 GENERIC_EXT_IOCB ext_iocb; 4440 RCV_SEQ_ELS_64_SLI3_EXT ext_rcv; 4441 uint32_t sli3Words[24]; /* 96 extra bytes */ 4442 /* for SLI-3 */ 4443 } unsli3; 4444 /* 128 bytes at this point */ 4445 #endif /* SLI3_SUPPORT */ 4446 4447 #define IOCB_FCP 1 /* IOCB is used for */ 4448 /* FCP ELS cmds - ulpRsvByte */ 4449 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 4450 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 4451 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 4452 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Xfer Len */ 4453 #define CLASS1 0 /* Class 1 */ 4454 #define CLASS2 1 /* Class 2 */ 4455 #define CLASS3 2 /* Class 3 */ 4456 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 4457 4458 #define IOSTAT_SUCCESS 0x0 /* ulpStatus */ 4459 #define IOSTAT_FCP_RSP_ERROR 0x1 4460 #define IOSTAT_REMOTE_STOP 0x2 4461 #define IOSTAT_LOCAL_REJECT 0x3 4462 #define IOSTAT_NPORT_RJT 0x4 4463 #define IOSTAT_FABRIC_RJT 0x5 4464 #define IOSTAT_NPORT_BSY 0x6 4465 #define IOSTAT_FABRIC_BSY 0x7 4466 #define IOSTAT_INTERMED_RSP 0x8 4467 #define IOSTAT_LS_RJT 0x9 4468 #define IOSTAT_RESERVED_A 0xA 4469 #define IOSTAT_CMD_REJECT 0xB 4470 #define IOSTAT_FCP_TGT_LENCHK 0xC 4471 #define IOSTAT_NEED_BUF_ENTRY 0xD 4472 #define IOSTAT_RESERVED_E 0xE 4473 #define IOSTAT_ILLEGAL_FRAME_RCVD 0xF 4474 4475 /* Special error codes */ 4476 #define IOSTAT_DATA_OVERRUN 0x10 /* Added for resid handling */ 4477 #define IOSTAT_DATA_UNDERRUN 0x11 /* Added for resid handling */ 4478 } emlxs_iocb_t; 4479 typedef emlxs_iocb_t IOCB; 4480 4481 4482 typedef struct emlxs_iocbq 4483 { 4484 emlxs_iocb_t iocb; 4485 struct emlxs_iocbq *next; 4486 4487 uint8_t *bp; /* ptr to data buffer structure */ 4488 void *port; /* Board info pointer */ 4489 void *ring; /* Ring pointer */ 4490 void *node; /* Node pointer */ 4491 void *sbp; /* Pkt pointer */ 4492 uint32_t flag; 4493 4494 #define IOCB_POOL_ALLOCATED 0x00000001 4495 #define IOCB_PRIORITY 0x00000002 4496 #define IOCB_SPECIAL 0x00000004 4497 } emlxs_iocbq_t; 4498 typedef emlxs_iocbq_t IOCBQ; 4499 4500 4501 typedef struct emlxs_mbq 4502 { 4503 volatile uint32_t mbox[MAILBOX_CMD_WSIZE]; 4504 struct emlxs_mbq *next; 4505 4506 /* Defferred handling pointers */ 4507 uint8_t *bp; /* ptr to data buffer */ 4508 /* structure */ 4509 uint8_t *sbp; /* ptr to emlxs_buf_t */ 4510 /* structure */ 4511 uint8_t *ubp; /* ptr to fc_unsol_buf_t */ 4512 /* structure */ 4513 uint8_t *iocbq; /* ptr to IOCBQ structure */ 4514 uint32_t flag; 4515 4516 #define MBQ_POOL_ALLOCATED 0x00000001 4517 #define MBQ_PASSTHRU 0x00000002 4518 #define MBQ_COMPLETED 0x00010000 /* Used for MBX_SLEEP */ 4519 #define MBQ_INIT_MASK 0x0000ffff 4520 4521 #ifdef MBOX_EXT_SUPPORT 4522 uint8_t *extbuf; /* ptr to mailbox ext buffer */ 4523 uint32_t extsize; /* size of mailbox ext buffer */ 4524 #endif /* MBOX_EXT_SUPPORT */ 4525 } emlxs_mbq_t; 4526 typedef emlxs_mbq_t MAILBOXQ; 4527 4528 4529 /* We currently do not support IOCBs in SLI1 mode */ 4530 typedef struct 4531 { 4532 MAILBOX mbx; 4533 #ifdef MBOX_EXT_SUPPORT 4534 uint8_t mbxExt[MBOX_EXTENSION_SIZE]; 4535 #endif /* MBOX_EXT_SUPPORT */ 4536 uint8_t pad[(SLI_SLIM1_SIZE - 4537 (sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))]; 4538 } SLIM1; 4539 4540 4541 typedef struct 4542 { 4543 MAILBOX mbx; 4544 #ifdef MBOX_EXT_SUPPORT 4545 uint8_t mbxExt[MBOX_EXTENSION_SIZE]; 4546 #endif /* MBOX_EXT_SUPPORT */ 4547 PCB pcb; 4548 uint8_t IOCBs[SLI_IOCB_MAX_SIZE]; 4549 } SLIM2; 4550 4551 4552 4553 /* 4554 * This file defines the Header File for the FDMI HBA Management Service 4555 */ 4556 4557 /* 4558 * FDMI HBA MAnagement Operations Command Codes 4559 */ 4560 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 4561 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 4562 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 4563 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 4564 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 4565 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 4566 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 4567 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 4568 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 4569 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 4570 4571 /* 4572 * Management Service Subtypes 4573 */ 4574 #define SLI_CT_FDMI_Subtypes 0x10 4575 4576 4577 /* 4578 * HBA Management Service Reject Code 4579 */ 4580 #define REJECT_CODE 0x9 /* Unable to perform command request */ 4581 4582 /* 4583 * HBA Management Service Reject Reason Code 4584 * Please refer to the Reason Codes above 4585 */ 4586 4587 /* 4588 * HBA Attribute Types 4589 */ 4590 #define NODE_NAME 0x1 4591 #define MANUFACTURER 0x2 4592 #define SERIAL_NUMBER 0x3 4593 #define MODEL 0x4 4594 #define MODEL_DESCRIPTION 0x5 4595 #define HARDWARE_VERSION 0x6 4596 #define DRIVER_VERSION 0x7 4597 #define OPTION_ROM_VERSION 0x8 4598 #define FIRMWARE_VERSION 0x9 4599 #define VENDOR_SPECIFIC 0xa 4600 #define DRV_NAME 0xb 4601 #define OS_NAME_VERSION 0xc 4602 #define MAX_CT_PAYLOAD_LEN 0xd 4603 4604 /* 4605 * Port Attrubute Types 4606 */ 4607 #define SUPPORTED_FC4_TYPES 0x1 4608 #define SUPPORTED_SPEED 0x2 4609 #define PORT_SPEED 0x3 4610 #define MAX_FRAME_SIZE 0x4 4611 #define OS_DEVICE_NAME 0x5 4612 4613 union AttributesDef 4614 { 4615 /* Structure is in Big Endian format */ 4616 struct 4617 { 4618 uint32_t AttrType:16; 4619 uint32_t AttrLen:16; 4620 } bits; 4621 uint32_t word; 4622 }; 4623 4624 /* 4625 * HBA Attribute Entry (8 - 260 bytes) 4626 */ 4627 typedef struct 4628 { 4629 union AttributesDef ad; 4630 union 4631 { 4632 uint32_t VendorSpecific; 4633 uint32_t SupportSpeed; 4634 uint32_t PortSpeed; 4635 uint32_t MaxFrameSize; 4636 uint32_t MaxCTPayloadLen; 4637 uint8_t SupportFC4Types[32]; 4638 uint8_t OsDeviceName[256]; 4639 uint8_t Manufacturer[64]; 4640 uint8_t SerialNumber[64]; 4641 uint8_t Model[256]; 4642 uint8_t ModelDescription[256]; 4643 uint8_t HardwareVersion[256]; 4644 uint8_t DriverVersion[256]; 4645 uint8_t OptionROMVersion[256]; 4646 uint8_t FirmwareVersion[256]; 4647 uint8_t DriverName[256]; 4648 NAME_TYPE NodeName; 4649 } un; 4650 } ATTRIBUTE_ENTRY, *PATTRIBUTE_ENTRY; 4651 4652 4653 /* 4654 * HBA Attribute Block 4655 */ 4656 typedef struct 4657 { 4658 uint32_t EntryCnt; /* Number of HBA attribute entries */ 4659 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 4660 } ATTRIBUTE_BLOCK, *PATTRIBUTE_BLOCK; 4661 4662 4663 /* 4664 * Port Entry 4665 */ 4666 typedef struct 4667 { 4668 NAME_TYPE PortName; 4669 } PORT_ENTRY, *PPORT_ENTRY; 4670 4671 /* 4672 * HBA Identifier 4673 */ 4674 typedef struct 4675 { 4676 NAME_TYPE PortName; 4677 } HBA_IDENTIFIER, *PHBA_IDENTIFIER; 4678 4679 /* 4680 * Registered Port List Format 4681 */ 4682 typedef struct 4683 { 4684 uint32_t EntryCnt; 4685 PORT_ENTRY pe; /* Variable-length array */ 4686 } REG_PORT_LIST, *PREG_PORT_LIST; 4687 4688 /* 4689 * Register HBA(RHBA) 4690 */ 4691 typedef struct 4692 { 4693 HBA_IDENTIFIER hi; 4694 REG_PORT_LIST rpl; /* variable-length array */ 4695 } REG_HBA, *PREG_HBA; 4696 4697 /* 4698 * Register HBA Attributes (RHAT) 4699 */ 4700 typedef struct 4701 { 4702 NAME_TYPE HBA_PortName; 4703 ATTRIBUTE_BLOCK ab; 4704 } REG_HBA_ATTRIBUTE, *PREG_HBA_ATTRIBUTE; 4705 4706 /* 4707 * Register Port Attributes (RPA) 4708 */ 4709 typedef struct 4710 { 4711 NAME_TYPE HBA_PortName; 4712 NAME_TYPE PortName; 4713 ATTRIBUTE_BLOCK ab; 4714 } REG_PORT_ATTRIBUTE, *PREG_PORT_ATTRIBUTE; 4715 4716 /* 4717 * Get Registered HBA List (GRHL) Accept Payload Format 4718 */ 4719 typedef struct 4720 { 4721 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Ids */ 4722 NAME_TYPE HBA_PortName; /* Variable-length array */ 4723 } GRHL_ACC_PAYLOAD, *PGRHL_ACC_PAYLOAD; 4724 4725 /* 4726 * Get Registered Port List (GRPL) Accept Payload Format 4727 */ 4728 typedef struct 4729 { 4730 uint32_t RPL_Entry_Cnt; /* No of Reg Port Entries */ 4731 PORT_ENTRY eg_Port_Entry[1]; /* Variable-length array */ 4732 } GRPL_ACC_PAYLOAD, *PGRPL_ACC_PAYLOAD; 4733 4734 /* 4735 * Get Port Attributes (GPAT) Accept Payload Format 4736 */ 4737 4738 typedef struct 4739 { 4740 ATTRIBUTE_BLOCK pab; 4741 } GPAT_ACC_PAYLOAD, *PGPAT_ACC_PAYLOAD; 4742 4743 /* 4744 * Use for Firmware DownLoad 4745 */ 4746 4747 /* download.h */ 4748 4749 #define REDUCED_SRAM_CFG 0x7FFFC /* 9802DC */ 4750 #define FULL_SRAM_CFG 0x13FFFC /* 9802 */ 4751 4752 #define SLI_FW_TYPE_SHIFT(x) ((x << 20)) 4753 #define SLI_FW_ADAPTER_TYPE_MASK 0x00f00000 4754 #define SLI_FW_TYPE_6000 SLI_FW_TYPE_SHIFT(0) 4755 #define SLI_FW_TYPE_7000 SLI_FW_TYPE_SHIFT(1) 4756 #define SLI_FW_TYPE_8000 SLI_FW_TYPE_SHIFT(2) 4757 #define SLI_FW_TYPE_850 SLI_FW_TYPE_SHIFT(3) 4758 #define SLI_FW_TYPE_9000 SLI_FW_TYPE_SHIFT(4) 4759 #define SLI_FW_TYPE_950 SLI_FW_TYPE_SHIFT(5) 4760 #define SLI_FW_TYPE_9802 SLI_FW_TYPE_SHIFT(6) /* [022702] */ 4761 #define SLI_FW_TYPE_982 SLI_FW_TYPE_SHIFT(7) 4762 #define SLI_FW_TYPE_10000 SLI_FW_TYPE_SHIFT(8) 4763 #define SLI_FW_TYPE_1050 SLI_FW_TYPE_SHIFT(9) 4764 #define SLI_FW_TYPE_X1000 SLI_FW_TYPE_SHIFT(0xa) 4765 #define SLI_FW_TYPE_101 SLI_FW_TYPE_SHIFT(0xb) /* LP101 */ 4766 4767 4768 enum emlxs_prog_type 4769 { 4770 TEST_PROGRAM, /* 0 */ 4771 UTIL_PROGRAM, /* 1 */ 4772 FUNC_FIRMWARE, /* 2 */ 4773 BOOT_BIOS, /* 3 */ 4774 CONFIG_DATA, /* 4 */ 4775 SEQUENCER_CODE, /* 5 */ 4776 SLI1_OVERLAY, /* 6 */ 4777 SLI2_OVERLAY, /* 7 */ 4778 GASKET, /* 8 */ 4779 HARDWARE_IMAGE, /* 9 */ 4780 SBUS_FCODE, /* A */ 4781 SLI3_OVERLAY, /* B */ 4782 RESERVED_C, 4783 RESERVED_D, 4784 SLI4_OVERLAY, /* E */ 4785 KERNEL_CODE, /* F */ 4786 MAX_PROG_TYPES 4787 } emlxs_prog_type_t; 4788 4789 4790 typedef struct emlxs_fw_file 4791 { 4792 uint32_t version; 4793 uint32_t revcomp; 4794 char label[16]; 4795 uint32_t offset; 4796 } emlxs_fw_file_t; 4797 4798 typedef struct emlxs_fw_image 4799 { 4800 emlxs_fw_file_t awc; 4801 emlxs_fw_file_t bwc; 4802 emlxs_fw_file_t dwc; 4803 emlxs_fw_file_t prog[MAX_PROG_TYPES]; 4804 } emlxs_fw_image_t; 4805 4806 4807 4808 4809 #define NOP_IMAGE_TYPE 0xe1a00000 4810 4811 #define FLASH_BASE_ADR 0x01400000 4812 #define DL_FROM_SLIM_OFFSET MBOX_EXTENSION_OFFSET 4813 4814 #ifdef MBOX_EXT_SUPPORT 4815 #define DL_SLIM_SEG_BYTE_COUNT MBOX_EXTENSION_SIZE 4816 #else 4817 #define DL_SLIM_SEG_BYTE_COUNT 128 4818 #endif /* MBOX_EXT_SUPPORT */ 4819 4820 #define SLI_CKSUM_LENGTH 4 4821 #define SLI_CKSUM_SEED 0x55555555 4822 #define SLI_CKSUM_ERR 0x1982abcd 4823 4824 #define AIF_NOOP 0xe1a00000 4825 #define AIF_BLAL 0xeb000000 4826 #define OS_EXIT 0xef000011 4827 #define OS_GETENV 0xef000010 4828 #define AIF_IMAGEBASE 0x00008000 4829 #define AIF_BLZINIT 0xeb00000c 4830 #define DEBUG_TASK 0xef041d41 4831 #define AIF_DBG_SRC 2 4832 #define AIF_DBG_LL 1 4833 #define AIF_DATABASAT 0x100 4834 4835 #define JEDEC_ID_ADDRESS 0x0080001c 4836 #define MAX_RBUS_SRAM_SIZE_ADR 0x788 4837 #define MAX_IBUS_SRAM_SIZE_ADR 0x78c 4838 #define FULL_RBUS_SRAM_CFG 0x7fffc 4839 #define FULL_IBUS_SRAM_CFG 0x187fffc 4840 #define REDUCED_RBUS_SRAM_CFG 0x5fffc 4841 #define REDUCED_IBUS_SRAM_CFG 0x183fffc 4842 4843 #define FULL_SRAM_CFG_PROG_ID 1 4844 #define REDUCED_SRAM_CFG_PROG_ID 2 4845 #define OTHER_SRAM_CFG_PROG_ID 3 4846 4847 #define NO_FLASH_MEM_AVAIL 0xf1 4848 4849 #define PROG_TYPE_MASK 0xff000000 4850 #define PROG_TYPE_SHIFT 24 4851 4852 #define FLASH_LOAD_LIST_ADR 0x79c 4853 #define RAM_LOAD_ENTRY_SIZE 9 4854 #define FLASH_LOAD_ENTRY_SIZE 6 4855 #define RAM_LOAD_ENTRY_TYPE 0 4856 #define FLASH_LOAD_ENTRY_TYPE 1 4857 4858 #define CFG_DATA_NO_REGION -3 4859 4860 #define SLI_IMAGE_START 0x20080 4861 #define SLI_VERSION_LOC 0x270 4862 4863 /* def for new 2MB Flash (Pegasus ...) */ 4864 #define MBX_LOAD_AREA 0x81 4865 #define MBX_LOAD_EXP_ROM 0x9C 4866 4867 #define FILE_TYPE_AWC 0xE1A01001 4868 #define FILE_TYPE_DWC 0xE1A02002 4869 #define FILE_TYPE_BWC 0xE1A03003 4870 4871 #define AREA_ID_MASK 0xFFFFFF0F 4872 #define AREA_ID_AWC 0x00000001 4873 #define AREA_ID_DWC 0x00000002 4874 #define AREA_ID_BWC 0x00000003 4875 4876 #define CMD_START_ERASE 1 4877 #define CMD_CONTINUE_ERASE 2 4878 #define CMD_DOWNLOAD 3 4879 #define CMD_END_DOWNLOAD 4 4880 4881 #define RSP_ERASE_STARTED 1 4882 #define RSP_ERASE_COMPLETE 2 4883 #define RSP_DOWNLOAD_MORE 3 4884 #define RSP_DOWNLOAD_DONE 4 4885 4886 #define EROM_CMD_FIND_IMAGE 8 4887 #define EROM_CMD_CONTINUE_ERASE 9 4888 #define EROM_CMD_COPY 10 4889 4890 #define EROM_RSP_ERASE_STARTED 8 4891 #define EROM_RSP_ERASE_COMPLETE 9 4892 #define EROM_RSP_COPY_MORE 10 4893 #define EROM_RSP_COPY_DONE 11 4894 4895 #define ALLext 1 4896 #define DWCext 2 4897 #define BWCext 3 4898 4899 #define NO_ALL 0 4900 #define ALL_WITHOUT_BWC 1 4901 #define ALL_WITH_BWC 2 4902 4903 #define KERNEL_START_ADDRESS 0x000000 4904 #define DOWNLOAD_START_ADDRESS 0x040000 4905 #define EXP_ROM_START_ADDRESS 0x180000 4906 #define SCRATCH_START_ADDRESS 0x1C0000 4907 #define CONFIG_START_ADDRESS 0x1E0000 4908 4909 4910 typedef struct SliAifHdr 4911 { 4912 uint32_t CompressBr; 4913 uint32_t RelocBr; 4914 uint32_t ZinitBr; 4915 uint32_t EntryBr; 4916 uint32_t Area_ID; 4917 uint32_t RoSize; 4918 uint32_t RwSize; 4919 uint32_t DbgSize; 4920 uint32_t ZinitSize; 4921 uint32_t DbgType; 4922 uint32_t ImageBase; 4923 uint32_t Area_Size; 4924 uint32_t AddressMode; 4925 uint32_t DataBase; 4926 uint32_t AVersion; 4927 uint32_t Spare2; 4928 uint32_t DebugSwi; 4929 uint32_t ZinitCode[15]; 4930 } AIF_HDR, *PAIF_HDR; 4931 4932 typedef struct ImageHdr 4933 { 4934 uint32_t BlockSize; 4935 PROG_ID Id; 4936 uint32_t Flags; 4937 uint32_t EntryAdr; 4938 uint32_t InitAdr; 4939 uint32_t ExitAdr; 4940 uint32_t ImageBase; 4941 uint32_t ImageSize; 4942 uint32_t ZinitSize; 4943 uint32_t RelocSize; 4944 uint32_t HdrCks; 4945 } IMAGE_HDR, *PIMAGE_HDR; 4946 4947 4948 4949 typedef struct 4950 { 4951 PROG_ID prog_id; 4952 #ifdef EMLXS_BIG_ENDIAN 4953 uint32_t pci_cfg_rsvd:27; 4954 uint32_t use_hdw_def:1; 4955 uint32_t pci_cfg_sel:3; 4956 uint32_t pci_cfg_lookup_sel:1; 4957 #endif 4958 #ifdef EMLXS_LITTLE_ENDIAN 4959 uint32_t pci_cfg_lookup_sel:1; 4960 uint32_t pci_cfg_sel:3; 4961 uint32_t use_hdw_def:1; 4962 uint32_t pci_cfg_rsvd:27; 4963 #endif 4964 union 4965 { 4966 PROG_ID boot_bios_id; 4967 uint32_t boot_bios_wd[2]; 4968 } u0; 4969 PROG_ID sli1_prog_id; 4970 PROG_ID sli2_prog_id; 4971 PROG_ID sli3_prog_id; 4972 PROG_ID sli4_prog_id; 4973 union 4974 { 4975 PROG_ID EROM_prog_id; 4976 uint32_t EROM_prog_wd[2]; 4977 } u1; 4978 } WAKE_UP_PARMS, *PWAKE_UP_PARMS; 4979 4980 4981 #define PROG_DESCR_STR_LEN 24 4982 #define MAX_LOAD_ENTRY 10 4983 4984 typedef struct 4985 { 4986 uint32_t next; 4987 uint32_t prev; 4988 uint32_t start_adr; 4989 uint32_t len; 4990 union 4991 { 4992 PROG_ID id; 4993 uint32_t wd[2]; 4994 } un; 4995 uint8_t prog_descr[PROG_DESCR_STR_LEN]; 4996 } LOAD_ENTRY; 4997 4998 typedef struct 4999 { 5000 uint32_t head; 5001 uint32_t tail; 5002 uint32_t entry_cnt; 5003 LOAD_ENTRY load_entry[MAX_LOAD_ENTRY]; 5004 } LOAD_LIST; 5005 5006 5007 5008 #define SLI_HW_REVISION_CHECK(x, y) ((x & 0xf0) == y) 5009 #define SLI_FCODE_REVISION_CHECK(x, y) (x == y) 5010 5011 5012 #ifdef __cplusplus 5013 } 5014 #endif 5015 5016 #endif /* _EMLXS_HW_H */ 5017