1fcf3ce44SJohn Forte /* 2fcf3ce44SJohn Forte * CDDL HEADER START 3fcf3ce44SJohn Forte * 4fcf3ce44SJohn Forte * The contents of this file are subject to the terms of the 5fcf3ce44SJohn Forte * Common Development and Distribution License (the "License"). 6fcf3ce44SJohn Forte * You may not use this file except in compliance with the License. 7fcf3ce44SJohn Forte * 88f23e9faSHans Rosenfeld * You can obtain a copy of the license at 98f23e9faSHans Rosenfeld * http://www.opensource.org/licenses/cddl1.txt. 10fcf3ce44SJohn Forte * See the License for the specific language governing permissions 11fcf3ce44SJohn Forte * and limitations under the License. 12fcf3ce44SJohn Forte * 13fcf3ce44SJohn Forte * When distributing Covered Code, include this CDDL HEADER in each 14fcf3ce44SJohn Forte * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15fcf3ce44SJohn Forte * If applicable, add the following below this CDDL HEADER, with the 16fcf3ce44SJohn Forte * fields enclosed by brackets "[]" replaced with your own identifying 17fcf3ce44SJohn Forte * information: Portions Copyright [yyyy] [name of copyright owner] 18fcf3ce44SJohn Forte * 19fcf3ce44SJohn Forte * CDDL HEADER END 20fcf3ce44SJohn Forte */ 21fcf3ce44SJohn Forte 22fcf3ce44SJohn Forte /* 238f23e9faSHans Rosenfeld * Copyright (c) 2004-2011 Emulex. All rights reserved. 2482527734SSukumar Swaminathan * Use is subject to license terms. 25*a3170057SPaul Winder * Copyright 2020 RackTop Systems, Inc. 26fcf3ce44SJohn Forte */ 27fcf3ce44SJohn Forte 28fcf3ce44SJohn Forte #ifndef _EMLXS_HW_H 29fcf3ce44SJohn Forte #define _EMLXS_HW_H 30fcf3ce44SJohn Forte 31fcf3ce44SJohn Forte #ifdef __cplusplus 32fcf3ce44SJohn Forte extern "C" { 33fcf3ce44SJohn Forte #endif 34fcf3ce44SJohn Forte 35291a2b48SSukumar Swaminathan #define MAX_VPORTS 256 /* Max virtual ports per HBA */ 36291a2b48SSukumar Swaminathan /* (includes physical port) */ 37fcf3ce44SJohn Forte #define MAX_VPORTS_LIMITED 101 38fcf3ce44SJohn Forte 39291a2b48SSukumar Swaminathan #define FC_MAX_TRANSFER 0x40000 /* Max transfer size per */ 40291a2b48SSukumar Swaminathan /* operation */ 41fcf3ce44SJohn Forte 42fcf3ce44SJohn Forte #define MAX_RINGS_AVAILABLE 4 /* # rings available */ 43fcf3ce44SJohn Forte #define MAX_RINGS 4 /* Max # rings used */ 44fcf3ce44SJohn Forte 45fcf3ce44SJohn Forte #define PCB_SIZE 128 46fcf3ce44SJohn Forte 47fcf3ce44SJohn Forte #define SLIM_IOCB_CMD_R0_ENTRIES 128 /* SLI FCP cmd ring entries */ 48fcf3ce44SJohn Forte #define SLIM_IOCB_RSP_R0_ENTRIES 128 /* SLI FCP rsp ring entries */ 4982527734SSukumar Swaminathan #define SLIM_IOCB_CMD_R1_ENTRIES 128 /* SLI IP cmd ring entries */ 5082527734SSukumar Swaminathan #define SLIM_IOCB_RSP_R1_ENTRIES 128 /* SLI IP rsp ring entries */ 5182527734SSukumar Swaminathan #define SLIM_IOCB_CMD_R2_ENTRIES 128 /* SLI ELS cmd ring entries */ 5282527734SSukumar Swaminathan #define SLIM_IOCB_RSP_R2_ENTRIES 128 /* SLI ELS rspe ring entries */ 5382527734SSukumar Swaminathan #define SLIM_IOCB_CMD_R3_ENTRIES 128 /* SLI CT cmd ring entries */ 5482527734SSukumar Swaminathan #define SLIM_IOCB_RSP_R3_ENTRIES 128 /* SLI CT rsp ring entries */ 55291a2b48SSukumar Swaminathan 56291a2b48SSukumar Swaminathan /* 57291a2b48SSukumar Swaminathan * Total: 184 Cmd's + 184 Rsp's = 368 58291a2b48SSukumar Swaminathan * Command and response entry counts are not required to be equal 59291a2b48SSukumar Swaminathan */ 60fcf3ce44SJohn Forte 61291a2b48SSukumar Swaminathan #define SLIM_IOCB_CMD_ENTRIES (SLIM_IOCB_CMD_R0_ENTRIES + \ 62291a2b48SSukumar Swaminathan SLIM_IOCB_CMD_R1_ENTRIES + \ 63291a2b48SSukumar Swaminathan SLIM_IOCB_CMD_R2_ENTRIES + \ 64291a2b48SSukumar Swaminathan SLIM_IOCB_CMD_R3_ENTRIES) 65fcf3ce44SJohn Forte 66291a2b48SSukumar Swaminathan #define SLIM_IOCB_RSP_ENTRIES (SLIM_IOCB_RSP_R0_ENTRIES + \ 67291a2b48SSukumar Swaminathan SLIM_IOCB_RSP_R1_ENTRIES + \ 68291a2b48SSukumar Swaminathan SLIM_IOCB_RSP_R2_ENTRIES + \ 69291a2b48SSukumar Swaminathan SLIM_IOCB_RSP_R3_ENTRIES) 70fcf3ce44SJohn Forte 71291a2b48SSukumar Swaminathan #define SLIM_IOCB_ENTRIES (SLIM_IOCB_CMD_ENTRIES + \ 72291a2b48SSukumar Swaminathan SLIM_IOCB_RSP_ENTRIES) 73fcf3ce44SJohn Forte 74fcf3ce44SJohn Forte 75fcf3ce44SJohn Forte /* SLI1 Definitions */ 76291a2b48SSukumar Swaminathan #define SLI_SLIM1_SIZE 4096 /* Fixed size memory */ 77fcf3ce44SJohn Forte 78fcf3ce44SJohn Forte 79fcf3ce44SJohn Forte /* SLI2 Definitions */ 80fcf3ce44SJohn Forte #define SLI2_IOCB_CMD_SIZE 32 81fcf3ce44SJohn Forte #define SLI2_IOCB_RSP_SIZE 32 82291a2b48SSukumar Swaminathan #define SLI2_IOCB_MAX_SIZE ((SLI2_IOCB_CMD_SIZE * \ 83291a2b48SSukumar Swaminathan SLIM_IOCB_CMD_ENTRIES) + \ 84291a2b48SSukumar Swaminathan (SLI2_IOCB_RSP_SIZE * \ 85291a2b48SSukumar Swaminathan SLIM_IOCB_RSP_ENTRIES)) 86291a2b48SSukumar Swaminathan #define SLI2_SLIM2_SIZE (MBOX_SIZE + MBOX_EXTENSION_SIZE + \ 87291a2b48SSukumar Swaminathan PCB_SIZE + SLI2_IOCB_MAX_SIZE) 88291a2b48SSukumar Swaminathan 89fcf3ce44SJohn Forte 90fcf3ce44SJohn Forte /* SLI3 Definitions */ 91fcf3ce44SJohn Forte #define SLI3_MAX_BDE 7 92fcf3ce44SJohn Forte #define SLI3_IOCB_CMD_SIZE 128 93fcf3ce44SJohn Forte #define SLI3_IOCB_RSP_SIZE 64 94291a2b48SSukumar Swaminathan #define SLI3_IOCB_MAX_SIZE ((SLI3_IOCB_CMD_SIZE * \ 95291a2b48SSukumar Swaminathan SLIM_IOCB_CMD_ENTRIES) + \ 96291a2b48SSukumar Swaminathan (SLI3_IOCB_RSP_SIZE * \ 97291a2b48SSukumar Swaminathan SLIM_IOCB_RSP_ENTRIES)) 98291a2b48SSukumar Swaminathan #define SLI3_SLIM2_SIZE (MBOX_SIZE + MBOX_EXTENSION_SIZE + \ 99291a2b48SSukumar Swaminathan PCB_SIZE + SLI3_IOCB_MAX_SIZE) 100fcf3ce44SJohn Forte 101fcf3ce44SJohn Forte #define SLI_SLIM2_SIZE SLI3_SLIM2_SIZE 102fcf3ce44SJohn Forte #define SLI_IOCB_MAX_SIZE SLI3_IOCB_MAX_SIZE 103fcf3ce44SJohn Forte 104fcf3ce44SJohn Forte 10582527734SSukumar Swaminathan /* These two are defined to indicate FCP cmd or non FCP cmd */ 10682527734SSukumar Swaminathan #define FC_FCP_CMD 0 10782527734SSukumar Swaminathan #define FC_FCT_CMD 0 10882527734SSukumar Swaminathan #define FC_IP_CMD 1 10982527734SSukumar Swaminathan #define FC_ELS_CMD 2 11082527734SSukumar Swaminathan #define FC_CT_CMD 3 11182527734SSukumar Swaminathan 11282527734SSukumar Swaminathan #define FC_NFCP_CMD 1 /* could be a bit mask */ 113fcf3ce44SJohn Forte 114fcf3ce44SJohn Forte #define FC_MAXRETRY 3 /* max retries for ELS commands */ 115291a2b48SSukumar Swaminathan #define FC_FCP_RING 0 /* use ring 0 for FCP initiator cmds */ 116291a2b48SSukumar Swaminathan #define FC_FCT_RING 0 /* use ring 0 for FCP target cmds */ 117fcf3ce44SJohn Forte 118fcf3ce44SJohn Forte #define FC_IP_RING 1 /* use ring 1 for IP commands */ 119fcf3ce44SJohn Forte #define FC_ELS_RING 2 /* use ring 2 for ELS commands */ 120fcf3ce44SJohn Forte #define FC_CT_RING 3 /* use ring 3 for CT commands */ 121fcf3ce44SJohn Forte 122fcf3ce44SJohn Forte #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 123fcf3ce44SJohn Forte #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 124fcf3ce44SJohn Forte #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 125fcf3ce44SJohn Forte #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 126291a2b48SSukumar Swaminathan #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG */ 127291a2b48SSukumar Swaminathan /* iocb */ 128291a2b48SSukumar Swaminathan #define FF_REG_AREA_SIZE 256 /* size, in bytes, of i/o register */ 129291a2b48SSukumar Swaminathan /* area */ 130fcf3ce44SJohn Forte 131fcf3ce44SJohn Forte /* 132fcf3ce44SJohn Forte * Miscellaneous stuff.... 133fcf3ce44SJohn Forte */ 1348f23e9faSHans Rosenfeld 1358f23e9faSHans Rosenfeld #define MAX_NODE_THROTTLE 2048 1368f23e9faSHans Rosenfeld 137fcf3ce44SJohn Forte /* HBA Mgmt */ 138fcf3ce44SJohn Forte #define FDMI_DID ((uint32_t)0xfffffa) 13982527734SSukumar Swaminathan #define NAMESERVER_DID ((uint32_t)0xfffffc) 140fcf3ce44SJohn Forte #define SCR_DID ((uint32_t)0xfffffd) 14182527734SSukumar Swaminathan #define FABRIC_DID ((uint32_t)0xfffffe) 14282527734SSukumar Swaminathan #define BCAST_DID ((uint32_t)0xffffff) 14382527734SSukumar Swaminathan #define MASK_DID ((uint32_t)0xffffff) 144fcf3ce44SJohn Forte #define CT_DID_MASK ((uint32_t)0xffff00) 14582527734SSukumar Swaminathan #define FABRIC_DID_MASK ((uint32_t)0xfff000) 146fcf3ce44SJohn Forte #define WELL_KNOWN_DID_MASK ((uint32_t)0xfffff0) 147fcf3ce44SJohn Forte 148fcf3ce44SJohn Forte #define EMLXS_MENLO_DID ((uint32_t)0x00fc0e) 149fcf3ce44SJohn Forte 150fcf3ce44SJohn Forte #define OWN_CHIP 1 /* IOCB / Mailbox is owned by FireFly */ 151fcf3ce44SJohn Forte #define OWN_HOST 0 /* IOCB / Mailbox is owned by Host */ 152291a2b48SSukumar Swaminathan #define END_OF_CHAIN 0 153fcf3ce44SJohn Forte 154fcf3ce44SJohn Forte 155fcf3ce44SJohn Forte /* defines for type field in fc header */ 156fcf3ce44SJohn Forte #define EMLXS_MENLO_TYPE 0xFE 157fcf3ce44SJohn Forte 158fcf3ce44SJohn Forte /* defines for rctl field in fc header */ 159fcf3ce44SJohn Forte #define FC_DEV_DATA 0x0 160fcf3ce44SJohn Forte #define FC_UNSOL_CTL 0x2 161fcf3ce44SJohn Forte #define FC_SOL_CTL 0x3 162fcf3ce44SJohn Forte #define FC_UNSOL_DATA 0x4 163fcf3ce44SJohn Forte #define FC_FCP_CMND 0x6 164fcf3ce44SJohn Forte #define FC_ELS_REQ 0x22 165fcf3ce44SJohn Forte #define FC_ELS_RSP 0x23 166fcf3ce44SJohn Forte #define FC_NET_HDR 0x20 /* network headers for Dfctl field */ 167fcf3ce44SJohn Forte 168fcf3ce44SJohn Forte /* 169fcf3ce44SJohn Forte * Common Transport structures and definitions 170fcf3ce44SJohn Forte * 171fcf3ce44SJohn Forte */ 172fcf3ce44SJohn Forte #define EMLXS_COMMAND 0 173fcf3ce44SJohn Forte #define EMLXS_RESPONSE 1 174fcf3ce44SJohn Forte 175291a2b48SSukumar Swaminathan typedef union CtRevisionId 176291a2b48SSukumar Swaminathan { 177fcf3ce44SJohn Forte /* Structure is in Big Endian format */ 178291a2b48SSukumar Swaminathan struct 179291a2b48SSukumar Swaminathan { 180291a2b48SSukumar Swaminathan uint32_t Revision:8; 181291a2b48SSukumar Swaminathan uint32_t InId:24; 182fcf3ce44SJohn Forte } bits; 183291a2b48SSukumar Swaminathan uint32_t word; 184fcf3ce44SJohn Forte } CtRevisionId_t; 185fcf3ce44SJohn Forte 186291a2b48SSukumar Swaminathan typedef union CtCommandResponse 187291a2b48SSukumar Swaminathan { 188fcf3ce44SJohn Forte /* Structure is in Big Endian format */ 189291a2b48SSukumar Swaminathan struct 190291a2b48SSukumar Swaminathan { 191291a2b48SSukumar Swaminathan uint32_t CmdRsp:16; 192291a2b48SSukumar Swaminathan uint32_t Size:16; 193fcf3ce44SJohn Forte } bits; 194291a2b48SSukumar Swaminathan uint32_t word; 195fcf3ce44SJohn Forte } CtCommandResponse_t; 196fcf3ce44SJohn Forte 197291a2b48SSukumar Swaminathan typedef struct SliCtRequest 198291a2b48SSukumar Swaminathan { 199fcf3ce44SJohn Forte /* Structure is in Big Endian format */ 200291a2b48SSukumar Swaminathan CtRevisionId_t RevisionId; 201291a2b48SSukumar Swaminathan uint8_t FsType; 202291a2b48SSukumar Swaminathan uint8_t FsSubType; 203291a2b48SSukumar Swaminathan uint8_t Options; 204291a2b48SSukumar Swaminathan uint8_t Rsrvd1; 205291a2b48SSukumar Swaminathan CtCommandResponse_t CommandResponse; 206291a2b48SSukumar Swaminathan uint8_t Rsrvd2; 207291a2b48SSukumar Swaminathan uint8_t ReasonCode; 208291a2b48SSukumar Swaminathan uint8_t Explanation; 209291a2b48SSukumar Swaminathan uint8_t VendorUnique; 210291a2b48SSukumar Swaminathan 211291a2b48SSukumar Swaminathan union 212291a2b48SSukumar Swaminathan { 213291a2b48SSukumar Swaminathan uint32_t data; 214291a2b48SSukumar Swaminathan uint32_t PortID; 215291a2b48SSukumar Swaminathan 216291a2b48SSukumar Swaminathan struct gid 217291a2b48SSukumar Swaminathan { 218291a2b48SSukumar Swaminathan uint8_t PortType; /* for GID_PT requests */ 219291a2b48SSukumar Swaminathan uint8_t DomainScope; 220291a2b48SSukumar Swaminathan uint8_t AreaScope; 221291a2b48SSukumar Swaminathan uint8_t Fc4Type; /* for GID_FT requests */ 222fcf3ce44SJohn Forte } gid; 223291a2b48SSukumar Swaminathan struct rft 224291a2b48SSukumar Swaminathan { 225291a2b48SSukumar Swaminathan uint32_t PortId; /* For RFT_ID requests */ 226fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 227291a2b48SSukumar Swaminathan uint32_t rsvd0:16; 228291a2b48SSukumar Swaminathan uint32_t rsvd1:7; 229291a2b48SSukumar Swaminathan uint32_t fcpReg:1; /* Type 8 */ 230291a2b48SSukumar Swaminathan uint32_t rsvd2:2; 231291a2b48SSukumar Swaminathan uint32_t ipReg:1; /* Type 5 */ 232291a2b48SSukumar Swaminathan uint32_t rsvd3:5; 233fcf3ce44SJohn Forte #endif 234fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 235291a2b48SSukumar Swaminathan uint32_t rsvd0:16; 236291a2b48SSukumar Swaminathan uint32_t fcpReg:1; /* Type 8 */ 237291a2b48SSukumar Swaminathan uint32_t rsvd1:7; 238291a2b48SSukumar Swaminathan uint32_t rsvd3:5; 239291a2b48SSukumar Swaminathan uint32_t ipReg:1; /* Type 5 */ 240291a2b48SSukumar Swaminathan uint32_t rsvd2:2; 241291a2b48SSukumar Swaminathan #endif 242291a2b48SSukumar Swaminathan uint32_t rsvd[7]; 243fcf3ce44SJohn Forte } rft; 244fcf3ce44SJohn Forte 245291a2b48SSukumar Swaminathan struct rsnn 246291a2b48SSukumar Swaminathan { 247291a2b48SSukumar Swaminathan uint8_t wwnn[8]; 248291a2b48SSukumar Swaminathan uint8_t snn_len; 249291a2b48SSukumar Swaminathan char snn[256]; 250fcf3ce44SJohn Forte } rsnn; 251fcf3ce44SJohn Forte 252291a2b48SSukumar Swaminathan struct rspn 253291a2b48SSukumar Swaminathan { 254291a2b48SSukumar Swaminathan uint32_t PortId; 255291a2b48SSukumar Swaminathan uint8_t spn_len; 256291a2b48SSukumar Swaminathan char spn[256]; 257fcf3ce44SJohn Forte } rspn; 258fcf3ce44SJohn Forte } un; 259fcf3ce44SJohn Forte } SliCtRequest_t; 260fcf3ce44SJohn Forte typedef SliCtRequest_t SLI_CT_REQUEST; 261fcf3ce44SJohn Forte 262291a2b48SSukumar Swaminathan #define SLI_CT_REVISION 1 263fcf3ce44SJohn Forte 264fcf3ce44SJohn Forte 265fcf3ce44SJohn Forte /* 266fcf3ce44SJohn Forte * FsType Definitions 267fcf3ce44SJohn Forte */ 268fcf3ce44SJohn Forte 269291a2b48SSukumar Swaminathan #define SLI_CT_MANAGEMENT_SERVICE 0xFA 270291a2b48SSukumar Swaminathan #define SLI_CT_TIME_SERVICE 0xFB 271291a2b48SSukumar Swaminathan #define SLI_CT_DIRECTORY_SERVICE 0xFC 272291a2b48SSukumar Swaminathan #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 273fcf3ce44SJohn Forte 274fcf3ce44SJohn Forte /* 275fcf3ce44SJohn Forte * Directory Service Subtypes 276fcf3ce44SJohn Forte */ 277fcf3ce44SJohn Forte 278291a2b48SSukumar Swaminathan #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 279fcf3ce44SJohn Forte 280fcf3ce44SJohn Forte /* 281fcf3ce44SJohn Forte * Response Codes 282fcf3ce44SJohn Forte */ 283fcf3ce44SJohn Forte 284291a2b48SSukumar Swaminathan #define SLI_CT_RESPONSE_FS_RJT 0x8001 285291a2b48SSukumar Swaminathan #define SLI_CT_RESPONSE_FS_ACC 0x8002 286fcf3ce44SJohn Forte 287fcf3ce44SJohn Forte /* 288fcf3ce44SJohn Forte * Reason Codes 289fcf3ce44SJohn Forte */ 290fcf3ce44SJohn Forte 291291a2b48SSukumar Swaminathan #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 292291a2b48SSukumar Swaminathan #define SLI_CT_INVALID_COMMAND 0x01 293291a2b48SSukumar Swaminathan #define SLI_CT_INVALID_VERSION 0x02 294291a2b48SSukumar Swaminathan #define SLI_CT_LOGICAL_ERROR 0x03 295291a2b48SSukumar Swaminathan #define SLI_CT_INVALID_IU_SIZE 0x04 296291a2b48SSukumar Swaminathan #define SLI_CT_LOGICAL_BUSY 0x05 297291a2b48SSukumar Swaminathan #define SLI_CT_PROTOCOL_ERROR 0x07 298291a2b48SSukumar Swaminathan #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 299291a2b48SSukumar Swaminathan #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 300291a2b48SSukumar Swaminathan #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 301291a2b48SSukumar Swaminathan #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 302291a2b48SSukumar Swaminathan #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 303291a2b48SSukumar Swaminathan #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 304291a2b48SSukumar Swaminathan #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 305291a2b48SSukumar Swaminathan #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 306291a2b48SSukumar Swaminathan #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 307291a2b48SSukumar Swaminathan #define SLI_CT_VENDOR_UNIQUE 0xff 308fcf3ce44SJohn Forte 309fcf3ce44SJohn Forte /* 310fcf3ce44SJohn Forte * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 311fcf3ce44SJohn Forte */ 312fcf3ce44SJohn Forte 313291a2b48SSukumar Swaminathan #define SLI_CT_NO_PORT_ID 0x01 314291a2b48SSukumar Swaminathan #define SLI_CT_NO_PORT_NAME 0x02 315291a2b48SSukumar Swaminathan #define SLI_CT_NO_NODE_NAME 0x03 316291a2b48SSukumar Swaminathan #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 317291a2b48SSukumar Swaminathan #define SLI_CT_NO_IP_ADDRESS 0x05 318291a2b48SSukumar Swaminathan #define SLI_CT_NO_IPA 0x06 319291a2b48SSukumar Swaminathan #define SLI_CT_NO_FC4_TYPES 0x07 320291a2b48SSukumar Swaminathan #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 321291a2b48SSukumar Swaminathan #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 322291a2b48SSukumar Swaminathan #define SLI_CT_NO_PORT_TYPE 0x0A 323291a2b48SSukumar Swaminathan #define SLI_CT_ACCESS_DENIED 0x10 324291a2b48SSukumar Swaminathan #define SLI_CT_INVALID_PORT_ID 0x11 325291a2b48SSukumar Swaminathan #define SLI_CT_DATABASE_EMPTY 0x12 326fcf3ce44SJohn Forte 327fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 328fcf3ce44SJohn Forte #define CT_CMD_MASK 0xffff0000 329fcf3ce44SJohn Forte #endif 330fcf3ce44SJohn Forte 331fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 332fcf3ce44SJohn Forte #define CT_CMD_MASK 0xffff 333fcf3ce44SJohn Forte #endif 334fcf3ce44SJohn Forte 335fcf3ce44SJohn Forte /* 336fcf3ce44SJohn Forte * Management Server Interface Command Codes 337fcf3ce44SJohn Forte */ 338fcf3ce44SJohn Forte 339291a2b48SSukumar Swaminathan #define MS_GTIN 0x0100 340291a2b48SSukumar Swaminathan #define MS_GIEL 0x0101 341291a2b48SSukumar Swaminathan #define MS_GIET 0x0111 342291a2b48SSukumar Swaminathan #define MS_GDID 0x0112 343291a2b48SSukumar Swaminathan #define MS_GMID 0x0113 344291a2b48SSukumar Swaminathan #define MS_GFN 0x0114 345291a2b48SSukumar Swaminathan #define MS_GIELN 0x0115 346291a2b48SSukumar Swaminathan #define MS_GMAL 0x0116 347291a2b48SSukumar Swaminathan #define MS_GIEIL 0x0117 348291a2b48SSukumar Swaminathan #define MS_GPL 0x0118 349291a2b48SSukumar Swaminathan #define MS_GPT 0x0121 350291a2b48SSukumar Swaminathan #define MS_GPPN 0x0122 351291a2b48SSukumar Swaminathan #define MS_GAPNL 0x0124 352291a2b48SSukumar Swaminathan #define MS_GPS 0x0126 353291a2b48SSukumar Swaminathan #define MS_GPSC 0x0127 354291a2b48SSukumar Swaminathan #define MS_GATIN 0x0128 355291a2b48SSukumar Swaminathan #define MS_GSES 0x0130 356291a2b48SSukumar Swaminathan #define MS_GPLNL 0x0191 357291a2b48SSukumar Swaminathan #define MS_GPLT 0x0192 358291a2b48SSukumar Swaminathan #define MS_GPLML 0x0193 359291a2b48SSukumar Swaminathan #define MS_GPAB 0x0197 360291a2b48SSukumar Swaminathan #define MS_GNPL 0x01A1 361291a2b48SSukumar Swaminathan #define MS_GPNL 0x01A2 362291a2b48SSukumar Swaminathan #define MS_GPFCP 0x01A4 363291a2b48SSukumar Swaminathan #define MS_GPLI 0x01A5 364291a2b48SSukumar Swaminathan #define MS_GNID 0x01B1 365291a2b48SSukumar Swaminathan #define MS_RIELN 0x0215 366291a2b48SSukumar Swaminathan #define MS_RPL 0x0280 367291a2b48SSukumar Swaminathan #define MS_RPLN 0x0291 368291a2b48SSukumar Swaminathan #define MS_RPLT 0x0292 369291a2b48SSukumar Swaminathan #define MS_RPLM 0x0293 370291a2b48SSukumar Swaminathan #define MS_RPAB 0x0298 371291a2b48SSukumar Swaminathan #define MS_RPFCP 0x029A 372291a2b48SSukumar Swaminathan #define MS_RPLI 0x029B 373291a2b48SSukumar Swaminathan #define MS_DPL 0x0380 374291a2b48SSukumar Swaminathan #define MS_DPLN 0x0391 375291a2b48SSukumar Swaminathan #define MS_DPLM 0x0392 376291a2b48SSukumar Swaminathan #define MS_DPLML 0x0393 377291a2b48SSukumar Swaminathan #define MS_DPLI 0x0394 378291a2b48SSukumar Swaminathan #define MS_DPAB 0x0395 379291a2b48SSukumar Swaminathan #define MS_DPALL 0x039F 380fcf3ce44SJohn Forte 381fcf3ce44SJohn Forte /* 382fcf3ce44SJohn Forte * Name Server Command Codes 383fcf3ce44SJohn Forte */ 384291a2b48SSukumar Swaminathan #define SLI_CTNS_GA_NXT 0x0100 385291a2b48SSukumar Swaminathan #define SLI_CTNS_GPN_ID 0x0112 386291a2b48SSukumar Swaminathan #define SLI_CTNS_GNN_ID 0x0113 387291a2b48SSukumar Swaminathan #define SLI_CTNS_GCS_ID 0x0114 388291a2b48SSukumar Swaminathan #define SLI_CTNS_GFT_ID 0x0117 389291a2b48SSukumar Swaminathan #define SLI_CTNS_GSPN_ID 0x0118 390291a2b48SSukumar Swaminathan #define SLI_CTNS_GPT_ID 0x011A 391291a2b48SSukumar Swaminathan #define SLI_CTNS_GID_PN 0x0121 392291a2b48SSukumar Swaminathan #define SLI_CTNS_GID_NN 0x0131 393291a2b48SSukumar Swaminathan #define SLI_CTNS_GIP_NN 0x0135 394291a2b48SSukumar Swaminathan #define SLI_CTNS_GIPA_NN 0x0136 395291a2b48SSukumar Swaminathan #define SLI_CTNS_GSNN_NN 0x0139 396291a2b48SSukumar Swaminathan #define SLI_CTNS_GNN_IP 0x0153 397291a2b48SSukumar Swaminathan #define SLI_CTNS_GIPA_IP 0x0156 398291a2b48SSukumar Swaminathan #define SLI_CTNS_GID_FT 0x0171 399291a2b48SSukumar Swaminathan #define SLI_CTNS_GID_PT 0x01A1 400291a2b48SSukumar Swaminathan #define SLI_CTNS_RPN_ID 0x0212 401291a2b48SSukumar Swaminathan #define SLI_CTNS_RNN_ID 0x0213 402291a2b48SSukumar Swaminathan #define SLI_CTNS_RCS_ID 0x0214 403291a2b48SSukumar Swaminathan #define SLI_CTNS_RFT_ID 0x0217 404291a2b48SSukumar Swaminathan #define SLI_CTNS_RSPN_ID 0x0218 405291a2b48SSukumar Swaminathan #define SLI_CTNS_RPT_ID 0x021A 406291a2b48SSukumar Swaminathan #define SLI_CTNS_RIP_NN 0x0235 407291a2b48SSukumar Swaminathan #define SLI_CTNS_RIPA_NN 0x0236 408291a2b48SSukumar Swaminathan #define SLI_CTNS_RSNN_NN 0x0239 409291a2b48SSukumar Swaminathan #define SLI_CTNS_DA_ID 0x0300 410291a2b48SSukumar Swaminathan 411291a2b48SSukumar Swaminathan #define SLI_CT_LOOPBACK 0xFCFC 412fcf3ce44SJohn Forte 413fcf3ce44SJohn Forte 414fcf3ce44SJohn Forte /* 415fcf3ce44SJohn Forte * Port Types 416fcf3ce44SJohn Forte */ 417fcf3ce44SJohn Forte 418291a2b48SSukumar Swaminathan #define SLI_CTPT_N_PORT 0x01 419291a2b48SSukumar Swaminathan #define SLI_CTPT_NL_PORT 0x02 420291a2b48SSukumar Swaminathan #define SLI_CTPT_FNL_PORT 0x03 421291a2b48SSukumar Swaminathan #define SLI_CTPT_IP 0x04 422291a2b48SSukumar Swaminathan #define SLI_CTPT_FCP 0x08 423291a2b48SSukumar Swaminathan #define SLI_CTPT_NX_PORT 0x7F 424291a2b48SSukumar Swaminathan #define SLI_CTPT_F_PORT 0x81 425291a2b48SSukumar Swaminathan #define SLI_CTPT_FL_PORT 0x82 426291a2b48SSukumar Swaminathan #define SLI_CTPT_E_PORT 0x84 427fcf3ce44SJohn Forte 428fcf3ce44SJohn Forte #define SLI_CT_LAST_ENTRY 0x80000000 429fcf3ce44SJohn Forte 430fcf3ce44SJohn Forte /* ===================================================================== */ 431fcf3ce44SJohn Forte 432fcf3ce44SJohn Forte /* 433fcf3ce44SJohn Forte * Start FireFly Register definitions 434fcf3ce44SJohn Forte */ 435fcf3ce44SJohn Forte 436fcf3ce44SJohn Forte /* PCI register offsets */ 437291a2b48SSukumar Swaminathan #define MEM_ADDR_OFFSET 0x10 /* SLIM base memory address */ 438fcf3ce44SJohn Forte #define MEMH_OFFSET 0x14 /* SLIM base memory high address */ 439291a2b48SSukumar Swaminathan #define REG_ADDR_OFFSET 0x18 /* REGISTER base memory address */ 440fcf3ce44SJohn Forte #define REGH_OFFSET 0x1c /* REGISTER base memory high address */ 441291a2b48SSukumar Swaminathan #define IO_ADDR_OFFSET 0x20 /* BIU I/O registers */ 442291a2b48SSukumar Swaminathan #define REGIOH_OFFSET 0x24 /* REGISTER base io high address */ 443fcf3ce44SJohn Forte 444291a2b48SSukumar Swaminathan #define CMD_REG_OFFSET 0x4 /* PCI command configuration */ 445fcf3ce44SJohn Forte 446fcf3ce44SJohn Forte /* General PCI Register Definitions */ 447fcf3ce44SJohn Forte /* Refer To The PCI Specification For Detailed Explanations */ 448fcf3ce44SJohn Forte 449291a2b48SSukumar Swaminathan #define PCI_VENDOR_ID_REGISTER 0x00 /* PCI Vendor ID Reg */ 450291a2b48SSukumar Swaminathan #define PCI_DEVICE_ID_REGISTER 0x02 /* PCI Device ID Reg */ 451fcf3ce44SJohn Forte #define PCI_CONFIG_ID_REGISTER 0x00 /* PCI Configuration ID Reg */ 452291a2b48SSukumar Swaminathan #define PCI_COMMAND_REGISTER 0x04 /* PCI Command Reg */ 453291a2b48SSukumar Swaminathan #define PCI_STATUS_REGISTER 0x06 /* PCI Status Reg */ 454291a2b48SSukumar Swaminathan #define PCI_REV_ID_REGISTER 0x08 /* PCI Revision ID Reg */ 455291a2b48SSukumar Swaminathan #define PCI_CLASS_CODE_REGISTER 0x09 /* PCI Class Code Reg */ 456291a2b48SSukumar Swaminathan #define PCI_CACHE_LINE_REGISTER 0x0C /* PCI Cache Line Reg */ 457291a2b48SSukumar Swaminathan #define PCI_LATENCY_TMR_REGISTER 0x0D /* PCI Latency Timer Reg */ 458291a2b48SSukumar Swaminathan #define PCI_HEADER_TYPE_REGISTER 0x0E /* PCI Header Type Reg */ 459fcf3ce44SJohn Forte #define PCI_BIST_REGISTER 0x0F /* PCI Built-In SelfTest Reg */ 460fcf3ce44SJohn Forte #define PCI_BAR_0_REGISTER 0x10 /* PCI Base Address Reg 0 */ 461fcf3ce44SJohn Forte #define PCI_BAR_1_REGISTER 0x14 /* PCI Base Address Reg 1 */ 462fcf3ce44SJohn Forte #define PCI_BAR_2_REGISTER 0x18 /* PCI Base Address Reg 2 */ 463fcf3ce44SJohn Forte #define PCI_BAR_3_REGISTER 0x1C /* PCI Base Address Reg 3 */ 464fcf3ce44SJohn Forte #define PCI_BAR_4_REGISTER 0x20 /* PCI Base Address Reg 4 */ 465fcf3ce44SJohn Forte #define PCI_BAR_5_REGISTER 0x24 /* PCI Base Address Reg 5 */ 466fcf3ce44SJohn Forte #define PCI_SSID_REGISTER 0x2C 467fcf3ce44SJohn Forte #define PCI_SSVID_REGISTER 0x2C 468fcf3ce44SJohn Forte #define PCI_SSDID_REGISTER 0x2E 469fcf3ce44SJohn Forte #define PCI_EXPANSION_ROM 0x30 /* PCI Expansion ROM Base Reg */ 470fcf3ce44SJohn Forte #define PCI_CAP_POINTER 0x34 471fcf3ce44SJohn Forte 4728f23e9faSHans Rosenfeld /* PCI capatability registers are defined in pci.h */ 4738f23e9faSHans Rosenfeld #define PCI_CAP_ID_SHIFT 0 4748f23e9faSHans Rosenfeld #define PCI_CAP_ID_MASK 0xff 4758f23e9faSHans Rosenfeld #define PCI_CAP_NEXT_PTR_SHIFT 8 4768f23e9faSHans Rosenfeld #define PCI_CAP_NEXT_PTR_MASK 0xff 4778f23e9faSHans Rosenfeld 4788f23e9faSHans Rosenfeld /* PCI extended capatability registers are defined in pcie.h */ 4798f23e9faSHans Rosenfeld #define PCI_EXT_CAP_MAX_PTR 0x30 4808f23e9faSHans Rosenfeld 4818f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_MRIOV 0x0000 /* ??? */ 4828f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_SRIOV 0x0010 4838f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_11 0x0011 4848f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_12 0x0012 4858f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_13 0x0013 4868f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_14 0x0014 4878f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_15 0x0015 4888f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_16 0x0016 4898f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_TPH 0x0017 4908f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_18 0x0018 4918f23e9faSHans Rosenfeld #define PCI_EXT_CAP_ID_SEC_PCI 0x0019 4928f23e9faSHans Rosenfeld 4938f23e9faSHans Rosenfeld /* Vendor Specific (VS) register */ 4948f23e9faSHans Rosenfeld #define PCI_VS_SLI_INTF_OFFSET 4 495fcf3ce44SJohn Forte 496fcf3ce44SJohn Forte /* PCI access methods */ 497fcf3ce44SJohn Forte #define P_CONF_T1 1 498fcf3ce44SJohn Forte #define P_CONF_T2 2 499fcf3ce44SJohn Forte 500fcf3ce44SJohn Forte /* max number of pci buses */ 501291a2b48SSukumar Swaminathan #define MAX_PCI_BUSES 0xFF 502fcf3ce44SJohn Forte 503fcf3ce44SJohn Forte /* number of PCI config bytes to access */ 504fcf3ce44SJohn Forte #define PCI_BYTE 1 505fcf3ce44SJohn Forte #define PCI_WORD 2 506fcf3ce44SJohn Forte #define PCI_DWORD 4 507fcf3ce44SJohn Forte 508fcf3ce44SJohn Forte /* PCI related constants */ 509fcf3ce44SJohn Forte #define CMD_IO_ENBL 0x0001 510291a2b48SSukumar Swaminathan #define CMD_MEM_ENBL 0x0002 511291a2b48SSukumar Swaminathan #define CMD_BUS_MASTER 0x0004 512fcf3ce44SJohn Forte #define CMD_MWI 0x0010 513291a2b48SSukumar Swaminathan #define CMD_PARITY_CHK 0x0040 514291a2b48SSukumar Swaminathan #define CMD_SERR_ENBL 0x0100 515fcf3ce44SJohn Forte 516291a2b48SSukumar Swaminathan #define CMD_CFG_VALUE 0x156 /* mem enable, master, MWI, SERR, PERR */ 517fcf3ce44SJohn Forte 518fcf3ce44SJohn Forte /* PCI addresses */ 519fcf3ce44SJohn Forte #define PCI_SPACE_ENABLE 0x0CF8 520fcf3ce44SJohn Forte #define CF1_CONFIG_ADDR_REGISTER 0x0CF8 521fcf3ce44SJohn Forte #define CF1_CONFIG_DATA_REGISTER 0x0CFC 522fcf3ce44SJohn Forte #define CF2_FORWARD_REGISTER 0x0CFA 523fcf3ce44SJohn Forte #define CF2_BASE_ADDRESS 0xC000 524fcf3ce44SJohn Forte 525fcf3ce44SJohn Forte 526291a2b48SSukumar Swaminathan #define DEFAULT_PCI_LATENCY_CLOCKS 0xf8 /* 0xF8 is a special value */ 527291a2b48SSukumar Swaminathan /* for FF11.1N6 firmware. */ 528291a2b48SSukumar Swaminathan /* Use 0x80 for pre-FF11.1N6 */ 529291a2b48SSukumar Swaminathan /* &N7, etc */ 530fcf3ce44SJohn Forte #define PCI_LATENCY_VALUE 0xf8 531fcf3ce44SJohn Forte 532fcf3ce44SJohn Forte 533fcf3ce44SJohn Forte 534fcf3ce44SJohn Forte /* ==== Register Bit Definitions ==== */ 535fcf3ce44SJohn Forte 536fcf3ce44SJohn Forte /* Used by SBUS adapter */ 537fcf3ce44SJohn Forte /* SBUS Control Register */ 538fcf3ce44SJohn Forte #define SBUS_CTRL_REG_OFFSET 0 /* Word offset from reg base addr */ 539fcf3ce44SJohn Forte 540fcf3ce44SJohn Forte #define SBUS_CTRL_SBRST 0x00000001 /* Bit 0 */ 541fcf3ce44SJohn Forte #define SBUS_CTRL_BKOFF 0x00000002 /* Bit 1 */ 542fcf3ce44SJohn Forte #define SBUS_CTRL_ENP 0x00000004 /* Bit 2 */ 543fcf3ce44SJohn Forte #define SBUS_CTRL_EN64 0x00000008 /* Bit 3 */ 544291a2b48SSukumar Swaminathan #define SBUS_CTRL_SIR_1 0x00000010 /* Bit [6:4] IRL 1, */ 545291a2b48SSukumar Swaminathan /* lowset priority */ 546fcf3ce44SJohn Forte #define SBUS_CTRL_SIR_2 0x00000020 547fcf3ce44SJohn Forte #define SBUS_CTRL_SIR_3 0x00000030 548fcf3ce44SJohn Forte #define SBUS_CTRL_SIR_4 0x00000040 549fcf3ce44SJohn Forte #define SBUS_CTRL_SIR_5 0x00000050 550fcf3ce44SJohn Forte #define SBUS_CTRL_SIR_6 0x00000060 551fcf3ce44SJohn Forte #define SBUS_CTRL_SIR_7 0x00000070 /* IRL 7, highest priority */ 552fcf3ce44SJohn Forte 553fcf3ce44SJohn Forte /* SBUS Status Register */ 554fcf3ce44SJohn Forte #define SBUS_STAT_REG_OFFSET 1 /* Word offset from reg base addr */ 555fcf3ce44SJohn Forte #define SBUS_STAT_IP 0x00000001 /* Bit 0 */ 556fcf3ce44SJohn Forte #define SBUS_STAT_LERR 0x00000002 /* Bit 1 */ 557fcf3ce44SJohn Forte #define SBUS_STAT_SBPE 0x00000004 /* Bit 2 */ 558fcf3ce44SJohn Forte #define SBUS_STAT_TE 0x00000008 /* Bit 3 */ 559fcf3ce44SJohn Forte #define SBUS_STAT_WPE 0x00000010 /* Bit 4 */ 560fcf3ce44SJohn Forte #define SBUS_STAT_PERR 0x00000020 /* Bit 5 */ 561fcf3ce44SJohn Forte #define SBUS_STAT_SERR 0x00000040 /* Bit 6 */ 562fcf3ce44SJohn Forte #define SBUS_STAT_PTA 0x00000080 /* Bit 7 */ 563fcf3ce44SJohn Forte 564fcf3ce44SJohn Forte /* SBUS Update Register */ 565fcf3ce44SJohn Forte #define SBUS_UPDATE_REG_OFFSET 2 /* Word offfset from reg base addr */ 566fcf3ce44SJohn Forte 567fcf3ce44SJohn Forte #define SBUS_UPDATE_DATA 0x00000001 /* Bit 0 */ 568fcf3ce44SJohn Forte #define SBUS_UPDATE_SPCLK 0x00000002 /* Bit 1 */ 569fcf3ce44SJohn Forte #define SBUS_UPDATE_SPCE 0x00000004 /* Bit 2 */ 570fcf3ce44SJohn Forte #define SBUS_UPDATE_SPRST 0x00000008 /* Bit 3 */ 571fcf3ce44SJohn Forte #define SBUS_UPDATE_SPWE 0x00000010 /* Bit 4 */ 572fcf3ce44SJohn Forte #define SBUS_UPDATE_LDFPGA 0x00000080 /* Bit 7 */ 573fcf3ce44SJohn Forte 574fcf3ce44SJohn Forte /* Host Attention Register */ 575fcf3ce44SJohn Forte 576fcf3ce44SJohn Forte #define HA_REG_OFFSET 0 /* Word offset from register base address */ 577fcf3ce44SJohn Forte 578fcf3ce44SJohn Forte #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 579fcf3ce44SJohn Forte #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 580fcf3ce44SJohn Forte #define HA_R0ATT 0x00000008 /* Bit 3 */ 581fcf3ce44SJohn Forte #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 582fcf3ce44SJohn Forte #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 583fcf3ce44SJohn Forte #define HA_R1ATT 0x00000080 /* Bit 7 */ 584fcf3ce44SJohn Forte #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 585fcf3ce44SJohn Forte #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 586fcf3ce44SJohn Forte #define HA_R2ATT 0x00000800 /* Bit 11 */ 587fcf3ce44SJohn Forte #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 588fcf3ce44SJohn Forte #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 589fcf3ce44SJohn Forte #define HA_R3ATT 0x00008000 /* Bit 15 */ 590fcf3ce44SJohn Forte #define HA_LATT 0x20000000 /* Bit 29 */ 591fcf3ce44SJohn Forte #define HA_MBATT 0x40000000 /* Bit 30 */ 592fcf3ce44SJohn Forte #define HA_ERATT 0x80000000 /* Bit 31 */ 593fcf3ce44SJohn Forte 594fcf3ce44SJohn Forte 595fcf3ce44SJohn Forte #ifdef MSI_SUPPORT 596fcf3ce44SJohn Forte 59782527734SSukumar Swaminathan 598fcf3ce44SJohn Forte /* Host attention interrupt map */ 599291a2b48SSukumar Swaminathan #define EMLXS_MSI_MAP8 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, \ 600291a2b48SSukumar Swaminathan HA_R3ATT, HA_LATT, HA_MBATT, HA_ERATT} 601291a2b48SSukumar Swaminathan #define EMLXS_MSI_MAP4 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, 0, 0, 0, 0} 602291a2b48SSukumar Swaminathan #define EMLXS_MSI_MAP2 {0, HA_R0ATT, 0, 0, 0, 0, 0, 0} 603291a2b48SSukumar Swaminathan #define EMLXS_MSI_MAP1 {0, 0, 0, 0, 0, 0, 0, 0} 604fcf3ce44SJohn Forte 605fcf3ce44SJohn Forte /* MSI 0 interrupt mask */ 606291a2b48SSukumar Swaminathan #define EMLXS_MSI0_MASK8 0 607291a2b48SSukumar Swaminathan #define EMLXS_MSI0_MASK4 (HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \ 608291a2b48SSukumar Swaminathan HC_ERINT_ENA) 609291a2b48SSukumar Swaminathan #define EMLXS_MSI0_MASK2 (HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA| \ 610291a2b48SSukumar Swaminathan HC_MBINT_ENA|HC_LAINT_ENA|HC_ERINT_ENA) 611291a2b48SSukumar Swaminathan #define EMLXS_MSI0_MASK1 (HC_R0INT_ENA|HC_R1INT_ENA|HC_R2INT_ENA| \ 612291a2b48SSukumar Swaminathan HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \ 613291a2b48SSukumar Swaminathan HC_ERINT_ENA) 614fcf3ce44SJohn Forte 615fcf3ce44SJohn Forte 616291a2b48SSukumar Swaminathan #define EMLXS_MSI_MAX_INTRS 8 617fcf3ce44SJohn Forte 618291a2b48SSukumar Swaminathan #define EMLXS_MSI_MODE1 0 619291a2b48SSukumar Swaminathan #define EMLXS_MSI_MODE2 1 620291a2b48SSukumar Swaminathan #define EMLXS_MSI_MODE4 2 621291a2b48SSukumar Swaminathan #define EMLXS_MSI_MODE8 3 622291a2b48SSukumar Swaminathan #define EMLXS_MSI_MODES 4 623fcf3ce44SJohn Forte 624fcf3ce44SJohn Forte #endif /* MSI_SUPPORT */ 625fcf3ce44SJohn Forte 626fcf3ce44SJohn Forte 627291a2b48SSukumar Swaminathan #define IO_THROTTLE_RESERVE 12 628fcf3ce44SJohn Forte 629fcf3ce44SJohn Forte 630fcf3ce44SJohn Forte 631fcf3ce44SJohn Forte 632fcf3ce44SJohn Forte /* Chip Attention Register */ 633fcf3ce44SJohn Forte 634291a2b48SSukumar Swaminathan #define CA_REG_OFFSET 1 /* Word offset from register base address */ 635fcf3ce44SJohn Forte 636fcf3ce44SJohn Forte #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 637fcf3ce44SJohn Forte #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 638fcf3ce44SJohn Forte #define CA_R0ATT 0x00000008 /* Bit 3 */ 639fcf3ce44SJohn Forte #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 640fcf3ce44SJohn Forte #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 641fcf3ce44SJohn Forte #define CA_R1ATT 0x00000080 /* Bit 7 */ 642fcf3ce44SJohn Forte #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 643fcf3ce44SJohn Forte #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 644fcf3ce44SJohn Forte #define CA_R2ATT 0x00000800 /* Bit 11 */ 645fcf3ce44SJohn Forte #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 646fcf3ce44SJohn Forte #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 647fcf3ce44SJohn Forte #define CA_R3ATT 0x00008000 /* Bit 15 */ 648fcf3ce44SJohn Forte #define CA_MBATT 0x40000000 /* Bit 30 */ 649fcf3ce44SJohn Forte 650fcf3ce44SJohn Forte /* Host Status Register */ 651fcf3ce44SJohn Forte 652291a2b48SSukumar Swaminathan #define HS_REG_OFFSET 2 /* Word offset from register base address */ 653fcf3ce44SJohn Forte 654fcf3ce44SJohn Forte #define HS_OVERTEMP 0x00000100 /* Bit 8 */ 655fcf3ce44SJohn Forte #define HS_MBRDY 0x00400000 /* Bit 22 */ 656fcf3ce44SJohn Forte #define HS_FFRDY 0x00800000 /* Bit 23 */ 657fcf3ce44SJohn Forte #define HS_FFER8 0x01000000 /* Bit 24 */ 658fcf3ce44SJohn Forte #define HS_FFER7 0x02000000 /* Bit 25 */ 659fcf3ce44SJohn Forte #define HS_FFER6 0x04000000 /* Bit 26 */ 660fcf3ce44SJohn Forte #define HS_FFER5 0x08000000 /* Bit 27 */ 661fcf3ce44SJohn Forte #define HS_FFER4 0x10000000 /* Bit 28 */ 662fcf3ce44SJohn Forte #define HS_FFER3 0x20000000 /* Bit 29 */ 663fcf3ce44SJohn Forte #define HS_FFER2 0x40000000 /* Bit 30 */ 664fcf3ce44SJohn Forte #define HS_FFER1 0x80000000 /* Bit 31 */ 665fcf3ce44SJohn Forte #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */ 666fcf3ce44SJohn Forte 667fcf3ce44SJohn Forte /* Host Control Register */ 668fcf3ce44SJohn Forte 669291a2b48SSukumar Swaminathan #define HC_REG_OFFSET 3 /* Word offset from register base address */ 670fcf3ce44SJohn Forte 671fcf3ce44SJohn Forte #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 672fcf3ce44SJohn Forte #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 673fcf3ce44SJohn Forte #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 674fcf3ce44SJohn Forte #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 675fcf3ce44SJohn Forte #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 676fcf3ce44SJohn Forte #define HC_INITHBI 0x02000000 /* Bit 25 */ 677fcf3ce44SJohn Forte #define HC_INITMB 0x04000000 /* Bit 26 */ 678fcf3ce44SJohn Forte #define HC_INITFF 0x08000000 /* Bit 27 */ 679fcf3ce44SJohn Forte #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 680fcf3ce44SJohn Forte #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 681fcf3ce44SJohn Forte 682fcf3ce44SJohn Forte /* BIU Configuration Register */ 683fcf3ce44SJohn Forte 684291a2b48SSukumar Swaminathan #define BC_REG_OFFSET 4 /* Word offset from register base address */ 685fcf3ce44SJohn Forte 686fcf3ce44SJohn Forte #define BC_BSE 0x00000001 /* Bit 0 */ 687fcf3ce44SJohn Forte #define BC_BSE_SWAP 0x01000000 /* Bit 0 - swapped */ 688fcf3ce44SJohn Forte 689fcf3ce44SJohn Forte /* 690fcf3ce44SJohn Forte * End FireFly Register definitions 691fcf3ce44SJohn Forte */ 692fcf3ce44SJohn Forte 69382527734SSukumar Swaminathan /* 69482527734SSukumar Swaminathan * Start SLI 4 section. 69582527734SSukumar Swaminathan */ 69682527734SSukumar Swaminathan 69782527734SSukumar Swaminathan /* PCI Config Register offsets */ 69882527734SSukumar Swaminathan #define PCICFG_UE_STATUS_LO_OFFSET 0xA0 /* Error Indication - low */ 69982527734SSukumar Swaminathan #define PCICFG_UE_STATUS_HI_OFFSET 0xA4 /* Error Indication - high */ 700fe199829SSukumar Swaminathan #define PCICFG_UE_MASK_LO_OFFSET 0xA8 /* Error mask - low */ 701fe199829SSukumar Swaminathan #define PCICFG_UE_MASK_HI_OFFSET 0xAC /* Error mask - high */ 70282527734SSukumar Swaminathan #define PCICFG_UE_STATUS_ONLINE1 0xB0 /* Error status1 */ 70382527734SSukumar Swaminathan #define PCICFG_UE_STATUS_ONLINE2 0xB4 /* Error status2 */ 70482527734SSukumar Swaminathan 70582527734SSukumar Swaminathan /* BAR1 and BAR2 register offsets */ 70682527734SSukumar Swaminathan 70782527734SSukumar Swaminathan /* BAR1 offsets for principal registers */ 70882527734SSukumar Swaminathan #define CSR_ISR0_OFFSET 0x0C18 /* CSR for EQ interrupt indications */ 70982527734SSukumar Swaminathan #define CSR_IMR0_OFFSET 0x0C48 /* CSR for EQ interrupt masking */ 71082527734SSukumar Swaminathan #define CSR_ISCR0_OFFSET 0x0C78 /* CSR for EQ interrupt clearing */ 71182527734SSukumar Swaminathan 71282527734SSukumar Swaminathan #define ISR0_EQ0_INDC 0x00000001 /* Indication bit for EQ0 */ 71382527734SSukumar Swaminathan #define ISR0_EQ1_INDC 0x00000002 /* Indication bit for EQ1 */ 71482527734SSukumar Swaminathan #define ISR0_EQ2_INDC 0x00000004 /* Indication bit for EQ2 */ 71582527734SSukumar Swaminathan #define ISR0_EQ3_INDC 0x00000008 /* Indication bit for EQ3 */ 71682527734SSukumar Swaminathan #define ISR0_EQ4_INDC 0x00000010 /* Indication bit for EQ4 */ 71782527734SSukumar Swaminathan #define ISR0_EQ5_INDC 0x00000020 /* Indication bit for EQ5 */ 71882527734SSukumar Swaminathan #define ISR0_EQ6_INDC 0x00000040 /* Indication bit for EQ6 */ 71982527734SSukumar Swaminathan #define ISR0_EQ7_INDC 0x00000080 /* Indication bit for EQ7 */ 72082527734SSukumar Swaminathan 72182527734SSukumar Swaminathan /* MPU EP Semaphore register (ARM POST) */ 72282527734SSukumar Swaminathan #define CSR_MPU_EP_SEMAPHORE_OFFSET 0x00AC 72382527734SSukumar Swaminathan 7248f23e9faSHans Rosenfeld /* SLI Status register */ 7258f23e9faSHans Rosenfeld #define SLI_STATUS_ERROR 0x80000000 7268f23e9faSHans Rosenfeld #define SLI_STATUS_BE 0x40000000 7278f23e9faSHans Rosenfeld #define SLI_STATUS_OTI 0x20000000 7288f23e9faSHans Rosenfeld #define SLI_STATUS_DUMP_LOCATION 0x04000000 7298f23e9faSHans Rosenfeld #define SLI_STATUS_DUMP_IMAGE_PRESENT 0x02000000 7308f23e9faSHans Rosenfeld #define SLI_STATUS_RESET_NEEDED 0x01000000 7318f23e9faSHans Rosenfeld #define SLI_STATUS_READY 0x00800000 7328f23e9faSHans Rosenfeld #define SLI_STATUS_INTERRUPT_DISABLE 0x00400000 7338f23e9faSHans Rosenfeld 7348f23e9faSHans Rosenfeld /* SLI Control register */ 7358f23e9faSHans Rosenfeld #define SLI_CNTL_BE 0x40000000 7368f23e9faSHans Rosenfeld #define SLI_CNTL_INIT_PORT 0x08000000 7378f23e9faSHans Rosenfeld 7388f23e9faSHans Rosenfeld /* SLI PHYDEV Control register */ 7398f23e9faSHans Rosenfeld #define SLI_PHYDEV_RERROR 0x80000000 7408f23e9faSHans Rosenfeld #define SLI_PHYDEV_INP 0x40000000 7418f23e9faSHans Rosenfeld #define SLI_PHYDEV_IPLD 0x00008000 7428f23e9faSHans Rosenfeld #define SLI_PHYDEV_GPC 0x00004000 7438f23e9faSHans Rosenfeld #define SLI_PHYDEV_GP 0x00002000 7448f23e9faSHans Rosenfeld 7458f23e9faSHans Rosenfeld #define SLI_PHYDEV_RC_MASK 0x00000700 7468f23e9faSHans Rosenfeld #define SLI_PHYDEV_RC_UNKNOWN 0x00000000 7478f23e9faSHans Rosenfeld #define SLI_PHYDEV_RC_PROFILE 0x00000100 7488f23e9faSHans Rosenfeld #define SLI_PHYDEV_RC_FACTORY 0x00000200 7498f23e9faSHans Rosenfeld 7508f23e9faSHans Rosenfeld #define SLI_PHYDEV_FRL_MASK 0x000000F0 7518f23e9faSHans Rosenfeld #define SLI_PHYDEV_FRL_ALL 0x00000000 7528f23e9faSHans Rosenfeld #define SLI_PHYDEV_FRL_FCOE 0x00000010 7538f23e9faSHans Rosenfeld 7548f23e9faSHans Rosenfeld #define SLI_PHYDEV_LC 0x00000008 7558f23e9faSHans Rosenfeld #define SLI_PHYDEV_DD 0x00000004 7568f23e9faSHans Rosenfeld #define SLI_PHYDEV_FRST 0x00000002 7578f23e9faSHans Rosenfeld #define SLI_PHYDEV_DRST 0x00000001 7588f23e9faSHans Rosenfeld 75982527734SSukumar Swaminathan /* POST Stages of interest */ 76082527734SSukumar Swaminathan #define ARM_POST_FATAL 0x80000000 76182527734SSukumar Swaminathan #define ARM_POST_READY 0xc000 76282527734SSukumar Swaminathan #define ARM_POST_MASK 0xffff 7638f23e9faSHans Rosenfeld #define ARM_UNRECOVERABLE_ERROR 0xf000 76482527734SSukumar Swaminathan 76582527734SSukumar Swaminathan #define MPU_EP_DL 0x04000000 /* Driverloadedbitmask */ 76682527734SSukumar Swaminathan #define MPU_EP_ORI 0x08000000 /* OptionROMinstalledbitmask */ 76782527734SSukumar Swaminathan #define MPU_EP_IPC 0x10000000 /* IPaddressconflictmask */ 76882527734SSukumar Swaminathan #define MPU_EP_NIP 0x20000000 /* NoIPaddressmask */ 76982527734SSukumar Swaminathan #define MPU_EP_BFW 0x40000000 /* BackupFWinusemask */ 77082527734SSukumar Swaminathan #define MPU_EP_ERR 0x80000000 /* POSTfatalerrormask */ 77182527734SSukumar Swaminathan 77282527734SSukumar Swaminathan /* BAR2 offsets for principal doorbell registers */ 77382527734SSukumar Swaminathan 77482527734SSukumar Swaminathan #define PD_RQ_DB_OFFSET 0x00A0 /* Doorbell notify of posted RQEs */ 77582527734SSukumar Swaminathan #define PD_WQ_DB_OFFSET 0x0040 /* Doorbell notify of posted WQEs */ 77682527734SSukumar Swaminathan #define PD_CQ_DB_OFFSET 0x0120 /* Doorbell notify of processed CQEs or EQEs */ 77782527734SSukumar Swaminathan #define PD_MQ_DB_OFFSET 0x0140 /* Doorbell notify of posted MQEs */ 77882527734SSukumar Swaminathan #define PD_MB_DB_OFFSET 0x0160 /* Doorbell Bootstrap Mailbox */ 77982527734SSukumar Swaminathan 7808f23e9faSHans Rosenfeld #define SLIPORT_SEMAPHORE_OFFSET 0x0400 7818f23e9faSHans Rosenfeld #define SLIPORT_STATUS_OFFSET 0x0404 7828f23e9faSHans Rosenfeld #define SLIPORT_CONTROL_OFFSET 0x0408 7838f23e9faSHans Rosenfeld #define SLIPORT_ERROR1_OFFSET 0x040C 7848f23e9faSHans Rosenfeld #define SLIPORT_ERROR2_OFFSET 0x0410 7858f23e9faSHans Rosenfeld #define PHYSDEV_CONTROL_OFFSET 0x0414 7868f23e9faSHans Rosenfeld 7878f23e9faSHans Rosenfeld 78882527734SSukumar Swaminathan /* Doorbell definitions */ 78982527734SSukumar Swaminathan 79082527734SSukumar Swaminathan /* Defines for MQ doorbell */ 79182527734SSukumar Swaminathan #define MQ_DB_POP_SHIFT 16 /* shift for entries popped */ 79282527734SSukumar Swaminathan #define MQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 79382527734SSukumar Swaminathan 79482527734SSukumar Swaminathan /* Defines for CQ doorbell */ 79582527734SSukumar Swaminathan #define CQ_DB_POP_SHIFT 16 /* shift for entries popped */ 79682527734SSukumar Swaminathan #define CQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 79782527734SSukumar Swaminathan #define CQ_DB_REARM 0x20000000 /* Bit 29, rearm */ 798*a3170057SPaul Winder #define CQ_ID_LO_BITS 10 /* num of id bits that are "low" */ 799*a3170057SPaul Winder #define CQ_DB_ID_LO_MASK ((1 << CQ_ID_LO_BITS) - 1) 800*a3170057SPaul Winder #define CQ_DB_ID_HI_SHIFT 11 801*a3170057SPaul Winder #define CQ_DB_ID_HI_MASK (0x1F << CQ_DB_ID_HI_SHIFT) 80282527734SSukumar Swaminathan 80382527734SSukumar Swaminathan /* Defines for EQ doorbell */ 80482527734SSukumar Swaminathan #define EQ_DB_CLEAR 0x00000200 /* Bit 9, designates clear EQ ISR */ 80582527734SSukumar Swaminathan #define EQ_DB_EVENT 0x00000400 /* Bit 10, designates EQ */ 80682527734SSukumar Swaminathan #define EQ_DB_POP_SHIFT 16 /* shift for entries popped */ 80782527734SSukumar Swaminathan #define EQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 80882527734SSukumar Swaminathan #define EQ_DB_REARM 0x20000000 /* Bit 29, rearm */ 809*a3170057SPaul Winder #define EQ_ID_LO_BITS 9 /* num of id bits that are "low" */ 810*a3170057SPaul Winder #define EQ_DB_ID_LO_MASK ((1 << EQ_ID_LO_BITS) - 1) 811*a3170057SPaul Winder #define EQ_DB_ID_HI_SHIFT 11 812*a3170057SPaul Winder #define EQ_DB_ID_HI_MASK (0x1F << EQ_DB_ID_HI_SHIFT) 813*a3170057SPaul Winder 814*a3170057SPaul Winder /* Defines for WQ doorbell */ 815*a3170057SPaul Winder #define WQ_DB_POST_SHIFT 24 816*a3170057SPaul Winder #define WQ_DB_POST_MASK (0xFF << WQ_DB_POST_SHIFT) 817*a3170057SPaul Winder #define WQ_DB_IDX_SHIFT 16 818*a3170057SPaul Winder #define WQ_DB_IDX_MASK (0xFF << WQ_DB_IDX_SHIFT) 81982527734SSukumar Swaminathan 82082527734SSukumar Swaminathan /* bootstrap mailbox doorbell defines */ 82182527734SSukumar Swaminathan #define BMBX_READY 0x00000001 /* Mask for Port Ready bit */ 82282527734SSukumar Swaminathan #define BMBX_ADDR_HI 0x00000002 /* Mask for Addr Hi bit */ 823*a3170057SPaul Winder #define BMBX_ADDR 0xFFFFFFFC /* Mask for Addr bits */ 82482527734SSukumar Swaminathan 82582527734SSukumar Swaminathan /* Sizeof bootstrap mailbox */ 82682527734SSukumar Swaminathan #define EMLXS_BOOTSTRAP_MB_SIZE 256 82782527734SSukumar Swaminathan 8288f23e9faSHans Rosenfeld #define FW_INITIALIZE_WORD0 0xFF1234FF /* Initialize bootstrap wd 0 */ 8298f23e9faSHans Rosenfeld #define FW_INITIALIZE_WORD1 0xFF5678FF /* Initialize bootstrap wd 1 */ 83082527734SSukumar Swaminathan 8318f23e9faSHans Rosenfeld #define FW_DEINITIALIZE_WORD0 0xFFAABBFF /* DeInitialize bootstrap wd 0 */ 8328f23e9faSHans Rosenfeld #define FW_DEINITIALIZE_WORD1 0xFFCCDDFF /* DeInitialize bootstrap wd 1 */ 83382527734SSukumar Swaminathan 834fcf3ce44SJohn Forte /* ===================================================================== */ 835fcf3ce44SJohn Forte 836fcf3ce44SJohn Forte /* 837fcf3ce44SJohn Forte * Start of FCP specific structures 838fcf3ce44SJohn Forte */ 839fcf3ce44SJohn Forte 840291a2b48SSukumar Swaminathan typedef struct emlxs_fcp_rsp 841291a2b48SSukumar Swaminathan { 842291a2b48SSukumar Swaminathan uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 843291a2b48SSukumar Swaminathan uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 844fcf3ce44SJohn Forte 845291a2b48SSukumar Swaminathan uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 846291a2b48SSukumar Swaminathan uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 847291a2b48SSukumar Swaminathan uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 848fcf3ce44SJohn Forte #define RSP_LEN_VALID 0x01 /* bit 0 */ 849fcf3ce44SJohn Forte #define SNS_LEN_VALID 0x02 /* bit 1 */ 850fcf3ce44SJohn Forte #define RESID_OVER 0x04 /* bit 2 */ 851fcf3ce44SJohn Forte #define RESID_UNDER 0x08 /* bit 3 */ 852291a2b48SSukumar Swaminathan 853291a2b48SSukumar Swaminathan uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 854fcf3ce44SJohn Forte #define SCSI_STAT_GOOD 0x00 855fcf3ce44SJohn Forte #define SCSI_STAT_CHECK_COND 0x02 856fcf3ce44SJohn Forte #define SCSI_STAT_COND_MET 0x04 857fcf3ce44SJohn Forte #define SCSI_STAT_BUSY 0x08 858fcf3ce44SJohn Forte #define SCSI_STAT_INTERMED 0x10 859fcf3ce44SJohn Forte #define SCSI_STAT_INTERMED_CM 0x14 860fcf3ce44SJohn Forte #define SCSI_STAT_RES_CNFLCT 0x18 861fcf3ce44SJohn Forte #define SCSI_STAT_CMD_TERM 0x22 862fcf3ce44SJohn Forte #define SCSI_STAT_QUE_FULL 0x28 863fcf3ce44SJohn Forte #define SCSI_STAT_ACA_ACTIVE 0x30 864fcf3ce44SJohn Forte #define SCSI_STAT_TASK_ABORT 0x40 865fcf3ce44SJohn Forte 866291a2b48SSukumar Swaminathan uint32_t rspResId; /* Residual xfer if RESID_xxxx set */ 867291a2b48SSukumar Swaminathan /* in fcpStatus2. */ 86882527734SSukumar Swaminathan /* Received in Big Endian format */ 869291a2b48SSukumar Swaminathan uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 87082527734SSukumar Swaminathan /* Received in Big Endian format */ 871291a2b48SSukumar Swaminathan uint32_t rspRspLen; /* Length of FCP response data */ 872291a2b48SSukumar Swaminathan /* in fcpRspInfo */ 87382527734SSukumar Swaminathan /* Received in Big Endian format */ 874fcf3ce44SJohn Forte 875291a2b48SSukumar Swaminathan uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 876291a2b48SSukumar Swaminathan uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 877291a2b48SSukumar Swaminathan uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 878291a2b48SSukumar Swaminathan uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 879fcf3ce44SJohn Forte 880fcf3ce44SJohn Forte #define RSP_NO_FAILURE 0x00 881fcf3ce44SJohn Forte #define RSP_DATA_BURST_ERR 0x01 882fcf3ce44SJohn Forte #define RSP_CMD_FIELD_ERR 0x02 883fcf3ce44SJohn Forte #define RSP_RO_MISMATCH_ERR 0x03 884fcf3ce44SJohn Forte #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 885fcf3ce44SJohn Forte #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 886fcf3ce44SJohn Forte 887291a2b48SSukumar Swaminathan uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 888fcf3ce44SJohn Forte 889fcf3ce44SJohn Forte /* 890291a2b48SSukumar Swaminathan * Define maximum size of SCSI Sense buffer. 891291a2b48SSukumar Swaminathan * Seagate never issues more than 18 bytes of Sense data 892fcf3ce44SJohn Forte */ 893291a2b48SSukumar Swaminathan #define MAX_FCP_SNS 128 894291a2b48SSukumar Swaminathan uint8_t rspSnsInfo[MAX_FCP_SNS]; 895fcf3ce44SJohn Forte } emlxs_fcp_rsp; 896fcf3ce44SJohn Forte typedef emlxs_fcp_rsp FCP_RSP; 897fcf3ce44SJohn Forte 898fcf3ce44SJohn Forte 899291a2b48SSukumar Swaminathan typedef struct emlxs_fcp_cmd 900291a2b48SSukumar Swaminathan { 901291a2b48SSukumar Swaminathan uint32_t fcpLunMsl; /* most significant lun word */ 902291a2b48SSukumar Swaminathan uint32_t fcpLunLsl; /* least significant lun word */ 903fcf3ce44SJohn Forte 904fcf3ce44SJohn Forte /* 905291a2b48SSukumar Swaminathan * # of bits to shift lun id to end up in right payload word, 906291a2b48SSukumar Swaminathan * little endian = 8, big = 16. 907fcf3ce44SJohn Forte */ 908fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 909fcf3ce44SJohn Forte #define FC_LUN_SHIFT 8 910fcf3ce44SJohn Forte #define FC_ADDR_MODE_SHIFT 0 911fcf3ce44SJohn Forte #endif 912fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 913fcf3ce44SJohn Forte #define FC_LUN_SHIFT 16 914fcf3ce44SJohn Forte #define FC_ADDR_MODE_SHIFT 24 915fcf3ce44SJohn Forte #endif 916fcf3ce44SJohn Forte 917291a2b48SSukumar Swaminathan uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 918291a2b48SSukumar Swaminathan uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 919291a2b48SSukumar Swaminathan #define SIMPLE_Q 0x00 920291a2b48SSukumar Swaminathan #define HEAD_OF_Q 0x01 921291a2b48SSukumar Swaminathan #define ORDERED_Q 0x02 922291a2b48SSukumar Swaminathan #define ACA_Q 0x04 923291a2b48SSukumar Swaminathan #define UNTAGGED 0x05 924291a2b48SSukumar Swaminathan 925291a2b48SSukumar Swaminathan uint8_t fcpCntl2; /* FCP_CTL byte 2 task management */ 926291a2b48SSukumar Swaminathan /* codes */ 927291a2b48SSukumar Swaminathan #define ABORT_TASK_SET 0x02 /* Bit 1 */ 928291a2b48SSukumar Swaminathan #define CLEAR_TASK_SET 0x04 /* bit 2 */ 929291a2b48SSukumar Swaminathan #define LUN_RESET 0x10 /* bit 4 */ 930291a2b48SSukumar Swaminathan #define TARGET_RESET 0x20 /* bit 5 */ 931291a2b48SSukumar Swaminathan #define CLEAR_ACA 0x40 /* bit 6 */ 932291a2b48SSukumar Swaminathan #define TERMINATE_TASK 0x80 /* bit 7 */ 933291a2b48SSukumar Swaminathan 934291a2b48SSukumar Swaminathan uint8_t fcpCntl3; 935291a2b48SSukumar Swaminathan #define WRITE_DATA 0x01 /* Bit 0 */ 936291a2b48SSukumar Swaminathan #define READ_DATA 0x02 /* Bit 1 */ 937291a2b48SSukumar Swaminathan 938291a2b48SSukumar Swaminathan uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 939291a2b48SSukumar Swaminathan uint32_t fcpDl; /* Total transfer length */ 940fcf3ce44SJohn Forte } emlxs_fcp_cmd_t; 941fcf3ce44SJohn Forte typedef emlxs_fcp_cmd_t FCP_CMND; 942fcf3ce44SJohn Forte 943fcf3ce44SJohn Forte 944fcf3ce44SJohn Forte 945fcf3ce44SJohn Forte 946fcf3ce44SJohn Forte /* SCSI INQUIRY Command Structure */ 947fcf3ce44SJohn Forte 948291a2b48SSukumar Swaminathan typedef struct emlxs_inquiryDataType 949291a2b48SSukumar Swaminathan { 950291a2b48SSukumar Swaminathan uint8_t DeviceType:5; 951291a2b48SSukumar Swaminathan uint8_t DeviceTypeQualifier:3; 952291a2b48SSukumar Swaminathan 953291a2b48SSukumar Swaminathan uint8_t DeviceTypeModifier:7; 954291a2b48SSukumar Swaminathan uint8_t RemovableMedia:1; 955291a2b48SSukumar Swaminathan 956291a2b48SSukumar Swaminathan uint8_t Versions; 957291a2b48SSukumar Swaminathan uint8_t ResponseDataFormat; 958291a2b48SSukumar Swaminathan uint8_t AdditionalLength; 959291a2b48SSukumar Swaminathan uint8_t Reserved[2]; 960291a2b48SSukumar Swaminathan 961291a2b48SSukumar Swaminathan uint8_t SoftReset:1; 962291a2b48SSukumar Swaminathan uint8_t CommandQueue:1; 963291a2b48SSukumar Swaminathan uint8_t Reserved2:1; 964291a2b48SSukumar Swaminathan uint8_t LinkedCommands:1; 965291a2b48SSukumar Swaminathan uint8_t Synchronous:1; 966291a2b48SSukumar Swaminathan uint8_t Wide16Bit:1; 967291a2b48SSukumar Swaminathan uint8_t Wide32Bit:1; 968291a2b48SSukumar Swaminathan uint8_t RelativeAddressing:1; 969291a2b48SSukumar Swaminathan 970291a2b48SSukumar Swaminathan uint8_t VendorId[8]; 971291a2b48SSukumar Swaminathan uint8_t ProductId[16]; 972291a2b48SSukumar Swaminathan uint8_t ProductRevisionLevel[4]; 973291a2b48SSukumar Swaminathan uint8_t VendorSpecific[20]; 974291a2b48SSukumar Swaminathan uint8_t Reserved3[40]; 975fcf3ce44SJohn Forte } emlxs_inquiry_data_type_t; 976fcf3ce44SJohn Forte typedef emlxs_inquiry_data_type_t INQUIRY_DATA_DEF; 977fcf3ce44SJohn Forte 978fcf3ce44SJohn Forte 979291a2b48SSukumar Swaminathan typedef struct emlxs_read_capacity_data 980291a2b48SSukumar Swaminathan { 981291a2b48SSukumar Swaminathan uint32_t LogicalBlockAddress; 982291a2b48SSukumar Swaminathan uint32_t BytesPerBlock; 983fcf3ce44SJohn Forte } emlxs_read_capacity_data_t; 984fcf3ce44SJohn Forte typedef emlxs_read_capacity_data_t READ_CAPACITY_DATA_DEF; 985fcf3ce44SJohn Forte 986fcf3ce44SJohn Forte 987fcf3ce44SJohn Forte /* SCSI CDB command codes */ 988fcf3ce44SJohn Forte #define FCP_SCSI_FORMAT_UNIT 0x04 989fcf3ce44SJohn Forte #define FCP_SCSI_INQUIRY 0x12 990fcf3ce44SJohn Forte #define FCP_SCSI_MODE_SELECT 0x15 991fcf3ce44SJohn Forte #define FCP_SCSI_MODE_SENSE 0x1A 992fcf3ce44SJohn Forte #define FCP_SCSI_PAUSE_RESUME 0x4B 993fcf3ce44SJohn Forte #define FCP_SCSI_PLAY_AUDIO 0x45 994fcf3ce44SJohn Forte #define FCP_SCSI_PLAY_AUDIO_EXT 0xA5 995fcf3ce44SJohn Forte #define FCP_SCSI_PLAY_AUDIO_MSF 0x47 996fcf3ce44SJohn Forte #define FCP_SCSI_PLAY_AUDIO_TRK_INDX 0x48 997fcf3ce44SJohn Forte #define FCP_SCSI_PREVENT_ALLOW_REMOVAL 0x1E 998fcf3ce44SJohn Forte #define FCP_SCSI_READ_CMD 0x08 999fcf3ce44SJohn Forte #define FCP_SCSI_READ_BUFFER 0x3C 1000fcf3ce44SJohn Forte #define FCP_SCSI_READ_CAPACITY 0x25 1001fcf3ce44SJohn Forte #define FCP_SCSI_READ_DEFECT_LIST 0x37 1002fcf3ce44SJohn Forte #define FCP_SCSI_READ_EXTENDED 0x28 1003fcf3ce44SJohn Forte #define FCP_SCSI_READ_HEADER 0x44 1004fcf3ce44SJohn Forte #define FCP_SCSI_READ_LONG 0xE8 1005fcf3ce44SJohn Forte #define FCP_SCSI_READ_SUB_CHANNEL 0x42 1006fcf3ce44SJohn Forte #define FCP_SCSI_READ_TOC 0x43 1007fcf3ce44SJohn Forte #define FCP_SCSI_REASSIGN_BLOCK 0x07 1008fcf3ce44SJohn Forte #define FCP_SCSI_RECEIVE_DIAGNOSTIC_RESULTS 0x1C 1009fcf3ce44SJohn Forte #define FCP_SCSI_RELEASE_UNIT 0x17 1010fcf3ce44SJohn Forte #define FCP_SCSI_REPORT_LUNS 0xa0 1011fcf3ce44SJohn Forte #define FCP_SCSI_REQUEST_SENSE 0x03 1012fcf3ce44SJohn Forte #define FCP_SCSI_RESERVE_UNIT 0x16 1013fcf3ce44SJohn Forte #define FCP_SCSI_REZERO_UNIT 0x01 1014fcf3ce44SJohn Forte #define FCP_SCSI_SEEK 0x0B 1015fcf3ce44SJohn Forte #define FCP_SCSI_SEEK_EXTENDED 0x2B 1016fcf3ce44SJohn Forte #define FCP_SCSI_SEND_DIAGNOSTIC 0x1D 1017fcf3ce44SJohn Forte #define FCP_SCSI_START_STOP_UNIT 0x1B 1018fcf3ce44SJohn Forte #define FCP_SCSI_TEST_UNIT_READY 0x00 1019fcf3ce44SJohn Forte #define FCP_SCSI_VERIFY 0x2F 1020fcf3ce44SJohn Forte #define FCP_SCSI_WRITE_CMD 0x0A 1021fcf3ce44SJohn Forte #define FCP_SCSI_WRITE_AND_VERIFY 0x2E 1022fcf3ce44SJohn Forte #define FCP_SCSI_WRITE_BUFFER 0x3B 1023fcf3ce44SJohn Forte #define FCP_SCSI_WRITE_EXTENDED 0x2A 1024fcf3ce44SJohn Forte #define FCP_SCSI_WRITE_LONG 0xEA 1025fcf3ce44SJohn Forte #define FCP_SCSI_RELEASE_LUNR 0xBB 1026fcf3ce44SJohn Forte #define FCP_SCSI_RELEASE_LUNV 0xBF 1027fcf3ce44SJohn Forte 1028fcf3ce44SJohn Forte #define HPVA_SETPASSTHROUGHMODE 0x27 1029fcf3ce44SJohn Forte #define HPVA_EXECUTEPASSTHROUGH 0x29 1030fcf3ce44SJohn Forte #define HPVA_CREATELUN 0xE2 1031fcf3ce44SJohn Forte #define HPVA_SETLUNSECURITYLIST 0xED 1032fcf3ce44SJohn Forte #define HPVA_SETCLOCK 0xF9 1033fcf3ce44SJohn Forte #define HPVA_RECOVER 0xFA 1034fcf3ce44SJohn Forte #define HPVA_GENERICSERVICEOUT 0xFD 1035fcf3ce44SJohn Forte 1036fcf3ce44SJohn Forte #define DMEP_EXPORT_IN 0x85 1037fcf3ce44SJohn Forte #define DMEP_EXPORT_OUT 0x89 1038fcf3ce44SJohn Forte 1039fcf3ce44SJohn Forte #define MDACIOCTL_DIRECT_CMD 0x22 1040fcf3ce44SJohn Forte #define MDACIOCTL_STOREIMAGE 0x2C 1041fcf3ce44SJohn Forte #define MDACIOCTL_WRITESIGNATURE 0xA6 1042fcf3ce44SJohn Forte #define MDACIOCTL_SETREALTIMECLOCK 0xAC 1043fcf3ce44SJohn Forte #define MDACIOCTL_PASS_THRU_CDB 0xAD 1044fcf3ce44SJohn Forte #define MDACIOCTL_PASS_THRU_INITIATE 0xAE 1045fcf3ce44SJohn Forte #define MDACIOCTL_CREATENEWCONF 0xC0 1046fcf3ce44SJohn Forte #define MDACIOCTL_ADDNEWCONF 0xC4 1047fcf3ce44SJohn Forte #define MDACIOCTL_MORE 0xC6 1048fcf3ce44SJohn Forte #define MDACIOCTL_SETPHYSDEVPARAMETER 0xC8 1049fcf3ce44SJohn Forte #define MDACIOCTL_SETLOGDEVPARAMETER 0xCF 1050fcf3ce44SJohn Forte #define MDACIOCTL_SETCONTROLLERPARAMETER 0xD1 1051fcf3ce44SJohn Forte #define MDACIOCTL_WRITESANMAP 0xD4 1052fcf3ce44SJohn Forte #define MDACIOCTL_SETMACADDRESS 0xD5 1053fcf3ce44SJohn Forte 1054fcf3ce44SJohn Forte /* 1055fcf3ce44SJohn Forte * End of FCP specific structures 1056fcf3ce44SJohn Forte */ 1057fcf3ce44SJohn Forte 1058291a2b48SSukumar Swaminathan #define FL_ALPA 0x00 /* AL_PA of FL_Port */ 1059fcf3ce44SJohn Forte 1060fcf3ce44SJohn Forte /* Fibre Channel Service Parameter definitions */ 1061fcf3ce44SJohn Forte 1062291a2b48SSukumar Swaminathan #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 1063291a2b48SSukumar Swaminathan #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 1064291a2b48SSukumar Swaminathan #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 1065291a2b48SSukumar Swaminathan #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 1066fcf3ce44SJohn Forte 1067291a2b48SSukumar Swaminathan #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 1068291a2b48SSukumar Swaminathan #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 1069291a2b48SSukumar Swaminathan #define FC_PH3 0x20 /* FC-PH-3 version */ 1070fcf3ce44SJohn Forte 1071291a2b48SSukumar Swaminathan #define FF_FRAME_SIZE 2048 1072fcf3ce44SJohn Forte 1073fcf3ce44SJohn Forte 1074291a2b48SSukumar Swaminathan typedef struct emlxs_rings 1075291a2b48SSukumar Swaminathan { 1076fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1077291a2b48SSukumar Swaminathan uint32_t crReserved:16; 1078291a2b48SSukumar Swaminathan uint32_t crBegin:8; 1079291a2b48SSukumar Swaminathan uint32_t crEnd:8; /* Low order bit first word */ 1080291a2b48SSukumar Swaminathan uint32_t rrReserved:16; 1081291a2b48SSukumar Swaminathan uint32_t rrBegin:8; 1082291a2b48SSukumar Swaminathan uint32_t rrEnd:8; /* Low order bit second word */ 1083fcf3ce44SJohn Forte #endif 1084fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1085291a2b48SSukumar Swaminathan uint32_t crEnd:8; /* Low order bit first word */ 1086291a2b48SSukumar Swaminathan uint32_t crBegin:8; 1087291a2b48SSukumar Swaminathan uint32_t crReserved:16; 1088291a2b48SSukumar Swaminathan uint32_t rrEnd:8; /* Low order bit second word */ 1089291a2b48SSukumar Swaminathan uint32_t rrBegin:8; 1090291a2b48SSukumar Swaminathan uint32_t rrReserved:16; 1091fcf3ce44SJohn Forte #endif 1092fcf3ce44SJohn Forte } emlxs_rings_t; 1093fcf3ce44SJohn Forte typedef emlxs_rings_t RINGS; 1094fcf3ce44SJohn Forte 1095fcf3ce44SJohn Forte 1096291a2b48SSukumar Swaminathan typedef struct emlxs_ring_def 1097291a2b48SSukumar Swaminathan { 1098fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1099291a2b48SSukumar Swaminathan uint16_t offCiocb; 1100291a2b48SSukumar Swaminathan uint16_t numCiocb; 1101291a2b48SSukumar Swaminathan uint16_t offRiocb; 1102291a2b48SSukumar Swaminathan uint16_t numRiocb; 1103fcf3ce44SJohn Forte #endif 1104fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1105291a2b48SSukumar Swaminathan uint16_t numCiocb; 1106291a2b48SSukumar Swaminathan uint16_t offCiocb; 1107291a2b48SSukumar Swaminathan uint16_t numRiocb; 1108291a2b48SSukumar Swaminathan uint16_t offRiocb; 1109fcf3ce44SJohn Forte #endif 1110fcf3ce44SJohn Forte } emlxs_ring_def_t; 1111fcf3ce44SJohn Forte typedef emlxs_ring_def_t RING_DEF; 1112fcf3ce44SJohn Forte 1113fcf3ce44SJohn Forte /* 1114fcf3ce44SJohn Forte * The following F.C. frame stuctures are defined in Big Endian format. 1115fcf3ce44SJohn Forte */ 1116fcf3ce44SJohn Forte 1117291a2b48SSukumar Swaminathan typedef struct emlxs_name_type 1118291a2b48SSukumar Swaminathan { 1119fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1120291a2b48SSukumar Swaminathan uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1121291a2b48SSukumar Swaminathan uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 */ 1122291a2b48SSukumar Swaminathan /* of IEEE ext */ 1123fcf3ce44SJohn Forte #endif 1124fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1125291a2b48SSukumar Swaminathan uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 */ 1126291a2b48SSukumar Swaminathan /* of IEEE ext */ 1127291a2b48SSukumar Swaminathan uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1128fcf3ce44SJohn Forte #endif 1129fcf3ce44SJohn Forte #define NAME_IEEE 0x1 /* IEEE name - nameType */ 1130fcf3ce44SJohn Forte #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 1131fcf3ce44SJohn Forte #define NAME_FC_TYPE 0x3 /* FC native name type */ 1132fcf3ce44SJohn Forte #define NAME_IP_TYPE 0x4 /* IP address */ 1133fcf3ce44SJohn Forte #define NAME_CCITT_TYPE 0xC 1134fcf3ce44SJohn Forte #define NAME_CCITT_GR_TYPE 0xE 1135291a2b48SSukumar Swaminathan uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, */ 1136291a2b48SSukumar Swaminathan /* IEEE extended Lsb */ 1137291a2b48SSukumar Swaminathan uint8_t IEEE[6]; /* FC IEEE address */ 1138fcf3ce44SJohn Forte } emlxs_name_type_t; 1139fcf3ce44SJohn Forte typedef emlxs_name_type_t NAME_TYPE; 1140fcf3ce44SJohn Forte 1141fcf3ce44SJohn Forte 11428f23e9faSHans Rosenfeld /* 11438f23e9faSHans Rosenfeld * Word 1 Bit 31 in common service parameter is overloaded. 11448f23e9faSHans Rosenfeld * Word 1 Bit 31 in FLOGI/FDISC request is multiple NPort request 11458f23e9faSHans Rosenfeld * Word 1 Bit 31 in FLOGI/FDISC response is clean address bit 11468f23e9faSHans Rosenfeld */ 11478f23e9faSHans Rosenfeld #define CLEAN_ADDRESS_BIT reqMultipleNPort /* Word 1, bit 31 */ 11488f23e9faSHans Rosenfeld 1149291a2b48SSukumar Swaminathan typedef struct emlxs_csp 1150291a2b48SSukumar Swaminathan { 1151291a2b48SSukumar Swaminathan uint8_t fcphHigh; /* FC Word 0, byte 0 */ 1152291a2b48SSukumar Swaminathan uint8_t fcphLow; 1153291a2b48SSukumar Swaminathan uint8_t bbCreditMsb; 1154291a2b48SSukumar Swaminathan uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 1155fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1156291a2b48SSukumar Swaminathan uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1157291a2b48SSukumar Swaminathan uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1158291a2b48SSukumar Swaminathan uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1159291a2b48SSukumar Swaminathan uint16_t fPort:1; /* FC Word 1, bit 28 */ 1160291a2b48SSukumar Swaminathan uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1161291a2b48SSukumar Swaminathan uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1162291a2b48SSukumar Swaminathan uint16_t multicast:1; /* FC Word 1, bit 25 */ 1163291a2b48SSukumar Swaminathan uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1164291a2b48SSukumar Swaminathan 1165291a2b48SSukumar Swaminathan uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1166291a2b48SSukumar Swaminathan uint16_t simplex:1; /* FC Word 1, bit 22 */ 1167291a2b48SSukumar Swaminathan 1168291a2b48SSukumar Swaminathan uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1169291a2b48SSukumar Swaminathan uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1170291a2b48SSukumar Swaminathan uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1171291a2b48SSukumar Swaminathan 1172291a2b48SSukumar Swaminathan uint16_t dhd:1; /* FC Word 1, bit 18 */ 1173291a2b48SSukumar Swaminathan uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1174291a2b48SSukumar Swaminathan uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1175fcf3ce44SJohn Forte #endif 1176fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1177291a2b48SSukumar Swaminathan uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1178291a2b48SSukumar Swaminathan uint16_t multicast:1; /* FC Word 1, bit 25 */ 1179291a2b48SSukumar Swaminathan uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1180291a2b48SSukumar Swaminathan uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1181291a2b48SSukumar Swaminathan uint16_t fPort:1; /* FC Word 1, bit 28 */ 1182291a2b48SSukumar Swaminathan uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1183291a2b48SSukumar Swaminathan uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1184291a2b48SSukumar Swaminathan uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1185291a2b48SSukumar Swaminathan 1186291a2b48SSukumar Swaminathan uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1187291a2b48SSukumar Swaminathan uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1188291a2b48SSukumar Swaminathan uint16_t dhd:1; /* FC Word 1, bit 18 */ 1189291a2b48SSukumar Swaminathan 1190291a2b48SSukumar Swaminathan uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1191291a2b48SSukumar Swaminathan uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1192291a2b48SSukumar Swaminathan uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1193291a2b48SSukumar Swaminathan 1194291a2b48SSukumar Swaminathan uint16_t simplex:1; /* FC Word 1, bit 22 */ 1195291a2b48SSukumar Swaminathan uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1196291a2b48SSukumar Swaminathan #endif 1197291a2b48SSukumar Swaminathan uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 1198291a2b48SSukumar Swaminathan uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 1199291a2b48SSukumar Swaminathan union 1200291a2b48SSukumar Swaminathan { 1201291a2b48SSukumar Swaminathan struct 1202291a2b48SSukumar Swaminathan { 1203291a2b48SSukumar Swaminathan uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 1204291a2b48SSukumar Swaminathan 1205291a2b48SSukumar Swaminathan uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 1206291a2b48SSukumar Swaminathan uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 1207291a2b48SSukumar Swaminathan 1208291a2b48SSukumar Swaminathan uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 1209fcf3ce44SJohn Forte } nPort; 1210291a2b48SSukumar Swaminathan uint32_t r_a_tov; /* R_A_TOV must be in Big */ 1211291a2b48SSukumar Swaminathan /* Endian format */ 1212fcf3ce44SJohn Forte } w2; 1213fcf3ce44SJohn Forte 1214291a2b48SSukumar Swaminathan uint32_t e_d_tov; /* E_D_TOV must be in Big */ 1215291a2b48SSukumar Swaminathan /* Endian format */ 1216fcf3ce44SJohn Forte } emlxs_csp_t; 1217fcf3ce44SJohn Forte typedef emlxs_csp_t CSP; 1218fcf3ce44SJohn Forte 1219fcf3ce44SJohn Forte 1220291a2b48SSukumar Swaminathan typedef struct emlxs_class_parms 1221291a2b48SSukumar Swaminathan { 1222fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1223291a2b48SSukumar Swaminathan uint8_t classValid:1; /* FC Word 0, bit 31 */ 1224291a2b48SSukumar Swaminathan uint8_t intermix:1; /* FC Word 0, bit 30 */ 1225291a2b48SSukumar Swaminathan uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1226291a2b48SSukumar Swaminathan uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1227291a2b48SSukumar Swaminathan uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1228291a2b48SSukumar Swaminathan uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1229fcf3ce44SJohn Forte #endif 1230fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1231291a2b48SSukumar Swaminathan uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1232291a2b48SSukumar Swaminathan uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1233291a2b48SSukumar Swaminathan uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1234291a2b48SSukumar Swaminathan uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1235291a2b48SSukumar Swaminathan uint8_t intermix:1; /* FC Word 0, bit 30 */ 1236291a2b48SSukumar Swaminathan uint8_t classValid:1; /* FC Word 0, bit 31 */ 1237fcf3ce44SJohn Forte 1238fcf3ce44SJohn Forte #endif 1239291a2b48SSukumar Swaminathan uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 1240fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1241291a2b48SSukumar Swaminathan uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1242291a2b48SSukumar Swaminathan uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1243291a2b48SSukumar Swaminathan uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1244291a2b48SSukumar Swaminathan uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1245291a2b48SSukumar Swaminathan uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1246fcf3ce44SJohn Forte #endif 1247fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1248291a2b48SSukumar Swaminathan uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1249291a2b48SSukumar Swaminathan uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1250291a2b48SSukumar Swaminathan uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1251291a2b48SSukumar Swaminathan uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1252291a2b48SSukumar Swaminathan uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1253fcf3ce44SJohn Forte #endif 1254291a2b48SSukumar Swaminathan uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 1255fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1256291a2b48SSukumar Swaminathan uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1257291a2b48SSukumar Swaminathan uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1258291a2b48SSukumar Swaminathan uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1259291a2b48SSukumar Swaminathan uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1260291a2b48SSukumar Swaminathan uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1261291a2b48SSukumar Swaminathan uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1262fcf3ce44SJohn Forte #endif 1263fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1264291a2b48SSukumar Swaminathan uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1265291a2b48SSukumar Swaminathan uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1266291a2b48SSukumar Swaminathan uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1267291a2b48SSukumar Swaminathan uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1268291a2b48SSukumar Swaminathan uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1269291a2b48SSukumar Swaminathan uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1270291a2b48SSukumar Swaminathan #endif 1271291a2b48SSukumar Swaminathan uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 1272291a2b48SSukumar Swaminathan uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 1273291a2b48SSukumar Swaminathan uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 1274291a2b48SSukumar Swaminathan 1275291a2b48SSukumar Swaminathan uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 1276291a2b48SSukumar Swaminathan uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 1277291a2b48SSukumar Swaminathan uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 1278291a2b48SSukumar Swaminathan uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 1279291a2b48SSukumar Swaminathan 1280291a2b48SSukumar Swaminathan uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 1281291a2b48SSukumar Swaminathan uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 1282291a2b48SSukumar Swaminathan uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 1283291a2b48SSukumar Swaminathan uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 1284fcf3ce44SJohn Forte } emlxs_class_parms_t; 1285fcf3ce44SJohn Forte typedef emlxs_class_parms_t CLASS_PARMS; 1286fcf3ce44SJohn Forte 1287fcf3ce44SJohn Forte 1288291a2b48SSukumar Swaminathan typedef struct emlxs_serv_parms 1289291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1290291a2b48SSukumar Swaminathan CSP cmn; 1291291a2b48SSukumar Swaminathan NAME_TYPE portName; 1292291a2b48SSukumar Swaminathan NAME_TYPE nodeName; 1293291a2b48SSukumar Swaminathan CLASS_PARMS cls1; 1294291a2b48SSukumar Swaminathan CLASS_PARMS cls2; 1295291a2b48SSukumar Swaminathan CLASS_PARMS cls3; 1296291a2b48SSukumar Swaminathan CLASS_PARMS cls4; 1297291a2b48SSukumar Swaminathan uint8_t vendorVersion[16]; 1298fcf3ce44SJohn Forte } emlxs_serv_parms_t; 1299fcf3ce44SJohn Forte typedef emlxs_serv_parms_t SERV_PARM; 1300fcf3ce44SJohn Forte 1301291a2b48SSukumar Swaminathan typedef struct 1302291a2b48SSukumar Swaminathan { 1303291a2b48SSukumar Swaminathan union 1304291a2b48SSukumar Swaminathan { 1305291a2b48SSukumar Swaminathan uint32_t word0; 1306291a2b48SSukumar Swaminathan struct 1307291a2b48SSukumar Swaminathan { 1308fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1309fcf3ce44SJohn Forte uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1310291a2b48SSukumar Swaminathan uint32_t oui:24; /* Elx Organization */ 1311291a2b48SSukumar Swaminathan /* Unique ID (0000C9) */ 1312fcf3ce44SJohn Forte #endif 1313fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1314291a2b48SSukumar Swaminathan uint32_t oui:24; /* Elx Organization */ 1315291a2b48SSukumar Swaminathan /* Unique ID (0000C9) */ 1316fcf3ce44SJohn Forte uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1317fcf3ce44SJohn Forte #endif 1318fcf3ce44SJohn Forte } w0; 1319fcf3ce44SJohn Forte } un0; 1320291a2b48SSukumar Swaminathan union 1321291a2b48SSukumar Swaminathan { 1322291a2b48SSukumar Swaminathan uint32_t word1; 1323291a2b48SSukumar Swaminathan struct 1324291a2b48SSukumar Swaminathan { 1325fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1326fcf3ce44SJohn Forte uint32_t vport:1; /* Word 1, Bit 31 */ 1327fcf3ce44SJohn Forte uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1328fcf3ce44SJohn Forte #endif 1329fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1330fcf3ce44SJohn Forte uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1331fcf3ce44SJohn Forte uint32_t vport:1; /* Word 1, Bit 31 */ 1332fcf3ce44SJohn Forte #endif 1333fcf3ce44SJohn Forte } w1; 1334fcf3ce44SJohn Forte } un1; 1335291a2b48SSukumar Swaminathan uint8_t rsvd2[8]; 1336fcf3ce44SJohn Forte } emlxs_vvl_fmt_t; 1337fcf3ce44SJohn Forte 133882527734SSukumar Swaminathan #define VALID_VENDOR_VERSION cmn.rspMultipleNPort 1339fcf3ce44SJohn Forte 1340fcf3ce44SJohn Forte 1341fcf3ce44SJohn Forte 1342fcf3ce44SJohn Forte /* 1343fcf3ce44SJohn Forte * Extended Link Service LS_COMMAND codes (Payload BYTE 0) 1344fcf3ce44SJohn Forte */ 1345fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1346291a2b48SSukumar Swaminathan #define ELS_CMD_SHIFT 24 1347291a2b48SSukumar Swaminathan #define ELS_CMD_MASK 0xff000000 1348291a2b48SSukumar Swaminathan #define ELS_RSP_MASK 0xff000000 1349291a2b48SSukumar Swaminathan #define ELS_CMD_LS_RJT 0x01000000 1350291a2b48SSukumar Swaminathan #define ELS_CMD_ACC 0x02000000 1351291a2b48SSukumar Swaminathan #define ELS_CMD_PLOGI 0x03000000 1352291a2b48SSukumar Swaminathan #define ELS_CMD_FLOGI 0x04000000 1353291a2b48SSukumar Swaminathan #define ELS_CMD_LOGO 0x05000000 1354291a2b48SSukumar Swaminathan #define ELS_CMD_ABTX 0x06000000 1355291a2b48SSukumar Swaminathan #define ELS_CMD_RCS 0x07000000 1356291a2b48SSukumar Swaminathan #define ELS_CMD_RES 0x08000000 1357291a2b48SSukumar Swaminathan #define ELS_CMD_RSS 0x09000000 1358291a2b48SSukumar Swaminathan #define ELS_CMD_RSI 0x0A000000 1359291a2b48SSukumar Swaminathan #define ELS_CMD_ESTS 0x0B000000 1360291a2b48SSukumar Swaminathan #define ELS_CMD_ESTC 0x0C000000 1361291a2b48SSukumar Swaminathan #define ELS_CMD_ADVC 0x0D000000 1362291a2b48SSukumar Swaminathan #define ELS_CMD_RTV 0x0E000000 1363291a2b48SSukumar Swaminathan #define ELS_CMD_RLS 0x0F000000 1364291a2b48SSukumar Swaminathan #define ELS_CMD_ECHO 0x10000000 1365291a2b48SSukumar Swaminathan #define ELS_CMD_TEST 0x11000000 1366291a2b48SSukumar Swaminathan #define ELS_CMD_RRQ 0x12000000 1367a9800bebSGarrett D'Amore #define ELS_CMD_REC 0x13000000 1368291a2b48SSukumar Swaminathan #define ELS_CMD_PRLI 0x20000000 1369291a2b48SSukumar Swaminathan #define ELS_CMD_PRLO 0x21000000 1370291a2b48SSukumar Swaminathan #define ELS_CMD_SCN 0x22000000 1371291a2b48SSukumar Swaminathan #define ELS_CMD_TPLS 0x23000000 1372291a2b48SSukumar Swaminathan #define ELS_CMD_GPRLO 0x24000000 1373291a2b48SSukumar Swaminathan #define ELS_CMD_GAID 0x30000000 1374291a2b48SSukumar Swaminathan #define ELS_CMD_FACT 0x31000000 1375291a2b48SSukumar Swaminathan #define ELS_CMD_FDACT 0x32000000 1376291a2b48SSukumar Swaminathan #define ELS_CMD_NACT 0x33000000 1377291a2b48SSukumar Swaminathan #define ELS_CMD_NDACT 0x34000000 1378291a2b48SSukumar Swaminathan #define ELS_CMD_QoSR 0x40000000 1379291a2b48SSukumar Swaminathan #define ELS_CMD_RVCS 0x41000000 1380291a2b48SSukumar Swaminathan #define ELS_CMD_PDISC 0x50000000 1381291a2b48SSukumar Swaminathan #define ELS_CMD_FDISC 0x51000000 1382291a2b48SSukumar Swaminathan #define ELS_CMD_ADISC 0x52000000 1383291a2b48SSukumar Swaminathan #define ELS_CMD_FARP 0x54000000 1384291a2b48SSukumar Swaminathan #define ELS_CMD_FARPR 0x55000000 1385291a2b48SSukumar Swaminathan #define ELS_CMD_FAN 0x60000000 1386291a2b48SSukumar Swaminathan #define ELS_CMD_RSCN 0x61000000 1387291a2b48SSukumar Swaminathan #define ELS_CMD_SCR 0x62000000 1388291a2b48SSukumar Swaminathan #define ELS_CMD_LINIT 0x70000000 1389291a2b48SSukumar Swaminathan #define ELS_CMD_RNID 0x78000000 1390291a2b48SSukumar Swaminathan #define ELS_CMD_AUTH 0x90000000 1391fcf3ce44SJohn Forte #endif 1392fcf3ce44SJohn Forte 1393fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1394291a2b48SSukumar Swaminathan #define ELS_CMD_SHIFT 0 1395291a2b48SSukumar Swaminathan #define ELS_CMD_MASK 0xff 1396291a2b48SSukumar Swaminathan #define ELS_RSP_MASK 0xff 1397291a2b48SSukumar Swaminathan #define ELS_CMD_LS_RJT 0x01 1398291a2b48SSukumar Swaminathan #define ELS_CMD_ACC 0x02 1399291a2b48SSukumar Swaminathan #define ELS_CMD_PLOGI 0x03 1400291a2b48SSukumar Swaminathan #define ELS_CMD_FLOGI 0x04 1401291a2b48SSukumar Swaminathan #define ELS_CMD_LOGO 0x05 1402291a2b48SSukumar Swaminathan #define ELS_CMD_ABTX 0x06 1403291a2b48SSukumar Swaminathan #define ELS_CMD_RCS 0x07 1404291a2b48SSukumar Swaminathan #define ELS_CMD_RES 0x08 1405291a2b48SSukumar Swaminathan #define ELS_CMD_RSS 0x09 1406291a2b48SSukumar Swaminathan #define ELS_CMD_RSI 0x0A 1407291a2b48SSukumar Swaminathan #define ELS_CMD_ESTS 0x0B 1408291a2b48SSukumar Swaminathan #define ELS_CMD_ESTC 0x0C 1409291a2b48SSukumar Swaminathan #define ELS_CMD_ADVC 0x0D 1410291a2b48SSukumar Swaminathan #define ELS_CMD_RTV 0x0E 1411291a2b48SSukumar Swaminathan #define ELS_CMD_RLS 0x0F 1412291a2b48SSukumar Swaminathan #define ELS_CMD_ECHO 0x10 1413291a2b48SSukumar Swaminathan #define ELS_CMD_TEST 0x11 1414291a2b48SSukumar Swaminathan #define ELS_CMD_RRQ 0x12 1415a9800bebSGarrett D'Amore #define ELS_CMD_REC 0x13 1416291a2b48SSukumar Swaminathan #define ELS_CMD_PRLI 0x20 1417291a2b48SSukumar Swaminathan #define ELS_CMD_PRLO 0x21 1418291a2b48SSukumar Swaminathan #define ELS_CMD_SCN 0x22 1419291a2b48SSukumar Swaminathan #define ELS_CMD_TPLS 0x23 1420291a2b48SSukumar Swaminathan #define ELS_CMD_GPRLO 0x24 1421291a2b48SSukumar Swaminathan #define ELS_CMD_GAID 0x30 1422291a2b48SSukumar Swaminathan #define ELS_CMD_FACT 0x31 1423291a2b48SSukumar Swaminathan #define ELS_CMD_FDACT 0x32 1424291a2b48SSukumar Swaminathan #define ELS_CMD_NACT 0x33 1425291a2b48SSukumar Swaminathan #define ELS_CMD_NDACT 0x34 1426291a2b48SSukumar Swaminathan #define ELS_CMD_QoSR 0x40 1427291a2b48SSukumar Swaminathan #define ELS_CMD_RVCS 0x41 1428291a2b48SSukumar Swaminathan #define ELS_CMD_PDISC 0x50 1429291a2b48SSukumar Swaminathan #define ELS_CMD_FDISC 0x51 1430291a2b48SSukumar Swaminathan #define ELS_CMD_ADISC 0x52 1431291a2b48SSukumar Swaminathan #define ELS_CMD_FARP 0x54 1432291a2b48SSukumar Swaminathan #define ELS_CMD_FARPR 0x55 1433291a2b48SSukumar Swaminathan #define ELS_CMD_FAN 0x60 1434291a2b48SSukumar Swaminathan #define ELS_CMD_RSCN 0x61 1435291a2b48SSukumar Swaminathan #define ELS_CMD_SCR 0x62 1436291a2b48SSukumar Swaminathan #define ELS_CMD_LINIT 0x70 1437291a2b48SSukumar Swaminathan #define ELS_CMD_RNID 0x78 1438291a2b48SSukumar Swaminathan #define ELS_CMD_AUTH 0x90 1439fcf3ce44SJohn Forte #endif 1440fcf3ce44SJohn Forte 1441fcf3ce44SJohn Forte 1442fcf3ce44SJohn Forte /* 1443fcf3ce44SJohn Forte * LS_RJT Payload Definition 1444fcf3ce44SJohn Forte */ 1445fcf3ce44SJohn Forte 1446291a2b48SSukumar Swaminathan typedef struct _LS_RJT 1447291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1448291a2b48SSukumar Swaminathan union 1449291a2b48SSukumar Swaminathan { 1450291a2b48SSukumar Swaminathan uint32_t lsRjtError; 1451291a2b48SSukumar Swaminathan struct 1452291a2b48SSukumar Swaminathan { 1453291a2b48SSukumar Swaminathan uint8_t lsRjtRsvd0; /* FC Word 0, */ 1454291a2b48SSukumar Swaminathan /* bit 24:31 */ 1455291a2b48SSukumar Swaminathan 1456291a2b48SSukumar Swaminathan uint8_t lsRjtRsnCode; /* FC Word 0, */ 1457291a2b48SSukumar Swaminathan /* bit 16:23 */ 1458fcf3ce44SJohn Forte /* LS_RJT reason codes */ 1459fcf3ce44SJohn Forte #define LSRJT_INVALID_CMD 0x01 1460fcf3ce44SJohn Forte #define LSRJT_LOGICAL_ERR 0x03 1461fcf3ce44SJohn Forte #define LSRJT_LOGICAL_BSY 0x05 1462fcf3ce44SJohn Forte #define LSRJT_PROTOCOL_ERR 0x07 1463fcf3ce44SJohn Forte #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 1464fcf3ce44SJohn Forte #define LSRJT_CMD_UNSUPPORTED 0x0B 1465fcf3ce44SJohn Forte #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 1466fcf3ce44SJohn Forte 1467291a2b48SSukumar Swaminathan uint8_t lsRjtRsnCodeExp; /* FC Word 0, */ 1468291a2b48SSukumar Swaminathan /* bit 8:15 */ 1469fcf3ce44SJohn Forte /* LS_RJT reason explanation */ 1470fcf3ce44SJohn Forte #define LSEXP_NOTHING_MORE 0x00 1471fcf3ce44SJohn Forte #define LSEXP_SPARM_OPTIONS 0x01 1472fcf3ce44SJohn Forte #define LSEXP_SPARM_ICTL 0x03 1473fcf3ce44SJohn Forte #define LSEXP_SPARM_RCTL 0x05 1474fcf3ce44SJohn Forte #define LSEXP_SPARM_RCV_SIZE 0x07 1475fcf3ce44SJohn Forte #define LSEXP_SPARM_CONCUR_SEQ 0x09 1476fcf3ce44SJohn Forte #define LSEXP_SPARM_CREDIT 0x0B 1477fcf3ce44SJohn Forte #define LSEXP_INVALID_PNAME 0x0D 1478fcf3ce44SJohn Forte #define LSEXP_INVALID_NNAME 0x0E 1479fcf3ce44SJohn Forte #define LSEXP_INVALID_CSP 0x0F 1480fcf3ce44SJohn Forte #define LSEXP_INVALID_ASSOC_HDR 0x11 1481fcf3ce44SJohn Forte #define LSEXP_ASSOC_HDR_REQ 0x13 1482fcf3ce44SJohn Forte #define LSEXP_INVALID_O_SID 0x15 1483fcf3ce44SJohn Forte #define LSEXP_INVALID_OX_RX 0x17 1484fcf3ce44SJohn Forte #define LSEXP_CMD_IN_PROGRESS 0x19 1485fcf3ce44SJohn Forte #define LSEXP_INVALID_NPORT_ID 0x1F 1486fcf3ce44SJohn Forte #define LSEXP_INVALID_SEQ_ID 0x21 1487fcf3ce44SJohn Forte #define LSEXP_INVALID_XCHG 0x23 1488fcf3ce44SJohn Forte #define LSEXP_INACTIVE_XCHG 0x25 1489fcf3ce44SJohn Forte #define LSEXP_RQ_REQUIRED 0x27 1490fcf3ce44SJohn Forte #define LSEXP_OUT_OF_RESOURCE 0x29 1491fcf3ce44SJohn Forte #define LSEXP_CANT_GIVE_DATA 0x2A 1492291a2b48SSukumar Swaminathan #define LSEXP_REQ_UNSUPPORTED 0x2C 1493291a2b48SSukumar Swaminathan uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 1494fcf3ce44SJohn Forte } b; 1495fcf3ce44SJohn Forte } un; 1496fcf3ce44SJohn Forte } LS_RJT; 1497fcf3ce44SJohn Forte 1498fcf3ce44SJohn Forte 1499fcf3ce44SJohn Forte /* 1500fcf3ce44SJohn Forte * N_Port Login (FLOGO/PLOGO Request) Payload Definition 1501fcf3ce44SJohn Forte */ 1502fcf3ce44SJohn Forte 1503291a2b48SSukumar Swaminathan typedef struct _LOGO 1504291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1505291a2b48SSukumar Swaminathan union 1506291a2b48SSukumar Swaminathan { 1507291a2b48SSukumar Swaminathan uint32_t nPortId32; /* Access nPortId as a word */ 1508291a2b48SSukumar Swaminathan struct 1509291a2b48SSukumar Swaminathan { 1510291a2b48SSukumar Swaminathan uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 1511291a2b48SSukumar Swaminathan uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 1512291a2b48SSukumar Swaminathan uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 1513291a2b48SSukumar Swaminathan uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 1514fcf3ce44SJohn Forte } b; 1515fcf3ce44SJohn Forte } un; 1516291a2b48SSukumar Swaminathan NAME_TYPE portName; /* N_port name field */ 1517fcf3ce44SJohn Forte } LOGO; 1518fcf3ce44SJohn Forte 1519fcf3ce44SJohn Forte 1520fcf3ce44SJohn Forte /* 1521fcf3ce44SJohn Forte * FCP Login (PRLI Request / ACC) Payload Definition 1522fcf3ce44SJohn Forte */ 1523fcf3ce44SJohn Forte 1524291a2b48SSukumar Swaminathan #define PRLX_PAGE_LEN 0x10 1525291a2b48SSukumar Swaminathan #define TPRLO_PAGE_LEN 0x14 1526fcf3ce44SJohn Forte 1527291a2b48SSukumar Swaminathan typedef struct _PRLI 1528291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1529291a2b48SSukumar Swaminathan uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 1530fcf3ce44SJohn Forte 1531fcf3ce44SJohn Forte #define PRLI_FCP_TYPE 0x08 1532291a2b48SSukumar Swaminathan uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1533fcf3ce44SJohn Forte 1534fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1535291a2b48SSukumar Swaminathan uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1536291a2b48SSukumar Swaminathan uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1537291a2b48SSukumar Swaminathan uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1538fcf3ce44SJohn Forte 1539fcf3ce44SJohn Forte /* ACC = imagePairEstablished */ 1540291a2b48SSukumar Swaminathan uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1541291a2b48SSukumar Swaminathan uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1542291a2b48SSukumar Swaminathan /* ACC ONLY */ 1543fcf3ce44SJohn Forte #endif 1544fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1545291a2b48SSukumar Swaminathan uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1546291a2b48SSukumar Swaminathan /* ACC ONLY */ 1547291a2b48SSukumar Swaminathan uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1548291a2b48SSukumar Swaminathan uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1549291a2b48SSukumar Swaminathan uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1550291a2b48SSukumar Swaminathan uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1551fcf3ce44SJohn Forte /* ACC = imagePairEstablished */ 1552fcf3ce44SJohn Forte #endif 1553291a2b48SSukumar Swaminathan #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 1554fcf3ce44SJohn Forte #define PRLI_NO_RESOURCES 0x2 1555fcf3ce44SJohn Forte #define PRLI_INIT_INCOMPLETE 0x3 1556fcf3ce44SJohn Forte #define PRLI_NO_SUCH_PA 0x4 1557fcf3ce44SJohn Forte #define PRLI_PREDEF_CONFIG 0x5 1558fcf3ce44SJohn Forte #define PRLI_PARTIAL_SUCCESS 0x6 1559fcf3ce44SJohn Forte #define PRLI_INVALID_PAGE_CNT 0x7 1560291a2b48SSukumar Swaminathan uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1561fcf3ce44SJohn Forte 1562291a2b48SSukumar Swaminathan uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1563fcf3ce44SJohn Forte 1564291a2b48SSukumar Swaminathan uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1565fcf3ce44SJohn Forte 1566291a2b48SSukumar Swaminathan uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 1567291a2b48SSukumar Swaminathan uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 1568fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1569291a2b48SSukumar Swaminathan uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1570291a2b48SSukumar Swaminathan uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1571291a2b48SSukumar Swaminathan uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1572291a2b48SSukumar Swaminathan uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1573291a2b48SSukumar Swaminathan uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1574291a2b48SSukumar Swaminathan uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1575291a2b48SSukumar Swaminathan uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1576291a2b48SSukumar Swaminathan uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1577291a2b48SSukumar Swaminathan uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1578291a2b48SSukumar Swaminathan uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1579291a2b48SSukumar Swaminathan uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1580291a2b48SSukumar Swaminathan uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1581291a2b48SSukumar Swaminathan uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1582291a2b48SSukumar Swaminathan uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1583291a2b48SSukumar Swaminathan uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1584291a2b48SSukumar Swaminathan uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1585fcf3ce44SJohn Forte #endif 1586fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1587291a2b48SSukumar Swaminathan uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1588291a2b48SSukumar Swaminathan uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1589291a2b48SSukumar Swaminathan uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1590291a2b48SSukumar Swaminathan uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1591291a2b48SSukumar Swaminathan uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1592291a2b48SSukumar Swaminathan uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1593291a2b48SSukumar Swaminathan uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1594291a2b48SSukumar Swaminathan uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1595291a2b48SSukumar Swaminathan uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1596291a2b48SSukumar Swaminathan uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1597291a2b48SSukumar Swaminathan uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1598291a2b48SSukumar Swaminathan uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1599291a2b48SSukumar Swaminathan uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1600291a2b48SSukumar Swaminathan uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1601291a2b48SSukumar Swaminathan uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1602291a2b48SSukumar Swaminathan uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1603fcf3ce44SJohn Forte #endif 1604fcf3ce44SJohn Forte } PRLI; 1605fcf3ce44SJohn Forte 1606fcf3ce44SJohn Forte /* 1607fcf3ce44SJohn Forte * FCP Logout (PRLO Request / ACC) Payload Definition 1608fcf3ce44SJohn Forte */ 1609fcf3ce44SJohn Forte 1610291a2b48SSukumar Swaminathan typedef struct _PRLO 1611291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1612291a2b48SSukumar Swaminathan uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 1613fcf3ce44SJohn Forte 1614291a2b48SSukumar Swaminathan #define PRLO_FCP_TYPE 0x08 1615291a2b48SSukumar Swaminathan uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1616fcf3ce44SJohn Forte 1617fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1618291a2b48SSukumar Swaminathan uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1619291a2b48SSukumar Swaminathan uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1620291a2b48SSukumar Swaminathan uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1621291a2b48SSukumar Swaminathan uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1622291a2b48SSukumar Swaminathan /* ACC ONLY */ 1623fcf3ce44SJohn Forte #endif 1624fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1625291a2b48SSukumar Swaminathan uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1626291a2b48SSukumar Swaminathan /* ACC ONLY */ 1627291a2b48SSukumar Swaminathan uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1628291a2b48SSukumar Swaminathan uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1629291a2b48SSukumar Swaminathan uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1630fcf3ce44SJohn Forte #endif 1631291a2b48SSukumar Swaminathan #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 1632fcf3ce44SJohn Forte #define PRLO_NO_SUCH_IMAGE 0x4 1633fcf3ce44SJohn Forte #define PRLO_INVALID_PAGE_CNT 0x7 1634fcf3ce44SJohn Forte 1635291a2b48SSukumar Swaminathan uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1636291a2b48SSukumar Swaminathan uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1637291a2b48SSukumar Swaminathan uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1638291a2b48SSukumar Swaminathan uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 1639fcf3ce44SJohn Forte } PRLO; 1640fcf3ce44SJohn Forte 1641fcf3ce44SJohn Forte 1642291a2b48SSukumar Swaminathan typedef struct _ADISC 1643291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1644291a2b48SSukumar Swaminathan uint32_t hardAL_PA; 1645291a2b48SSukumar Swaminathan NAME_TYPE portName; 1646291a2b48SSukumar Swaminathan NAME_TYPE nodeName; 1647291a2b48SSukumar Swaminathan uint32_t DID; 1648fcf3ce44SJohn Forte } ADISC; 1649fcf3ce44SJohn Forte 1650fcf3ce44SJohn Forte 1651291a2b48SSukumar Swaminathan typedef struct _FARP 1652291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1653291a2b48SSukumar Swaminathan uint32_t Mflags:8; 1654291a2b48SSukumar Swaminathan uint32_t Odid:24; 1655291a2b48SSukumar Swaminathan #define FARP_NO_ACTION 0 /* FARP information enclosed, no action */ 1656291a2b48SSukumar Swaminathan #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 1657291a2b48SSukumar Swaminathan #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 1658291a2b48SSukumar Swaminathan #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 1659291a2b48SSukumar Swaminathan #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not supported */ 1660291a2b48SSukumar Swaminathan #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not supported */ 1661291a2b48SSukumar Swaminathan uint32_t Rflags:8; 1662291a2b48SSukumar Swaminathan uint32_t Rdid:24; 1663fcf3ce44SJohn Forte #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 1664fcf3ce44SJohn Forte #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 1665291a2b48SSukumar Swaminathan NAME_TYPE OportName; 1666291a2b48SSukumar Swaminathan NAME_TYPE OnodeName; 1667291a2b48SSukumar Swaminathan NAME_TYPE RportName; 1668291a2b48SSukumar Swaminathan NAME_TYPE RnodeName; 1669291a2b48SSukumar Swaminathan uint8_t Oipaddr[16]; 1670291a2b48SSukumar Swaminathan uint8_t Ripaddr[16]; 1671fcf3ce44SJohn Forte } FARP; 1672fcf3ce44SJohn Forte 1673291a2b48SSukumar Swaminathan typedef struct _FAN 1674291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1675291a2b48SSukumar Swaminathan uint32_t Fdid; 1676291a2b48SSukumar Swaminathan NAME_TYPE FportName; 1677291a2b48SSukumar Swaminathan NAME_TYPE FnodeName; 1678fcf3ce44SJohn Forte } FAN; 1679fcf3ce44SJohn Forte 1680291a2b48SSukumar Swaminathan typedef struct _SCR 1681291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1682291a2b48SSukumar Swaminathan uint8_t resvd1; 1683291a2b48SSukumar Swaminathan uint8_t resvd2; 1684291a2b48SSukumar Swaminathan uint8_t resvd3; 1685291a2b48SSukumar Swaminathan uint8_t Function; 1686291a2b48SSukumar Swaminathan #define SCR_FUNC_FABRIC 0x01 1687291a2b48SSukumar Swaminathan #define SCR_FUNC_NPORT 0x02 1688291a2b48SSukumar Swaminathan #define SCR_FUNC_FULL 0x03 1689291a2b48SSukumar Swaminathan #define SCR_CLEAR 0xff 1690fcf3ce44SJohn Forte } SCR; 1691fcf3ce44SJohn Forte 1692291a2b48SSukumar Swaminathan typedef struct _RNID_TOP_DISC 1693291a2b48SSukumar Swaminathan { 1694291a2b48SSukumar Swaminathan NAME_TYPE portName; 1695291a2b48SSukumar Swaminathan uint8_t resvd[8]; 1696291a2b48SSukumar Swaminathan uint32_t unitType; 1697291a2b48SSukumar Swaminathan #define RNID_HBA 0x7 1698291a2b48SSukumar Swaminathan #define RNID_HOST 0xa 1699291a2b48SSukumar Swaminathan #define RNID_DRIVER 0xd 1700291a2b48SSukumar Swaminathan uint32_t physPort; 1701291a2b48SSukumar Swaminathan uint32_t attachedNodes; 1702291a2b48SSukumar Swaminathan uint16_t ipVersion; 1703291a2b48SSukumar Swaminathan #define RNID_IPV4 0x1 1704291a2b48SSukumar Swaminathan #define RNID_IPV6 0x2 1705291a2b48SSukumar Swaminathan uint16_t UDPport; 1706291a2b48SSukumar Swaminathan uint8_t ipAddr[16]; 1707291a2b48SSukumar Swaminathan uint16_t resvd1; 1708291a2b48SSukumar Swaminathan uint16_t flags; 1709291a2b48SSukumar Swaminathan #define RNID_TD_SUPPORT 0x1 1710291a2b48SSukumar Swaminathan #define RNID_LP_VALID 0x2 1711fcf3ce44SJohn Forte } RNID_TOP_DISC; 1712fcf3ce44SJohn Forte 1713291a2b48SSukumar Swaminathan typedef struct _RNID 1714291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1715291a2b48SSukumar Swaminathan uint8_t Format; 1716fcf3ce44SJohn Forte #define RNID_TOPOLOGY_DISC 0xdf 1717291a2b48SSukumar Swaminathan uint8_t CommonLen; 1718291a2b48SSukumar Swaminathan uint8_t resvd1; 1719291a2b48SSukumar Swaminathan uint8_t SpecificLen; 1720291a2b48SSukumar Swaminathan NAME_TYPE portName; 1721291a2b48SSukumar Swaminathan NAME_TYPE nodeName; 1722291a2b48SSukumar Swaminathan union 1723291a2b48SSukumar Swaminathan { 1724fcf3ce44SJohn Forte RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 1725fcf3ce44SJohn Forte } un; 1726fcf3ce44SJohn Forte } RNID; 1727fcf3ce44SJohn Forte 1728291a2b48SSukumar Swaminathan typedef struct _RRQ 1729291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1730291a2b48SSukumar Swaminathan uint32_t SID; 1731291a2b48SSukumar Swaminathan uint16_t Oxid; 1732291a2b48SSukumar Swaminathan uint16_t Rxid; 1733291a2b48SSukumar Swaminathan uint8_t resv[32]; /* optional association hdr */ 1734fcf3ce44SJohn Forte } RRQ; 1735fcf3ce44SJohn Forte 1736fcf3ce44SJohn Forte 1737fcf3ce44SJohn Forte /* This is used for RSCN command */ 1738291a2b48SSukumar Swaminathan typedef struct _D_ID 1739291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1740291a2b48SSukumar Swaminathan union 1741291a2b48SSukumar Swaminathan { 1742291a2b48SSukumar Swaminathan uint32_t word; 1743291a2b48SSukumar Swaminathan struct 1744291a2b48SSukumar Swaminathan { 1745fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1746291a2b48SSukumar Swaminathan uint8_t resv; 1747291a2b48SSukumar Swaminathan uint8_t domain; 1748291a2b48SSukumar Swaminathan uint8_t area; 1749291a2b48SSukumar Swaminathan uint8_t id; 1750fcf3ce44SJohn Forte #endif 1751fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1752291a2b48SSukumar Swaminathan uint8_t id; 1753291a2b48SSukumar Swaminathan uint8_t area; 1754291a2b48SSukumar Swaminathan uint8_t domain; 1755291a2b48SSukumar Swaminathan uint8_t resv; 1756fcf3ce44SJohn Forte #endif 1757fcf3ce44SJohn Forte } b; 1758fcf3ce44SJohn Forte } un; 1759fcf3ce44SJohn Forte } D_ID; 1760fcf3ce44SJohn Forte 1761fcf3ce44SJohn Forte /* 1762291a2b48SSukumar Swaminathan * Structure to define all ELS Payload types 1763fcf3ce44SJohn Forte */ 1764fcf3ce44SJohn Forte 1765291a2b48SSukumar Swaminathan typedef struct _ELS_PKT 1766291a2b48SSukumar Swaminathan { /* Structure is in Big Endian format */ 1767291a2b48SSukumar Swaminathan uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1768291a2b48SSukumar Swaminathan uint8_t elsByte1; 1769291a2b48SSukumar Swaminathan uint8_t elsByte2; 1770291a2b48SSukumar Swaminathan uint8_t elsByte3; 1771291a2b48SSukumar Swaminathan union 1772291a2b48SSukumar Swaminathan { 1773291a2b48SSukumar Swaminathan LS_RJT lsRjt; /* Payload for LS_RJT */ 1774291a2b48SSukumar Swaminathan SERV_PARM logi; /* Payload for PLOGI, FLOGI */ 1775291a2b48SSukumar Swaminathan /* PDISC, ACC */ 1776291a2b48SSukumar Swaminathan LOGO logo; /* Payload for PLOGO, FLOGO */ 1777291a2b48SSukumar Swaminathan /* ACC */ 1778291a2b48SSukumar Swaminathan PRLI prli; /* Payload for PRLI/ACC */ 1779291a2b48SSukumar Swaminathan PRLO prlo; /* Payload for PRLO/ACC */ 1780291a2b48SSukumar Swaminathan ADISC adisc; /* Payload for ADISC/ACC */ 1781291a2b48SSukumar Swaminathan FARP farp; /* Payload for FARP/ACC */ 1782291a2b48SSukumar Swaminathan FAN fan; /* Payload for FAN */ 1783291a2b48SSukumar Swaminathan SCR scr; /* Payload for SCR/ACC */ 1784291a2b48SSukumar Swaminathan RRQ rrq; /* Payload for RRQ */ 1785291a2b48SSukumar Swaminathan RNID rnid; /* Payload for RNID */ 1786291a2b48SSukumar Swaminathan uint8_t pad[128 - 4]; /* Pad out to payload of */ 1787291a2b48SSukumar Swaminathan /* 128 bytes */ 1788fcf3ce44SJohn Forte } un; 1789fcf3ce44SJohn Forte } ELS_PKT; 1790fcf3ce44SJohn Forte 1791fcf3ce44SJohn Forte 1792291a2b48SSukumar Swaminathan typedef struct 1793291a2b48SSukumar Swaminathan { 1794291a2b48SSukumar Swaminathan uint32_t bdeAddress; 1795fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1796291a2b48SSukumar Swaminathan uint32_t bdeReserved:4; 1797291a2b48SSukumar Swaminathan uint32_t bdeAddrHigh:4; 1798291a2b48SSukumar Swaminathan uint32_t bdeSize:24; 1799fcf3ce44SJohn Forte #endif 1800fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1801291a2b48SSukumar Swaminathan uint32_t bdeSize:24; 1802291a2b48SSukumar Swaminathan uint32_t bdeAddrHigh:4; 1803291a2b48SSukumar Swaminathan uint32_t bdeReserved:4; 1804fcf3ce44SJohn Forte #endif 1805fcf3ce44SJohn Forte } ULP_BDE; 1806fcf3ce44SJohn Forte 1807291a2b48SSukumar Swaminathan typedef struct ULP_BDE_64 1808291a2b48SSukumar Swaminathan { /* SLI-2 */ 1809291a2b48SSukumar Swaminathan union ULP_BDE_TUS 1810291a2b48SSukumar Swaminathan { 1811291a2b48SSukumar Swaminathan uint32_t w; 1812291a2b48SSukumar Swaminathan struct 1813291a2b48SSukumar Swaminathan { 1814fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1815291a2b48SSukumar Swaminathan uint32_t bdeFlags:8; /* BDE Flags 0 IS A */ 1816291a2b48SSukumar Swaminathan /* SUPPORTED VALUE !! */ 1817291a2b48SSukumar Swaminathan uint32_t bdeSize:24; /* buff size in bytes */ 1818fcf3ce44SJohn Forte #endif 1819fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1820291a2b48SSukumar Swaminathan uint32_t bdeSize:24; /* buff size in bytes */ 1821291a2b48SSukumar Swaminathan uint32_t bdeFlags:8; /* BDE Flags 0 IS A */ 1822291a2b48SSukumar Swaminathan /* SUPPORTED VALUE !! */ 1823fcf3ce44SJohn Forte #endif 1824fcf3ce44SJohn Forte #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 1825fcf3ce44SJohn Forte #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 1826291a2b48SSukumar Swaminathan #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 1827291a2b48SSukumar Swaminathan #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, */ 1828291a2b48SSukumar Swaminathan /* 0=xmit buffer */ 1829291a2b48SSukumar Swaminathan #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr */ 1830291a2b48SSukumar Swaminathan /* 0=64 bit addr */ 1831fcf3ce44SJohn Forte #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 1832fcf3ce44SJohn Forte #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 1833fcf3ce44SJohn Forte #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 1834fcf3ce44SJohn Forte } f; 1835fcf3ce44SJohn Forte } tus; 1836291a2b48SSukumar Swaminathan uint32_t addrLow; 1837291a2b48SSukumar Swaminathan uint32_t addrHigh; 1838fcf3ce44SJohn Forte } ULP_BDE64; 1839fcf3ce44SJohn Forte 1840291a2b48SSukumar Swaminathan #define BDE64_SIZE_WORD 0 1841291a2b48SSukumar Swaminathan #define BPL64_SIZE_WORD 0x40 1842fcf3ce44SJohn Forte 1843291a2b48SSukumar Swaminathan /* ULP */ 1844291a2b48SSukumar Swaminathan typedef struct ULP_BPL_64 1845291a2b48SSukumar Swaminathan { 1846291a2b48SSukumar Swaminathan ULP_BDE64 fccmd_payload; 1847291a2b48SSukumar Swaminathan ULP_BDE64 fcrsp_payload; 1848291a2b48SSukumar Swaminathan ULP_BDE64 fcdat_payload; 1849291a2b48SSukumar Swaminathan ULP_BDE64 pat0; 1850fcf3ce44SJohn Forte } ULP_BPL64; 1851fcf3ce44SJohn Forte 1852291a2b48SSukumar Swaminathan typedef struct ULP_BDL 1853291a2b48SSukumar Swaminathan { /* SLI-2 */ 1854fcf3ce44SJohn Forte #ifdef EMLXS_BIG_ENDIAN 1855291a2b48SSukumar Swaminathan uint32_t bdeFlags:8; /* BDL Flags */ 1856291a2b48SSukumar Swaminathan uint32_t bdeSize:24; /* Size of BDL array in host */ 1857291a2b48SSukumar Swaminathan /* memory (bytes) */ 1858fcf3ce44SJohn Forte #endif 1859fcf3ce44SJohn Forte #ifdef EMLXS_LITTLE_ENDIAN 1860291a2b48SSukumar Swaminathan uint32_t bdeSize:24; /* Size of BDL array in host */ 1861291a2b48SSukumar Swaminathan /* memory (bytes) */ 1862291a2b48SSukumar Swaminathan uint32_t bdeFlags:8; /* BDL Flags */ 1863fcf3ce44SJohn Forte #endif 1864291a2b48SSukumar Swaminathan uint32_t addrLow; /* Address 0:31 */ 1865291a2b48SSukumar Swaminathan uint32_t addrHigh; /* Address 32:63 */ 1866291a2b48SSukumar Swaminathan uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1867fcf3ce44SJohn Forte } ULP_BDL; 1868fcf3ce44SJohn Forte 186982527734SSukumar Swaminathan typedef struct ULP_SGE_64 187082527734SSukumar Swaminathan { /* SLI-4 */ 187182527734SSukumar Swaminathan uint32_t addrHigh; /* Address 32:63 */ 187282527734SSukumar Swaminathan uint32_t addrLow; /* Address 0:31 */ 187382527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 187482527734SSukumar Swaminathan uint32_t last:1; /* Last entry in SGL */ 18758f23e9faSHans Rosenfeld uint32_t type:4; 18768f23e9faSHans Rosenfeld uint32_t offset:27; 187782527734SSukumar Swaminathan #endif 187882527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 18798f23e9faSHans Rosenfeld uint32_t offset:27; 18808f23e9faSHans Rosenfeld uint32_t type:4; 188182527734SSukumar Swaminathan uint32_t last:1; /* Last entry in SGL */ 188282527734SSukumar Swaminathan #endif 18838f23e9faSHans Rosenfeld #define EMLXS_SGE_TYPE_DATA 0x0 18848f23e9faSHans Rosenfeld #define EMLXS_SGE_TYPE_DIF 0x4 18858f23e9faSHans Rosenfeld #define EMLXS_SGE_TYPE_LSP 0x5 18868f23e9faSHans Rosenfeld #define EMLXS_SGE_TYPE_ENC_DIF 0x6 18878f23e9faSHans Rosenfeld #define EMLXS_SGE_TYPE_ENC_SEED 0x7 18888f23e9faSHans Rosenfeld #define EMLXS_SGE_TYPE_SEED 0x8 18898f23e9faSHans Rosenfeld #define EMLXS_SGE_TYPE_ENC 0x9 18908f23e9faSHans Rosenfeld #define EMLXS_SGE_TYPE_SKIP 0xC 18918f23e9faSHans Rosenfeld 189282527734SSukumar Swaminathan uint32_t length; 189382527734SSukumar Swaminathan #define EMLXS_MAX_SGE_SIZE 0x10000 /* 64K max length */ 189482527734SSukumar Swaminathan } ULP_SGE64; 189582527734SSukumar Swaminathan 18968f23e9faSHans Rosenfeld #define EMLXS_XFER_RDY_SIZE 12 /* Payload size of a FCP Transfer Ready */ 189782527734SSukumar Swaminathan 189882527734SSukumar Swaminathan typedef struct _BE_PHYS_ADDR 189982527734SSukumar Swaminathan { 190082527734SSukumar Swaminathan uint32_t addrLow; 190182527734SSukumar Swaminathan uint32_t addrHigh; 190282527734SSukumar Swaminathan } BE_PHYS_ADDR; 190382527734SSukumar Swaminathan 190482527734SSukumar Swaminathan 1905291a2b48SSukumar Swaminathan typedef struct 1906291a2b48SSukumar Swaminathan { 1907a9800bebSGarrett D'Amore void *fc_mptr; 190882527734SSukumar Swaminathan struct emlxs_memseg *segment; /* Parent segment */ 190982527734SSukumar Swaminathan 1910a9800bebSGarrett D'Amore void *virt; /* virtual address ptr */ 1911291a2b48SSukumar Swaminathan uint64_t phys; /* mapped address */ 1912291a2b48SSukumar Swaminathan uint32_t size; 191382527734SSukumar Swaminathan 1914291a2b48SSukumar Swaminathan void *data_handle; 1915291a2b48SSukumar Swaminathan void *dma_handle; 1916291a2b48SSukumar Swaminathan uint32_t tag; 1917291a2b48SSukumar Swaminathan uint32_t flag; 1918291a2b48SSukumar Swaminathan #define MAP_POOL_ALLOCATED 0x00000001 1919291a2b48SSukumar Swaminathan #define MAP_BUF_ALLOCATED 0x00000002 1920291a2b48SSukumar Swaminathan #define MAP_TABLE_ALLOCATED 0x00000004 19218f23e9faSHans Rosenfeld 19228f23e9faSHans Rosenfeld #ifdef SFCT_SUPPORT 19238f23e9faSHans Rosenfeld void *fct_private; 19248f23e9faSHans Rosenfeld #endif /* SFCT_SUPPORT */ 1925fcf3ce44SJohn Forte } MATCHMAP; 1926fcf3ce44SJohn Forte 1927291a2b48SSukumar Swaminathan 192882527734SSukumar Swaminathan /* 192982527734SSukumar Swaminathan * This file defines the Header File for the FDMI HBA Management Service 193082527734SSukumar Swaminathan */ 1931fcf3ce44SJohn Forte 193282527734SSukumar Swaminathan /* 193382527734SSukumar Swaminathan * FDMI HBA MAnagement Operations Command Codes 193482527734SSukumar Swaminathan */ 193582527734SSukumar Swaminathan #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 193682527734SSukumar Swaminathan #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 193782527734SSukumar Swaminathan #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 193882527734SSukumar Swaminathan #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 193982527734SSukumar Swaminathan #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 194082527734SSukumar Swaminathan #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 194182527734SSukumar Swaminathan #define SLI_MGMT_RPRT 0x210 /* Register Port */ 194282527734SSukumar Swaminathan #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 194382527734SSukumar Swaminathan #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 194482527734SSukumar Swaminathan #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1945fcf3ce44SJohn Forte 194682527734SSukumar Swaminathan /* 194782527734SSukumar Swaminathan * Management Service Subtypes 194882527734SSukumar Swaminathan */ 194982527734SSukumar Swaminathan #define SLI_CT_FDMI_SUBTYPES 0x10 1950fcf3ce44SJohn Forte 1951fcf3ce44SJohn Forte 195282527734SSukumar Swaminathan /* 195382527734SSukumar Swaminathan * HBA Management Service Reject Code 195482527734SSukumar Swaminathan */ 195582527734SSukumar Swaminathan #define REJECT_CODE 0x9 /* Unable to perform command request */ 1956fcf3ce44SJohn Forte 195782527734SSukumar Swaminathan /* 195882527734SSukumar Swaminathan * HBA Management Service Reject Reason Code 195982527734SSukumar Swaminathan * Please refer to the Reason Codes above 196082527734SSukumar Swaminathan */ 1961fcf3ce44SJohn Forte 196282527734SSukumar Swaminathan /* 196382527734SSukumar Swaminathan * HBA Attribute Types 196482527734SSukumar Swaminathan */ 196582527734SSukumar Swaminathan #define NODE_NAME 0x1 196682527734SSukumar Swaminathan #define MANUFACTURER 0x2 196782527734SSukumar Swaminathan #define SERIAL_NUMBER 0x3 196882527734SSukumar Swaminathan #define MODEL 0x4 196982527734SSukumar Swaminathan #define MODEL_DESCRIPTION 0x5 197082527734SSukumar Swaminathan #define HARDWARE_VERSION 0x6 197182527734SSukumar Swaminathan #define DRIVER_VERSION 0x7 197282527734SSukumar Swaminathan #define OPTION_ROM_VERSION 0x8 197382527734SSukumar Swaminathan #define FIRMWARE_VERSION 0x9 197482527734SSukumar Swaminathan #define VENDOR_SPECIFIC 0xa 197582527734SSukumar Swaminathan #define DRV_NAME 0xb 197682527734SSukumar Swaminathan #define OS_NAME_VERSION 0xc 197782527734SSukumar Swaminathan #define MAX_CT_PAYLOAD_LEN 0xd 1978fcf3ce44SJohn Forte 197982527734SSukumar Swaminathan /* 198082527734SSukumar Swaminathan * Port Attrubute Types 198182527734SSukumar Swaminathan */ 198282527734SSukumar Swaminathan #define SUPPORTED_FC4_TYPES 0x1 198382527734SSukumar Swaminathan #define SUPPORTED_SPEED 0x2 198482527734SSukumar Swaminathan #define PORT_SPEED 0x3 198582527734SSukumar Swaminathan #define MAX_FRAME_SIZE 0x4 198682527734SSukumar Swaminathan #define OS_DEVICE_NAME 0x5 1987fcf3ce44SJohn Forte 198882527734SSukumar Swaminathan union AttributesDef 198982527734SSukumar Swaminathan { 199082527734SSukumar Swaminathan /* Structure is in Big Endian format */ 199182527734SSukumar Swaminathan struct 199282527734SSukumar Swaminathan { 199382527734SSukumar Swaminathan uint32_t AttrType:16; 199482527734SSukumar Swaminathan uint32_t AttrLen:16; 199582527734SSukumar Swaminathan } bits; 199682527734SSukumar Swaminathan uint32_t word; 199782527734SSukumar Swaminathan }; 1998fcf3ce44SJohn Forte 199982527734SSukumar Swaminathan /* 200082527734SSukumar Swaminathan * HBA Attribute Entry (8 - 260 bytes) 200182527734SSukumar Swaminathan */ 2002291a2b48SSukumar Swaminathan typedef struct 2003291a2b48SSukumar Swaminathan { 200482527734SSukumar Swaminathan union AttributesDef ad; 2005291a2b48SSukumar Swaminathan union 2006291a2b48SSukumar Swaminathan { 200782527734SSukumar Swaminathan uint32_t VendorSpecific; 200882527734SSukumar Swaminathan uint32_t SupportSpeed; 200982527734SSukumar Swaminathan uint32_t PortSpeed; 201082527734SSukumar Swaminathan uint32_t MaxFrameSize; 201182527734SSukumar Swaminathan uint32_t MaxCTPayloadLen; 201282527734SSukumar Swaminathan uint8_t SupportFC4Types[32]; 201382527734SSukumar Swaminathan uint8_t OsDeviceName[256]; 201482527734SSukumar Swaminathan uint8_t Manufacturer[64]; 201582527734SSukumar Swaminathan uint8_t SerialNumber[64]; 201682527734SSukumar Swaminathan uint8_t Model[256]; 201782527734SSukumar Swaminathan uint8_t ModelDescription[256]; 201882527734SSukumar Swaminathan uint8_t HardwareVersion[256]; 201982527734SSukumar Swaminathan uint8_t DriverVersion[256]; 202082527734SSukumar Swaminathan uint8_t OptionROMVersion[256]; 202182527734SSukumar Swaminathan uint8_t FirmwareVersion[256]; 202282527734SSukumar Swaminathan uint8_t DriverName[256]; 202382527734SSukumar Swaminathan NAME_TYPE NodeName; 2024fcf3ce44SJohn Forte } un; 202582527734SSukumar Swaminathan } ATTRIBUTE_ENTRY, *PATTRIBUTE_ENTRY; 2026fcf3ce44SJohn Forte 2027fcf3ce44SJohn Forte 202882527734SSukumar Swaminathan /* 202982527734SSukumar Swaminathan * HBA Attribute Block 203082527734SSukumar Swaminathan */ 2031291a2b48SSukumar Swaminathan typedef struct 2032291a2b48SSukumar Swaminathan { 203382527734SSukumar Swaminathan uint32_t EntryCnt; /* Number of HBA attribute entries */ 203482527734SSukumar Swaminathan ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 203582527734SSukumar Swaminathan } ATTRIBUTE_BLOCK, *PATTRIBUTE_BLOCK; 2036fcf3ce44SJohn Forte 2037fcf3ce44SJohn Forte 2038fcf3ce44SJohn Forte /* 2039fcf3ce44SJohn Forte * Port Entry 2040fcf3ce44SJohn Forte */ 2041291a2b48SSukumar Swaminathan typedef struct 2042291a2b48SSukumar Swaminathan { 2043291a2b48SSukumar Swaminathan NAME_TYPE PortName; 2044fcf3ce44SJohn Forte } PORT_ENTRY, *PPORT_ENTRY; 2045fcf3ce44SJohn Forte 2046fcf3ce44SJohn Forte /* 2047fcf3ce44SJohn Forte * HBA Identifier 2048fcf3ce44SJohn Forte */ 2049291a2b48SSukumar Swaminathan typedef struct 2050291a2b48SSukumar Swaminathan { 2051291a2b48SSukumar Swaminathan NAME_TYPE PortName; 2052fcf3ce44SJohn Forte } HBA_IDENTIFIER, *PHBA_IDENTIFIER; 2053fcf3ce44SJohn Forte 2054fcf3ce44SJohn Forte /* 2055fcf3ce44SJohn Forte * Registered Port List Format 2056fcf3ce44SJohn Forte */ 2057291a2b48SSukumar Swaminathan typedef struct 2058291a2b48SSukumar Swaminathan { 2059291a2b48SSukumar Swaminathan uint32_t EntryCnt; 2060291a2b48SSukumar Swaminathan PORT_ENTRY pe; /* Variable-length array */ 2061fcf3ce44SJohn Forte } REG_PORT_LIST, *PREG_PORT_LIST; 2062fcf3ce44SJohn Forte 2063fcf3ce44SJohn Forte /* 2064fcf3ce44SJohn Forte * Register HBA(RHBA) 2065fcf3ce44SJohn Forte */ 2066291a2b48SSukumar Swaminathan typedef struct 2067291a2b48SSukumar Swaminathan { 2068291a2b48SSukumar Swaminathan HBA_IDENTIFIER hi; 2069291a2b48SSukumar Swaminathan REG_PORT_LIST rpl; /* variable-length array */ 2070fcf3ce44SJohn Forte } REG_HBA, *PREG_HBA; 2071fcf3ce44SJohn Forte 2072fcf3ce44SJohn Forte /* 2073fcf3ce44SJohn Forte * Register HBA Attributes (RHAT) 2074fcf3ce44SJohn Forte */ 2075291a2b48SSukumar Swaminathan typedef struct 2076291a2b48SSukumar Swaminathan { 2077291a2b48SSukumar Swaminathan NAME_TYPE HBA_PortName; 2078291a2b48SSukumar Swaminathan ATTRIBUTE_BLOCK ab; 2079fcf3ce44SJohn Forte } REG_HBA_ATTRIBUTE, *PREG_HBA_ATTRIBUTE; 2080fcf3ce44SJohn Forte 2081fcf3ce44SJohn Forte /* 2082fcf3ce44SJohn Forte * Register Port Attributes (RPA) 2083fcf3ce44SJohn Forte */ 2084291a2b48SSukumar Swaminathan typedef struct 2085291a2b48SSukumar Swaminathan { 2086291a2b48SSukumar Swaminathan NAME_TYPE HBA_PortName; 2087291a2b48SSukumar Swaminathan NAME_TYPE PortName; 2088291a2b48SSukumar Swaminathan ATTRIBUTE_BLOCK ab; 2089fcf3ce44SJohn Forte } REG_PORT_ATTRIBUTE, *PREG_PORT_ATTRIBUTE; 2090fcf3ce44SJohn Forte 2091fcf3ce44SJohn Forte /* 2092fcf3ce44SJohn Forte * Get Registered HBA List (GRHL) Accept Payload Format 2093fcf3ce44SJohn Forte */ 2094291a2b48SSukumar Swaminathan typedef struct 2095291a2b48SSukumar Swaminathan { 2096291a2b48SSukumar Swaminathan uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Ids */ 2097291a2b48SSukumar Swaminathan NAME_TYPE HBA_PortName; /* Variable-length array */ 2098fcf3ce44SJohn Forte } GRHL_ACC_PAYLOAD, *PGRHL_ACC_PAYLOAD; 2099fcf3ce44SJohn Forte 2100fcf3ce44SJohn Forte /* 2101fcf3ce44SJohn Forte * Get Registered Port List (GRPL) Accept Payload Format 2102fcf3ce44SJohn Forte */ 2103291a2b48SSukumar Swaminathan typedef struct 2104291a2b48SSukumar Swaminathan { 2105291a2b48SSukumar Swaminathan uint32_t RPL_Entry_Cnt; /* No of Reg Port Entries */ 2106291a2b48SSukumar Swaminathan PORT_ENTRY eg_Port_Entry[1]; /* Variable-length array */ 2107fcf3ce44SJohn Forte } GRPL_ACC_PAYLOAD, *PGRPL_ACC_PAYLOAD; 2108fcf3ce44SJohn Forte 2109fcf3ce44SJohn Forte /* 2110fcf3ce44SJohn Forte * Get Port Attributes (GPAT) Accept Payload Format 2111fcf3ce44SJohn Forte */ 2112fcf3ce44SJohn Forte 2113291a2b48SSukumar Swaminathan typedef struct 2114291a2b48SSukumar Swaminathan { 2115291a2b48SSukumar Swaminathan ATTRIBUTE_BLOCK pab; 2116fcf3ce44SJohn Forte } GPAT_ACC_PAYLOAD, *PGPAT_ACC_PAYLOAD; 2117fcf3ce44SJohn Forte 2118fcf3ce44SJohn Forte /* 2119fcf3ce44SJohn Forte * Use for Firmware DownLoad 2120fcf3ce44SJohn Forte */ 2121fcf3ce44SJohn Forte 2122291a2b48SSukumar Swaminathan /* download.h */ 2123291a2b48SSukumar Swaminathan 2124291a2b48SSukumar Swaminathan #define REDUCED_SRAM_CFG 0x7FFFC /* 9802DC */ 2125291a2b48SSukumar Swaminathan #define FULL_SRAM_CFG 0x13FFFC /* 9802 */ 2126291a2b48SSukumar Swaminathan 2127291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_SHIFT(x) ((x << 20)) 2128291a2b48SSukumar Swaminathan #define SLI_FW_ADAPTER_TYPE_MASK 0x00f00000 2129291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_6000 SLI_FW_TYPE_SHIFT(0) 2130291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_7000 SLI_FW_TYPE_SHIFT(1) 2131291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_8000 SLI_FW_TYPE_SHIFT(2) 2132291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_850 SLI_FW_TYPE_SHIFT(3) 2133291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_9000 SLI_FW_TYPE_SHIFT(4) 2134291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_950 SLI_FW_TYPE_SHIFT(5) 2135291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_9802 SLI_FW_TYPE_SHIFT(6) /* [022702] */ 2136291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_982 SLI_FW_TYPE_SHIFT(7) 2137291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_10000 SLI_FW_TYPE_SHIFT(8) 2138291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_1050 SLI_FW_TYPE_SHIFT(9) 2139291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_X1000 SLI_FW_TYPE_SHIFT(0xa) 2140291a2b48SSukumar Swaminathan #define SLI_FW_TYPE_101 SLI_FW_TYPE_SHIFT(0xb) /* LP101 */ 2141291a2b48SSukumar Swaminathan 2142291a2b48SSukumar Swaminathan 2143291a2b48SSukumar Swaminathan enum emlxs_prog_type 2144291a2b48SSukumar Swaminathan { 2145fcf3ce44SJohn Forte TEST_PROGRAM, /* 0 */ 2146fcf3ce44SJohn Forte UTIL_PROGRAM, /* 1 */ 2147fcf3ce44SJohn Forte FUNC_FIRMWARE, /* 2 */ 2148fcf3ce44SJohn Forte BOOT_BIOS, /* 3 */ 2149fcf3ce44SJohn Forte CONFIG_DATA, /* 4 */ 2150fcf3ce44SJohn Forte SEQUENCER_CODE, /* 5 */ 2151fcf3ce44SJohn Forte SLI1_OVERLAY, /* 6 */ 2152fcf3ce44SJohn Forte SLI2_OVERLAY, /* 7 */ 215382527734SSukumar Swaminathan GASKET, /* 8 */ 2154fcf3ce44SJohn Forte HARDWARE_IMAGE, /* 9 */ 2155fcf3ce44SJohn Forte SBUS_FCODE, /* A */ 2156fcf3ce44SJohn Forte SLI3_OVERLAY, /* B */ 2157fcf3ce44SJohn Forte RESERVED_C, 2158fcf3ce44SJohn Forte RESERVED_D, 2159fcf3ce44SJohn Forte SLI4_OVERLAY, /* E */ 2160fcf3ce44SJohn Forte KERNEL_CODE, /* F */ 2161fcf3ce44SJohn Forte MAX_PROG_TYPES 2162fcf3ce44SJohn Forte } emlxs_prog_type_t; 2163fcf3ce44SJohn Forte 2164fcf3ce44SJohn Forte 2165291a2b48SSukumar Swaminathan typedef struct emlxs_fw_file 2166291a2b48SSukumar Swaminathan { 2167291a2b48SSukumar Swaminathan uint32_t version; 2168291a2b48SSukumar Swaminathan uint32_t revcomp; 2169291a2b48SSukumar Swaminathan char label[16]; 2170291a2b48SSukumar Swaminathan uint32_t offset; 2171fcf3ce44SJohn Forte } emlxs_fw_file_t; 2172fcf3ce44SJohn Forte 2173291a2b48SSukumar Swaminathan typedef struct emlxs_fw_image 2174291a2b48SSukumar Swaminathan { 2175fcf3ce44SJohn Forte emlxs_fw_file_t awc; 2176fcf3ce44SJohn Forte emlxs_fw_file_t bwc; 2177fcf3ce44SJohn Forte emlxs_fw_file_t dwc; 2178fcf3ce44SJohn Forte emlxs_fw_file_t prog[MAX_PROG_TYPES]; 2179fcf3ce44SJohn Forte } emlxs_fw_image_t; 2180fcf3ce44SJohn Forte 2181fcf3ce44SJohn Forte 2182fcf3ce44SJohn Forte 2183291a2b48SSukumar Swaminathan #define NOP_IMAGE_TYPE 0xe1a00000 2184fcf3ce44SJohn Forte 2185291a2b48SSukumar Swaminathan #define FLASH_BASE_ADR 0x01400000 2186291a2b48SSukumar Swaminathan #define DL_FROM_SLIM_OFFSET MBOX_EXTENSION_OFFSET 2187fcf3ce44SJohn Forte 2188fcf3ce44SJohn Forte #ifdef MBOX_EXT_SUPPORT 2189291a2b48SSukumar Swaminathan #define DL_SLIM_SEG_BYTE_COUNT MBOX_EXTENSION_SIZE 2190fcf3ce44SJohn Forte #else 2191291a2b48SSukumar Swaminathan #define DL_SLIM_SEG_BYTE_COUNT 128 2192291a2b48SSukumar Swaminathan #endif /* MBOX_EXT_SUPPORT */ 2193291a2b48SSukumar Swaminathan 2194291a2b48SSukumar Swaminathan #define SLI_CKSUM_LENGTH 4 2195291a2b48SSukumar Swaminathan #define SLI_CKSUM_SEED 0x55555555 2196291a2b48SSukumar Swaminathan #define SLI_CKSUM_ERR 0x1982abcd 2197291a2b48SSukumar Swaminathan 2198291a2b48SSukumar Swaminathan #define AIF_NOOP 0xe1a00000 2199291a2b48SSukumar Swaminathan #define AIF_BLAL 0xeb000000 2200291a2b48SSukumar Swaminathan #define OS_EXIT 0xef000011 2201291a2b48SSukumar Swaminathan #define OS_GETENV 0xef000010 2202291a2b48SSukumar Swaminathan #define AIF_IMAGEBASE 0x00008000 2203291a2b48SSukumar Swaminathan #define AIF_BLZINIT 0xeb00000c 2204291a2b48SSukumar Swaminathan #define DEBUG_TASK 0xef041d41 2205291a2b48SSukumar Swaminathan #define AIF_DBG_SRC 2 2206291a2b48SSukumar Swaminathan #define AIF_DBG_LL 1 2207291a2b48SSukumar Swaminathan #define AIF_DATABASAT 0x100 2208291a2b48SSukumar Swaminathan 2209291a2b48SSukumar Swaminathan #define JEDEC_ID_ADDRESS 0x0080001c 2210291a2b48SSukumar Swaminathan #define MAX_RBUS_SRAM_SIZE_ADR 0x788 2211291a2b48SSukumar Swaminathan #define MAX_IBUS_SRAM_SIZE_ADR 0x78c 2212291a2b48SSukumar Swaminathan #define FULL_RBUS_SRAM_CFG 0x7fffc 2213291a2b48SSukumar Swaminathan #define FULL_IBUS_SRAM_CFG 0x187fffc 2214291a2b48SSukumar Swaminathan #define REDUCED_RBUS_SRAM_CFG 0x5fffc 2215291a2b48SSukumar Swaminathan #define REDUCED_IBUS_SRAM_CFG 0x183fffc 2216291a2b48SSukumar Swaminathan 2217291a2b48SSukumar Swaminathan #define FULL_SRAM_CFG_PROG_ID 1 2218291a2b48SSukumar Swaminathan #define REDUCED_SRAM_CFG_PROG_ID 2 2219291a2b48SSukumar Swaminathan #define OTHER_SRAM_CFG_PROG_ID 3 2220291a2b48SSukumar Swaminathan 2221291a2b48SSukumar Swaminathan #define NO_FLASH_MEM_AVAIL 0xf1 2222291a2b48SSukumar Swaminathan 2223291a2b48SSukumar Swaminathan #define PROG_TYPE_MASK 0xff000000 2224291a2b48SSukumar Swaminathan #define PROG_TYPE_SHIFT 24 2225291a2b48SSukumar Swaminathan 2226291a2b48SSukumar Swaminathan #define FLASH_LOAD_LIST_ADR 0x79c 2227291a2b48SSukumar Swaminathan #define RAM_LOAD_ENTRY_SIZE 9 2228291a2b48SSukumar Swaminathan #define FLASH_LOAD_ENTRY_SIZE 6 2229291a2b48SSukumar Swaminathan #define RAM_LOAD_ENTRY_TYPE 0 2230291a2b48SSukumar Swaminathan #define FLASH_LOAD_ENTRY_TYPE 1 2231291a2b48SSukumar Swaminathan 2232291a2b48SSukumar Swaminathan #define CFG_DATA_NO_REGION -3 2233291a2b48SSukumar Swaminathan 2234291a2b48SSukumar Swaminathan #define SLI_IMAGE_START 0x20080 2235291a2b48SSukumar Swaminathan #define SLI_VERSION_LOC 0x270 2236fcf3ce44SJohn Forte 2237fcf3ce44SJohn Forte 2238291a2b48SSukumar Swaminathan #define SLI_HW_REVISION_CHECK(x, y) ((x & 0xf0) == y) 2239291a2b48SSukumar Swaminathan #define SLI_FCODE_REVISION_CHECK(x, y) (x == y) 2240fcf3ce44SJohn Forte 2241fcf3ce44SJohn Forte 22428f23e9faSHans Rosenfeld /* ************ OBJ firmware ************** */ 22438f23e9faSHans Rosenfeld #define OBJ_MAX_XFER_SIZE 32768 22448f23e9faSHans Rosenfeld 22458f23e9faSHans Rosenfeld 2246a9800bebSGarrett D'Amore /* ************ BladeEngine ************** */ 2247a9800bebSGarrett D'Amore #define BE_SIGNATURE "ServerEngines" 224882527734SSukumar Swaminathan #define BE_DIR_SIGNATURE "*** SE FLAS" 2249a9800bebSGarrett D'Amore #define BE_BUILD_SIZE 24 225082527734SSukumar Swaminathan #define BE_VERSION_SIZE 32 225182527734SSukumar Swaminathan #define BE_COOKIE_SIZE 32 225282527734SSukumar Swaminathan #define BE_CONTROLLER_SIZE 8 225382527734SSukumar Swaminathan #define BE_FLASH_ENTRIES 32 225482527734SSukumar Swaminathan #define BE_MAX_XFER_SIZE 32768 /* 4K aligned */ 225582527734SSukumar Swaminathan 2256a9800bebSGarrett D'Amore /* ************** BE3 **************** */ 2257a9800bebSGarrett D'Amore #define BE3_SIGNATURE_SIZE 52 2258a9800bebSGarrett D'Amore #define BE3_MAX_IMAGE_HEADERS 32 2259a9800bebSGarrett D'Amore 2260a9800bebSGarrett D'Amore typedef struct emlxs_be3_image_header 2261a9800bebSGarrett D'Amore { 2262a9800bebSGarrett D'Amore uint32_t id; 2263a9800bebSGarrett D'Amore #define UFI_BE3_FLASH_ID 0x01 2264a9800bebSGarrett D'Amore 2265a9800bebSGarrett D'Amore uint32_t offset; 2266a9800bebSGarrett D'Amore uint32_t length; 2267a9800bebSGarrett D'Amore uint32_t checksum; 2268a9800bebSGarrett D'Amore uint8_t version[BE_VERSION_SIZE]; 2269a9800bebSGarrett D'Amore 2270a9800bebSGarrett D'Amore } emlxs_be3_image_header_t; 2271a9800bebSGarrett D'Amore 2272a9800bebSGarrett D'Amore typedef struct emlxs_be3_ufi_header 2273a9800bebSGarrett D'Amore { 2274a9800bebSGarrett D'Amore char signature[BE3_SIGNATURE_SIZE]; 2275a9800bebSGarrett D'Amore uint32_t ufi_version; 2276a9800bebSGarrett D'Amore uint32_t file_length; 2277a9800bebSGarrett D'Amore uint32_t checksum; 2278a9800bebSGarrett D'Amore uint32_t antidote; 2279a9800bebSGarrett D'Amore uint32_t image_cnt; 2280a9800bebSGarrett D'Amore char build[BE_BUILD_SIZE]; 2281a9800bebSGarrett D'Amore uint8_t resv1[32]; 2282a9800bebSGarrett D'Amore 2283a9800bebSGarrett D'Amore } emlxs_be3_ufi_header_t; 2284a9800bebSGarrett D'Amore 2285a9800bebSGarrett D'Amore typedef struct emlxs_be3_ufi_controller 228682527734SSukumar Swaminathan { 228782527734SSukumar Swaminathan uint32_t vendor_id; 228882527734SSukumar Swaminathan uint32_t device_id; 228982527734SSukumar Swaminathan uint32_t sub_vendor_id; 229082527734SSukumar Swaminathan uint32_t sub_device_id; 229182527734SSukumar Swaminathan 2292a9800bebSGarrett D'Amore } emlxs_be3_ufi_controller_t; 229382527734SSukumar Swaminathan 2294a9800bebSGarrett D'Amore typedef struct emlxs_be3_flash_header 229582527734SSukumar Swaminathan { 2296a9800bebSGarrett D'Amore uint32_t format_rev; 229782527734SSukumar Swaminathan uint32_t checksum; 229882527734SSukumar Swaminathan uint32_t antidote; 2299a9800bebSGarrett D'Amore uint32_t entry_count; 2300a9800bebSGarrett D'Amore emlxs_be3_ufi_controller_t controller[BE_CONTROLLER_SIZE]; 2301a9800bebSGarrett D'Amore uint32_t resv0; 2302a9800bebSGarrett D'Amore uint32_t resv1; 2303a9800bebSGarrett D'Amore uint32_t resv2; 2304a9800bebSGarrett D'Amore uint32_t resv3; 2305a9800bebSGarrett D'Amore } emlxs_be3_flash_header_t; 2306a9800bebSGarrett D'Amore 2307a9800bebSGarrett D'Amore typedef struct emlxs_be3_flash_entry 2308a9800bebSGarrett D'Amore { 2309a9800bebSGarrett D'Amore uint32_t type; 2310a9800bebSGarrett D'Amore uint32_t offset; 2311a9800bebSGarrett D'Amore uint32_t block_size; 2312a9800bebSGarrett D'Amore uint32_t image_size; 2313a9800bebSGarrett D'Amore uint32_t checksum; 2314a9800bebSGarrett D'Amore uint32_t entry_point; 2315a9800bebSGarrett D'Amore uint32_t resv0; 2316a9800bebSGarrett D'Amore uint32_t resv1; 2317a9800bebSGarrett D'Amore char version[BE_VERSION_SIZE]; 2318a9800bebSGarrett D'Amore 2319a9800bebSGarrett D'Amore } emlxs_be3_flash_entry_t; 2320a9800bebSGarrett D'Amore 2321a9800bebSGarrett D'Amore typedef struct emlxs_be3_flash_dir 2322a9800bebSGarrett D'Amore { 2323a9800bebSGarrett D'Amore char cookie[BE_COOKIE_SIZE]; 2324a9800bebSGarrett D'Amore emlxs_be3_flash_header_t header; 2325a9800bebSGarrett D'Amore emlxs_be3_flash_entry_t entry[BE_FLASH_ENTRIES]; 2326a9800bebSGarrett D'Amore 2327a9800bebSGarrett D'Amore } emlxs_be3_flash_dir_t; 2328a9800bebSGarrett D'Amore 2329a9800bebSGarrett D'Amore typedef struct emlxs_be3_ncsi_header { 2330a9800bebSGarrett D'Amore uint32_t magic; 2331a9800bebSGarrett D'Amore uint8_t hdr_len; 2332a9800bebSGarrett D'Amore uint8_t type; 2333a9800bebSGarrett D'Amore uint16_t hdr_ver; 2334a9800bebSGarrett D'Amore uint16_t rsvd0; 2335a9800bebSGarrett D'Amore uint16_t load_offset; 2336a9800bebSGarrett D'Amore uint32_t len; 2337a9800bebSGarrett D'Amore uint32_t flash_offset; 2338a9800bebSGarrett D'Amore uint8_t ver[16]; 2339a9800bebSGarrett D'Amore uint8_t name[24]; 2340a9800bebSGarrett D'Amore uint32_t img_cksum; 2341a9800bebSGarrett D'Amore uint32_t rsvd1; 2342a9800bebSGarrett D'Amore uint32_t hdr_cksum; 2343a9800bebSGarrett D'Amore } emlxs_be3_ncsi_header_t; 2344a9800bebSGarrett D'Amore 2345a9800bebSGarrett D'Amore 2346a9800bebSGarrett D'Amore /* ************** BE2 **************** */ 2347a9800bebSGarrett D'Amore #define BE2_SIGNATURE_SIZE 32 2348a9800bebSGarrett D'Amore 2349a9800bebSGarrett D'Amore 2350a9800bebSGarrett D'Amore typedef struct emlxs_be2_ufi_controller 2351a9800bebSGarrett D'Amore { 2352a9800bebSGarrett D'Amore uint32_t vendor_id; 2353a9800bebSGarrett D'Amore uint32_t device_id; 2354a9800bebSGarrett D'Amore uint32_t sub_vendor_id; 2355a9800bebSGarrett D'Amore uint32_t sub_device_id; 2356a9800bebSGarrett D'Amore 2357a9800bebSGarrett D'Amore } emlxs_be2_ufi_controller_t; 2358a9800bebSGarrett D'Amore 2359a9800bebSGarrett D'Amore typedef struct emlxs_be2_ufi_header 2360a9800bebSGarrett D'Amore { 2361a9800bebSGarrett D'Amore char signature[BE2_SIGNATURE_SIZE]; 2362a9800bebSGarrett D'Amore uint32_t checksum; 2363a9800bebSGarrett D'Amore uint32_t antidote; 2364a9800bebSGarrett D'Amore emlxs_be2_ufi_controller_t controller; 236582527734SSukumar Swaminathan uint32_t file_length; 236682527734SSukumar Swaminathan uint32_t chunk_num; 236782527734SSukumar Swaminathan uint32_t chunk_cnt; 236882527734SSukumar Swaminathan uint32_t image_cnt; 236982527734SSukumar Swaminathan char build[BE_BUILD_SIZE]; 237082527734SSukumar Swaminathan 2371a9800bebSGarrett D'Amore } emlxs_be2_ufi_header_t; 237282527734SSukumar Swaminathan 2373a9800bebSGarrett D'Amore typedef struct emlxs_be2_flash_header /* 96 bytes */ 237482527734SSukumar Swaminathan { 237582527734SSukumar Swaminathan uint32_t format_rev; 237682527734SSukumar Swaminathan uint32_t checksum; 237782527734SSukumar Swaminathan uint32_t antidote; 237882527734SSukumar Swaminathan uint32_t build_num; 2379a9800bebSGarrett D'Amore emlxs_be2_ufi_controller_t controller[BE_CONTROLLER_SIZE]; 238082527734SSukumar Swaminathan uint32_t active_entry_mask; 238182527734SSukumar Swaminathan uint32_t valid_entry_mask; 238282527734SSukumar Swaminathan uint32_t orig_content_mask; 238382527734SSukumar Swaminathan uint32_t resv0; 238482527734SSukumar Swaminathan uint32_t resv1; 238582527734SSukumar Swaminathan uint32_t resv2; 238682527734SSukumar Swaminathan uint32_t resv3; 238782527734SSukumar Swaminathan uint32_t resv4; 238882527734SSukumar Swaminathan 2389a9800bebSGarrett D'Amore } emlxs_be2_flash_header_t; 239082527734SSukumar Swaminathan 2391a9800bebSGarrett D'Amore typedef struct emlxs_be2_flash_entry 239282527734SSukumar Swaminathan { 239382527734SSukumar Swaminathan uint32_t type; 239482527734SSukumar Swaminathan uint32_t offset; 239582527734SSukumar Swaminathan uint32_t pad_size; 239682527734SSukumar Swaminathan uint32_t image_size; 239782527734SSukumar Swaminathan uint32_t checksum; 239882527734SSukumar Swaminathan uint32_t entry_point; 239982527734SSukumar Swaminathan uint32_t resv0; 240082527734SSukumar Swaminathan uint32_t resv1; 240182527734SSukumar Swaminathan char version[BE_VERSION_SIZE]; 240282527734SSukumar Swaminathan 2403a9800bebSGarrett D'Amore } emlxs_be2_flash_entry_t; 240482527734SSukumar Swaminathan 2405a9800bebSGarrett D'Amore typedef struct emlxs_be2_flash_dir 240682527734SSukumar Swaminathan { 240782527734SSukumar Swaminathan char cookie[BE_COOKIE_SIZE]; 2408a9800bebSGarrett D'Amore emlxs_be2_flash_header_t header; 2409a9800bebSGarrett D'Amore emlxs_be2_flash_entry_t entry[BE_FLASH_ENTRIES]; 241082527734SSukumar Swaminathan 2411a9800bebSGarrett D'Amore } emlxs_be2_flash_dir_t; 241282527734SSukumar Swaminathan 241382527734SSukumar Swaminathan 241482527734SSukumar Swaminathan /* FLASH ENTRY TYPES */ 24158f23e9faSHans Rosenfeld #define BE_FLASHTYPE_NCSI_FIRMWARE 0x10 /* BE3 */ 24168f23e9faSHans Rosenfeld #define BE_FLASHTYPE_PXE_BIOS 0x20 24178f23e9faSHans Rosenfeld #define BE_FLASHTYPE_FCOE_BIOS 0x21 24188f23e9faSHans Rosenfeld #define BE_FLASHTYPE_ISCSI_BIOS 0x22 24198f23e9faSHans Rosenfeld #define BE_FLASHTYPE_FLASH_ISM 0x30 /* BE3 */ 24208f23e9faSHans Rosenfeld #define BE_FLASHTYPE_ISCSI_FIRMWARE 0xA0 24218f23e9faSHans Rosenfeld #define BE_FLASHTYPE_ISCSI_FIRMWARE_COMP 0xA1 24228f23e9faSHans Rosenfeld #define BE_FLASHTYPE_FCOE_FIRMWARE 0xA2 24238f23e9faSHans Rosenfeld #define BE_FLASHTYPE_FCOE_FIRMWARE_COMP 0xA3 24248f23e9faSHans Rosenfeld #define BE_FLASHTYPE_ISCSI_BACKUP 0xB0 24258f23e9faSHans Rosenfeld #define BE_FLASHTYPE_ISCSI_BACKUP_COMP 0xB1 24268f23e9faSHans Rosenfeld #define BE_FLASHTYPE_FCOE_BACKUP 0xB2 24278f23e9faSHans Rosenfeld #define BE_FLASHTYPE_FCOE_BACKUP_COMP 0xB3 24288f23e9faSHans Rosenfeld #define BE_FLASHTYPE_PHY_FIRMWARE 0xC0 /* 10Base-T */ 24298f23e9faSHans Rosenfeld #define BE_FLASHTYPE_REDBOOT 0xE0 243082527734SSukumar Swaminathan 243182527734SSukumar Swaminathan /* Flash types in download order */ 243282527734SSukumar Swaminathan typedef enum emlxs_be_flashtypes 243382527734SSukumar Swaminathan { 24348f23e9faSHans Rosenfeld PHY_FIRMWARE_FLASHTYPE, 2435a9800bebSGarrett D'Amore NCSI_FIRMWARE_FLASHTYPE, 243682527734SSukumar Swaminathan ISCSI_FIRMWARE_FLASHTYPE, 243782527734SSukumar Swaminathan ISCSI_BACKUP_FLASHTYPE, 243882527734SSukumar Swaminathan FCOE_FIRMWARE_FLASHTYPE, 243982527734SSukumar Swaminathan FCOE_BACKUP_FLASHTYPE, 244082527734SSukumar Swaminathan ISCSI_BIOS_FLASHTYPE, 244182527734SSukumar Swaminathan FCOE_BIOS_FLASHTYPE, 244282527734SSukumar Swaminathan PXE_BIOS_FLASHTYPE, 244382527734SSukumar Swaminathan REDBOOT_FLASHTYPE, 244482527734SSukumar Swaminathan BE_MAX_FLASHTYPES 244582527734SSukumar Swaminathan 244682527734SSukumar Swaminathan } emlxs_be_flashtypes_t; 244782527734SSukumar Swaminathan 244882527734SSukumar Swaminathan /* Driver level constructs */ 244982527734SSukumar Swaminathan typedef struct emlxs_be_fw_file 245082527734SSukumar Swaminathan { 2451a9800bebSGarrett D'Amore uint32_t be_version; 2452a9800bebSGarrett D'Amore uint32_t ufi_plus; 2453a9800bebSGarrett D'Amore 245482527734SSukumar Swaminathan uint32_t type; 245582527734SSukumar Swaminathan uint32_t image_offset; 245682527734SSukumar Swaminathan uint32_t image_size; 245782527734SSukumar Swaminathan uint32_t block_size; 245882527734SSukumar Swaminathan uint32_t block_crc; 2459a9800bebSGarrett D'Amore uint32_t load_address; /* BE3 */ 246082527734SSukumar Swaminathan char label[BE_VERSION_SIZE]; 246182527734SSukumar Swaminathan } emlxs_be_fw_file_t; 246282527734SSukumar Swaminathan 246382527734SSukumar Swaminathan typedef struct emlxs_be_fw_image 246482527734SSukumar Swaminathan { 2465a9800bebSGarrett D'Amore uint32_t be_version; 2466a9800bebSGarrett D'Amore uint32_t ufi_plus; 2467a9800bebSGarrett D'Amore 2468a9800bebSGarrett D'Amore uint32_t fcoe_version; 2469a9800bebSGarrett D'Amore char fcoe_label[BE_VERSION_SIZE]; 2470a9800bebSGarrett D'Amore 2471a9800bebSGarrett D'Amore uint32_t iscsi_version; 2472a9800bebSGarrett D'Amore char iscsi_label[BE_VERSION_SIZE]; 247382527734SSukumar Swaminathan 247482527734SSukumar Swaminathan emlxs_be_fw_file_t file[BE_MAX_FLASHTYPES]; 247582527734SSukumar Swaminathan } emlxs_be_fw_image_t; 247682527734SSukumar Swaminathan 24778f23e9faSHans Rosenfeld 24788f23e9faSHans Rosenfeld typedef struct emlxs_obj_header 24798f23e9faSHans Rosenfeld { 24808f23e9faSHans Rosenfeld uint32_t FileSize; 24818f23e9faSHans Rosenfeld 24828f23e9faSHans Rosenfeld #ifdef EMLXS_BIG_ENDIAN 24838f23e9faSHans Rosenfeld uint16_t MagicNumHi; 24848f23e9faSHans Rosenfeld uint16_t MagicNumLo; 24858f23e9faSHans Rosenfeld 24868f23e9faSHans Rosenfeld uint32_t FileType:8; 24878f23e9faSHans Rosenfeld uint32_t Id:8; 24888f23e9faSHans Rosenfeld uint32_t rsvd0:16; 24898f23e9faSHans Rosenfeld #endif 24908f23e9faSHans Rosenfeld 24918f23e9faSHans Rosenfeld #ifdef EMLXS_LITTLE_ENDIAN 24928f23e9faSHans Rosenfeld uint16_t MagicNumLo; 24938f23e9faSHans Rosenfeld uint16_t MagicNumHi; 24948f23e9faSHans Rosenfeld 24958f23e9faSHans Rosenfeld uint32_t rsvd0:16; 24968f23e9faSHans Rosenfeld uint32_t Id:8; 24978f23e9faSHans Rosenfeld uint32_t FileType:8; 24988f23e9faSHans Rosenfeld #endif 24998f23e9faSHans Rosenfeld 25008f23e9faSHans Rosenfeld #define OBJ_MAGIC_NUM_HI 0xFEAA 25018f23e9faSHans Rosenfeld #define OBJ_MAGIC_NUM_LO 0x0001 25028f23e9faSHans Rosenfeld 25038f23e9faSHans Rosenfeld #define OBJ_GRP_FILE_TYPE 0xF7 25048f23e9faSHans Rosenfeld 25058f23e9faSHans Rosenfeld #define OBJ_LANCER_ID 0xA2 25068f23e9faSHans Rosenfeld 25078f23e9faSHans Rosenfeld char RevName[128]; 25088f23e9faSHans Rosenfeld char Date[12]; 25098f23e9faSHans Rosenfeld char Revision[32]; 25108f23e9faSHans Rosenfeld } emlxs_obj_header_t; 25118f23e9faSHans Rosenfeld 25128f23e9faSHans Rosenfeld 2513fcf3ce44SJohn Forte #ifdef __cplusplus 2514fcf3ce44SJohn Forte } 2515fcf3ce44SJohn Forte #endif 2516fcf3ce44SJohn Forte 2517fcf3ce44SJohn Forte #endif /* _EMLXS_HW_H */ 2518