1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Emulex.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _EMLXS_FC_H
28 #define	_EMLXS_FC_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 typedef struct emlxs_buf
35 {
36 	fc_packet_t		*pkt;		/* scsi_pkt reference */
37 	struct emlxs_port	*port;		/* pointer to port */
38 	void			*bmp;		/* Save the buffer pointer */
39 						/* list for later use. */
40 	struct emlxs_buf	*fc_fwd;	/* Use it by chip_Q */
41 	struct emlxs_buf	*fc_bkwd;	/* Use it by chip_Q */
42 	struct emlxs_buf	*next;		/* Use it when the iodone */
43 	void 			*node;		/* Save node and used by */
44 						/* abort */
45 	void			*channel;	/* Save channel and used by */
46 						/* abort */
47 	struct emlxs_buf	*fpkt;		/* Flush pkt pointer */
48 	struct XRIobject	*xp;		/* Exchange resource */
49 	IOCBQ			iocbq;
50 	kmutex_t		mtx;
51 	uint32_t		pkt_flags;
52 	uint32_t		iotag;		/* iotag for this cmd */
53 	uint32_t		ticks;		/* save the timeout ticks */
54 						/* for the fc_packet_t */
55 	uint32_t		abort_attempts;
56 	uint32_t		lun;		/* Save LUN id and used by */
57 						/* abort */
58 	uint32_t		class;		/* Save class and used by */
59 						/* abort */
60 	uint32_t		ucmd;		/* Unsolicted command that */
61 						/* this packet is responding */
62 						/* to, if any */
63 	int32_t			flush_count;	/* Valid only in flush pkts */
64 	uint32_t		did;
65 
66 #ifdef SFCT_SUPPORT
67 	kmutex_t		fct_mtx;
68 	fc_packet_t		*fct_pkt;
69 	fct_cmd_t		*fct_cmd;
70 
71 	uint8_t			fct_type;
72 
73 #define	EMLXS_FCT_ELS_CMD		0x01	/* Unsolicted */
74 #define	EMLXS_FCT_ELS_REQ		0x02	/* Solicited */
75 #define	EMLXS_FCT_ELS_RSP		0x04
76 #define	EMLXS_FCT_CT_REQ		0x08	/* Solicited */
77 #define	EMLXS_FCT_FCP_CMD		0x10	/* Unsolicted */
78 #define	EMLXS_FCT_FCP_DATA		0x20
79 #define	EMLXS_FCT_FCP_STATUS		0x40
80 
81 
82 	uint8_t			fct_flags;
83 
84 #define	EMLXS_FCT_SEND_STATUS		0x01
85 #define	EMLXS_FCT_ABORT_INP		0x02
86 #define	EMLXS_FCT_IO_INP		0x04
87 #define	EMLXS_FCT_REGISTERED		0x10
88 #define	EMLXS_FCT_PLOGI_RECEIVED	0x20
89 #define	EMLXS_FCT_FLOGI			0x40
90 
91 	uint16_t		fct_state;
92 
93 #define	EMLXS_FCT_FCP_CMD_RECEIVED	1
94 #define	EMLXS_FCT_ELS_CMD_RECEIVED	2
95 #define	EMLXS_FCT_CMD_POSTED		3
96 #define	EMLXS_FCT_CMD_WAITQ		4
97 #define	EMLXS_FCT_SEND_CMD_RSP		5
98 #define	EMLXS_FCT_SEND_ELS_RSP		6
99 #define	EMLXS_FCT_SEND_ELS_REQ		7
100 #define	EMLXS_FCT_SEND_CT_REQ		8
101 #define	EMLXS_FCT_RSP_PENDING		9
102 #define	EMLXS_FCT_REQ_PENDING		10
103 #define	EMLXS_FCT_REG_PENDING		11
104 #define	EMLXS_FCT_REG_COMPLETE		12
105 #define	EMLXS_FCT_OWNED			13
106 #define	EMLXS_FCT_SEND_FCP_DATA		14
107 #define	EMLXS_FCT_SEND_FCP_STATUS	15
108 #define	EMLXS_FCT_DATA_PENDING		16
109 #define	EMLXS_FCT_STATUS_PENDING	17
110 #define	EMLXS_FCT_PKT_COMPLETE		18
111 #define	EMLXS_FCT_PKT_FCPRSP_COMPLETE	19
112 #define	EMLXS_FCT_PKT_ELSRSP_COMPLETE	20
113 #define	EMLXS_FCT_PKT_ELSCMD_COMPLETE	21
114 #define	EMLXS_FCT_PKT_CTCMD_COMPLETE	22
115 #define	EMLXS_FCT_REQ_COMPLETE		23
116 #define	EMLXS_FCT_CLOSE_PENDING		24
117 #define	EMLXS_FCT_ABORT_PENDING		25
118 #define	EMLXS_FCT_ABORT_DONE		26
119 #define	EMLXS_FCT_IO_DONE		27
120 
121 #define	EMLXS_FCT_IOCB_ISSUED		256 /* For tracing only */
122 #define	EMLXS_FCT_IOCB_COMPLETE		257 /* For tracing only */
123 
124 	stmf_data_buf_t		*fct_buf;
125 
126 #endif /* SFCT_SUPPORT */
127 
128 #ifdef SAN_DIAG_SUPPORT
129 	hrtime_t		sd_start_time;
130 #endif
131 } emlxs_buf_t;
132 
133 
134 
135 #ifdef FCT_IO_TRACE
136 #define	EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state)	\
137 	(_cmd_sbp)->fct_state = _state;			\
138 	emlxs_fct_io_trace((_cmd_sbp)->port, _fct_cmd, _state)
139 #else
140 /* define to set fct_state */
141 #define	EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state)	\
142 	(_cmd_sbp)->fct_state = _state
143 #endif /* FCT_IO_TRACE */
144 
145 
146 /* pkt_flags */
147 #define	PACKET_IN_COMPLETION	0x00000001
148 #define	PACKET_IN_TXQ		0x00000002
149 #define	PACKET_IN_CHIPQ		0x00000004
150 #define	PACKET_IN_DONEQ		0x00000008
151 
152 #define	PACKET_FCP_RESET	0x00000030
153 #define	PACKET_FCP_TGT_RESET	0x00000010
154 #define	PACKET_FCP_LUN_RESET	0x00000020
155 #define	PACKET_POLLED		0x00000040
156 
157 #ifdef EMLXS_I386
158 #define	PACKET_FCP_SWAPPED	0x00000100
159 #define	PACKET_ELS_SWAPPED	0x00000200
160 #define	PACKET_CT_SWAPPED	0x00000400
161 #define	PACKET_CSP_SWAPPED	0x00000800
162 #endif	/* EMLXS_I386 */
163 
164 #define	PACKET_STALE		0x00001000
165 
166 #define	PACKET_IN_TIMEOUT	0x00010000
167 #define	PACKET_IN_FLUSH		0x00020000
168 #define	PACKET_IN_ABORT		0x00040000
169 #define	PACKET_XRI_CLOSED	0x00080000	/* An XRI abort or */
170 						/* XRI close was issued */
171 
172 #define	PACKET_CHIP_COMP	0x00100000
173 #define	PACKET_COMPLETED	0x00200000
174 #define	PACKET_ULP_OWNED	0x00400000
175 
176 #define	PACKET_STATE_VALID	0x01000000
177 #define	PACKET_FCP_RSP_VALID	0x02000000
178 #define	PACKET_ELS_RSP_VALID	0x04000000
179 #define	PACKET_CT_RSP_VALID	0x08000000
180 
181 #define	PACKET_DELAY_REQUIRED	0x10000000
182 #define	PACKET_ALLOCATED	0x40000000
183 #define	PACKET_VALID		0x80000000
184 
185 
186 #define	STALE_PACKET		((emlxs_buf_t *)0xFFFFFFFF)
187 
188 
189 /*
190  * From fc_error.h pkt_reason (except for state = NPORT_RJT, FABRIC_RJT,
191  * NPORT_BSY, FABRIC_BSY, LS_RJT, BA_RJT, FS_RJT)
192  *
193  * FCA unique error codes can begin after FC_REASON_FCA_UNIQUE.
194  * Each FCA defines its own set with values greater >= 0x7F
195  */
196 #define	FC_REASON_FCA_DEFINED   0x100
197 
198 
199 /*
200  * Device VPD save area
201  */
202 
203 typedef struct emlxs_vpd
204 {
205 	uint32_t	biuRev;
206 	uint32_t	smRev;
207 	uint32_t	smFwRev;
208 	uint32_t	endecRev;
209 	uint16_t	rBit;
210 	uint8_t		fcphHigh;
211 	uint8_t		fcphLow;
212 	uint8_t		feaLevelHigh;
213 	uint8_t		feaLevelLow;
214 
215 	uint32_t	postKernRev;
216 	char		postKernName[32];
217 
218 	uint32_t	opFwRev;
219 	char		opFwName[32];
220 	char		opFwLabel[32];
221 
222 	uint32_t	sli1FwRev;
223 	char		sli1FwName[32];
224 	char		sli1FwLabel[32];
225 
226 	uint32_t	sli2FwRev;
227 	char		sli2FwName[32];
228 	char		sli2FwLabel[32];
229 
230 	uint32_t	sli3FwRev;
231 	char		sli3FwName[32];
232 	char		sli3FwLabel[32];
233 
234 	uint32_t	sli4FwRev;
235 	char		sli4FwName[32];
236 	char		sli4FwLabel[32];
237 
238 	char		fw_version[32];
239 	char		fw_label[32];
240 
241 	char		fcode_version[32];
242 	char		boot_version[32];
243 
244 	char		serial_num[32];
245 	char		part_num[32];
246 	char		port_num[20];
247 	char		eng_change[32];
248 	char		manufacturer[80];
249 	char		model[80];
250 	char		model_desc[256];
251 	char		prog_types[256];
252 	char		id[80];
253 
254 	uint32_t	port_index;
255 	uint8_t		link_speed;
256 } emlxs_vpd_t;
257 
258 
259 typedef struct emlxs_queue
260 {
261 	uint8_t		*q_first;	/* queue first element */
262 	uint8_t		*q_last;	/* queue last element */
263 	uint16_t	q_cnt;	/* current length of queue */
264 	uint16_t	q_max;	/* max length queue can get */
265 } emlxs_queue_t;
266 typedef emlxs_queue_t Q;
267 
268 
269 
270 /*
271  * This structure is used when allocating a buffer pool.
272  * Note: this should be identical to gasket buf_info (fldl.h).
273  */
274 typedef struct emlxs_buf_info
275 {
276 	int32_t		size;	/* Specifies the number of bytes to allocate. */
277 	int32_t		align;	/* The desired address boundary. */
278 
279 	int32_t		flags;
280 
281 #define	FC_MBUF_DMA		0x01	/* blocks are for DMA */
282 #define	FC_MBUF_PHYSONLY	0x02	/* For malloc - map a given virtual */
283 					/* address to physical address (skip */
284 					/* the malloc). */
285 					/* For free - just unmap the given */
286 					/* physical address (skip the free). */
287 #define	FC_MBUF_IOCTL		0x04	/* called from dfc_ioctl */
288 #define	FC_MBUF_UNLOCK		0x08	/* called with driver unlocked */
289 #define	FC_MBUF_SNGLSG		0x10	/* allocate a single contiguous */
290 					/* physical memory */
291 #define	FC_MBUF_DMA32		0x20
292 
293 	uint64_t	phys;		/* specifies physical buffer pointer */
294 	void		*virt;		/* specifies virtual buffer pointer */
295 	void		*data_handle;
296 	void		*dma_handle;
297 } emlxs_buf_info_t;
298 typedef emlxs_buf_info_t MBUF_INFO;
299 
300 
301 #define	EMLXS_MAX_HBQ   	16	/* Max HBQs handled by firmware */
302 #define	EMLXS_ELS_HBQ_ID	0
303 #define	EMLXS_IP_HBQ_ID		1
304 #define	EMLXS_CT_HBQ_ID		2
305 #define	EMLXS_FCT_HBQ_ID	3
306 
307 #ifdef SFCT_SUPPORT
308 #define	EMLXS_NUM_HBQ		4	/* Number of HBQs supported by driver */
309 #else
310 #define	EMLXS_NUM_HBQ		3	/* Number of HBQs supported by driver */
311 #endif /* SFCT_SUPPORT */
312 
313 
314 /*
315  * An IO Channel is a object that comprises a xmit/cmpl
316  * path for IOs.
317  * For SLI3, an IO path maps to a ring (cmd/rsp)
318  * For SLI4, an IO path map to a queue pair (WQ/CQ)
319  */
320 typedef struct emlxs_channel
321 {
322 	struct emlxs_hba *hba;			/* ptr to hba for channel */
323 	void		*iopath;		/* ptr to SLI3/4 io path */
324 
325 	kmutex_t	rsp_lock;
326 	IOCBQ		*rsp_head;	/* deferred completion head */
327 	IOCBQ		*rsp_tail;	/* deferred completion tail */
328 	emlxs_thread_t  intr_thread;
329 
330 
331 	uint16_t	channelno;
332 	uint16_t	chan_flag;
333 
334 #define	EMLXS_NEEDS_TRIGGER 1
335 
336 	/* Protected by EMLXS_TX_CHANNEL_LOCK */
337 	emlxs_queue_t	nodeq;			/* Node service queue */
338 
339 	kmutex_t	channel_cmd_lock;
340 	uint32_t	timeout;
341 
342 	/* Channel command counters */
343 	uint32_t	ulpSendCmd;
344 	uint32_t	ulpCmplCmd;
345 	uint32_t	hbaSendCmd;
346 	uint32_t	hbaCmplCmd;
347 	uint32_t	hbaSendCmd_sbp;
348 	uint32_t	hbaCmplCmd_sbp;
349 
350 } emlxs_channel_t;
351 typedef emlxs_channel_t CHANNEL;
352 
353 /*
354  * Should be able to handle max number of io paths for a
355  * SLI4 HBA (EMLXS_MAX_WQS) or for a SLI3 HBA (MAX_RINGS)
356  */
357 #define	MAX_CHANNEL EMLXS_MSI_MAX_INTRS
358 
359 
360 /* Structure used to access adapter rings */
361 typedef struct emlxs_ring
362 {
363 	void		*fc_cmdringaddr;	/* virtual offset for cmd */
364 						/* rings */
365 	void		*fc_rspringaddr;	/* virtual offset for rsp */
366 						/* rings */
367 
368 	uint8_t		*fc_mpon;		/* index ptr for match */
369 						/* structure */
370 	uint8_t		*fc_mpoff;		/* index ptr for match */
371 						/* structure */
372 	struct emlxs_hba *hba;			/* ptr to hba for ring */
373 
374 	uint8_t		fc_numCiocb;		/* number of command iocb's */
375 						/* per ring */
376 	uint8_t		fc_numRiocb;		/* number of response iocb's */
377 						/* per ring */
378 	uint8_t		fc_rspidx;		/* current index in response */
379 						/* ring */
380 	uint8_t		fc_cmdidx;		/* current index in command */
381 						/* ring */
382 	uint8_t		fc_port_rspidx;
383 	uint8_t		fc_port_cmdidx;
384 	uint8_t		ringno;
385 
386 	uint16_t	fc_missbufcnt;		/* buf cnt we need to repost */
387 	CHANNEL		*channelp;
388 
389 
390 } emlxs_ring_t;
391 typedef emlxs_ring_t RING;
392 
393 
394 #ifdef SAN_DIAG_SUPPORT
395 /*
396  * Although right now it's just 1 field, SAN Diag anticipates that this
397  * structure will grow in the future.
398  */
399 typedef struct sd_timestat_level0 {
400 	int		count;
401 } sd_timestat_level0_t;
402 #endif
403 
404 typedef struct emlxs_node
405 {
406 	struct emlxs_node	*nlp_list_next;
407 	struct emlxs_node	*nlp_list_prev;
408 
409 	NAME_TYPE		nlp_portname;	/* port name */
410 	NAME_TYPE		nlp_nodename;	/* node name */
411 
412 	uint32_t		nlp_DID;	/* fibre channel D_ID */
413 	uint32_t		nlp_oldDID;
414 
415 	uint16_t		nlp_Rpi;	/* login id returned by */
416 						/* REG_LOGIN */
417 	uint16_t		nlp_Xri;	/* login id returned by */
418 						/* REG_LOGIN */
419 
420 	uint8_t			nlp_fcp_info;	/* Remote class info */
421 
422 	/* nlp_fcp_info */
423 #define	NLP_FCP_TGT_DEVICE	0x10	/* FCP TGT device */
424 #define	NLP_FCP_INI_DEVICE	0x20	/* FCP Initiator device */
425 #define	NLP_FCP_2_DEVICE	0x40	/* FCP-2 TGT device */
426 #define	NLP_EMLX_VPORT		0x80    /* Virtual port */
427 
428 	uint32_t		nlp_force_rscn;
429 	uint32_t		nlp_tag;	/* Tag used by port_offline */
430 	uint32_t		flag;
431 
432 #define	NODE_POOL_ALLOCATED 	0x00000001
433 
434 	SERV_PARM		sparm;
435 
436 	/* Protected by EMLXS_TX_CHANNEL_LOCK */
437 	uint32_t		nlp_active;	/* Node active flag */
438 	uint32_t		nlp_base;
439 	uint32_t		nlp_flag[MAX_CHANNEL];	/* Node level channel */
440 							/* flags */
441 
442 	/* nlp_flag */
443 #define	NLP_CLOSED		0x1
444 #define	NLP_OFFLINE		0x2
445 #define	NLP_RPI_XRI		0x4
446 
447 	uint32_t		nlp_tics[MAX_CHANNEL];	/* gate timeout */
448 	emlxs_queue_t		nlp_tx[MAX_CHANNEL];	/* Transmit Q head */
449 	emlxs_queue_t		nlp_ptx[MAX_CHANNEL];	/* Priority transmit */
450 							/* Queue head */
451 	void			*nlp_next[MAX_CHANNEL];	/* Service Request */
452 							/* Queue pointer used */
453 							/* when node needs */
454 							/* servicing */
455 #ifdef DHCHAP_SUPPORT
456 	emlxs_node_dhc_t	node_dhc;
457 #endif	/* DHCHAP_SUPPORT */
458 
459 #ifdef SAN_DIAG_SUPPORT
460 	sd_timestat_level0_t	sd_dev_bucket[SD_IO_LATENCY_MAX_BUCKETS];
461 #endif
462 
463 	struct RPIobject	*RPIp;	/* SLI4 only */
464 #define	EMLXS_NODE_TO_RPI(_h, _n)	\
465 	((_n)?((_n->RPIp)?_n->RPIp:emlxs_sli4_find_rpi(_h, _n->nlp_Rpi)):NULL)
466 
467 } emlxs_node_t;
468 typedef emlxs_node_t NODELIST;
469 
470 
471 
472 #define	NADDR_LEN	6	/* MAC network address length */
473 typedef struct emlxs_fcip_nethdr
474 {
475 	NAME_TYPE	fc_destname;	/* destination port name */
476 	NAME_TYPE	fc_srcname;	/* source port name */
477 } emlxs_fcip_nethdr_t;
478 typedef emlxs_fcip_nethdr_t NETHDR;
479 
480 
481 #define	MEM_NLP		0	/* memory segment to hold node list entries */
482 #define	MEM_IOCB	1	/* memory segment to hold iocb commands */
483 #define	MEM_MBOX	2	/* memory segment to hold mailbox cmds  */
484 #define	MEM_BPL		3	/* and to hold buffer ptr lists - SLI2   */
485 #define	MEM_BUF		4	/* memory segment to hold buffer data   */
486 #define	MEM_ELSBUF	4	/* memory segment to hold buffer data   */
487 #define	MEM_IPBUF	5	/* memory segment to hold IP buffer data */
488 #define	MEM_CTBUF	6	/* memory segment to hold CT buffer data */
489 #define	MEM_FCTBUF	7	/* memory segment to hold FCT buffer data */
490 
491 #ifdef SFCT_SUPPORT
492 #define	FC_MAX_SEG	8
493 #else
494 #define	FC_MAX_SEG	7
495 #endif /* SFCT_SUPPORT */
496 
497 
498 /* A BPL entry is 12 bytes. Subtract 2 for command and response buffers */
499 #define	BPL_TO_SGLLEN(_bpl)   ((_bpl/12)-2)
500 #define	MEM_BPL_SIZE		1024  /* Default size */
501 
502 /* A SGL entry is 16 bytes. Subtract 2 for command and response buffers */
503 #define	SGL_TO_SGLLEN(_sgl)   ((_sgl/16)-2)
504 #define	MEM_SGL_SIZE		1024  /* Default size */
505 
506 #ifdef EMLXS_I386
507 #define	EMLXS_SGLLEN		BPL_TO_SGLLEN(MEM_BPL_SIZE)
508 #else	/* EMLXS_SPARC */
509 #define	EMLXS_SGLLEN		1
510 #endif	/* EMLXS_I386 */
511 
512 #define	MEM_BUF_SIZE		1024
513 #define	MEM_BUF_COUNT		64
514 
515 #define	MEM_ELSBUF_SIZE   	MEM_BUF_SIZE
516 #define	MEM_ELSBUF_COUNT  	hba->max_nodes
517 #define	MEM_IPBUF_SIZE  	65535
518 #define	MEM_IPBUF_COUNT		60
519 #define	MEM_CTBUF_SIZE		MAX_CT_PAYLOAD	/* (1024*320) */
520 #define	MEM_CTBUF_COUNT		8
521 #define	MEM_FCTBUF_SIZE  	65535
522 #define	MEM_FCTBUF_COUNT	128
523 
524 typedef struct emlxs_memseg
525 {
526 	uint8_t			*fc_memget_ptr;
527 	uint8_t			*fc_memget_end;
528 	uint8_t			*fc_memput_ptr;
529 	uint8_t			*fc_memput_end;
530 
531 	uint8_t			*fc_memstart_virt;	/* beginning address */
532 							/* of memory block */
533 	uint64_t		fc_memstart_phys;	/* beginning address */
534 							/* of memory block */
535 	ddi_dma_handle_t	fc_mem_dma_handle;
536 	ddi_acc_handle_t	fc_mem_dat_handle;
537 	uint32_t		fc_total_memsize;
538 	uint32_t		fc_memsize;		/* size of mem blks */
539 	uint32_t		fc_numblks;		/* no of mem blks */
540 	uint32_t		fc_memget_cnt;		/* no of mem get blks */
541 	uint32_t		fc_memput_cnt;		/* no of mem put blks */
542 	uint32_t		fc_memflag;  /* emlxs_buf_info_t FLAGS */
543 	uint32_t		fc_reserved; /* used with priority flag */
544 	uint32_t		fc_memalign;
545 	uint32_t		fc_memtag;
546 	char			fc_label[32];
547 
548 } emlxs_memseg_t;
549 typedef emlxs_memseg_t MEMSEG;
550 
551 
552 /* Board stat counters */
553 typedef struct emlxs_stats
554 {
555 	uint32_t	LinkUp;
556 	uint32_t	LinkDown;
557 	uint32_t	LinkEvent;
558 	uint32_t	LinkMultiEvent;
559 
560 	uint32_t	MboxIssued;
561 	uint32_t	MboxCompleted;	/* MboxError + MbxGood */
562 	uint32_t	MboxGood;
563 	uint32_t	MboxError;
564 	uint32_t	MboxBusy;
565 	uint32_t	MboxInvalid;
566 
567 	uint32_t	IocbIssued[MAX_CHANNEL];
568 	uint32_t	IocbReceived[MAX_CHANNEL];
569 	uint32_t	IocbTxPut[MAX_CHANNEL];
570 	uint32_t	IocbTxGet[MAX_CHANNEL];
571 	uint32_t	IocbRingFull[MAX_CHANNEL];
572 	uint32_t	IocbThrottled;
573 
574 	uint32_t	IntrEvent[8];
575 
576 	uint32_t	FcpIssued;
577 	uint32_t	FcpCompleted;	/* FcpGood + FcpError */
578 	uint32_t	FcpGood;
579 	uint32_t	FcpError;
580 
581 	uint32_t	FcpEvent;	/* FcpStray + FcpCompleted */
582 	uint32_t	FcpStray;
583 #ifdef SFCT_SUPPORT
584 	uint32_t	FctRingEvent;
585 	uint32_t	FctRingError;
586 	uint32_t	FctRingDropped;
587 #endif /* SFCT_SUPPORT */
588 
589 	uint32_t	ElsEvent;	/* ElsStray + ElsCmplt (cmd + rsp) */
590 	uint32_t	ElsStray;
591 
592 	uint32_t	ElsCmdIssued;
593 	uint32_t	ElsCmdCompleted;	/* ElsCmdGood + ElsCmdError */
594 	uint32_t	ElsCmdGood;
595 	uint32_t	ElsCmdError;
596 
597 	uint32_t	ElsRspIssued;
598 	uint32_t	ElsRspCompleted;
599 
600 	uint32_t	ElsRcvEvent;	/* ElsRcvErr + ElsRcvDrop + ElsCmdRcv */
601 	uint32_t	ElsRcvError;
602 	uint32_t	ElsRcvDropped;
603 	uint32_t	ElsCmdReceived;	/* ElsRscnRcv + ElsPlogiRcv + ... */
604 	uint32_t	ElsRscnReceived;
605 	uint32_t	ElsFlogiReceived;
606 	uint32_t	ElsPlogiReceived;
607 	uint32_t	ElsPrliReceived;
608 	uint32_t	ElsPrloReceived;
609 	uint32_t	ElsLogoReceived;
610 	uint32_t	ElsAdiscReceived;
611 	uint32_t	ElsAuthReceived;
612 	uint32_t	ElsGenReceived;
613 
614 	uint32_t	CtEvent;	/* CtStray + CtCompleted (cmd + rsp) */
615 	uint32_t	CtStray;
616 
617 	uint32_t	CtCmdIssued;
618 	uint32_t	CtCmdCompleted;	/* CtCmdGood + CtCmdError */
619 	uint32_t	CtCmdGood;
620 	uint32_t	CtCmdError;
621 
622 	uint32_t	CtRspIssued;
623 	uint32_t	CtRspCompleted;
624 
625 	uint32_t	CtRcvEvent;	/* CtRcvError + CtRcvDrop + CtCmdRcvd */
626 	uint32_t	CtRcvError;
627 	uint32_t	CtRcvDropped;
628 	uint32_t	CtCmdReceived;
629 
630 	uint32_t	IpEvent;	/* IpStray + IpSeqCmpl + IpBcastCmpl */
631 	uint32_t	IpStray;
632 
633 	uint32_t	IpSeqIssued;
634 	uint32_t	IpSeqCompleted;	/* IpSeqGood + IpSeqError */
635 	uint32_t	IpSeqGood;
636 	uint32_t	IpSeqError;
637 
638 	uint32_t	IpBcastIssued;
639 	uint32_t	IpBcastCompleted;	/* IpBcastGood + IpBcastError */
640 	uint32_t	IpBcastGood;
641 	uint32_t	IpBcastError;
642 
643 	uint32_t	IpRcvEvent;	/* IpDrop + IpSeqRcv + IpBcastRcv */
644 	uint32_t	IpDropped;
645 	uint32_t	IpSeqReceived;
646 	uint32_t	IpBcastReceived;
647 
648 	uint32_t	IpUbPosted;
649 	uint32_t	ElsUbPosted;
650 	uint32_t	CtUbPosted;
651 #ifdef SFCT_SUPPORT
652 	uint32_t	FctUbPosted;
653 #endif /* SFCT_SUPPORT */
654 
655 	uint32_t	ResetTime;	/* Time of last reset */
656 } emlxs_stats_t;
657 
658 
659 #define	FC_MAX_ADPTMSG   (8*28)	/* max size of a msg from adapter */
660 
661 #define	EMLXS_NUM_THREADS	8
662 #define	EMLXS_MIN_TASKS		8
663 #define	EMLXS_MAX_TASKS		8
664 
665 #define	EMLXS_NUM_HASH_QUES	32
666 #define	EMLXS_DID_HASH(x)	((x) & (EMLXS_NUM_HASH_QUES - 1))
667 
668 
669 /* pkt_tran_flag */
670 #define	FC_TRAN_COMPLETED	0x8000
671 
672 
673 typedef struct emlxs_dfc_event
674 {
675 	uint32_t	pid;
676 	uint32_t	event;
677 	uint32_t	last_id;
678 
679 	void		*dataout;
680 	uint32_t	size;
681 	uint32_t	mode;
682 } emlxs_dfc_event_t;
683 
684 
685 typedef struct emlxs_hba_event
686 {
687 	uint32_t	last_id;
688 	uint32_t	new;
689 	uint32_t	missed;
690 } emlxs_hba_event_t;
691 
692 
693 #ifdef SFCT_SUPPORT
694 
695 #define	TGTPORTSTAT			port->fct_stat
696 
697 /*
698  * FctP2IOXcnt will count IOs by their fcpDL. Counters
699  * are for buckets of various power of 2 sizes.
700  * Bucket 0  <  512  > 0
701  * Bucket 1  >= 512  < 1024
702  * Bucket 2  >= 1024 < 2048
703  * Bucket 3  >= 2048 < 4096
704  * Bucket 4  >= 4096 < 8192
705  * Bucket 5  >= 8192 < 16K
706  * Bucket 6  >= 16K  < 32K
707  * Bucket 7  >= 32K  < 64K
708  * Bucket 8  >= 64K  < 128K
709  * Bucket 9  >= 128K < 256K
710  * Bucket 10 >= 256K < 512K
711  * Bucket 11 >= 512K < 1MB
712  * Bucket 12 >= 1MB  < 2MB
713  * Bucket 13 >= 2MB  < 4MB
714  * Bucket 14 >= 4MB  < 8MB
715  * Bucket 15 >= 8MB
716  */
717 #define	MAX_TGTPORT_IOCNT  16
718 
719 
720 /*
721  * These routines will bump the right counter, based on
722  * the size of the IO inputed, with the least number of
723  * comparisions.  A max of 5 comparisions is only needed
724  * to classify the IO in one of 16 ranges. A binary search
725  * to locate the high bit in the size is used.
726  */
727 #define	EMLXS_BUMP_RDIOCTR(port, cnt) \
728 { \
729 	/* Use binary search to find the first high bit */ \
730 	if (cnt & 0xffff0000) { \
731 		if (cnt & 0xff800000) { \
732 			TGTPORTSTAT.FctP2IORcnt[15]++; \
733 		} \
734 		else { \
735 			/* It must be 0x007f0000 */ \
736 			if (cnt & 0x00700000) { \
737 				if (cnt & 0x00400000) { \
738 					TGTPORTSTAT.FctP2IORcnt[14]++; \
739 				} \
740 				else { \
741 					/* it must be 0x00300000 */ \
742 					if (cnt & 0x00200000) { \
743 						TGTPORTSTAT.FctP2IORcnt[13]++; \
744 					} \
745 					else { \
746 						/* It must be 0x00100000 */ \
747 						TGTPORTSTAT.FctP2IORcnt[12]++; \
748 					} \
749 				} \
750 			} \
751 			else { \
752 				/* It must be 0x000f0000 */ \
753 				if (cnt & 0x000c0000) {	\
754 					if (cnt & 0x00080000) {	\
755 						TGTPORTSTAT.FctP2IORcnt[11]++; \
756 					} \
757 					else { \
758 						/* It must be 0x00040000 */ \
759 						TGTPORTSTAT.FctP2IORcnt[10]++; \
760 					} \
761 				} \
762 				else { \
763 					/* It must be 0x00030000 */ \
764 					if (cnt & 0x00020000) {	\
765 						TGTPORTSTAT.FctP2IORcnt[9]++; \
766 					} \
767 					else { \
768 						/* It must be 0x00010000 */ \
769 						TGTPORTSTAT.FctP2IORcnt[8]++; \
770 					} \
771 				} \
772 			} \
773 		} \
774 	} \
775 	else { \
776 		if (cnt & 0x0000fe00) { \
777 			if (cnt & 0x0000f000) { \
778 				if (cnt & 0x0000c000) { \
779 					if (cnt & 0x00008000) { \
780 						TGTPORTSTAT.FctP2IORcnt[7]++; \
781 					} \
782 					else { \
783 						/* It must be 0x00004000 */ \
784 						TGTPORTSTAT.FctP2IORcnt[6]++; \
785 					} \
786 				} \
787 				else { \
788 					/* It must be 0x00000300 */ \
789 					if (cnt & 0x00000200) { \
790 						TGTPORTSTAT.FctP2IORcnt[5]++; \
791 					} \
792 					else { \
793 						/* It must be 0x00000100 */ \
794 						TGTPORTSTAT.FctP2IORcnt[4]++; \
795 					} \
796 				} \
797 			} \
798 			else { \
799 				/* It must be 0x00000e00 */ \
800 				if (cnt & 0x00000800) { \
801 					TGTPORTSTAT.FctP2IORcnt[3]++; \
802 				} \
803 				else { \
804 					/* It must be 0x00000600 */ \
805 					if (cnt & 0x00000400) { \
806 						TGTPORTSTAT.FctP2IORcnt[2]++; \
807 					} \
808 					else { \
809 						/* It must be 0x00000200 */ \
810 						TGTPORTSTAT.FctP2IORcnt[1]++; \
811 					} \
812 				} \
813 			} \
814 		} \
815 		else { \
816 			/* It must be 0x000001ff */ \
817 			TGTPORTSTAT.FctP2IORcnt[0]++; \
818 		} \
819 	} \
820 }
821 
822 
823 #define	EMLXS_BUMP_WRIOCTR(port, cnt) \
824 { \
825 /* Use binary search to find the first high bit */ \
826 	if (cnt & 0xffff0000) { \
827 		if (cnt & 0xff800000) { \
828 			TGTPORTSTAT.FctP2IOWcnt[15]++; \
829 		} \
830 		else { \
831 			/* It must be 0x007f0000 */ \
832 			if (cnt & 0x00700000) { \
833 				if (cnt & 0x00400000) { \
834 					TGTPORTSTAT.FctP2IOWcnt[14]++; \
835 				} \
836 				else { \
837 					/* It must be 0x00300000 */ \
838 					if (cnt & 0x00200000) { \
839 						TGTPORTSTAT.FctP2IOWcnt[13]++; \
840 					} \
841 					else { \
842 						/* It must be 0x00100000 */ \
843 						TGTPORTSTAT.FctP2IOWcnt[12]++; \
844 					} \
845 				} \
846 			} \
847 			else { \
848 				/* It must be 0x000f0000 */ \
849 				if (cnt & 0x000c0000) { \
850 					if (cnt & 0x00080000) { \
851 						TGTPORTSTAT.FctP2IOWcnt[11]++; \
852 					} \
853 					else { \
854 						/* it must be 0x00040000 */ \
855 						TGTPORTSTAT.FctP2IOWcnt[10]++; \
856 					} \
857 				} \
858 				else { \
859 					/* It must be 0x00030000 */ \
860 					if (cnt & 0x00020000) { \
861 						TGTPORTSTAT.FctP2IOWcnt[9]++; \
862 					} \
863 					else { \
864 						/* It must be 0x00010000 */ \
865 						TGTPORTSTAT.FctP2IOWcnt[8]++; \
866 					} \
867 				} \
868 			} \
869 		} \
870 	} \
871 	else { \
872 		if (cnt & 0x0000fe00) { \
873 			if (cnt & 0x0000f000) { \
874 				if (cnt & 0x0000c000) { \
875 					if (cnt & 0x00008000) { \
876 						TGTPORTSTAT.FctP2IOWcnt[7]++; \
877 					} \
878 					else { \
879 						/* It must be 0x00004000 */ \
880 						TGTPORTSTAT.FctP2IOWcnt[6]++; \
881 					} \
882 				} \
883 				else { \
884 					/* It must be 0x00000300 */ \
885 					if (cnt & 0x00000200) { \
886 						TGTPORTSTAT.FctP2IOWcnt[5]++; \
887 					} \
888 					else { \
889 						/* It must be 0x00000100 */ \
890 						TGTPORTSTAT.FctP2IOWcnt[4]++; \
891 					} \
892 				} \
893 			} \
894 			else { \
895 				/* It must be 0x00000e00 */ \
896 				if (cnt & 0x00000800) { \
897 					TGTPORTSTAT.FctP2IOWcnt[3]++; \
898 				} \
899 				else { \
900 					/* It must be 0x00000600 */ \
901 					if (cnt & 0x00000400) { \
902 						TGTPORTSTAT.FctP2IOWcnt[2]++; \
903 					} \
904 					else { \
905 						/* It must be 0x00000200 */ \
906 						TGTPORTSTAT.FctP2IOWcnt[1]++; \
907 					} \
908 				} \
909 			} \
910 		} \
911 		else { \
912 			/* It must be 0x000001ff */ \
913 			TGTPORTSTAT.FctP2IOWcnt[0]++; \
914 		} \
915 	} \
916 }
917 
918 typedef struct emlxs_tgtport_stat
919 {
920 	/* IO counters */
921 	uint64_t	FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */
922 	uint64_t	FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads  */
923 	uint64_t	FctIOCmdCnt;			/* Other, ie TUR */
924 	uint64_t	FctCmdReceived;			/* total IOs */
925 	uint64_t	FctReadBytes;			/* total read bytes */
926 	uint64_t	FctWriteBytes;			/* total write bytes */
927 
928 	/* IOCB handling counters */
929 	uint64_t	FctEvent;	/* FctStray + FctCompleted */
930 	uint64_t	FctCompleted;	/* FctCmplGood + FctCmplError */
931 	uint64_t	FctCmplGood;
932 
933 	uint32_t	FctCmplError;
934 	uint32_t	FctStray;
935 
936 	/* Fct event counters */
937 	uint32_t	FctRcvDropped;
938 	uint32_t	FctOverQDepth;
939 	uint32_t	FctOutstandingIO;
940 	uint32_t	FctFailedPortRegister;
941 	uint32_t	FctPortRegister;
942 	uint32_t	FctPortDeregister;
943 
944 	uint32_t	FctAbortSent;
945 	uint32_t	FctNoBuffer;
946 	uint32_t	FctScsiStatusErr;
947 	uint32_t	FctScsiQfullErr;
948 	uint32_t	FctScsiResidOver;
949 	uint32_t	FctScsiResidUnder;
950 	uint32_t	FctScsiSenseErr;
951 
952 	uint32_t	FctFiller1;
953 } emlxs_tgtport_stat_t;
954 
955 #ifdef FCT_IO_TRACE
956 #define	MAX_IO_TRACE	67
957 typedef struct emlxs_iotrace
958 {
959 	fct_cmd_t	*fct_cmd;
960 	uint32_t	xri;
961 	uint8_t		marker;  /* 0xff */
962 	uint8_t		trc[MAX_IO_TRACE]; /* trc[0] = index */
963 } emlxs_iotrace_t;
964 #endif /* FCT_IO_TRACE */
965 #endif /* SFCT_SUPPORT */
966 
967 
968 /*
969  *     Port Information Data Structure
970  */
971 
972 typedef struct emlxs_port
973 {
974 	struct emlxs_hba	*hba;
975 
976 	/* Virtual port management */
977 	uint32_t		vpi;
978 	uint32_t		flag;
979 #define	EMLXS_PORT_ENABLE		0x00000001
980 #define	EMLXS_PORT_BOUND		0x00000002
981 
982 #define	EMLXS_PORT_REGISTERED		0x00010000	/* VPI registered */
983 #define	EMLXS_PORT_INIT_VPI_CMPL	0x00020000	/* Init VPI - SLI4 */
984 #define	EMLXS_PORT_REG_VPI_CMPL		0x00040000	/* Reg VPI - SLI4 */
985 #define	EMLXS_PORT_IP_UP		0x00000010
986 #define	EMLXS_PORT_CONFIG		0x00000020
987 #define	EMLXS_PORT_RESTRICTED		0x00000040	/* Restrict logins */
988 							/* flag */
989 #define	EMLXS_PORT_FLOGI_CMPL		0x00000080	/* Fabric login */
990 							/* completed */
991 
992 #define	EMLXS_PORT_RESET_MASK		0x0000FFFF	/* Flags to keep */
993 							/* across hard reset */
994 #define	EMLXS_PORT_LINKDOWN_MASK	0xFFFFFFFF	/* Flags to keep */
995 							/* across link reset */
996 
997 	uint32_t		options;
998 #define	EMLXS_OPT_RESTRICT		0x00000001	/* Force restricted */
999 							/* logins */
1000 #define	EMLXS_OPT_UNRESTRICT		0x00000002	/* Force Unrestricted */
1001 							/* logins */
1002 #define	EMLXS_OPT_RESTRICT_MASK		0x00000003
1003 
1004 
1005 	/* FC world wide names */
1006 	NAME_TYPE		wwnn;
1007 	NAME_TYPE		wwpn;
1008 	char			snn[256];
1009 	char			spn[256];
1010 
1011 	/* Common service paramters */
1012 	SERV_PARM		sparam;
1013 	SERV_PARM		fabric_sparam;
1014 
1015 	/* fc_id management */
1016 	uint32_t		did;
1017 	uint32_t		prev_did;
1018 
1019 	/* support FC_PORT_GET_P2P_INFO only */
1020 	uint32_t		rdid;
1021 
1022 	/* FC_AL management */
1023 	uint8_t			lip_type;
1024 	uint8_t			alpa_map[128];
1025 
1026 	/* Node management */
1027 	emlxs_node_t		node_base;
1028 	uint32_t		node_count;
1029 	krwlock_t		node_rwlock;
1030 	emlxs_node_t		*node_table[EMLXS_NUM_HASH_QUES];
1031 
1032 	/* Polled packet management */
1033 	kcondvar_t		pkt_lock_cv;	/* pkt polling */
1034 	kmutex_t		pkt_lock;	/* pkt polling */
1035 
1036 	/* ULP */
1037 	uint32_t		ulp_statec;
1038 	void			(*ulp_statec_cb) ();	/* Port state change */
1039 							/* callback routine */
1040 	void			(*ulp_unsol_cb) ();	/* unsolicited event */
1041 							/* callback routine */
1042 	opaque_t		ulp_handle;
1043 
1044 	/* ULP unsolicited buffers */
1045 	kmutex_t		ub_lock;
1046 	uint32_t		ub_count;
1047 	emlxs_unsol_buf_t	*ub_pool;
1048 	uint32_t		ub_post[MAX_CHANNEL];
1049 	uint32_t		ub_timer;
1050 
1051 	emlxs_ub_priv_t		*ub_wait_head;	/* Unsolicited IO received */
1052 						/* before link up */
1053 	emlxs_ub_priv_t		*ub_wait_tail;	/* Unsolicited IO received */
1054 						/* before link up */
1055 
1056 
1057 #ifdef DHCHAP_SUPPORT
1058 	emlxs_port_dhc_t	port_dhc;
1059 #endif	/* DHCHAP_SUPPORT */
1060 
1061 	uint16_t		ini_mode;
1062 	uint16_t		tgt_mode;
1063 
1064 #ifdef SFCT_SUPPORT
1065 
1066 #define	FCT_BUF_COUNT_512		256
1067 #define	FCT_BUF_COUNT_8K		128
1068 #define	FCT_BUF_COUNT_64K		64
1069 #define	FCT_BUF_COUNT_128K		64
1070 #define	FCT_MAX_BUCKETS			16
1071 #define	FCT_DMEM_MAX_BUF_SIZE		131072   /* 128K */
1072 #define	FCT_DMEM_MAX_BUF_SEGMENT	8388608  /* 8M */
1073 
1074 	struct emlxs_fct_dmem_bucket dmem_bucket[FCT_MAX_BUCKETS];
1075 	int			fct_queue_depth;
1076 #define	EMLXS_FCT_DFLT_QDEPTH   64
1077 
1078 	char			cfd_name[24];
1079 	stmf_port_provider_t	*port_provider;
1080 	fct_local_port_t	*fct_port;
1081 	uint32_t		fct_flags;
1082 
1083 #define	FCT_STATE_PORT_ONLINE	0x00000001
1084 #define	FCT_STATE_NOT_ACKED	0x00000002
1085 #define	FCT_STATE_LINK_UP	0x00000010
1086 
1087 	emlxs_tgtport_stat_t	fct_stat;
1088 
1089 	/* Used to save fct_cmd for deferred unsol ELS commands, except FLOGI */
1090 	emlxs_buf_t		*fct_wait_head;
1091 	emlxs_buf_t		*fct_wait_tail;
1092 
1093 	/* Used to save context for deferred unsol FLOGIs */
1094 	fct_flogi_xchg_t	fx;
1095 	uint32_t		fx_context;
1096 #ifdef FCT_IO_TRACE
1097 	emlxs_iotrace_t		*iotrace;
1098 	uint16_t		iotrace_cnt;
1099 	uint16_t		iotrace_index;
1100 	kmutex_t		iotrace_mtx;
1101 #endif /* FCT_IO_TRACE */
1102 
1103 #endif /* SFCT_SUPPORT */
1104 
1105 #ifdef SAN_DIAG_SUPPORT
1106 	uint8_t			sd_io_latency_state;
1107 #define	SD_INVALID	0x00
1108 #define	SD_COLLECTING	0x01
1109 #define	SD_STOPPED	0x02
1110 
1111 	/* SD event management list */
1112 	uint32_t		sd_event_mask;   /* bit-mask */
1113 	emlxs_dfc_event_t	sd_events[MAX_DFC_EVENTS];
1114 #endif
1115 	/* Used for SLI4 */
1116 	uint16_t	outstandingRPIs;
1117 	struct VFIobject *VFIp;
1118 } emlxs_port_t;
1119 
1120 
1121 
1122 /* Host Attn reg */
1123 #define	FC_HA_REG(_hba)		((volatile uint32_t *) \
1124 				    ((_hba)->sli.sli3.ha_reg_addr))
1125 
1126 /* Chip Attn reg */
1127 #define	FC_CA_REG(_hba)		((volatile uint32_t *) \
1128 				    ((_hba)->sli.sli3.ca_reg_addr))
1129 
1130 /* Host Status reg */
1131 #define	FC_HS_REG(_hba)		((volatile uint32_t *) \
1132 				    ((_hba)->sli.sli3.hs_reg_addr))
1133 
1134 /* Host Cntl reg */
1135 #define	FC_HC_REG(_hba)		((volatile uint32_t *) \
1136 				    ((_hba)->sli.sli3.hc_reg_addr))
1137 
1138 /* BIU Configuration reg */
1139 #define	FC_BC_REG(_hba)		((volatile uint32_t *) \
1140 				    ((_hba)->sli.sli3.bc_reg_addr))
1141 
1142 /* Used by SBUS adapter */
1143 /* TITAN Cntl reg */
1144 #define	FC_SHC_REG(_hba)	((volatile uint32_t *) \
1145 				    ((_hba)->sli.sli3.shc_reg_addr))
1146 
1147 /* TITAN Status reg */
1148 #define	FC_SHS_REG(_hba)	((volatile uint32_t *) \
1149 				    ((_hba)->sli.sli3.shs_reg_addr))
1150 
1151 /* TITAN Update reg */
1152 #define	FC_SHU_REG(_hba)	((volatile uint32_t *) \
1153 				    ((_hba)->sli.sli3.shu_reg_addr))
1154 
1155 /* MPU Semaphore reg */
1156 #define	FC_SEMA_REG(_hba)	((volatile uint32_t *)\
1157 				    ((_hba)->sli.sli4.MPUEPSemaphore_reg_addr))
1158 
1159 /* Bootstrap Mailbox Doorbell reg */
1160 #define	FC_MBDB_REG(_hba)	((volatile uint32_t *) \
1161 				    ((_hba)->sli.sli4.MBDB_reg_addr))
1162 
1163 /* MQ Doorbell reg */
1164 #define	FC_MQDB_REG(_hba)	((volatile uint32_t *) \
1165 				    ((_hba)->sli.sli4.MQDB_reg_addr))
1166 
1167 /* CQ Doorbell reg */
1168 #define	FC_CQDB_REG(_hba)	((volatile uint32_t *) \
1169 				    ((_hba)->sli.sli4.CQDB_reg_addr))
1170 
1171 /* WQ Doorbell reg */
1172 #define	FC_WQDB_REG(_hba)	((volatile uint32_t *) \
1173 				    ((_hba)->sli.sli4.WQDB_reg_addr))
1174 
1175 /* RQ Doorbell reg */
1176 #define	FC_RQDB_REG(_hba)	((volatile uint32_t *) \
1177 				    ((_hba)->sli.sli4.RQDB_reg_addr))
1178 
1179 
1180 #define	FC_SLIM2_MAILBOX(_hba)	((MAILBOX *)(_hba)->sli.sli3.slim2.virt)
1181 
1182 #define	FC_SLIM1_MAILBOX(_hba)	((MAILBOX *)(_hba)->sli.sli3.slim_addr)
1183 
1184 #define	FC_MAILBOX(_hba)	(((_hba)->flag & FC_SLIM2_MODE) ? \
1185 	FC_SLIM2_MAILBOX(_hba) : FC_SLIM1_MAILBOX(_hba))
1186 
1187 #define	WRITE_CSR_REG(_hba, _regp, _value) ddi_put32(\
1188 	(_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp), \
1189 	(uint32_t)(_value))
1190 
1191 #define	READ_CSR_REG(_hba, _regp) ddi_get32(\
1192 	(_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp))
1193 
1194 #define	WRITE_SLIM_ADDR(_hba, _regp, _value) ddi_put32(\
1195 	(_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp), \
1196 	(uint32_t)(_value))
1197 
1198 #define	READ_SLIM_ADDR(_hba, _regp) ddi_get32(\
1199 	(_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp))
1200 
1201 #define	WRITE_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_put32(\
1202 	(_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \
1203 	(uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR)
1204 
1205 #define	READ_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_get32(\
1206 	(_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \
1207 	(uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR)
1208 
1209 /* Used by SBUS adapter */
1210 #define	WRITE_SBUS_CSR_REG(_hba, _regp, _value)	ddi_put32(\
1211 	(_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp), \
1212 	(uint32_t)(_value))
1213 
1214 #define	READ_SBUS_CSR_REG(_hba, _regp) ddi_get32(\
1215 	(_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp))
1216 
1217 #define	SBUS_WRITE_FLASH_COPY(_hba, _offset, _value) ddi_put8(\
1218 	(_hba)->sli.sli3.sbus_flash_acc_handle, \
1219 	(uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \
1220 	(_offset)), (uint8_t)(_value))
1221 
1222 #define	SBUS_READ_FLASH_COPY(_hba, _offset) ddi_get8(\
1223 	(_hba)->sli.sli3.sbus_flash_acc_handle, \
1224 	(uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \
1225 	(_offset)))
1226 
1227 /* SLI4 registers */
1228 #define	WRITE_BAR1_REG(_hba, _regp, _value) ddi_put32(\
1229 	(_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp), \
1230 	(uint32_t)(_value))
1231 
1232 #define	READ_BAR1_REG(_hba, _regp) ddi_get32(\
1233 	(_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp))
1234 
1235 #define	WRITE_BAR2_REG(_hba, _regp, _value) ddi_put32(\
1236 	(_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp), \
1237 	(uint32_t)(_value))
1238 
1239 #define	READ_BAR2_REG(_hba, _regp) ddi_get32(\
1240 	(_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp))
1241 
1242 
1243 #define	EMLXS_STATE_CHANGE(_hba, _state)\
1244 {									\
1245 	mutex_enter(&EMLXS_PORT_LOCK);					\
1246 	EMLXS_STATE_CHANGE_LOCKED((_hba), (_state));			\
1247 	mutex_exit(&EMLXS_PORT_LOCK);					\
1248 }
1249 
1250 /* Used when EMLXS_PORT_LOCK is already held */
1251 #define	EMLXS_STATE_CHANGE_LOCKED(_hba, _state)			\
1252 {									\
1253 	if ((_hba)->state != (_state))					\
1254 	{								\
1255 		uint32_t _st = _state;					\
1256 		EMLXS_MSGF(EMLXS_CONTEXT,				\
1257 			&emlxs_state_msg, "%s --> %s",			\
1258 			emlxs_ffstate_xlate((_hba)->state),		\
1259 			emlxs_ffstate_xlate(_state));			\
1260 			(_hba)->state = (_state);			\
1261 		if ((_st) == FC_ERROR)					\
1262 		{							\
1263 			(_hba)->flag |= FC_HARDWARE_ERROR;		\
1264 		}							\
1265 	}								\
1266 }
1267 
1268 #ifdef FMA_SUPPORT
1269 #define	EMLXS_CHK_ACC_HANDLE(_hba, _acc) \
1270 	if (emlxs_fm_check_acc_handle(_hba, _acc) != DDI_FM_OK) { \
1271 		EMLXS_MSGF(EMLXS_CONTEXT, \
1272 		    &emlxs_invalid_access_handle_msg, NULL); \
1273 	}
1274 #endif  /* FMA_SUPPORT */
1275 
1276 /*
1277  * This is the HBA control area for the adapter
1278  */
1279 
1280 #ifdef MODSYM_SUPPORT
1281 
1282 typedef struct emlxs_modsym
1283 {
1284 	ddi_modhandle_t  mod_fctl;	/* For Leadville */
1285 
1286 	/* Leadville (fctl) */
1287 	int		(*fc_fca_attach)(dev_info_t *, fc_fca_tran_t *);
1288 	int		(*fc_fca_detach)(dev_info_t *);
1289 	int		(*fc_fca_init)(struct dev_ops *);
1290 
1291 #ifdef SFCT_SUPPORT
1292 	uint32_t	fct_modopen;
1293 	uint32_t	reserved;  /* Padding for alignment */
1294 
1295 	ddi_modhandle_t  mod_fct;	/* For Comstar */
1296 	ddi_modhandle_t  mod_stmf;	/* For Comstar */
1297 
1298 	/* Comstar (fct) */
1299 	void*	(*fct_alloc)(fct_struct_id_t, int, int);
1300 	void	(*fct_free)(void *);
1301 	void*	(*fct_scsi_task_alloc)(void *, uint16_t, uint32_t, uint8_t *,
1302 			uint16_t, uint16_t);
1303 	int	(*fct_register_local_port)(fct_local_port_t *);
1304 	void	(*fct_deregister_local_port)(fct_local_port_t *);
1305 	void	(*fct_handle_event)(fct_local_port_t *, int, uint32_t, caddr_t);
1306 	void	(*fct_post_rcvd_cmd)(fct_cmd_t *, stmf_data_buf_t *);
1307 	void	(*fct_ctl)(void *, int, void *);
1308 	void	(*fct_queue_cmd_for_termination)(fct_cmd_t *, fct_status_t);
1309 	void	(*fct_send_response_done)(fct_cmd_t *, fct_status_t, uint32_t);
1310 	void	(*fct_send_cmd_done)(fct_cmd_t *, fct_status_t, uint32_t);
1311 	void	(*fct_scsi_data_xfer_done)(fct_cmd_t *, stmf_data_buf_t *,
1312 			uint32_t);
1313 	fct_status_t	(*fct_port_shutdown)
1314 				(fct_local_port_t *, uint32_t, char *);
1315 	fct_status_t	(*fct_port_initialize)
1316 				(fct_local_port_t *, uint32_t, char *);
1317 	void		(*fct_cmd_fca_aborted)
1318 				(fct_cmd_t *, fct_status_t, int);
1319 	fct_status_t	(*fct_handle_rcvd_flogi)
1320 				(fct_local_port_t *, fct_flogi_xchg_t *);
1321 
1322 	/* Comstar (stmf) */
1323 	void*  (*stmf_alloc)(stmf_struct_id_t, int, int);
1324 	void   (*stmf_free)(void *);
1325 	void	(*stmf_deregister_port_provider) (stmf_port_provider_t *);
1326 	int	(*stmf_register_port_provider) (stmf_port_provider_t *);
1327 #endif /* SFCT_SUPPORT */
1328 } emlxs_modsym_t;
1329 extern emlxs_modsym_t emlxs_modsym;
1330 
1331 #define	MODSYM(_f)	emlxs_modsym._f
1332 
1333 #else
1334 
1335 #define	MODSYM(_f)	_f
1336 
1337 #endif /* MODSYM_SUPPORT */
1338 
1339 
1340 
1341 /* defines for resource state */
1342 #define	RESOURCE_FREE		0
1343 #define	RESOURCE_ALLOCATED	1
1344 
1345 #define	RESOURCE_FCFI_REG	2
1346 #define	RESOURCE_FCFI_DISC	4
1347 #define	RESOURCE_FCFI_VLAN_ID	8
1348 
1349 #define	RESOURCE_VFI_REG	2
1350 
1351 #define	RESOURCE_RPI_PAUSED	2
1352 
1353 #define	RESOURCE_XRI_RESERVED		2
1354 #define	RESOURCE_XRI_PENDING_IO		4
1355 #define	RESOURCE_XRI_ABORT_INP		8
1356 
1357 typedef struct VFIobject
1358 {
1359 	uint16_t	index;
1360 	uint16_t	VFI;
1361 	uint16_t	state;
1362 	uint16_t	outstandingVPIs;
1363 	struct FCFIobject *FCFIp;
1364 } VFIobj_t;
1365 
1366 typedef struct RPIobject
1367 {
1368 	uint16_t	index;
1369 	uint16_t	RPI;
1370 	uint16_t	state;
1371 	uint16_t	outstandingXRIs;
1372 	emlxs_port_t	*VPIp;
1373 	uint32_t	did;
1374 	emlxs_node_t	*node;
1375 } RPIobj_t;
1376 
1377 typedef struct XRIobject
1378 {
1379 	struct XRIobject *_f;
1380 	struct XRIobject *_b;
1381 	uint16_t	XRI;
1382 	uint16_t	state;
1383 	uint16_t	sge_count;
1384 	uint16_t	iotag;
1385 	MBUF_INFO	SGList;
1386 	RPIobj_t	*RPIp;
1387 	emlxs_buf_t	*sbp;
1388 	uint32_t 	rx_id; /* Used for unsol exchanges */
1389 } XRIobj_t;
1390 
1391 typedef struct FCFIobject
1392 {
1393 	uint16_t	index;
1394 	uint16_t	FCFI;
1395 	uint16_t	FCF_index;
1396 	uint16_t	state;
1397 	uint16_t	outstandingVFIs;
1398 	uint16_t	vlan_id;
1399 	uint32_t	EventTag;
1400 	struct VFIobject *fcf_vfi;
1401 	emlxs_port_t	*fcf_vpi;
1402 	struct RPIobject scratch_rpi;
1403 	SERV_PARM	fcf_sparam;
1404 	FCF_RECORD_t	fcf_rec;
1405 } FCFIobj_t;
1406 
1407 typedef struct RPIHdrTmplate
1408 {
1409 	uint32_t	Word[16];  /* 64 bytes */
1410 } RPIHdrTmplate_t;
1411 
1412 typedef struct EQ_DESC
1413 {
1414 	uint16_t	host_index;
1415 	uint16_t	max_index;
1416 	uint16_t	qid;
1417 	uint16_t	msix_vector;
1418 	kmutex_t	lastwq_lock;
1419 	uint16_t	lastwq;
1420 	MBUF_INFO	addr;
1421 } EQ_DESC_t;
1422 
1423 typedef struct CQ_DESC
1424 {
1425 	uint16_t	host_index;
1426 	uint16_t	max_index;
1427 	uint16_t	qid;
1428 	uint16_t	eqid;
1429 	uint16_t	type;
1430 #define	EMLXS_CQ_TYPE_GROUP1	1  /* associated with a MQ and async events */
1431 #define	EMLXS_CQ_TYPE_GROUP2	2  /* associated with a WQ and RQ */
1432 	uint16_t	rsvd;
1433 
1434 	MBUF_INFO	addr;
1435 	CHANNEL		*channelp; /* ptr to CHANNEL associated with CQ */
1436 
1437 } CQ_DESC_t;
1438 
1439 typedef struct WQ_DESC
1440 {
1441 	uint16_t	host_index;
1442 	uint16_t	max_index;
1443 	uint16_t	port_index;
1444 	uint16_t	release_depth;
1445 #define	WQE_RELEASE_DEPTH	(8 * EMLXS_NUM_WQ_PAGES)
1446 	uint16_t	qid;
1447 	uint16_t	cqid;
1448 	MBUF_INFO	addr;
1449 } WQ_DESC_t;
1450 
1451 typedef struct RQ_DESC
1452 {
1453 	uint16_t	host_index;
1454 	uint16_t	max_index;
1455 	uint16_t	qid;
1456 	uint16_t	cqid;
1457 
1458 	MBUF_INFO	addr;
1459 	MEMSEG		rqb_pool;
1460 	MATCHMAP	*rqb[RQ_DEPTH];
1461 
1462 	kmutex_t	lock;
1463 
1464 } RQ_DESC_t;
1465 
1466 
1467 typedef struct RXQ_DESC
1468 {
1469 	kmutex_t	lock;
1470 	emlxs_queue_t	active;
1471 
1472 } RXQ_DESC_t;
1473 
1474 
1475 typedef struct MQ_DESC
1476 {
1477 	uint16_t	host_index;
1478 	uint16_t	max_index;
1479 	uint16_t	qid;
1480 	uint16_t	cqid;
1481 	MBUF_INFO	addr;
1482 } MQ_DESC_t;
1483 
1484 /* Define the number of queues the driver will be using */
1485 #define	EMLXS_MAX_EQS	EMLXS_MSI_MAX_INTRS
1486 #define	EMLXS_MAX_WQS	EMLXS_MSI_MAX_INTRS
1487 #define	EMLXS_MAX_RQS	2	/* ONLY 1 pair is allowed */
1488 #define	EMLXS_MAX_MQS	1
1489 
1490 /* One CQ for each WQ & (RQ pair) plus one for the MQ */
1491 #define	EMLXS_MAX_CQS	(EMLXS_MAX_WQS + (EMLXS_MAX_RQS/2) + 1)
1492 
1493 /* The First CQ created is ALWAYS for mbox / event handling */
1494 #define	EMLXS_CQ_MBOX		0
1495 
1496 /* The Second CQ created is ALWAYS for unsol rcv handling */
1497 /* At this time we are allowing ONLY 1 pair of RQs */
1498 #define	EMLXS_CQ_RCV		1
1499 
1500 /* The remaining CQs are for WQ completions */
1501 #define	EMLXS_CQ_OFFSET_WQ	2
1502 
1503 
1504 /* FCFI RQ Configuration */
1505 #define	EMLXS_FCFI_RQ0_INDEX	0
1506 #define	EMLXS_FCFI_RQ0_RMASK	0 /* match all */
1507 #define	EMLXS_FCFI_RQ0_RCTL	0 /* match all */
1508 #define	EMLXS_FCFI_RQ0_TMASK	0 /* match all */
1509 #define	EMLXS_FCFI_RQ0_TYPE	0 /* match all */
1510 
1511 /* Define the maximum value for a Queue Id */
1512 #define	EMLXS_MAX_EQ_IDS	256
1513 #define	EMLXS_MAX_CQ_IDS	1024
1514 #define	EMLXS_MAX_WQ_IDS	1024
1515 #define	EMLXS_MAX_RQ_IDS	4
1516 
1517 #define	EMLXS_RXQ_ELS		0
1518 #define	EMLXS_RXQ_CT		1
1519 #define	EMLXS_MAX_RXQS		2
1520 
1521 #define	PCI_CONFIG_SIZE   0x80
1522 
1523 typedef struct emlxs_sli3
1524 {
1525 	/* SLIM management */
1526 	MATCHMAP	slim2;
1527 
1528 	/* HBQ management */
1529 	uint32_t	hbq_count;	/* Total number of HBQs */
1530 					/* configured */
1531 	HBQ_INIT_t	hbq_table[EMLXS_NUM_HBQ];
1532 
1533 	/* Adapter memory management */
1534 	caddr_t		csr_addr;
1535 	caddr_t		slim_addr;
1536 	ddi_acc_handle_t csr_acc_handle;
1537 	ddi_acc_handle_t slim_acc_handle;
1538 
1539 	/* SBUS adapter management */
1540 	caddr_t		sbus_flash_addr;	/* Virt addr of R/W */
1541 						/* Flash */
1542 	caddr_t		sbus_core_addr;		/* Virt addr of TITAN */
1543 						/* CORE */
1544 	caddr_t		sbus_csr_addr;		/* Virt addr of TITAN */
1545 						/* CSR */
1546 	ddi_acc_handle_t sbus_flash_acc_handle;
1547 	ddi_acc_handle_t sbus_core_acc_handle;
1548 	ddi_acc_handle_t sbus_csr_handle;
1549 
1550 	/* SLI 2/3 Adapter register management */
1551 	uint32_t	*bc_reg_addr;	/* virtual offset for BIU */
1552 					/* config reg */
1553 	uint32_t	*ha_reg_addr;	/* virtual offset for host */
1554 					/* attn reg */
1555 	uint32_t	*hc_reg_addr;	/* virtual offset for host */
1556 					/* ctl reg */
1557 	uint32_t	*ca_reg_addr;	/* virtual offset for FF */
1558 					/* attn reg */
1559 	uint32_t	*hs_reg_addr;	/* virtual offset for */
1560 					/* status reg */
1561 	uint32_t	*shc_reg_addr;	/* virtual offset for SBUS */
1562 					/* Ctrl reg */
1563 	uint32_t	*shs_reg_addr;	/* virtual offset for SBUS */
1564 					/* Status reg */
1565 	uint32_t	*shu_reg_addr;	/* virtual offset for SBUS */
1566 					/* Update reg */
1567 	uint16_t	hgp_ring_offset;
1568 	uint16_t	hgp_hbq_offset;
1569 	uint16_t	iocb_cmd_size;
1570 	uint16_t	iocb_rsp_size;
1571 	uint32_t	hc_copy;	/* local copy of HC register */
1572 
1573 	/* Ring management */
1574 	uint32_t	ring_count;
1575 	emlxs_ring_t	ring[MAX_RINGS];
1576 	kmutex_t	ring_cmd_lock[MAX_RINGS];
1577 	uint8_t		ring_masks[4];	/* number of masks/rings used */
1578 	uint8_t		ring_rval[6];
1579 	uint8_t		ring_rmask[6];
1580 	uint8_t		ring_tval[6];
1581 	uint8_t		ring_tmask[6];
1582 
1583 	/* Protected by EMLXS_FCTAB_LOCK */
1584 #ifdef EMLXS_SPARC
1585 	MEMSEG		fcp_bpl_seg;
1586 	MATCHMAP	**fcp_bpl_table; /* iotag table for */
1587 					/* bpl buffers */
1588 #endif	/* EMLXS_SPARC */
1589 	uint32_t	mem_bpl_size;
1590 } emlxs_sli3_t;
1591 
1592 typedef struct emlxs_sli4
1593 {
1594 	MATCHMAP	bootstrapmb;
1595 	caddr_t		bar1_addr;
1596 	caddr_t		bar2_addr;
1597 	ddi_acc_handle_t bar1_acc_handle;
1598 	ddi_acc_handle_t bar2_acc_handle;
1599 
1600 	/* SLI4 Adapter register management */
1601 	uint32_t	*MPUEPSemaphore_reg_addr;
1602 	uint32_t	*MBDB_reg_addr;
1603 
1604 	uint32_t	*CQDB_reg_addr;
1605 	uint32_t	*MQDB_reg_addr;
1606 	uint32_t	*WQDB_reg_addr;
1607 	uint32_t	*RQDB_reg_addr;
1608 
1609 	uint32_t	flag;
1610 #define	EMLXS_SLI4_INTR_ENABLED		0x1
1611 
1612 	uint16_t	XRICount;
1613 	uint16_t	XRIBase;
1614 	uint16_t	RPICount;
1615 	uint16_t	RPIBase;
1616 	uint16_t	VPICount;
1617 	uint16_t	VPIBase;
1618 	uint16_t	VFICount;
1619 	uint16_t	VFIBase;
1620 	uint16_t	FCFICount;
1621 
1622 	kmutex_t	id_lock; /* for FCFI, VFI, VPI, RPI, XRI mgmt */
1623 	FCFIobj_t	*FCFIp;
1624 	VFIobj_t	*VFIp;
1625 
1626 	/* Save Config Region 23 info */
1627 	tlv_fcoe_t	cfgFCOE;
1628 	tlv_fcfconnectlist_t	cfgFCF;
1629 
1630 	MBUF_INFO	dump_region;
1631 #define	EMLXS_DUMP_REGION_SIZE	1024
1632 
1633 	RPIobj_t	*RPIp;
1634 	MBUF_INFO	HeaderTmplate;
1635 	XRIobj_t	*XRIp;
1636 	/* Single linked list for available XRIs */
1637 	XRIobj_t	*XRIfree_list;
1638 	XRIobj_t	*XRIfree_tail;
1639 	uint32_t	xrif_count;
1640 	uint32_t	mem_sgl_size;
1641 
1642 	/* Double linked list for XRIs in use */
1643 	XRIobj_t	*XRIinuse_f;
1644 	XRIobj_t	*XRIinuse_b;
1645 	uint32_t	xria_count;
1646 
1647 	EQ_DESC_t	eq[EMLXS_MAX_EQS];
1648 	CQ_DESC_t	cq[EMLXS_MAX_CQS];
1649 	WQ_DESC_t	wq[EMLXS_MAX_WQS];
1650 	RQ_DESC_t	rq[EMLXS_MAX_RQS];
1651 	MQ_DESC_t	mq;
1652 
1653 	/* Used to map a queue ID to a queue DESC_t */
1654 	uint16_t	eq_map[EMLXS_MAX_EQ_IDS];
1655 	uint16_t	cq_map[EMLXS_MAX_CQ_IDS];
1656 	uint16_t	wq_map[EMLXS_MAX_WQ_IDS];
1657 	uint16_t	rq_map[EMLXS_MAX_RQ_IDS];
1658 
1659 	RXQ_DESC_t	rxq[EMLXS_MAX_RXQS];
1660 
1661 } emlxs_sli4_t;
1662 
1663 
1664 typedef struct emlxs_sli_api
1665 {
1666 	int		(*sli_map_hdw)();
1667 	void		(*sli_unmap_hdw)();
1668 	int32_t		(*sli_online)();
1669 	void		(*sli_offline)();
1670 	uint32_t	(*sli_hba_reset)();
1671 	void		(*sli_hba_kill)();
1672 	void		(*sli_issue_iocb_cmd)();
1673 	uint32_t	(*sli_issue_mbox_cmd)();
1674 	uint32_t	(*sli_prep_fct_iocb)();
1675 	uint32_t	(*sli_prep_fcp_iocb)();
1676 	uint32_t	(*sli_prep_ip_iocb)();
1677 	uint32_t	(*sli_prep_els_iocb)();
1678 	uint32_t	(*sli_prep_ct_iocb)();
1679 	void		(*sli_poll_intr)();
1680 	int32_t		(*sli_intx_intr)();
1681 	uint32_t	(*sli_msi_intr)();
1682 	void		(*sli_disable_intr)();
1683 	void		(*sli_timer)();
1684 	void		(*sli_poll_erratt)();
1685 
1686 } emlxs_sli_api_t;
1687 
1688 
1689 typedef struct emlxs_hba
1690 {
1691 	dev_info_t	*dip;
1692 	int32_t		emlxinst;
1693 	int32_t		ddiinst;
1694 	uint8_t		pci_function_number;
1695 	uint8_t		pci_device_number;
1696 	uint8_t		pci_bus_number;
1697 #ifdef FMA_SUPPORT
1698 	int32_t		fm_caps;	/* FMA capabilities */
1699 #endif	/* FMA_SUPPORT */
1700 	fc_fca_tran_t	*fca_tran;
1701 
1702 	/* HBA Info */
1703 	emlxs_model_t	model_info;
1704 	emlxs_vpd_t	vpd;	/* vital product data */
1705 	NAME_TYPE	wwnn;
1706 	NAME_TYPE	wwpn;
1707 	char		snn[256];
1708 	char		spn[256];
1709 	PROG_ID		load_list[MAX_LOAD_ENTRY];
1710 	WAKE_UP_PARMS	wakeup_parms;
1711 	uint32_t	max_nodes;
1712 	uint32_t	io_throttle;
1713 	uint32_t	io_active;
1714 	uint32_t	bus_type;
1715 #define	PCI_FC  	0
1716 #define	SBUS_FC		1
1717 
1718 	/* Link management */
1719 	uint32_t	link_event_tag;
1720 	uint8_t		topology;
1721 	uint8_t		linkspeed;
1722 	uint32_t	linkup_wait_flag;
1723 	kcondvar_t	linkup_lock_cv;
1724 	kmutex_t	linkup_lock;
1725 
1726 	/* Memory Pool management */
1727 	emlxs_memseg_t	memseg[FC_MAX_SEG];	/* memory for buffer */
1728 							/* structures */
1729 	kmutex_t	memget_lock;	/* locks all memory pools get */
1730 	kmutex_t	memput_lock;	/* locks all memory pools put */
1731 
1732 	/* Fibre Channel Service Parameters */
1733 	SERV_PARM	sparam;
1734 	uint32_t	fc_edtov;	/* E_D_TOV timer value */
1735 	uint32_t	fc_arbtov;	/* ARB_TOV timer value */
1736 	uint32_t	fc_ratov;	/* R_A_TOV timer value */
1737 	uint32_t	fc_rttov;	/* R_T_TOV timer value */
1738 	uint32_t	fc_altov;	/* AL_TOV timer value */
1739 	uint32_t	fc_crtov;	/* C_R_TOV timer value */
1740 	uint32_t	fc_citov;	/* C_I_TOV timer value */
1741 
1742 	/* Adapter State management */
1743 	int32_t		state;
1744 #define	FC_ERROR		0x01	/* Adapter shutdown */
1745 #define	FC_KILLED		0x02	/* Adapter interlocked/killed */
1746 #define	FC_WARM_START		0x03	/* Adapter reset, but not restarted */
1747 #define	FC_INIT_START		0x10	/* Adapter restarted */
1748 #define	FC_INIT_NVPARAMS	0x11
1749 #define	FC_INIT_REV		0x12
1750 #define	FC_INIT_CFGPORT		0x13
1751 #define	FC_INIT_CFGRING		0x14
1752 #define	FC_INIT_INITLINK	0x15
1753 #define	FC_LINK_DOWN		0x20
1754 #define	FC_LINK_DOWN_PERSIST	0x21
1755 #define	FC_LINK_UP		0x30
1756 #define	FC_CLEAR_LA		0x31
1757 #define	FC_READY		0x40
1758 
1759 	uint32_t	flag;
1760 #define	FC_ONLINING_MODE	0x00000001
1761 #define	FC_ONLINE_MODE		0x00000002
1762 #define	FC_OFFLINING_MODE	0x00000004
1763 #define	FC_OFFLINE_MODE		0x00000008
1764 
1765 #define	FC_NPIV_ENABLED		0x00000010	/* NPIV enabled on adapter    */
1766 #define	FC_NPIV_SUPPORTED	0x00000020	/* NPIV supported on fabric   */
1767 #define	FC_NPIV_UNSUPPORTED	0x00000040	/* NPIV unsupported on fabric */
1768 #define	FC_NPIV_LINKUP		0x00000100	/* NPIV enabled, supported, */
1769 						/* and link is ready */
1770 #define	FC_NPIV_DELAY_REQUIRED	0x00000200	/* Delay issuing FLOGI/FDISC */
1771 						/* and NameServer cmds */
1772 
1773 #define	FC_BOOTSTRAPMB_INIT	0x00000400
1774 #define	FC_FIP_SUPPORTED	0x00000800	/* FIP supported */
1775 
1776 #define	FC_FABRIC_ATTACHED	0x00001000
1777 #define	FC_PT_TO_PT		0x00002000
1778 #define	FC_BYPASSED_MODE	0x00004000
1779 #define	FC_MENLO_MODE		0x00008000	/* Menlo maintenance mode */
1780 
1781 #define	FC_DUMP_SAFE		0x00010000	/* Safe to DUMP */
1782 #define	FC_DUMP_ACTIVE		0x00020000	/* DUMP in progress */
1783 
1784 #define	FC_SLIM2_MODE		0x00100000	/* SLIM in host memory */
1785 #define	FC_INTERLOCKED		0x00200000
1786 #define	FC_HBQ_ENABLED		0x00400000
1787 #define	FC_ASYNC_EVENTS		0x00800000
1788 
1789 #define	FC_ILB_MODE		0x01000000
1790 #define	FC_ELB_MODE		0x02000000
1791 #define	FC_LOOPBACK_MODE	0x03000000	/* Loopback Mode Mask */
1792 #define	FC_DUMP			0x04000000	/* DUMP in progress */
1793 #define	FC_SHUTDOWN		0x08000000	/* SHUTDOWN in progress */
1794 
1795 #define	FC_OVERTEMP_EVENT	0x10000000	/* FC_ERROR reason: */
1796 						/* over temperature event */
1797 #define	FC_MBOX_TIMEOUT		0x20000000	/* FC_ERROR reason: */
1798 						/* mailbox timeout event */
1799 #define	FC_HARDWARE_ERROR	0x80000000	/* FC_ERROR state triggered */
1800 
1801 #define	FC_RESET_MASK		0x00030C1F	/* Bits to protect during */
1802 						/* a hard reset */
1803 #define	FC_LINKDOWN_MASK	0xFFF30C1F	/* Bits to protect during */
1804 						/* a linkdown */
1805 
1806 	uint32_t temperature;			/* Last reported temperature */
1807 
1808 	/* SBUS adapter management */
1809 	caddr_t		sbus_pci_addr;		/* Virt addr of TITAN */
1810 						/* pci config */
1811 	ddi_acc_handle_t sbus_pci_handle;
1812 
1813 	/* PCI BUS adapter management */
1814 	caddr_t		pci_addr;
1815 	ddi_acc_handle_t pci_acc_handle;
1816 
1817 	uint32_t	sli_mode;
1818 #define	EMLXS_HBA_SLI1_MODE	1
1819 #define	EMLXS_HBA_SLI2_MODE	2
1820 #define	EMLXS_HBA_SLI3_MODE	3
1821 #define	EMLXS_HBA_SLI4_MODE	4
1822 
1823 	/* SLI private data */
1824 	union {
1825 		emlxs_sli3_t sli3;
1826 		emlxs_sli4_t sli4;
1827 	} sli;
1828 
1829 	/* SLI API entry point routines */
1830 	emlxs_sli_api_t sli_api;
1831 
1832 	uint32_t	io_poll_count;	/* Number of poll commands */
1833 					/* in progress */
1834 
1835 	/* IO Completion management */
1836 	uint32_t	iodone_count;	/* Number of IO's on done Q */
1837 	/* Protected by EMLXS_PORT_LOCK  */
1838 	emlxs_buf_t	*iodone_list;	/* fc_packet being deferred */
1839 	emlxs_buf_t	*iodone_tail;	/* fc_packet being deferred */
1840 	emlxs_thread_t	iodone_thread;
1841 	emlxs_thread_t	*spawn_thread_head;
1842 	emlxs_thread_t	*spawn_thread_tail;
1843 	kmutex_t	spawn_lock;
1844 	uint32_t	spawn_open;
1845 
1846 	/* IO Channel management */
1847 	int32_t		chan_count;
1848 	emlxs_channel_t	chan[MAX_CHANNEL];
1849 	kmutex_t	channel_tx_lock;
1850 	uint8_t		channel_fcp;	/* Default channel to use for FCP IO */
1851 #define	CHANNEL_FCT channel_fcp
1852 	uint8_t		channel_ip;	/* Default channel to use for IP IO */
1853 	uint8_t		channel_els;	/* Default channel to use for ELS IO */
1854 	uint8_t		channel_ct;	/* Default channel to use for CT IO */
1855 
1856 	/* IOTag management */
1857 	emlxs_buf_t	**fc_table;	/* sc_buf pointers indexed by */
1858 					/* iotag */
1859 	uint16_t	fc_iotag;	/* used to identify I/Os */
1860 	uint16_t	fc_oor_iotag;	/* OutOfRange (fc_table) iotags */
1861 					/* typically used for Abort/close */
1862 #define	EMLXS_MAX_ABORT_TAG	0x7fff
1863 	uint16_t	max_iotag;	/* ALL IOCBs except aborts */
1864 	kmutex_t	iotag_lock;
1865 	uint32_t	io_count;		/* No of IO holding */
1866 						/* regular iotag */
1867 	uint32_t	channel_tx_count;	/* No of IO on tx Q */
1868 
1869 	/* Mailbox Management */
1870 	uint32_t	mbox_queue_flag;
1871 	emlxs_queue_t	mbox_queue;
1872 	uint32_t	*mbox_mqe;	/* active mbox mqe */
1873 	uint8_t		*mbox_mbq;	/* active MAILBOXQ */
1874 	kcondvar_t	mbox_lock_cv;	/* MBX_SLEEP */
1875 	kmutex_t	mbox_lock;	/* MBX_SLEEP */
1876 	uint32_t	mbox_timer;
1877 
1878 	/* Interrupt management */
1879 	void		*intr_arg;
1880 	uint32_t	intr_unclaimed;
1881 	uint32_t	intr_autoClear;
1882 	uint32_t	intr_flags;
1883 #define	EMLXS_INTX_INITED	0x0001
1884 #define	EMLXS_INTX_ADDED	0x0002
1885 #define	EMLXS_MSI_ENABLED	0x0010
1886 #define	EMLXS_MSI_INITED	0x0020
1887 #define	EMLXS_MSI_ADDED		0x0040
1888 #define	EMLXS_INTR_INITED	(EMLXS_INTX_INITED|EMLXS_MSI_INITED)
1889 #define	EMLXS_INTR_ADDED	(EMLXS_INTX_ADDED|EMLXS_MSI_ADDED)
1890 
1891 #ifdef MSI_SUPPORT
1892 	ddi_intr_handle_t *intr_htable;
1893 	uint32_t	*intr_pri;
1894 	int32_t		*intr_cap;
1895 	uint32_t	intr_count;
1896 	uint32_t	intr_type;
1897 	uint32_t	intr_cond;
1898 	uint32_t	intr_map[EMLXS_MSI_MAX_INTRS];
1899 	uint32_t	intr_mask;
1900 	uint32_t	msi_cap_offset;
1901 #define	MSI_CAP_ID	0x05
1902 
1903 	uint32_t	msix_cap_offset;
1904 #define	MSIX_CAP_ID	0x11
1905 
1906 	kmutex_t	intr_lock[EMLXS_MSI_MAX_INTRS];
1907 #endif	/* MSI_SUPPORT */
1908 
1909 	uint32_t	heartbeat_timer;
1910 	uint32_t	heartbeat_flag;
1911 	uint32_t	heartbeat_active;
1912 
1913 	/* IOCTL management */
1914 	kmutex_t	ioctl_lock;
1915 	uint32_t	ioctl_flags;
1916 #define	EMLXS_OPEN		0x00000001
1917 #define	EMLXS_OPEN_EXCLUSIVE	0x00000002
1918 
1919 	/* Timer management */
1920 	kcondvar_t	timer_lock_cv;
1921 	kmutex_t	timer_lock;
1922 	timeout_id_t	timer_id;
1923 	uint32_t	timer_tics;
1924 	uint32_t	timer_flags;
1925 #define	EMLXS_TIMER_STARTED	0x0000001
1926 #define	EMLXS_TIMER_BUSY	0x0000002
1927 #define	EMLXS_TIMER_KILL	0x0000004
1928 #define	EMLXS_TIMER_ENDED	0x0000008
1929 
1930 	/* Misc Timers */
1931 	uint32_t	linkup_timer;
1932 	uint32_t	discovery_timer;
1933 	uint32_t	pkt_timer;
1934 
1935 	/* Power Management */
1936 	uint32_t	pm_state;
1937 	/* pm_state */
1938 #define	EMLXS_PM_IN_ATTACH	0x00000001
1939 #define	EMLXS_PM_IN_DETACH	0x00000002
1940 #define	EMLXS_PM_IN_SOL_CB	0x00000010
1941 #define	EMLXS_PM_IN_UNSOL_CB	0x00000020
1942 #define	EMLXS_PM_IN_LINK_RESET	0x00000100
1943 #define	EMLXS_PM_IN_HARD_RESET	0x00000200
1944 #define	EMLXS_PM_SUSPENDED	0x01000000
1945 
1946 	uint32_t	pm_level;
1947 	/* pm_level */
1948 #define	EMLXS_PM_ADAPTER_DOWN	0
1949 #define	EMLXS_PM_ADAPTER_UP	1
1950 
1951 	uint32_t	pm_busy;
1952 	kmutex_t	pm_lock;
1953 	uint8_t		pm_config[PCI_CONFIG_SIZE];
1954 #ifdef IDLE_TIMER
1955 	uint32_t	pm_idle_timer;
1956 	uint32_t	pm_active;	/* Only used by timer */
1957 #endif	/* IDLE_TIMER */
1958 
1959 	/* Loopback management */
1960 	uint32_t	loopback_tics;
1961 	void		*loopback_pkt;
1962 
1963 	/* Event management */
1964 	emlxs_event_queue_t event_queue;
1965 	uint32_t	event_mask;
1966 	uint32_t	event_timer;
1967 	emlxs_dfc_event_t dfc_event[MAX_DFC_EVENTS];
1968 	emlxs_hba_event_t hba_event;
1969 
1970 	/* Parameter management */
1971 	emlxs_config_t	config[NUM_CFG_PARAM];
1972 
1973 	/* Driver stat management */
1974 	kstat_t		*kstat;
1975 	emlxs_stats_t	stats;
1976 
1977 	/* Log management */
1978 	emlxs_msg_log_t	log;
1979 
1980 	/* Port managment */
1981 	uint32_t	vpi_base;
1982 	uint32_t	vpi_max;
1983 	uint32_t	vpi_high;
1984 	uint32_t	num_of_ports;
1985 
1986 	kmutex_t	port_lock;	/* locks port, nodes, rings */
1987 	emlxs_port_t	port[MAX_VPORTS + 1];	/* port specific info */
1988 						/* Last one is for */
1989 						/* NPIV ready test */
1990 
1991 #ifdef DHCHAP_SUPPORT
1992 	kmutex_t	dhc_lock;
1993 	kmutex_t	auth_lock;
1994 	emlxs_auth_cfg_t	auth_cfg;	/* Default auth_cfg. */
1995 						/* Points to list of entries. */
1996 						/* Protected by auth_lock */
1997 	uint32_t	auth_cfg_count;
1998 	emlxs_auth_key_t	auth_key;	/* Default auth_key. */
1999 						/* Points to list of entries. */
2000 						/* Protected by auth_lock */
2001 	uint32_t	auth_key_count;
2002 	uint32_t	rdn_flag;
2003 #endif	/* DHCHAP_SUPPORT */
2004 
2005 	uint16_t	ini_mode;
2006 	uint16_t	tgt_mode;
2007 
2008 #ifdef TEST_SUPPORT
2009 	uint32_t	underrun_counter;
2010 #endif /* TEST_SUPPORT */
2011 
2012 #ifdef MODFW_SUPPORT
2013 	ddi_modhandle_t	fw_modhandle;
2014 #endif /* MODFW_SUPPORT */
2015 
2016 #ifdef DUMP_SUPPORT
2017 	emlxs_file_t	dump_txtfile;
2018 	emlxs_file_t	dump_dmpfile;
2019 	emlxs_file_t	dump_ceefile;
2020 	kmutex_t	dump_lock;
2021 #define	EMLXS_DUMP_LOCK		hba->dump_lock
2022 #define	EMLXS_TXT_FILE		1
2023 #define	EMLXS_DMP_FILE		2
2024 #define	EMLXS_CEE_FILE		3
2025 
2026 #define	EMLXS_DRV_DUMP		0
2027 #define	EMLXS_TEMP_DUMP		1
2028 #define	EMLXS_USER_DUMP		2
2029 
2030 #endif /* DUMP_SUPPORT */
2031 
2032 } emlxs_hba_t;
2033 
2034 #define	EMLXS_SLI_MAP_HDW 		(hba->sli_api.sli_map_hdw)
2035 #define	EMLXS_SLI_UNMAP_HDW		(hba->sli_api.sli_unmap_hdw)
2036 #define	EMLXS_SLI_ONLINE		(hba->sli_api.sli_online)
2037 #define	EMLXS_SLI_OFFLINE		(hba->sli_api.sli_offline)
2038 #define	EMLXS_SLI_HBA_RESET		(hba->sli_api.sli_hba_reset)
2039 #define	EMLXS_SLI_HBA_KILL		(hba->sli_api.sli_hba_kill)
2040 #define	EMLXS_SLI_ISSUE_IOCB_CMD	(hba->sli_api.sli_issue_iocb_cmd)
2041 #define	EMLXS_SLI_ISSUE_MBOX_CMD	(hba->sli_api.sli_issue_mbox_cmd)
2042 #define	EMLXS_SLI_PREP_FCT_IOCB		(hba->sli_api.sli_prep_fct_iocb)
2043 #define	EMLXS_SLI_PREP_FCP_IOCB		(hba->sli_api.sli_prep_fcp_iocb)
2044 #define	EMLXS_SLI_PREP_IP_IOCB		(hba->sli_api.sli_prep_ip_iocb)
2045 #define	EMLXS_SLI_PREP_ELS_IOCB		(hba->sli_api.sli_prep_els_iocb)
2046 #define	EMLXS_SLI_PREP_CT_IOCB		(hba->sli_api.sli_prep_ct_iocb)
2047 #define	EMLXS_SLI_POLL_INTR		(hba->sli_api.sli_poll_intr)
2048 #define	EMLXS_SLI_INTX_INTR		(hba->sli_api.sli_intx_intr)
2049 #define	EMLXS_SLI_MSI_INTR		(hba->sli_api.sli_msi_intr)
2050 #define	EMLXS_SLI_DISABLE_INTR		(hba->sli_api.sli_disable_intr)
2051 #define	EMLXS_SLI_TIMER			(hba->sli_api.sli_timer)
2052 #define	EMLXS_SLI_POLL_ERRATT		(hba->sli_api.sli_poll_erratt)
2053 
2054 #define	EMLXS_HBA_T  1  /* flag emlxs_hba_t is already typedefed */
2055 
2056 #ifdef MSI_SUPPORT
2057 #define	EMLXS_INTR_INIT(_hba, _m)		emlxs_msi_init(_hba, _m)
2058 #define	EMLXS_INTR_UNINIT(_hba)			emlxs_msi_uninit(_hba)
2059 #define	EMLXS_INTR_ADD(_hba)			emlxs_msi_add(_hba)
2060 #define	EMLXS_INTR_REMOVE(_hba)			emlxs_msi_remove(_hba)
2061 #else
2062 #define	EMLXS_INTR_INIT(_hba, _m)		emlxs_intx_init(_hba, _m)
2063 #define	EMLXS_INTR_UNINIT(_hba)			emlxs_intx_uninit(_hba)
2064 #define	EMLXS_INTR_ADD(_hba)			emlxs_intx_add(_hba)
2065 #define	EMLXS_INTR_REMOVE(_hba)			emlxs_intx_remove(_hba)
2066 #endif	/* MSI_SUPPORT */
2067 
2068 
2069 /* Power Management Component */
2070 #define	EMLXS_PM_ADAPTER	0
2071 
2072 
2073 #define	DRV_TIME	(uint32_t)(ddi_get_time() - emlxs_device.drv_timestamp)
2074 
2075 #define	HBA			port->hba
2076 #define	PPORT			hba->port[0]
2077 #define	VPORT(x)		hba->port[x]
2078 #define	EMLXS_TIMER_LOCK	hba->timer_lock
2079 #define	VPD			hba->vpd
2080 #define	CFG			hba->config[0]
2081 #define	LOG			hba->log
2082 #define	EVENTQ			hba->event_queue
2083 #define	EMLXS_MBOX_LOCK		hba->mbox_lock
2084 #define	EMLXS_MBOX_CV		hba->mbox_lock_cv
2085 #define	EMLXS_LINKUP_LOCK	hba->linkup_lock
2086 #define	EMLXS_LINKUP_CV		hba->linkup_lock_cv
2087 #define	EMLXS_TX_CHANNEL_LOCK	hba->channel_tx_lock	/* ring txq lock */
2088 #define	EMLXS_MEMGET_LOCK	hba->memget_lock	/* mempool get lock */
2089 #define	EMLXS_MEMPUT_LOCK	hba->memput_lock	/* mempool put lock */
2090 #define	EMLXS_IOCTL_LOCK	hba->ioctl_lock		/* ioctl lock */
2091 #define	HBASTATS		hba->stats
2092 #define	EMLXS_CMD_RING_LOCK(n)	hba->sli.sli3.ring_cmd_lock[n]
2093 #define	EMLXS_FCTAB_LOCK	hba->iotag_lock
2094 #define	EMLXS_PORT_LOCK		hba->port_lock		/* locks ports, */
2095 							/* nodes, rings */
2096 #define	EMLXS_INTR_LOCK(_id)	hba->intr_lock[_id]	/* locks intr threads */
2097 
2098 #define	EMLXS_PKT_LOCK		port->pkt_lock		/* used for pkt */
2099 							/* polling */
2100 #define	EMLXS_PKT_CV		port->pkt_lock_cv	/* Used for pkt */
2101 							/* polling */
2102 #define	EMLXS_UB_LOCK		port->ub_lock		/* locks unsolicited */
2103 							/* buffer pool */
2104 
2105 /* These SWAPs will swap on any platform */
2106 #define	SWAP32_BUFFER(_b, _c)		emlxs_swap32_buffer(_b, _c)
2107 #define	SWAP32_BCOPY(_s, _d, _c)	emlxs_swap32_bcopy(_s, _d, _c)
2108 
2109 #define	SWAP64(_x)	((((uint64_t)(_x) & 0xFF)<<56) | \
2110 			    (((uint64_t)(_x) & 0xFF00)<<40) | \
2111 			    (((uint64_t)(_x) & 0xFF0000)<<24) | \
2112 			    (((uint64_t)(_x) & 0xFF000000)<<8) | \
2113 			    (((uint64_t)(_x) & 0xFF00000000)>>8) | \
2114 			    (((uint64_t)(_x) & 0xFF0000000000)>>24) | \
2115 			    (((uint64_t)(_x) & 0xFF000000000000)>>40) | \
2116 			    (((uint64_t)(_x) & 0xFF00000000000000)>>56))
2117 
2118 #define	SWAP32(_x)	((((uint32_t)(_x) & 0xFF)<<24) | \
2119 			    (((uint32_t)(_x) & 0xFF00)<<8) | \
2120 			    (((uint32_t)(_x) & 0xFF0000)>>8) | \
2121 			    (((uint32_t)(_x) & 0xFF000000)>>24))
2122 
2123 #define	SWAP16(_x)	((((uint16_t)(_x) & 0xFF)<<8) | \
2124 			    (((uint16_t)(_x) & 0xFF00)>>8))
2125 
2126 #define	SWAP24_LO(_x)	((((uint32_t)(_x) & 0xFF)<<16) | \
2127 			    ((uint32_t)(_x) & 0xFF00FF00) | \
2128 			    (((uint32_t)(_x) & 0x00FF0000)>>16))
2129 
2130 #define	SWAP24_HI(_x)	(((uint32_t)(_x) & 0x00FF00FF) | \
2131 			    (((uint32_t)(_x) & 0x0000FF00)<<16) | \
2132 			    (((uint32_t)(_x) & 0xFF000000)>>16))
2133 
2134 /* These LE_SWAPs will only swap on a LE platform */
2135 #ifdef EMLXS_LITTLE_ENDIAN
2136 #define	LE_SWAP32_BUFFER(_b, _c)	SWAP32_BUFFER(_b, _c)
2137 #define	LE_SWAP32_BCOPY(_s, _d, _c)	SWAP32_BCOPY(_s, _d, _c)
2138 #define	LE_SWAP64(_x)			SWAP64(_x)
2139 #define	LE_SWAP32(_x)			SWAP32(_x)
2140 #define	LE_SWAP16(_x)			SWAP16(_x)
2141 #define	LE_SWAP24_LO(_x)		SWAP24_LO(X)
2142 #define	LE_SWAP24_HI(_x)		SWAP24_HI(X)
2143 
2144 #if (EMLXS_MODREVX == EMLXS_MODREV2X)
2145 #undef	LE_SWAP24_LO
2146 #define	LE_SWAP24_LO(_x)		(_x)
2147 #undef	LE_SWAP24_HI
2148 #define	LE_SWAP24_HI(_x)		(_x)
2149 #endif	/* EMLXS_MODREV2X */
2150 
2151 #else /* BIG ENDIAN */
2152 #define	LE_SWAP32_BUFFER(_b, _c)
2153 #define	LE_SWAP32_BCOPY(_s, _d, _c)	bcopy(_s, _d, _c)
2154 #define	LE_SWAP64(_x)			(_x)
2155 #define	LE_SWAP32(_x)			(_x)
2156 #define	LE_SWAP16(_x)			(_x)
2157 #define	LE_SWAP24_LO(_x)		(_x)
2158 #define	LE_SWAP24_HI(_x)		(_x)
2159 #endif /* EMLXS_LITTLE_ENDIAN */
2160 
2161 /* These BE_SWAPs will only swap on a BE platform */
2162 #ifdef EMLXS_BIG_ENDIAN
2163 #define	BE_SWAP32_BUFFER(_b, _c)	SWAP32_BUFFER(_b, _c)
2164 #define	BE_SWAP32_BCOPY(_s, _d, _c)	SWAP32_BCOPY(_s, _d, _c)
2165 #define	BE_SWAP64(_x)			SWAP64(_x)
2166 #define	BE_SWAP32(_x)			SWAP32(_x)
2167 #define	BE_SWAP16(_x)			SWAP16(_x)
2168 #else /* LITTLE ENDIAN */
2169 #define	BE_SWAP32_BUFFER(_b, _c)
2170 #define	BE_SWAP32_BCOPY(_s, _d, _c)	bcopy(_s, _d, _c)
2171 #define	BE_SWAP64(_x)			(_x)
2172 #define	BE_SWAP32(_x)			(_x)
2173 #define	BE_SWAP16(_x)			(_x)
2174 #endif /* EMLXS_BIG_ENDIAN */
2175 
2176 #ifdef	__cplusplus
2177 }
2178 #endif
2179 
2180 #endif	/* _EMLXS_FC_H */
2181