emlxs_fc.h revision 291a2b48b9adcd7b3666c34e80ba6411929afe7f
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2009 Emulex.  All rights reserved.
24 * Use is subject to License terms.
25 */
26
27
28#ifndef _EMLXS_FC_H
29#define	_EMLXS_FC_H
30
31#ifdef	__cplusplus
32extern "C" {
33#endif
34
35
36/* ULP Patches: */
37/* #define	ULP_PATCH1 -  Obsolete */
38
39/* This patch enables the driver to auto respond to unsolicited LOGO's */
40/* This is needed because ULP is sometimes doesn't reply itself */
41#define	ULP_PATCH2
42
43/* This patch enables the driver to auto respond to unsolicited PRLI's */
44/* This is needed because ULP is known to panic sometimes */
45#define	ULP_PATCH3
46
47/* This patch enables the driver to auto respond to unsolicited PRLO's */
48/* This is needed because ULP is known to panic sometimes */
49#define	ULP_PATCH4
50
51/* This patch enables the driver to fail pkt abort requests */
52#define	ULP_PATCH5
53
54/* This patch enables the driver to generate an RSCN for unsolicited PRLO's */
55/* and LOGO's */
56#define	ULP_PATCH6
57
58/* Sun Disk Array Patches: */
59
60/* This patch enables the driver to fix a residual underrun issue with */
61/* check conditions */
62#define	FCP_UNDERRUN_PATCH1
63
64/* This patch enables the driver to fix a residual underrun issue with */
65/* SCSI inquiry commands */
66#define	FCP_UNDERRUN_PATCH2
67
68/* This patch enables the driver to adjust MAX_RRDY on private loop */
69/* #define	MAX_RRDY_PATCH */
70
71
72typedef struct emlxs_buf
73{
74	fc_packet_t		*pkt;		/* scsi_pkt reference */
75	struct emlxs_port	*port;		/* pointer to port */
76	void			*bmp;		/* Save the buffer pointer */
77						/* list for later use. */
78	struct emlxs_buf	*fc_fwd;	/* Use it by chip_Q */
79	struct emlxs_buf	*fc_bkwd;	/* Use it by chip_Q */
80	struct emlxs_buf	*next;		/* Use it when the iodone */
81	void 			*node;		/* Save node and used by */
82						/* abort */
83	void			*ring;		/* Save ring and used by */
84						/* abort */
85	struct emlxs_buf	 *fpkt;		/* Flush pkt pointer */
86	IOCBQ			iocbq;
87	kmutex_t		mtx;
88	uint32_t		pkt_flags;
89	uint32_t		iotag;		/* iotag for this cmd */
90	uint32_t		ticks;		/* save the timeout ticks */
91						/* for the fc_packet_t */
92	uint32_t		abort_attempts;
93	uint32_t		lun;		/* Save LUN id and used by */
94						/* abort */
95	uint32_t		class;		/* Save class and used by */
96						/* abort */
97	uint32_t		ucmd;		/* Unsolicted command that */
98						/* this packet is responding */
99						/* to, if any */
100	int32_t			flush_count;	/* Valid only in flush pkts */
101	uint32_t		did;
102
103#ifdef SFCT_SUPPORT
104	kmutex_t		fct_mtx;
105	fc_packet_t		*fct_pkt;
106	fct_cmd_t		*fct_cmd;
107
108	uint8_t			fct_type;
109
110#define	EMLXS_FCT_ELS_CMD		0x01	/* Unsolicted */
111#define	EMLXS_FCT_ELS_REQ		0x02	/* Solicited */
112#define	EMLXS_FCT_ELS_RSP		0x04
113#define	EMLXS_FCT_CT_REQ		0x08	/* Solicited */
114#define	EMLXS_FCT_FCP_CMD		0x10	/* Unsolicted */
115#define	EMLXS_FCT_FCP_DATA		0x20
116#define	EMLXS_FCT_FCP_STATUS		0x40
117
118
119	uint8_t			fct_flags;
120
121#define	EMLXS_FCT_SEND_STATUS		0x01
122#define	EMLXS_FCT_ABORT			0x02
123#define	EMLXS_FCT_ABORT_INP		0x04
124#define	EMLXS_FCT_IO_INP		0x08
125#define	EMLXS_FCT_REGISTERED		0x10
126#define	EMLXS_FCT_PLOGI_RECEIVED	0x20
127#define	EMLXS_FCT_FLOGI			0x40
128
129	uint16_t		fct_state;
130
131#define	EMLXS_FCT_FCP_CMD_RECEIVED	1
132#define	EMLXS_FCT_ELS_CMD_RECEIVED	2
133#define	EMLXS_FCT_CMD_POSTED		3
134#define	EMLXS_FCT_CMD_WAITQ		4
135#define	EMLXS_FCT_SEND_ELS_RSP		5
136#define	EMLXS_FCT_SEND_ELS_REQ		6
137#define	EMLXS_FCT_SEND_CT_REQ		7
138#define	EMLXS_FCT_RSP_PENDING		8
139#define	EMLXS_FCT_REQ_PENDING		9
140#define	EMLXS_FCT_REG_PENDING		10
141#define	EMLXS_FCT_REG_COMPLETE		11
142#define	EMLXS_FCT_OWNED			12
143#define	EMLXS_FCT_SEND_FCP_DATA		13
144#define	EMLXS_FCT_SEND_FCP_STATUS	14
145#define	EMLXS_FCT_DATA_PENDING		15
146#define	EMLXS_FCT_STATUS_PENDING	16
147#define	EMLXS_FCT_IOCB_ISSUED		17
148#define	EMLXS_FCT_IOCB_COMPLETE		18
149#define	EMLXS_FCT_PKT_COMPLETE		19
150#define	EMLXS_FCT_PKT_FCPRSP_COMPLETE	20
151#define	EMLXS_FCT_PKT_ELSRSP_COMPLETE	21
152#define	EMLXS_FCT_PKT_ELSCMD_COMPLETE	22
153#define	EMLXS_FCT_PKT_CTCMD_COMPLETE	23
154#define	EMLXS_FCT_REQ_COMPLETE		24
155#define	EMLXS_FCT_SEND_ABORT		25
156#define	EMLXS_FCT_CLOSE_PENDING		26
157#define	EMLXS_FCT_ABORT_PENDING		27
158#define	EMLXS_FCT_ABORT_COMPLETE	28
159#define	EMLXS_FCT_ABORT_DONE		30
160#define	EMLXS_FCT_IO_DONE		32
161
162	stmf_data_buf_t		*fct_buf;
163
164#endif /* SFCT_SUPPORT */
165
166#ifdef SAN_DIAG_SUPPORT
167	hrtime_t		sd_start_time;
168#endif
169} emlxs_buf_t;
170
171
172#if 0
173#define	FCT_IO_TRACE  /* Used to trace IOs */
174#endif
175
176#ifdef FCT_IO_TRACE
177#define	emlxs_fct_state_chg(fct_cmd, sbp, state)	\
178	(sbp)->fct_state = state;			\
179	emlxs_fct_io_trace((sbp)->port, fct_cmd, state)
180#else
181/* define to set fct_state */
182#define	emlxs_fct_state_chg(fct_cmd, sbp, state)	\
183	(sbp)->fct_state = state;
184#endif /* FCT_IO_TRACE */
185
186
187/* pkt_flags */
188#define	PACKET_IN_COMPLETION	0x00000001
189#define	PACKET_IN_TXQ		0x00000002
190#define	PACKET_IN_CHIPQ		0x00000004
191#define	PACKET_IN_DONEQ		0x00000008
192
193#define	PACKET_FCP_RESET	0x00000030
194#define	PACKET_FCP_TGT_RESET	0x00000010
195#define	PACKET_FCP_LUN_RESET	0x00000020
196#define	PACKET_POLLED		0x00000040
197
198#ifdef EMLXS_I386
199#define	PACKET_FCP_SWAPPED	0x00000100
200#define	PACKET_ELS_SWAPPED	0x00000200
201#define	PACKET_CT_SWAPPED	0x00000400
202#define	PACKET_CSP_SWAPPED	0x00000800
203#endif	/* EMLXS_I386 */
204
205#define	PACKET_STALE		0x00001000
206
207#define	PACKET_IN_TIMEOUT	0x00010000
208#define	PACKET_IN_FLUSH		0x00020000
209#define	PACKET_IN_ABORT		0x00040000
210#define	PACKET_XRI_CLOSED	0x00080000	/* An XRI abort or */
211						/* XRI close was issued */
212
213#define	PACKET_CHIP_COMP	0x00100000
214#define	PACKET_COMPLETED	0x00200000
215#define	PACKET_RETURNED		0x00400000
216
217#define	PACKET_STATE_VALID	0x01000000
218#define	PACKET_FCP_RSP_VALID	0x02000000
219#define	PACKET_ELS_RSP_VALID	0x04000000
220#define	PACKET_CT_RSP_VALID	0x08000000
221
222#define	PACKET_DELAY_REQUIRED	0x10000000
223#define	PACKET_ALLOCATED	0x40000000
224#define	PACKET_VALID		0x80000000
225
226
227#define	STALE_PACKET		((emlxs_buf_t *)0xFFFFFFFF)
228
229
230/*
231 * From fc_error.h pkt_reason (except for state = NPORT_RJT, FABRIC_RJT,
232 * NPORT_BSY, FABRIC_BSY, LS_RJT, BA_RJT, FS_RJT)
233 *
234 * FCA unique error codes can begin after FC_REASON_FCA_UNIQUE.
235 * Each FCA defines its own set with values greater >= 0x7F
236 */
237#define	FC_REASON_FCA_DEFINED   0x100
238
239
240/*
241 * Device VPD save area
242 */
243
244typedef struct emlxs_vpd
245{
246	uint32_t	biuRev;
247	uint32_t	smRev;
248	uint32_t	smFwRev;
249	uint32_t	endecRev;
250	uint16_t	rBit;
251	uint8_t		fcphHigh;
252	uint8_t		fcphLow;
253	uint8_t		feaLevelHigh;
254	uint8_t		feaLevelLow;
255
256	uint32_t	postKernRev;
257	char		postKernName[32];
258
259	uint32_t	opFwRev;
260	char		opFwName[32];
261	char		opFwLabel[32];
262
263	uint32_t	sli1FwRev;
264	char		sli1FwName[32];
265	char		sli1FwLabel[32];
266
267	uint32_t	sli2FwRev;
268	char		sli2FwName[32];
269	char		sli2FwLabel[32];
270
271	uint32_t	sli3FwRev;
272	char		sli3FwName[32];
273	char		sli3FwLabel[32];
274
275	uint32_t	sli4FwRev;
276	char		sli4FwName[32];
277	char		sli4FwLabel[32];
278
279	char		fw_version[32];
280	char		fw_label[32];
281
282	char		fcode_version[32];
283	char		boot_version[32];
284
285	char		serial_num[32];
286	char		part_num[32];
287	char		port_num[20];
288	char		eng_change[32];
289	char		manufacturer[80];
290	char		model[80];
291	char		model_desc[256];
292	char		prog_types[256];
293	char		id[80];
294
295	uint32_t	port_index;
296	uint8_t		link_speed;
297} emlxs_vpd_t;
298
299
300typedef struct emlxs_queue
301{
302	uint8_t		*q_first;	/* queue first element */
303	uint8_t		*q_last;	/* queue last element */
304	uint16_t	q_cnt;	/* current length of queue */
305	uint16_t	q_max;	/* max length queue can get */
306} emlxs_queue_t;
307typedef emlxs_queue_t Q;
308
309
310
311/*
312 * This structure is used when allocating a buffer pool.
313 * Note: this should be identical to gasket buf_info (fldl.h).
314 */
315typedef struct emlxs_buf_info
316{
317	int32_t		size;	/* Specifies the number of bytes to allocate. */
318	int32_t		align;	/* The desired address boundary. */
319
320	int32_t		flags;
321
322#define	FC_MBUF_DMA		0x01	/* blocks are for DMA */
323#define	FC_MBUF_PHYSONLY	0x02	/* For malloc - map a given virtual */
324					/* address to physical address (skip */
325					/* the malloc). */
326					/* For free - just unmap the given */
327					/* physical address (skip the free). */
328#define	FC_MBUF_IOCTL		0x04	/* called from dfc_ioctl */
329#define	FC_MBUF_UNLOCK		0x08	/* called with driver unlocked */
330#define	FC_MBUF_SNGLSG		0x10	/* allocate a single contiguous */
331					/* physical memory */
332#define	FC_MBUF_DMA32		0x20
333
334	uint64_t	phys;		/* specifies physical buffer pointer */
335	void		*virt;		/* specifies virtual buffer pointer */
336	void		*data_handle;
337	void		*dma_handle;
338} emlxs_buf_info_t;
339typedef emlxs_buf_info_t MBUF_INFO;
340
341
342
343#ifdef SLI3_SUPPORT
344
345#define	EMLXS_MAX_HBQ   	16	/* Max HBQs handled by firmware */
346#define	EMLXS_ELS_HBQ_ID	0
347#define	EMLXS_IP_HBQ_ID		1
348#define	EMLXS_CT_HBQ_ID		2
349#define	EMLXS_FCT_HBQ_ID	3
350
351#ifdef SFCT_SUPPORT
352#define	EMLXS_NUM_HBQ		4	/* Number of HBQs supported by driver */
353#else
354#define	EMLXS_NUM_HBQ		3	/* Number of HBQs supported by driver */
355#endif /* SFCT_SUPPORT */
356
357#endif	/* SLI3_SUPPORT */
358
359
360
361/* Structure used to access adapter rings */
362typedef struct emlxs_ring
363{
364	IOCBQ		*fc_iocbhd;		/* ptr to head iocb rsp list */
365						/* for ring */
366	IOCBQ		*fc_iocbtl;		/* ptr to tail iocb rsp list */
367						/* for ring */
368	void		*fc_cmdringaddr;	/* virtual offset for cmd */
369						/* rings */
370	void		*fc_rspringaddr;	/* virtual offset for rsp */
371						/* rings */
372
373	emlxs_buf_t	**fc_table;		/* sc_buf pointers indexed by */
374						/* iotag */
375	uint8_t		*fc_mpon;		/* index ptr for match */
376						/* structure */
377	uint8_t		*fc_mpoff;		/* index ptr for match */
378						/* structure */
379	struct emlxs_hba *hba;	/* ptr to hba for ring */
380
381	kmutex_t	rsp_lock;
382	IOCBQ		*rsp_head;	/* deferred completion head */
383	IOCBQ		*rsp_tail;	/* deferred completion tail */
384	emlxs_thread_t  intr_thread;
385
386	uint8_t		fc_numCiocb;		/* number of command iocb's */
387						/* per ring */
388	uint8_t		fc_numRiocb;		/* number of response iocb's */
389						/* per ring */
390	uint8_t		fc_rspidx;		/* current index in response */
391						/* ring */
392	uint8_t		fc_cmdidx;		/* current index in command */
393						/* ring */
394	uint8_t		fc_port_rspidx;
395	uint8_t		fc_port_cmdidx;
396	uint8_t		ringno;
397
398	uint16_t	fc_missbufcnt;		/* buf cnt we need to repost */
399	uint16_t	fc_iotag;		/* used to identify I/Os */
400	uint16_t	fc_abort_iotag;		/* used to identify Abort or */
401						/* close requests */
402	uint16_t	max_iotag;
403
404	uint32_t	timeout;
405
406	/* Protected by EMLXS_RINGTX_LOCK */
407	emlxs_queue_t	nodeq;			/* Node service queue */
408} emlxs_ring_t;
409typedef emlxs_ring_t RING;
410
411
412#ifdef SAN_DIAG_SUPPORT
413/*
414 * Although right now it's just 1 field, SAN Diag anticipates that this
415 * structure will grow in the future.
416 */
417typedef struct sd_timestat_level0 {
418	int		count;
419} sd_timestat_level0_t;
420#endif
421
422typedef struct emlxs_node
423{
424	struct emlxs_node	*nlp_list_next;
425	struct emlxs_node	*nlp_list_prev;
426
427	NAME_TYPE		nlp_portname;	/* port name */
428	NAME_TYPE		nlp_nodename;	/* node name */
429
430	uint32_t		nlp_DID;	/* fibre channel D_ID */
431	uint32_t		nlp_oldDID;
432
433	uint16_t		nlp_Rpi;	/* login id returned by */
434						/* REG_LOGIN */
435	uint16_t		nlp_Xri;	/* login id returned by */
436						/* REG_LOGIN */
437
438	uint8_t			nlp_fcp_info;	/* Remote class info */
439
440	/* nlp_fcp_info */
441#define	NLP_FCP_TGT_DEVICE	0x10	/* FCP TGT device */
442#define	NLP_FCP_INI_DEVICE	0x20	/* FCP Initiator device */
443#define	NLP_FCP_2_DEVICE	0x40	/* FCP-2 TGT device */
444#define	NLP_EMLX_VPORT		0x80    /* Virtual port */
445
446	uint32_t		nlp_tag;	/* Tag used by port_offline */
447	uint32_t		flag;
448
449#define	NODE_POOL_ALLOCATED 	0x00000001
450
451	SERV_PARM		sparm;
452
453	/* Protected by EMLXS_RINGTX_LOCK */
454	uint32_t		nlp_active;	/* Node active flag */
455	uint32_t		nlp_base;
456	uint32_t		nlp_flag[MAX_RINGS];	/* Node level ring */
457							/* flags */
458
459	/* nlp_flag */
460#define	NLP_CLOSED		0x1
461#define	NLP_OFFLINE		0x2
462#define	NLP_RPI_XRI		0x4
463
464	uint32_t		nlp_tics[MAX_RINGS];	/* gate timeout */
465	emlxs_queue_t		nlp_tx[MAX_RINGS];	/* Transmit Q head */
466	emlxs_queue_t		nlp_ptx[MAX_RINGS];	/* Priority transmit */
467							/* Queue head */
468	void			*nlp_next[MAX_RINGS];	/* Service Request */
469							/* Queue pointer used */
470							/* when node needs */
471							/* servicing */
472#ifdef DHCHAP_SUPPORT
473	emlxs_node_dhc_t	node_dhc;
474#endif	/* DHCHAP_SUPPORT */
475
476#ifdef SAN_DIAG_SUPPORT
477	sd_timestat_level0_t	sd_dev_bucket[SD_IO_LATENCY_MAX_BUCKETS];
478#endif
479} emlxs_node_t;
480typedef emlxs_node_t NODELIST;
481
482
483
484#define	NADDR_LEN	6	/* MAC network address length */
485typedef struct emlxs_fcip_nethdr
486{
487	NAME_TYPE	fc_destname;	/* destination port name */
488	NAME_TYPE	fc_srcname;	/* source port name */
489} emlxs_fcip_nethdr_t;
490typedef emlxs_fcip_nethdr_t NETHDR;
491
492
493#define	MEM_NLP		0	/* memory segment to hold node list entries */
494#define	MEM_IOCB	1	/* memory segment to hold iocb commands */
495#define	MEM_MBOX	2	/* memory segment to hold mailbox cmds  */
496#define	MEM_BPL		3	/* and to hold buffer ptr lists - SLI2   */
497#define	MEM_BUF		4	/* memory segment to hold buffer data   */
498#define	MEM_ELSBUF	4	/* memory segment to hold buffer data   */
499#define	MEM_IPBUF	5	/* memory segment to hold IP buffer data */
500#define	MEM_CTBUF	6	/* memory segment to hold CT buffer data */
501#define	MEM_FCTBUF	7	/* memory segment to hold FCT buffer data */
502
503#ifdef SFCT_SUPPORT
504#define	FC_MAX_SEG	8
505#else
506#define	FC_MAX_SEG	7
507#endif /* SFCT_SUPPORT */
508
509
510/* A BPL entry is 12 bytes. Subtract 2 for command and response buffers */
511#define	BPL_TO_SGLLEN(_bpl)   ((_bpl/12)-2)
512
513#define	MEM_BPL_SIZE		1024  /* Default size */
514
515#ifdef EMLXS_I386
516#define	EMLXS_SGLLEN		BPL_TO_SGLLEN(MEM_BPL_SIZE)
517#else	/* EMLXS_SPARC */
518#define	EMLXS_SGLLEN		1
519#endif	/* EMLXS_I386 */
520
521#define	MEM_BUF_SIZE		1024
522#define	MEM_BUF_COUNT		64
523
524#define	MEM_ELSBUF_SIZE   	MEM_BUF_SIZE
525#define	MEM_ELSBUF_COUNT  	hba->max_nodes
526#define	MEM_IPBUF_SIZE  	65535
527#define	MEM_IPBUF_COUNT		60
528#define	MEM_CTBUF_SIZE		MAX_CT_PAYLOAD	/* (1024*320) */
529#define	MEM_CTBUF_COUNT		8
530#define	MEM_FCTBUF_SIZE  	65535
531#define	MEM_FCTBUF_COUNT	128
532
533#define	MEM_SEG_MASK		0xff	/* mask used to mask off the */
534					/* priority bit */
535#define	MEM_PRI			0x100	/* Priority bit: set to exceed */
536					/* low water */
537
538
539
540typedef struct emlxs_memseg
541{
542	uint8_t			*fc_memget_ptr;
543	uint8_t			*fc_memget_end;
544	uint8_t			*fc_memput_ptr;
545	uint8_t			*fc_memput_end;
546
547	uint8_t			*fc_memstart_virt;	/* beginning address */
548							/* of memory block */
549	uint64_t		fc_memstart_phys;	/* beginning address */
550							/* of memory block */
551	ddi_dma_handle_t	fc_mem_dma_handle;
552	ddi_acc_handle_t	fc_mem_dat_handle;
553	uint32_t		fc_total_memsize;
554	uint32_t		fc_memsize;		/* size of mem blks */
555	uint32_t		fc_numblks;		/* no of mem blks */
556	uint32_t		fc_memget_cnt;		/* no of mem get blks */
557	uint32_t		fc_memput_cnt;		/* no of mem put blks */
558	uint32_t		fc_memflag;		/* what to do when */
559							/* list is exhausted */
560	uint32_t		fc_lowmem;		/* low water mark */
561							/* used w/MEM_PRI */
562} emlxs_memseg_t;
563typedef emlxs_memseg_t MEMSEG;
564
565
566#define	FC_MEM_ERR	1	/* return error memflag */
567#define	FC_MEM_GETMORE	2	/* get more memory memflag */
568#define	FC_MEM_DMA	4	/* blocks are for DMA */
569#define	FC_MEM_LOWHIT	8	/* low water mark was hit */
570#define	FC_MEMPAD	16	/* offset used for a FC_MEM_DMA buffer */
571
572/* Board stat counters */
573typedef struct emlxs_stats
574{
575	uint32_t	LinkUp;
576	uint32_t	LinkDown;
577	uint32_t	LinkEvent;
578	uint32_t	LinkMultiEvent;
579
580	uint32_t	MboxIssued;
581	uint32_t	MboxCompleted;	/* MboxError + MbxGood */
582	uint32_t	MboxGood;
583	uint32_t	MboxError;
584	uint32_t	MboxBusy;
585	uint32_t	MboxInvalid;
586
587	uint32_t	IocbIssued[MAX_RINGS];
588	uint32_t	IocbReceived[MAX_RINGS];
589	uint32_t	IocbTxPut[MAX_RINGS];
590	uint32_t	IocbTxGet[MAX_RINGS];
591	uint32_t	IocbRingFull[MAX_RINGS];
592	uint32_t	IocbThrottled;
593
594	uint32_t	IntrEvent[8];
595
596	uint32_t	FcpIssued;
597	uint32_t	FcpCompleted;	/* FcpGood + FcpError */
598	uint32_t	FcpGood;
599	uint32_t	FcpError;
600
601	uint32_t	FcpEvent;	/* FcpStray + FcpCompleted */
602	uint32_t	FcpStray;
603#ifdef SFCT_SUPPORT
604	uint32_t	FctRingEvent;
605	uint32_t	FctRingError;
606	uint32_t	FctRingDropped;
607#endif /* SFCT_SUPPORT */
608
609	uint32_t	ElsEvent;	/* ElsStray + ElsCmplt (cmd + rsp) */
610	uint32_t	ElsStray;
611
612	uint32_t	ElsCmdIssued;
613	uint32_t	ElsCmdCompleted;	/* ElsCmdGood + ElsCmdError */
614	uint32_t	ElsCmdGood;
615	uint32_t	ElsCmdError;
616
617	uint32_t	ElsRspIssued;
618	uint32_t	ElsRspCompleted;
619
620	uint32_t	ElsRcvEvent;	/* ElsRcvErr + ElsRcvDrop + ElsCmdRcv */
621	uint32_t	ElsRcvError;
622	uint32_t	ElsRcvDropped;
623	uint32_t	ElsCmdReceived;	/* ElsRscnRcv + ElsPlogiRcv + ... */
624	uint32_t	ElsRscnReceived;
625	uint32_t	ElsFlogiReceived;
626	uint32_t	ElsPlogiReceived;
627	uint32_t	ElsPrliReceived;
628	uint32_t	ElsPrloReceived;
629	uint32_t	ElsLogoReceived;
630	uint32_t	ElsAdiscReceived;
631	uint32_t	ElsAuthReceived;
632	uint32_t	ElsGenReceived;
633
634	uint32_t	CtEvent;	/* CtStray + CtCompleted (cmd + rsp) */
635	uint32_t	CtStray;
636
637	uint32_t	CtCmdIssued;
638	uint32_t	CtCmdCompleted;	/* CtCmdGood + CtCmdError */
639	uint32_t	CtCmdGood;
640	uint32_t	CtCmdError;
641
642	uint32_t	CtRspIssued;
643	uint32_t	CtRspCompleted;
644
645	uint32_t	CtRcvEvent;	/* CtRcvError + CtRcvDrop + CtCmdRcvd */
646	uint32_t	CtRcvError;
647	uint32_t	CtRcvDropped;
648	uint32_t	CtCmdReceived;
649
650	uint32_t	IpEvent;	/* IpStray + IpSeqCmpl + IpBcastCmpl */
651	uint32_t	IpStray;
652
653	uint32_t	IpSeqIssued;
654	uint32_t	IpSeqCompleted;	/* IpSeqGood + IpSeqError */
655	uint32_t	IpSeqGood;
656	uint32_t	IpSeqError;
657
658	uint32_t	IpBcastIssued;
659	uint32_t	IpBcastCompleted;	/* IpBcastGood + IpBcastError */
660	uint32_t	IpBcastGood;
661	uint32_t	IpBcastError;
662
663	uint32_t	IpRcvEvent;	/* IpDrop + IpSeqRcv + IpBcastRcv */
664	uint32_t	IpDropped;
665	uint32_t	IpSeqReceived;
666	uint32_t	IpBcastReceived;
667
668	uint32_t	IpUbPosted;
669	uint32_t	ElsUbPosted;
670	uint32_t	CtUbPosted;
671#ifdef SFCT_SUPPORT
672	uint32_t	FctUbPosted;
673#endif /* SFCT_SUPPORT */
674
675	uint32_t	ResetTime;	/* Time of last reset */
676} emlxs_stats_t;
677
678
679#define	FC_MAX_ADPTMSG   (8*28)	/* max size of a msg from adapter */
680
681#define	EMLXS_NUM_THREADS	8
682#define	EMLXS_MIN_TASKS		8
683#define	EMLXS_MAX_TASKS		8
684
685#define	EMLXS_NUM_HASH_QUES	32
686#define	EMLXS_DID_HASH(x)	((x) & (EMLXS_NUM_HASH_QUES - 1))
687
688
689/* pkt_tran_flag */
690#define	FC_TRAN_COMPLETED	0x8000
691
692
693typedef struct emlxs_dfc_event
694{
695	uint32_t	pid;
696	uint32_t	event;
697	uint32_t	last_id;
698
699	void		*dataout;
700	uint32_t	size;
701	uint32_t	mode;
702} emlxs_dfc_event_t;
703
704
705typedef struct emlxs_hba_event
706{
707	uint32_t	last_id;
708	uint32_t	new;
709	uint32_t	missed;
710} emlxs_hba_event_t;
711
712
713#ifdef SFCT_SUPPORT
714
715#define	TGTPORTSTAT			port->fct_stat
716
717/*
718 * FctP2IOXcnt will count IOs by their fcpDL. Counters
719 * are for buckets of various power of 2 sizes.
720 * Bucket 0  <  512  > 0
721 * Bucket 1  >= 512  < 1024
722 * Bucket 2  >= 1024 < 2048
723 * Bucket 3  >= 2048 < 4096
724 * Bucket 4  >= 4096 < 8192
725 * Bucket 5  >= 8192 < 16K
726 * Bucket 6  >= 16K  < 32K
727 * Bucket 7  >= 32K  < 64K
728 * Bucket 8  >= 64K  < 128K
729 * Bucket 9  >= 128K < 256K
730 * Bucket 10 >= 256K < 512K
731 * Bucket 11 >= 512K < 1MB
732 * Bucket 12 >= 1MB  < 2MB
733 * Bucket 13 >= 2MB  < 4MB
734 * Bucket 14 >= 4MB  < 8MB
735 * Bucket 15 >= 8MB
736 */
737#define	MAX_TGTPORT_IOCNT  16
738
739
740/*
741 * These routines will bump the right counter, based on
742 * the size of the IO inputed, with the least number of
743 * comparisions.  A max of 5 comparisions is only needed
744 * to classify the IO in one of 16 ranges. A binary search
745 * to locate the high bit in the size is used.
746 */
747#define	emlxs_bump_rdioctr(port, cnt) \
748{ \
749	/* Use binary search to find the first high bit */ \
750	if (cnt & 0xffff0000) { \
751		if (cnt & 0xff800000) { \
752			TGTPORTSTAT.FctP2IORcnt[15]++; \
753		} \
754		else { \
755			/* It must be 0x007f0000 */ \
756			if (cnt & 0x00700000) { \
757				if (cnt & 0x00400000) { \
758					TGTPORTSTAT.FctP2IORcnt[14]++; \
759				} \
760				else { \
761					/* it must be 0x00300000 */ \
762					if (cnt & 0x00200000) { \
763						TGTPORTSTAT.FctP2IORcnt[13]++; \
764					} \
765					else { \
766						/* It must be 0x00100000 */ \
767						TGTPORTSTAT.FctP2IORcnt[12]++; \
768					} \
769				} \
770			} \
771			else { \
772				/* It must be 0x000f0000 */ \
773				if (cnt & 0x000c0000) {	\
774					if (cnt & 0x00080000) {	\
775						TGTPORTSTAT.FctP2IORcnt[11]++; \
776					} \
777					else { \
778						/* It must be 0x00040000 */ \
779						TGTPORTSTAT.FctP2IORcnt[10]++; \
780					} \
781				} \
782				else { \
783					/* It must be 0x00030000 */ \
784					if (cnt & 0x00020000) {	\
785						TGTPORTSTAT.FctP2IORcnt[9]++; \
786					} \
787					else { \
788						/* It must be 0x00010000 */ \
789						TGTPORTSTAT.FctP2IORcnt[8]++; \
790					} \
791				} \
792			} \
793		} \
794	} \
795	else { \
796		if (cnt & 0x0000fe00) { \
797			if (cnt & 0x0000f000) { \
798				if (cnt & 0x0000c000) { \
799					if (cnt & 0x00008000) { \
800						TGTPORTSTAT.FctP2IORcnt[7]++; \
801					} \
802					else { \
803						/* It must be 0x00004000 */ \
804						TGTPORTSTAT.FctP2IORcnt[6]++; \
805					} \
806				} \
807				else { \
808					/* It must be 0x00000300 */ \
809					if (cnt & 0x00000200) { \
810						TGTPORTSTAT.FctP2IORcnt[5]++; \
811					} \
812					else { \
813						/* It must be 0x00000100 */ \
814						TGTPORTSTAT.FctP2IORcnt[4]++; \
815					} \
816				} \
817			} \
818			else { \
819				/* It must be 0x00000e00 */ \
820				if (cnt & 0x00000800) { \
821					TGTPORTSTAT.FctP2IORcnt[3]++; \
822				} \
823				else { \
824					/* It must be 0x00000600 */ \
825					if (cnt & 0x00000400) { \
826						TGTPORTSTAT.FctP2IORcnt[2]++; \
827					} \
828					else { \
829						/* It must be 0x00000200 */ \
830						TGTPORTSTAT.FctP2IORcnt[1]++; \
831					} \
832				} \
833			} \
834		} \
835		else { \
836			/* It must be 0x000001ff */ \
837			TGTPORTSTAT.FctP2IORcnt[0]++; \
838		} \
839	} \
840}
841
842
843#define	emlxs_bump_wrioctr(port, cnt) \
844{ \
845/* Use binary search to find the first high bit */ \
846	if (cnt & 0xffff0000) { \
847		if (cnt & 0xff800000) { \
848			TGTPORTSTAT.FctP2IOWcnt[15]++; \
849		} \
850		else { \
851			/* It must be 0x007f0000 */ \
852			if (cnt & 0x00700000) { \
853				if (cnt & 0x00400000) { \
854					TGTPORTSTAT.FctP2IOWcnt[14]++; \
855				} \
856				else { \
857					/* It must be 0x00300000 */ \
858					if (cnt & 0x00200000) { \
859						TGTPORTSTAT.FctP2IOWcnt[13]++; \
860					} \
861					else { \
862						/* It must be 0x00100000 */ \
863						TGTPORTSTAT.FctP2IOWcnt[12]++; \
864					} \
865				} \
866			} \
867			else { \
868				/* It must be 0x000f0000 */ \
869				if (cnt & 0x000c0000) { \
870					if (cnt & 0x00080000) { \
871						TGTPORTSTAT.FctP2IOWcnt[11]++; \
872					} \
873					else { \
874						/* it must be 0x00040000 */ \
875						TGTPORTSTAT.FctP2IOWcnt[10]++; \
876					} \
877				} \
878				else { \
879					/* It must be 0x00030000 */ \
880					if (cnt & 0x00020000) { \
881						TGTPORTSTAT.FctP2IOWcnt[9]++; \
882					} \
883					else { \
884						/* It must be 0x00010000 */ \
885						TGTPORTSTAT.FctP2IOWcnt[8]++; \
886					} \
887				} \
888			} \
889		} \
890	} \
891	else { \
892		if (cnt & 0x0000fe00) { \
893			if (cnt & 0x0000f000) { \
894				if (cnt & 0x0000c000) { \
895					if (cnt & 0x00008000) { \
896						TGTPORTSTAT.FctP2IOWcnt[7]++; \
897					} \
898					else { \
899						/* It must be 0x00004000 */ \
900						TGTPORTSTAT.FctP2IOWcnt[6]++; \
901					} \
902				} \
903				else { \
904					/* It must be 0x00000300 */ \
905					if (cnt & 0x00000200) { \
906						TGTPORTSTAT.FctP2IOWcnt[5]++; \
907					} \
908					else { \
909						/* It must be 0x00000100 */ \
910						TGTPORTSTAT.FctP2IOWcnt[4]++; \
911					} \
912				} \
913			} \
914			else { \
915				/* It must be 0x00000e00 */ \
916				if (cnt & 0x00000800) { \
917					TGTPORTSTAT.FctP2IOWcnt[3]++; \
918				} \
919				else { \
920					/* It must be 0x00000600 */ \
921					if (cnt & 0x00000400) { \
922						TGTPORTSTAT.FctP2IOWcnt[2]++; \
923					} \
924					else { \
925						/* It must be 0x00000200 */ \
926						TGTPORTSTAT.FctP2IOWcnt[1]++; \
927					} \
928				} \
929			} \
930		} \
931		else { \
932			/* It must be 0x000001ff */ \
933			TGTPORTSTAT.FctP2IOWcnt[0]++; \
934		} \
935	} \
936}
937
938typedef struct emlxs_tgtport_stat
939{
940	/* IO counters */
941	uint64_t	FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */
942	uint64_t	FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads  */
943	uint64_t	FctIOCmdCnt;			/* Other, ie TUR */
944	uint64_t	FctCmdReceived;			/* total IOs */
945	uint64_t	FctReadBytes;			/* total read bytes */
946	uint64_t	FctWriteBytes;			/* total write bytes */
947
948	/* IOCB handling counters */
949	uint64_t	FctEvent;	/* FctStray + FctCompleted */
950	uint64_t	FctCompleted;	/* FctCmplGood + FctCmplError */
951	uint64_t	FctCmplGood;
952
953	uint32_t	FctCmplError;
954	uint32_t	FctStray;
955
956	/* Fct event counters */
957	uint32_t	FctRcvDropped;
958	uint32_t	FctOverQDepth;
959	uint32_t	FctOutstandingIO;
960	uint32_t	FctFailedPortRegister;
961	uint32_t	FctPortRegister;
962	uint32_t	FctPortDeregister;
963
964	uint32_t	FctAbortSent;
965	uint32_t	FctNoBuffer;
966	uint32_t	FctScsiStatusErr;
967	uint32_t	FctScsiQfullErr;
968	uint32_t	FctScsiResidOver;
969	uint32_t	FctScsiResidUnder;
970	uint32_t	FctScsiSenseErr;
971
972	uint32_t	FctFiller1;
973} emlxs_tgtport_stat_t;
974
975#ifdef FCT_IO_TRACE
976#define	MAX_IO_TRACE	67
977typedef struct emlxs_iotrace
978{
979	fct_cmd_t	*fct_cmd;
980	uint32_t	xri;
981	uint8_t		marker;  /* 0xff */
982	uint8_t		trc[MAX_IO_TRACE]; /* trc[0] = index */
983} emlxs_iotrace_t;
984#endif /* FCT_IO_TRACE */
985#endif /* SFCT_SUPPORT */
986
987
988/*
989 *     Port Information Data Structure
990 */
991
992typedef struct emlxs_port
993{
994	struct emlxs_hba	*hba;
995
996	/* Virtual port management */
997	uint32_t		vpi;
998	uint32_t		flag;
999#define	EMLXS_PORT_ENABLE		0x00000001
1000#define	EMLXS_PORT_BOUND		0x00000002
1001
1002#define	EMLXS_PORT_REGISTERED		0x00010000	/* VPI registered */
1003#define	EMLXS_PORT_IP_UP		0x00000010
1004#define	EMLXS_PORT_CONFIG		0x00000020
1005#define	EMLXS_PORT_RESTRICTED		0x00000040	/* Restrict logins */
1006							/* flag */
1007#define	EMLXS_PORT_FLOGI_CMPL		0x00000080	/* Fabric login */
1008							/* completed */
1009
1010#define	EMLXS_PORT_RESET_MASK		0x0000FFFF	/* Flags to keep */
1011							/* across hard reset */
1012#define	EMLXS_PORT_LINKDOWN_MASK	0xFFFFFFFF	/* Flags to keep */
1013							/* across link reset */
1014
1015	uint32_t		options;
1016#define	EMLXS_OPT_RESTRICT		0x00000001	/* Force restricted */
1017							/* logins */
1018#define	EMLXS_OPT_UNRESTRICT		0x00000002	/* Force Unrestricted */
1019							/* logins */
1020#define	EMLXS_OPT_RESTRICT_MASK		0x00000003
1021
1022
1023	/* FC world wide names */
1024	NAME_TYPE		wwnn;
1025	NAME_TYPE		wwpn;
1026	char			snn[256];
1027	char			spn[256];
1028
1029	/* Common service paramters */
1030	SERV_PARM		sparam;
1031	SERV_PARM		fabric_sparam;
1032
1033	/* fc_id management */
1034	uint32_t		did;
1035	uint32_t		prev_did;
1036
1037	/* FC_AL management */
1038	uint8_t			lip_type;
1039	uint8_t			alpa_map[128];
1040
1041	/* Node management */
1042	emlxs_node_t		node_base;
1043	uint32_t		node_count;
1044	krwlock_t		node_rwlock;
1045	emlxs_node_t		*node_table[EMLXS_NUM_HASH_QUES];
1046
1047	/* Polled packet management */
1048	kcondvar_t		pkt_lock_cv;	/* pkt polling */
1049	kmutex_t		pkt_lock;	/* pkt polling */
1050
1051	/* ULP */
1052	uint32_t		ulp_statec;
1053	void			(*ulp_statec_cb) ();	/* Port state change */
1054							/* callback routine */
1055	void			(*ulp_unsol_cb) ();	/* unsolicited event */
1056							/* callback routine */
1057	opaque_t		ulp_handle;
1058
1059	/* ULP unsolicited buffers */
1060	kmutex_t		ub_lock;
1061	uint32_t		ub_count;
1062	emlxs_unsol_buf_t	*ub_pool;
1063	uint32_t		ub_post[MAX_RINGS];
1064	uint32_t		ub_timer;
1065
1066	emlxs_ub_priv_t		*ub_wait_head;	/* Unsolicited IO received */
1067						/* before link up */
1068	emlxs_ub_priv_t		*ub_wait_tail;	/* Unsolicited IO received */
1069						/* before link up */
1070
1071
1072#ifdef DHCHAP_SUPPORT
1073	emlxs_port_dhc_t	port_dhc;
1074#endif	/* DHCHAP_SUPPORT */
1075
1076	uint16_t		ini_mode;
1077	uint16_t		tgt_mode;
1078
1079#ifdef SFCT_SUPPORT
1080
1081#define	FCT_BUF_COUNT_512		256
1082#define	FCT_BUF_COUNT_8K		128
1083#define	FCT_BUF_COUNT_64K		64
1084#define	FCT_BUF_COUNT_128K		64
1085#define	FCT_MAX_BUCKETS			16
1086#define	FCT_DMEM_MAX_BUF_SIZE		131072   /* 128K */
1087#define	FCT_DMEM_MAX_BUF_SEGMENT	8388608  /* 8M */
1088
1089	struct emlxs_fct_dmem_bucket dmem_bucket[FCT_MAX_BUCKETS];
1090	int			fct_queue_depth;
1091#define	EMLXS_FCT_DFLT_QDEPTH   64
1092
1093	char			cfd_name[24];
1094	stmf_port_provider_t	*port_provider;
1095	fct_local_port_t	*fct_port;
1096	uint32_t		fct_flags;
1097
1098#define	FCT_STATE_PORT_ONLINE	0x00000001
1099#define	FCT_STATE_NOT_ACKED	0x00000002
1100#define	FCT_STATE_LINK_UP	0x00000010
1101
1102	emlxs_tgtport_stat_t	fct_stat;
1103
1104	/* Used to save fct_cmd for deferred unsol ELS commands, except FLOGI */
1105	emlxs_buf_t		*fct_wait_head;
1106	emlxs_buf_t		*fct_wait_tail;
1107
1108	/* Used to save context for deferred unsol FLOGIs */
1109	fct_flogi_xchg_t	fx;
1110	uint32_t		fx_context;
1111#ifdef FCT_IO_TRACE
1112	emlxs_iotrace_t		*iotrace;
1113	uint16_t		iotrace_cnt;
1114	uint16_t		iotrace_index;
1115	kmutex_t		iotrace_mtx;
1116#endif /* FCT_IO_TRACE */
1117
1118#endif /* SFCT_SUPPORT */
1119
1120#ifdef SAN_DIAG_SUPPORT
1121	uint8_t			sd_io_latency_state;
1122#define	SD_INVALID	0x00
1123#define	SD_COLLECTING	0x01
1124#define	SD_STOPPED	0x02
1125
1126	/* SD event management list */
1127	uint32_t		sd_reg_events;   /* bit-mask */
1128	emlxs_dfc_event_t	sd_events[MAX_DFC_EVENTS];
1129#endif
1130} emlxs_port_t;
1131
1132
1133
1134/* Host Attn reg */
1135#define	FC_HA_REG(_hba, _sa)	((volatile uint32_t *)\
1136	((volatile char *)_sa + ((_hba)->ha_reg_addr)))
1137
1138/* Chip Attn reg */
1139#define	FC_CA_REG(_hba, _sa)	((volatile uint32_t *)\
1140	((volatile char *)_sa + ((_hba)->ca_reg_addr)))
1141
1142/* Host Status reg */
1143#define	FC_HS_REG(_hba, _sa)	((volatile uint32_t *)\
1144	((volatile char *)_sa + ((_hba)->hs_reg_addr)))
1145
1146/* Host Cntl reg */
1147#define	FC_HC_REG(_hba, _sa)	((volatile uint32_t *)\
1148	((volatile char *)_sa + ((_hba)->hc_reg_addr)))
1149
1150/* BIU Configuration reg */
1151#define	FC_BC_REG(_hba, _sa)	((volatile uint32_t *)\
1152	((volatile char *)_sa + ((_hba)->bc_reg_addr)))
1153
1154/* Used by SBUS adapter */
1155/* TITAN Cntl reg */
1156#define	FC_SHC_REG(_hba, _sa)	((volatile uint32_t *)\
1157	((volatile char *)_sa + ((_hba)->shc_reg_addr)))
1158
1159/* TITAN Status reg */
1160#define	FC_SHS_REG(_hba, _sa)	((volatile uint32_t *)\
1161	((volatile char *)_sa + ((_hba)->shs_reg_addr)))
1162
1163/* TITAN Update reg */
1164#define	FC_SHU_REG(_hba, _sa)	((volatile uint32_t *)\
1165	((volatile char *)_sa + ((_hba)->shu_reg_addr)))
1166
1167
1168#define	FC_SLIM2_MAILBOX(_hba)	((MAILBOX *)(_hba)->slim2.virt)
1169
1170#define	FC_SLIM1_MAILBOX(_hba)	((MAILBOX *)(_hba)->slim_addr)
1171
1172#define	FC_MAILBOX(_hba)	(((_hba)->flag & FC_SLIM2_MODE) ? \
1173	FC_SLIM2_MAILBOX(_hba) : FC_SLIM1_MAILBOX(_hba))
1174
1175#define	WRITE_CSR_REG(_hba, _regp, _value) ddi_put32(\
1176	(_hba)->csr_acc_handle, (uint32_t *)(_regp), (uint32_t)(_value))
1177
1178#define	READ_CSR_REG(_hba, _regp) ddi_get32(\
1179	(_hba)->csr_acc_handle, (uint32_t *)(_regp))
1180
1181#define	WRITE_SLIM_ADDR(_hba, _regp, _value) ddi_put32(\
1182	(_hba)->slim_acc_handle, (uint32_t *)(_regp), (uint32_t)(_value))
1183
1184#define	READ_SLIM_ADDR(_hba, _regp) ddi_get32(\
1185	(_hba)->slim_acc_handle, (uint32_t *)(_regp))
1186
1187#define	WRITE_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_put32(\
1188	(_hba)->slim_acc_handle, (uint32_t *)(_bufp), (uint32_t *)(_slimp), \
1189	(_wcnt), DDI_DEV_AUTOINCR)
1190
1191#define	READ_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_get32(\
1192	(_hba)->slim_acc_handle, (uint32_t *)(_bufp), (uint32_t *)(_slimp), \
1193	(_wcnt), DDI_DEV_AUTOINCR)
1194
1195#define	WRITE_FLASH_COPY(_hba, _bufp, _flashp, _wcnt) ddi_rep_put32(\
1196	(_hba)->fc_flash_handle, (uint32_t *)(_bufp), (uint32_t *)(_flashp), \
1197	(_wcnt), DDI_DEV_AUTOINCR)
1198
1199#define	READ_FLASH_COPY(_hba, _bufp, _flashp, _wcnt) ddi_rep_get32(\
1200	(_hba)->fc_flash_handle, (uint32_t *)(_bufp), (uint32_t *)(_flashp), \
1201	(_wcnt), DDI_DEV_AUTOINCR)
1202
1203/* Used by SBUS adapter */
1204#define	WRITE_SBUS_CSR_REG(_hba, _regp, _value)	ddi_put32(\
1205	(_hba)->sbus_csr_handle, (uint32_t *)(_regp), (uint32_t)(_value))
1206
1207#define	READ_SBUS_CSR_REG(_hba, _regp) ddi_get32(\
1208	(_hba)->sbus_csr_handle, (uint32_t *)(_regp))
1209
1210#define	SBUS_WRITE_FLASH_COPY(_hba, _offset, _value) ddi_put8(\
1211	(_hba)->sbus_flash_acc_handle, \
1212	(uint8_t *)((volatile uint8_t *)(_hba)->sbus_flash_addr + (_offset)), \
1213	(uint8_t)(_value))
1214
1215#define	SBUS_READ_FLASH_COPY(_hba, _offset) ddi_get8(\
1216	(_hba)->sbus_flash_acc_handle, \
1217	(uint8_t *)((volatile uint8_t *)(_hba)->sbus_flash_addr + (_offset)))
1218
1219#define	emlxs_ffstate_change(_hba, _state)\
1220{									\
1221	mutex_enter(&EMLXS_PORT_LOCK);					\
1222	emlxs_ffstate_change_locked((_hba), (_state));			\
1223	mutex_exit(&EMLXS_PORT_LOCK);					\
1224}
1225
1226/* Used when EMLXS_PORT_LOCK is already held */
1227#define	emlxs_ffstate_change_locked(_hba, _state)			\
1228{									\
1229	if ((_hba)->state != (_state))					\
1230	{								\
1231		uint32_t _st = _state;					\
1232		EMLXS_MSGF(EMLXS_CONTEXT,				\
1233			&emlxs_state_msg, "%s --> %s",			\
1234			emlxs_ffstate_xlate((_hba)->state),		\
1235			emlxs_ffstate_xlate(_state));			\
1236		(_hba)->state = (_state);				\
1237		if ((_st) == FC_ERROR)				\
1238		{							\
1239			(_hba)->flag |= FC_HARDWARE_ERROR;		\
1240		}							\
1241	}								\
1242}
1243
1244/*
1245 * This is the HBA control area for the adapter
1246 */
1247
1248#ifdef MODSYM_SUPPORT
1249
1250typedef struct emlxs_modsym
1251{
1252	ddi_modhandle_t  mod_fctl;	/* For Leadville */
1253
1254	/* Leadville (fctl) */
1255	int		(*fc_fca_attach)(dev_info_t *, fc_fca_tran_t *);
1256	int		(*fc_fca_detach)(dev_info_t *);
1257	int		(*fc_fca_init)(struct dev_ops *);
1258
1259#ifdef SFCT_SUPPORT
1260	ddi_modhandle_t  mod_fct;	/* For Comstar */
1261	ddi_modhandle_t  mod_stmf;	/* For Comstar */
1262
1263	/* Comstar (fct) */
1264	void*	(*fct_alloc)(fct_struct_id_t, int, int);
1265	void	(*fct_free)(void *);
1266	void*	(*fct_scsi_task_alloc)(void *, uint16_t, uint32_t, uint8_t *,
1267			uint16_t, uint16_t);
1268	int	(*fct_register_local_port)(fct_local_port_t *);
1269	void	(*fct_deregister_local_port)(fct_local_port_t *);
1270	void	(*fct_handle_event)(fct_local_port_t *, int, uint32_t, caddr_t);
1271	void	(*fct_post_rcvd_cmd)(fct_cmd_t *, stmf_data_buf_t *);
1272	void	(*fct_ctl)(void *, int, void *);
1273	void	(*fct_queue_cmd_for_termination)(fct_cmd_t *, fct_status_t);
1274	void	(*fct_send_response_done)(fct_cmd_t *, fct_status_t, uint32_t);
1275	void	(*fct_send_cmd_done)(fct_cmd_t *, fct_status_t, uint32_t);
1276	void	(*fct_scsi_data_xfer_done)(fct_cmd_t *, stmf_data_buf_t *,
1277			uint32_t);
1278	fct_status_t	(*fct_port_shutdown)
1279				(fct_local_port_t *, uint32_t, char *);
1280	fct_status_t	(*fct_port_initialize)
1281				(fct_local_port_t *, uint32_t, char *);
1282	void		(*fct_cmd_fca_aborted)
1283				(fct_cmd_t *, fct_status_t, int);
1284	fct_status_t	(*fct_handle_rcvd_flogi)
1285				(fct_local_port_t *, fct_flogi_xchg_t *);
1286
1287	/* Comstar (stmf) */
1288	void*  (*stmf_alloc)(stmf_struct_id_t, int, int);
1289	void   (*stmf_free)(void *);
1290	void	(*stmf_deregister_port_provider) (stmf_port_provider_t *);
1291	int	(*stmf_register_port_provider) (stmf_port_provider_t *);
1292#endif /* SFCT_SUPPORT */
1293} emlxs_modsym_t;
1294extern emlxs_modsym_t emlxs_modsym;
1295
1296#define	MODSYM(_f)	emlxs_modsym._f
1297
1298#else
1299
1300#define	MODSYM(_f)	_f
1301
1302#endif /* MODSYM_SUPPORT */
1303
1304
1305
1306#define	PCI_CONFIG_SIZE   0x80
1307
1308typedef struct emlxs_hba
1309{
1310	dev_info_t	*dip;
1311	int32_t		emlxinst;
1312	int32_t		ddiinst;
1313#ifdef FMA_SUPPORT
1314	int32_t		fm_caps;	/* FMA capabilities */
1315#endif	/* FMA_SUPPORT */
1316	fc_fca_tran_t	*fca_tran;
1317
1318	/* HBA Info */
1319	emlxs_model_t	model_info;
1320	emlxs_vpd_t	vpd;	/* vital product data */
1321	NAME_TYPE	wwnn;
1322	NAME_TYPE	wwpn;
1323	char		snn[256];
1324	char		spn[256];
1325	PROG_ID		load_list[MAX_LOAD_ENTRY];
1326	WAKE_UP_PARMS	wakeup_parms;
1327	uint32_t	max_nodes;
1328	uint32_t	io_throttle;
1329	uint32_t	io_active;
1330	uint32_t	bus_type;
1331#define	PCI_FC  	0
1332#define	SBUS_FC		1
1333
1334	/* Link management */
1335	uint32_t	link_event_tag;
1336	uint8_t		topology;
1337	uint8_t		linkspeed;
1338	uint32_t	linkup_wait_flag;
1339	kcondvar_t	linkup_lock_cv;
1340	kmutex_t	linkup_lock;
1341
1342	/* Memory Pool management */
1343	uint32_t	mem_bpl_size;
1344	emlxs_memseg_t	memseg[FC_MAX_SEG];	/* memory for buffer */
1345							/* structures */
1346	kmutex_t	memget_lock;	/* locks all memory pools get */
1347	kmutex_t	memput_lock;	/* locks all memory pools put */
1348
1349	/* Fibre Channel Service Parameters */
1350	SERV_PARM	sparam;
1351	uint32_t	fc_edtov;	/* E_D_TOV timer value */
1352	uint32_t	fc_arbtov;	/* ARB_TOV timer value */
1353	uint32_t	fc_ratov;	/* R_A_TOV timer value */
1354	uint32_t	fc_rttov;	/* R_T_TOV timer value */
1355	uint32_t	fc_altov;	/* AL_TOV timer value */
1356	uint32_t	fc_crtov;	/* C_R_TOV timer value */
1357	uint32_t	fc_citov;	/* C_I_TOV timer value */
1358
1359	uint32_t	sli_mode;
1360#define	EMLXS_HBA_SLI1_MODE	1
1361#define	EMLXS_HBA_SLI2_MODE	2
1362#define	EMLXS_HBA_SLI3_MODE	3
1363#define	EMLXS_HBA_SLI4_MODE	4
1364
1365	/* SLIM management */
1366	MATCHMAP	slim2;
1367#ifdef SLI3_SUPPORT
1368	/* HBQ management */
1369	uint32_t	hbq_count;	/* Total number of HBQs */
1370					/* configured */
1371	HBQ_INIT_t	hbq_table[EMLXS_NUM_HBQ];
1372#endif	/* SLI3_SUPPORT	 */
1373
1374
1375	/* Adapter State management */
1376	int32_t		state;
1377#define	FC_ERROR		0x01	/* Adapter shutdown */
1378#define	FC_KILLED		0x02	/* Adapter interlocked/killed */
1379#define	FC_WARM_START		0x03	/* Adapter reset, but not restarted */
1380#define	FC_INIT_START		0x10	/* Adapter restarted */
1381#define	FC_INIT_NVPARAMS	0x11
1382#define	FC_INIT_REV		0x12
1383#define	FC_INIT_CFGPORT		0x13
1384#define	FC_INIT_CFGRING		0x14
1385#define	FC_INIT_INITLINK	0x15
1386#define	FC_LINK_DOWN		0x20
1387#define	FC_LINK_UP		0x30
1388#define	FC_CLEAR_LA		0x31
1389#define	FC_READY		0x40
1390
1391	uint32_t	flag;
1392#define	FC_ONLINING_MODE	0x00000001
1393#define	FC_ONLINE_MODE		0x00000002
1394#define	FC_OFFLINING_MODE	0x00000004
1395#define	FC_OFFLINE_MODE		0x00000008
1396
1397#define	FC_NPIV_ENABLED		0x00000010	/* NPIV enabled on adapter    */
1398#define	FC_NPIV_SUPPORTED	0x00000020	/* NPIV supported on fabric   */
1399#define	FC_NPIV_UNSUPPORTED	0x00000040	/* NPIV unsupported on fabric */
1400#define	FC_NPIV_LINKUP		0x00000100	/* NPIV enabled, supported, */
1401						/* and link is ready */
1402#define	FC_NPIV_DELAY_REQUIRED	0x00000200	/* Delay issuing FLOGI/FDISC */
1403						/* and NameServer cmds */
1404
1405#define	FC_FABRIC_ATTACHED	0x00001000
1406#define	FC_PT_TO_PT		0x00002000
1407#define	FC_BYPASSED_MODE	0x00004000
1408#define	FC_MENLO_MODE		0x00008000	/* Menlo maintenance mode */
1409
1410#define	FC_DUMP_SAFE		0x00010000	/* Safe to DUMP */
1411#define	FC_DUMP_ACTIVE		0x00020000	/* DUMP in progress */
1412
1413#define	FC_SLIM2_MODE		0x00100000	/* SLIM in host memory */
1414#define	FC_INTERLOCKED		0x00200000
1415#define	FC_HBQ_ENABLED		0x00400000
1416#define	FC_ASYNC_EVENTS		0x00800000
1417
1418#define	FC_ILB_MODE		0x01000000
1419#define	FC_ELB_MODE		0x02000000
1420#define	FC_LOOPBACK_MODE	0x03000000	/* Loopback Mode Mask */
1421#define	FC_DUMP			0x04000000	/* DUMP in progress */
1422#define	FC_SHUTDOWN		0x08000000	/* SHUTDOWN in progress */
1423
1424#define	FC_OVERTEMP_EVENT	0x10000000	/* FC_ERROR reason: */
1425						/* over temperature event */
1426#define	FC_MBOX_TIMEOUT		0x20000000	/* FC_ERROR reason: */
1427						/* mailbox timeout event */
1428#define	FC_HARDWARE_ERROR	0x80000000	/* FC_ERROR state triggered */
1429
1430#define	FC_RESET_MASK		0x0003001F	/* Bits to protect during */
1431						/* a hard reset */
1432#define	FC_LINKDOWN_MASK	0xFFF0001F	/* Bits to protect during */
1433						/* a linkdown */
1434
1435
1436	/* Adapter memory management */
1437	caddr_t		csr_addr;
1438	caddr_t		slim_addr;
1439	caddr_t		pci_addr;
1440	ddi_acc_handle_t csr_acc_handle;
1441	ddi_acc_handle_t slim_acc_handle;
1442	ddi_acc_handle_t pci_acc_handle;
1443
1444	/* SBUS adapter management */
1445	caddr_t		sbus_flash_addr;	/* Virt addr of R/W */
1446						/* Flash */
1447	caddr_t		sbus_core_addr;		/* Virt addr of TITAN */
1448						/* CORE */
1449	caddr_t		sbus_pci_addr;		/* Virt addr of TITAN */
1450						/* pci config */
1451	caddr_t		sbus_csr_addr;		/* Virt addr of TITAN */
1452						/* CSR */
1453	ddi_acc_handle_t sbus_flash_acc_handle;
1454	ddi_acc_handle_t sbus_core_acc_handle;
1455	ddi_acc_handle_t sbus_pci_handle;
1456	ddi_acc_handle_t sbus_csr_handle;
1457
1458	/* Adapter register management */
1459	uint32_t	bc_reg_addr;	/* virtual offset for BIU */
1460					/* config reg */
1461	uint32_t	ha_reg_addr;	/* virtual offset for host */
1462					/* attn reg */
1463	uint32_t	hc_reg_addr;	/* virtual offset for host */
1464					/* ctl reg */
1465	uint32_t	ca_reg_addr;	/* virtual offset for FF */
1466					/* attn reg */
1467	uint32_t	hs_reg_addr;	/* virtual offset for */
1468					/* status reg */
1469	uint32_t	shc_reg_addr;	/* virtual offset for SBUS */
1470					/* Ctrl reg */
1471	uint32_t	shs_reg_addr;	/* virtual offset for SBUS */
1472					/* Status reg */
1473	uint32_t	shu_reg_addr;	/* virtual offset for SBUS */
1474					/* Update reg */
1475	uint16_t	hgp_ring_offset;
1476	uint16_t	hgp_hbq_offset;
1477	uint16_t	iocb_cmd_size;
1478	uint16_t	iocb_rsp_size;
1479	uint32_t	hc_copy;	/* local copy of HC register */
1480
1481	uint32_t	io_poll_count;	/* Number of poll commands */
1482					/* in progress */
1483
1484	/* IO Completion management */
1485	uint32_t	iodone_count;	/* Number of IO's on done Q */
1486	/* Protected by EMLXS_PORT_LOCK  */
1487	emlxs_buf_t	*iodone_list;	/* fc_packet being deferred */
1488	emlxs_buf_t	*iodone_tail;	/* fc_packet being deferred */
1489	emlxs_thread_t	iodone_thread;
1490
1491	/* Ring management */
1492	int32_t		ring_count;
1493	emlxs_ring_t	ring[MAX_RINGS];
1494	kmutex_t	ring_cmd_lock[MAX_RINGS];
1495	uint8_t		ring_masks[4];	/* number of masks/rings used */
1496	uint8_t		ring_rval[6];
1497	uint8_t		ring_rmask[6];
1498	uint8_t		ring_tval[6];
1499	uint8_t		ring_tmask[6];
1500
1501	kmutex_t	ring_tx_lock;
1502	uint32_t	ring_tx_count[MAX_RINGS];	/* No of IO */
1503							/* on tx Q */
1504
1505	/* Mailbox Management */
1506	uint32_t	mbox_queue_flag;
1507	emlxs_queue_t	mbox_queue;
1508	uint8_t		*mbox_bp;	/* buffer ptr for MBX cmd */
1509	uint8_t		*mbox_sbp;	/* emlxs_buf_t ptr for MBX */
1510					/* cmd used by reg_login only */
1511	uint8_t		*mbox_ubp;	/* fc_unsol_buf_t ptr for MBX */
1512					/* cmd used by reg_login only */
1513	uint8_t		*mbox_iocbq;	/* IOCBQ ptr for MBX cmd */
1514					/* used by reg_login only */
1515	uint8_t		*mbox_mbq;	/* MBX_SLEEP context */
1516	uint32_t	mbox_mbqflag;
1517	kcondvar_t	mbox_lock_cv;	/* MBX_SLEEP */
1518	kmutex_t	mbox_lock;	/* MBX_SLEEP */
1519	uint32_t	mbox_timer;
1520
1521#ifdef MBOX_EXT_SUPPORT
1522	uint8_t		*mbox_ext;	/* ptr to MBX ext buffer */
1523	uint32_t	mbox_ext_size;	/* size of MBX ext buffer */
1524#endif /* MBOX_EXT_SUPPORT */
1525
1526	/* IOtag management */
1527	emlxs_buf_t	**iotag_table;
1528	kmutex_t	iotag_lock[MAX_RINGS];
1529	uint32_t	io_count[MAX_RINGS];	/* No of IO holding */
1530						/* regular iotag */
1531	/* Protected by EMLXS_FCTAB_LOCK */
1532#ifdef EMLXS_SPARC
1533	MATCHMAP	fcp_bpl_mp;
1534	MATCHMAP	*fcp_bpl_table;	/* iotag table for */
1535					/* bpl buffers */
1536#endif	/* EMLXS_SPARC */
1537
1538	/* Interrupt management */
1539	void		*intr_arg;
1540	uint32_t	intr_unclaimed;
1541	uint32_t	intr_autoClear;
1542	uint32_t	intr_flags;
1543#define	EMLXS_INTX_INITED	0x0001
1544#define	EMLXS_INTX_ADDED	0x0002
1545#define	EMLXS_MSI_ENABLED	0x0010
1546#define	EMLXS_MSI_INITED	0x0020
1547#define	EMLXS_MSI_ADDED		0x0040
1548#define	EMLXS_INTR_INITED	(EMLXS_INTX_INITED|EMLXS_MSI_INITED)
1549#define	EMLXS_INTR_ADDED	(EMLXS_INTX_ADDED|EMLXS_MSI_ADDED)
1550
1551#ifdef MSI_SUPPORT
1552	ddi_intr_handle_t *intr_htable;
1553	uint32_t	*intr_pri;
1554	int32_t		*intr_cap;
1555	uint32_t	intr_count;
1556	uint32_t	intr_type;
1557	uint32_t	intr_cond;
1558	uint32_t	intr_map[EMLXS_MSI_MAX_INTRS];
1559	uint32_t	intr_mask;
1560	uint32_t	msi_cap_offset;
1561#define	MSI_CAP_ID	0x05
1562
1563	uint32_t	msix_cap_offset;
1564#define	MSIX_CAP_ID	0x11
1565
1566	kmutex_t	intr_lock[EMLXS_MSI_MAX_INTRS];
1567#endif	/* MSI_SUPPORT */
1568
1569	uint32_t	heartbeat_timer;
1570	uint32_t	heartbeat_flag;
1571	uint32_t	heartbeat_active;
1572
1573	/* IOCTL management */
1574	kmutex_t	ioctl_lock;
1575	uint32_t	ioctl_flags;
1576#define	EMLXS_OPEN		0x00000001
1577#define	EMLXS_OPEN_EXCLUSIVE	0x00000002
1578
1579	/* Timer management */
1580	kcondvar_t	timer_lock_cv;
1581	kmutex_t	timer_lock;
1582	timeout_id_t	timer_id;
1583	uint32_t	timer_tics;
1584	uint32_t	timer_flags;
1585#define	EMLXS_TIMER_STARTED	0x0000001
1586#define	EMLXS_TIMER_BUSY	0x0000002
1587#define	EMLXS_TIMER_KILL	0x0000004
1588#define	EMLXS_TIMER_ENDED	0x0000008
1589
1590	/* Misc Timers */
1591	uint32_t	linkup_timer;
1592	uint32_t	discovery_timer;
1593	uint32_t	pkt_timer;
1594
1595	/* Power Management */
1596	uint32_t	pm_state;
1597	/* pm_state */
1598#define	EMLXS_PM_IN_ATTACH	0x00000001
1599#define	EMLXS_PM_IN_DETACH	0x00000002
1600#define	EMLXS_PM_IN_SOL_CB	0x00000010
1601#define	EMLXS_PM_IN_UNSOL_CB	0x00000020
1602#define	EMLXS_PM_IN_LINK_RESET	0x00000100
1603#define	EMLXS_PM_IN_HARD_RESET	0x00000200
1604#define	EMLXS_PM_SUSPENDED	0x01000000
1605
1606	uint32_t	pm_level;
1607	/* pm_level */
1608#define	EMLXS_PM_ADAPTER_DOWN	0
1609#define	EMLXS_PM_ADAPTER_UP	1
1610
1611	uint32_t	pm_busy;
1612	kmutex_t	pm_lock;
1613	uint8_t		pm_config[PCI_CONFIG_SIZE];
1614#ifdef IDLE_TIMER
1615	uint32_t	pm_idle_timer;
1616	uint32_t	pm_active;	/* Only used by timer */
1617#endif	/* IDLE_TIMER */
1618
1619
1620#ifdef DFC_SUPPORT
1621	/* Loopback management */
1622	uint32_t	loopback_tics;
1623	void		*loopback_pkt;
1624#endif	/* DFC_SUPPORT */
1625
1626	/* Event management */
1627	uint32_t	log_events;
1628	emlxs_dfc_event_t dfc_event[MAX_DFC_EVENTS];
1629	emlxs_hba_event_t hba_event;
1630
1631	/* Parameter management */
1632	emlxs_config_t	config[NUM_CFG_PARAM];
1633
1634	/* Driver stat management */
1635	kstat_t		*kstat;
1636	emlxs_stats_t	stats;
1637
1638	/* Log management */
1639	emlxs_msg_log_t	log;
1640
1641	/* Port managment */
1642	uint32_t	vpi_max;
1643	uint32_t	vpi_high;
1644	uint32_t	num_of_ports;
1645
1646	kmutex_t	port_lock;	/* locks port, nodes, rings */
1647	emlxs_port_t	port[MAX_VPORTS + 1];	/* port specific info */
1648						/* Last one is for */
1649						/* NPIV ready test */
1650
1651#ifdef DHCHAP_SUPPORT
1652	kmutex_t	dhc_lock;
1653	kmutex_t	auth_lock;
1654	emlxs_auth_cfg_t	auth_cfg;	/* Default auth_cfg. */
1655						/* Points to list of entries. */
1656						/* Protected by auth_lock */
1657	uint32_t	auth_cfg_count;
1658	emlxs_auth_key_t	auth_key;	/* Default auth_key. */
1659						/* Points to list of entries. */
1660						/* Protected by auth_lock */
1661	uint32_t	auth_key_count;
1662	uint32_t	rdn_flag;
1663#endif	/* DHCHAP_SUPPORT */
1664
1665	uint16_t	ini_mode;
1666	uint16_t	tgt_mode;
1667
1668#ifdef TEST_SUPPORT
1669	uint32_t	underrun_counter;
1670#endif /* TEST_SUPPORT */
1671
1672#ifdef MODFW_SUPPORT
1673	ddi_modhandle_t	fw_modhandle;
1674#endif /* MODFW_SUPPORT */
1675
1676#ifdef DUMP_SUPPORT
1677	emlxs_file_t	dump_txtfile;
1678	emlxs_file_t	dump_dmpfile;
1679	emlxs_file_t	dump_ceefile;
1680	kmutex_t	dump_lock;
1681#define	EMLXS_DUMP_LOCK		hba->dump_lock
1682#define	EMLXS_TXT_FILE		1
1683#define	EMLXS_DMP_FILE		2
1684#define	EMLXS_CEE_FILE		3
1685
1686#define	EMLXS_DRV_DUMP		0
1687#define	EMLXS_TEMP_DUMP		1
1688#define	EMLXS_USER_DUMP		2
1689
1690#endif /* DUMP_SUPPORT */
1691
1692/* Entry points for SLI API routines */
1693	int		(*emlxs_sli_api_map_hdw)();
1694	void		(*emlxs_sli_api_unmap_hdw)();
1695	int32_t		(*emlxs_sli_api_online)();
1696	void		(*emlxs_sli_api_offline)();
1697	uint32_t	(*emlxs_sli_api_hba_reset)();
1698	void		(*emlxs_sli_api_issue_iocb_cmd)();
1699	uint32_t	(*emlxs_sli_api_issue_mbox_cmd)();
1700	uint32_t	(*emlxs_sli_api_prep_fct_iocb)();
1701	uint32_t	(*emlxs_sli_api_prep_fcp_iocb)();
1702	uint32_t	(*emlxs_sli_api_prep_ip_iocb)();
1703	uint32_t	(*emlxs_sli_api_prep_els_iocb)();
1704	uint32_t	(*emlxs_sli_api_prep_ct_iocb)();
1705	void		(*emlxs_sli_api_poll_intr)();
1706	int32_t		(*emlxs_sli_api_intx_intr)();
1707	uint32_t	(*emlxs_sli_api_msi_intr)();
1708} emlxs_hba_t;
1709
1710#define	emlxs_sli_map_hdw		(hba->emlxs_sli_api_map_hdw)
1711#define	emlxs_sli_unmap_hdw		(hba->emlxs_sli_api_unmap_hdw)
1712#define	emlxs_sli_online		(hba->emlxs_sli_api_online)
1713#define	emlxs_sli_offline		(hba->emlxs_sli_api_offline)
1714#define	emlxs_sli_hba_reset		(hba->emlxs_sli_api_hba_reset)
1715#define	emlxs_sli_issue_iocb_cmd	(hba->emlxs_sli_api_issue_iocb_cmd)
1716#define	emlxs_sli_issue_mbox_cmd	(hba->emlxs_sli_api_issue_mbox_cmd)
1717#define	emlxs_sli_prep_fct_iocb		(hba->emlxs_sli_api_prep_fct_iocb)
1718#define	emlxs_sli_prep_fcp_iocb		(hba->emlxs_sli_api_prep_fcp_iocb)
1719#define	emlxs_sli_prep_ip_iocb		(hba->emlxs_sli_api_prep_ip_iocb)
1720#define	emlxs_sli_prep_els_iocb		(hba->emlxs_sli_api_prep_els_iocb)
1721#define	emlxs_sli_prep_ct_iocb		(hba->emlxs_sli_api_prep_ct_iocb)
1722#define	emlxs_sli_poll_intr		(hba->emlxs_sli_api_poll_intr)
1723#define	emlxs_sli_intx_intr		(hba->emlxs_sli_api_intx_intr)
1724#define	emlxs_sli_msi_intr		(hba->emlxs_sli_api_msi_intr)
1725
1726#define	EMLXS_HBA_T  1  /* flag emlxs_hba_t is already typedefed */
1727
1728
1729#ifdef MSI_SUPPORT
1730#define	EMLXS_INTR_INIT(_hba, _m)		emlxs_msi_init(_hba, _m)
1731#define	EMLXS_INTR_UNINIT(_hba)			emlxs_msi_uninit(_hba)
1732#define	EMLXS_INTR_ADD(_hba)			emlxs_msi_add(_hba)
1733#define	EMLXS_INTR_REMOVE(_hba)			emlxs_msi_remove(_hba)
1734#else
1735#define	EMLXS_INTR_INIT(_hba, _m)		emlxs_intx_init(_hba, _m)
1736#define	EMLXS_INTR_UNINIT(_hba)			emlxs_intx_uninit(_hba)
1737#define	EMLXS_INTR_ADD(_hba)			emlxs_intx_add(_hba)
1738#define	EMLXS_INTR_REMOVE(_hba)			emlxs_intx_remove(_hba)
1739#endif	/* MSI_SUPPORT */
1740
1741
1742/* Power Management Component */
1743#define	EMLXS_PM_ADAPTER	0
1744
1745
1746#define	DRV_TIME	(uint32_t)(ddi_get_time() - emlxs_device.drv_timestamp)
1747
1748#define	HBA			port->hba
1749#define	PPORT			hba->port[0]
1750#define	VPORT(x)		hba->port[x]
1751#define	EMLXS_TIMER_LOCK	hba->timer_lock
1752#define	VPD			hba->vpd
1753#define	CFG			hba->config[0]
1754#define	LOG			hba->log
1755#define	EMLXS_MBOX_LOCK		hba->mbox_lock
1756#define	EMLXS_MBOX_CV		hba->mbox_lock_cv
1757#define	EMLXS_LINKUP_LOCK	hba->linkup_lock
1758#define	EMLXS_LINKUP_CV		hba->linkup_lock_cv
1759#define	EMLXS_RINGTX_LOCK	hba->ring_tx_lock	/* ring txq lock */
1760#define	EMLXS_MEMGET_LOCK	hba->memget_lock	/* mempool get lock */
1761#define	EMLXS_MEMPUT_LOCK	hba->memput_lock	/* mempool put lock */
1762#define	EMLXS_IOCTL_LOCK	hba->ioctl_lock		/* ioctl lock */
1763#define	HBASTATS		hba->stats
1764#define	EMLXS_CMD_RING_LOCK(n)	hba->ring_cmd_lock[n]
1765#define	EMLXS_FCTAB_LOCK(n)	hba->iotag_lock[n]
1766#define	EMLXS_PORT_LOCK		hba->port_lock		/* locks ports, */
1767							/* nodes, rings */
1768#define	EMLXS_INTR_LOCK(_id)	hba->intr_lock[_id]	/* locks intr threads */
1769
1770#define	EMLXS_PKT_LOCK		port->pkt_lock		/* used for pkt */
1771							/* polling */
1772#define	EMLXS_PKT_CV		port->pkt_lock_cv	/* Used for pkt */
1773							/* polling */
1774#define	EMLXS_UB_LOCK		port->ub_lock		/* locks unsolicited */
1775							/* buffer pool */
1776
1777#ifdef EMLXS_LITTLE_ENDIAN
1778#define	SWAP_SHORT(x)	(x)
1779#define	SWAP_LONG(x)	(x)
1780#define	SWAP_DATA64(x)	((((x) & 0xFF)<<56) | (((x) & 0xFF00)<< 40) | \
1781	(((x) & 0xFF0000)<<24) | (((x) & 0xFF000000)<<8) | \
1782	(((x) & 0xFF00000000)>>8) | (((x) & 0xFF0000000000)>>24) | \
1783	(((x) & 0xFF000000000000)>>40) | (((x) & 0xFF00000000000000)>>56))
1784#define	SWAP_DATA32(x)	((((x) & 0xFF)<<24) | (((x) & 0xFF00)<<8) | \
1785	(((x) & 0xFF0000)>>8) | (((x) & 0xFF000000)>>24))
1786#define	SWAP_DATA16(x)	((((x) & 0xFF) << 8) | ((x) >> 8))
1787#define	PCIMEM_SHORT(x)	SWAP_SHORT(x)
1788#define	PCIMEM_LONG(x)	SWAP_LONG(x)
1789#define	PCIMEM_DATA(x)	SWAP_DATA32(x)
1790
1791
1792#if (EMLXS_MODREVX == EMLXS_MODREV2X)
1793#define	SWAP_DATA24_LO(x)	(x)
1794#define	SWAP_DATA24_HI(x)	(x)
1795#endif	/* EMLXS_MODREV2X */
1796
1797#if (EMLXS_MODREVX == EMLXS_MODREV3X)
1798#define	SWAP_DATA24_LO(x)	((((x) & 0xFF)<<16) | \
1799	((x) & 0xFF00FF00) | (((x) & 0x00FF0000)>>16))
1800#define	SWAP_DATA24_HI(x)	(((x) & 0x00FF00FF) | \
1801	(((x) & 0x0000FF00)<<16) | (((x) & 0xFF000000)>>16))
1802#endif	/* EMLXS_MODREV3X */
1803
1804#endif	/* EMLXS_LITTLE_ENDIAN */
1805
1806
1807
1808#ifdef EMLXS_BIG_ENDIAN
1809
1810#define	SWAP_SHORT(x)	((((x) & 0xFF) << 8) | ((x) >> 8))
1811#define	SWAP_LONG(x)	((((x) & 0xFF)<<24) | (((x) & 0xFF00)<<8) | \
1812	(((x) & 0xFF0000)>>8) | (((x) & 0xFF000000)>>24))
1813
1814#define	SWAP_DATA64(x)	(x)
1815#define	SWAP_DATA32(x)	(x)
1816#define	SWAP_DATA16(x)	(x)
1817
1818#define	PCIMEM_SHORT(x)	SWAP_SHORT(x)
1819#define	PCIMEM_LONG(x)	SWAP_LONG(x)
1820#define	PCIMEM_DATA(x)	SWAP_DATA32(x)
1821
1822#define	SWAP_DATA24_LO(x)	(x)
1823#define	SWAP_DATA24_HI(x)	(x)
1824
1825#endif	/* EMLXS_BIG_ENDIAN */
1826
1827#define	SWAP_ALWAYS(x)	((((x) & 0xFF)<<24) | (((x) & 0xFF00)<<8) | \
1828	(((x) & 0xFF0000)>>8) | (((x) & 0xFF000000)>>24))
1829#define	SWAP_ALWAYS16(x)	((((x) & 0xFF) << 8) | ((x) >> 8))
1830
1831/*
1832 * For PCI configuration
1833 */
1834#define	ADDR_LO(addr)	((int)(addr) & 0xffff)	/* low 16 bits */
1835#define	ADDR_HI(addr)	(((int)(addr) >> 16) & 0xffff)	/* high 16 bits */
1836
1837
1838#ifdef	__cplusplus
1839}
1840#endif
1841
1842#endif	/* _EMLXS_FC_H */
1843