1fcf3ce44SJohn Forte /* 2fcf3ce44SJohn Forte * CDDL HEADER START 3fcf3ce44SJohn Forte * 4fcf3ce44SJohn Forte * The contents of this file are subject to the terms of the 5fcf3ce44SJohn Forte * Common Development and Distribution License (the "License"). 6fcf3ce44SJohn Forte * You may not use this file except in compliance with the License. 7fcf3ce44SJohn Forte * 88f23e9faSHans Rosenfeld * You can obtain a copy of the license at 98f23e9faSHans Rosenfeld * http://www.opensource.org/licenses/cddl1.txt. 10fcf3ce44SJohn Forte * See the License for the specific language governing permissions 11fcf3ce44SJohn Forte * and limitations under the License. 12fcf3ce44SJohn Forte * 13fcf3ce44SJohn Forte * When distributing Covered Code, include this CDDL HEADER in each 14fcf3ce44SJohn Forte * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15fcf3ce44SJohn Forte * If applicable, add the following below this CDDL HEADER, with the 16fcf3ce44SJohn Forte * fields enclosed by brackets "[]" replaced with your own identifying 17fcf3ce44SJohn Forte * information: Portions Copyright [yyyy] [name of copyright owner] 18fcf3ce44SJohn Forte * 19fcf3ce44SJohn Forte * CDDL HEADER END 20fcf3ce44SJohn Forte */ 21fcf3ce44SJohn Forte 22fcf3ce44SJohn Forte /* 238f23e9faSHans Rosenfeld * Copyright (c) 2004-2012 Emulex. All rights reserved. 2482527734SSukumar Swaminathan * Use is subject to license terms. 25a3170057SPaul Winder * Copyright 2018 OmniOS Community Edition (OmniOSce) Association. 26a3170057SPaul Winder * Copyright 2020 RackTop Systems, Inc. 27fcf3ce44SJohn Forte */ 28fcf3ce44SJohn Forte 29fcf3ce44SJohn Forte #ifndef _EMLXS_FC_H 30fcf3ce44SJohn Forte #define _EMLXS_FC_H 31fcf3ce44SJohn Forte 32fcf3ce44SJohn Forte #ifdef __cplusplus 33fcf3ce44SJohn Forte extern "C" { 34fcf3ce44SJohn Forte #endif 35fcf3ce44SJohn Forte 36291a2b48SSukumar Swaminathan typedef struct emlxs_buf 37291a2b48SSukumar Swaminathan { 38291a2b48SSukumar Swaminathan fc_packet_t *pkt; /* scsi_pkt reference */ 39291a2b48SSukumar Swaminathan struct emlxs_port *port; /* pointer to port */ 40291a2b48SSukumar Swaminathan void *bmp; /* Save the buffer pointer */ 41291a2b48SSukumar Swaminathan /* list for later use. */ 42291a2b48SSukumar Swaminathan struct emlxs_buf *fc_fwd; /* Use it by chip_Q */ 43291a2b48SSukumar Swaminathan struct emlxs_buf *fc_bkwd; /* Use it by chip_Q */ 44291a2b48SSukumar Swaminathan struct emlxs_buf *next; /* Use it when the iodone */ 45a9800bebSGarrett D'Amore struct emlxs_node *node; 4682527734SSukumar Swaminathan void *channel; /* Save channel and used by */ 47291a2b48SSukumar Swaminathan /* abort */ 4882527734SSukumar Swaminathan struct emlxs_buf *fpkt; /* Flush pkt pointer */ 49a9800bebSGarrett D'Amore struct XRIobj *xrip; /* Exchange resource */ 50291a2b48SSukumar Swaminathan IOCBQ iocbq; 51291a2b48SSukumar Swaminathan kmutex_t mtx; 52291a2b48SSukumar Swaminathan uint32_t pkt_flags; 53291a2b48SSukumar Swaminathan uint32_t iotag; /* iotag for this cmd */ 54291a2b48SSukumar Swaminathan uint32_t ticks; /* save the timeout ticks */ 55291a2b48SSukumar Swaminathan /* for the fc_packet_t */ 56291a2b48SSukumar Swaminathan uint32_t abort_attempts; 57a9800bebSGarrett D'Amore uint32_t lun; 58a9800bebSGarrett D'Amore #define EMLXS_LUN_NONE 0xFFFFFFFF 59a9800bebSGarrett D'Amore 60291a2b48SSukumar Swaminathan uint32_t class; /* Save class and used by */ 61291a2b48SSukumar Swaminathan /* abort */ 62291a2b48SSukumar Swaminathan uint32_t ucmd; /* Unsolicted command that */ 63291a2b48SSukumar Swaminathan /* this packet is responding */ 64291a2b48SSukumar Swaminathan /* to, if any */ 65291a2b48SSukumar Swaminathan int32_t flush_count; /* Valid only in flush pkts */ 66291a2b48SSukumar Swaminathan uint32_t did; 67fcf3ce44SJohn Forte 68fcf3ce44SJohn Forte #ifdef SFCT_SUPPORT 69291a2b48SSukumar Swaminathan kmutex_t fct_mtx; 70291a2b48SSukumar Swaminathan fc_packet_t *fct_pkt; 71291a2b48SSukumar Swaminathan fct_cmd_t *fct_cmd; 72fcf3ce44SJohn Forte 73291a2b48SSukumar Swaminathan uint8_t fct_type; 74fcf3ce44SJohn Forte 75fcf3ce44SJohn Forte #define EMLXS_FCT_ELS_CMD 0x01 /* Unsolicted */ 76fcf3ce44SJohn Forte #define EMLXS_FCT_ELS_REQ 0x02 /* Solicited */ 77fcf3ce44SJohn Forte #define EMLXS_FCT_ELS_RSP 0x04 78fcf3ce44SJohn Forte #define EMLXS_FCT_CT_REQ 0x08 /* Solicited */ 79fcf3ce44SJohn Forte #define EMLXS_FCT_FCP_CMD 0x10 /* Unsolicted */ 80fcf3ce44SJohn Forte #define EMLXS_FCT_FCP_DATA 0x20 81fcf3ce44SJohn Forte #define EMLXS_FCT_FCP_STATUS 0x40 82fcf3ce44SJohn Forte 83fcf3ce44SJohn Forte 84291a2b48SSukumar Swaminathan uint8_t fct_flags; 85fcf3ce44SJohn Forte 86fcf3ce44SJohn Forte #define EMLXS_FCT_SEND_STATUS 0x01 8782527734SSukumar Swaminathan #define EMLXS_FCT_ABORT_INP 0x02 8882527734SSukumar Swaminathan #define EMLXS_FCT_IO_INP 0x04 89a9800bebSGarrett D'Amore #define EMLXS_FCT_PLOGI_RECEIVED 0x10 90a9800bebSGarrett D'Amore #define EMLXS_FCT_REGISTERED 0x20 91291a2b48SSukumar Swaminathan 92291a2b48SSukumar Swaminathan uint16_t fct_state; 93291a2b48SSukumar Swaminathan 94291a2b48SSukumar Swaminathan #define EMLXS_FCT_FCP_CMD_RECEIVED 1 95291a2b48SSukumar Swaminathan #define EMLXS_FCT_ELS_CMD_RECEIVED 2 96291a2b48SSukumar Swaminathan #define EMLXS_FCT_CMD_POSTED 3 97291a2b48SSukumar Swaminathan #define EMLXS_FCT_CMD_WAITQ 4 9882527734SSukumar Swaminathan #define EMLXS_FCT_SEND_CMD_RSP 5 9982527734SSukumar Swaminathan #define EMLXS_FCT_SEND_ELS_RSP 6 10082527734SSukumar Swaminathan #define EMLXS_FCT_SEND_ELS_REQ 7 10182527734SSukumar Swaminathan #define EMLXS_FCT_SEND_CT_REQ 8 10282527734SSukumar Swaminathan #define EMLXS_FCT_RSP_PENDING 9 10382527734SSukumar Swaminathan #define EMLXS_FCT_REQ_PENDING 10 10482527734SSukumar Swaminathan #define EMLXS_FCT_REG_PENDING 11 10582527734SSukumar Swaminathan #define EMLXS_FCT_REG_COMPLETE 12 10682527734SSukumar Swaminathan #define EMLXS_FCT_OWNED 13 10782527734SSukumar Swaminathan #define EMLXS_FCT_SEND_FCP_DATA 14 10882527734SSukumar Swaminathan #define EMLXS_FCT_SEND_FCP_STATUS 15 10982527734SSukumar Swaminathan #define EMLXS_FCT_DATA_PENDING 16 11082527734SSukumar Swaminathan #define EMLXS_FCT_STATUS_PENDING 17 11182527734SSukumar Swaminathan #define EMLXS_FCT_PKT_COMPLETE 18 11282527734SSukumar Swaminathan #define EMLXS_FCT_PKT_FCPRSP_COMPLETE 19 11382527734SSukumar Swaminathan #define EMLXS_FCT_PKT_ELSRSP_COMPLETE 20 11482527734SSukumar Swaminathan #define EMLXS_FCT_PKT_ELSCMD_COMPLETE 21 11582527734SSukumar Swaminathan #define EMLXS_FCT_PKT_CTCMD_COMPLETE 22 11682527734SSukumar Swaminathan #define EMLXS_FCT_REQ_COMPLETE 23 11782527734SSukumar Swaminathan #define EMLXS_FCT_CLOSE_PENDING 24 11882527734SSukumar Swaminathan #define EMLXS_FCT_ABORT_PENDING 25 11982527734SSukumar Swaminathan #define EMLXS_FCT_ABORT_DONE 26 12082527734SSukumar Swaminathan #define EMLXS_FCT_IO_DONE 27 12182527734SSukumar Swaminathan 12282527734SSukumar Swaminathan #define EMLXS_FCT_IOCB_ISSUED 256 /* For tracing only */ 12382527734SSukumar Swaminathan #define EMLXS_FCT_IOCB_COMPLETE 257 /* For tracing only */ 124291a2b48SSukumar Swaminathan 125291a2b48SSukumar Swaminathan stmf_data_buf_t *fct_buf; 126291a2b48SSukumar Swaminathan 127291a2b48SSukumar Swaminathan #endif /* SFCT_SUPPORT */ 128291a2b48SSukumar Swaminathan 129291a2b48SSukumar Swaminathan #ifdef SAN_DIAG_SUPPORT 130291a2b48SSukumar Swaminathan hrtime_t sd_start_time; 1318f23e9faSHans Rosenfeld #endif /* SAN_DIAG_SUPPORT */ 1328f23e9faSHans Rosenfeld 133291a2b48SSukumar Swaminathan } emlxs_buf_t; 134fcf3ce44SJohn Forte 135fcf3ce44SJohn Forte 136fcf3ce44SJohn Forte 137291a2b48SSukumar Swaminathan #ifdef FCT_IO_TRACE 13882527734SSukumar Swaminathan #define EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state) \ 13982527734SSukumar Swaminathan (_cmd_sbp)->fct_state = _state; \ 14082527734SSukumar Swaminathan emlxs_fct_io_trace((_cmd_sbp)->port, _fct_cmd, _state) 141291a2b48SSukumar Swaminathan #else 142291a2b48SSukumar Swaminathan /* define to set fct_state */ 14382527734SSukumar Swaminathan #define EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state) \ 14482527734SSukumar Swaminathan (_cmd_sbp)->fct_state = _state 145291a2b48SSukumar Swaminathan #endif /* FCT_IO_TRACE */ 146fcf3ce44SJohn Forte 147fcf3ce44SJohn Forte 148fcf3ce44SJohn Forte /* pkt_flags */ 149fcf3ce44SJohn Forte #define PACKET_IN_COMPLETION 0x00000001 150fcf3ce44SJohn Forte #define PACKET_IN_TXQ 0x00000002 151fcf3ce44SJohn Forte #define PACKET_IN_CHIPQ 0x00000004 152fcf3ce44SJohn Forte #define PACKET_IN_DONEQ 0x00000008 153fcf3ce44SJohn Forte 154fcf3ce44SJohn Forte #define PACKET_FCP_RESET 0x00000030 155fcf3ce44SJohn Forte #define PACKET_FCP_TGT_RESET 0x00000010 156fcf3ce44SJohn Forte #define PACKET_FCP_LUN_RESET 0x00000020 157fcf3ce44SJohn Forte #define PACKET_POLLED 0x00000040 158fcf3ce44SJohn Forte 159fcf3ce44SJohn Forte #ifdef EMLXS_I386 160fcf3ce44SJohn Forte #define PACKET_FCP_SWAPPED 0x00000100 161fcf3ce44SJohn Forte #define PACKET_ELS_SWAPPED 0x00000200 162fcf3ce44SJohn Forte #define PACKET_CT_SWAPPED 0x00000400 163fcf3ce44SJohn Forte #define PACKET_CSP_SWAPPED 0x00000800 164fcf3ce44SJohn Forte #endif /* EMLXS_I386 */ 165fcf3ce44SJohn Forte 166fcf3ce44SJohn Forte #define PACKET_STALE 0x00001000 167fcf3ce44SJohn Forte 168fcf3ce44SJohn Forte #define PACKET_IN_TIMEOUT 0x00010000 169fcf3ce44SJohn Forte #define PACKET_IN_FLUSH 0x00020000 170fcf3ce44SJohn Forte #define PACKET_IN_ABORT 0x00040000 171e2ca2865SSukumar Swaminathan #define PACKET_XRI_CLOSED 0x00080000 /* An XRI abort/close was issued */ 172fcf3ce44SJohn Forte 173fcf3ce44SJohn Forte #define PACKET_CHIP_COMP 0x00100000 174fcf3ce44SJohn Forte #define PACKET_COMPLETED 0x00200000 17582527734SSukumar Swaminathan #define PACKET_ULP_OWNED 0x00400000 176fcf3ce44SJohn Forte 177fcf3ce44SJohn Forte #define PACKET_STATE_VALID 0x01000000 178fcf3ce44SJohn Forte #define PACKET_FCP_RSP_VALID 0x02000000 179fcf3ce44SJohn Forte #define PACKET_ELS_RSP_VALID 0x04000000 180fcf3ce44SJohn Forte #define PACKET_CT_RSP_VALID 0x08000000 181fcf3ce44SJohn Forte 182fcf3ce44SJohn Forte #define PACKET_DELAY_REQUIRED 0x10000000 183fcf3ce44SJohn Forte #define PACKET_ALLOCATED 0x40000000 184fcf3ce44SJohn Forte #define PACKET_VALID 0x80000000 185fcf3ce44SJohn Forte 186fcf3ce44SJohn Forte 187fcf3ce44SJohn Forte #define STALE_PACKET ((emlxs_buf_t *)0xFFFFFFFF) 188fcf3ce44SJohn Forte 189fcf3ce44SJohn Forte 190fcf3ce44SJohn Forte /* 191fcf3ce44SJohn Forte * From fc_error.h pkt_reason (except for state = NPORT_RJT, FABRIC_RJT, 192fcf3ce44SJohn Forte * NPORT_BSY, FABRIC_BSY, LS_RJT, BA_RJT, FS_RJT) 193fcf3ce44SJohn Forte * 194fcf3ce44SJohn Forte * FCA unique error codes can begin after FC_REASON_FCA_UNIQUE. 195fcf3ce44SJohn Forte * Each FCA defines its own set with values greater >= 0x7F 196fcf3ce44SJohn Forte */ 197fcf3ce44SJohn Forte #define FC_REASON_FCA_DEFINED 0x100 198fcf3ce44SJohn Forte 199fcf3ce44SJohn Forte 200fcf3ce44SJohn Forte /* 201fcf3ce44SJohn Forte * Device VPD save area 202fcf3ce44SJohn Forte */ 203fcf3ce44SJohn Forte 204291a2b48SSukumar Swaminathan typedef struct emlxs_vpd 205291a2b48SSukumar Swaminathan { 206291a2b48SSukumar Swaminathan uint32_t biuRev; 207291a2b48SSukumar Swaminathan uint32_t smRev; 208291a2b48SSukumar Swaminathan uint32_t smFwRev; 209291a2b48SSukumar Swaminathan uint32_t endecRev; 210291a2b48SSukumar Swaminathan uint16_t rBit; 211291a2b48SSukumar Swaminathan uint8_t fcphHigh; 212291a2b48SSukumar Swaminathan uint8_t fcphLow; 213291a2b48SSukumar Swaminathan uint8_t feaLevelHigh; 214291a2b48SSukumar Swaminathan uint8_t feaLevelLow; 215291a2b48SSukumar Swaminathan 216291a2b48SSukumar Swaminathan uint32_t postKernRev; 217291a2b48SSukumar Swaminathan char postKernName[32]; 218291a2b48SSukumar Swaminathan 219291a2b48SSukumar Swaminathan uint32_t opFwRev; 220291a2b48SSukumar Swaminathan char opFwName[32]; 221291a2b48SSukumar Swaminathan char opFwLabel[32]; 222291a2b48SSukumar Swaminathan 223291a2b48SSukumar Swaminathan uint32_t sli1FwRev; 224291a2b48SSukumar Swaminathan char sli1FwName[32]; 225291a2b48SSukumar Swaminathan char sli1FwLabel[32]; 226291a2b48SSukumar Swaminathan 227291a2b48SSukumar Swaminathan uint32_t sli2FwRev; 228291a2b48SSukumar Swaminathan char sli2FwName[32]; 229291a2b48SSukumar Swaminathan char sli2FwLabel[32]; 230291a2b48SSukumar Swaminathan 231291a2b48SSukumar Swaminathan uint32_t sli3FwRev; 232291a2b48SSukumar Swaminathan char sli3FwName[32]; 233291a2b48SSukumar Swaminathan char sli3FwLabel[32]; 234291a2b48SSukumar Swaminathan 235291a2b48SSukumar Swaminathan uint32_t sli4FwRev; 236291a2b48SSukumar Swaminathan char sli4FwName[32]; 237291a2b48SSukumar Swaminathan char sli4FwLabel[32]; 238291a2b48SSukumar Swaminathan 239291a2b48SSukumar Swaminathan char fw_version[32]; 240291a2b48SSukumar Swaminathan char fw_label[32]; 241291a2b48SSukumar Swaminathan 242291a2b48SSukumar Swaminathan char fcode_version[32]; 243291a2b48SSukumar Swaminathan char boot_version[32]; 244291a2b48SSukumar Swaminathan 245291a2b48SSukumar Swaminathan char serial_num[32]; 246291a2b48SSukumar Swaminathan char part_num[32]; 247291a2b48SSukumar Swaminathan char port_num[20]; 248291a2b48SSukumar Swaminathan char eng_change[32]; 249291a2b48SSukumar Swaminathan char manufacturer[80]; 250291a2b48SSukumar Swaminathan char model[80]; 251291a2b48SSukumar Swaminathan char model_desc[256]; 252291a2b48SSukumar Swaminathan char prog_types[256]; 2538f23e9faSHans Rosenfeld char id[256]; 254291a2b48SSukumar Swaminathan 255291a2b48SSukumar Swaminathan uint32_t port_index; 256a9800bebSGarrett D'Amore uint16_t link_speed; 257fcf3ce44SJohn Forte } emlxs_vpd_t; 258fcf3ce44SJohn Forte 259fcf3ce44SJohn Forte 260291a2b48SSukumar Swaminathan typedef struct emlxs_queue 261291a2b48SSukumar Swaminathan { 262a9800bebSGarrett D'Amore void *q_first; /* queue first element */ 263a9800bebSGarrett D'Amore void *q_last; /* queue last element */ 264291a2b48SSukumar Swaminathan uint16_t q_cnt; /* current length of queue */ 265291a2b48SSukumar Swaminathan uint16_t q_max; /* max length queue can get */ 266fcf3ce44SJohn Forte } emlxs_queue_t; 267fcf3ce44SJohn Forte typedef emlxs_queue_t Q; 268fcf3ce44SJohn Forte 269fcf3ce44SJohn Forte 270fcf3ce44SJohn Forte 271fcf3ce44SJohn Forte /* 272fcf3ce44SJohn Forte * This structure is used when allocating a buffer pool. 273fcf3ce44SJohn Forte * Note: this should be identical to gasket buf_info (fldl.h). 274fcf3ce44SJohn Forte */ 275291a2b48SSukumar Swaminathan typedef struct emlxs_buf_info 276291a2b48SSukumar Swaminathan { 277291a2b48SSukumar Swaminathan int32_t size; /* Specifies the number of bytes to allocate. */ 278291a2b48SSukumar Swaminathan int32_t align; /* The desired address boundary. */ 279fcf3ce44SJohn Forte 280291a2b48SSukumar Swaminathan int32_t flags; 281fcf3ce44SJohn Forte 282fcf3ce44SJohn Forte #define FC_MBUF_DMA 0x01 /* blocks are for DMA */ 283fcf3ce44SJohn Forte #define FC_MBUF_PHYSONLY 0x02 /* For malloc - map a given virtual */ 284291a2b48SSukumar Swaminathan /* address to physical address (skip */ 285291a2b48SSukumar Swaminathan /* the malloc). */ 286291a2b48SSukumar Swaminathan /* For free - just unmap the given */ 287fcf3ce44SJohn Forte /* physical address (skip the free). */ 288fcf3ce44SJohn Forte #define FC_MBUF_IOCTL 0x04 /* called from dfc_ioctl */ 289fcf3ce44SJohn Forte #define FC_MBUF_UNLOCK 0x08 /* called with driver unlocked */ 290291a2b48SSukumar Swaminathan #define FC_MBUF_SNGLSG 0x10 /* allocate a single contiguous */ 291291a2b48SSukumar Swaminathan /* physical memory */ 292fcf3ce44SJohn Forte 293291a2b48SSukumar Swaminathan uint64_t phys; /* specifies physical buffer pointer */ 294291a2b48SSukumar Swaminathan void *virt; /* specifies virtual buffer pointer */ 295291a2b48SSukumar Swaminathan void *data_handle; 296291a2b48SSukumar Swaminathan void *dma_handle; 297fcf3ce44SJohn Forte } emlxs_buf_info_t; 298fcf3ce44SJohn Forte typedef emlxs_buf_info_t MBUF_INFO; 299fcf3ce44SJohn Forte 300fcf3ce44SJohn Forte 301fcf3ce44SJohn Forte #define EMLXS_MAX_HBQ 16 /* Max HBQs handled by firmware */ 302fcf3ce44SJohn Forte #define EMLXS_ELS_HBQ_ID 0 303fcf3ce44SJohn Forte #define EMLXS_IP_HBQ_ID 1 304fcf3ce44SJohn Forte #define EMLXS_CT_HBQ_ID 2 305fcf3ce44SJohn Forte #define EMLXS_FCT_HBQ_ID 3 306fcf3ce44SJohn Forte 307fcf3ce44SJohn Forte #ifdef SFCT_SUPPORT 308fcf3ce44SJohn Forte #define EMLXS_NUM_HBQ 4 /* Number of HBQs supported by driver */ 309fcf3ce44SJohn Forte #else 310fcf3ce44SJohn Forte #define EMLXS_NUM_HBQ 3 /* Number of HBQs supported by driver */ 311291a2b48SSukumar Swaminathan #endif /* SFCT_SUPPORT */ 312fcf3ce44SJohn Forte 313fcf3ce44SJohn Forte 31482527734SSukumar Swaminathan /* 31582527734SSukumar Swaminathan * An IO Channel is a object that comprises a xmit/cmpl 31682527734SSukumar Swaminathan * path for IOs. 31782527734SSukumar Swaminathan * For SLI3, an IO path maps to a ring (cmd/rsp) 31882527734SSukumar Swaminathan * For SLI4, an IO path map to a queue pair (WQ/CQ) 31982527734SSukumar Swaminathan */ 32082527734SSukumar Swaminathan typedef struct emlxs_channel 32182527734SSukumar Swaminathan { 32282527734SSukumar Swaminathan struct emlxs_hba *hba; /* ptr to hba for channel */ 32382527734SSukumar Swaminathan void *iopath; /* ptr to SLI3/4 io path */ 32482527734SSukumar Swaminathan 32582527734SSukumar Swaminathan kmutex_t rsp_lock; 32682527734SSukumar Swaminathan IOCBQ *rsp_head; /* deferred completion head */ 32782527734SSukumar Swaminathan IOCBQ *rsp_tail; /* deferred completion tail */ 32882527734SSukumar Swaminathan emlxs_thread_t intr_thread; 32982527734SSukumar Swaminathan 33082527734SSukumar Swaminathan 33182527734SSukumar Swaminathan uint16_t channelno; 33282527734SSukumar Swaminathan uint16_t chan_flag; 33382527734SSukumar Swaminathan 33482527734SSukumar Swaminathan #define EMLXS_NEEDS_TRIGGER 1 33582527734SSukumar Swaminathan 33682527734SSukumar Swaminathan /* Protected by EMLXS_TX_CHANNEL_LOCK */ 33782527734SSukumar Swaminathan emlxs_queue_t nodeq; /* Node service queue */ 33882527734SSukumar Swaminathan 33982527734SSukumar Swaminathan kmutex_t channel_cmd_lock; 34082527734SSukumar Swaminathan uint32_t timeout; 34182527734SSukumar Swaminathan 34282527734SSukumar Swaminathan /* Channel command counters */ 34382527734SSukumar Swaminathan uint32_t ulpSendCmd; 34482527734SSukumar Swaminathan uint32_t ulpCmplCmd; 34582527734SSukumar Swaminathan uint32_t hbaSendCmd; 34682527734SSukumar Swaminathan uint32_t hbaCmplCmd; 34782527734SSukumar Swaminathan uint32_t hbaSendCmd_sbp; 34882527734SSukumar Swaminathan uint32_t hbaCmplCmd_sbp; 34982527734SSukumar Swaminathan 35082527734SSukumar Swaminathan } emlxs_channel_t; 35182527734SSukumar Swaminathan typedef emlxs_channel_t CHANNEL; 35282527734SSukumar Swaminathan 35382527734SSukumar Swaminathan /* 35482527734SSukumar Swaminathan * Should be able to handle max number of io paths for a 35582527734SSukumar Swaminathan * SLI4 HBA (EMLXS_MAX_WQS) or for a SLI3 HBA (MAX_RINGS) 35682527734SSukumar Swaminathan */ 35782527734SSukumar Swaminathan #define MAX_CHANNEL EMLXS_MSI_MAX_INTRS 358fcf3ce44SJohn Forte 359fcf3ce44SJohn Forte 360fcf3ce44SJohn Forte /* Structure used to access adapter rings */ 361291a2b48SSukumar Swaminathan typedef struct emlxs_ring 362291a2b48SSukumar Swaminathan { 363291a2b48SSukumar Swaminathan void *fc_cmdringaddr; /* virtual offset for cmd */ 364291a2b48SSukumar Swaminathan /* rings */ 365291a2b48SSukumar Swaminathan void *fc_rspringaddr; /* virtual offset for rsp */ 366291a2b48SSukumar Swaminathan /* rings */ 367291a2b48SSukumar Swaminathan 368a9800bebSGarrett D'Amore void *fc_mpon; /* index ptr for match */ 369291a2b48SSukumar Swaminathan /* structure */ 370a9800bebSGarrett D'Amore void *fc_mpoff; /* index ptr for match */ 371291a2b48SSukumar Swaminathan /* structure */ 37282527734SSukumar Swaminathan struct emlxs_hba *hba; /* ptr to hba for ring */ 373291a2b48SSukumar Swaminathan 374291a2b48SSukumar Swaminathan uint8_t fc_numCiocb; /* number of command iocb's */ 375291a2b48SSukumar Swaminathan /* per ring */ 376291a2b48SSukumar Swaminathan uint8_t fc_numRiocb; /* number of response iocb's */ 377291a2b48SSukumar Swaminathan /* per ring */ 378291a2b48SSukumar Swaminathan uint8_t fc_rspidx; /* current index in response */ 379291a2b48SSukumar Swaminathan /* ring */ 380291a2b48SSukumar Swaminathan uint8_t fc_cmdidx; /* current index in command */ 381291a2b48SSukumar Swaminathan /* ring */ 382291a2b48SSukumar Swaminathan uint8_t fc_port_rspidx; 383291a2b48SSukumar Swaminathan uint8_t fc_port_cmdidx; 384291a2b48SSukumar Swaminathan uint8_t ringno; 385291a2b48SSukumar Swaminathan 386291a2b48SSukumar Swaminathan uint16_t fc_missbufcnt; /* buf cnt we need to repost */ 38782527734SSukumar Swaminathan CHANNEL *channelp; 388291a2b48SSukumar Swaminathan 389fcf3ce44SJohn Forte 390fcf3ce44SJohn Forte } emlxs_ring_t; 391fcf3ce44SJohn Forte typedef emlxs_ring_t RING; 392fcf3ce44SJohn Forte 393fcf3ce44SJohn Forte 394291a2b48SSukumar Swaminathan #ifdef SAN_DIAG_SUPPORT 395291a2b48SSukumar Swaminathan /* 396291a2b48SSukumar Swaminathan * Although right now it's just 1 field, SAN Diag anticipates that this 397291a2b48SSukumar Swaminathan * structure will grow in the future. 398291a2b48SSukumar Swaminathan */ 399291a2b48SSukumar Swaminathan typedef struct sd_timestat_level0 { 400291a2b48SSukumar Swaminathan int count; 401291a2b48SSukumar Swaminathan } sd_timestat_level0_t; 402291a2b48SSukumar Swaminathan #endif 403291a2b48SSukumar Swaminathan 404291a2b48SSukumar Swaminathan typedef struct emlxs_node 405291a2b48SSukumar Swaminathan { 406291a2b48SSukumar Swaminathan struct emlxs_node *nlp_list_next; 407291a2b48SSukumar Swaminathan struct emlxs_node *nlp_list_prev; 408fcf3ce44SJohn Forte 409291a2b48SSukumar Swaminathan NAME_TYPE nlp_portname; /* port name */ 410291a2b48SSukumar Swaminathan NAME_TYPE nlp_nodename; /* node name */ 411fcf3ce44SJohn Forte 412291a2b48SSukumar Swaminathan uint32_t nlp_DID; /* fibre channel D_ID */ 413fcf3ce44SJohn Forte 414291a2b48SSukumar Swaminathan uint16_t nlp_Rpi; /* login id returned by */ 415291a2b48SSukumar Swaminathan /* REG_LOGIN */ 416291a2b48SSukumar Swaminathan uint16_t nlp_Xri; /* login id returned by */ 417291a2b48SSukumar Swaminathan /* REG_LOGIN */ 418fcf3ce44SJohn Forte 419291a2b48SSukumar Swaminathan uint8_t nlp_fcp_info; /* Remote class info */ 420fcf3ce44SJohn Forte 421fcf3ce44SJohn Forte /* nlp_fcp_info */ 422fcf3ce44SJohn Forte #define NLP_FCP_TGT_DEVICE 0x10 /* FCP TGT device */ 423fcf3ce44SJohn Forte #define NLP_FCP_INI_DEVICE 0x20 /* FCP Initiator device */ 424fcf3ce44SJohn Forte #define NLP_FCP_2_DEVICE 0x40 /* FCP-2 TGT device */ 425291a2b48SSukumar Swaminathan #define NLP_EMLX_VPORT 0x80 /* Virtual port */ 426fcf3ce44SJohn Forte 4278f23e9faSHans Rosenfeld uint8_t dfc_state; 4288f23e9faSHans Rosenfeld #define EMLXS_SET_DFC_STATE(_n, _state) if (_n && _n->nlp_active)\ 4298f23e9faSHans Rosenfeld {(_n)->dfc_state = (_state); } 4308f23e9faSHans Rosenfeld 43182527734SSukumar Swaminathan uint32_t nlp_force_rscn; 432291a2b48SSukumar Swaminathan uint32_t nlp_tag; /* Tag used by port_offline */ 433291a2b48SSukumar Swaminathan uint32_t flag; 434fcf3ce44SJohn Forte 435291a2b48SSukumar Swaminathan #define NODE_POOL_ALLOCATED 0x00000001 436fcf3ce44SJohn Forte 437291a2b48SSukumar Swaminathan SERV_PARM sparm; 438fcf3ce44SJohn Forte 43982527734SSukumar Swaminathan /* Protected by EMLXS_TX_CHANNEL_LOCK */ 440291a2b48SSukumar Swaminathan uint32_t nlp_active; /* Node active flag */ 441291a2b48SSukumar Swaminathan uint32_t nlp_base; 44282527734SSukumar Swaminathan uint32_t nlp_flag[MAX_CHANNEL]; /* Node level channel */ 443291a2b48SSukumar Swaminathan /* flags */ 444fcf3ce44SJohn Forte 445fcf3ce44SJohn Forte /* nlp_flag */ 446291a2b48SSukumar Swaminathan #define NLP_CLOSED 0x1 447291a2b48SSukumar Swaminathan #define NLP_OFFLINE 0x2 448291a2b48SSukumar Swaminathan #define NLP_RPI_XRI 0x4 449291a2b48SSukumar Swaminathan 45082527734SSukumar Swaminathan uint32_t nlp_tics[MAX_CHANNEL]; /* gate timeout */ 45182527734SSukumar Swaminathan emlxs_queue_t nlp_tx[MAX_CHANNEL]; /* Transmit Q head */ 45282527734SSukumar Swaminathan emlxs_queue_t nlp_ptx[MAX_CHANNEL]; /* Priority transmit */ 453291a2b48SSukumar Swaminathan /* Queue head */ 45482527734SSukumar Swaminathan void *nlp_next[MAX_CHANNEL]; /* Service Request */ 455291a2b48SSukumar Swaminathan /* Queue pointer used */ 456291a2b48SSukumar Swaminathan /* when node needs */ 457291a2b48SSukumar Swaminathan /* servicing */ 458fcf3ce44SJohn Forte #ifdef DHCHAP_SUPPORT 459291a2b48SSukumar Swaminathan emlxs_node_dhc_t node_dhc; 460fcf3ce44SJohn Forte #endif /* DHCHAP_SUPPORT */ 461fcf3ce44SJohn Forte 462291a2b48SSukumar Swaminathan #ifdef SAN_DIAG_SUPPORT 463291a2b48SSukumar Swaminathan sd_timestat_level0_t sd_dev_bucket[SD_IO_LATENCY_MAX_BUCKETS]; 464291a2b48SSukumar Swaminathan #endif 46582527734SSukumar Swaminathan 466a9800bebSGarrett D'Amore struct RPIobj *rpip; /* SLI4 only */ 467a9800bebSGarrett D'Amore #define EMLXS_NODE_TO_RPI(_p, _n) \ 468a9800bebSGarrett D'Amore ((_n)?((_n->rpip)?_n->rpip:emlxs_rpi_find(_p, _n->nlp_Rpi)):NULL) 46982527734SSukumar Swaminathan 4708f23e9faSHans Rosenfeld #ifdef NODE_THROTTLE_SUPPORT 4718f23e9faSHans Rosenfeld uint32_t io_throttle; 4728f23e9faSHans Rosenfeld uint32_t io_active; 4738f23e9faSHans Rosenfeld #endif /* NODE_THROTTLE_SUPPORT */ 4748f23e9faSHans Rosenfeld 475fcf3ce44SJohn Forte } emlxs_node_t; 476fcf3ce44SJohn Forte typedef emlxs_node_t NODELIST; 477fcf3ce44SJohn Forte 478fcf3ce44SJohn Forte 479fcf3ce44SJohn Forte 480fcf3ce44SJohn Forte #define NADDR_LEN 6 /* MAC network address length */ 481291a2b48SSukumar Swaminathan typedef struct emlxs_fcip_nethdr 482291a2b48SSukumar Swaminathan { 483291a2b48SSukumar Swaminathan NAME_TYPE fc_destname; /* destination port name */ 484291a2b48SSukumar Swaminathan NAME_TYPE fc_srcname; /* source port name */ 485fcf3ce44SJohn Forte } emlxs_fcip_nethdr_t; 486fcf3ce44SJohn Forte typedef emlxs_fcip_nethdr_t NETHDR; 487fcf3ce44SJohn Forte 488fcf3ce44SJohn Forte 489fcf3ce44SJohn Forte #define MEM_NLP 0 /* memory segment to hold node list entries */ 490fcf3ce44SJohn Forte #define MEM_IOCB 1 /* memory segment to hold iocb commands */ 491291a2b48SSukumar Swaminathan #define MEM_MBOX 2 /* memory segment to hold mailbox cmds */ 492291a2b48SSukumar Swaminathan #define MEM_BPL 3 /* and to hold buffer ptr lists - SLI2 */ 493291a2b48SSukumar Swaminathan #define MEM_BUF 4 /* memory segment to hold buffer data */ 494291a2b48SSukumar Swaminathan #define MEM_ELSBUF 4 /* memory segment to hold buffer data */ 495fcf3ce44SJohn Forte #define MEM_IPBUF 5 /* memory segment to hold IP buffer data */ 496fcf3ce44SJohn Forte #define MEM_CTBUF 6 /* memory segment to hold CT buffer data */ 497fcf3ce44SJohn Forte #define MEM_FCTBUF 7 /* memory segment to hold FCT buffer data */ 498*e2d1a434SCarsten Grzemba #define MEM_SGL1K 8 /* memory segment to hold 1K SGL entries */ 499*e2d1a434SCarsten Grzemba #define MEM_SGL2K 9 /* memory segment to hold 2K SGL entries */ 500*e2d1a434SCarsten Grzemba #define MEM_SGL4K 10 /* memory segment to hold 4K SGL entries */ 501fcf3ce44SJohn Forte 502fcf3ce44SJohn Forte #ifdef SFCT_SUPPORT 503a3170057SPaul Winder #define FC_MAX_SEG 11 504a3170057SPaul Winder #define MEM_FCTSEG 13 /* must be greater than FC_MAX_SEG */ 505fcf3ce44SJohn Forte #else 506a3170057SPaul Winder #define FC_MAX_SEG 10 507291a2b48SSukumar Swaminathan #endif /* SFCT_SUPPORT */ 508fcf3ce44SJohn Forte 509fcf3ce44SJohn Forte 510fcf3ce44SJohn Forte /* A BPL entry is 12 bytes. Subtract 2 for command and response buffers */ 5118f23e9faSHans Rosenfeld #define BPL_TO_SGLLEN(_bpl) ((_bpl/12)-2) 5128f23e9faSHans Rosenfeld #define MEM_BPL_SIZE 36 /* Default size */ 513fcf3ce44SJohn Forte 51482527734SSukumar Swaminathan /* A SGL entry is 16 bytes. Subtract 2 for command and response buffers */ 5158f23e9faSHans Rosenfeld #define SGL_TO_SGLLEN(_sgl) ((_sgl/16)-2) 5168f23e9faSHans Rosenfeld #define MEM_SGL_SIZE 4096 /* Default size */ 517fcf3ce44SJohn Forte 518fcf3ce44SJohn Forte #define MEM_BUF_SIZE 1024 519fcf3ce44SJohn Forte #define MEM_BUF_COUNT 64 520fcf3ce44SJohn Forte 521291a2b48SSukumar Swaminathan #define MEM_ELSBUF_SIZE MEM_BUF_SIZE 522291a2b48SSukumar Swaminathan #define MEM_ELSBUF_COUNT hba->max_nodes 523291a2b48SSukumar Swaminathan #define MEM_IPBUF_SIZE 65535 524fcf3ce44SJohn Forte #define MEM_IPBUF_COUNT 60 525fcf3ce44SJohn Forte #define MEM_CTBUF_SIZE MAX_CT_PAYLOAD /* (1024*320) */ 526fcf3ce44SJohn Forte #define MEM_CTBUF_COUNT 8 527291a2b48SSukumar Swaminathan #define MEM_FCTBUF_SIZE 65535 528fcf3ce44SJohn Forte #define MEM_FCTBUF_COUNT 128 529fcf3ce44SJohn Forte 530291a2b48SSukumar Swaminathan typedef struct emlxs_memseg 531291a2b48SSukumar Swaminathan { 532a9800bebSGarrett D'Amore void *fc_memget_ptr; 533a9800bebSGarrett D'Amore void *fc_memget_end; 534a9800bebSGarrett D'Amore void *fc_memput_ptr; 535a9800bebSGarrett D'Amore void *fc_memput_end; 536291a2b48SSukumar Swaminathan 537291a2b48SSukumar Swaminathan uint32_t fc_total_memsize; 538291a2b48SSukumar Swaminathan uint32_t fc_memsize; /* size of mem blks */ 539291a2b48SSukumar Swaminathan uint32_t fc_numblks; /* no of mem blks */ 540291a2b48SSukumar Swaminathan uint32_t fc_memget_cnt; /* no of mem get blks */ 541291a2b48SSukumar Swaminathan uint32_t fc_memput_cnt; /* no of mem put blks */ 54282527734SSukumar Swaminathan uint32_t fc_memflag; /* emlxs_buf_info_t FLAGS */ 5438f23e9faSHans Rosenfeld #define FC_MEMSEG_PUT_ENABLED 0x20000000 5448f23e9faSHans Rosenfeld #define FC_MEMSEG_GET_ENABLED 0x40000000 5458f23e9faSHans Rosenfeld #define FC_MEMSEG_DYNAMIC 0x80000000 5468f23e9faSHans Rosenfeld 54782527734SSukumar Swaminathan uint32_t fc_memalign; 54882527734SSukumar Swaminathan uint32_t fc_memtag; 54982527734SSukumar Swaminathan char fc_label[32]; 55082527734SSukumar Swaminathan 5518f23e9faSHans Rosenfeld uint32_t fc_hi_water; 5528f23e9faSHans Rosenfeld uint32_t fc_lo_water; 5538f23e9faSHans Rosenfeld uint32_t fc_step; /* Dyn increment. Zero = static */ 5548f23e9faSHans Rosenfeld uint32_t fc_low; /* Lowest free count (dyn only) */ 5558f23e9faSHans Rosenfeld uint32_t fc_last; /* Last fc_numblks (dyn only) */ 5568f23e9faSHans Rosenfeld 557fcf3ce44SJohn Forte } emlxs_memseg_t; 558fcf3ce44SJohn Forte typedef emlxs_memseg_t MEMSEG; 559fcf3ce44SJohn Forte 560fcf3ce44SJohn Forte 561fcf3ce44SJohn Forte /* Board stat counters */ 562291a2b48SSukumar Swaminathan typedef struct emlxs_stats 563291a2b48SSukumar Swaminathan { 564291a2b48SSukumar Swaminathan uint32_t LinkUp; 565291a2b48SSukumar Swaminathan uint32_t LinkDown; 566291a2b48SSukumar Swaminathan uint32_t LinkEvent; 567291a2b48SSukumar Swaminathan uint32_t LinkMultiEvent; 568291a2b48SSukumar Swaminathan 569291a2b48SSukumar Swaminathan uint32_t MboxIssued; 570291a2b48SSukumar Swaminathan uint32_t MboxCompleted; /* MboxError + MbxGood */ 571291a2b48SSukumar Swaminathan uint32_t MboxGood; 572291a2b48SSukumar Swaminathan uint32_t MboxError; 573291a2b48SSukumar Swaminathan uint32_t MboxBusy; 574291a2b48SSukumar Swaminathan uint32_t MboxInvalid; 575291a2b48SSukumar Swaminathan 57682527734SSukumar Swaminathan uint32_t IocbIssued[MAX_CHANNEL]; 57782527734SSukumar Swaminathan uint32_t IocbReceived[MAX_CHANNEL]; 57882527734SSukumar Swaminathan uint32_t IocbTxPut[MAX_CHANNEL]; 57982527734SSukumar Swaminathan uint32_t IocbTxGet[MAX_CHANNEL]; 58082527734SSukumar Swaminathan uint32_t IocbRingFull[MAX_CHANNEL]; 581291a2b48SSukumar Swaminathan uint32_t IocbThrottled; 582291a2b48SSukumar Swaminathan 583291a2b48SSukumar Swaminathan uint32_t IntrEvent[8]; 584291a2b48SSukumar Swaminathan 585291a2b48SSukumar Swaminathan uint32_t FcpIssued; 586291a2b48SSukumar Swaminathan uint32_t FcpCompleted; /* FcpGood + FcpError */ 587291a2b48SSukumar Swaminathan uint32_t FcpGood; 588291a2b48SSukumar Swaminathan uint32_t FcpError; 589291a2b48SSukumar Swaminathan 590291a2b48SSukumar Swaminathan uint32_t FcpEvent; /* FcpStray + FcpCompleted */ 591291a2b48SSukumar Swaminathan uint32_t FcpStray; 592fcf3ce44SJohn Forte #ifdef SFCT_SUPPORT 593291a2b48SSukumar Swaminathan uint32_t FctRingEvent; 594291a2b48SSukumar Swaminathan uint32_t FctRingError; 595291a2b48SSukumar Swaminathan uint32_t FctRingDropped; 596291a2b48SSukumar Swaminathan #endif /* SFCT_SUPPORT */ 597291a2b48SSukumar Swaminathan 598291a2b48SSukumar Swaminathan uint32_t ElsEvent; /* ElsStray + ElsCmplt (cmd + rsp) */ 599291a2b48SSukumar Swaminathan uint32_t ElsStray; 600291a2b48SSukumar Swaminathan 601291a2b48SSukumar Swaminathan uint32_t ElsCmdIssued; 602291a2b48SSukumar Swaminathan uint32_t ElsCmdCompleted; /* ElsCmdGood + ElsCmdError */ 603291a2b48SSukumar Swaminathan uint32_t ElsCmdGood; 604291a2b48SSukumar Swaminathan uint32_t ElsCmdError; 605291a2b48SSukumar Swaminathan 606291a2b48SSukumar Swaminathan uint32_t ElsRspIssued; 607291a2b48SSukumar Swaminathan uint32_t ElsRspCompleted; 608291a2b48SSukumar Swaminathan 609291a2b48SSukumar Swaminathan uint32_t ElsRcvEvent; /* ElsRcvErr + ElsRcvDrop + ElsCmdRcv */ 610291a2b48SSukumar Swaminathan uint32_t ElsRcvError; 611291a2b48SSukumar Swaminathan uint32_t ElsRcvDropped; 612291a2b48SSukumar Swaminathan uint32_t ElsCmdReceived; /* ElsRscnRcv + ElsPlogiRcv + ... */ 613291a2b48SSukumar Swaminathan uint32_t ElsRscnReceived; 614291a2b48SSukumar Swaminathan uint32_t ElsFlogiReceived; 615291a2b48SSukumar Swaminathan uint32_t ElsPlogiReceived; 616291a2b48SSukumar Swaminathan uint32_t ElsPrliReceived; 617291a2b48SSukumar Swaminathan uint32_t ElsPrloReceived; 618291a2b48SSukumar Swaminathan uint32_t ElsLogoReceived; 619291a2b48SSukumar Swaminathan uint32_t ElsAdiscReceived; 620291a2b48SSukumar Swaminathan uint32_t ElsAuthReceived; 621291a2b48SSukumar Swaminathan uint32_t ElsGenReceived; 622291a2b48SSukumar Swaminathan 623291a2b48SSukumar Swaminathan uint32_t CtEvent; /* CtStray + CtCompleted (cmd + rsp) */ 624291a2b48SSukumar Swaminathan uint32_t CtStray; 625291a2b48SSukumar Swaminathan 626291a2b48SSukumar Swaminathan uint32_t CtCmdIssued; 627291a2b48SSukumar Swaminathan uint32_t CtCmdCompleted; /* CtCmdGood + CtCmdError */ 628291a2b48SSukumar Swaminathan uint32_t CtCmdGood; 629291a2b48SSukumar Swaminathan uint32_t CtCmdError; 630291a2b48SSukumar Swaminathan 631291a2b48SSukumar Swaminathan uint32_t CtRspIssued; 632291a2b48SSukumar Swaminathan uint32_t CtRspCompleted; 633291a2b48SSukumar Swaminathan 634291a2b48SSukumar Swaminathan uint32_t CtRcvEvent; /* CtRcvError + CtRcvDrop + CtCmdRcvd */ 635291a2b48SSukumar Swaminathan uint32_t CtRcvError; 636291a2b48SSukumar Swaminathan uint32_t CtRcvDropped; 637291a2b48SSukumar Swaminathan uint32_t CtCmdReceived; 638291a2b48SSukumar Swaminathan 639291a2b48SSukumar Swaminathan uint32_t IpEvent; /* IpStray + IpSeqCmpl + IpBcastCmpl */ 640291a2b48SSukumar Swaminathan uint32_t IpStray; 641291a2b48SSukumar Swaminathan 642291a2b48SSukumar Swaminathan uint32_t IpSeqIssued; 643291a2b48SSukumar Swaminathan uint32_t IpSeqCompleted; /* IpSeqGood + IpSeqError */ 644291a2b48SSukumar Swaminathan uint32_t IpSeqGood; 645291a2b48SSukumar Swaminathan uint32_t IpSeqError; 646291a2b48SSukumar Swaminathan 647291a2b48SSukumar Swaminathan uint32_t IpBcastIssued; 648291a2b48SSukumar Swaminathan uint32_t IpBcastCompleted; /* IpBcastGood + IpBcastError */ 649291a2b48SSukumar Swaminathan uint32_t IpBcastGood; 650291a2b48SSukumar Swaminathan uint32_t IpBcastError; 651291a2b48SSukumar Swaminathan 652291a2b48SSukumar Swaminathan uint32_t IpRcvEvent; /* IpDrop + IpSeqRcv + IpBcastRcv */ 653291a2b48SSukumar Swaminathan uint32_t IpDropped; 654291a2b48SSukumar Swaminathan uint32_t IpSeqReceived; 655291a2b48SSukumar Swaminathan uint32_t IpBcastReceived; 656291a2b48SSukumar Swaminathan 657291a2b48SSukumar Swaminathan uint32_t IpUbPosted; 658291a2b48SSukumar Swaminathan uint32_t ElsUbPosted; 659291a2b48SSukumar Swaminathan uint32_t CtUbPosted; 660fcf3ce44SJohn Forte #ifdef SFCT_SUPPORT 661291a2b48SSukumar Swaminathan uint32_t FctUbPosted; 662291a2b48SSukumar Swaminathan #endif /* SFCT_SUPPORT */ 663fcf3ce44SJohn Forte 664291a2b48SSukumar Swaminathan uint32_t ResetTime; /* Time of last reset */ 665a9800bebSGarrett D'Amore 666a9800bebSGarrett D'Amore uint32_t ElsTestReceived; 667a9800bebSGarrett D'Amore uint32_t ElsEstcReceived; 668a9800bebSGarrett D'Amore uint32_t ElsFarprReceived; 669a9800bebSGarrett D'Amore uint32_t ElsEchoReceived; 670a9800bebSGarrett D'Amore uint32_t ElsRlsReceived; 671a9800bebSGarrett D'Amore uint32_t ElsRtvReceived; 672a9800bebSGarrett D'Amore 673fcf3ce44SJohn Forte } emlxs_stats_t; 674fcf3ce44SJohn Forte 675fcf3ce44SJohn Forte 676291a2b48SSukumar Swaminathan #define FC_MAX_ADPTMSG (8*28) /* max size of a msg from adapter */ 677fcf3ce44SJohn Forte 678fcf3ce44SJohn Forte #define EMLXS_NUM_THREADS 8 679fcf3ce44SJohn Forte #define EMLXS_MIN_TASKS 8 680fcf3ce44SJohn Forte #define EMLXS_MAX_TASKS 8 681fcf3ce44SJohn Forte 682fcf3ce44SJohn Forte #define EMLXS_NUM_HASH_QUES 32 683fcf3ce44SJohn Forte #define EMLXS_DID_HASH(x) ((x) & (EMLXS_NUM_HASH_QUES - 1)) 684fcf3ce44SJohn Forte 685fcf3ce44SJohn Forte 686fcf3ce44SJohn Forte /* pkt_tran_flag */ 687fcf3ce44SJohn Forte #define FC_TRAN_COMPLETED 0x8000 688fcf3ce44SJohn Forte 689fcf3ce44SJohn Forte 690291a2b48SSukumar Swaminathan typedef struct emlxs_dfc_event 691291a2b48SSukumar Swaminathan { 692291a2b48SSukumar Swaminathan uint32_t pid; 693291a2b48SSukumar Swaminathan uint32_t event; 694291a2b48SSukumar Swaminathan uint32_t last_id; 695fcf3ce44SJohn Forte 696291a2b48SSukumar Swaminathan void *dataout; 697291a2b48SSukumar Swaminathan uint32_t size; 698291a2b48SSukumar Swaminathan uint32_t mode; 699fcf3ce44SJohn Forte } emlxs_dfc_event_t; 700fcf3ce44SJohn Forte 701fcf3ce44SJohn Forte 702291a2b48SSukumar Swaminathan typedef struct emlxs_hba_event 703291a2b48SSukumar Swaminathan { 704291a2b48SSukumar Swaminathan uint32_t last_id; 705291a2b48SSukumar Swaminathan uint32_t new; 706291a2b48SSukumar Swaminathan uint32_t missed; 707fcf3ce44SJohn Forte } emlxs_hba_event_t; 708fcf3ce44SJohn Forte 709fcf3ce44SJohn Forte 710fcf3ce44SJohn Forte #ifdef SFCT_SUPPORT 711fcf3ce44SJohn Forte 712fcf3ce44SJohn Forte #define TGTPORTSTAT port->fct_stat 713fcf3ce44SJohn Forte 714fcf3ce44SJohn Forte /* 715fcf3ce44SJohn Forte * FctP2IOXcnt will count IOs by their fcpDL. Counters 716fcf3ce44SJohn Forte * are for buckets of various power of 2 sizes. 717fcf3ce44SJohn Forte * Bucket 0 < 512 > 0 718fcf3ce44SJohn Forte * Bucket 1 >= 512 < 1024 719fcf3ce44SJohn Forte * Bucket 2 >= 1024 < 2048 720fcf3ce44SJohn Forte * Bucket 3 >= 2048 < 4096 721fcf3ce44SJohn Forte * Bucket 4 >= 4096 < 8192 722fcf3ce44SJohn Forte * Bucket 5 >= 8192 < 16K 723fcf3ce44SJohn Forte * Bucket 6 >= 16K < 32K 724fcf3ce44SJohn Forte * Bucket 7 >= 32K < 64K 725fcf3ce44SJohn Forte * Bucket 8 >= 64K < 128K 726fcf3ce44SJohn Forte * Bucket 9 >= 128K < 256K 727fcf3ce44SJohn Forte * Bucket 10 >= 256K < 512K 728fcf3ce44SJohn Forte * Bucket 11 >= 512K < 1MB 729fcf3ce44SJohn Forte * Bucket 12 >= 1MB < 2MB 730fcf3ce44SJohn Forte * Bucket 13 >= 2MB < 4MB 731fcf3ce44SJohn Forte * Bucket 14 >= 4MB < 8MB 732fcf3ce44SJohn Forte * Bucket 15 >= 8MB 733fcf3ce44SJohn Forte */ 734291a2b48SSukumar Swaminathan #define MAX_TGTPORT_IOCNT 16 735fcf3ce44SJohn Forte 736fcf3ce44SJohn Forte 737fcf3ce44SJohn Forte /* 738fcf3ce44SJohn Forte * These routines will bump the right counter, based on 739fcf3ce44SJohn Forte * the size of the IO inputed, with the least number of 740fcf3ce44SJohn Forte * comparisions. A max of 5 comparisions is only needed 741fcf3ce44SJohn Forte * to classify the IO in one of 16 ranges. A binary search 742fcf3ce44SJohn Forte * to locate the high bit in the size is used. 743fcf3ce44SJohn Forte */ 74482527734SSukumar Swaminathan #define EMLXS_BUMP_RDIOCTR(port, cnt) \ 745291a2b48SSukumar Swaminathan { \ 746291a2b48SSukumar Swaminathan /* Use binary search to find the first high bit */ \ 747291a2b48SSukumar Swaminathan if (cnt & 0xffff0000) { \ 748291a2b48SSukumar Swaminathan if (cnt & 0xff800000) { \ 749291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[15]++; \ 750291a2b48SSukumar Swaminathan } \ 751291a2b48SSukumar Swaminathan else { \ 752291a2b48SSukumar Swaminathan /* It must be 0x007f0000 */ \ 753291a2b48SSukumar Swaminathan if (cnt & 0x00700000) { \ 754291a2b48SSukumar Swaminathan if (cnt & 0x00400000) { \ 755291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[14]++; \ 756291a2b48SSukumar Swaminathan } \ 757291a2b48SSukumar Swaminathan else { \ 758291a2b48SSukumar Swaminathan /* it must be 0x00300000 */ \ 759291a2b48SSukumar Swaminathan if (cnt & 0x00200000) { \ 760291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[13]++; \ 761291a2b48SSukumar Swaminathan } \ 762291a2b48SSukumar Swaminathan else { \ 763291a2b48SSukumar Swaminathan /* It must be 0x00100000 */ \ 764291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[12]++; \ 765291a2b48SSukumar Swaminathan } \ 766291a2b48SSukumar Swaminathan } \ 767291a2b48SSukumar Swaminathan } \ 768291a2b48SSukumar Swaminathan else { \ 769291a2b48SSukumar Swaminathan /* It must be 0x000f0000 */ \ 770291a2b48SSukumar Swaminathan if (cnt & 0x000c0000) { \ 771291a2b48SSukumar Swaminathan if (cnt & 0x00080000) { \ 772fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IORcnt[11]++; \ 773291a2b48SSukumar Swaminathan } \ 774291a2b48SSukumar Swaminathan else { \ 775291a2b48SSukumar Swaminathan /* It must be 0x00040000 */ \ 776fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IORcnt[10]++; \ 777291a2b48SSukumar Swaminathan } \ 778291a2b48SSukumar Swaminathan } \ 779291a2b48SSukumar Swaminathan else { \ 780291a2b48SSukumar Swaminathan /* It must be 0x00030000 */ \ 781291a2b48SSukumar Swaminathan if (cnt & 0x00020000) { \ 782291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[9]++; \ 783291a2b48SSukumar Swaminathan } \ 784291a2b48SSukumar Swaminathan else { \ 785291a2b48SSukumar Swaminathan /* It must be 0x00010000 */ \ 786291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[8]++; \ 787291a2b48SSukumar Swaminathan } \ 788291a2b48SSukumar Swaminathan } \ 789291a2b48SSukumar Swaminathan } \ 790291a2b48SSukumar Swaminathan } \ 791291a2b48SSukumar Swaminathan } \ 792291a2b48SSukumar Swaminathan else { \ 793291a2b48SSukumar Swaminathan if (cnt & 0x0000fe00) { \ 794291a2b48SSukumar Swaminathan if (cnt & 0x0000f000) { \ 795291a2b48SSukumar Swaminathan if (cnt & 0x0000c000) { \ 796291a2b48SSukumar Swaminathan if (cnt & 0x00008000) { \ 797291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[7]++; \ 798291a2b48SSukumar Swaminathan } \ 799291a2b48SSukumar Swaminathan else { \ 800291a2b48SSukumar Swaminathan /* It must be 0x00004000 */ \ 801291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[6]++; \ 802291a2b48SSukumar Swaminathan } \ 803291a2b48SSukumar Swaminathan } \ 804291a2b48SSukumar Swaminathan else { \ 805291a2b48SSukumar Swaminathan /* It must be 0x00000300 */ \ 806291a2b48SSukumar Swaminathan if (cnt & 0x00000200) { \ 807291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[5]++; \ 808291a2b48SSukumar Swaminathan } \ 809291a2b48SSukumar Swaminathan else { \ 810291a2b48SSukumar Swaminathan /* It must be 0x00000100 */ \ 811291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[4]++; \ 812291a2b48SSukumar Swaminathan } \ 813291a2b48SSukumar Swaminathan } \ 814291a2b48SSukumar Swaminathan } \ 815291a2b48SSukumar Swaminathan else { \ 816291a2b48SSukumar Swaminathan /* It must be 0x00000e00 */ \ 817291a2b48SSukumar Swaminathan if (cnt & 0x00000800) { \ 818291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[3]++; \ 819291a2b48SSukumar Swaminathan } \ 820291a2b48SSukumar Swaminathan else { \ 821291a2b48SSukumar Swaminathan /* It must be 0x00000600 */ \ 822291a2b48SSukumar Swaminathan if (cnt & 0x00000400) { \ 823291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[2]++; \ 824291a2b48SSukumar Swaminathan } \ 825291a2b48SSukumar Swaminathan else { \ 826291a2b48SSukumar Swaminathan /* It must be 0x00000200 */ \ 827291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[1]++; \ 828291a2b48SSukumar Swaminathan } \ 829291a2b48SSukumar Swaminathan } \ 830291a2b48SSukumar Swaminathan } \ 831291a2b48SSukumar Swaminathan } \ 832291a2b48SSukumar Swaminathan else { \ 833291a2b48SSukumar Swaminathan /* It must be 0x000001ff */ \ 834291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IORcnt[0]++; \ 835291a2b48SSukumar Swaminathan } \ 836291a2b48SSukumar Swaminathan } \ 837fcf3ce44SJohn Forte } 838fcf3ce44SJohn Forte 839291a2b48SSukumar Swaminathan 84082527734SSukumar Swaminathan #define EMLXS_BUMP_WRIOCTR(port, cnt) \ 841291a2b48SSukumar Swaminathan { \ 842291a2b48SSukumar Swaminathan /* Use binary search to find the first high bit */ \ 843291a2b48SSukumar Swaminathan if (cnt & 0xffff0000) { \ 844291a2b48SSukumar Swaminathan if (cnt & 0xff800000) { \ 845291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IOWcnt[15]++; \ 846291a2b48SSukumar Swaminathan } \ 847291a2b48SSukumar Swaminathan else { \ 848291a2b48SSukumar Swaminathan /* It must be 0x007f0000 */ \ 849291a2b48SSukumar Swaminathan if (cnt & 0x00700000) { \ 850291a2b48SSukumar Swaminathan if (cnt & 0x00400000) { \ 851291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IOWcnt[14]++; \ 852291a2b48SSukumar Swaminathan } \ 853291a2b48SSukumar Swaminathan else { \ 854291a2b48SSukumar Swaminathan /* It must be 0x00300000 */ \ 855291a2b48SSukumar Swaminathan if (cnt & 0x00200000) { \ 856fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[13]++; \ 857291a2b48SSukumar Swaminathan } \ 858291a2b48SSukumar Swaminathan else { \ 859291a2b48SSukumar Swaminathan /* It must be 0x00100000 */ \ 860fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[12]++; \ 861291a2b48SSukumar Swaminathan } \ 862291a2b48SSukumar Swaminathan } \ 863291a2b48SSukumar Swaminathan } \ 864291a2b48SSukumar Swaminathan else { \ 865291a2b48SSukumar Swaminathan /* It must be 0x000f0000 */ \ 866291a2b48SSukumar Swaminathan if (cnt & 0x000c0000) { \ 867291a2b48SSukumar Swaminathan if (cnt & 0x00080000) { \ 868fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[11]++; \ 869291a2b48SSukumar Swaminathan } \ 870291a2b48SSukumar Swaminathan else { \ 871291a2b48SSukumar Swaminathan /* it must be 0x00040000 */ \ 872fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[10]++; \ 873291a2b48SSukumar Swaminathan } \ 874291a2b48SSukumar Swaminathan } \ 875291a2b48SSukumar Swaminathan else { \ 876291a2b48SSukumar Swaminathan /* It must be 0x00030000 */ \ 877291a2b48SSukumar Swaminathan if (cnt & 0x00020000) { \ 878fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[9]++; \ 879291a2b48SSukumar Swaminathan } \ 880291a2b48SSukumar Swaminathan else { \ 881291a2b48SSukumar Swaminathan /* It must be 0x00010000 */ \ 882fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[8]++; \ 883291a2b48SSukumar Swaminathan } \ 884291a2b48SSukumar Swaminathan } \ 885291a2b48SSukumar Swaminathan } \ 886291a2b48SSukumar Swaminathan } \ 887291a2b48SSukumar Swaminathan } \ 888291a2b48SSukumar Swaminathan else { \ 889291a2b48SSukumar Swaminathan if (cnt & 0x0000fe00) { \ 890291a2b48SSukumar Swaminathan if (cnt & 0x0000f000) { \ 891291a2b48SSukumar Swaminathan if (cnt & 0x0000c000) { \ 892291a2b48SSukumar Swaminathan if (cnt & 0x00008000) { \ 893fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[7]++; \ 894291a2b48SSukumar Swaminathan } \ 895291a2b48SSukumar Swaminathan else { \ 896291a2b48SSukumar Swaminathan /* It must be 0x00004000 */ \ 897fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[6]++; \ 898291a2b48SSukumar Swaminathan } \ 899291a2b48SSukumar Swaminathan } \ 900291a2b48SSukumar Swaminathan else { \ 901291a2b48SSukumar Swaminathan /* It must be 0x00000300 */ \ 902291a2b48SSukumar Swaminathan if (cnt & 0x00000200) { \ 903fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[5]++; \ 904291a2b48SSukumar Swaminathan } \ 905291a2b48SSukumar Swaminathan else { \ 906291a2b48SSukumar Swaminathan /* It must be 0x00000100 */ \ 907fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[4]++; \ 908291a2b48SSukumar Swaminathan } \ 909291a2b48SSukumar Swaminathan } \ 910291a2b48SSukumar Swaminathan } \ 911291a2b48SSukumar Swaminathan else { \ 912291a2b48SSukumar Swaminathan /* It must be 0x00000e00 */ \ 913291a2b48SSukumar Swaminathan if (cnt & 0x00000800) { \ 914291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IOWcnt[3]++; \ 915291a2b48SSukumar Swaminathan } \ 916291a2b48SSukumar Swaminathan else { \ 917291a2b48SSukumar Swaminathan /* It must be 0x00000600 */ \ 918291a2b48SSukumar Swaminathan if (cnt & 0x00000400) { \ 919fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[2]++; \ 920291a2b48SSukumar Swaminathan } \ 921291a2b48SSukumar Swaminathan else { \ 922291a2b48SSukumar Swaminathan /* It must be 0x00000200 */ \ 923fcf3ce44SJohn Forte TGTPORTSTAT.FctP2IOWcnt[1]++; \ 924291a2b48SSukumar Swaminathan } \ 925291a2b48SSukumar Swaminathan } \ 926291a2b48SSukumar Swaminathan } \ 927291a2b48SSukumar Swaminathan } \ 928291a2b48SSukumar Swaminathan else { \ 929291a2b48SSukumar Swaminathan /* It must be 0x000001ff */ \ 930291a2b48SSukumar Swaminathan TGTPORTSTAT.FctP2IOWcnt[0]++; \ 931291a2b48SSukumar Swaminathan } \ 932291a2b48SSukumar Swaminathan } \ 933fcf3ce44SJohn Forte } 934fcf3ce44SJohn Forte 935291a2b48SSukumar Swaminathan typedef struct emlxs_tgtport_stat 936291a2b48SSukumar Swaminathan { 937fcf3ce44SJohn Forte /* IO counters */ 938291a2b48SSukumar Swaminathan uint64_t FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */ 939291a2b48SSukumar Swaminathan uint64_t FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads */ 940291a2b48SSukumar Swaminathan uint64_t FctIOCmdCnt; /* Other, ie TUR */ 941291a2b48SSukumar Swaminathan uint64_t FctCmdReceived; /* total IOs */ 942291a2b48SSukumar Swaminathan uint64_t FctReadBytes; /* total read bytes */ 943291a2b48SSukumar Swaminathan uint64_t FctWriteBytes; /* total write bytes */ 944fcf3ce44SJohn Forte 945fcf3ce44SJohn Forte /* IOCB handling counters */ 946291a2b48SSukumar Swaminathan uint64_t FctEvent; /* FctStray + FctCompleted */ 947291a2b48SSukumar Swaminathan uint64_t FctCompleted; /* FctCmplGood + FctCmplError */ 948291a2b48SSukumar Swaminathan uint64_t FctCmplGood; 949fcf3ce44SJohn Forte 950291a2b48SSukumar Swaminathan uint32_t FctCmplError; 951291a2b48SSukumar Swaminathan uint32_t FctStray; 952fcf3ce44SJohn Forte 953fcf3ce44SJohn Forte /* Fct event counters */ 954291a2b48SSukumar Swaminathan uint32_t FctRcvDropped; 955291a2b48SSukumar Swaminathan uint32_t FctOverQDepth; 956291a2b48SSukumar Swaminathan uint32_t FctOutstandingIO; 957291a2b48SSukumar Swaminathan uint32_t FctFailedPortRegister; 958291a2b48SSukumar Swaminathan uint32_t FctPortRegister; 959291a2b48SSukumar Swaminathan uint32_t FctPortDeregister; 960291a2b48SSukumar Swaminathan 961291a2b48SSukumar Swaminathan uint32_t FctAbortSent; 962291a2b48SSukumar Swaminathan uint32_t FctNoBuffer; 963291a2b48SSukumar Swaminathan uint32_t FctScsiStatusErr; 964291a2b48SSukumar Swaminathan uint32_t FctScsiQfullErr; 965291a2b48SSukumar Swaminathan uint32_t FctScsiResidOver; 966291a2b48SSukumar Swaminathan uint32_t FctScsiResidUnder; 967291a2b48SSukumar Swaminathan uint32_t FctScsiSenseErr; 968291a2b48SSukumar Swaminathan 969291a2b48SSukumar Swaminathan uint32_t FctFiller1; 970fcf3ce44SJohn Forte } emlxs_tgtport_stat_t; 971291a2b48SSukumar Swaminathan 972291a2b48SSukumar Swaminathan #ifdef FCT_IO_TRACE 973291a2b48SSukumar Swaminathan #define MAX_IO_TRACE 67 974291a2b48SSukumar Swaminathan typedef struct emlxs_iotrace 975291a2b48SSukumar Swaminathan { 976291a2b48SSukumar Swaminathan fct_cmd_t *fct_cmd; 977291a2b48SSukumar Swaminathan uint32_t xri; 978291a2b48SSukumar Swaminathan uint8_t marker; /* 0xff */ 979291a2b48SSukumar Swaminathan uint8_t trc[MAX_IO_TRACE]; /* trc[0] = index */ 980291a2b48SSukumar Swaminathan } emlxs_iotrace_t; 981291a2b48SSukumar Swaminathan #endif /* FCT_IO_TRACE */ 982291a2b48SSukumar Swaminathan #endif /* SFCT_SUPPORT */ 983fcf3ce44SJohn Forte 984fcf3ce44SJohn Forte 985a9800bebSGarrett D'Amore #include <emlxs_fcf.h> 986a9800bebSGarrett D'Amore 987fcf3ce44SJohn Forte /* 988291a2b48SSukumar Swaminathan * Port Information Data Structure 989fcf3ce44SJohn Forte */ 990fcf3ce44SJohn Forte 991291a2b48SSukumar Swaminathan typedef struct emlxs_port 992291a2b48SSukumar Swaminathan { 993291a2b48SSukumar Swaminathan struct emlxs_hba *hba; 994fcf3ce44SJohn Forte 995fcf3ce44SJohn Forte /* Virtual port management */ 996a9800bebSGarrett D'Amore struct VPIobj VPIobj; 9978f23e9faSHans Rosenfeld struct VPIobj *vpip; /* &VPIobj */ 9988f23e9faSHans Rosenfeld 9998f23e9faSHans Rosenfeld uint32_t vpi; /* Legacy vpi == vpip->index */ 10008f23e9faSHans Rosenfeld uint32_t mode; 10018f23e9faSHans Rosenfeld uint32_t mode_mask; /* User configured */ 10028f23e9faSHans Rosenfeld #define MODE_NONE 0x00000000 10038f23e9faSHans Rosenfeld #define MODE_INITIATOR 0x00000001 10048f23e9faSHans Rosenfeld #define MODE_TARGET 0x00000002 10058f23e9faSHans Rosenfeld #define MODE_ALL 0x00000003 1006a9800bebSGarrett D'Amore 1007291a2b48SSukumar Swaminathan uint32_t flag; 10088f23e9faSHans Rosenfeld #define EMLXS_PORT_ENABLED 0x00000001 /* vport setting */ 10098f23e9faSHans Rosenfeld #define EMLXS_PORT_CONFIG 0x00000002 /* vport setting */ 10108f23e9faSHans Rosenfeld 10118f23e9faSHans Rosenfeld #define EMLXS_INI_ENABLED 0x00000010 /* emlxs_mode_init */ 10128f23e9faSHans Rosenfeld #define EMLXS_INI_BOUND 0x00000020 /* emlxs_fca_bind_port */ 10138f23e9faSHans Rosenfeld #define EMLXS_TGT_ENABLED 0x00000040 /* emlxs_mode_init */ 10148f23e9faSHans Rosenfeld #define EMLXS_TGT_BOUND 0x00000080 /* emlxs_fct_bind_port */ 10158f23e9faSHans Rosenfeld #define EMLXS_PORT_BOUND (EMLXS_INI_BOUND|EMLXS_TGT_BOUND) 10168f23e9faSHans Rosenfeld 10178f23e9faSHans Rosenfeld #define EMLXS_PORT_IP_UP 0x00000100 10188f23e9faSHans Rosenfeld #define EMLXS_PORT_RESTRICTED 0x00000200 /* Restrict logins */ 1019fcf3ce44SJohn Forte 1020a9800bebSGarrett D'Amore #define EMLXS_PORT_REG_VPI 0x00010000 /* SLI3 */ 1021a9800bebSGarrett D'Amore #define EMLXS_PORT_REG_VPI_CMPL 0x00020000 /* SLI3 */ 1022a9800bebSGarrett D'Amore 10238f23e9faSHans Rosenfeld #define EMLXS_PORT_FLOGI_CMPL 0x01000000 /* Fabric login */ 10248f23e9faSHans Rosenfeld /* completed */ 1025fcf3ce44SJohn Forte 10268f23e9faSHans Rosenfeld #define EMLXS_PORT_RESET_MASK 0x0000FFFF /* Flags to keep */ 10278f23e9faSHans Rosenfeld /* across hard reset */ 10288f23e9faSHans Rosenfeld #define EMLXS_PORT_LINKDOWN_MASK 0x00FFFFFF /* Flags to keep */ 10298f23e9faSHans Rosenfeld /* across link reset */ 1030fcf3ce44SJohn Forte 1031291a2b48SSukumar Swaminathan uint32_t options; 1032a9800bebSGarrett D'Amore #define EMLXS_OPT_RESTRICT 0x00000001 /* Force restricted */ 1033a9800bebSGarrett D'Amore /* logins */ 1034a9800bebSGarrett D'Amore #define EMLXS_OPT_UNRESTRICT 0x00000002 /* Force Unrestricted */ 1035a9800bebSGarrett D'Amore /* logins */ 1036fcf3ce44SJohn Forte #define EMLXS_OPT_RESTRICT_MASK 0x00000003 1037fcf3ce44SJohn Forte 1038fcf3ce44SJohn Forte 1039fcf3ce44SJohn Forte /* FC world wide names */ 1040291a2b48SSukumar Swaminathan NAME_TYPE wwnn; 1041291a2b48SSukumar Swaminathan NAME_TYPE wwpn; 1042291a2b48SSukumar Swaminathan char snn[256]; 1043291a2b48SSukumar Swaminathan char spn[256]; 1044fcf3ce44SJohn Forte 1045fcf3ce44SJohn Forte /* Common service paramters */ 1046291a2b48SSukumar Swaminathan SERV_PARM sparam; 1047291a2b48SSukumar Swaminathan SERV_PARM fabric_sparam; 1048a9800bebSGarrett D'Amore SERV_PARM prev_fabric_sparam; 1049fcf3ce44SJohn Forte 1050fcf3ce44SJohn Forte /* fc_id management */ 1051291a2b48SSukumar Swaminathan uint32_t did; 1052291a2b48SSukumar Swaminathan uint32_t prev_did; 1053fcf3ce44SJohn Forte 105482527734SSukumar Swaminathan /* support FC_PORT_GET_P2P_INFO only */ 105582527734SSukumar Swaminathan uint32_t rdid; 105682527734SSukumar Swaminathan 1057fcf3ce44SJohn Forte /* FC_AL management */ 1058291a2b48SSukumar Swaminathan uint8_t lip_type; 10598f23e9faSHans Rosenfeld uint8_t granted_alpa; 1060291a2b48SSukumar Swaminathan uint8_t alpa_map[128]; 1061fcf3ce44SJohn Forte 1062fcf3ce44SJohn Forte /* Node management */ 1063291a2b48SSukumar Swaminathan emlxs_node_t node_base; 1064291a2b48SSukumar Swaminathan uint32_t node_count; 1065291a2b48SSukumar Swaminathan krwlock_t node_rwlock; 1066291a2b48SSukumar Swaminathan emlxs_node_t *node_table[EMLXS_NUM_HASH_QUES]; 1067fcf3ce44SJohn Forte 1068fcf3ce44SJohn Forte /* Polled packet management */ 1069291a2b48SSukumar Swaminathan kcondvar_t pkt_lock_cv; /* pkt polling */ 1070291a2b48SSukumar Swaminathan kmutex_t pkt_lock; /* pkt polling */ 1071fcf3ce44SJohn Forte 1072fcf3ce44SJohn Forte /* ULP */ 10738f23e9faSHans Rosenfeld uint32_t ulp_busy; 1074291a2b48SSukumar Swaminathan uint32_t ulp_statec; 1075291a2b48SSukumar Swaminathan void (*ulp_statec_cb) (); /* Port state change */ 1076291a2b48SSukumar Swaminathan /* callback routine */ 1077291a2b48SSukumar Swaminathan void (*ulp_unsol_cb) (); /* unsolicited event */ 1078291a2b48SSukumar Swaminathan /* callback routine */ 1079291a2b48SSukumar Swaminathan opaque_t ulp_handle; 1080fcf3ce44SJohn Forte 1081fcf3ce44SJohn Forte /* ULP unsolicited buffers */ 1082291a2b48SSukumar Swaminathan kmutex_t ub_lock; 1083291a2b48SSukumar Swaminathan uint32_t ub_count; 1084291a2b48SSukumar Swaminathan emlxs_unsol_buf_t *ub_pool; 108582527734SSukumar Swaminathan uint32_t ub_post[MAX_CHANNEL]; 1086291a2b48SSukumar Swaminathan uint32_t ub_timer; 1087fcf3ce44SJohn Forte 1088291a2b48SSukumar Swaminathan emlxs_ub_priv_t *ub_wait_head; /* Unsolicited IO received */ 1089291a2b48SSukumar Swaminathan /* before link up */ 1090291a2b48SSukumar Swaminathan emlxs_ub_priv_t *ub_wait_tail; /* Unsolicited IO received */ 1091291a2b48SSukumar Swaminathan /* before link up */ 1092fcf3ce44SJohn Forte 1093fcf3ce44SJohn Forte #ifdef DHCHAP_SUPPORT 1094291a2b48SSukumar Swaminathan emlxs_port_dhc_t port_dhc; 1095fcf3ce44SJohn Forte #endif /* DHCHAP_SUPPORT */ 1096fcf3ce44SJohn Forte 1097fcf3ce44SJohn Forte #ifdef SFCT_SUPPORT 10988f23e9faSHans Rosenfeld emlxs_memseg_t *fct_memseg; /* Array */ 10998f23e9faSHans Rosenfeld uint32_t fct_memseg_cnt; 11008f23e9faSHans Rosenfeld 11018f23e9faSHans Rosenfeld /* Default buffer counts */ 11028f23e9faSHans Rosenfeld #define FCT_BUF_COUNT_2K 16 11038f23e9faSHans Rosenfeld #define FCT_BUF_COUNT_4K 0 11048f23e9faSHans Rosenfeld #define FCT_BUF_COUNT_8K 16 11058f23e9faSHans Rosenfeld #define FCT_BUF_COUNT_16K 0 11068f23e9faSHans Rosenfeld #define FCT_BUF_COUNT_32K 0 11078f23e9faSHans Rosenfeld #define FCT_BUF_COUNT_64K 16 11088f23e9faSHans Rosenfeld #define FCT_BUF_COUNT_128K 16 11098f23e9faSHans Rosenfeld #define FCT_BUF_COUNT_256K 0 1110fcf3ce44SJohn Forte 1111291a2b48SSukumar Swaminathan char cfd_name[24]; 1112291a2b48SSukumar Swaminathan stmf_port_provider_t *port_provider; 1113291a2b48SSukumar Swaminathan fct_local_port_t *fct_port; 11148f23e9faSHans Rosenfeld uint8_t fct_els_only_bmap; 1115291a2b48SSukumar Swaminathan uint32_t fct_flags; 1116fcf3ce44SJohn Forte 1117e2ca2865SSukumar Swaminathan #define FCT_STATE_PORT_ONLINE 0x00000001 1118e2ca2865SSukumar Swaminathan #define FCT_STATE_NOT_ACKED 0x00000002 1119e2ca2865SSukumar Swaminathan #define FCT_STATE_LINK_UP 0x00000010 1120e2ca2865SSukumar Swaminathan #define FCT_STATE_LINK_UP_ACKED 0x00000020 11218f23e9faSHans Rosenfeld #define FCT_STATE_FLOGI_CMPL 0x00000040 1122fcf3ce44SJohn Forte 1123291a2b48SSukumar Swaminathan emlxs_tgtport_stat_t fct_stat; 1124291a2b48SSukumar Swaminathan 1125291a2b48SSukumar Swaminathan /* Used to save fct_cmd for deferred unsol ELS commands, except FLOGI */ 1126291a2b48SSukumar Swaminathan emlxs_buf_t *fct_wait_head; 1127291a2b48SSukumar Swaminathan emlxs_buf_t *fct_wait_tail; 1128291a2b48SSukumar Swaminathan 1129291a2b48SSukumar Swaminathan /* Used to save context for deferred unsol FLOGIs */ 1130291a2b48SSukumar Swaminathan fct_flogi_xchg_t fx; 1131e2ca2865SSukumar Swaminathan 1132291a2b48SSukumar Swaminathan #ifdef FCT_IO_TRACE 1133291a2b48SSukumar Swaminathan emlxs_iotrace_t *iotrace; 1134291a2b48SSukumar Swaminathan uint16_t iotrace_cnt; 1135291a2b48SSukumar Swaminathan uint16_t iotrace_index; 1136291a2b48SSukumar Swaminathan kmutex_t iotrace_mtx; 1137291a2b48SSukumar Swaminathan #endif /* FCT_IO_TRACE */ 1138291a2b48SSukumar Swaminathan 1139291a2b48SSukumar Swaminathan #endif /* SFCT_SUPPORT */ 1140291a2b48SSukumar Swaminathan 11418f23e9faSHans Rosenfeld uint32_t clean_address_timer; 11428f23e9faSHans Rosenfeld emlxs_buf_t *clean_address_sbp; 11438f23e9faSHans Rosenfeld 1144291a2b48SSukumar Swaminathan #ifdef SAN_DIAG_SUPPORT 1145291a2b48SSukumar Swaminathan uint8_t sd_io_latency_state; 1146291a2b48SSukumar Swaminathan #define SD_INVALID 0x00 1147291a2b48SSukumar Swaminathan #define SD_COLLECTING 0x01 1148291a2b48SSukumar Swaminathan #define SD_STOPPED 0x02 1149291a2b48SSukumar Swaminathan 1150291a2b48SSukumar Swaminathan /* SD event management list */ 115182527734SSukumar Swaminathan uint32_t sd_event_mask; /* bit-mask */ 1152291a2b48SSukumar Swaminathan emlxs_dfc_event_t sd_events[MAX_DFC_EVENTS]; 1153291a2b48SSukumar Swaminathan #endif 1154fcf3ce44SJohn Forte 1155a9800bebSGarrett D'Amore } emlxs_port_t; 1156fcf3ce44SJohn Forte 1157fcf3ce44SJohn Forte 1158fcf3ce44SJohn Forte /* Host Attn reg */ 115982527734SSukumar Swaminathan #define FC_HA_REG(_hba) ((volatile uint32_t *) \ 116082527734SSukumar Swaminathan ((_hba)->sli.sli3.ha_reg_addr)) 1161fcf3ce44SJohn Forte 1162fcf3ce44SJohn Forte /* Chip Attn reg */ 116382527734SSukumar Swaminathan #define FC_CA_REG(_hba) ((volatile uint32_t *) \ 116482527734SSukumar Swaminathan ((_hba)->sli.sli3.ca_reg_addr)) 1165fcf3ce44SJohn Forte 1166fcf3ce44SJohn Forte /* Host Status reg */ 116782527734SSukumar Swaminathan #define FC_HS_REG(_hba) ((volatile uint32_t *) \ 116882527734SSukumar Swaminathan ((_hba)->sli.sli3.hs_reg_addr)) 1169fcf3ce44SJohn Forte 1170fcf3ce44SJohn Forte /* Host Cntl reg */ 117182527734SSukumar Swaminathan #define FC_HC_REG(_hba) ((volatile uint32_t *) \ 117282527734SSukumar Swaminathan ((_hba)->sli.sli3.hc_reg_addr)) 1173fcf3ce44SJohn Forte 1174fcf3ce44SJohn Forte /* BIU Configuration reg */ 117582527734SSukumar Swaminathan #define FC_BC_REG(_hba) ((volatile uint32_t *) \ 117682527734SSukumar Swaminathan ((_hba)->sli.sli3.bc_reg_addr)) 1177fcf3ce44SJohn Forte 1178fcf3ce44SJohn Forte /* Used by SBUS adapter */ 1179fcf3ce44SJohn Forte /* TITAN Cntl reg */ 118082527734SSukumar Swaminathan #define FC_SHC_REG(_hba) ((volatile uint32_t *) \ 118182527734SSukumar Swaminathan ((_hba)->sli.sli3.shc_reg_addr)) 1182fcf3ce44SJohn Forte 1183fcf3ce44SJohn Forte /* TITAN Status reg */ 118482527734SSukumar Swaminathan #define FC_SHS_REG(_hba) ((volatile uint32_t *) \ 118582527734SSukumar Swaminathan ((_hba)->sli.sli3.shs_reg_addr)) 1186fcf3ce44SJohn Forte 1187fcf3ce44SJohn Forte /* TITAN Update reg */ 118882527734SSukumar Swaminathan #define FC_SHU_REG(_hba) ((volatile uint32_t *) \ 118982527734SSukumar Swaminathan ((_hba)->sli.sli3.shu_reg_addr)) 119082527734SSukumar Swaminathan 119182527734SSukumar Swaminathan /* MPU Semaphore reg */ 119282527734SSukumar Swaminathan #define FC_SEMA_REG(_hba) ((volatile uint32_t *)\ 119382527734SSukumar Swaminathan ((_hba)->sli.sli4.MPUEPSemaphore_reg_addr)) 119482527734SSukumar Swaminathan 119582527734SSukumar Swaminathan /* Bootstrap Mailbox Doorbell reg */ 119682527734SSukumar Swaminathan #define FC_MBDB_REG(_hba) ((volatile uint32_t *) \ 119782527734SSukumar Swaminathan ((_hba)->sli.sli4.MBDB_reg_addr)) 119882527734SSukumar Swaminathan 119982527734SSukumar Swaminathan /* MQ Doorbell reg */ 120082527734SSukumar Swaminathan #define FC_MQDB_REG(_hba) ((volatile uint32_t *) \ 120182527734SSukumar Swaminathan ((_hba)->sli.sli4.MQDB_reg_addr)) 1202fcf3ce44SJohn Forte 120382527734SSukumar Swaminathan /* CQ Doorbell reg */ 120482527734SSukumar Swaminathan #define FC_CQDB_REG(_hba) ((volatile uint32_t *) \ 120582527734SSukumar Swaminathan ((_hba)->sli.sli4.CQDB_reg_addr)) 1206fcf3ce44SJohn Forte 120782527734SSukumar Swaminathan /* WQ Doorbell reg */ 120882527734SSukumar Swaminathan #define FC_WQDB_REG(_hba) ((volatile uint32_t *) \ 120982527734SSukumar Swaminathan ((_hba)->sli.sli4.WQDB_reg_addr)) 1210fcf3ce44SJohn Forte 121182527734SSukumar Swaminathan /* RQ Doorbell reg */ 121282527734SSukumar Swaminathan #define FC_RQDB_REG(_hba) ((volatile uint32_t *) \ 121382527734SSukumar Swaminathan ((_hba)->sli.sli4.RQDB_reg_addr)) 121482527734SSukumar Swaminathan 121582527734SSukumar Swaminathan 121682527734SSukumar Swaminathan #define FC_SLIM2_MAILBOX(_hba) ((MAILBOX *)(_hba)->sli.sli3.slim2.virt) 121782527734SSukumar Swaminathan 121882527734SSukumar Swaminathan #define FC_SLIM1_MAILBOX(_hba) ((MAILBOX *)(_hba)->sli.sli3.slim_addr) 1219fcf3ce44SJohn Forte 1220fcf3ce44SJohn Forte #define FC_MAILBOX(_hba) (((_hba)->flag & FC_SLIM2_MODE) ? \ 1221291a2b48SSukumar Swaminathan FC_SLIM2_MAILBOX(_hba) : FC_SLIM1_MAILBOX(_hba)) 1222291a2b48SSukumar Swaminathan 1223291a2b48SSukumar Swaminathan #define WRITE_CSR_REG(_hba, _regp, _value) ddi_put32(\ 122482527734SSukumar Swaminathan (_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp), \ 122582527734SSukumar Swaminathan (uint32_t)(_value)) 1226291a2b48SSukumar Swaminathan 1227291a2b48SSukumar Swaminathan #define READ_CSR_REG(_hba, _regp) ddi_get32(\ 122882527734SSukumar Swaminathan (_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp)) 1229291a2b48SSukumar Swaminathan 1230291a2b48SSukumar Swaminathan #define WRITE_SLIM_ADDR(_hba, _regp, _value) ddi_put32(\ 123182527734SSukumar Swaminathan (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp), \ 123282527734SSukumar Swaminathan (uint32_t)(_value)) 1233291a2b48SSukumar Swaminathan 1234291a2b48SSukumar Swaminathan #define READ_SLIM_ADDR(_hba, _regp) ddi_get32(\ 123582527734SSukumar Swaminathan (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp)) 1236291a2b48SSukumar Swaminathan 1237291a2b48SSukumar Swaminathan #define WRITE_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_put32(\ 123882527734SSukumar Swaminathan (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \ 123982527734SSukumar Swaminathan (uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR) 1240291a2b48SSukumar Swaminathan 1241291a2b48SSukumar Swaminathan #define READ_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_get32(\ 124282527734SSukumar Swaminathan (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \ 124382527734SSukumar Swaminathan (uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR) 1244fcf3ce44SJohn Forte 1245fcf3ce44SJohn Forte /* Used by SBUS adapter */ 1246291a2b48SSukumar Swaminathan #define WRITE_SBUS_CSR_REG(_hba, _regp, _value) ddi_put32(\ 124782527734SSukumar Swaminathan (_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp), \ 124882527734SSukumar Swaminathan (uint32_t)(_value)) 1249291a2b48SSukumar Swaminathan 1250291a2b48SSukumar Swaminathan #define READ_SBUS_CSR_REG(_hba, _regp) ddi_get32(\ 125182527734SSukumar Swaminathan (_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp)) 1252291a2b48SSukumar Swaminathan 1253291a2b48SSukumar Swaminathan #define SBUS_WRITE_FLASH_COPY(_hba, _offset, _value) ddi_put8(\ 125482527734SSukumar Swaminathan (_hba)->sli.sli3.sbus_flash_acc_handle, \ 125582527734SSukumar Swaminathan (uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \ 125682527734SSukumar Swaminathan (_offset)), (uint8_t)(_value)) 1257fcf3ce44SJohn Forte 1258291a2b48SSukumar Swaminathan #define SBUS_READ_FLASH_COPY(_hba, _offset) ddi_get8(\ 125982527734SSukumar Swaminathan (_hba)->sli.sli3.sbus_flash_acc_handle, \ 126082527734SSukumar Swaminathan (uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \ 126182527734SSukumar Swaminathan (_offset))) 126282527734SSukumar Swaminathan 126382527734SSukumar Swaminathan /* SLI4 registers */ 12648f23e9faSHans Rosenfeld #define WRITE_BAR0_REG(_hba, _regp, _value) ddi_put32(\ 12658f23e9faSHans Rosenfeld (_hba)->sli.sli4.bar0_acc_handle, (uint32_t *)(_regp), \ 12668f23e9faSHans Rosenfeld (uint32_t)(_value)) 12678f23e9faSHans Rosenfeld 12688f23e9faSHans Rosenfeld #define READ_BAR0_REG(_hba, _regp) ddi_get32(\ 12698f23e9faSHans Rosenfeld (_hba)->sli.sli4.bar0_acc_handle, (uint32_t *)(_regp)) 12708f23e9faSHans Rosenfeld 127182527734SSukumar Swaminathan #define WRITE_BAR1_REG(_hba, _regp, _value) ddi_put32(\ 127282527734SSukumar Swaminathan (_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp), \ 127382527734SSukumar Swaminathan (uint32_t)(_value)) 127482527734SSukumar Swaminathan 127582527734SSukumar Swaminathan #define READ_BAR1_REG(_hba, _regp) ddi_get32(\ 127682527734SSukumar Swaminathan (_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp)) 127782527734SSukumar Swaminathan 127882527734SSukumar Swaminathan #define WRITE_BAR2_REG(_hba, _regp, _value) ddi_put32(\ 127982527734SSukumar Swaminathan (_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp), \ 128082527734SSukumar Swaminathan (uint32_t)(_value)) 1281fcf3ce44SJohn Forte 128282527734SSukumar Swaminathan #define READ_BAR2_REG(_hba, _regp) ddi_get32(\ 128382527734SSukumar Swaminathan (_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp)) 128482527734SSukumar Swaminathan 128582527734SSukumar Swaminathan 128682527734SSukumar Swaminathan #define EMLXS_STATE_CHANGE(_hba, _state)\ 1287fcf3ce44SJohn Forte { \ 1288fcf3ce44SJohn Forte mutex_enter(&EMLXS_PORT_LOCK); \ 128982527734SSukumar Swaminathan EMLXS_STATE_CHANGE_LOCKED((_hba), (_state)); \ 1290fcf3ce44SJohn Forte mutex_exit(&EMLXS_PORT_LOCK); \ 1291fcf3ce44SJohn Forte } 1292fcf3ce44SJohn Forte 1293fcf3ce44SJohn Forte /* Used when EMLXS_PORT_LOCK is already held */ 129482527734SSukumar Swaminathan #define EMLXS_STATE_CHANGE_LOCKED(_hba, _state) \ 1295fcf3ce44SJohn Forte { \ 1296fcf3ce44SJohn Forte if ((_hba)->state != (_state)) \ 1297fcf3ce44SJohn Forte { \ 1298fcf3ce44SJohn Forte uint32_t _st = _state; \ 1299fcf3ce44SJohn Forte EMLXS_MSGF(EMLXS_CONTEXT, \ 1300fcf3ce44SJohn Forte &emlxs_state_msg, "%s --> %s", \ 1301fcf3ce44SJohn Forte emlxs_ffstate_xlate((_hba)->state), \ 1302fcf3ce44SJohn Forte emlxs_ffstate_xlate(_state)); \ 130382527734SSukumar Swaminathan (_hba)->state = (_state); \ 130482527734SSukumar Swaminathan if ((_st) == FC_ERROR) \ 1305fcf3ce44SJohn Forte { \ 1306fcf3ce44SJohn Forte (_hba)->flag |= FC_HARDWARE_ERROR; \ 1307fcf3ce44SJohn Forte } \ 1308fcf3ce44SJohn Forte } \ 1309fcf3ce44SJohn Forte } 1310fcf3ce44SJohn Forte 131182527734SSukumar Swaminathan #ifdef FMA_SUPPORT 131282527734SSukumar Swaminathan #define EMLXS_CHK_ACC_HANDLE(_hba, _acc) \ 131382527734SSukumar Swaminathan if (emlxs_fm_check_acc_handle(_hba, _acc) != DDI_FM_OK) { \ 131482527734SSukumar Swaminathan EMLXS_MSGF(EMLXS_CONTEXT, \ 131582527734SSukumar Swaminathan &emlxs_invalid_access_handle_msg, NULL); \ 131682527734SSukumar Swaminathan } 131782527734SSukumar Swaminathan #endif /* FMA_SUPPORT */ 131882527734SSukumar Swaminathan 1319fcf3ce44SJohn Forte /* 1320fcf3ce44SJohn Forte * This is the HBA control area for the adapter 1321fcf3ce44SJohn Forte */ 1322fcf3ce44SJohn Forte 1323fcf3ce44SJohn Forte #ifdef MODSYM_SUPPORT 1324fcf3ce44SJohn Forte 1325291a2b48SSukumar Swaminathan typedef struct emlxs_modsym 1326291a2b48SSukumar Swaminathan { 1327291a2b48SSukumar Swaminathan ddi_modhandle_t mod_fctl; /* For Leadville */ 1328fcf3ce44SJohn Forte 1329fcf3ce44SJohn Forte /* Leadville (fctl) */ 1330291a2b48SSukumar Swaminathan int (*fc_fca_attach)(dev_info_t *, fc_fca_tran_t *); 1331291a2b48SSukumar Swaminathan int (*fc_fca_detach)(dev_info_t *); 1332291a2b48SSukumar Swaminathan int (*fc_fca_init)(struct dev_ops *); 1333fcf3ce44SJohn Forte 1334fcf3ce44SJohn Forte #ifdef SFCT_SUPPORT 133582527734SSukumar Swaminathan uint32_t fct_modopen; 133682527734SSukumar Swaminathan uint32_t reserved; /* Padding for alignment */ 133782527734SSukumar Swaminathan 1338291a2b48SSukumar Swaminathan ddi_modhandle_t mod_fct; /* For Comstar */ 1339291a2b48SSukumar Swaminathan ddi_modhandle_t mod_stmf; /* For Comstar */ 1340fcf3ce44SJohn Forte 1341fcf3ce44SJohn Forte /* Comstar (fct) */ 1342291a2b48SSukumar Swaminathan void* (*fct_alloc)(fct_struct_id_t, int, int); 1343291a2b48SSukumar Swaminathan void (*fct_free)(void *); 1344291a2b48SSukumar Swaminathan void* (*fct_scsi_task_alloc)(void *, uint16_t, uint32_t, uint8_t *, 1345291a2b48SSukumar Swaminathan uint16_t, uint16_t); 1346291a2b48SSukumar Swaminathan int (*fct_register_local_port)(fct_local_port_t *); 1347291a2b48SSukumar Swaminathan void (*fct_deregister_local_port)(fct_local_port_t *); 1348291a2b48SSukumar Swaminathan void (*fct_handle_event)(fct_local_port_t *, int, uint32_t, caddr_t); 1349291a2b48SSukumar Swaminathan void (*fct_post_rcvd_cmd)(fct_cmd_t *, stmf_data_buf_t *); 1350291a2b48SSukumar Swaminathan void (*fct_ctl)(void *, int, void *); 1351291a2b48SSukumar Swaminathan void (*fct_queue_cmd_for_termination)(fct_cmd_t *, fct_status_t); 1352291a2b48SSukumar Swaminathan void (*fct_send_response_done)(fct_cmd_t *, fct_status_t, uint32_t); 1353291a2b48SSukumar Swaminathan void (*fct_send_cmd_done)(fct_cmd_t *, fct_status_t, uint32_t); 1354291a2b48SSukumar Swaminathan void (*fct_scsi_data_xfer_done)(fct_cmd_t *, stmf_data_buf_t *, 1355291a2b48SSukumar Swaminathan uint32_t); 1356291a2b48SSukumar Swaminathan fct_status_t (*fct_port_shutdown) 1357291a2b48SSukumar Swaminathan (fct_local_port_t *, uint32_t, char *); 1358291a2b48SSukumar Swaminathan fct_status_t (*fct_port_initialize) 1359291a2b48SSukumar Swaminathan (fct_local_port_t *, uint32_t, char *); 1360291a2b48SSukumar Swaminathan void (*fct_cmd_fca_aborted) 1361291a2b48SSukumar Swaminathan (fct_cmd_t *, fct_status_t, int); 1362291a2b48SSukumar Swaminathan fct_status_t (*fct_handle_rcvd_flogi) 1363291a2b48SSukumar Swaminathan (fct_local_port_t *, fct_flogi_xchg_t *); 1364fcf3ce44SJohn Forte 1365fcf3ce44SJohn Forte /* Comstar (stmf) */ 1366291a2b48SSukumar Swaminathan void* (*stmf_alloc)(stmf_struct_id_t, int, int); 1367291a2b48SSukumar Swaminathan void (*stmf_free)(void *); 1368291a2b48SSukumar Swaminathan void (*stmf_deregister_port_provider) (stmf_port_provider_t *); 1369291a2b48SSukumar Swaminathan int (*stmf_register_port_provider) (stmf_port_provider_t *); 1370291a2b48SSukumar Swaminathan #endif /* SFCT_SUPPORT */ 1371fcf3ce44SJohn Forte } emlxs_modsym_t; 1372fcf3ce44SJohn Forte extern emlxs_modsym_t emlxs_modsym; 1373fcf3ce44SJohn Forte 1374291a2b48SSukumar Swaminathan #define MODSYM(_f) emlxs_modsym._f 1375fcf3ce44SJohn Forte 1376fcf3ce44SJohn Forte #else 1377fcf3ce44SJohn Forte 1378291a2b48SSukumar Swaminathan #define MODSYM(_f) _f 1379fcf3ce44SJohn Forte 1380291a2b48SSukumar Swaminathan #endif /* MODSYM_SUPPORT */ 1381fcf3ce44SJohn Forte 1382fcf3ce44SJohn Forte 1383fcf3ce44SJohn Forte 138482527734SSukumar Swaminathan typedef struct RPIHdrTmplate 138582527734SSukumar Swaminathan { 138682527734SSukumar Swaminathan uint32_t Word[16]; /* 64 bytes */ 138782527734SSukumar Swaminathan } RPIHdrTmplate_t; 138882527734SSukumar Swaminathan 1389a9800bebSGarrett D'Amore 139082527734SSukumar Swaminathan typedef struct EQ_DESC 139182527734SSukumar Swaminathan { 139282527734SSukumar Swaminathan uint16_t host_index; 139382527734SSukumar Swaminathan uint16_t max_index; 139482527734SSukumar Swaminathan uint16_t qid; 139582527734SSukumar Swaminathan uint16_t msix_vector; 139682527734SSukumar Swaminathan kmutex_t lastwq_lock; 139782527734SSukumar Swaminathan uint16_t lastwq; 139882527734SSukumar Swaminathan MBUF_INFO addr; 13998f23e9faSHans Rosenfeld 1400*e2d1a434SCarsten Grzemba uint16_t qe_valid; 14018f23e9faSHans Rosenfeld /* Statistics */ 14028f23e9faSHans Rosenfeld uint32_t max_proc; 14038f23e9faSHans Rosenfeld uint32_t isr_count; 14048f23e9faSHans Rosenfeld uint32_t num_proc; 140582527734SSukumar Swaminathan } EQ_DESC_t; 140682527734SSukumar Swaminathan 1407a9800bebSGarrett D'Amore 140882527734SSukumar Swaminathan typedef struct CQ_DESC 140982527734SSukumar Swaminathan { 141082527734SSukumar Swaminathan uint16_t host_index; 141182527734SSukumar Swaminathan uint16_t max_index; 141282527734SSukumar Swaminathan uint16_t qid; 141382527734SSukumar Swaminathan uint16_t eqid; 141482527734SSukumar Swaminathan uint16_t type; 141582527734SSukumar Swaminathan #define EMLXS_CQ_TYPE_GROUP1 1 /* associated with a MQ and async events */ 141682527734SSukumar Swaminathan #define EMLXS_CQ_TYPE_GROUP2 2 /* associated with a WQ and RQ */ 1417*e2d1a434SCarsten Grzemba 1418*e2d1a434SCarsten Grzemba /* 1419*e2d1a434SCarsten Grzemba * queue entry autovalid logic on if_type == 6 1420*e2d1a434SCarsten Grzemba * this value toggles for each iteration of the queue (host_index==0) 1421*e2d1a434SCarsten Grzemba * a queue entry is valid when cqe valid bit matches this value 1422*e2d1a434SCarsten Grzemba */ 1423*e2d1a434SCarsten Grzemba uint16_t qe_valid; 142482527734SSukumar Swaminathan 142582527734SSukumar Swaminathan MBUF_INFO addr; 142682527734SSukumar Swaminathan CHANNEL *channelp; /* ptr to CHANNEL associated with CQ */ 142782527734SSukumar Swaminathan 14288f23e9faSHans Rosenfeld /* Statistics */ 14298f23e9faSHans Rosenfeld uint32_t max_proc; 14308f23e9faSHans Rosenfeld uint32_t isr_count; 14318f23e9faSHans Rosenfeld uint32_t num_proc; 143282527734SSukumar Swaminathan } CQ_DESC_t; 143382527734SSukumar Swaminathan 1434a9800bebSGarrett D'Amore 143582527734SSukumar Swaminathan typedef struct WQ_DESC 143682527734SSukumar Swaminathan { 143782527734SSukumar Swaminathan uint16_t host_index; 143882527734SSukumar Swaminathan uint16_t max_index; 143982527734SSukumar Swaminathan uint16_t port_index; 144082527734SSukumar Swaminathan uint16_t release_depth; 144182527734SSukumar Swaminathan #define WQE_RELEASE_DEPTH (8 * EMLXS_NUM_WQ_PAGES) 144282527734SSukumar Swaminathan uint16_t qid; 144382527734SSukumar Swaminathan uint16_t cqid; 144482527734SSukumar Swaminathan MBUF_INFO addr; 14458f23e9faSHans Rosenfeld 14468f23e9faSHans Rosenfeld /* Statistics */ 14478f23e9faSHans Rosenfeld uint32_t num_proc; 14488f23e9faSHans Rosenfeld uint32_t num_busy; 144982527734SSukumar Swaminathan } WQ_DESC_t; 145082527734SSukumar Swaminathan 1451a9800bebSGarrett D'Amore 145282527734SSukumar Swaminathan typedef struct RQ_DESC 145382527734SSukumar Swaminathan { 145482527734SSukumar Swaminathan uint16_t host_index; 145582527734SSukumar Swaminathan uint16_t max_index; 145682527734SSukumar Swaminathan uint16_t qid; 145782527734SSukumar Swaminathan uint16_t cqid; 145882527734SSukumar Swaminathan 145982527734SSukumar Swaminathan MBUF_INFO addr; 1460b3660a96SSukumar Swaminathan MBUF_INFO rqb[RQ_DEPTH]; 146182527734SSukumar Swaminathan 146282527734SSukumar Swaminathan kmutex_t lock; 146382527734SSukumar Swaminathan 14648f23e9faSHans Rosenfeld /* Statistics */ 14658f23e9faSHans Rosenfeld uint32_t num_proc; 146682527734SSukumar Swaminathan } RQ_DESC_t; 146782527734SSukumar Swaminathan 146882527734SSukumar Swaminathan 146982527734SSukumar Swaminathan typedef struct RXQ_DESC 147082527734SSukumar Swaminathan { 147182527734SSukumar Swaminathan kmutex_t lock; 147282527734SSukumar Swaminathan emlxs_queue_t active; 147382527734SSukumar Swaminathan 147482527734SSukumar Swaminathan } RXQ_DESC_t; 147582527734SSukumar Swaminathan 147682527734SSukumar Swaminathan 147782527734SSukumar Swaminathan typedef struct MQ_DESC 147882527734SSukumar Swaminathan { 147982527734SSukumar Swaminathan uint16_t host_index; 148082527734SSukumar Swaminathan uint16_t max_index; 148182527734SSukumar Swaminathan uint16_t qid; 148282527734SSukumar Swaminathan uint16_t cqid; 148382527734SSukumar Swaminathan MBUF_INFO addr; 148482527734SSukumar Swaminathan } MQ_DESC_t; 148582527734SSukumar Swaminathan 1486a9800bebSGarrett D'Amore 148782527734SSukumar Swaminathan /* Define the number of queues the driver will be using */ 148882527734SSukumar Swaminathan #define EMLXS_MAX_EQS EMLXS_MSI_MAX_INTRS 14898f23e9faSHans Rosenfeld #define EMLXS_MAX_WQS EMLXS_MAX_WQS_PER_EQ * EMLXS_MAX_EQS 149082527734SSukumar Swaminathan #define EMLXS_MAX_RQS 2 /* ONLY 1 pair is allowed */ 149182527734SSukumar Swaminathan #define EMLXS_MAX_MQS 1 149282527734SSukumar Swaminathan 149382527734SSukumar Swaminathan /* One CQ for each WQ & (RQ pair) plus one for the MQ */ 149482527734SSukumar Swaminathan #define EMLXS_MAX_CQS (EMLXS_MAX_WQS + (EMLXS_MAX_RQS/2) + 1) 149582527734SSukumar Swaminathan 149682527734SSukumar Swaminathan /* The First CQ created is ALWAYS for mbox / event handling */ 149782527734SSukumar Swaminathan #define EMLXS_CQ_MBOX 0 149882527734SSukumar Swaminathan 149982527734SSukumar Swaminathan /* The Second CQ created is ALWAYS for unsol rcv handling */ 150082527734SSukumar Swaminathan /* At this time we are allowing ONLY 1 pair of RQs */ 150182527734SSukumar Swaminathan #define EMLXS_CQ_RCV 1 150282527734SSukumar Swaminathan 150382527734SSukumar Swaminathan /* The remaining CQs are for WQ completions */ 150482527734SSukumar Swaminathan #define EMLXS_CQ_OFFSET_WQ 2 150582527734SSukumar Swaminathan 150682527734SSukumar Swaminathan 150782527734SSukumar Swaminathan /* FCFI RQ Configuration */ 150882527734SSukumar Swaminathan #define EMLXS_FCFI_RQ0_INDEX 0 150982527734SSukumar Swaminathan #define EMLXS_FCFI_RQ0_RMASK 0 /* match all */ 151082527734SSukumar Swaminathan #define EMLXS_FCFI_RQ0_RCTL 0 /* match all */ 151182527734SSukumar Swaminathan #define EMLXS_FCFI_RQ0_TMASK 0 /* match all */ 151282527734SSukumar Swaminathan #define EMLXS_FCFI_RQ0_TYPE 0 /* match all */ 151382527734SSukumar Swaminathan 151482527734SSukumar Swaminathan #define EMLXS_RXQ_ELS 0 151582527734SSukumar Swaminathan #define EMLXS_RXQ_CT 1 151682527734SSukumar Swaminathan #define EMLXS_MAX_RXQS 2 151782527734SSukumar Swaminathan 1518291a2b48SSukumar Swaminathan #define PCI_CONFIG_SIZE 0x80 1519fcf3ce44SJohn Forte 152082527734SSukumar Swaminathan typedef struct emlxs_sli3 152182527734SSukumar Swaminathan { 152282527734SSukumar Swaminathan /* SLIM management */ 152382527734SSukumar Swaminathan MATCHMAP slim2; 152482527734SSukumar Swaminathan 152582527734SSukumar Swaminathan /* HBQ management */ 152682527734SSukumar Swaminathan uint32_t hbq_count; /* Total number of HBQs */ 152782527734SSukumar Swaminathan /* configured */ 152882527734SSukumar Swaminathan HBQ_INIT_t hbq_table[EMLXS_NUM_HBQ]; 152982527734SSukumar Swaminathan 153082527734SSukumar Swaminathan /* Adapter memory management */ 153182527734SSukumar Swaminathan caddr_t csr_addr; 153282527734SSukumar Swaminathan caddr_t slim_addr; 153382527734SSukumar Swaminathan ddi_acc_handle_t csr_acc_handle; 153482527734SSukumar Swaminathan ddi_acc_handle_t slim_acc_handle; 153582527734SSukumar Swaminathan 153682527734SSukumar Swaminathan /* SBUS adapter management */ 153782527734SSukumar Swaminathan caddr_t sbus_flash_addr; /* Virt addr of R/W */ 153882527734SSukumar Swaminathan /* Flash */ 153982527734SSukumar Swaminathan caddr_t sbus_core_addr; /* Virt addr of TITAN */ 154082527734SSukumar Swaminathan /* CORE */ 154182527734SSukumar Swaminathan caddr_t sbus_csr_addr; /* Virt addr of TITAN */ 154282527734SSukumar Swaminathan /* CSR */ 154382527734SSukumar Swaminathan ddi_acc_handle_t sbus_flash_acc_handle; 154482527734SSukumar Swaminathan ddi_acc_handle_t sbus_core_acc_handle; 154582527734SSukumar Swaminathan ddi_acc_handle_t sbus_csr_handle; 154682527734SSukumar Swaminathan 154782527734SSukumar Swaminathan /* SLI 2/3 Adapter register management */ 154882527734SSukumar Swaminathan uint32_t *bc_reg_addr; /* virtual offset for BIU */ 154982527734SSukumar Swaminathan /* config reg */ 155082527734SSukumar Swaminathan uint32_t *ha_reg_addr; /* virtual offset for host */ 155182527734SSukumar Swaminathan /* attn reg */ 155282527734SSukumar Swaminathan uint32_t *hc_reg_addr; /* virtual offset for host */ 155382527734SSukumar Swaminathan /* ctl reg */ 155482527734SSukumar Swaminathan uint32_t *ca_reg_addr; /* virtual offset for FF */ 155582527734SSukumar Swaminathan /* attn reg */ 155682527734SSukumar Swaminathan uint32_t *hs_reg_addr; /* virtual offset for */ 155782527734SSukumar Swaminathan /* status reg */ 155882527734SSukumar Swaminathan uint32_t *shc_reg_addr; /* virtual offset for SBUS */ 155982527734SSukumar Swaminathan /* Ctrl reg */ 156082527734SSukumar Swaminathan uint32_t *shs_reg_addr; /* virtual offset for SBUS */ 156182527734SSukumar Swaminathan /* Status reg */ 156282527734SSukumar Swaminathan uint32_t *shu_reg_addr; /* virtual offset for SBUS */ 156382527734SSukumar Swaminathan /* Update reg */ 156482527734SSukumar Swaminathan uint16_t hgp_ring_offset; 156582527734SSukumar Swaminathan uint16_t hgp_hbq_offset; 156682527734SSukumar Swaminathan uint16_t iocb_cmd_size; 156782527734SSukumar Swaminathan uint16_t iocb_rsp_size; 156882527734SSukumar Swaminathan uint32_t hc_copy; /* local copy of HC register */ 156982527734SSukumar Swaminathan 157082527734SSukumar Swaminathan /* Ring management */ 157182527734SSukumar Swaminathan uint32_t ring_count; 157282527734SSukumar Swaminathan emlxs_ring_t ring[MAX_RINGS]; 157382527734SSukumar Swaminathan kmutex_t ring_cmd_lock[MAX_RINGS]; 157482527734SSukumar Swaminathan uint8_t ring_masks[4]; /* number of masks/rings used */ 157582527734SSukumar Swaminathan uint8_t ring_rval[6]; 157682527734SSukumar Swaminathan uint8_t ring_rmask[6]; 157782527734SSukumar Swaminathan uint8_t ring_tval[6]; 157882527734SSukumar Swaminathan uint8_t ring_tmask[6]; 157982527734SSukumar Swaminathan 158082527734SSukumar Swaminathan /* Protected by EMLXS_FCTAB_LOCK */ 15818f23e9faSHans Rosenfeld MATCHMAP **bpl_table; /* iotag table for */ 158282527734SSukumar Swaminathan /* bpl buffers */ 158382527734SSukumar Swaminathan uint32_t mem_bpl_size; 158482527734SSukumar Swaminathan } emlxs_sli3_t; 158582527734SSukumar Swaminathan 158682527734SSukumar Swaminathan typedef struct emlxs_sli4 158782527734SSukumar Swaminathan { 158882527734SSukumar Swaminathan MATCHMAP bootstrapmb; 15898f23e9faSHans Rosenfeld caddr_t bar0_addr; 159082527734SSukumar Swaminathan caddr_t bar1_addr; 159182527734SSukumar Swaminathan caddr_t bar2_addr; 15928f23e9faSHans Rosenfeld ddi_acc_handle_t bar0_acc_handle; 159382527734SSukumar Swaminathan ddi_acc_handle_t bar1_acc_handle; 159482527734SSukumar Swaminathan ddi_acc_handle_t bar2_acc_handle; 159582527734SSukumar Swaminathan 159682527734SSukumar Swaminathan /* SLI4 Adapter register management */ 159782527734SSukumar Swaminathan uint32_t *MPUEPSemaphore_reg_addr; 159882527734SSukumar Swaminathan uint32_t *MBDB_reg_addr; 159982527734SSukumar Swaminathan 160082527734SSukumar Swaminathan uint32_t *CQDB_reg_addr; 1601*e2d1a434SCarsten Grzemba uint32_t *EQDB_reg_addr; 160282527734SSukumar Swaminathan uint32_t *MQDB_reg_addr; 160382527734SSukumar Swaminathan uint32_t *WQDB_reg_addr; 160482527734SSukumar Swaminathan uint32_t *RQDB_reg_addr; 16058f23e9faSHans Rosenfeld uint32_t *SEMA_reg_addr; 16068f23e9faSHans Rosenfeld uint32_t *STATUS_reg_addr; 16078f23e9faSHans Rosenfeld uint32_t *CNTL_reg_addr; 16088f23e9faSHans Rosenfeld uint32_t *ERR1_reg_addr; 16098f23e9faSHans Rosenfeld uint32_t *ERR2_reg_addr; 16108f23e9faSHans Rosenfeld uint32_t *PHYSDEV_reg_addr; 161182527734SSukumar Swaminathan 161282527734SSukumar Swaminathan uint32_t flag; 1613a9800bebSGarrett D'Amore #define EMLXS_SLI4_INTR_ENABLED 0x00000001 1614a9800bebSGarrett D'Amore #define EMLXS_SLI4_HW_ERROR 0x00000002 1615a9800bebSGarrett D'Amore #define EMLXS_SLI4_DOWN_LINK 0x00000004 16168f23e9faSHans Rosenfeld #define EMLXS_SLI4_PHON 0x00000008 16178f23e9faSHans Rosenfeld #define EMLXS_SLI4_PHWQ 0x00000010 16188f23e9faSHans Rosenfeld #define EMLXS_SLI4_NULL_XRI 0x00000020 16198f23e9faSHans Rosenfeld 16208f23e9faSHans Rosenfeld #define EMLXS_SLI4_FCF_INIT 0x10000000 16218f23e9faSHans Rosenfeld #define EMLXS_SLI4_FCOE_MODE 0x80000000 16228f23e9faSHans Rosenfeld 16238f23e9faSHans Rosenfeld #define SLI4_FCOE_MODE (hba->sli.sli4.flag & EMLXS_SLI4_FCOE_MODE) 16248f23e9faSHans Rosenfeld #define SLI4_FC_MODE (!SLI4_FCOE_MODE) 16258f23e9faSHans Rosenfeld 16268f23e9faSHans Rosenfeld 162782527734SSukumar Swaminathan 162882527734SSukumar Swaminathan uint16_t XRICount; 16298f23e9faSHans Rosenfeld uint16_t XRIExtCount; 16308f23e9faSHans Rosenfeld uint16_t XRIExtSize; 16318f23e9faSHans Rosenfeld uint16_t XRIBase[MAX_EXTENTS]; 16328f23e9faSHans Rosenfeld 163382527734SSukumar Swaminathan uint16_t RPICount; 16348f23e9faSHans Rosenfeld uint16_t RPIExtCount; 16358f23e9faSHans Rosenfeld uint16_t RPIExtSize; 16368f23e9faSHans Rosenfeld uint16_t RPIBase[MAX_EXTENTS]; 16378f23e9faSHans Rosenfeld 163882527734SSukumar Swaminathan uint16_t VPICount; 16398f23e9faSHans Rosenfeld uint16_t VPIExtCount; 16408f23e9faSHans Rosenfeld uint16_t VPIExtSize; 16418f23e9faSHans Rosenfeld uint16_t VPIBase[MAX_EXTENTS]; 16428f23e9faSHans Rosenfeld 164382527734SSukumar Swaminathan uint16_t VFICount; 16448f23e9faSHans Rosenfeld uint16_t VFIExtCount; 16458f23e9faSHans Rosenfeld uint16_t VFIExtSize; 16468f23e9faSHans Rosenfeld uint16_t VFIBase[MAX_EXTENTS]; 16478f23e9faSHans Rosenfeld 164882527734SSukumar Swaminathan uint16_t FCFICount; 164982527734SSukumar Swaminathan 1650a9800bebSGarrett D'Amore kmutex_t fcf_lock; 1651a9800bebSGarrett D'Amore FCFTable_t fcftab; 1652a9800bebSGarrett D'Amore VFIobj_t *VFI_table; 165382527734SSukumar Swaminathan 165482527734SSukumar Swaminathan /* Save Config Region 23 info */ 165582527734SSukumar Swaminathan tlv_fcoe_t cfgFCOE; 165682527734SSukumar Swaminathan tlv_fcfconnectlist_t cfgFCF; 165782527734SSukumar Swaminathan 1658b3660a96SSukumar Swaminathan MBUF_INFO slim2; 165982527734SSukumar Swaminathan MBUF_INFO dump_region; 166082527734SSukumar Swaminathan #define EMLXS_DUMP_REGION_SIZE 1024 166182527734SSukumar Swaminathan 166282527734SSukumar Swaminathan RPIobj_t *RPIp; 166382527734SSukumar Swaminathan MBUF_INFO HeaderTmplate; 166482527734SSukumar Swaminathan XRIobj_t *XRIp; 1665b3660a96SSukumar Swaminathan 1666b3660a96SSukumar Swaminathan /* Double linked list for available XRIs */ 1667b3660a96SSukumar Swaminathan XRIobj_t *XRIfree_f; 1668b3660a96SSukumar Swaminathan XRIobj_t *XRIfree_b; 166982527734SSukumar Swaminathan uint32_t xrif_count; 167082527734SSukumar Swaminathan uint32_t mem_sgl_size; 167182527734SSukumar Swaminathan 167282527734SSukumar Swaminathan /* Double linked list for XRIs in use */ 167382527734SSukumar Swaminathan XRIobj_t *XRIinuse_f; 167482527734SSukumar Swaminathan XRIobj_t *XRIinuse_b; 167582527734SSukumar Swaminathan uint32_t xria_count; 167682527734SSukumar Swaminathan 1677a9800bebSGarrett D'Amore kmutex_t que_lock[EMLXS_MAX_WQS]; 167882527734SSukumar Swaminathan EQ_DESC_t eq[EMLXS_MAX_EQS]; 167982527734SSukumar Swaminathan CQ_DESC_t cq[EMLXS_MAX_CQS]; 168082527734SSukumar Swaminathan WQ_DESC_t wq[EMLXS_MAX_WQS]; 168182527734SSukumar Swaminathan RQ_DESC_t rq[EMLXS_MAX_RQS]; 168282527734SSukumar Swaminathan RXQ_DESC_t rxq[EMLXS_MAX_RXQS]; 16838f23e9faSHans Rosenfeld MQ_DESC_t mq; 16848f23e9faSHans Rosenfeld uint32_t que_stat_timer; 168582527734SSukumar Swaminathan 1686fe199829SSukumar Swaminathan uint32_t ue_mask_lo; 1687fe199829SSukumar Swaminathan uint32_t ue_mask_hi; 1688a9800bebSGarrett D'Amore 16898f23e9faSHans Rosenfeld sli_params_t param; 16908f23e9faSHans Rosenfeld 16918f23e9faSHans Rosenfeld uint8_t port_name[4]; 16928f23e9faSHans Rosenfeld uint32_t link_number; 16938f23e9faSHans Rosenfeld 169482527734SSukumar Swaminathan } emlxs_sli4_t; 169582527734SSukumar Swaminathan 169682527734SSukumar Swaminathan 169782527734SSukumar Swaminathan typedef struct emlxs_sli_api 169882527734SSukumar Swaminathan { 169982527734SSukumar Swaminathan int (*sli_map_hdw)(); 170082527734SSukumar Swaminathan void (*sli_unmap_hdw)(); 170182527734SSukumar Swaminathan int32_t (*sli_online)(); 170282527734SSukumar Swaminathan void (*sli_offline)(); 170382527734SSukumar Swaminathan uint32_t (*sli_hba_reset)(); 170482527734SSukumar Swaminathan void (*sli_hba_kill)(); 170582527734SSukumar Swaminathan void (*sli_issue_iocb_cmd)(); 170682527734SSukumar Swaminathan uint32_t (*sli_issue_mbox_cmd)(); 170782527734SSukumar Swaminathan uint32_t (*sli_prep_fct_iocb)(); 170882527734SSukumar Swaminathan uint32_t (*sli_prep_fcp_iocb)(); 170982527734SSukumar Swaminathan uint32_t (*sli_prep_ip_iocb)(); 171082527734SSukumar Swaminathan uint32_t (*sli_prep_els_iocb)(); 171182527734SSukumar Swaminathan uint32_t (*sli_prep_ct_iocb)(); 171282527734SSukumar Swaminathan void (*sli_poll_intr)(); 171382527734SSukumar Swaminathan int32_t (*sli_intx_intr)(); 171482527734SSukumar Swaminathan uint32_t (*sli_msi_intr)(); 171582527734SSukumar Swaminathan void (*sli_disable_intr)(); 171682527734SSukumar Swaminathan void (*sli_timer)(); 171782527734SSukumar Swaminathan void (*sli_poll_erratt)(); 17188f23e9faSHans Rosenfeld uint32_t (*sli_reg_did)(); 17198f23e9faSHans Rosenfeld uint32_t (*sli_unreg_node)(); 172082527734SSukumar Swaminathan 172182527734SSukumar Swaminathan } emlxs_sli_api_t; 172282527734SSukumar Swaminathan 172382527734SSukumar Swaminathan 1724291a2b48SSukumar Swaminathan typedef struct emlxs_hba 1725291a2b48SSukumar Swaminathan { 1726291a2b48SSukumar Swaminathan dev_info_t *dip; 1727291a2b48SSukumar Swaminathan int32_t emlxinst; 1728291a2b48SSukumar Swaminathan int32_t ddiinst; 172982527734SSukumar Swaminathan uint8_t pci_function_number; 173082527734SSukumar Swaminathan uint8_t pci_device_number; 173182527734SSukumar Swaminathan uint8_t pci_bus_number; 1732a9800bebSGarrett D'Amore uint8_t pci_cap_offset[PCI_CAP_MAX_PTR]; 17338f23e9faSHans Rosenfeld uint16_t pci_ecap_offset[PCI_EXT_CAP_MAX_PTR]; 1734a9800bebSGarrett D'Amore 1735291a2b48SSukumar Swaminathan #ifdef FMA_SUPPORT 1736291a2b48SSukumar Swaminathan int32_t fm_caps; /* FMA capabilities */ 1737291a2b48SSukumar Swaminathan #endif /* FMA_SUPPORT */ 1738291a2b48SSukumar Swaminathan fc_fca_tran_t *fca_tran; 1739fcf3ce44SJohn Forte 174062379b58SSukumar Swaminathan /* DMA attributes */ 174162379b58SSukumar Swaminathan ddi_dma_attr_t dma_attr; 174262379b58SSukumar Swaminathan ddi_dma_attr_t dma_attr_ro; 174362379b58SSukumar Swaminathan ddi_dma_attr_t dma_attr_1sg; 174462379b58SSukumar Swaminathan ddi_dma_attr_t dma_attr_fcip_rsp; 174562379b58SSukumar Swaminathan 1746fcf3ce44SJohn Forte /* HBA Info */ 1747291a2b48SSukumar Swaminathan emlxs_model_t model_info; 1748291a2b48SSukumar Swaminathan emlxs_vpd_t vpd; /* vital product data */ 1749291a2b48SSukumar Swaminathan NAME_TYPE wwnn; 1750291a2b48SSukumar Swaminathan NAME_TYPE wwpn; 1751291a2b48SSukumar Swaminathan char snn[256]; 1752291a2b48SSukumar Swaminathan char spn[256]; 1753291a2b48SSukumar Swaminathan PROG_ID load_list[MAX_LOAD_ENTRY]; 1754291a2b48SSukumar Swaminathan WAKE_UP_PARMS wakeup_parms; 1755291a2b48SSukumar Swaminathan uint32_t max_nodes; 1756291a2b48SSukumar Swaminathan uint32_t io_throttle; 1757291a2b48SSukumar Swaminathan uint32_t io_active; 1758291a2b48SSukumar Swaminathan uint32_t bus_type; 1759291a2b48SSukumar Swaminathan #define PCI_FC 0 1760fcf3ce44SJohn Forte #define SBUS_FC 1 17618f23e9faSHans Rosenfeld uint32_t sli_intf; 17628f23e9faSHans Rosenfeld #define SLI_INTF_VALID_MASK 0xe0000000 17638f23e9faSHans Rosenfeld #define SLI_INTF_VALID 0xc0000000 17648f23e9faSHans Rosenfeld 17658f23e9faSHans Rosenfeld #define SLI_INTF_HINT2_MASK 0x1f000000 17668f23e9faSHans Rosenfeld #define SLI_INTF_HINT2_0 0x00000000 17678f23e9faSHans Rosenfeld 17688f23e9faSHans Rosenfeld #define SLI_INTF_HINT1_MASK 0x00ff0000 17698f23e9faSHans Rosenfeld #define SLI_INTF_HINT1_0 0x00000000 17708f23e9faSHans Rosenfeld #define SLI_INTF_HINT1_1 0x00010000 17718f23e9faSHans Rosenfeld #define SLI_INTF_HINT1_2 0x00020000 17728f23e9faSHans Rosenfeld 17738f23e9faSHans Rosenfeld #define SLI_INTF_IF_TYPE_MASK 0x0000f000 17748f23e9faSHans Rosenfeld #define SLI_INTF_IF_TYPE_0 0x00000000 17758f23e9faSHans Rosenfeld #define SLI_INTF_IF_TYPE_1 0x00001000 17768f23e9faSHans Rosenfeld #define SLI_INTF_IF_TYPE_2 0x00002000 17778f23e9faSHans Rosenfeld #define SLI_INTF_IF_TYPE_3 0x00003000 1778*e2d1a434SCarsten Grzemba #define SLI_INTF_IF_TYPE_6 0x00006000 17798f23e9faSHans Rosenfeld 17808f23e9faSHans Rosenfeld #define SLI_INTF_FAMILY_MASK 0x00000f00 17818f23e9faSHans Rosenfeld #define SLI_INTF_FAMILY_BE2 0x00000000 17828f23e9faSHans Rosenfeld #define SLI_INTF_FAMILY_BE3 0x00000100 17838f23e9faSHans Rosenfeld #define SLI_INTF_FAMILY_LANCER_A 0x00000a00 17848f23e9faSHans Rosenfeld #define SLI_INTF_FAMILY_LANCER_B 0x00000b00 17858f23e9faSHans Rosenfeld 17868f23e9faSHans Rosenfeld #define SLI_INTF_SLI_REV_MASK 0x000000f0 17878f23e9faSHans Rosenfeld #define SLI_INTF_SLI_REV_NONE 0x00000000 17888f23e9faSHans Rosenfeld #define SLI_INTF_SLI_REV_3 0x00000030 17898f23e9faSHans Rosenfeld #define SLI_INTF_SLI_REV_4 0x00000040 17908f23e9faSHans Rosenfeld 17918f23e9faSHans Rosenfeld #define SLI_INTF_RESERVED1 0x0000000e 17928f23e9faSHans Rosenfeld 17938f23e9faSHans Rosenfeld #define SLI_INTF_FUNC_TYPE_MASK 0x00000001 17948f23e9faSHans Rosenfeld #define SLI_INTF_FUNC_PF 0x00000000 17958f23e9faSHans Rosenfeld #define SLI_INTF_FUNC_VF 0x00000001 1796fcf3ce44SJohn Forte 1797fcf3ce44SJohn Forte /* Link management */ 1798291a2b48SSukumar Swaminathan uint32_t link_event_tag; 1799291a2b48SSukumar Swaminathan uint8_t topology; 1800291a2b48SSukumar Swaminathan uint8_t linkspeed; 1801b3660a96SSukumar Swaminathan uint16_t qos_linkspeed; 1802291a2b48SSukumar Swaminathan uint32_t linkup_wait_flag; 1803291a2b48SSukumar Swaminathan kcondvar_t linkup_lock_cv; 1804291a2b48SSukumar Swaminathan kmutex_t linkup_lock; 1805fcf3ce44SJohn Forte 1806fcf3ce44SJohn Forte /* Memory Pool management */ 1807291a2b48SSukumar Swaminathan emlxs_memseg_t memseg[FC_MAX_SEG]; /* memory for buffer */ 1808291a2b48SSukumar Swaminathan /* structures */ 1809291a2b48SSukumar Swaminathan kmutex_t memget_lock; /* locks all memory pools get */ 1810291a2b48SSukumar Swaminathan kmutex_t memput_lock; /* locks all memory pools put */ 18118f23e9faSHans Rosenfeld uint32_t mem_timer; 1812fcf3ce44SJohn Forte 1813fcf3ce44SJohn Forte /* Fibre Channel Service Parameters */ 1814291a2b48SSukumar Swaminathan SERV_PARM sparam; 1815291a2b48SSukumar Swaminathan uint32_t fc_edtov; /* E_D_TOV timer value */ 1816291a2b48SSukumar Swaminathan uint32_t fc_arbtov; /* ARB_TOV timer value */ 1817291a2b48SSukumar Swaminathan uint32_t fc_ratov; /* R_A_TOV timer value */ 1818291a2b48SSukumar Swaminathan uint32_t fc_rttov; /* R_T_TOV timer value */ 1819291a2b48SSukumar Swaminathan uint32_t fc_altov; /* AL_TOV timer value */ 1820291a2b48SSukumar Swaminathan uint32_t fc_crtov; /* C_R_TOV timer value */ 1821291a2b48SSukumar Swaminathan uint32_t fc_citov; /* C_I_TOV timer value */ 1822291a2b48SSukumar Swaminathan 1823fcf3ce44SJohn Forte /* Adapter State management */ 1824291a2b48SSukumar Swaminathan int32_t state; 1825fcf3ce44SJohn Forte #define FC_ERROR 0x01 /* Adapter shutdown */ 1826fcf3ce44SJohn Forte #define FC_KILLED 0x02 /* Adapter interlocked/killed */ 1827fcf3ce44SJohn Forte #define FC_WARM_START 0x03 /* Adapter reset, but not restarted */ 1828fcf3ce44SJohn Forte #define FC_INIT_START 0x10 /* Adapter restarted */ 1829fcf3ce44SJohn Forte #define FC_INIT_NVPARAMS 0x11 1830fcf3ce44SJohn Forte #define FC_INIT_REV 0x12 1831fcf3ce44SJohn Forte #define FC_INIT_CFGPORT 0x13 1832fcf3ce44SJohn Forte #define FC_INIT_CFGRING 0x14 1833fcf3ce44SJohn Forte #define FC_INIT_INITLINK 0x15 1834fcf3ce44SJohn Forte #define FC_LINK_DOWN 0x20 183582527734SSukumar Swaminathan #define FC_LINK_DOWN_PERSIST 0x21 1836fcf3ce44SJohn Forte #define FC_LINK_UP 0x30 1837fcf3ce44SJohn Forte #define FC_CLEAR_LA 0x31 1838fcf3ce44SJohn Forte #define FC_READY 0x40 1839fcf3ce44SJohn Forte 1840291a2b48SSukumar Swaminathan uint32_t flag; 1841fcf3ce44SJohn Forte #define FC_ONLINING_MODE 0x00000001 1842fcf3ce44SJohn Forte #define FC_ONLINE_MODE 0x00000002 1843fcf3ce44SJohn Forte #define FC_OFFLINING_MODE 0x00000004 1844fcf3ce44SJohn Forte #define FC_OFFLINE_MODE 0x00000008 1845fcf3ce44SJohn Forte 1846291a2b48SSukumar Swaminathan #define FC_NPIV_ENABLED 0x00000010 /* NPIV enabled on adapter */ 1847291a2b48SSukumar Swaminathan #define FC_NPIV_SUPPORTED 0x00000020 /* NPIV supported on fabric */ 1848fcf3ce44SJohn Forte #define FC_NPIV_UNSUPPORTED 0x00000040 /* NPIV unsupported on fabric */ 1849fcf3ce44SJohn Forte #define FC_NPIV_LINKUP 0x00000100 /* NPIV enabled, supported, */ 1850fcf3ce44SJohn Forte /* and link is ready */ 1851fcf3ce44SJohn Forte #define FC_NPIV_DELAY_REQUIRED 0x00000200 /* Delay issuing FLOGI/FDISC */ 1852fcf3ce44SJohn Forte /* and NameServer cmds */ 1853fcf3ce44SJohn Forte 185482527734SSukumar Swaminathan #define FC_BOOTSTRAPMB_INIT 0x00000400 185582527734SSukumar Swaminathan #define FC_FIP_SUPPORTED 0x00000800 /* FIP supported */ 185682527734SSukumar Swaminathan 1857fcf3ce44SJohn Forte #define FC_FABRIC_ATTACHED 0x00001000 1858fcf3ce44SJohn Forte #define FC_PT_TO_PT 0x00002000 1859fcf3ce44SJohn Forte #define FC_BYPASSED_MODE 0x00004000 1860291a2b48SSukumar Swaminathan #define FC_MENLO_MODE 0x00008000 /* Menlo maintenance mode */ 1861291a2b48SSukumar Swaminathan 1862291a2b48SSukumar Swaminathan #define FC_DUMP_SAFE 0x00010000 /* Safe to DUMP */ 1863291a2b48SSukumar Swaminathan #define FC_DUMP_ACTIVE 0x00020000 /* DUMP in progress */ 1864a9800bebSGarrett D'Amore #define FC_NEW_FABRIC 0x00040000 1865088c6f3fSHans Rosenfeld #define FC_GPIO_LINK_UP 0x00080000 1866fcf3ce44SJohn Forte 1867fcf3ce44SJohn Forte #define FC_SLIM2_MODE 0x00100000 /* SLIM in host memory */ 1868fcf3ce44SJohn Forte #define FC_INTERLOCKED 0x00200000 1869fcf3ce44SJohn Forte #define FC_HBQ_ENABLED 0x00400000 1870fcf3ce44SJohn Forte #define FC_ASYNC_EVENTS 0x00800000 1871fcf3ce44SJohn Forte 1872fcf3ce44SJohn Forte #define FC_ILB_MODE 0x01000000 1873fcf3ce44SJohn Forte #define FC_ELB_MODE 0x02000000 1874fcf3ce44SJohn Forte #define FC_LOOPBACK_MODE 0x03000000 /* Loopback Mode Mask */ 1875291a2b48SSukumar Swaminathan #define FC_DUMP 0x04000000 /* DUMP in progress */ 1876fcf3ce44SJohn Forte #define FC_SHUTDOWN 0x08000000 /* SHUTDOWN in progress */ 1877fcf3ce44SJohn Forte 1878291a2b48SSukumar Swaminathan #define FC_OVERTEMP_EVENT 0x10000000 /* FC_ERROR reason: */ 1879291a2b48SSukumar Swaminathan /* over temperature event */ 1880291a2b48SSukumar Swaminathan #define FC_MBOX_TIMEOUT 0x20000000 /* FC_ERROR reason: */ 1881291a2b48SSukumar Swaminathan /* mailbox timeout event */ 1882b3660a96SSukumar Swaminathan #define FC_DMA_CHECK_ERROR 0x40000000 /* Shared memory (slim,..) */ 1883b3660a96SSukumar Swaminathan /* DMA handle went bad */ 1884fcf3ce44SJohn Forte #define FC_HARDWARE_ERROR 0x80000000 /* FC_ERROR state triggered */ 1885fcf3ce44SJohn Forte 188682527734SSukumar Swaminathan #define FC_RESET_MASK 0x00030C1F /* Bits to protect during */ 1887291a2b48SSukumar Swaminathan /* a hard reset */ 188882527734SSukumar Swaminathan #define FC_LINKDOWN_MASK 0xFFF30C1F /* Bits to protect during */ 1889291a2b48SSukumar Swaminathan /* a linkdown */ 1890fcf3ce44SJohn Forte 18916a573d82SSukumar Swaminathan uint32_t fw_timer; 18926a573d82SSukumar Swaminathan uint32_t fw_flag; 18936a573d82SSukumar Swaminathan #define FW_UPDATE_NEEDED 0x00000001 18946a573d82SSukumar Swaminathan #define FW_UPDATE_KERNEL 0x00000002 18956a573d82SSukumar Swaminathan 189682527734SSukumar Swaminathan uint32_t temperature; /* Last reported temperature */ 1897fcf3ce44SJohn Forte 1898fcf3ce44SJohn Forte /* SBUS adapter management */ 1899291a2b48SSukumar Swaminathan caddr_t sbus_pci_addr; /* Virt addr of TITAN */ 1900291a2b48SSukumar Swaminathan /* pci config */ 1901fcf3ce44SJohn Forte ddi_acc_handle_t sbus_pci_handle; 1902fcf3ce44SJohn Forte 190382527734SSukumar Swaminathan /* PCI BUS adapter management */ 190482527734SSukumar Swaminathan caddr_t pci_addr; 190582527734SSukumar Swaminathan ddi_acc_handle_t pci_acc_handle; 190682527734SSukumar Swaminathan 190782527734SSukumar Swaminathan uint32_t sli_mode; 190882527734SSukumar Swaminathan #define EMLXS_HBA_SLI1_MODE 1 190982527734SSukumar Swaminathan #define EMLXS_HBA_SLI2_MODE 2 191082527734SSukumar Swaminathan #define EMLXS_HBA_SLI3_MODE 3 191182527734SSukumar Swaminathan #define EMLXS_HBA_SLI4_MODE 4 191282527734SSukumar Swaminathan 191382527734SSukumar Swaminathan /* SLI private data */ 191482527734SSukumar Swaminathan union { 191582527734SSukumar Swaminathan emlxs_sli3_t sli3; 191682527734SSukumar Swaminathan emlxs_sli4_t sli4; 191782527734SSukumar Swaminathan } sli; 191882527734SSukumar Swaminathan 191982527734SSukumar Swaminathan /* SLI API entry point routines */ 192082527734SSukumar Swaminathan emlxs_sli_api_t sli_api; 1921291a2b48SSukumar Swaminathan 1922291a2b48SSukumar Swaminathan uint32_t io_poll_count; /* Number of poll commands */ 1923291a2b48SSukumar Swaminathan /* in progress */ 1924fcf3ce44SJohn Forte 1925fcf3ce44SJohn Forte /* IO Completion management */ 1926291a2b48SSukumar Swaminathan uint32_t iodone_count; /* Number of IO's on done Q */ 1927fcf3ce44SJohn Forte /* Protected by EMLXS_PORT_LOCK */ 1928291a2b48SSukumar Swaminathan emlxs_buf_t *iodone_list; /* fc_packet being deferred */ 1929291a2b48SSukumar Swaminathan emlxs_buf_t *iodone_tail; /* fc_packet being deferred */ 1930291a2b48SSukumar Swaminathan emlxs_thread_t iodone_thread; 1931bb63f56eSSukumar Swaminathan emlxs_thread_t *spawn_thread_head; 1932bb63f56eSSukumar Swaminathan emlxs_thread_t *spawn_thread_tail; 1933bb63f56eSSukumar Swaminathan kmutex_t spawn_lock; 1934bb63f56eSSukumar Swaminathan uint32_t spawn_open; 1935fcf3ce44SJohn Forte 193682527734SSukumar Swaminathan /* IO Channel management */ 193782527734SSukumar Swaminathan int32_t chan_count; 193882527734SSukumar Swaminathan emlxs_channel_t chan[MAX_CHANNEL]; 193982527734SSukumar Swaminathan kmutex_t channel_tx_lock; 194082527734SSukumar Swaminathan uint8_t channel_fcp; /* Default channel to use for FCP IO */ 194182527734SSukumar Swaminathan #define CHANNEL_FCT channel_fcp 194282527734SSukumar Swaminathan uint8_t channel_ip; /* Default channel to use for IP IO */ 194382527734SSukumar Swaminathan uint8_t channel_els; /* Default channel to use for ELS IO */ 194482527734SSukumar Swaminathan uint8_t channel_ct; /* Default channel to use for CT IO */ 194582527734SSukumar Swaminathan 194682527734SSukumar Swaminathan /* IOTag management */ 194782527734SSukumar Swaminathan emlxs_buf_t **fc_table; /* sc_buf pointers indexed by */ 194882527734SSukumar Swaminathan /* iotag */ 194982527734SSukumar Swaminathan uint16_t fc_iotag; /* used to identify I/Os */ 195082527734SSukumar Swaminathan uint16_t fc_oor_iotag; /* OutOfRange (fc_table) iotags */ 195182527734SSukumar Swaminathan /* typically used for Abort/close */ 195282527734SSukumar Swaminathan #define EMLXS_MAX_ABORT_TAG 0x7fff 195382527734SSukumar Swaminathan uint16_t max_iotag; /* ALL IOCBs except aborts */ 195482527734SSukumar Swaminathan kmutex_t iotag_lock; 195582527734SSukumar Swaminathan uint32_t io_count; /* No of IO holding */ 195682527734SSukumar Swaminathan /* regular iotag */ 195782527734SSukumar Swaminathan uint32_t channel_tx_count; /* No of IO on tx Q */ 1958fcf3ce44SJohn Forte 1959fcf3ce44SJohn Forte /* Mailbox Management */ 1960291a2b48SSukumar Swaminathan uint32_t mbox_queue_flag; 1961291a2b48SSukumar Swaminathan emlxs_queue_t mbox_queue; 1962a9800bebSGarrett D'Amore void *mbox_mqe; /* active mbox mqe */ 1963a9800bebSGarrett D'Amore void *mbox_mbq; /* active MAILBOXQ */ 1964291a2b48SSukumar Swaminathan kcondvar_t mbox_lock_cv; /* MBX_SLEEP */ 1965291a2b48SSukumar Swaminathan kmutex_t mbox_lock; /* MBX_SLEEP */ 1966291a2b48SSukumar Swaminathan uint32_t mbox_timer; 1967fcf3ce44SJohn Forte 1968fcf3ce44SJohn Forte /* Interrupt management */ 1969291a2b48SSukumar Swaminathan void *intr_arg; 1970291a2b48SSukumar Swaminathan uint32_t intr_unclaimed; 1971291a2b48SSukumar Swaminathan uint32_t intr_autoClear; 19728f23e9faSHans Rosenfeld uint32_t intr_busy_cnt; 19738f23e9faSHans Rosenfeld 1974291a2b48SSukumar Swaminathan uint32_t intr_flags; 1975fcf3ce44SJohn Forte #define EMLXS_INTX_INITED 0x0001 1976fcf3ce44SJohn Forte #define EMLXS_INTX_ADDED 0x0002 1977fcf3ce44SJohn Forte #define EMLXS_MSI_ENABLED 0x0010 1978fcf3ce44SJohn Forte #define EMLXS_MSI_INITED 0x0020 1979fcf3ce44SJohn Forte #define EMLXS_MSI_ADDED 0x0040 1980291a2b48SSukumar Swaminathan #define EMLXS_INTR_INITED (EMLXS_INTX_INITED|EMLXS_MSI_INITED) 1981291a2b48SSukumar Swaminathan #define EMLXS_INTR_ADDED (EMLXS_INTX_ADDED|EMLXS_MSI_ADDED) 1982fcf3ce44SJohn Forte 1983fcf3ce44SJohn Forte #ifdef MSI_SUPPORT 1984fcf3ce44SJohn Forte ddi_intr_handle_t *intr_htable; 1985291a2b48SSukumar Swaminathan uint32_t *intr_pri; 1986291a2b48SSukumar Swaminathan int32_t *intr_cap; 1987291a2b48SSukumar Swaminathan uint32_t intr_count; 1988291a2b48SSukumar Swaminathan uint32_t intr_type; 1989291a2b48SSukumar Swaminathan uint32_t intr_cond; 1990291a2b48SSukumar Swaminathan uint32_t intr_map[EMLXS_MSI_MAX_INTRS]; 1991291a2b48SSukumar Swaminathan uint32_t intr_mask; 1992fcf3ce44SJohn Forte 1993a9800bebSGarrett D'Amore kmutex_t msiid_lock; /* for last_msiid */ 1994a9800bebSGarrett D'Amore int last_msiid; 1995fcf3ce44SJohn Forte 1996291a2b48SSukumar Swaminathan kmutex_t intr_lock[EMLXS_MSI_MAX_INTRS]; 1997a9800bebSGarrett D'Amore int chan2msi[MAX_CHANNEL]; 1998a9800bebSGarrett D'Amore /* Index is the channel id */ 1999a9800bebSGarrett D'Amore int msi2chan[EMLXS_MSI_MAX_INTRS]; 2000a9800bebSGarrett D'Amore /* Index is the MSX-X msg id */ 2001fcf3ce44SJohn Forte #endif /* MSI_SUPPORT */ 2002fcf3ce44SJohn Forte 2003291a2b48SSukumar Swaminathan uint32_t heartbeat_timer; 2004291a2b48SSukumar Swaminathan uint32_t heartbeat_flag; 2005291a2b48SSukumar Swaminathan uint32_t heartbeat_active; 2006fcf3ce44SJohn Forte 2007fcf3ce44SJohn Forte /* IOCTL management */ 2008291a2b48SSukumar Swaminathan kmutex_t ioctl_lock; 2009291a2b48SSukumar Swaminathan uint32_t ioctl_flags; 2010fcf3ce44SJohn Forte #define EMLXS_OPEN 0x00000001 2011fcf3ce44SJohn Forte #define EMLXS_OPEN_EXCLUSIVE 0x00000002 2012fcf3ce44SJohn Forte 2013fcf3ce44SJohn Forte /* Timer management */ 2014291a2b48SSukumar Swaminathan kcondvar_t timer_lock_cv; 2015291a2b48SSukumar Swaminathan kmutex_t timer_lock; 2016291a2b48SSukumar Swaminathan timeout_id_t timer_id; 2017291a2b48SSukumar Swaminathan uint32_t timer_tics; 2018291a2b48SSukumar Swaminathan uint32_t timer_flags; 2019fcf3ce44SJohn Forte #define EMLXS_TIMER_STARTED 0x0000001 2020fcf3ce44SJohn Forte #define EMLXS_TIMER_BUSY 0x0000002 2021fcf3ce44SJohn Forte #define EMLXS_TIMER_KILL 0x0000004 2022fcf3ce44SJohn Forte #define EMLXS_TIMER_ENDED 0x0000008 2023fcf3ce44SJohn Forte 2024fcf3ce44SJohn Forte /* Misc Timers */ 2025291a2b48SSukumar Swaminathan uint32_t linkup_timer; 2026291a2b48SSukumar Swaminathan uint32_t discovery_timer; 2027291a2b48SSukumar Swaminathan uint32_t pkt_timer; 2028fcf3ce44SJohn Forte 2029088c6f3fSHans Rosenfeld /* GPIO Management */ 2030088c6f3fSHans Rosenfeld uint8_t gpio_desired; 2031088c6f3fSHans Rosenfeld uint8_t gpio_current; 2032088c6f3fSHans Rosenfeld uint8_t gpio_bit; 2033088c6f3fSHans Rosenfeld #define EMLXS_GPIO_LO 0x01 2034088c6f3fSHans Rosenfeld #define EMLXS_GPIO_HI 0x02 2035088c6f3fSHans Rosenfeld #define EMLXS_GPIO_ACT 0x04 2036088c6f3fSHans Rosenfeld #define EMLXS_GPIO_LASER 0x08 2037088c6f3fSHans Rosenfeld #define EMLXS_GPIO_LOC 0x10 2038088c6f3fSHans Rosenfeld 2039088c6f3fSHans Rosenfeld uint8_t gpio_pin[4]; 2040088c6f3fSHans Rosenfeld 2041088c6f3fSHans Rosenfeld #define EMLXS_GPIO_PIN_LO 0 2042088c6f3fSHans Rosenfeld #define EMLXS_GPIO_PIN_HI 1 2043088c6f3fSHans Rosenfeld #define EMLXS_GPIO_PIN_ACT 2 2044088c6f3fSHans Rosenfeld #define EMLXS_GPIO_PIN_LASER 3 2045088c6f3fSHans Rosenfeld 2046088c6f3fSHans Rosenfeld kmutex_t gpio_lock; /* Timer lock */ 2047088c6f3fSHans Rosenfeld timeout_id_t gpio_timer; 2048088c6f3fSHans Rosenfeld 2049fcf3ce44SJohn Forte /* Power Management */ 2050291a2b48SSukumar Swaminathan uint32_t pm_state; 2051fcf3ce44SJohn Forte /* pm_state */ 2052fcf3ce44SJohn Forte #define EMLXS_PM_IN_ATTACH 0x00000001 2053fcf3ce44SJohn Forte #define EMLXS_PM_IN_DETACH 0x00000002 2054fcf3ce44SJohn Forte #define EMLXS_PM_IN_SOL_CB 0x00000010 2055fcf3ce44SJohn Forte #define EMLXS_PM_IN_UNSOL_CB 0x00000020 2056fcf3ce44SJohn Forte #define EMLXS_PM_IN_LINK_RESET 0x00000100 2057fcf3ce44SJohn Forte #define EMLXS_PM_IN_HARD_RESET 0x00000200 2058fcf3ce44SJohn Forte #define EMLXS_PM_SUSPENDED 0x01000000 2059fcf3ce44SJohn Forte 2060291a2b48SSukumar Swaminathan uint32_t pm_level; 2061fcf3ce44SJohn Forte /* pm_level */ 2062fcf3ce44SJohn Forte #define EMLXS_PM_ADAPTER_DOWN 0 2063fcf3ce44SJohn Forte #define EMLXS_PM_ADAPTER_UP 1 2064fcf3ce44SJohn Forte 2065291a2b48SSukumar Swaminathan uint32_t pm_busy; 2066291a2b48SSukumar Swaminathan kmutex_t pm_lock; 2067291a2b48SSukumar Swaminathan uint8_t pm_config[PCI_CONFIG_SIZE]; 2068fcf3ce44SJohn Forte #ifdef IDLE_TIMER 2069291a2b48SSukumar Swaminathan uint32_t pm_idle_timer; 2070291a2b48SSukumar Swaminathan uint32_t pm_active; /* Only used by timer */ 2071fcf3ce44SJohn Forte #endif /* IDLE_TIMER */ 2072fcf3ce44SJohn Forte 2073fcf3ce44SJohn Forte /* Loopback management */ 2074291a2b48SSukumar Swaminathan uint32_t loopback_tics; 2075291a2b48SSukumar Swaminathan void *loopback_pkt; 2076fcf3ce44SJohn Forte 2077fcf3ce44SJohn Forte /* Event management */ 207882527734SSukumar Swaminathan emlxs_event_queue_t event_queue; 207982527734SSukumar Swaminathan uint32_t event_mask; 208082527734SSukumar Swaminathan uint32_t event_timer; 2081fcf3ce44SJohn Forte emlxs_dfc_event_t dfc_event[MAX_DFC_EVENTS]; 2082fcf3ce44SJohn Forte emlxs_hba_event_t hba_event; 2083fcf3ce44SJohn Forte 2084fcf3ce44SJohn Forte /* Parameter management */ 2085291a2b48SSukumar Swaminathan emlxs_config_t config[NUM_CFG_PARAM]; 2086fcf3ce44SJohn Forte 2087fcf3ce44SJohn Forte /* Driver stat management */ 2088291a2b48SSukumar Swaminathan kstat_t *kstat; 2089291a2b48SSukumar Swaminathan emlxs_stats_t stats; 2090fcf3ce44SJohn Forte 2091fcf3ce44SJohn Forte /* Log management */ 2092291a2b48SSukumar Swaminathan emlxs_msg_log_t log; 2093fcf3ce44SJohn Forte 2094fcf3ce44SJohn Forte /* Port managment */ 2095291a2b48SSukumar Swaminathan uint32_t vpi_max; 2096291a2b48SSukumar Swaminathan uint32_t vpi_high; 2097291a2b48SSukumar Swaminathan uint32_t num_of_ports; 2098fcf3ce44SJohn Forte 2099291a2b48SSukumar Swaminathan kmutex_t port_lock; /* locks port, nodes, rings */ 2100291a2b48SSukumar Swaminathan emlxs_port_t port[MAX_VPORTS + 1]; /* port specific info */ 2101291a2b48SSukumar Swaminathan /* Last one is for */ 2102291a2b48SSukumar Swaminathan /* NPIV ready test */ 2103fcf3ce44SJohn Forte 2104fcf3ce44SJohn Forte #ifdef DHCHAP_SUPPORT 2105291a2b48SSukumar Swaminathan kmutex_t dhc_lock; 2106291a2b48SSukumar Swaminathan kmutex_t auth_lock; 2107291a2b48SSukumar Swaminathan emlxs_auth_cfg_t auth_cfg; /* Default auth_cfg. */ 2108291a2b48SSukumar Swaminathan /* Points to list of entries. */ 2109291a2b48SSukumar Swaminathan /* Protected by auth_lock */ 2110291a2b48SSukumar Swaminathan uint32_t auth_cfg_count; 2111291a2b48SSukumar Swaminathan emlxs_auth_key_t auth_key; /* Default auth_key. */ 2112291a2b48SSukumar Swaminathan /* Points to list of entries. */ 2113291a2b48SSukumar Swaminathan /* Protected by auth_lock */ 2114291a2b48SSukumar Swaminathan uint32_t auth_key_count; 2115291a2b48SSukumar Swaminathan uint32_t rdn_flag; 2116fcf3ce44SJohn Forte #endif /* DHCHAP_SUPPORT */ 2117fcf3ce44SJohn Forte 2118fcf3ce44SJohn Forte #ifdef TEST_SUPPORT 2119291a2b48SSukumar Swaminathan uint32_t underrun_counter; 2120291a2b48SSukumar Swaminathan #endif /* TEST_SUPPORT */ 2121291a2b48SSukumar Swaminathan 2122291a2b48SSukumar Swaminathan #ifdef MODFW_SUPPORT 2123291a2b48SSukumar Swaminathan ddi_modhandle_t fw_modhandle; 2124291a2b48SSukumar Swaminathan #endif /* MODFW_SUPPORT */ 2125291a2b48SSukumar Swaminathan 2126291a2b48SSukumar Swaminathan #ifdef DUMP_SUPPORT 2127291a2b48SSukumar Swaminathan emlxs_file_t dump_txtfile; 2128291a2b48SSukumar Swaminathan emlxs_file_t dump_dmpfile; 2129291a2b48SSukumar Swaminathan emlxs_file_t dump_ceefile; 2130291a2b48SSukumar Swaminathan kmutex_t dump_lock; 2131291a2b48SSukumar Swaminathan #define EMLXS_DUMP_LOCK hba->dump_lock 2132291a2b48SSukumar Swaminathan #define EMLXS_TXT_FILE 1 2133291a2b48SSukumar Swaminathan #define EMLXS_DMP_FILE 2 2134291a2b48SSukumar Swaminathan #define EMLXS_CEE_FILE 3 2135291a2b48SSukumar Swaminathan 2136291a2b48SSukumar Swaminathan #define EMLXS_DRV_DUMP 0 2137291a2b48SSukumar Swaminathan #define EMLXS_TEMP_DUMP 1 2138291a2b48SSukumar Swaminathan #define EMLXS_USER_DUMP 2 2139291a2b48SSukumar Swaminathan 2140291a2b48SSukumar Swaminathan #endif /* DUMP_SUPPORT */ 2141291a2b48SSukumar Swaminathan 21428f23e9faSHans Rosenfeld uint32_t reset_request; 21438f23e9faSHans Rosenfeld #define FC_LINK_RESET 1 21448f23e9faSHans Rosenfeld #define FC_PORT_RESET 2 21458f23e9faSHans Rosenfeld 21468f23e9faSHans Rosenfeld uint32_t reset_state; 21478f23e9faSHans Rosenfeld #define FC_LINK_RESET_INP 1 21488f23e9faSHans Rosenfeld #define FC_PORT_RESET_INP 2 21498f23e9faSHans Rosenfeld 2150fcf3ce44SJohn Forte } emlxs_hba_t; 2151fcf3ce44SJohn Forte 215282527734SSukumar Swaminathan #define EMLXS_SLI_MAP_HDW (hba->sli_api.sli_map_hdw) 215382527734SSukumar Swaminathan #define EMLXS_SLI_UNMAP_HDW (hba->sli_api.sli_unmap_hdw) 215482527734SSukumar Swaminathan #define EMLXS_SLI_ONLINE (hba->sli_api.sli_online) 215582527734SSukumar Swaminathan #define EMLXS_SLI_OFFLINE (hba->sli_api.sli_offline) 215682527734SSukumar Swaminathan #define EMLXS_SLI_HBA_RESET (hba->sli_api.sli_hba_reset) 215782527734SSukumar Swaminathan #define EMLXS_SLI_HBA_KILL (hba->sli_api.sli_hba_kill) 215882527734SSukumar Swaminathan #define EMLXS_SLI_ISSUE_IOCB_CMD (hba->sli_api.sli_issue_iocb_cmd) 215982527734SSukumar Swaminathan #define EMLXS_SLI_ISSUE_MBOX_CMD (hba->sli_api.sli_issue_mbox_cmd) 216082527734SSukumar Swaminathan #define EMLXS_SLI_PREP_FCT_IOCB (hba->sli_api.sli_prep_fct_iocb) 216182527734SSukumar Swaminathan #define EMLXS_SLI_PREP_FCP_IOCB (hba->sli_api.sli_prep_fcp_iocb) 216282527734SSukumar Swaminathan #define EMLXS_SLI_PREP_IP_IOCB (hba->sli_api.sli_prep_ip_iocb) 216382527734SSukumar Swaminathan #define EMLXS_SLI_PREP_ELS_IOCB (hba->sli_api.sli_prep_els_iocb) 216482527734SSukumar Swaminathan #define EMLXS_SLI_PREP_CT_IOCB (hba->sli_api.sli_prep_ct_iocb) 216582527734SSukumar Swaminathan #define EMLXS_SLI_POLL_INTR (hba->sli_api.sli_poll_intr) 216682527734SSukumar Swaminathan #define EMLXS_SLI_INTX_INTR (hba->sli_api.sli_intx_intr) 216782527734SSukumar Swaminathan #define EMLXS_SLI_MSI_INTR (hba->sli_api.sli_msi_intr) 216882527734SSukumar Swaminathan #define EMLXS_SLI_DISABLE_INTR (hba->sli_api.sli_disable_intr) 216982527734SSukumar Swaminathan #define EMLXS_SLI_TIMER (hba->sli_api.sli_timer) 217082527734SSukumar Swaminathan #define EMLXS_SLI_POLL_ERRATT (hba->sli_api.sli_poll_erratt) 21718f23e9faSHans Rosenfeld #define EMLXS_SLI_REG_DID (hba->sli_api.sli_reg_did) 21728f23e9faSHans Rosenfeld #define EMLXS_SLI_UNREG_NODE (hba->sli_api.sli_unreg_node) 2173291a2b48SSukumar Swaminathan 2174291a2b48SSukumar Swaminathan #define EMLXS_HBA_T 1 /* flag emlxs_hba_t is already typedefed */ 2175fcf3ce44SJohn Forte 2176fcf3ce44SJohn Forte #ifdef MSI_SUPPORT 2177291a2b48SSukumar Swaminathan #define EMLXS_INTR_INIT(_hba, _m) emlxs_msi_init(_hba, _m) 2178291a2b48SSukumar Swaminathan #define EMLXS_INTR_UNINIT(_hba) emlxs_msi_uninit(_hba) 2179291a2b48SSukumar Swaminathan #define EMLXS_INTR_ADD(_hba) emlxs_msi_add(_hba) 2180291a2b48SSukumar Swaminathan #define EMLXS_INTR_REMOVE(_hba) emlxs_msi_remove(_hba) 2181fcf3ce44SJohn Forte #else 2182291a2b48SSukumar Swaminathan #define EMLXS_INTR_INIT(_hba, _m) emlxs_intx_init(_hba, _m) 2183291a2b48SSukumar Swaminathan #define EMLXS_INTR_UNINIT(_hba) emlxs_intx_uninit(_hba) 2184291a2b48SSukumar Swaminathan #define EMLXS_INTR_ADD(_hba) emlxs_intx_add(_hba) 2185291a2b48SSukumar Swaminathan #define EMLXS_INTR_REMOVE(_hba) emlxs_intx_remove(_hba) 2186fcf3ce44SJohn Forte #endif /* MSI_SUPPORT */ 2187fcf3ce44SJohn Forte 2188fcf3ce44SJohn Forte 2189fcf3ce44SJohn Forte /* Power Management Component */ 2190291a2b48SSukumar Swaminathan #define EMLXS_PM_ADAPTER 0 2191291a2b48SSukumar Swaminathan 2192291a2b48SSukumar Swaminathan 2193291a2b48SSukumar Swaminathan #define DRV_TIME (uint32_t)(ddi_get_time() - emlxs_device.drv_timestamp) 2194291a2b48SSukumar Swaminathan 2195291a2b48SSukumar Swaminathan #define HBA port->hba 2196291a2b48SSukumar Swaminathan #define PPORT hba->port[0] 2197291a2b48SSukumar Swaminathan #define VPORT(x) hba->port[x] 2198291a2b48SSukumar Swaminathan #define EMLXS_TIMER_LOCK hba->timer_lock 2199291a2b48SSukumar Swaminathan #define VPD hba->vpd 2200291a2b48SSukumar Swaminathan #define CFG hba->config[0] 2201291a2b48SSukumar Swaminathan #define LOG hba->log 220282527734SSukumar Swaminathan #define EVENTQ hba->event_queue 2203291a2b48SSukumar Swaminathan #define EMLXS_MBOX_LOCK hba->mbox_lock 2204291a2b48SSukumar Swaminathan #define EMLXS_MBOX_CV hba->mbox_lock_cv 2205291a2b48SSukumar Swaminathan #define EMLXS_LINKUP_LOCK hba->linkup_lock 2206291a2b48SSukumar Swaminathan #define EMLXS_LINKUP_CV hba->linkup_lock_cv 220782527734SSukumar Swaminathan #define EMLXS_TX_CHANNEL_LOCK hba->channel_tx_lock /* ring txq lock */ 2208291a2b48SSukumar Swaminathan #define EMLXS_MEMGET_LOCK hba->memget_lock /* mempool get lock */ 2209291a2b48SSukumar Swaminathan #define EMLXS_MEMPUT_LOCK hba->memput_lock /* mempool put lock */ 2210291a2b48SSukumar Swaminathan #define EMLXS_IOCTL_LOCK hba->ioctl_lock /* ioctl lock */ 2211d08970deSSukumar Swaminathan #define EMLXS_SPAWN_LOCK hba->spawn_lock /* spawn lock */ 2212d08970deSSukumar Swaminathan #define EMLXS_PM_LOCK hba->pm_lock /* pm lock */ 2213291a2b48SSukumar Swaminathan #define HBASTATS hba->stats 221482527734SSukumar Swaminathan #define EMLXS_CMD_RING_LOCK(n) hba->sli.sli3.ring_cmd_lock[n] 2215a9800bebSGarrett D'Amore 2216a9800bebSGarrett D'Amore #define EMLXS_QUE_LOCK(n) hba->sli.sli4.que_lock[n] 2217a9800bebSGarrett D'Amore #define EMLXS_MSIID_LOCK hba->msiid_lock 2218a9800bebSGarrett D'Amore 221982527734SSukumar Swaminathan #define EMLXS_FCTAB_LOCK hba->iotag_lock 2220a9800bebSGarrett D'Amore 2221a9800bebSGarrett D'Amore #define EMLXS_FCF_LOCK hba->sli.sli4.fcf_lock 2222a9800bebSGarrett D'Amore 2223291a2b48SSukumar Swaminathan #define EMLXS_PORT_LOCK hba->port_lock /* locks ports, */ 2224fcf3ce44SJohn Forte /* nodes, rings */ 2225291a2b48SSukumar Swaminathan #define EMLXS_INTR_LOCK(_id) hba->intr_lock[_id] /* locks intr threads */ 2226fcf3ce44SJohn Forte 2227291a2b48SSukumar Swaminathan #define EMLXS_PKT_LOCK port->pkt_lock /* used for pkt */ 2228291a2b48SSukumar Swaminathan /* polling */ 2229291a2b48SSukumar Swaminathan #define EMLXS_PKT_CV port->pkt_lock_cv /* Used for pkt */ 2230291a2b48SSukumar Swaminathan /* polling */ 2231291a2b48SSukumar Swaminathan #define EMLXS_UB_LOCK port->ub_lock /* locks unsolicited */ 2232fcf3ce44SJohn Forte /* buffer pool */ 2233fcf3ce44SJohn Forte 223482527734SSukumar Swaminathan /* These SWAPs will swap on any platform */ 223582527734SSukumar Swaminathan #define SWAP32_BUFFER(_b, _c) emlxs_swap32_buffer(_b, _c) 223682527734SSukumar Swaminathan #define SWAP32_BCOPY(_s, _d, _c) emlxs_swap32_bcopy(_s, _d, _c) 2237fcf3ce44SJohn Forte 223882527734SSukumar Swaminathan #define SWAP64(_x) ((((uint64_t)(_x) & 0xFF)<<56) | \ 223982527734SSukumar Swaminathan (((uint64_t)(_x) & 0xFF00)<<40) | \ 224082527734SSukumar Swaminathan (((uint64_t)(_x) & 0xFF0000)<<24) | \ 224182527734SSukumar Swaminathan (((uint64_t)(_x) & 0xFF000000)<<8) | \ 224282527734SSukumar Swaminathan (((uint64_t)(_x) & 0xFF00000000)>>8) | \ 224382527734SSukumar Swaminathan (((uint64_t)(_x) & 0xFF0000000000)>>24) | \ 224482527734SSukumar Swaminathan (((uint64_t)(_x) & 0xFF000000000000)>>40) | \ 224582527734SSukumar Swaminathan (((uint64_t)(_x) & 0xFF00000000000000)>>56)) 2246fcf3ce44SJohn Forte 224782527734SSukumar Swaminathan #define SWAP32(_x) ((((uint32_t)(_x) & 0xFF)<<24) | \ 224882527734SSukumar Swaminathan (((uint32_t)(_x) & 0xFF00)<<8) | \ 224982527734SSukumar Swaminathan (((uint32_t)(_x) & 0xFF0000)>>8) | \ 225082527734SSukumar Swaminathan (((uint32_t)(_x) & 0xFF000000)>>24)) 2251fcf3ce44SJohn Forte 225282527734SSukumar Swaminathan #define SWAP16(_x) ((((uint16_t)(_x) & 0xFF)<<8) | \ 225382527734SSukumar Swaminathan (((uint16_t)(_x) & 0xFF00)>>8)) 2254fcf3ce44SJohn Forte 225582527734SSukumar Swaminathan #define SWAP24_LO(_x) ((((uint32_t)(_x) & 0xFF)<<16) | \ 225682527734SSukumar Swaminathan ((uint32_t)(_x) & 0xFF00FF00) | \ 225782527734SSukumar Swaminathan (((uint32_t)(_x) & 0x00FF0000)>>16)) 2258fcf3ce44SJohn Forte 225982527734SSukumar Swaminathan #define SWAP24_HI(_x) (((uint32_t)(_x) & 0x00FF00FF) | \ 226082527734SSukumar Swaminathan (((uint32_t)(_x) & 0x0000FF00)<<16) | \ 226182527734SSukumar Swaminathan (((uint32_t)(_x) & 0xFF000000)>>16)) 2262fcf3ce44SJohn Forte 226382527734SSukumar Swaminathan /* These LE_SWAPs will only swap on a LE platform */ 226482527734SSukumar Swaminathan #ifdef EMLXS_LITTLE_ENDIAN 226582527734SSukumar Swaminathan #define LE_SWAP32_BUFFER(_b, _c) SWAP32_BUFFER(_b, _c) 226682527734SSukumar Swaminathan #define LE_SWAP32_BCOPY(_s, _d, _c) SWAP32_BCOPY(_s, _d, _c) 226782527734SSukumar Swaminathan #define LE_SWAP64(_x) SWAP64(_x) 226882527734SSukumar Swaminathan #define LE_SWAP32(_x) SWAP32(_x) 226982527734SSukumar Swaminathan #define LE_SWAP16(_x) SWAP16(_x) 227082527734SSukumar Swaminathan #define LE_SWAP24_LO(_x) SWAP24_LO(X) 227182527734SSukumar Swaminathan #define LE_SWAP24_HI(_x) SWAP24_HI(X) 2272fcf3ce44SJohn Forte 227382527734SSukumar Swaminathan #if (EMLXS_MODREVX == EMLXS_MODREV2X) 227482527734SSukumar Swaminathan #undef LE_SWAP24_LO 227582527734SSukumar Swaminathan #define LE_SWAP24_LO(_x) (_x) 227682527734SSukumar Swaminathan #undef LE_SWAP24_HI 227782527734SSukumar Swaminathan #define LE_SWAP24_HI(_x) (_x) 227882527734SSukumar Swaminathan #endif /* EMLXS_MODREV2X */ 2279291a2b48SSukumar Swaminathan 228082527734SSukumar Swaminathan #else /* BIG ENDIAN */ 228182527734SSukumar Swaminathan #define LE_SWAP32_BUFFER(_b, _c) 228282527734SSukumar Swaminathan #define LE_SWAP32_BCOPY(_s, _d, _c) bcopy(_s, _d, _c) 228382527734SSukumar Swaminathan #define LE_SWAP64(_x) (_x) 228482527734SSukumar Swaminathan #define LE_SWAP32(_x) (_x) 228582527734SSukumar Swaminathan #define LE_SWAP16(_x) (_x) 228682527734SSukumar Swaminathan #define LE_SWAP24_LO(_x) (_x) 228782527734SSukumar Swaminathan #define LE_SWAP24_HI(_x) (_x) 228882527734SSukumar Swaminathan #endif /* EMLXS_LITTLE_ENDIAN */ 228982527734SSukumar Swaminathan 229082527734SSukumar Swaminathan /* These BE_SWAPs will only swap on a BE platform */ 229182527734SSukumar Swaminathan #ifdef EMLXS_BIG_ENDIAN 229282527734SSukumar Swaminathan #define BE_SWAP32_BUFFER(_b, _c) SWAP32_BUFFER(_b, _c) 229382527734SSukumar Swaminathan #define BE_SWAP32_BCOPY(_s, _d, _c) SWAP32_BCOPY(_s, _d, _c) 229482527734SSukumar Swaminathan #define BE_SWAP64(_x) SWAP64(_x) 229582527734SSukumar Swaminathan #define BE_SWAP32(_x) SWAP32(_x) 229682527734SSukumar Swaminathan #define BE_SWAP16(_x) SWAP16(_x) 229782527734SSukumar Swaminathan #else /* LITTLE ENDIAN */ 229882527734SSukumar Swaminathan #define BE_SWAP32_BUFFER(_b, _c) 229982527734SSukumar Swaminathan #define BE_SWAP32_BCOPY(_s, _d, _c) bcopy(_s, _d, _c) 230082527734SSukumar Swaminathan #define BE_SWAP64(_x) (_x) 230182527734SSukumar Swaminathan #define BE_SWAP32(_x) (_x) 230282527734SSukumar Swaminathan #define BE_SWAP16(_x) (_x) 230382527734SSukumar Swaminathan #endif /* EMLXS_BIG_ENDIAN */ 2304fcf3ce44SJohn Forte 23058f23e9faSHans Rosenfeld #define EMLXS_DFC_RESET_ALL 0x10 23068f23e9faSHans Rosenfeld #define EMLXS_DFC_RESET_ALL_FORCE_DUMP 0x11 23078f23e9faSHans Rosenfeld 2308fcf3ce44SJohn Forte #ifdef __cplusplus 2309fcf3ce44SJohn Forte } 2310fcf3ce44SJohn Forte #endif 2311fcf3ce44SJohn Forte 2312fcf3ce44SJohn Forte #endif /* _EMLXS_FC_H */ 2313